/*
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  License, v. 2.0. If a copy of the MPL was not distributed with this
  file, You can obtain one at http://mozilla.org/MPL/2.0/.

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file, then You may include the notice in a location (such as a LICENSE
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# ! [doc = "Peripheral access API for CH32V103XX microcontrollers (generated using svd2rust v0.31.5 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.31.5/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
# ! [allow (non_camel_case_types)]
# ! [allow (non_snake_case)]
# ! [no_std]
use core :: ops :: Deref ; use core :: marker :: PhantomData ; # [allow (unused_imports)]
use generic :: * ; # [doc = r"Common register and bit access and modify traits"]
pub mod generic { use core :: marker ; # [doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
pub trait RawReg : Copy + Default + From < bool > + core :: ops :: BitOr < Output = Self > + core :: ops :: BitAnd < Output = Self > + core :: ops :: BitOrAssign + core :: ops :: BitAndAssign + core :: ops :: Not < Output = Self > + core :: ops :: Shl < u8 , Output = Self > { # [doc = " Mask for bits of width `WI`"]
fn mask < const WI : u8 > () -> Self ; # [doc = " Mask for bits of width 1"]
fn one () -> Self ; } macro_rules ! raw_reg { ($ U : ty , $ size : literal , $ mask : ident) => { impl RawReg for $ U { # [inline (always)]
fn mask < const WI : u8 > () -> Self { $ mask ::< WI > () } # [inline (always)]
fn one () -> Self { 1 } } const fn $ mask < const WI : u8 > () -> $ U { <$ U >:: MAX >> ($ size - WI) } impl FieldSpec for $ U { type Ux = $ U ; } } ; } raw_reg ! (u8 , 8 , mask_u8) ; raw_reg ! (u16 , 16 , mask_u16) ; raw_reg ! (u32 , 32 , mask_u32) ; raw_reg ! (u64 , 64 , mask_u64) ; # [doc = " Raw register type"]
pub trait RegisterSpec { # [doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
type Ux : RawReg ; } # [doc = " Raw field type"]
pub trait FieldSpec : Sized { # [doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
type Ux : Copy + PartialEq + From < Self > ; } # [doc = " Trait implemented by readable registers to enable the `read` method."]
# [doc = ""]
# [doc = " Registers marked with `Writable` can be also be `modify`'ed."]
pub trait Readable : RegisterSpec { } # [doc = " Trait implemented by writeable registers."]
# [doc = ""]
# [doc = " This enables the  `write`, `write_with_zero` and `reset` methods."]
# [doc = ""]
# [doc = " Registers marked with `Readable` can be also be `modify`'ed."]
pub trait Writable : RegisterSpec { # [doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux ; # [doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux ; } # [doc = " Reset value of the register."]
# [doc = ""]
# [doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
# [doc = " register by using the `reset` method."]
pub trait Resettable : RegisterSpec { # [doc = " Reset value of the register."]
const RESET_VALUE : Self :: Ux ; # [doc = " Reset value of the register."]
# [inline (always)]
fn reset_value () -> Self :: Ux { Self :: RESET_VALUE } } # [doc = " This structure provides volatile access to registers."]
# [repr (transparent)]
pub struct Reg < REG : RegisterSpec > { register : vcell :: VolatileCell < REG :: Ux > , _marker : marker :: PhantomData < REG > , } unsafe impl < REG : RegisterSpec > Send for Reg < REG > where REG :: Ux : Send { } impl < REG : RegisterSpec > Reg < REG > { # [doc = " Returns the underlying memory address of register."]
# [doc = ""]
# [doc = " ```ignore"]
# [doc = " let reg_ptr = periph.reg.as_ptr();"]
# [doc = " ```"]
# [inline (always)]
pub fn as_ptr (& self) -> * mut REG :: Ux { self . register . as_ptr () } } impl < REG : Readable > Reg < REG > { # [doc = " Reads the contents of a `Readable` register."]
# [doc = ""]
# [doc = " You can read the raw contents of a register by using `bits`:"]
# [doc = " ```ignore"]
# [doc = " let bits = periph.reg.read().bits();"]
# [doc = " ```"]
# [doc = " or get the content of a particular field of a register:"]
# [doc = " ```ignore"]
# [doc = " let reader = periph.reg.read();"]
# [doc = " let bits = reader.field1().bits();"]
# [doc = " let flag = reader.field2().bit_is_set();"]
# [doc = " ```"]
# [inline (always)]
pub fn read (& self) -> R < REG > { R { bits : self . register . get () , _reg : marker :: PhantomData , } } } impl < REG : Resettable + Writable > Reg < REG > { # [doc = " Writes the reset value to `Writable` register."]
# [doc = ""]
# [doc = " Resets the register to its initial state."]
# [inline (always)]
pub fn reset (& self) { self . register . set (REG :: RESET_VALUE) } # [doc = " Writes bits to a `Writable` register."]
# [doc = ""]
# [doc = " You can write raw bits into a register:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
# [doc = " ```"]
# [doc = " or write only the fields you need:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.write(|w| w"]
# [doc = "     .field1().bits(newfield1bits)"]
# [doc = "     .field2().set_bit()"]
# [doc = "     .field3().variant(VARIANT)"]
# [doc = " );"]
# [doc = " ```"]
# [doc = " or an alternative way of saying the same:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.write(|w| {"]
# [doc = "     w.field1().bits(newfield1bits);"]
# [doc = "     w.field2().set_bit();"]
# [doc = "     w.field3().variant(VARIANT)"]
# [doc = " });"]
# [doc = " ```"]
# [doc = " In the latter case, other fields will be set to their reset value."]
# [inline (always)]
pub fn write < F > (& self , f : F) where F : FnOnce (& mut W < REG >) -> & mut W < REG > , { self . register . set (f (& mut W { bits : REG :: RESET_VALUE & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , }) . bits ,) ; } } impl < REG : Writable > Reg < REG > { # [doc = " Writes 0 to a `Writable` register."]
# [doc = ""]
# [doc = " Similar to `write`, but unused bits will contain 0."]
# [doc = ""]
# [doc = " # Safety"]
# [doc = ""]
# [doc = " Unsafe to use with registers which don't allow to write 0."]
# [inline (always)]
pub unsafe fn write_with_zero < F > (& self , f : F) where F : FnOnce (& mut W < REG >) -> & mut W < REG > , { self . register . set (f (& mut W { bits : REG :: Ux :: default () , _reg : marker :: PhantomData , }) . bits ,) ; } } impl < REG : Readable + Writable > Reg < REG > { # [doc = " Modifies the contents of the register by reading and then writing it."]
# [doc = ""]
# [doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
# [doc = "    r.bits() | 3"]
# [doc = " ) });"]
# [doc = " ```"]
# [doc = " or"]
# [doc = " ```ignore"]
# [doc = " periph.reg.modify(|_, w| w"]
# [doc = "     .field1().bits(newfield1bits)"]
# [doc = "     .field2().set_bit()"]
# [doc = "     .field3().variant(VARIANT)"]
# [doc = " );"]
# [doc = " ```"]
# [doc = " or an alternative way of saying the same:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.modify(|_, w| {"]
# [doc = "     w.field1().bits(newfield1bits);"]
# [doc = "     w.field2().set_bit();"]
# [doc = "     w.field3().variant(VARIANT)"]
# [doc = " });"]
# [doc = " ```"]
# [doc = " Other fields will have the value they had before the call to `modify`."]
# [inline (always)]
pub fn modify < F > (& self , f : F) where for < 'w > F : FnOnce (& R < REG > , & 'w mut W < REG >) -> & 'w mut W < REG > , { let bits = self . register . get () ; self . register . set (f (& R { bits , _reg : marker :: PhantomData , } , & mut W { bits : bits & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , } ,) . bits ,) ; } } # [doc (hidden)]
pub mod raw { use super :: { marker , BitM , FieldSpec , RegisterSpec , Unsafe , Writable } ; pub struct R < REG : RegisterSpec > { pub (crate) bits : REG :: Ux , pub (super) _reg : marker :: PhantomData < REG > , } pub struct W < REG : RegisterSpec > { # [doc = "Writable bits"]
pub (crate) bits : REG :: Ux , pub (super) _reg : marker :: PhantomData < REG > , } pub struct FieldReader < FI = u8 > where FI : FieldSpec , { pub (crate) bits : FI :: Ux , _reg : marker :: PhantomData < FI > , } impl < FI : FieldSpec > FieldReader < FI > { # [doc = " Creates a new instance of the reader."]
# [allow (unused)]
# [inline (always)]
pub (crate) const fn new (bits : FI :: Ux) -> Self { Self { bits , _reg : marker :: PhantomData , } } } pub struct BitReader < FI = bool > { pub (crate) bits : bool , _reg : marker :: PhantomData < FI > , } impl < FI > BitReader < FI > { # [doc = " Creates a new instance of the reader."]
# [allow (unused)]
# [inline (always)]
pub (crate) const fn new (bits : bool) -> Self { Self { bits , _reg : marker :: PhantomData , } } } pub struct FieldWriter < 'a , REG , const WI : u8 , FI = u8 , Safety = Unsafe > where REG : Writable + RegisterSpec , FI : FieldSpec , { pub (crate) w : & 'a mut W < REG > , pub (crate) o : u8 , _field : marker :: PhantomData < (FI , Safety) > , } impl < 'a , REG , const WI : u8 , FI , Safety > FieldWriter < 'a , REG , WI , FI , Safety > where REG : Writable + RegisterSpec , FI : FieldSpec , { # [doc = " Creates a new instance of the writer"]
# [allow (unused)]
# [inline (always)]
pub (crate) fn new (w : & 'a mut W < REG > , o : u8) -> Self { Self { w , o , _field : marker :: PhantomData , } } } pub struct BitWriter < 'a , REG , FI = bool , M = BitM > where REG : Writable + RegisterSpec , bool : From < FI > , { pub (crate) w : & 'a mut W < REG > , pub (crate) o : u8 , _field : marker :: PhantomData < (FI , M) > , } impl < 'a , REG , FI , M > BitWriter < 'a , REG , FI , M > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = " Creates a new instance of the writer"]
# [allow (unused)]
# [inline (always)]
pub (crate) fn new (w : & 'a mut W < REG > , o : u8) -> Self { Self { w , o , _field : marker :: PhantomData , } } } } # [doc = " Register reader."]
# [doc = ""]
# [doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
# [doc = " method."]
pub type R < REG > = raw :: R < REG > ; impl < REG : RegisterSpec > R < REG > { # [doc = " Reads raw bits from register."]
# [inline (always)]
pub const fn bits (& self) -> REG :: Ux { self . bits } } impl < REG : RegisterSpec , FI > PartialEq < FI > for R < REG > where REG :: Ux : PartialEq , FI : Copy , REG :: Ux : From < FI > , { # [inline (always)]
fn eq (& self , other : & FI) -> bool { self . bits . eq (& REG :: Ux :: from (* other)) } } # [doc = " Register writer."]
# [doc = ""]
# [doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
pub type W < REG > = raw :: W < REG > ; # [doc = " Field reader."]
# [doc = ""]
# [doc = " Result of the `read` methods of fields."]
pub type FieldReader < FI = u8 > = raw :: FieldReader < FI > ; # [doc = " Bit-wise field reader"]
pub type BitReader < FI = bool > = raw :: BitReader < FI > ; impl < FI : FieldSpec > FieldReader < FI > { # [doc = " Reads raw bits from field."]
# [inline (always)]
pub const fn bits (& self) -> FI :: Ux { self . bits } } impl < FI > PartialEq < FI > for FieldReader < FI > where FI : FieldSpec + Copy , { # [inline (always)]
fn eq (& self , other : & FI) -> bool { self . bits . eq (& FI :: Ux :: from (* other)) } } impl < FI > PartialEq < FI > for BitReader < FI > where FI : Copy , bool : From < FI > , { # [inline (always)]
fn eq (& self , other : & FI) -> bool { self . bits . eq (& bool :: from (* other)) } } impl < FI > BitReader < FI > { # [doc = " Value of the field as raw bits."]
# [inline (always)]
pub const fn bit (& self) -> bool { self . bits } # [doc = " Returns `true` if the bit is clear (0)."]
# [inline (always)]
pub const fn bit_is_clear (& self) -> bool { ! self . bit () } # [doc = " Returns `true` if the bit is set (1)."]
# [inline (always)]
pub const fn bit_is_set (& self) -> bool { self . bit () } } # [doc (hidden)]
pub struct Safe ; # [doc (hidden)]
pub struct Unsafe ; # [doc = " Write field Proxy with unsafe `bits`"]
pub type FieldWriter < 'a , REG , const WI : u8 , FI = u8 > = raw :: FieldWriter < 'a , REG , WI , FI , Unsafe > ; # [doc = " Write field Proxy with safe `bits`"]
pub type FieldWriterSafe < 'a , REG , const WI : u8 , FI = u8 > = raw :: FieldWriter < 'a , REG , WI , FI , Safe > ; impl < 'a , REG , const WI : u8 , FI > FieldWriter < 'a , REG , WI , FI > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , { # [doc = " Field width"]
pub const WIDTH : u8 = WI ; # [doc = " Field width"]
# [inline (always)]
pub const fn width (& self) -> u8 { WI } # [doc = " Field offset"]
# [inline (always)]
pub const fn offset (& self) -> u8 { self . o } # [doc = " Writes raw bits to the field"]
# [doc = ""]
# [doc = " # Safety"]
# [doc = ""]
# [doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (self , value : FI :: Ux) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: mask :: < WI > () << self . o) ; self . w . bits |= (REG :: Ux :: from (value) & REG :: Ux :: mask :: < WI > ()) << self . o ; self . w } # [doc = " Writes `variant` to the field"]
# [inline (always)]
pub fn variant (self , variant : FI) -> & 'a mut W < REG > { unsafe { self . bits (FI :: Ux :: from (variant)) } } } impl < 'a , REG , const WI : u8 , FI > FieldWriterSafe < 'a , REG , WI , FI > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , { # [doc = " Field width"]
pub const WIDTH : u8 = WI ; # [doc = " Field width"]
# [inline (always)]
pub const fn width (& self) -> u8 { WI } # [doc = " Field offset"]
# [inline (always)]
pub const fn offset (& self) -> u8 { self . o } # [doc = " Writes raw bits to the field"]
# [inline (always)]
pub fn bits (self , value : FI :: Ux) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: mask :: < WI > () << self . o) ; self . w . bits |= (REG :: Ux :: from (value) & REG :: Ux :: mask :: < WI > ()) << self . o ; self . w } # [doc = " Writes `variant` to the field"]
# [inline (always)]
pub fn variant (self , variant : FI) -> & 'a mut W < REG > { self . bits (FI :: Ux :: from (variant)) } } macro_rules ! bit_proxy { ($ writer : ident , $ mwv : ident) => { # [doc (hidden)]
pub struct $ mwv ; # [doc = " Bit-wise write field proxy"]
pub type $ writer <'a , REG , FI = bool > = raw :: BitWriter <'a , REG , FI , $ mwv >; impl <'a , REG , FI > $ writer <'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI >, { # [doc = " Field width"]
pub const WIDTH : u8 = 1 ; # [doc = " Field width"]
# [inline (always)]
pub const fn width (& self) -> u8 { Self :: WIDTH } # [doc = " Field offset"]
# [inline (always)]
pub const fn offset (& self) -> u8 { self . o } # [doc = " Writes bit to the field"]
# [inline (always)]
pub fn bit (self , value : bool) -> &'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << self . o) ; self . w . bits |= (REG :: Ux :: from (value) & REG :: Ux :: one ()) << self . o ; self . w } # [doc = " Writes `variant` to the field"]
# [inline (always)]
pub fn variant (self , variant : FI) -> &'a mut W < REG > { self . bit (bool :: from (variant)) } } } ; } bit_proxy ! (BitWriter , BitM) ; bit_proxy ! (BitWriter1S , Bit1S) ; bit_proxy ! (BitWriter0C , Bit0C) ; bit_proxy ! (BitWriter1C , Bit1C) ; bit_proxy ! (BitWriter0S , Bit0S) ; bit_proxy ! (BitWriter1T , Bit1T) ; bit_proxy ! (BitWriter0T , Bit0T) ; impl < 'a , REG , FI > BitWriter < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = " Sets the field bit"]
# [inline (always)]
pub fn set_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: one () << self . o ; self . w } # [doc = " Clears the field bit"]
# [inline (always)]
pub fn clear_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << self . o) ; self . w } } impl < 'a , REG , FI > BitWriter1S < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = " Sets the field bit"]
# [inline (always)]
pub fn set_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: one () << self . o ; self . w } } impl < 'a , REG , FI > BitWriter0C < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = " Clears the field bit"]
# [inline (always)]
pub fn clear_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << self . o) ; self . w } } impl < 'a , REG , FI > BitWriter1C < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = "Clears the field bit by passing one"]
# [inline (always)]
pub fn clear_bit_by_one (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: one () << self . o ; self . w } } impl < 'a , REG , FI > BitWriter0S < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = "Sets the field bit by passing zero"]
# [inline (always)]
pub fn set_bit_by_zero (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << self . o) ; self . w } } impl < 'a , REG , FI > BitWriter1T < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = "Toggle the field bit by passing one"]
# [inline (always)]
pub fn toggle_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: one () << self . o ; self . w } } impl < 'a , REG , FI > BitWriter0T < 'a , REG , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = "Toggle the field bit by passing zero"]
# [inline (always)]
pub fn toggle_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << self . o) ; self . w } } } # [cfg (feature = "rt")]
extern "C" { fn RCC () ; fn WWDG () ; fn PVD () ; fn TAMPER () ; fn RTC () ; fn FLASH () ; fn EXTI0 () ; fn EXTI1 () ; fn EXTI2 () ; fn EXTI3 () ; fn EXTI4 () ; fn DMA1_CHANNEL1 () ; fn DMA1_CHANNEL2 () ; fn DMA1_CHANNEL3 () ; fn DMA1_CHANNEL4 () ; fn DMA1_CHANNEL5 () ; fn DMA1_CHANNEL6 () ; fn DMA1_CHANNEL7 () ; fn ADC () ; fn EXTI9_5 () ; fn TIM1_BRK_TIM9 () ; fn TIM1_UP_TIM10 () ; fn TIM1_TRG_COM_TIM11 () ; fn TIM1_CC () ; fn TIM2 () ; fn TIM3 () ; fn TIM4 () ; fn I2C1_EV () ; fn I2C1_ER () ; fn I2C2_EV () ; fn I2C2_ER () ; fn SPI1 () ; fn SPI2 () ; fn USART1 () ; fn USART2 () ; fn USART3 () ; fn EXTI15_10 () ; fn RTCALARM () ; fn USB_FS_WKUP () ; fn USBHD () ; } # [doc (hidden)]
# [repr (C)]
pub union Vector { pub _handler : unsafe extern "C" fn () , pub _reserved : usize , } # [cfg (feature = "rt")]
# [doc (hidden)]
# [no_mangle]
pub static __EXTERNAL_INTERRUPTS : [Vector ; 60]
= [Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _handler : RCC } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _handler : WWDG } , Vector { _handler : PVD } , Vector { _handler : TAMPER } , Vector { _handler : RTC } , Vector { _handler : FLASH } , Vector { _reserved : 0 } , Vector { _handler : EXTI0 } , Vector { _handler : EXTI1 } , Vector { _handler : EXTI2 } , Vector { _handler : EXTI3 } , Vector { _handler : EXTI4 } , Vector { _handler : DMA1_CHANNEL1 } , Vector { _handler : DMA1_CHANNEL2 } , Vector { _handler : DMA1_CHANNEL3 } , Vector { _handler : DMA1_CHANNEL4 } , Vector { _handler : DMA1_CHANNEL5 } , Vector { _handler : DMA1_CHANNEL6 } , Vector { _handler : DMA1_CHANNEL7 } , Vector { _handler : ADC } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _handler : EXTI9_5 } , Vector { _handler : TIM1_BRK_TIM9 } , Vector { _handler : TIM1_UP_TIM10 } , Vector { _handler : TIM1_TRG_COM_TIM11 } , Vector { _handler : TIM1_CC } , Vector { _handler : TIM2 } , Vector { _handler : TIM3 } , Vector { _handler : TIM4 } , Vector { _handler : I2C1_EV } , Vector { _handler : I2C1_ER } , Vector { _handler : I2C2_EV } , Vector { _handler : I2C2_ER } , Vector { _handler : SPI1 } , Vector { _handler : SPI2 } , Vector { _handler : USART1 } , Vector { _handler : USART2 } , Vector { _handler : USART3 } , Vector { _handler : EXTI15_10 } , Vector { _handler : RTCALARM } , Vector { _handler : USB_FS_WKUP } , Vector { _handler : USBHD } ,]
; # [doc (hidden)]
pub mod interrupt { # [doc = r"Enumeration of all the interrupts."]
# [derive (Copy , Clone , Debug , PartialEq , Eq)]
# [repr (u16)]
pub enum Interrupt { # [doc = "5 - RCC global interrupt"]
RCC = 5 , # [doc = "16 - Window Watchdog interrupt"]
WWDG = 16 , # [doc = "17 - PVD through EXTI line detection interrupt"]
PVD = 17 , # [doc = "18 - Tamper interrupt"]
TAMPER = 18 , # [doc = "19 - RTC global interrupt"]
RTC = 19 , # [doc = "20 - Flash global interrupt"]
FLASH = 20 , # [doc = "22 - EXTI Line0 interrupt"]
EXTI0 = 22 , # [doc = "23 - EXTI Line1 interrupt"]
EXTI1 = 23 , # [doc = "24 - EXTI Line2 interrupt"]
EXTI2 = 24 , # [doc = "25 - EXTI Line3 interrupt"]
EXTI3 = 25 , # [doc = "26 - EXTI Line4 interrupt"]
EXTI4 = 26 , # [doc = "27 - DMA1 Channel1 global interrupt"]
DMA1_CHANNEL1 = 27 , # [doc = "28 - DMA1 Channel2 global interrupt"]
DMA1_CHANNEL2 = 28 , # [doc = "29 - DMA1 Channel3 global interrupt"]
DMA1_CHANNEL3 = 29 , # [doc = "30 - DMA1 Channel4 global interrupt"]
DMA1_CHANNEL4 = 30 , # [doc = "31 - DMA1 Channel5 global interrupt"]
DMA1_CHANNEL5 = 31 , # [doc = "32 - DMA1 Channel6 global interrupt"]
DMA1_CHANNEL6 = 32 , # [doc = "33 - DMA1 Channel7 global interrupt"]
DMA1_CHANNEL7 = 33 , # [doc = "34 - ADC1 global interrupt"]
ADC = 34 , # [doc = "39 - EXTI Line\\[9:5\\]
interrupts"]
EXTI9_5 = 39 , # [doc = "40 - TIM1 Break interrupt and TIM9 global interrupt"]
TIM1_BRK_TIM9 = 40 , # [doc = "41 - TIM1 Update interrupt and TIM10 global interrupt"]
TIM1_UP_TIM10 = 41 , # [doc = "42 - TIM1 Trigger and Commutation interrupts and TIM11 global interrupt"]
TIM1_TRG_COM_TIM11 = 42 , # [doc = "43 - TIM1 Capture Compare interrupt"]
TIM1_CC = 43 , # [doc = "44 - TIM2 global interrupt"]
TIM2 = 44 , # [doc = "45 - TIM3 global interrupt"]
TIM3 = 45 , # [doc = "46 - TIM4 global interrupt"]
TIM4 = 46 , # [doc = "47 - I2C1 event interrupt"]
I2C1_EV = 47 , # [doc = "48 - I2C1 error interrupt"]
I2C1_ER = 48 , # [doc = "49 - I2C2 event interrupt"]
I2C2_EV = 49 , # [doc = "50 - I2C2 error interrupt"]
I2C2_ER = 50 , # [doc = "51 - SPI1 global interrupt"]
SPI1 = 51 , # [doc = "52 - SPI2 global interrupt"]
SPI2 = 52 , # [doc = "53 - USART1 global interrupt"]
USART1 = 53 , # [doc = "54 - USART2 global interrupt"]
USART2 = 54 , # [doc = "55 - USART3 global interrupt"]
USART3 = 55 , # [doc = "56 - EXTI Line\\[15:10\\]
interrupts"]
EXTI15_10 = 56 , # [doc = "57 - RTC Alarms through EXTI line interrupt"]
RTCALARM = 57 , # [doc = "58 - USB Device FS Wakeup through EXTI line interrupt"]
USB_FS_WKUP = 58 , # [doc = "59 - USBHD_IRQHandler"]
USBHD = 59 , } # [doc = r" TryFromInterruptError"]
# [derive (Debug , Copy , Clone)]
pub struct TryFromInterruptError (()) ; impl Interrupt { # [doc = r" Attempt to convert a given value into an `Interrupt`"]
# [inline]
pub fn try_from (value : u8) -> Result < Self , TryFromInterruptError > { match value { 5 => Ok (Interrupt :: RCC) , 16 => Ok (Interrupt :: WWDG) , 17 => Ok (Interrupt :: PVD) , 18 => Ok (Interrupt :: TAMPER) , 19 => Ok (Interrupt :: RTC) , 20 => Ok (Interrupt :: FLASH) , 22 => Ok (Interrupt :: EXTI0) , 23 => Ok (Interrupt :: EXTI1) , 24 => Ok (Interrupt :: EXTI2) , 25 => Ok (Interrupt :: EXTI3) , 26 => Ok (Interrupt :: EXTI4) , 27 => Ok (Interrupt :: DMA1_CHANNEL1) , 28 => Ok (Interrupt :: DMA1_CHANNEL2) , 29 => Ok (Interrupt :: DMA1_CHANNEL3) , 30 => Ok (Interrupt :: DMA1_CHANNEL4) , 31 => Ok (Interrupt :: DMA1_CHANNEL5) , 32 => Ok (Interrupt :: DMA1_CHANNEL6) , 33 => Ok (Interrupt :: DMA1_CHANNEL7) , 34 => Ok (Interrupt :: ADC) , 39 => Ok (Interrupt :: EXTI9_5) , 40 => Ok (Interrupt :: TIM1_BRK_TIM9) , 41 => Ok (Interrupt :: TIM1_UP_TIM10) , 42 => Ok (Interrupt :: TIM1_TRG_COM_TIM11) , 43 => Ok (Interrupt :: TIM1_CC) , 44 => Ok (Interrupt :: TIM2) , 45 => Ok (Interrupt :: TIM3) , 46 => Ok (Interrupt :: TIM4) , 47 => Ok (Interrupt :: I2C1_EV) , 48 => Ok (Interrupt :: I2C1_ER) , 49 => Ok (Interrupt :: I2C2_EV) , 50 => Ok (Interrupt :: I2C2_ER) , 51 => Ok (Interrupt :: SPI1) , 52 => Ok (Interrupt :: SPI2) , 53 => Ok (Interrupt :: USART1) , 54 => Ok (Interrupt :: USART2) , 55 => Ok (Interrupt :: USART3) , 56 => Ok (Interrupt :: EXTI15_10) , 57 => Ok (Interrupt :: RTCALARM) , 58 => Ok (Interrupt :: USB_FS_WKUP) , 59 => Ok (Interrupt :: USBHD) , _ => Err (TryFromInterruptError (())) , } } } # [cfg (feature = "rt")]
# [macro_export]
# [doc = r" Assigns a handler to an interrupt"]
# [doc = r""]
# [doc = r" This macro takes two arguments: the name of an interrupt and the path to the"]
# [doc = r" function that will be used as the handler of that interrupt. That function"]
# [doc = r" must have signature `fn()`."]
# [doc = r""]
# [doc = r" Optionally, a third argument may be used to declare interrupt local data."]
# [doc = r" The handler will have exclusive access to these *local* variables on each"]
# [doc = r" invocation. If the third argument is used then the signature of the handler"]
# [doc = r" function must be `fn(&mut $NAME::Locals)` where `$NAME` is the first argument"]
# [doc = r" passed to the macro."]
# [doc = r""]
# [doc = r" # Example"]
# [doc = r""]
# [doc = r" ``` ignore"]
# [doc = r" interrupt!(TIM2, periodic);"]
# [doc = r""]
# [doc = r" fn periodic() {"]
# [doc = r#"     print!(".");"#]
# [doc = r" }"]
# [doc = r""]
# [doc = r" interrupt!(TIM3, tick, locals: {"]
# [doc = r"     tick: bool = false;"]
# [doc = r" });"]
# [doc = r""]
# [doc = r" fn tick(locals: &mut TIM3::Locals) {"]
# [doc = r"     locals.tick = !locals.tick;"]
# [doc = r""]
# [doc = r"     if locals.tick {"]
# [doc = r#"         println!("Tick");"#]
# [doc = r"     } else {"]
# [doc = r#"         println!("Tock");"#]
# [doc = r"     }"]
# [doc = r" }"]
# [doc = r" ```"]
macro_rules ! interrupt { ($ NAME : ident , $ path : path , locals : { $ ($ lvar : ident : $ lty : ty = $ lval : expr ;) * }) => { # [allow (non_snake_case)]
mod $ NAME { pub struct Locals { $ (pub $ lvar : $ lty ,) * } } # [allow (non_snake_case)]
# [no_mangle]
pub extern "C" fn $ NAME () { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; static mut LOCALS : self :: $ NAME :: Locals = self :: $ NAME :: Locals { $ ($ lvar : $ lval ,) * } ; let f : fn (& mut self :: $ NAME :: Locals) = $ path ; f (unsafe { & mut LOCALS }) ; } } ; ($ NAME : ident , $ path : path) => { # [allow (non_snake_case)]
# [no_mangle]
pub extern "C" fn $ NAME () { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; let f : fn () = $ path ; f () ; } } } } pub use self :: interrupt :: Interrupt ; # [doc = "Power control"]
pub struct PWR { _marker : PhantomData < * const () > } unsafe impl Send for PWR { } impl PWR { # [doc = r"Pointer to the register block"]
pub const PTR : * const pwr :: RegisterBlock = 0x4000_7000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const pwr :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for PWR { type Target = pwr :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for PWR { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("PWR") . finish () } } # [doc = "Power control"]
pub mod pwr { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { ctlr : CTLR , csr : CSR , } impl RegisterBlock { # [doc = "0x00 - Power control register (PWR_CTRL)"]
# [inline (always)]
pub const fn ctlr (& self) -> & CTLR { & self . ctlr } # [doc = "0x04 - Power control register (PWR_CSR)"]
# [inline (always)]
pub const fn csr (& self) -> & CSR { & self . csr } } # [doc = "CTLR (rw) register accessor: Power control register (PWR_CTRL)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr`]
module"]
pub type CTLR = crate :: Reg < ctlr :: CTLR_SPEC > ; # [doc = "Power control register (PWR_CTRL)"]
pub mod ctlr { # [doc = "Register `CTLR` reader"]
pub type R = crate :: R < CTLR_SPEC > ; # [doc = "Register `CTLR` writer"]
pub type W = crate :: W < CTLR_SPEC > ; # [doc = "Field `LPDS` reader - Low Power Deep Sleep"]
pub type LPDS_R = crate :: BitReader ; # [doc = "Field `LPDS` writer - Low Power Deep Sleep"]
pub type LPDS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PDDS` reader - Power Down Deep Sleep"]
pub type PDDS_R = crate :: BitReader ; # [doc = "Field `PDDS` writer - Power Down Deep Sleep"]
pub type PDDS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CWUF` reader - Clear Wake-up Flag"]
pub type CWUF_R = crate :: BitReader ; # [doc = "Field `CWUF` writer - Clear Wake-up Flag"]
pub type CWUF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CSBF` reader - Clear STANDBY Flag"]
pub type CSBF_R = crate :: BitReader ; # [doc = "Field `CSBF` writer - Clear STANDBY Flag"]
pub type CSBF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PVDE` reader - Power Voltage Detector Enable"]
pub type PVDE_R = crate :: BitReader ; # [doc = "Field `PVDE` writer - Power Voltage Detector Enable"]
pub type PVDE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PLS` reader - PVD Level Selection"]
pub type PLS_R = crate :: FieldReader ; # [doc = "Field `PLS` writer - PVD Level Selection"]
pub type PLS_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `DBP` reader - Disable Backup Domain write protection"]
pub type DBP_R = crate :: BitReader ; # [doc = "Field `DBP` writer - Disable Backup Domain write protection"]
pub type DBP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Low Power Deep Sleep"]
# [inline (always)]
pub fn lpds (& self) -> LPDS_R { LPDS_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Power Down Deep Sleep"]
# [inline (always)]
pub fn pdds (& self) -> PDDS_R { PDDS_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Clear Wake-up Flag"]
# [inline (always)]
pub fn cwuf (& self) -> CWUF_R { CWUF_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Clear STANDBY Flag"]
# [inline (always)]
pub fn csbf (& self) -> CSBF_R { CSBF_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Power Voltage Detector Enable"]
# [inline (always)]
pub fn pvde (& self) -> PVDE_R { PVDE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:7 - PVD Level Selection"]
# [inline (always)]
pub fn pls (& self) -> PLS_R { PLS_R :: new (((self . bits >> 5) & 7) as u8) } # [doc = "Bit 8 - Disable Backup Domain write protection"]
# [inline (always)]
pub fn dbp (& self) -> DBP_R { DBP_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 0 - Low Power Deep Sleep"]
# [inline (always)]
# [must_use]
pub fn lpds (& mut self) -> LPDS_W < CTLR_SPEC > { LPDS_W :: new (self , 0) } # [doc = "Bit 1 - Power Down Deep Sleep"]
# [inline (always)]
# [must_use]
pub fn pdds (& mut self) -> PDDS_W < CTLR_SPEC > { PDDS_W :: new (self , 1) } # [doc = "Bit 2 - Clear Wake-up Flag"]
# [inline (always)]
# [must_use]
pub fn cwuf (& mut self) -> CWUF_W < CTLR_SPEC > { CWUF_W :: new (self , 2) } # [doc = "Bit 3 - Clear STANDBY Flag"]
# [inline (always)]
# [must_use]
pub fn csbf (& mut self) -> CSBF_W < CTLR_SPEC > { CSBF_W :: new (self , 3) } # [doc = "Bit 4 - Power Voltage Detector Enable"]
# [inline (always)]
# [must_use]
pub fn pvde (& mut self) -> PVDE_W < CTLR_SPEC > { PVDE_W :: new (self , 4) } # [doc = "Bits 5:7 - PVD Level Selection"]
# [inline (always)]
# [must_use]
pub fn pls (& mut self) -> PLS_W < CTLR_SPEC > { PLS_W :: new (self , 5) } # [doc = "Bit 8 - Disable Backup Domain write protection"]
# [inline (always)]
# [must_use]
pub fn dbp (& mut self) -> DBP_W < CTLR_SPEC > { DBP_W :: new (self , 8) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power control register (PWR_CTRL)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR_SPEC ; impl crate :: RegisterSpec for CTLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr::R`](R) reader structure"]
impl crate :: Readable for CTLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr::W`](W) writer structure"]
impl crate :: Writable for CTLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR to value 0"]
impl crate :: Resettable for CTLR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CSR (rw) register accessor: Power control register (PWR_CSR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csr`]
module"]
pub type CSR = crate :: Reg < csr :: CSR_SPEC > ; # [doc = "Power control register (PWR_CSR)"]
pub mod csr { # [doc = "Register `CSR` reader"]
pub type R = crate :: R < CSR_SPEC > ; # [doc = "Register `CSR` writer"]
pub type W = crate :: W < CSR_SPEC > ; # [doc = "Field `WUF` reader - Wake-Up Flag"]
pub type WUF_R = crate :: BitReader ; # [doc = "Field `SBF` reader - STANDBY Flag"]
pub type SBF_R = crate :: BitReader ; # [doc = "Field `PVDO` reader - PVD Output"]
pub type PVDO_R = crate :: BitReader ; # [doc = "Field `EWUP` reader - Enable WKUP pin"]
pub type EWUP_R = crate :: BitReader ; # [doc = "Field `EWUP` writer - Enable WKUP pin"]
pub type EWUP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Wake-Up Flag"]
# [inline (always)]
pub fn wuf (& self) -> WUF_R { WUF_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - STANDBY Flag"]
# [inline (always)]
pub fn sbf (& self) -> SBF_R { SBF_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - PVD Output"]
# [inline (always)]
pub fn pvdo (& self) -> PVDO_R { PVDO_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 8 - Enable WKUP pin"]
# [inline (always)]
pub fn ewup (& self) -> EWUP_R { EWUP_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Enable WKUP pin"]
# [inline (always)]
# [must_use]
pub fn ewup (& mut self) -> EWUP_W < CSR_SPEC > { EWUP_W :: new (self , 8) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power control register (PWR_CSR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CSR_SPEC ; impl crate :: RegisterSpec for CSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`csr::R`](R) reader structure"]
impl crate :: Readable for CSR_SPEC { } # [doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"]
impl crate :: Writable for CSR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CSR to value 0"]
impl crate :: Resettable for CSR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Reset and clock control"]
pub struct RCC { _marker : PhantomData < * const () > } unsafe impl Send for RCC { } impl RCC { # [doc = r"Pointer to the register block"]
pub const PTR : * const rcc :: RegisterBlock = 0x4002_1000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const rcc :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for RCC { type Target = rcc :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for RCC { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("RCC") . finish () } } # [doc = "Reset and clock control"]
pub mod rcc { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { ctlr : CTLR , cfgr0 : CFGR0 , intr : INTR , apb2prstr : APB2PRSTR , apb1prstr : APB1PRSTR , ahbpcenr : AHBPCENR , apb2pcenr : APB2PCENR , apb1pcenr : APB1PCENR , bdctlr : BDCTLR , rstsckr : RSTSCKR , ahbrstr : AHBRSTR , } impl RegisterBlock { # [doc = "0x00 - Clock control register"]
# [inline (always)]
pub const fn ctlr (& self) -> & CTLR { & self . ctlr } # [doc = "0x04 - Clock configuration register(RCC_CFGR0)"]
# [inline (always)]
pub const fn cfgr0 (& self) -> & CFGR0 { & self . cfgr0 } # [doc = "0x08 - Clock interrupt register(RCC_INTR)"]
# [inline (always)]
pub const fn intr (& self) -> & INTR { & self . intr } # [doc = "0x0c - APB2 peripheral reset register(RCC_APB2PRSTR)"]
# [inline (always)]
pub const fn apb2prstr (& self) -> & APB2PRSTR { & self . apb2prstr } # [doc = "0x10 - APB1 peripheral reset register(RCC_APB1PRSTR)"]
# [inline (always)]
pub const fn apb1prstr (& self) -> & APB1PRSTR { & self . apb1prstr } # [doc = "0x14 - AHB Peripheral Clock enable register(RCC_AHBPCENR)"]
# [inline (always)]
pub const fn ahbpcenr (& self) -> & AHBPCENR { & self . ahbpcenr } # [doc = "0x18 - APB2 peripheral clock enable register (RCC_APB2PCENR)"]
# [inline (always)]
pub const fn apb2pcenr (& self) -> & APB2PCENR { & self . apb2pcenr } # [doc = "0x1c - APB1 peripheral clock enable register (RCC_APB1PCENR)"]
# [inline (always)]
pub const fn apb1pcenr (& self) -> & APB1PCENR { & self . apb1pcenr } # [doc = "0x20 - Backup domain control register(RCC_BDCTLR)"]
# [inline (always)]
pub const fn bdctlr (& self) -> & BDCTLR { & self . bdctlr } # [doc = "0x24 - Control/status register(RCC_RSTSCKR)"]
# [inline (always)]
pub const fn rstsckr (& self) -> & RSTSCKR { & self . rstsckr } # [doc = "0x28 - AHB reset register(RCC_APHBRSTR)"]
# [inline (always)]
pub const fn ahbrstr (& self) -> & AHBRSTR { & self . ahbrstr } } # [doc = "CTLR (rw) register accessor: Clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr`]
module"]
pub type CTLR = crate :: Reg < ctlr :: CTLR_SPEC > ; # [doc = "Clock control register"]
pub mod ctlr { # [doc = "Register `CTLR` reader"]
pub type R = crate :: R < CTLR_SPEC > ; # [doc = "Register `CTLR` writer"]
pub type W = crate :: W < CTLR_SPEC > ; # [doc = "Field `HSION` reader - Internal High Speed clock enable"]
pub type HSION_R = crate :: BitReader ; # [doc = "Field `HSION` writer - Internal High Speed clock enable"]
pub type HSION_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSIRDY` reader - Internal High Speed clock ready flag"]
pub type HSIRDY_R = crate :: BitReader ; # [doc = "Field `HSITRIM` reader - Internal High Speed clock trimming"]
pub type HSITRIM_R = crate :: FieldReader ; # [doc = "Field `HSITRIM` writer - Internal High Speed clock trimming"]
pub type HSITRIM_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `HSICAL` reader - Internal High Speed clock Calibration"]
pub type HSICAL_R = crate :: FieldReader ; # [doc = "Field `HSEON` reader - External High Speed clock enable"]
pub type HSEON_R = crate :: BitReader ; # [doc = "Field `HSEON` writer - External High Speed clock enable"]
pub type HSEON_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSERDY` reader - External High Speed clock ready flag"]
pub type HSERDY_R = crate :: BitReader ; # [doc = "Field `HSEBYP` reader - External High Speed clock Bypass"]
pub type HSEBYP_R = crate :: BitReader ; # [doc = "Field `HSEBYP` writer - External High Speed clock Bypass"]
pub type HSEBYP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CSSON` reader - Clock Security System enable"]
pub type CSSON_R = crate :: BitReader ; # [doc = "Field `CSSON` writer - Clock Security System enable"]
pub type CSSON_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PLLON` reader - PLL enable"]
pub type PLLON_R = crate :: BitReader ; # [doc = "Field `PLLON` writer - PLL enable"]
pub type PLLON_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PLLRDY` reader - PLL clock ready flag"]
pub type PLLRDY_R = crate :: BitReader ; impl R { # [doc = "Bit 0 - Internal High Speed clock enable"]
# [inline (always)]
pub fn hsion (& self) -> HSION_R { HSION_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Internal High Speed clock ready flag"]
# [inline (always)]
pub fn hsirdy (& self) -> HSIRDY_R { HSIRDY_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 3:7 - Internal High Speed clock trimming"]
# [inline (always)]
pub fn hsitrim (& self) -> HSITRIM_R { HSITRIM_R :: new (((self . bits >> 3) & 0x1f) as u8) } # [doc = "Bits 8:15 - Internal High Speed clock Calibration"]
# [inline (always)]
pub fn hsical (& self) -> HSICAL_R { HSICAL_R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bit 16 - External High Speed clock enable"]
# [inline (always)]
pub fn hseon (& self) -> HSEON_R { HSEON_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - External High Speed clock ready flag"]
# [inline (always)]
pub fn hserdy (& self) -> HSERDY_R { HSERDY_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - External High Speed clock Bypass"]
# [inline (always)]
pub fn hsebyp (& self) -> HSEBYP_R { HSEBYP_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Clock Security System enable"]
# [inline (always)]
pub fn csson (& self) -> CSSON_R { CSSON_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 24 - PLL enable"]
# [inline (always)]
pub fn pllon (& self) -> PLLON_R { PLLON_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - PLL clock ready flag"]
# [inline (always)]
pub fn pllrdy (& self) -> PLLRDY_R { PLLRDY_R :: new (((self . bits >> 25) & 1) != 0) } } impl W { # [doc = "Bit 0 - Internal High Speed clock enable"]
# [inline (always)]
# [must_use]
pub fn hsion (& mut self) -> HSION_W < CTLR_SPEC > { HSION_W :: new (self , 0) } # [doc = "Bits 3:7 - Internal High Speed clock trimming"]
# [inline (always)]
# [must_use]
pub fn hsitrim (& mut self) -> HSITRIM_W < CTLR_SPEC > { HSITRIM_W :: new (self , 3) } # [doc = "Bit 16 - External High Speed clock enable"]
# [inline (always)]
# [must_use]
pub fn hseon (& mut self) -> HSEON_W < CTLR_SPEC > { HSEON_W :: new (self , 16) } # [doc = "Bit 18 - External High Speed clock Bypass"]
# [inline (always)]
# [must_use]
pub fn hsebyp (& mut self) -> HSEBYP_W < CTLR_SPEC > { HSEBYP_W :: new (self , 18) } # [doc = "Bit 19 - Clock Security System enable"]
# [inline (always)]
# [must_use]
pub fn csson (& mut self) -> CSSON_W < CTLR_SPEC > { CSSON_W :: new (self , 19) } # [doc = "Bit 24 - PLL enable"]
# [inline (always)]
# [must_use]
pub fn pllon (& mut self) -> PLLON_W < CTLR_SPEC > { PLLON_W :: new (self , 24) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR_SPEC ; impl crate :: RegisterSpec for CTLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr::R`](R) reader structure"]
impl crate :: Readable for CTLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr::W`](W) writer structure"]
impl crate :: Writable for CTLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR to value 0x83"]
impl crate :: Resettable for CTLR_SPEC { const RESET_VALUE : u32 = 0x83 ; } } # [doc = "CFGR0 (rw) register accessor: Clock configuration register(RCC_CFGR0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr0`]
module"]
pub type CFGR0 = crate :: Reg < cfgr0 :: CFGR0_SPEC > ; # [doc = "Clock configuration register(RCC_CFGR0)"]
pub mod cfgr0 { # [doc = "Register `CFGR0` reader"]
pub type R = crate :: R < CFGR0_SPEC > ; # [doc = "Register `CFGR0` writer"]
pub type W = crate :: W < CFGR0_SPEC > ; # [doc = "Field `SW` reader - System clock Switch"]
pub type SW_R = crate :: FieldReader ; # [doc = "Field `SW` writer - System clock Switch"]
pub type SW_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SWS` reader - System Clock Switch Status"]
pub type SWS_R = crate :: FieldReader ; # [doc = "Field `HPRE` reader - AHB prescaler"]
pub type HPRE_R = crate :: FieldReader ; # [doc = "Field `HPRE` writer - AHB prescaler"]
pub type HPRE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PPRE1` reader - APB Low speed prescaler(APB1)"]
pub type PPRE1_R = crate :: FieldReader ; # [doc = "Field `PPRE1` writer - APB Low speed prescaler(APB1)"]
pub type PPRE1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PPRE2` reader - APB High speed prescaler(APB2)"]
pub type PPRE2_R = crate :: FieldReader ; # [doc = "Field `PPRE2` writer - APB High speed prescaler(APB2)"]
pub type PPRE2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `ADCPRE` reader - ADC prescaler"]
pub type ADCPRE_R = crate :: FieldReader ; # [doc = "Field `ADCPRE` writer - ADC prescaler"]
pub type ADCPRE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PLLSRC` reader - PLL entry clock source"]
pub type PLLSRC_R = crate :: BitReader ; # [doc = "Field `PLLSRC` writer - PLL entry clock source"]
pub type PLLSRC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PLLXTPRE` reader - HSE divider for PLL entry"]
pub type PLLXTPRE_R = crate :: BitReader ; # [doc = "Field `PLLXTPRE` writer - HSE divider for PLL entry"]
pub type PLLXTPRE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PLLMUL` reader - PLL Multiplication Factor"]
pub type PLLMUL_R = crate :: FieldReader ; # [doc = "Field `PLLMUL` writer - PLL Multiplication Factor"]
pub type PLLMUL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `USBPRE` reader - USB prescaler"]
pub type USBPRE_R = crate :: BitReader ; # [doc = "Field `USBPRE` writer - USB prescaler"]
pub type USBPRE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MCO` reader - Microcontroller clock output"]
pub type MCO_R = crate :: FieldReader ; # [doc = "Field `MCO` writer - Microcontroller clock output"]
pub type MCO_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:1 - System clock Switch"]
# [inline (always)]
pub fn sw (& self) -> SW_R { SW_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - System Clock Switch Status"]
# [inline (always)]
pub fn sws (& self) -> SWS_R { SWS_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - AHB prescaler"]
# [inline (always)]
pub fn hpre (& self) -> HPRE_R { HPRE_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:10 - APB Low speed prescaler(APB1)"]
# [inline (always)]
pub fn ppre1 (& self) -> PPRE1_R { PPRE1_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 11:13 - APB High speed prescaler(APB2)"]
# [inline (always)]
pub fn ppre2 (& self) -> PPRE2_R { PPRE2_R :: new (((self . bits >> 11) & 7) as u8) } # [doc = "Bits 14:15 - ADC prescaler"]
# [inline (always)]
pub fn adcpre (& self) -> ADCPRE_R { ADCPRE_R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bit 16 - PLL entry clock source"]
# [inline (always)]
pub fn pllsrc (& self) -> PLLSRC_R { PLLSRC_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - HSE divider for PLL entry"]
# [inline (always)]
pub fn pllxtpre (& self) -> PLLXTPRE_R { PLLXTPRE_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:21 - PLL Multiplication Factor"]
# [inline (always)]
pub fn pllmul (& self) -> PLLMUL_R { PLLMUL_R :: new (((self . bits >> 18) & 0x0f) as u8) } # [doc = "Bit 22 - USB prescaler"]
# [inline (always)]
pub fn usbpre (& self) -> USBPRE_R { USBPRE_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bits 24:26 - Microcontroller clock output"]
# [inline (always)]
pub fn mco (& self) -> MCO_R { MCO_R :: new (((self . bits >> 24) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - System clock Switch"]
# [inline (always)]
# [must_use]
pub fn sw (& mut self) -> SW_W < CFGR0_SPEC > { SW_W :: new (self , 0) } # [doc = "Bits 4:7 - AHB prescaler"]
# [inline (always)]
# [must_use]
pub fn hpre (& mut self) -> HPRE_W < CFGR0_SPEC > { HPRE_W :: new (self , 4) } # [doc = "Bits 8:10 - APB Low speed prescaler(APB1)"]
# [inline (always)]
# [must_use]
pub fn ppre1 (& mut self) -> PPRE1_W < CFGR0_SPEC > { PPRE1_W :: new (self , 8) } # [doc = "Bits 11:13 - APB High speed prescaler(APB2)"]
# [inline (always)]
# [must_use]
pub fn ppre2 (& mut self) -> PPRE2_W < CFGR0_SPEC > { PPRE2_W :: new (self , 11) } # [doc = "Bits 14:15 - ADC prescaler"]
# [inline (always)]
# [must_use]
pub fn adcpre (& mut self) -> ADCPRE_W < CFGR0_SPEC > { ADCPRE_W :: new (self , 14) } # [doc = "Bit 16 - PLL entry clock source"]
# [inline (always)]
# [must_use]
pub fn pllsrc (& mut self) -> PLLSRC_W < CFGR0_SPEC > { PLLSRC_W :: new (self , 16) } # [doc = "Bit 17 - HSE divider for PLL entry"]
# [inline (always)]
# [must_use]
pub fn pllxtpre (& mut self) -> PLLXTPRE_W < CFGR0_SPEC > { PLLXTPRE_W :: new (self , 17) } # [doc = "Bits 18:21 - PLL Multiplication Factor"]
# [inline (always)]
# [must_use]
pub fn pllmul (& mut self) -> PLLMUL_W < CFGR0_SPEC > { PLLMUL_W :: new (self , 18) } # [doc = "Bit 22 - USB prescaler"]
# [inline (always)]
# [must_use]
pub fn usbpre (& mut self) -> USBPRE_W < CFGR0_SPEC > { USBPRE_W :: new (self , 22) } # [doc = "Bits 24:26 - Microcontroller clock output"]
# [inline (always)]
# [must_use]
pub fn mco (& mut self) -> MCO_W < CFGR0_SPEC > { MCO_W :: new (self , 24) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock configuration register(RCC_CFGR0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGR0_SPEC ; impl crate :: RegisterSpec for CFGR0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr0::R`](R) reader structure"]
impl crate :: Readable for CFGR0_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgr0::W`](W) writer structure"]
impl crate :: Writable for CFGR0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFGR0 to value 0"]
impl crate :: Resettable for CFGR0_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTR (rw) register accessor: Clock interrupt register(RCC_INTR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr`]
module"]
pub type INTR = crate :: Reg < intr :: INTR_SPEC > ; # [doc = "Clock interrupt register(RCC_INTR)"]
pub mod intr { # [doc = "Register `INTR` reader"]
pub type R = crate :: R < INTR_SPEC > ; # [doc = "Register `INTR` writer"]
pub type W = crate :: W < INTR_SPEC > ; # [doc = "Field `LSIRDYF` reader - LSI Ready Interrupt flag"]
pub type LSIRDYF_R = crate :: BitReader ; # [doc = "Field `LSERDYF` reader - LSE Ready Interrupt flag"]
pub type LSERDYF_R = crate :: BitReader ; # [doc = "Field `HSIRDYF` reader - HSI Ready Interrupt flag"]
pub type HSIRDYF_R = crate :: BitReader ; # [doc = "Field `HSERDYF` reader - HSE Ready Interrupt flag"]
pub type HSERDYF_R = crate :: BitReader ; # [doc = "Field `PLLRDYF` reader - PLL Ready Interrupt flag"]
pub type PLLRDYF_R = crate :: BitReader ; # [doc = "Field `CSSF` reader - Clock Security System Interrupt flag"]
pub type CSSF_R = crate :: BitReader ; # [doc = "Field `LSIRDYIE` reader - LSI Ready Interrupt Enable"]
pub type LSIRDYIE_R = crate :: BitReader ; # [doc = "Field `LSIRDYIE` writer - LSI Ready Interrupt Enable"]
pub type LSIRDYIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LSERDYIE` reader - LSE Ready Interrupt Enable"]
pub type LSERDYIE_R = crate :: BitReader ; # [doc = "Field `LSERDYIE` writer - LSE Ready Interrupt Enable"]
pub type LSERDYIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSIRDYIE` reader - HSI Ready Interrupt Enable"]
pub type HSIRDYIE_R = crate :: BitReader ; # [doc = "Field `HSIRDYIE` writer - HSI Ready Interrupt Enable"]
pub type HSIRDYIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSERDYIE` reader - HSE Ready Interrupt Enable"]
pub type HSERDYIE_R = crate :: BitReader ; # [doc = "Field `HSERDYIE` writer - HSE Ready Interrupt Enable"]
pub type HSERDYIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PLLRDYIE` reader - PLL Ready Interrupt Enable"]
pub type PLLRDYIE_R = crate :: BitReader ; # [doc = "Field `PLLRDYIE` writer - PLL Ready Interrupt Enable"]
pub type PLLRDYIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LSIRDYC` writer - LSI Ready Interrupt Clear"]
pub type LSIRDYC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LSERDYC` writer - LSE Ready Interrupt Clear"]
pub type LSERDYC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSIRDYC` writer - HSI Ready Interrupt Clear"]
pub type HSIRDYC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSERDYC` writer - HSE Ready Interrupt Clear"]
pub type HSERDYC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PLLRDYC` writer - PLL Ready Interrupt Clear"]
pub type PLLRDYC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CSSC` writer - Clock security system interrupt clear"]
pub type CSSC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - LSI Ready Interrupt flag"]
# [inline (always)]
pub fn lsirdyf (& self) -> LSIRDYF_R { LSIRDYF_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - LSE Ready Interrupt flag"]
# [inline (always)]
pub fn lserdyf (& self) -> LSERDYF_R { LSERDYF_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - HSI Ready Interrupt flag"]
# [inline (always)]
pub fn hsirdyf (& self) -> HSIRDYF_R { HSIRDYF_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - HSE Ready Interrupt flag"]
# [inline (always)]
pub fn hserdyf (& self) -> HSERDYF_R { HSERDYF_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - PLL Ready Interrupt flag"]
# [inline (always)]
pub fn pllrdyf (& self) -> PLLRDYF_R { PLLRDYF_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 7 - Clock Security System Interrupt flag"]
# [inline (always)]
pub fn cssf (& self) -> CSSF_R { CSSF_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - LSI Ready Interrupt Enable"]
# [inline (always)]
pub fn lsirdyie (& self) -> LSIRDYIE_R { LSIRDYIE_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - LSE Ready Interrupt Enable"]
# [inline (always)]
pub fn lserdyie (& self) -> LSERDYIE_R { LSERDYIE_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - HSI Ready Interrupt Enable"]
# [inline (always)]
pub fn hsirdyie (& self) -> HSIRDYIE_R { HSIRDYIE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - HSE Ready Interrupt Enable"]
# [inline (always)]
pub fn hserdyie (& self) -> HSERDYIE_R { HSERDYIE_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - PLL Ready Interrupt Enable"]
# [inline (always)]
pub fn pllrdyie (& self) -> PLLRDYIE_R { PLLRDYIE_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bit 8 - LSI Ready Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn lsirdyie (& mut self) -> LSIRDYIE_W < INTR_SPEC > { LSIRDYIE_W :: new (self , 8) } # [doc = "Bit 9 - LSE Ready Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn lserdyie (& mut self) -> LSERDYIE_W < INTR_SPEC > { LSERDYIE_W :: new (self , 9) } # [doc = "Bit 10 - HSI Ready Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn hsirdyie (& mut self) -> HSIRDYIE_W < INTR_SPEC > { HSIRDYIE_W :: new (self , 10) } # [doc = "Bit 11 - HSE Ready Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn hserdyie (& mut self) -> HSERDYIE_W < INTR_SPEC > { HSERDYIE_W :: new (self , 11) } # [doc = "Bit 12 - PLL Ready Interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn pllrdyie (& mut self) -> PLLRDYIE_W < INTR_SPEC > { PLLRDYIE_W :: new (self , 12) } # [doc = "Bit 16 - LSI Ready Interrupt Clear"]
# [inline (always)]
# [must_use]
pub fn lsirdyc (& mut self) -> LSIRDYC_W < INTR_SPEC > { LSIRDYC_W :: new (self , 16) } # [doc = "Bit 17 - LSE Ready Interrupt Clear"]
# [inline (always)]
# [must_use]
pub fn lserdyc (& mut self) -> LSERDYC_W < INTR_SPEC > { LSERDYC_W :: new (self , 17) } # [doc = "Bit 18 - HSI Ready Interrupt Clear"]
# [inline (always)]
# [must_use]
pub fn hsirdyc (& mut self) -> HSIRDYC_W < INTR_SPEC > { HSIRDYC_W :: new (self , 18) } # [doc = "Bit 19 - HSE Ready Interrupt Clear"]
# [inline (always)]
# [must_use]
pub fn hserdyc (& mut self) -> HSERDYC_W < INTR_SPEC > { HSERDYC_W :: new (self , 19) } # [doc = "Bit 20 - PLL Ready Interrupt Clear"]
# [inline (always)]
# [must_use]
pub fn pllrdyc (& mut self) -> PLLRDYC_W < INTR_SPEC > { PLLRDYC_W :: new (self , 20) } # [doc = "Bit 23 - Clock security system interrupt clear"]
# [inline (always)]
# [must_use]
pub fn cssc (& mut self) -> CSSC_W < INTR_SPEC > { CSSC_W :: new (self , 23) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock interrupt register(RCC_INTR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTR_SPEC ; impl crate :: RegisterSpec for INTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`intr::R`](R) reader structure"]
impl crate :: Readable for INTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"]
impl crate :: Writable for INTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTR to value 0"]
impl crate :: Resettable for INTR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "APB2PRSTR (rw) register accessor: APB2 peripheral reset register(RCC_APB2PRSTR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2prstr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apb2prstr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2prstr`]
module"]
pub type APB2PRSTR = crate :: Reg < apb2prstr :: APB2PRSTR_SPEC > ; # [doc = "APB2 peripheral reset register(RCC_APB2PRSTR)"]
pub mod apb2prstr { # [doc = "Register `APB2PRSTR` reader"]
pub type R = crate :: R < APB2PRSTR_SPEC > ; # [doc = "Register `APB2PRSTR` writer"]
pub type W = crate :: W < APB2PRSTR_SPEC > ; # [doc = "Field `AFIORST` reader - Alternate function I/O reset"]
pub type AFIORST_R = crate :: BitReader ; # [doc = "Field `AFIORST` writer - Alternate function I/O reset"]
pub type AFIORST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IOPARST` reader - IO port A reset"]
pub type IOPARST_R = crate :: BitReader ; # [doc = "Field `IOPARST` writer - IO port A reset"]
pub type IOPARST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IOPBRST` reader - IO port B reset"]
pub type IOPBRST_R = crate :: BitReader ; # [doc = "Field `IOPBRST` writer - IO port B reset"]
pub type IOPBRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IOPCRST` reader - IO port C reset"]
pub type IOPCRST_R = crate :: BitReader ; # [doc = "Field `IOPCRST` writer - IO port C reset"]
pub type IOPCRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IOPDRST` reader - IO port D reset"]
pub type IOPDRST_R = crate :: BitReader ; # [doc = "Field `IOPDRST` writer - IO port D reset"]
pub type IOPDRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCRST` reader - ADC interface reset"]
pub type ADCRST_R = crate :: BitReader ; # [doc = "Field `ADCRST` writer - ADC interface reset"]
pub type ADCRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIM1RST` reader - TIM1 timer reset"]
pub type TIM1RST_R = crate :: BitReader ; # [doc = "Field `TIM1RST` writer - TIM1 timer reset"]
pub type TIM1RST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPI1RST` reader - SPI 1 reset"]
pub type SPI1RST_R = crate :: BitReader ; # [doc = "Field `SPI1RST` writer - SPI 1 reset"]
pub type SPI1RST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USART1RST` reader - USART1 reset"]
pub type USART1RST_R = crate :: BitReader ; # [doc = "Field `USART1RST` writer - USART1 reset"]
pub type USART1RST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Alternate function I/O reset"]
# [inline (always)]
pub fn afiorst (& self) -> AFIORST_R { AFIORST_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - IO port A reset"]
# [inline (always)]
pub fn ioparst (& self) -> IOPARST_R { IOPARST_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - IO port B reset"]
# [inline (always)]
pub fn iopbrst (& self) -> IOPBRST_R { IOPBRST_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - IO port C reset"]
# [inline (always)]
pub fn iopcrst (& self) -> IOPCRST_R { IOPCRST_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - IO port D reset"]
# [inline (always)]
pub fn iopdrst (& self) -> IOPDRST_R { IOPDRST_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 9 - ADC interface reset"]
# [inline (always)]
pub fn adcrst (& self) -> ADCRST_R { ADCRST_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 11 - TIM1 timer reset"]
# [inline (always)]
pub fn tim1rst (& self) -> TIM1RST_R { TIM1RST_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - SPI 1 reset"]
# [inline (always)]
pub fn spi1rst (& self) -> SPI1RST_R { SPI1RST_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 14 - USART1 reset"]
# [inline (always)]
pub fn usart1rst (& self) -> USART1RST_R { USART1RST_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Alternate function I/O reset"]
# [inline (always)]
# [must_use]
pub fn afiorst (& mut self) -> AFIORST_W < APB2PRSTR_SPEC > { AFIORST_W :: new (self , 0) } # [doc = "Bit 2 - IO port A reset"]
# [inline (always)]
# [must_use]
pub fn ioparst (& mut self) -> IOPARST_W < APB2PRSTR_SPEC > { IOPARST_W :: new (self , 2) } # [doc = "Bit 3 - IO port B reset"]
# [inline (always)]
# [must_use]
pub fn iopbrst (& mut self) -> IOPBRST_W < APB2PRSTR_SPEC > { IOPBRST_W :: new (self , 3) } # [doc = "Bit 4 - IO port C reset"]
# [inline (always)]
# [must_use]
pub fn iopcrst (& mut self) -> IOPCRST_W < APB2PRSTR_SPEC > { IOPCRST_W :: new (self , 4) } # [doc = "Bit 5 - IO port D reset"]
# [inline (always)]
# [must_use]
pub fn iopdrst (& mut self) -> IOPDRST_W < APB2PRSTR_SPEC > { IOPDRST_W :: new (self , 5) } # [doc = "Bit 9 - ADC interface reset"]
# [inline (always)]
# [must_use]
pub fn adcrst (& mut self) -> ADCRST_W < APB2PRSTR_SPEC > { ADCRST_W :: new (self , 9) } # [doc = "Bit 11 - TIM1 timer reset"]
# [inline (always)]
# [must_use]
pub fn tim1rst (& mut self) -> TIM1RST_W < APB2PRSTR_SPEC > { TIM1RST_W :: new (self , 11) } # [doc = "Bit 12 - SPI 1 reset"]
# [inline (always)]
# [must_use]
pub fn spi1rst (& mut self) -> SPI1RST_W < APB2PRSTR_SPEC > { SPI1RST_W :: new (self , 12) } # [doc = "Bit 14 - USART1 reset"]
# [inline (always)]
# [must_use]
pub fn usart1rst (& mut self) -> USART1RST_W < APB2PRSTR_SPEC > { USART1RST_W :: new (self , 14) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "APB2 peripheral reset register(RCC_APB2PRSTR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2prstr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apb2prstr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct APB2PRSTR_SPEC ; impl crate :: RegisterSpec for APB2PRSTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`apb2prstr::R`](R) reader structure"]
impl crate :: Readable for APB2PRSTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`apb2prstr::W`](W) writer structure"]
impl crate :: Writable for APB2PRSTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APB2PRSTR to value 0"]
impl crate :: Resettable for APB2PRSTR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "APB1PRSTR (rw) register accessor: APB1 peripheral reset register(RCC_APB1PRSTR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb1prstr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apb1prstr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb1prstr`]
module"]
pub type APB1PRSTR = crate :: Reg < apb1prstr :: APB1PRSTR_SPEC > ; # [doc = "APB1 peripheral reset register(RCC_APB1PRSTR)"]
pub mod apb1prstr { # [doc = "Register `APB1PRSTR` reader"]
pub type R = crate :: R < APB1PRSTR_SPEC > ; # [doc = "Register `APB1PRSTR` writer"]
pub type W = crate :: W < APB1PRSTR_SPEC > ; # [doc = "Field `TIM2RST` reader - Timer 2 reset"]
pub type TIM2RST_R = crate :: BitReader ; # [doc = "Field `TIM2RST` writer - Timer 2 reset"]
pub type TIM2RST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIM3RST` reader - Timer 3 reset"]
pub type TIM3RST_R = crate :: BitReader ; # [doc = "Field `TIM3RST` writer - Timer 3 reset"]
pub type TIM3RST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIM4RST` reader - Timer 4 reset"]
pub type TIM4RST_R = crate :: BitReader ; # [doc = "Field `TIM4RST` writer - Timer 4 reset"]
pub type TIM4RST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WWDGRST` reader - Window watchdog reset"]
pub type WWDGRST_R = crate :: BitReader ; # [doc = "Field `WWDGRST` writer - Window watchdog reset"]
pub type WWDGRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPI2RST` reader - SPI2 reset"]
pub type SPI2RST_R = crate :: BitReader ; # [doc = "Field `SPI2RST` writer - SPI2 reset"]
pub type SPI2RST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USART2RST` reader - USART 2 reset"]
pub type USART2RST_R = crate :: BitReader ; # [doc = "Field `USART2RST` writer - USART 2 reset"]
pub type USART2RST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USART3RST` reader - USART 3 reset"]
pub type USART3RST_R = crate :: BitReader ; # [doc = "Field `USART3RST` writer - USART 3 reset"]
pub type USART3RST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2C1RST` reader - I2C1 reset"]
pub type I2C1RST_R = crate :: BitReader ; # [doc = "Field `I2C1RST` writer - I2C1 reset"]
pub type I2C1RST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2C2RST` reader - I2C2 reset"]
pub type I2C2RST_R = crate :: BitReader ; # [doc = "Field `I2C2RST` writer - I2C2 reset"]
pub type I2C2RST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USBDRST` reader - USBD reset"]
pub type USBDRST_R = crate :: BitReader ; # [doc = "Field `USBDRST` writer - USBD reset"]
pub type USBDRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CANRST` reader - CAN reset"]
pub type CANRST_R = crate :: BitReader ; # [doc = "Field `CANRST` writer - CAN reset"]
pub type CANRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BKPRST` reader - Backup interface reset"]
pub type BKPRST_R = crate :: BitReader ; # [doc = "Field `BKPRST` writer - Backup interface reset"]
pub type BKPRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PWRRST` reader - Power interface reset"]
pub type PWRRST_R = crate :: BitReader ; # [doc = "Field `PWRRST` writer - Power interface reset"]
pub type PWRRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DACRST` reader - DAC interface reset"]
pub type DACRST_R = crate :: BitReader ; # [doc = "Field `DACRST` writer - DAC interface reset"]
pub type DACRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Timer 2 reset"]
# [inline (always)]
pub fn tim2rst (& self) -> TIM2RST_R { TIM2RST_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Timer 3 reset"]
# [inline (always)]
pub fn tim3rst (& self) -> TIM3RST_R { TIM3RST_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Timer 4 reset"]
# [inline (always)]
pub fn tim4rst (& self) -> TIM4RST_R { TIM4RST_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 11 - Window watchdog reset"]
# [inline (always)]
pub fn wwdgrst (& self) -> WWDGRST_R { WWDGRST_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 14 - SPI2 reset"]
# [inline (always)]
pub fn spi2rst (& self) -> SPI2RST_R { SPI2RST_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 17 - USART 2 reset"]
# [inline (always)]
pub fn usart2rst (& self) -> USART2RST_R { USART2RST_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - USART 3 reset"]
# [inline (always)]
pub fn usart3rst (& self) -> USART3RST_R { USART3RST_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 21 - I2C1 reset"]
# [inline (always)]
pub fn i2c1rst (& self) -> I2C1RST_R { I2C1RST_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - I2C2 reset"]
# [inline (always)]
pub fn i2c2rst (& self) -> I2C2RST_R { I2C2RST_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - USBD reset"]
# [inline (always)]
pub fn usbdrst (& self) -> USBDRST_R { USBDRST_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - CAN reset"]
# [inline (always)]
pub fn canrst (& self) -> CANRST_R { CANRST_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 27 - Backup interface reset"]
# [inline (always)]
pub fn bkprst (& self) -> BKPRST_R { BKPRST_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - Power interface reset"]
# [inline (always)]
pub fn pwrrst (& self) -> PWRRST_R { PWRRST_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DAC interface reset"]
# [inline (always)]
pub fn dacrst (& self) -> DACRST_R { DACRST_R :: new (((self . bits >> 29) & 1) != 0) } } impl W { # [doc = "Bit 0 - Timer 2 reset"]
# [inline (always)]
# [must_use]
pub fn tim2rst (& mut self) -> TIM2RST_W < APB1PRSTR_SPEC > { TIM2RST_W :: new (self , 0) } # [doc = "Bit 1 - Timer 3 reset"]
# [inline (always)]
# [must_use]
pub fn tim3rst (& mut self) -> TIM3RST_W < APB1PRSTR_SPEC > { TIM3RST_W :: new (self , 1) } # [doc = "Bit 2 - Timer 4 reset"]
# [inline (always)]
# [must_use]
pub fn tim4rst (& mut self) -> TIM4RST_W < APB1PRSTR_SPEC > { TIM4RST_W :: new (self , 2) } # [doc = "Bit 11 - Window watchdog reset"]
# [inline (always)]
# [must_use]
pub fn wwdgrst (& mut self) -> WWDGRST_W < APB1PRSTR_SPEC > { WWDGRST_W :: new (self , 11) } # [doc = "Bit 14 - SPI2 reset"]
# [inline (always)]
# [must_use]
pub fn spi2rst (& mut self) -> SPI2RST_W < APB1PRSTR_SPEC > { SPI2RST_W :: new (self , 14) } # [doc = "Bit 17 - USART 2 reset"]
# [inline (always)]
# [must_use]
pub fn usart2rst (& mut self) -> USART2RST_W < APB1PRSTR_SPEC > { USART2RST_W :: new (self , 17) } # [doc = "Bit 18 - USART 3 reset"]
# [inline (always)]
# [must_use]
pub fn usart3rst (& mut self) -> USART3RST_W < APB1PRSTR_SPEC > { USART3RST_W :: new (self , 18) } # [doc = "Bit 21 - I2C1 reset"]
# [inline (always)]
# [must_use]
pub fn i2c1rst (& mut self) -> I2C1RST_W < APB1PRSTR_SPEC > { I2C1RST_W :: new (self , 21) } # [doc = "Bit 22 - I2C2 reset"]
# [inline (always)]
# [must_use]
pub fn i2c2rst (& mut self) -> I2C2RST_W < APB1PRSTR_SPEC > { I2C2RST_W :: new (self , 22) } # [doc = "Bit 23 - USBD reset"]
# [inline (always)]
# [must_use]
pub fn usbdrst (& mut self) -> USBDRST_W < APB1PRSTR_SPEC > { USBDRST_W :: new (self , 23) } # [doc = "Bit 25 - CAN reset"]
# [inline (always)]
# [must_use]
pub fn canrst (& mut self) -> CANRST_W < APB1PRSTR_SPEC > { CANRST_W :: new (self , 25) } # [doc = "Bit 27 - Backup interface reset"]
# [inline (always)]
# [must_use]
pub fn bkprst (& mut self) -> BKPRST_W < APB1PRSTR_SPEC > { BKPRST_W :: new (self , 27) } # [doc = "Bit 28 - Power interface reset"]
# [inline (always)]
# [must_use]
pub fn pwrrst (& mut self) -> PWRRST_W < APB1PRSTR_SPEC > { PWRRST_W :: new (self , 28) } # [doc = "Bit 29 - DAC interface reset"]
# [inline (always)]
# [must_use]
pub fn dacrst (& mut self) -> DACRST_W < APB1PRSTR_SPEC > { DACRST_W :: new (self , 29) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "APB1 peripheral reset register(RCC_APB1PRSTR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb1prstr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apb1prstr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct APB1PRSTR_SPEC ; impl crate :: RegisterSpec for APB1PRSTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1prstr::R`](R) reader structure"]
impl crate :: Readable for APB1PRSTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`apb1prstr::W`](W) writer structure"]
impl crate :: Writable for APB1PRSTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APB1PRSTR to value 0"]
impl crate :: Resettable for APB1PRSTR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "AHBPCENR (rw) register accessor: AHB Peripheral Clock enable register(RCC_AHBPCENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahbpcenr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahbpcenr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahbpcenr`]
module"]
pub type AHBPCENR = crate :: Reg < ahbpcenr :: AHBPCENR_SPEC > ; # [doc = "AHB Peripheral Clock enable register(RCC_AHBPCENR)"]
pub mod ahbpcenr { # [doc = "Register `AHBPCENR` reader"]
pub type R = crate :: R < AHBPCENR_SPEC > ; # [doc = "Register `AHBPCENR` writer"]
pub type W = crate :: W < AHBPCENR_SPEC > ; # [doc = "Field `DMAEN` reader - DMA clock enable"]
pub type DMAEN_R = crate :: BitReader ; # [doc = "Field `DMAEN` writer - DMA clock enable"]
pub type DMAEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SRAMEN` reader - SRAM interface clock enable"]
pub type SRAMEN_R = crate :: BitReader ; # [doc = "Field `SRAMEN` writer - SRAM interface clock enable"]
pub type SRAMEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FLITFEN` reader - FLITF clock enable"]
pub type FLITFEN_R = crate :: BitReader ; # [doc = "Field `FLITFEN` writer - FLITF clock enable"]
pub type FLITFEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CRCEN` reader - CRC clock enable"]
pub type CRCEN_R = crate :: BitReader ; # [doc = "Field `CRCEN` writer - CRC clock enable"]
pub type CRCEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USBHDEN` reader - USBHD clock enable"]
pub type USBHDEN_R = crate :: BitReader ; # [doc = "Field `USBHDEN` writer - USBHD clock enable"]
pub type USBHDEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DMA clock enable"]
# [inline (always)]
pub fn dmaen (& self) -> DMAEN_R { DMAEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - SRAM interface clock enable"]
# [inline (always)]
pub fn sramen (& self) -> SRAMEN_R { SRAMEN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 4 - FLITF clock enable"]
# [inline (always)]
pub fn flitfen (& self) -> FLITFEN_R { FLITFEN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 6 - CRC clock enable"]
# [inline (always)]
pub fn crcen (& self) -> CRCEN_R { CRCEN_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 12 - USBHD clock enable"]
# [inline (always)]
pub fn usbhden (& self) -> USBHDEN_R { USBHDEN_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bit 0 - DMA clock enable"]
# [inline (always)]
# [must_use]
pub fn dmaen (& mut self) -> DMAEN_W < AHBPCENR_SPEC > { DMAEN_W :: new (self , 0) } # [doc = "Bit 2 - SRAM interface clock enable"]
# [inline (always)]
# [must_use]
pub fn sramen (& mut self) -> SRAMEN_W < AHBPCENR_SPEC > { SRAMEN_W :: new (self , 2) } # [doc = "Bit 4 - FLITF clock enable"]
# [inline (always)]
# [must_use]
pub fn flitfen (& mut self) -> FLITFEN_W < AHBPCENR_SPEC > { FLITFEN_W :: new (self , 4) } # [doc = "Bit 6 - CRC clock enable"]
# [inline (always)]
# [must_use]
pub fn crcen (& mut self) -> CRCEN_W < AHBPCENR_SPEC > { CRCEN_W :: new (self , 6) } # [doc = "Bit 12 - USBHD clock enable"]
# [inline (always)]
# [must_use]
pub fn usbhden (& mut self) -> USBHDEN_W < AHBPCENR_SPEC > { USBHDEN_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "AHB Peripheral Clock enable register(RCC_AHBPCENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahbpcenr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahbpcenr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AHBPCENR_SPEC ; impl crate :: RegisterSpec for AHBPCENR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ahbpcenr::R`](R) reader structure"]
impl crate :: Readable for AHBPCENR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ahbpcenr::W`](W) writer structure"]
impl crate :: Writable for AHBPCENR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AHBPCENR to value 0x14"]
impl crate :: Resettable for AHBPCENR_SPEC { const RESET_VALUE : u32 = 0x14 ; } } # [doc = "APB2PCENR (rw) register accessor: APB2 peripheral clock enable register (RCC_APB2PCENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2pcenr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apb2pcenr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2pcenr`]
module"]
pub type APB2PCENR = crate :: Reg < apb2pcenr :: APB2PCENR_SPEC > ; # [doc = "APB2 peripheral clock enable register (RCC_APB2PCENR)"]
pub mod apb2pcenr { # [doc = "Register `APB2PCENR` reader"]
pub type R = crate :: R < APB2PCENR_SPEC > ; # [doc = "Register `APB2PCENR` writer"]
pub type W = crate :: W < APB2PCENR_SPEC > ; # [doc = "Field `AFIOEN` reader - Alternate function I/O clock enable"]
pub type AFIOEN_R = crate :: BitReader ; # [doc = "Field `AFIOEN` writer - Alternate function I/O clock enable"]
pub type AFIOEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IOPAEN` reader - I/O port A clock enable"]
pub type IOPAEN_R = crate :: BitReader ; # [doc = "Field `IOPAEN` writer - I/O port A clock enable"]
pub type IOPAEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IOPBEN` reader - I/O port B clock enable"]
pub type IOPBEN_R = crate :: BitReader ; # [doc = "Field `IOPBEN` writer - I/O port B clock enable"]
pub type IOPBEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IOPCEN` reader - I/O port C clock enable"]
pub type IOPCEN_R = crate :: BitReader ; # [doc = "Field `IOPCEN` writer - I/O port C clock enable"]
pub type IOPCEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IOPDEN` reader - I/O port D clock enable"]
pub type IOPDEN_R = crate :: BitReader ; # [doc = "Field `IOPDEN` writer - I/O port D clock enable"]
pub type IOPDEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADCEN` reader - ADC interface clock enable"]
pub type ADCEN_R = crate :: BitReader ; # [doc = "Field `ADCEN` writer - ADC interface clock enable"]
pub type ADCEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIM1EN` reader - TIM1 Timer clock enable"]
pub type TIM1EN_R = crate :: BitReader ; # [doc = "Field `TIM1EN` writer - TIM1 Timer clock enable"]
pub type TIM1EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPI1EN` reader - SPI 1 clock enable"]
pub type SPI1EN_R = crate :: BitReader ; # [doc = "Field `SPI1EN` writer - SPI 1 clock enable"]
pub type SPI1EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USART1EN` reader - USART1 clock enable"]
pub type USART1EN_R = crate :: BitReader ; # [doc = "Field `USART1EN` writer - USART1 clock enable"]
pub type USART1EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Alternate function I/O clock enable"]
# [inline (always)]
pub fn afioen (& self) -> AFIOEN_R { AFIOEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - I/O port A clock enable"]
# [inline (always)]
pub fn iopaen (& self) -> IOPAEN_R { IOPAEN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - I/O port B clock enable"]
# [inline (always)]
pub fn iopben (& self) -> IOPBEN_R { IOPBEN_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - I/O port C clock enable"]
# [inline (always)]
pub fn iopcen (& self) -> IOPCEN_R { IOPCEN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - I/O port D clock enable"]
# [inline (always)]
pub fn iopden (& self) -> IOPDEN_R { IOPDEN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 9 - ADC interface clock enable"]
# [inline (always)]
pub fn adcen (& self) -> ADCEN_R { ADCEN_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 11 - TIM1 Timer clock enable"]
# [inline (always)]
pub fn tim1en (& self) -> TIM1EN_R { TIM1EN_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - SPI 1 clock enable"]
# [inline (always)]
pub fn spi1en (& self) -> SPI1EN_R { SPI1EN_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 14 - USART1 clock enable"]
# [inline (always)]
pub fn usart1en (& self) -> USART1EN_R { USART1EN_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Alternate function I/O clock enable"]
# [inline (always)]
# [must_use]
pub fn afioen (& mut self) -> AFIOEN_W < APB2PCENR_SPEC > { AFIOEN_W :: new (self , 0) } # [doc = "Bit 2 - I/O port A clock enable"]
# [inline (always)]
# [must_use]
pub fn iopaen (& mut self) -> IOPAEN_W < APB2PCENR_SPEC > { IOPAEN_W :: new (self , 2) } # [doc = "Bit 3 - I/O port B clock enable"]
# [inline (always)]
# [must_use]
pub fn iopben (& mut self) -> IOPBEN_W < APB2PCENR_SPEC > { IOPBEN_W :: new (self , 3) } # [doc = "Bit 4 - I/O port C clock enable"]
# [inline (always)]
# [must_use]
pub fn iopcen (& mut self) -> IOPCEN_W < APB2PCENR_SPEC > { IOPCEN_W :: new (self , 4) } # [doc = "Bit 5 - I/O port D clock enable"]
# [inline (always)]
# [must_use]
pub fn iopden (& mut self) -> IOPDEN_W < APB2PCENR_SPEC > { IOPDEN_W :: new (self , 5) } # [doc = "Bit 9 - ADC interface clock enable"]
# [inline (always)]
# [must_use]
pub fn adcen (& mut self) -> ADCEN_W < APB2PCENR_SPEC > { ADCEN_W :: new (self , 9) } # [doc = "Bit 11 - TIM1 Timer clock enable"]
# [inline (always)]
# [must_use]
pub fn tim1en (& mut self) -> TIM1EN_W < APB2PCENR_SPEC > { TIM1EN_W :: new (self , 11) } # [doc = "Bit 12 - SPI 1 clock enable"]
# [inline (always)]
# [must_use]
pub fn spi1en (& mut self) -> SPI1EN_W < APB2PCENR_SPEC > { SPI1EN_W :: new (self , 12) } # [doc = "Bit 14 - USART1 clock enable"]
# [inline (always)]
# [must_use]
pub fn usart1en (& mut self) -> USART1EN_W < APB2PCENR_SPEC > { USART1EN_W :: new (self , 14) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "APB2 peripheral clock enable register (RCC_APB2PCENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2pcenr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apb2pcenr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct APB2PCENR_SPEC ; impl crate :: RegisterSpec for APB2PCENR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`apb2pcenr::R`](R) reader structure"]
impl crate :: Readable for APB2PCENR_SPEC { } # [doc = "`write(|w| ..)` method takes [`apb2pcenr::W`](W) writer structure"]
impl crate :: Writable for APB2PCENR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APB2PCENR to value 0"]
impl crate :: Resettable for APB2PCENR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "APB1PCENR (rw) register accessor: APB1 peripheral clock enable register (RCC_APB1PCENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb1pcenr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apb1pcenr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb1pcenr`]
module"]
pub type APB1PCENR = crate :: Reg < apb1pcenr :: APB1PCENR_SPEC > ; # [doc = "APB1 peripheral clock enable register (RCC_APB1PCENR)"]
pub mod apb1pcenr { # [doc = "Register `APB1PCENR` reader"]
pub type R = crate :: R < APB1PCENR_SPEC > ; # [doc = "Register `APB1PCENR` writer"]
pub type W = crate :: W < APB1PCENR_SPEC > ; # [doc = "Field `TIM2EN` reader - Timer 2 clock enable"]
pub type TIM2EN_R = crate :: BitReader ; # [doc = "Field `TIM2EN` writer - Timer 2 clock enable"]
pub type TIM2EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIM3EN` reader - Timer 3 clock enable"]
pub type TIM3EN_R = crate :: BitReader ; # [doc = "Field `TIM3EN` writer - Timer 3 clock enable"]
pub type TIM3EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIM4EN` reader - Timer 4 clock enable"]
pub type TIM4EN_R = crate :: BitReader ; # [doc = "Field `TIM4EN` writer - Timer 4 clock enable"]
pub type TIM4EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WWDGEN` reader - Window watchdog clock enable"]
pub type WWDGEN_R = crate :: BitReader ; # [doc = "Field `WWDGEN` writer - Window watchdog clock enable"]
pub type WWDGEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SPI2EN` reader - SPI 2 clock enable"]
pub type SPI2EN_R = crate :: BitReader ; # [doc = "Field `SPI2EN` writer - SPI 2 clock enable"]
pub type SPI2EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USART2EN` reader - USART 2 clock enable"]
pub type USART2EN_R = crate :: BitReader ; # [doc = "Field `USART2EN` writer - USART 2 clock enable"]
pub type USART2EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USART3EN` reader - USART 3 clock enable"]
pub type USART3EN_R = crate :: BitReader ; # [doc = "Field `USART3EN` writer - USART 3 clock enable"]
pub type USART3EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2C1EN` reader - I2C 1 clock enable"]
pub type I2C1EN_R = crate :: BitReader ; # [doc = "Field `I2C1EN` writer - I2C 1 clock enable"]
pub type I2C1EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2C2EN` reader - I2C 2 clock enable"]
pub type I2C2EN_R = crate :: BitReader ; # [doc = "Field `I2C2EN` writer - I2C 2 clock enable"]
pub type I2C2EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USBDEN` reader - USBD clock enable"]
pub type USBDEN_R = crate :: BitReader ; # [doc = "Field `USBDEN` writer - USBD clock enable"]
pub type USBDEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CANEN` reader - CAN clock enable"]
pub type CANEN_R = crate :: BitReader ; # [doc = "Field `CANEN` writer - CAN clock enable"]
pub type CANEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BKPEN` reader - Backup interface clock enable"]
pub type BKPEN_R = crate :: BitReader ; # [doc = "Field `BKPEN` writer - Backup interface clock enable"]
pub type BKPEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PWREN` reader - Power interface clock enable"]
pub type PWREN_R = crate :: BitReader ; # [doc = "Field `PWREN` writer - Power interface clock enable"]
pub type PWREN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DACEN` reader - DAC interface clock enable"]
pub type DACEN_R = crate :: BitReader ; # [doc = "Field `DACEN` writer - DAC interface clock enable"]
pub type DACEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Timer 2 clock enable"]
# [inline (always)]
pub fn tim2en (& self) -> TIM2EN_R { TIM2EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Timer 3 clock enable"]
# [inline (always)]
pub fn tim3en (& self) -> TIM3EN_R { TIM3EN_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Timer 4 clock enable"]
# [inline (always)]
pub fn tim4en (& self) -> TIM4EN_R { TIM4EN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 11 - Window watchdog clock enable"]
# [inline (always)]
pub fn wwdgen (& self) -> WWDGEN_R { WWDGEN_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 14 - SPI 2 clock enable"]
# [inline (always)]
pub fn spi2en (& self) -> SPI2EN_R { SPI2EN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 17 - USART 2 clock enable"]
# [inline (always)]
pub fn usart2en (& self) -> USART2EN_R { USART2EN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - USART 3 clock enable"]
# [inline (always)]
pub fn usart3en (& self) -> USART3EN_R { USART3EN_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 21 - I2C 1 clock enable"]
# [inline (always)]
pub fn i2c1en (& self) -> I2C1EN_R { I2C1EN_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - I2C 2 clock enable"]
# [inline (always)]
pub fn i2c2en (& self) -> I2C2EN_R { I2C2EN_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - USBD clock enable"]
# [inline (always)]
pub fn usbden (& self) -> USBDEN_R { USBDEN_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 25 - CAN clock enable"]
# [inline (always)]
pub fn canen (& self) -> CANEN_R { CANEN_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 27 - Backup interface clock enable"]
# [inline (always)]
pub fn bkpen (& self) -> BKPEN_R { BKPEN_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - Power interface clock enable"]
# [inline (always)]
pub fn pwren (& self) -> PWREN_R { PWREN_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DAC interface clock enable"]
# [inline (always)]
pub fn dacen (& self) -> DACEN_R { DACEN_R :: new (((self . bits >> 29) & 1) != 0) } } impl W { # [doc = "Bit 0 - Timer 2 clock enable"]
# [inline (always)]
# [must_use]
pub fn tim2en (& mut self) -> TIM2EN_W < APB1PCENR_SPEC > { TIM2EN_W :: new (self , 0) } # [doc = "Bit 1 - Timer 3 clock enable"]
# [inline (always)]
# [must_use]
pub fn tim3en (& mut self) -> TIM3EN_W < APB1PCENR_SPEC > { TIM3EN_W :: new (self , 1) } # [doc = "Bit 2 - Timer 4 clock enable"]
# [inline (always)]
# [must_use]
pub fn tim4en (& mut self) -> TIM4EN_W < APB1PCENR_SPEC > { TIM4EN_W :: new (self , 2) } # [doc = "Bit 11 - Window watchdog clock enable"]
# [inline (always)]
# [must_use]
pub fn wwdgen (& mut self) -> WWDGEN_W < APB1PCENR_SPEC > { WWDGEN_W :: new (self , 11) } # [doc = "Bit 14 - SPI 2 clock enable"]
# [inline (always)]
# [must_use]
pub fn spi2en (& mut self) -> SPI2EN_W < APB1PCENR_SPEC > { SPI2EN_W :: new (self , 14) } # [doc = "Bit 17 - USART 2 clock enable"]
# [inline (always)]
# [must_use]
pub fn usart2en (& mut self) -> USART2EN_W < APB1PCENR_SPEC > { USART2EN_W :: new (self , 17) } # [doc = "Bit 18 - USART 3 clock enable"]
# [inline (always)]
# [must_use]
pub fn usart3en (& mut self) -> USART3EN_W < APB1PCENR_SPEC > { USART3EN_W :: new (self , 18) } # [doc = "Bit 21 - I2C 1 clock enable"]
# [inline (always)]
# [must_use]
pub fn i2c1en (& mut self) -> I2C1EN_W < APB1PCENR_SPEC > { I2C1EN_W :: new (self , 21) } # [doc = "Bit 22 - I2C 2 clock enable"]
# [inline (always)]
# [must_use]
pub fn i2c2en (& mut self) -> I2C2EN_W < APB1PCENR_SPEC > { I2C2EN_W :: new (self , 22) } # [doc = "Bit 23 - USBD clock enable"]
# [inline (always)]
# [must_use]
pub fn usbden (& mut self) -> USBDEN_W < APB1PCENR_SPEC > { USBDEN_W :: new (self , 23) } # [doc = "Bit 25 - CAN clock enable"]
# [inline (always)]
# [must_use]
pub fn canen (& mut self) -> CANEN_W < APB1PCENR_SPEC > { CANEN_W :: new (self , 25) } # [doc = "Bit 27 - Backup interface clock enable"]
# [inline (always)]
# [must_use]
pub fn bkpen (& mut self) -> BKPEN_W < APB1PCENR_SPEC > { BKPEN_W :: new (self , 27) } # [doc = "Bit 28 - Power interface clock enable"]
# [inline (always)]
# [must_use]
pub fn pwren (& mut self) -> PWREN_W < APB1PCENR_SPEC > { PWREN_W :: new (self , 28) } # [doc = "Bit 29 - DAC interface clock enable"]
# [inline (always)]
# [must_use]
pub fn dacen (& mut self) -> DACEN_W < APB1PCENR_SPEC > { DACEN_W :: new (self , 29) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "APB1 peripheral clock enable register (RCC_APB1PCENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb1pcenr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apb1pcenr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct APB1PCENR_SPEC ; impl crate :: RegisterSpec for APB1PCENR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`apb1pcenr::R`](R) reader structure"]
impl crate :: Readable for APB1PCENR_SPEC { } # [doc = "`write(|w| ..)` method takes [`apb1pcenr::W`](W) writer structure"]
impl crate :: Writable for APB1PCENR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets APB1PCENR to value 0"]
impl crate :: Resettable for APB1PCENR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "BDCTLR (rw) register accessor: Backup domain control register(RCC_BDCTLR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bdctlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bdctlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bdctlr`]
module"]
pub type BDCTLR = crate :: Reg < bdctlr :: BDCTLR_SPEC > ; # [doc = "Backup domain control register(RCC_BDCTLR)"]
pub mod bdctlr { # [doc = "Register `BDCTLR` reader"]
pub type R = crate :: R < BDCTLR_SPEC > ; # [doc = "Register `BDCTLR` writer"]
pub type W = crate :: W < BDCTLR_SPEC > ; # [doc = "Field `LSEON` reader - External Low Speed oscillator enable"]
pub type LSEON_R = crate :: BitReader ; # [doc = "Field `LSEON` writer - External Low Speed oscillator enable"]
pub type LSEON_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LSERDY` reader - External Low Speed oscillator ready"]
pub type LSERDY_R = crate :: BitReader ; # [doc = "Field `LSEBYP` reader - External Low Speed oscillator bypass"]
pub type LSEBYP_R = crate :: BitReader ; # [doc = "Field `LSEBYP` writer - External Low Speed oscillator bypass"]
pub type LSEBYP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RTCSEL` reader - RTC clock source selection"]
pub type RTCSEL_R = crate :: FieldReader ; # [doc = "Field `RTCSEL` writer - RTC clock source selection"]
pub type RTCSEL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RTCEN` reader - RTC clock enable"]
pub type RTCEN_R = crate :: BitReader ; # [doc = "Field `RTCEN` writer - RTC clock enable"]
pub type RTCEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BDRST` reader - Backup domain software reset"]
pub type BDRST_R = crate :: BitReader ; # [doc = "Field `BDRST` writer - Backup domain software reset"]
pub type BDRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - External Low Speed oscillator enable"]
# [inline (always)]
pub fn lseon (& self) -> LSEON_R { LSEON_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - External Low Speed oscillator ready"]
# [inline (always)]
pub fn lserdy (& self) -> LSERDY_R { LSERDY_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - External Low Speed oscillator bypass"]
# [inline (always)]
pub fn lsebyp (& self) -> LSEBYP_R { LSEBYP_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 8:9 - RTC clock source selection"]
# [inline (always)]
pub fn rtcsel (& self) -> RTCSEL_R { RTCSEL_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 15 - RTC clock enable"]
# [inline (always)]
pub fn rtcen (& self) -> RTCEN_R { RTCEN_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Backup domain software reset"]
# [inline (always)]
pub fn bdrst (& self) -> BDRST_R { BDRST_R :: new (((self . bits >> 16) & 1) != 0) } } impl W { # [doc = "Bit 0 - External Low Speed oscillator enable"]
# [inline (always)]
# [must_use]
pub fn lseon (& mut self) -> LSEON_W < BDCTLR_SPEC > { LSEON_W :: new (self , 0) } # [doc = "Bit 2 - External Low Speed oscillator bypass"]
# [inline (always)]
# [must_use]
pub fn lsebyp (& mut self) -> LSEBYP_W < BDCTLR_SPEC > { LSEBYP_W :: new (self , 2) } # [doc = "Bits 8:9 - RTC clock source selection"]
# [inline (always)]
# [must_use]
pub fn rtcsel (& mut self) -> RTCSEL_W < BDCTLR_SPEC > { RTCSEL_W :: new (self , 8) } # [doc = "Bit 15 - RTC clock enable"]
# [inline (always)]
# [must_use]
pub fn rtcen (& mut self) -> RTCEN_W < BDCTLR_SPEC > { RTCEN_W :: new (self , 15) } # [doc = "Bit 16 - Backup domain software reset"]
# [inline (always)]
# [must_use]
pub fn bdrst (& mut self) -> BDRST_W < BDCTLR_SPEC > { BDRST_W :: new (self , 16) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Backup domain control register(RCC_BDCTLR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bdctlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bdctlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BDCTLR_SPEC ; impl crate :: RegisterSpec for BDCTLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`bdctlr::R`](R) reader structure"]
impl crate :: Readable for BDCTLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`bdctlr::W`](W) writer structure"]
impl crate :: Writable for BDCTLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets BDCTLR to value 0"]
impl crate :: Resettable for BDCTLR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "RSTSCKR (rw) register accessor: Control/status register(RCC_RSTSCKR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstsckr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstsckr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstsckr`]
module"]
pub type RSTSCKR = crate :: Reg < rstsckr :: RSTSCKR_SPEC > ; # [doc = "Control/status register(RCC_RSTSCKR)"]
pub mod rstsckr { # [doc = "Register `RSTSCKR` reader"]
pub type R = crate :: R < RSTSCKR_SPEC > ; # [doc = "Register `RSTSCKR` writer"]
pub type W = crate :: W < RSTSCKR_SPEC > ; # [doc = "Field `LSION` reader - Internal low speed oscillator enable"]
pub type LSION_R = crate :: BitReader ; # [doc = "Field `LSION` writer - Internal low speed oscillator enable"]
pub type LSION_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LSIRDY` reader - Internal low speed oscillator ready"]
pub type LSIRDY_R = crate :: BitReader ; # [doc = "Field `RMVF` reader - Remove reset flag"]
pub type RMVF_R = crate :: BitReader ; # [doc = "Field `RMVF` writer - Remove reset flag"]
pub type RMVF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PINRSTF` reader - PIN reset flag"]
pub type PINRSTF_R = crate :: BitReader ; # [doc = "Field `PINRSTF` writer - PIN reset flag"]
pub type PINRSTF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PORRSTF` reader - POR/PDR reset flag"]
pub type PORRSTF_R = crate :: BitReader ; # [doc = "Field `PORRSTF` writer - POR/PDR reset flag"]
pub type PORRSTF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SFTRSTF` reader - Software reset flag"]
pub type SFTRSTF_R = crate :: BitReader ; # [doc = "Field `SFTRSTF` writer - Software reset flag"]
pub type SFTRSTF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IWDGRSTF` reader - Independent watchdog reset flag"]
pub type IWDGRSTF_R = crate :: BitReader ; # [doc = "Field `IWDGRSTF` writer - Independent watchdog reset flag"]
pub type IWDGRSTF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WWDGRSTF` reader - Window watchdog reset flag"]
pub type WWDGRSTF_R = crate :: BitReader ; # [doc = "Field `WWDGRSTF` writer - Window watchdog reset flag"]
pub type WWDGRSTF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LPWRRSTF` reader - Low-power reset flag"]
pub type LPWRRSTF_R = crate :: BitReader ; # [doc = "Field `LPWRRSTF` writer - Low-power reset flag"]
pub type LPWRRSTF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Internal low speed oscillator enable"]
# [inline (always)]
pub fn lsion (& self) -> LSION_R { LSION_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Internal low speed oscillator ready"]
# [inline (always)]
pub fn lsirdy (& self) -> LSIRDY_R { LSIRDY_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 24 - Remove reset flag"]
# [inline (always)]
pub fn rmvf (& self) -> RMVF_R { RMVF_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 26 - PIN reset flag"]
# [inline (always)]
pub fn pinrstf (& self) -> PINRSTF_R { PINRSTF_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - POR/PDR reset flag"]
# [inline (always)]
pub fn porrstf (& self) -> PORRSTF_R { PORRSTF_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - Software reset flag"]
# [inline (always)]
pub fn sftrstf (& self) -> SFTRSTF_R { SFTRSTF_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - Independent watchdog reset flag"]
# [inline (always)]
pub fn iwdgrstf (& self) -> IWDGRSTF_R { IWDGRSTF_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - Window watchdog reset flag"]
# [inline (always)]
pub fn wwdgrstf (& self) -> WWDGRSTF_R { WWDGRSTF_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - Low-power reset flag"]
# [inline (always)]
pub fn lpwrrstf (& self) -> LPWRRSTF_R { LPWRRSTF_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - Internal low speed oscillator enable"]
# [inline (always)]
# [must_use]
pub fn lsion (& mut self) -> LSION_W < RSTSCKR_SPEC > { LSION_W :: new (self , 0) } # [doc = "Bit 24 - Remove reset flag"]
# [inline (always)]
# [must_use]
pub fn rmvf (& mut self) -> RMVF_W < RSTSCKR_SPEC > { RMVF_W :: new (self , 24) } # [doc = "Bit 26 - PIN reset flag"]
# [inline (always)]
# [must_use]
pub fn pinrstf (& mut self) -> PINRSTF_W < RSTSCKR_SPEC > { PINRSTF_W :: new (self , 26) } # [doc = "Bit 27 - POR/PDR reset flag"]
# [inline (always)]
# [must_use]
pub fn porrstf (& mut self) -> PORRSTF_W < RSTSCKR_SPEC > { PORRSTF_W :: new (self , 27) } # [doc = "Bit 28 - Software reset flag"]
# [inline (always)]
# [must_use]
pub fn sftrstf (& mut self) -> SFTRSTF_W < RSTSCKR_SPEC > { SFTRSTF_W :: new (self , 28) } # [doc = "Bit 29 - Independent watchdog reset flag"]
# [inline (always)]
# [must_use]
pub fn iwdgrstf (& mut self) -> IWDGRSTF_W < RSTSCKR_SPEC > { IWDGRSTF_W :: new (self , 29) } # [doc = "Bit 30 - Window watchdog reset flag"]
# [inline (always)]
# [must_use]
pub fn wwdgrstf (& mut self) -> WWDGRSTF_W < RSTSCKR_SPEC > { WWDGRSTF_W :: new (self , 30) } # [doc = "Bit 31 - Low-power reset flag"]
# [inline (always)]
# [must_use]
pub fn lpwrrstf (& mut self) -> LPWRRSTF_W < RSTSCKR_SPEC > { LPWRRSTF_W :: new (self , 31) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control/status register(RCC_RSTSCKR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstsckr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstsckr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTSCKR_SPEC ; impl crate :: RegisterSpec for RSTSCKR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rstsckr::R`](R) reader structure"]
impl crate :: Readable for RSTSCKR_SPEC { } # [doc = "`write(|w| ..)` method takes [`rstsckr::W`](W) writer structure"]
impl crate :: Writable for RSTSCKR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RSTSCKR to value 0x0c00_0000"]
impl crate :: Resettable for RSTSCKR_SPEC { const RESET_VALUE : u32 = 0x0c00_0000 ; } } # [doc = "AHBRSTR (rw) register accessor: AHB reset register(RCC_APHBRSTR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahbrstr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahbrstr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahbrstr`]
module"]
pub type AHBRSTR = crate :: Reg < ahbrstr :: AHBRSTR_SPEC > ; # [doc = "AHB reset register(RCC_APHBRSTR)"]
pub mod ahbrstr { # [doc = "Register `AHBRSTR` reader"]
pub type R = crate :: R < AHBRSTR_SPEC > ; # [doc = "Register `AHBRSTR` writer"]
pub type W = crate :: W < AHBRSTR_SPEC > ; # [doc = "Field `USBHDRST` reader - USBHD reset"]
pub type USBHDRST_R = crate :: BitReader ; # [doc = "Field `USBHDRST` writer - USBHD reset"]
pub type USBHDRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 12 - USBHD reset"]
# [inline (always)]
pub fn usbhdrst (& self) -> USBHDRST_R { USBHDRST_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bit 12 - USBHD reset"]
# [inline (always)]
# [must_use]
pub fn usbhdrst (& mut self) -> USBHDRST_W < AHBRSTR_SPEC > { USBHDRST_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "AHB reset register(RCC_APHBRSTR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahbrstr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahbrstr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AHBRSTR_SPEC ; impl crate :: RegisterSpec for AHBRSTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ahbrstr::R`](R) reader structure"]
impl crate :: Readable for AHBRSTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ahbrstr::W`](W) writer structure"]
impl crate :: Writable for AHBRSTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets AHBRSTR to value 0"]
impl crate :: Resettable for AHBRSTR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "extension configuration"]
pub struct EXTEND { _marker : PhantomData < * const () > } unsafe impl Send for EXTEND { } impl EXTEND { # [doc = r"Pointer to the register block"]
pub const PTR : * const extend :: RegisterBlock = 0x4002_3800 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const extend :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for EXTEND { type Target = extend :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for EXTEND { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("EXTEND") . finish () } } # [doc = "extension configuration"]
pub mod extend { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { extend_ctr : EXTEND_CTR , } impl RegisterBlock { # [doc = "0x00 - EXTEND register"]
# [inline (always)]
pub const fn extend_ctr (& self) -> & EXTEND_CTR { & self . extend_ctr } } # [doc = "EXTEND_CTR (rw) register accessor: EXTEND register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extend_ctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`extend_ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@extend_ctr`]
module"]
pub type EXTEND_CTR = crate :: Reg < extend_ctr :: EXTEND_CTR_SPEC > ; # [doc = "EXTEND register"]
pub mod extend_ctr { # [doc = "Register `EXTEND_CTR` reader"]
pub type R = crate :: R < EXTEND_CTR_SPEC > ; # [doc = "Register `EXTEND_CTR` writer"]
pub type W = crate :: W < EXTEND_CTR_SPEC > ; # [doc = "Field `USBDLS` reader - USBD Lowspeed Enable"]
pub type USBDLS_R = crate :: BitReader ; # [doc = "Field `USBDLS` writer - USBD Lowspeed Enable"]
pub type USBDLS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USBDPU` reader - USBD pullup Enable"]
pub type USBDPU_R = crate :: BitReader ; # [doc = "Field `USBDPU` writer - USBD pullup Enable"]
pub type USBDPU_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USBHDIO` reader - USBHD IO(PB6/PB7) Enable"]
pub type USBHDIO_R = crate :: BitReader ; # [doc = "Field `USBHDIO` writer - USBHD IO(PB6/PB7) Enable"]
pub type USBHDIO_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USB5VSEL` reader - USB 5V Enable"]
pub type USB5VSEL_R = crate :: BitReader ; # [doc = "Field `USB5VSEL` writer - USB 5V Enable"]
pub type USB5VSEL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HSIPRE` reader - Whether HSI is divided"]
pub type HSIPRE_R = crate :: BitReader ; # [doc = "Field `HSIPRE` writer - Whether HSI is divided"]
pub type HSIPRE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LKUPEN` reader - LOCKUP"]
pub type LKUPEN_R = crate :: BitReader ; # [doc = "Field `LKUPEN` writer - LOCKUP"]
pub type LKUPEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LKUPRESET` reader - LOCKUP RESET"]
pub type LKUPRESET_R = crate :: BitReader ; # [doc = "Field `LKUPRESET` writer - LOCKUP RESET"]
pub type LKUPRESET_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ULLDOTRIM` reader - ULLDOTRIM"]
pub type ULLDOTRIM_R = crate :: FieldReader ; # [doc = "Field `ULLDOTRIM` writer - ULLDOTRIM"]
pub type ULLDOTRIM_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `LDOTRIM` reader - LDOTRIM"]
pub type LDOTRIM_R = crate :: BitReader ; # [doc = "Field `LDOTRIM` writer - LDOTRIM"]
pub type LDOTRIM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - USBD Lowspeed Enable"]
# [inline (always)]
pub fn usbdls (& self) -> USBDLS_R { USBDLS_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - USBD pullup Enable"]
# [inline (always)]
pub fn usbdpu (& self) -> USBDPU_R { USBDPU_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - USBHD IO(PB6/PB7) Enable"]
# [inline (always)]
pub fn usbhdio (& self) -> USBHDIO_R { USBHDIO_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - USB 5V Enable"]
# [inline (always)]
pub fn usb5vsel (& self) -> USB5VSEL_R { USB5VSEL_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Whether HSI is divided"]
# [inline (always)]
pub fn hsipre (& self) -> HSIPRE_R { HSIPRE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 6 - LOCKUP"]
# [inline (always)]
pub fn lkupen (& self) -> LKUPEN_R { LKUPEN_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - LOCKUP RESET"]
# [inline (always)]
pub fn lkupreset (& self) -> LKUPRESET_R { LKUPRESET_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - ULLDOTRIM"]
# [inline (always)]
pub fn ulldotrim (& self) -> ULLDOTRIM_R { ULLDOTRIM_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 10 - LDOTRIM"]
# [inline (always)]
pub fn ldotrim (& self) -> LDOTRIM_R { LDOTRIM_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - USBD Lowspeed Enable"]
# [inline (always)]
# [must_use]
pub fn usbdls (& mut self) -> USBDLS_W < EXTEND_CTR_SPEC > { USBDLS_W :: new (self , 0) } # [doc = "Bit 1 - USBD pullup Enable"]
# [inline (always)]
# [must_use]
pub fn usbdpu (& mut self) -> USBDPU_W < EXTEND_CTR_SPEC > { USBDPU_W :: new (self , 1) } # [doc = "Bit 2 - USBHD IO(PB6/PB7) Enable"]
# [inline (always)]
# [must_use]
pub fn usbhdio (& mut self) -> USBHDIO_W < EXTEND_CTR_SPEC > { USBHDIO_W :: new (self , 2) } # [doc = "Bit 3 - USB 5V Enable"]
# [inline (always)]
# [must_use]
pub fn usb5vsel (& mut self) -> USB5VSEL_W < EXTEND_CTR_SPEC > { USB5VSEL_W :: new (self , 3) } # [doc = "Bit 4 - Whether HSI is divided"]
# [inline (always)]
# [must_use]
pub fn hsipre (& mut self) -> HSIPRE_W < EXTEND_CTR_SPEC > { HSIPRE_W :: new (self , 4) } # [doc = "Bit 6 - LOCKUP"]
# [inline (always)]
# [must_use]
pub fn lkupen (& mut self) -> LKUPEN_W < EXTEND_CTR_SPEC > { LKUPEN_W :: new (self , 6) } # [doc = "Bit 7 - LOCKUP RESET"]
# [inline (always)]
# [must_use]
pub fn lkupreset (& mut self) -> LKUPRESET_W < EXTEND_CTR_SPEC > { LKUPRESET_W :: new (self , 7) } # [doc = "Bits 8:9 - ULLDOTRIM"]
# [inline (always)]
# [must_use]
pub fn ulldotrim (& mut self) -> ULLDOTRIM_W < EXTEND_CTR_SPEC > { ULLDOTRIM_W :: new (self , 8) } # [doc = "Bit 10 - LDOTRIM"]
# [inline (always)]
# [must_use]
pub fn ldotrim (& mut self) -> LDOTRIM_W < EXTEND_CTR_SPEC > { LDOTRIM_W :: new (self , 10) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "EXTEND register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extend_ctr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`extend_ctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EXTEND_CTR_SPEC ; impl crate :: RegisterSpec for EXTEND_CTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`extend_ctr::R`](R) reader structure"]
impl crate :: Readable for EXTEND_CTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`extend_ctr::W`](W) writer structure"]
impl crate :: Writable for EXTEND_CTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EXTEND_CTR to value 0x20"]
impl crate :: Resettable for EXTEND_CTR_SPEC { const RESET_VALUE : u32 = 0x20 ; } } } # [doc = "General purpose I/O"]
pub struct GPIOA { _marker : PhantomData < * const () > } unsafe impl Send for GPIOA { } impl GPIOA { # [doc = r"Pointer to the register block"]
pub const PTR : * const gpioa :: RegisterBlock = 0x4001_0800 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const gpioa :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for GPIOA { type Target = gpioa :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for GPIOA { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("GPIOA") . finish () } } # [doc = "General purpose I/O"]
pub mod gpioa { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { cfglr : CFGLR , cfghr : CFGHR , indr : INDR , outdr : OUTDR , bshr : BSHR , bcr : BCR , lckr : LCKR , } impl RegisterBlock { # [doc = "0x00 - Port configuration register low(GPIOn_CFGLR)"]
# [inline (always)]
pub const fn cfglr (& self) -> & CFGLR { & self . cfglr } # [doc = "0x04 - Port configuration register high (GPIOn_CFGHR)"]
# [inline (always)]
pub const fn cfghr (& self) -> & CFGHR { & self . cfghr } # [doc = "0x08 - Port input data register (GPIOn_INDR)"]
# [inline (always)]
pub const fn indr (& self) -> & INDR { & self . indr } # [doc = "0x0c - Port output data register (GPIOn_OUTDR)"]
# [inline (always)]
pub const fn outdr (& self) -> & OUTDR { & self . outdr } # [doc = "0x10 - Port bit set/reset register (GPIOn_BSHR)"]
# [inline (always)]
pub const fn bshr (& self) -> & BSHR { & self . bshr } # [doc = "0x14 - Port bit reset register (GPIOn_BCR)"]
# [inline (always)]
pub const fn bcr (& self) -> & BCR { & self . bcr } # [doc = "0x18 - Port configuration lock register"]
# [inline (always)]
pub const fn lckr (& self) -> & LCKR { & self . lckr } } # [doc = "CFGLR (rw) register accessor: Port configuration register low(GPIOn_CFGLR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfglr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfglr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfglr`]
module"]
pub type CFGLR = crate :: Reg < cfglr :: CFGLR_SPEC > ; # [doc = "Port configuration register low(GPIOn_CFGLR)"]
pub mod cfglr { # [doc = "Register `CFGLR` reader"]
pub type R = crate :: R < CFGLR_SPEC > ; # [doc = "Register `CFGLR` writer"]
pub type W = crate :: W < CFGLR_SPEC > ; # [doc = "Field `MODE0` reader - Port n.0 mode bits"]
pub type MODE0_R = crate :: FieldReader ; # [doc = "Field `MODE0` writer - Port n.0 mode bits"]
pub type MODE0_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF0` reader - Port n.0 configuration bits"]
pub type CNF0_R = crate :: FieldReader ; # [doc = "Field `CNF0` writer - Port n.0 configuration bits"]
pub type CNF0_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE1` reader - Port n.1 mode bits"]
pub type MODE1_R = crate :: FieldReader ; # [doc = "Field `MODE1` writer - Port n.1 mode bits"]
pub type MODE1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF1` reader - Port n.1 configuration bits"]
pub type CNF1_R = crate :: FieldReader ; # [doc = "Field `CNF1` writer - Port n.1 configuration bits"]
pub type CNF1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE2` reader - Port n.2 mode bits"]
pub type MODE2_R = crate :: FieldReader ; # [doc = "Field `MODE2` writer - Port n.2 mode bits"]
pub type MODE2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF2` reader - Port n.2 configuration bits"]
pub type CNF2_R = crate :: FieldReader ; # [doc = "Field `CNF2` writer - Port n.2 configuration bits"]
pub type CNF2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE3` reader - Port n.3 mode bits"]
pub type MODE3_R = crate :: FieldReader ; # [doc = "Field `MODE3` writer - Port n.3 mode bits"]
pub type MODE3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF3` reader - Port n.3 configuration bits"]
pub type CNF3_R = crate :: FieldReader ; # [doc = "Field `CNF3` writer - Port n.3 configuration bits"]
pub type CNF3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE4` reader - Port n.4 mode bits"]
pub type MODE4_R = crate :: FieldReader ; # [doc = "Field `MODE4` writer - Port n.4 mode bits"]
pub type MODE4_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF4` reader - Port n.4 configuration bits"]
pub type CNF4_R = crate :: FieldReader ; # [doc = "Field `CNF4` writer - Port n.4 configuration bits"]
pub type CNF4_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE5` reader - Port n.5 mode bits"]
pub type MODE5_R = crate :: FieldReader ; # [doc = "Field `MODE5` writer - Port n.5 mode bits"]
pub type MODE5_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF5` reader - Port n.5 configuration bits"]
pub type CNF5_R = crate :: FieldReader ; # [doc = "Field `CNF5` writer - Port n.5 configuration bits"]
pub type CNF5_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE6` reader - Port n.6 mode bits"]
pub type MODE6_R = crate :: FieldReader ; # [doc = "Field `MODE6` writer - Port n.6 mode bits"]
pub type MODE6_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF6` reader - Port n.6 configuration bits"]
pub type CNF6_R = crate :: FieldReader ; # [doc = "Field `CNF6` writer - Port n.6 configuration bits"]
pub type CNF6_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE7` reader - Port n.7 mode bits"]
pub type MODE7_R = crate :: FieldReader ; # [doc = "Field `MODE7` writer - Port n.7 mode bits"]
pub type MODE7_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF7` reader - Port n.7 configuration bits"]
pub type CNF7_R = crate :: FieldReader ; # [doc = "Field `CNF7` writer - Port n.7 configuration bits"]
pub type CNF7_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Port n.0 mode bits"]
# [inline (always)]
pub fn mode0 (& self) -> MODE0_R { MODE0_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Port n.0 configuration bits"]
# [inline (always)]
pub fn cnf0 (& self) -> CNF0_R { CNF0_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Port n.1 mode bits"]
# [inline (always)]
pub fn mode1 (& self) -> MODE1_R { MODE1_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 6:7 - Port n.1 configuration bits"]
# [inline (always)]
pub fn cnf1 (& self) -> CNF1_R { CNF1_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:9 - Port n.2 mode bits"]
# [inline (always)]
pub fn mode2 (& self) -> MODE2_R { MODE2_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Port n.2 configuration bits"]
# [inline (always)]
pub fn cnf2 (& self) -> CNF2_R { CNF2_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - Port n.3 mode bits"]
# [inline (always)]
pub fn mode3 (& self) -> MODE3_R { MODE3_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 14:15 - Port n.3 configuration bits"]
# [inline (always)]
pub fn cnf3 (& self) -> CNF3_R { CNF3_R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:17 - Port n.4 mode bits"]
# [inline (always)]
pub fn mode4 (& self) -> MODE4_R { MODE4_R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bits 18:19 - Port n.4 configuration bits"]
# [inline (always)]
pub fn cnf4 (& self) -> CNF4_R { CNF4_R :: new (((self . bits >> 18) & 3) as u8) } # [doc = "Bits 20:21 - Port n.5 mode bits"]
# [inline (always)]
pub fn mode5 (& self) -> MODE5_R { MODE5_R :: new (((self . bits >> 20) & 3) as u8) } # [doc = "Bits 22:23 - Port n.5 configuration bits"]
# [inline (always)]
pub fn cnf5 (& self) -> CNF5_R { CNF5_R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bits 24:25 - Port n.6 mode bits"]
# [inline (always)]
pub fn mode6 (& self) -> MODE6_R { MODE6_R :: new (((self . bits >> 24) & 3) as u8) } # [doc = "Bits 26:27 - Port n.6 configuration bits"]
# [inline (always)]
pub fn cnf6 (& self) -> CNF6_R { CNF6_R :: new (((self . bits >> 26) & 3) as u8) } # [doc = "Bits 28:29 - Port n.7 mode bits"]
# [inline (always)]
pub fn mode7 (& self) -> MODE7_R { MODE7_R :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - Port n.7 configuration bits"]
# [inline (always)]
pub fn cnf7 (& self) -> CNF7_R { CNF7_R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Port n.0 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode0 (& mut self) -> MODE0_W < CFGLR_SPEC > { MODE0_W :: new (self , 0) } # [doc = "Bits 2:3 - Port n.0 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf0 (& mut self) -> CNF0_W < CFGLR_SPEC > { CNF0_W :: new (self , 2) } # [doc = "Bits 4:5 - Port n.1 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode1 (& mut self) -> MODE1_W < CFGLR_SPEC > { MODE1_W :: new (self , 4) } # [doc = "Bits 6:7 - Port n.1 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf1 (& mut self) -> CNF1_W < CFGLR_SPEC > { CNF1_W :: new (self , 6) } # [doc = "Bits 8:9 - Port n.2 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode2 (& mut self) -> MODE2_W < CFGLR_SPEC > { MODE2_W :: new (self , 8) } # [doc = "Bits 10:11 - Port n.2 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf2 (& mut self) -> CNF2_W < CFGLR_SPEC > { CNF2_W :: new (self , 10) } # [doc = "Bits 12:13 - Port n.3 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode3 (& mut self) -> MODE3_W < CFGLR_SPEC > { MODE3_W :: new (self , 12) } # [doc = "Bits 14:15 - Port n.3 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf3 (& mut self) -> CNF3_W < CFGLR_SPEC > { CNF3_W :: new (self , 14) } # [doc = "Bits 16:17 - Port n.4 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode4 (& mut self) -> MODE4_W < CFGLR_SPEC > { MODE4_W :: new (self , 16) } # [doc = "Bits 18:19 - Port n.4 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf4 (& mut self) -> CNF4_W < CFGLR_SPEC > { CNF4_W :: new (self , 18) } # [doc = "Bits 20:21 - Port n.5 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode5 (& mut self) -> MODE5_W < CFGLR_SPEC > { MODE5_W :: new (self , 20) } # [doc = "Bits 22:23 - Port n.5 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf5 (& mut self) -> CNF5_W < CFGLR_SPEC > { CNF5_W :: new (self , 22) } # [doc = "Bits 24:25 - Port n.6 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode6 (& mut self) -> MODE6_W < CFGLR_SPEC > { MODE6_W :: new (self , 24) } # [doc = "Bits 26:27 - Port n.6 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf6 (& mut self) -> CNF6_W < CFGLR_SPEC > { CNF6_W :: new (self , 26) } # [doc = "Bits 28:29 - Port n.7 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode7 (& mut self) -> MODE7_W < CFGLR_SPEC > { MODE7_W :: new (self , 28) } # [doc = "Bits 30:31 - Port n.7 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf7 (& mut self) -> CNF7_W < CFGLR_SPEC > { CNF7_W :: new (self , 30) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Port configuration register low(GPIOn_CFGLR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfglr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfglr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGLR_SPEC ; impl crate :: RegisterSpec for CFGLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfglr::R`](R) reader structure"]
impl crate :: Readable for CFGLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfglr::W`](W) writer structure"]
impl crate :: Writable for CFGLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFGLR to value 0x4444_4444"]
impl crate :: Resettable for CFGLR_SPEC { const RESET_VALUE : u32 = 0x4444_4444 ; } } # [doc = "CFGHR (rw) register accessor: Port configuration register high (GPIOn_CFGHR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfghr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfghr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfghr`]
module"]
pub type CFGHR = crate :: Reg < cfghr :: CFGHR_SPEC > ; # [doc = "Port configuration register high (GPIOn_CFGHR)"]
pub mod cfghr { # [doc = "Register `CFGHR` reader"]
pub type R = crate :: R < CFGHR_SPEC > ; # [doc = "Register `CFGHR` writer"]
pub type W = crate :: W < CFGHR_SPEC > ; # [doc = "Field `MODE8` reader - Port n.8 mode bits"]
pub type MODE8_R = crate :: FieldReader ; # [doc = "Field `MODE8` writer - Port n.8 mode bits"]
pub type MODE8_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF8` reader - Port n.8 configuration bits"]
pub type CNF8_R = crate :: FieldReader ; # [doc = "Field `CNF8` writer - Port n.8 configuration bits"]
pub type CNF8_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE9` reader - Port n.9 mode bits"]
pub type MODE9_R = crate :: FieldReader ; # [doc = "Field `MODE9` writer - Port n.9 mode bits"]
pub type MODE9_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF9` reader - Port n.9 configuration bits"]
pub type CNF9_R = crate :: FieldReader ; # [doc = "Field `CNF9` writer - Port n.9 configuration bits"]
pub type CNF9_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE10` reader - Port n.10 mode bits"]
pub type MODE10_R = crate :: FieldReader ; # [doc = "Field `MODE10` writer - Port n.10 mode bits"]
pub type MODE10_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF10` reader - Port n.10 configuration bits"]
pub type CNF10_R = crate :: FieldReader ; # [doc = "Field `CNF10` writer - Port n.10 configuration bits"]
pub type CNF10_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE11` reader - Port n.11 mode bits"]
pub type MODE11_R = crate :: FieldReader ; # [doc = "Field `MODE11` writer - Port n.11 mode bits"]
pub type MODE11_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF11` reader - Port n.11 configuration bits"]
pub type CNF11_R = crate :: FieldReader ; # [doc = "Field `CNF11` writer - Port n.11 configuration bits"]
pub type CNF11_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE12` reader - Port n.12 mode bits"]
pub type MODE12_R = crate :: FieldReader ; # [doc = "Field `MODE12` writer - Port n.12 mode bits"]
pub type MODE12_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF12` reader - Port n.12 configuration bits"]
pub type CNF12_R = crate :: FieldReader ; # [doc = "Field `CNF12` writer - Port n.12 configuration bits"]
pub type CNF12_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE13` reader - Port n.13 mode bits"]
pub type MODE13_R = crate :: FieldReader ; # [doc = "Field `MODE13` writer - Port n.13 mode bits"]
pub type MODE13_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF13` reader - Port n.13 configuration bits"]
pub type CNF13_R = crate :: FieldReader ; # [doc = "Field `CNF13` writer - Port n.13 configuration bits"]
pub type CNF13_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE14` reader - Port n.14 mode bits"]
pub type MODE14_R = crate :: FieldReader ; # [doc = "Field `MODE14` writer - Port n.14 mode bits"]
pub type MODE14_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF14` reader - Port n.14 configuration bits"]
pub type CNF14_R = crate :: FieldReader ; # [doc = "Field `CNF14` writer - Port n.14 configuration bits"]
pub type CNF14_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MODE15` reader - Port n.15 mode bits"]
pub type MODE15_R = crate :: FieldReader ; # [doc = "Field `MODE15` writer - Port n.15 mode bits"]
pub type MODE15_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CNF15` reader - Port n.15 configuration bits"]
pub type CNF15_R = crate :: FieldReader ; # [doc = "Field `CNF15` writer - Port n.15 configuration bits"]
pub type CNF15_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:1 - Port n.8 mode bits"]
# [inline (always)]
pub fn mode8 (& self) -> MODE8_R { MODE8_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Port n.8 configuration bits"]
# [inline (always)]
pub fn cnf8 (& self) -> CNF8_R { CNF8_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Port n.9 mode bits"]
# [inline (always)]
pub fn mode9 (& self) -> MODE9_R { MODE9_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 6:7 - Port n.9 configuration bits"]
# [inline (always)]
pub fn cnf9 (& self) -> CNF9_R { CNF9_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:9 - Port n.10 mode bits"]
# [inline (always)]
pub fn mode10 (& self) -> MODE10_R { MODE10_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Port n.10 configuration bits"]
# [inline (always)]
pub fn cnf10 (& self) -> CNF10_R { CNF10_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - Port n.11 mode bits"]
# [inline (always)]
pub fn mode11 (& self) -> MODE11_R { MODE11_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 14:15 - Port n.11 configuration bits"]
# [inline (always)]
pub fn cnf11 (& self) -> CNF11_R { CNF11_R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:17 - Port n.12 mode bits"]
# [inline (always)]
pub fn mode12 (& self) -> MODE12_R { MODE12_R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bits 18:19 - Port n.12 configuration bits"]
# [inline (always)]
pub fn cnf12 (& self) -> CNF12_R { CNF12_R :: new (((self . bits >> 18) & 3) as u8) } # [doc = "Bits 20:21 - Port n.13 mode bits"]
# [inline (always)]
pub fn mode13 (& self) -> MODE13_R { MODE13_R :: new (((self . bits >> 20) & 3) as u8) } # [doc = "Bits 22:23 - Port n.13 configuration bits"]
# [inline (always)]
pub fn cnf13 (& self) -> CNF13_R { CNF13_R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bits 24:25 - Port n.14 mode bits"]
# [inline (always)]
pub fn mode14 (& self) -> MODE14_R { MODE14_R :: new (((self . bits >> 24) & 3) as u8) } # [doc = "Bits 26:27 - Port n.14 configuration bits"]
# [inline (always)]
pub fn cnf14 (& self) -> CNF14_R { CNF14_R :: new (((self . bits >> 26) & 3) as u8) } # [doc = "Bits 28:29 - Port n.15 mode bits"]
# [inline (always)]
pub fn mode15 (& self) -> MODE15_R { MODE15_R :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - Port n.15 configuration bits"]
# [inline (always)]
pub fn cnf15 (& self) -> CNF15_R { CNF15_R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Port n.8 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode8 (& mut self) -> MODE8_W < CFGHR_SPEC > { MODE8_W :: new (self , 0) } # [doc = "Bits 2:3 - Port n.8 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf8 (& mut self) -> CNF8_W < CFGHR_SPEC > { CNF8_W :: new (self , 2) } # [doc = "Bits 4:5 - Port n.9 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode9 (& mut self) -> MODE9_W < CFGHR_SPEC > { MODE9_W :: new (self , 4) } # [doc = "Bits 6:7 - Port n.9 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf9 (& mut self) -> CNF9_W < CFGHR_SPEC > { CNF9_W :: new (self , 6) } # [doc = "Bits 8:9 - Port n.10 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode10 (& mut self) -> MODE10_W < CFGHR_SPEC > { MODE10_W :: new (self , 8) } # [doc = "Bits 10:11 - Port n.10 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf10 (& mut self) -> CNF10_W < CFGHR_SPEC > { CNF10_W :: new (self , 10) } # [doc = "Bits 12:13 - Port n.11 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode11 (& mut self) -> MODE11_W < CFGHR_SPEC > { MODE11_W :: new (self , 12) } # [doc = "Bits 14:15 - Port n.11 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf11 (& mut self) -> CNF11_W < CFGHR_SPEC > { CNF11_W :: new (self , 14) } # [doc = "Bits 16:17 - Port n.12 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode12 (& mut self) -> MODE12_W < CFGHR_SPEC > { MODE12_W :: new (self , 16) } # [doc = "Bits 18:19 - Port n.12 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf12 (& mut self) -> CNF12_W < CFGHR_SPEC > { CNF12_W :: new (self , 18) } # [doc = "Bits 20:21 - Port n.13 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode13 (& mut self) -> MODE13_W < CFGHR_SPEC > { MODE13_W :: new (self , 20) } # [doc = "Bits 22:23 - Port n.13 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf13 (& mut self) -> CNF13_W < CFGHR_SPEC > { CNF13_W :: new (self , 22) } # [doc = "Bits 24:25 - Port n.14 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode14 (& mut self) -> MODE14_W < CFGHR_SPEC > { MODE14_W :: new (self , 24) } # [doc = "Bits 26:27 - Port n.14 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf14 (& mut self) -> CNF14_W < CFGHR_SPEC > { CNF14_W :: new (self , 26) } # [doc = "Bits 28:29 - Port n.15 mode bits"]
# [inline (always)]
# [must_use]
pub fn mode15 (& mut self) -> MODE15_W < CFGHR_SPEC > { MODE15_W :: new (self , 28) } # [doc = "Bits 30:31 - Port n.15 configuration bits"]
# [inline (always)]
# [must_use]
pub fn cnf15 (& mut self) -> CNF15_W < CFGHR_SPEC > { CNF15_W :: new (self , 30) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Port configuration register high (GPIOn_CFGHR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfghr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfghr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGHR_SPEC ; impl crate :: RegisterSpec for CFGHR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfghr::R`](R) reader structure"]
impl crate :: Readable for CFGHR_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfghr::W`](W) writer structure"]
impl crate :: Writable for CFGHR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFGHR to value 0x4444_4444"]
impl crate :: Resettable for CFGHR_SPEC { const RESET_VALUE : u32 = 0x4444_4444 ; } } # [doc = "INDR (r) register accessor: Port input data register (GPIOn_INDR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@indr`]
module"]
pub type INDR = crate :: Reg < indr :: INDR_SPEC > ; # [doc = "Port input data register (GPIOn_INDR)"]
pub mod indr { # [doc = "Register `INDR` reader"]
pub type R = crate :: R < INDR_SPEC > ; # [doc = "Field `IDR0` reader - Port input data"]
pub type IDR0_R = crate :: BitReader ; # [doc = "Field `IDR1` reader - Port input data"]
pub type IDR1_R = crate :: BitReader ; # [doc = "Field `IDR2` reader - Port input data"]
pub type IDR2_R = crate :: BitReader ; # [doc = "Field `IDR3` reader - Port input data"]
pub type IDR3_R = crate :: BitReader ; # [doc = "Field `IDR4` reader - Port input data"]
pub type IDR4_R = crate :: BitReader ; # [doc = "Field `IDR5` reader - Port input data"]
pub type IDR5_R = crate :: BitReader ; # [doc = "Field `IDR6` reader - Port input data"]
pub type IDR6_R = crate :: BitReader ; # [doc = "Field `IDR7` reader - Port input data"]
pub type IDR7_R = crate :: BitReader ; # [doc = "Field `IDR8` reader - Port input data"]
pub type IDR8_R = crate :: BitReader ; # [doc = "Field `IDR9` reader - Port input data"]
pub type IDR9_R = crate :: BitReader ; # [doc = "Field `IDR10` reader - Port input data"]
pub type IDR10_R = crate :: BitReader ; # [doc = "Field `IDR11` reader - Port input data"]
pub type IDR11_R = crate :: BitReader ; # [doc = "Field `IDR12` reader - Port input data"]
pub type IDR12_R = crate :: BitReader ; # [doc = "Field `IDR13` reader - Port input data"]
pub type IDR13_R = crate :: BitReader ; # [doc = "Field `IDR14` reader - Port input data"]
pub type IDR14_R = crate :: BitReader ; # [doc = "Field `IDR15` reader - Port input data"]
pub type IDR15_R = crate :: BitReader ; impl R { # [doc = "Bit 0 - Port input data"]
# [inline (always)]
pub fn idr0 (& self) -> IDR0_R { IDR0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Port input data"]
# [inline (always)]
pub fn idr1 (& self) -> IDR1_R { IDR1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Port input data"]
# [inline (always)]
pub fn idr2 (& self) -> IDR2_R { IDR2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Port input data"]
# [inline (always)]
pub fn idr3 (& self) -> IDR3_R { IDR3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Port input data"]
# [inline (always)]
pub fn idr4 (& self) -> IDR4_R { IDR4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Port input data"]
# [inline (always)]
pub fn idr5 (& self) -> IDR5_R { IDR5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Port input data"]
# [inline (always)]
pub fn idr6 (& self) -> IDR6_R { IDR6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Port input data"]
# [inline (always)]
pub fn idr7 (& self) -> IDR7_R { IDR7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Port input data"]
# [inline (always)]
pub fn idr8 (& self) -> IDR8_R { IDR8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Port input data"]
# [inline (always)]
pub fn idr9 (& self) -> IDR9_R { IDR9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Port input data"]
# [inline (always)]
pub fn idr10 (& self) -> IDR10_R { IDR10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Port input data"]
# [inline (always)]
pub fn idr11 (& self) -> IDR11_R { IDR11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Port input data"]
# [inline (always)]
pub fn idr12 (& self) -> IDR12_R { IDR12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Port input data"]
# [inline (always)]
pub fn idr13 (& self) -> IDR13_R { IDR13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Port input data"]
# [inline (always)]
pub fn idr14 (& self) -> IDR14_R { IDR14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Port input data"]
# [inline (always)]
pub fn idr15 (& self) -> IDR15_R { IDR15_R :: new (((self . bits >> 15) & 1) != 0) } } # [doc = "Port input data register (GPIOn_INDR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`indr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INDR_SPEC ; impl crate :: RegisterSpec for INDR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`indr::R`](R) reader structure"]
impl crate :: Readable for INDR_SPEC { } # [doc = "`reset()` method sets INDR to value 0"]
impl crate :: Resettable for INDR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "OUTDR (rw) register accessor: Port output data register (GPIOn_OUTDR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outdr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`outdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outdr`]
module"]
pub type OUTDR = crate :: Reg < outdr :: OUTDR_SPEC > ; # [doc = "Port output data register (GPIOn_OUTDR)"]
pub mod outdr { # [doc = "Register `OUTDR` reader"]
pub type R = crate :: R < OUTDR_SPEC > ; # [doc = "Register `OUTDR` writer"]
pub type W = crate :: W < OUTDR_SPEC > ; # [doc = "Field `ODR0` reader - Port output data"]
pub type ODR0_R = crate :: BitReader ; # [doc = "Field `ODR0` writer - Port output data"]
pub type ODR0_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR1` reader - Port output data"]
pub type ODR1_R = crate :: BitReader ; # [doc = "Field `ODR1` writer - Port output data"]
pub type ODR1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR2` reader - Port output data"]
pub type ODR2_R = crate :: BitReader ; # [doc = "Field `ODR2` writer - Port output data"]
pub type ODR2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR3` reader - Port output data"]
pub type ODR3_R = crate :: BitReader ; # [doc = "Field `ODR3` writer - Port output data"]
pub type ODR3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR4` reader - Port output data"]
pub type ODR4_R = crate :: BitReader ; # [doc = "Field `ODR4` writer - Port output data"]
pub type ODR4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR5` reader - Port output data"]
pub type ODR5_R = crate :: BitReader ; # [doc = "Field `ODR5` writer - Port output data"]
pub type ODR5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR6` reader - Port output data"]
pub type ODR6_R = crate :: BitReader ; # [doc = "Field `ODR6` writer - Port output data"]
pub type ODR6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR7` reader - Port output data"]
pub type ODR7_R = crate :: BitReader ; # [doc = "Field `ODR7` writer - Port output data"]
pub type ODR7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR8` reader - Port output data"]
pub type ODR8_R = crate :: BitReader ; # [doc = "Field `ODR8` writer - Port output data"]
pub type ODR8_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR9` reader - Port output data"]
pub type ODR9_R = crate :: BitReader ; # [doc = "Field `ODR9` writer - Port output data"]
pub type ODR9_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR10` reader - Port output data"]
pub type ODR10_R = crate :: BitReader ; # [doc = "Field `ODR10` writer - Port output data"]
pub type ODR10_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR11` reader - Port output data"]
pub type ODR11_R = crate :: BitReader ; # [doc = "Field `ODR11` writer - Port output data"]
pub type ODR11_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR12` reader - Port output data"]
pub type ODR12_R = crate :: BitReader ; # [doc = "Field `ODR12` writer - Port output data"]
pub type ODR12_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR13` reader - Port output data"]
pub type ODR13_R = crate :: BitReader ; # [doc = "Field `ODR13` writer - Port output data"]
pub type ODR13_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR14` reader - Port output data"]
pub type ODR14_R = crate :: BitReader ; # [doc = "Field `ODR14` writer - Port output data"]
pub type ODR14_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ODR15` reader - Port output data"]
pub type ODR15_R = crate :: BitReader ; # [doc = "Field `ODR15` writer - Port output data"]
pub type ODR15_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Port output data"]
# [inline (always)]
pub fn odr0 (& self) -> ODR0_R { ODR0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Port output data"]
# [inline (always)]
pub fn odr1 (& self) -> ODR1_R { ODR1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Port output data"]
# [inline (always)]
pub fn odr2 (& self) -> ODR2_R { ODR2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Port output data"]
# [inline (always)]
pub fn odr3 (& self) -> ODR3_R { ODR3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Port output data"]
# [inline (always)]
pub fn odr4 (& self) -> ODR4_R { ODR4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Port output data"]
# [inline (always)]
pub fn odr5 (& self) -> ODR5_R { ODR5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Port output data"]
# [inline (always)]
pub fn odr6 (& self) -> ODR6_R { ODR6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Port output data"]
# [inline (always)]
pub fn odr7 (& self) -> ODR7_R { ODR7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Port output data"]
# [inline (always)]
pub fn odr8 (& self) -> ODR8_R { ODR8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Port output data"]
# [inline (always)]
pub fn odr9 (& self) -> ODR9_R { ODR9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Port output data"]
# [inline (always)]
pub fn odr10 (& self) -> ODR10_R { ODR10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Port output data"]
# [inline (always)]
pub fn odr11 (& self) -> ODR11_R { ODR11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Port output data"]
# [inline (always)]
pub fn odr12 (& self) -> ODR12_R { ODR12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Port output data"]
# [inline (always)]
pub fn odr13 (& self) -> ODR13_R { ODR13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Port output data"]
# [inline (always)]
pub fn odr14 (& self) -> ODR14_R { ODR14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Port output data"]
# [inline (always)]
pub fn odr15 (& self) -> ODR15_R { ODR15_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bit 0 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr0 (& mut self) -> ODR0_W < OUTDR_SPEC > { ODR0_W :: new (self , 0) } # [doc = "Bit 1 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr1 (& mut self) -> ODR1_W < OUTDR_SPEC > { ODR1_W :: new (self , 1) } # [doc = "Bit 2 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr2 (& mut self) -> ODR2_W < OUTDR_SPEC > { ODR2_W :: new (self , 2) } # [doc = "Bit 3 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr3 (& mut self) -> ODR3_W < OUTDR_SPEC > { ODR3_W :: new (self , 3) } # [doc = "Bit 4 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr4 (& mut self) -> ODR4_W < OUTDR_SPEC > { ODR4_W :: new (self , 4) } # [doc = "Bit 5 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr5 (& mut self) -> ODR5_W < OUTDR_SPEC > { ODR5_W :: new (self , 5) } # [doc = "Bit 6 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr6 (& mut self) -> ODR6_W < OUTDR_SPEC > { ODR6_W :: new (self , 6) } # [doc = "Bit 7 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr7 (& mut self) -> ODR7_W < OUTDR_SPEC > { ODR7_W :: new (self , 7) } # [doc = "Bit 8 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr8 (& mut self) -> ODR8_W < OUTDR_SPEC > { ODR8_W :: new (self , 8) } # [doc = "Bit 9 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr9 (& mut self) -> ODR9_W < OUTDR_SPEC > { ODR9_W :: new (self , 9) } # [doc = "Bit 10 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr10 (& mut self) -> ODR10_W < OUTDR_SPEC > { ODR10_W :: new (self , 10) } # [doc = "Bit 11 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr11 (& mut self) -> ODR11_W < OUTDR_SPEC > { ODR11_W :: new (self , 11) } # [doc = "Bit 12 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr12 (& mut self) -> ODR12_W < OUTDR_SPEC > { ODR12_W :: new (self , 12) } # [doc = "Bit 13 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr13 (& mut self) -> ODR13_W < OUTDR_SPEC > { ODR13_W :: new (self , 13) } # [doc = "Bit 14 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr14 (& mut self) -> ODR14_W < OUTDR_SPEC > { ODR14_W :: new (self , 14) } # [doc = "Bit 15 - Port output data"]
# [inline (always)]
# [must_use]
pub fn odr15 (& mut self) -> ODR15_W < OUTDR_SPEC > { ODR15_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Port output data register (GPIOn_OUTDR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outdr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`outdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OUTDR_SPEC ; impl crate :: RegisterSpec for OUTDR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`outdr::R`](R) reader structure"]
impl crate :: Readable for OUTDR_SPEC { } # [doc = "`write(|w| ..)` method takes [`outdr::W`](W) writer structure"]
impl crate :: Writable for OUTDR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets OUTDR to value 0"]
impl crate :: Resettable for OUTDR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "BSHR (w) register accessor: Port bit set/reset register (GPIOn_BSHR)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bshr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bshr`]
module"]
pub type BSHR = crate :: Reg < bshr :: BSHR_SPEC > ; # [doc = "Port bit set/reset register (GPIOn_BSHR)"]
pub mod bshr { # [doc = "Register `BSHR` writer"]
pub type W = crate :: W < BSHR_SPEC > ; # [doc = "Field `BS0` writer - Set bit 0"]
pub type BS0_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS1` writer - Set bit 1"]
pub type BS1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS2` writer - Set bit 1"]
pub type BS2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS3` writer - Set bit 3"]
pub type BS3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS4` writer - Set bit 4"]
pub type BS4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS5` writer - Set bit 5"]
pub type BS5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS6` writer - Set bit 6"]
pub type BS6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS7` writer - Set bit 7"]
pub type BS7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS8` writer - Set bit 8"]
pub type BS8_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS9` writer - Set bit 9"]
pub type BS9_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS10` writer - Set bit 10"]
pub type BS10_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS11` writer - Set bit 11"]
pub type BS11_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS12` writer - Set bit 12"]
pub type BS12_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS13` writer - Set bit 13"]
pub type BS13_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS14` writer - Set bit 14"]
pub type BS14_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BS15` writer - Set bit 15"]
pub type BS15_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR0` writer - Reset bit 0"]
pub type BR0_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR1` writer - Reset bit 1"]
pub type BR1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR2` writer - Reset bit 2"]
pub type BR2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR3` writer - Reset bit 3"]
pub type BR3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR4` writer - Reset bit 4"]
pub type BR4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR5` writer - Reset bit 5"]
pub type BR5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR6` writer - Reset bit 6"]
pub type BR6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR7` writer - Reset bit 7"]
pub type BR7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR8` writer - Reset bit 8"]
pub type BR8_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR9` writer - Reset bit 9"]
pub type BR9_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR10` writer - Reset bit 10"]
pub type BR10_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR11` writer - Reset bit 11"]
pub type BR11_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR12` writer - Reset bit 12"]
pub type BR12_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR13` writer - Reset bit 13"]
pub type BR13_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR14` writer - Reset bit 14"]
pub type BR14_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR15` writer - Reset bit 15"]
pub type BR15_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W { # [doc = "Bit 0 - Set bit 0"]
# [inline (always)]
# [must_use]
pub fn bs0 (& mut self) -> BS0_W < BSHR_SPEC > { BS0_W :: new (self , 0) } # [doc = "Bit 1 - Set bit 1"]
# [inline (always)]
# [must_use]
pub fn bs1 (& mut self) -> BS1_W < BSHR_SPEC > { BS1_W :: new (self , 1) } # [doc = "Bit 2 - Set bit 1"]
# [inline (always)]
# [must_use]
pub fn bs2 (& mut self) -> BS2_W < BSHR_SPEC > { BS2_W :: new (self , 2) } # [doc = "Bit 3 - Set bit 3"]
# [inline (always)]
# [must_use]
pub fn bs3 (& mut self) -> BS3_W < BSHR_SPEC > { BS3_W :: new (self , 3) } # [doc = "Bit 4 - Set bit 4"]
# [inline (always)]
# [must_use]
pub fn bs4 (& mut self) -> BS4_W < BSHR_SPEC > { BS4_W :: new (self , 4) } # [doc = "Bit 5 - Set bit 5"]
# [inline (always)]
# [must_use]
pub fn bs5 (& mut self) -> BS5_W < BSHR_SPEC > { BS5_W :: new (self , 5) } # [doc = "Bit 6 - Set bit 6"]
# [inline (always)]
# [must_use]
pub fn bs6 (& mut self) -> BS6_W < BSHR_SPEC > { BS6_W :: new (self , 6) } # [doc = "Bit 7 - Set bit 7"]
# [inline (always)]
# [must_use]
pub fn bs7 (& mut self) -> BS7_W < BSHR_SPEC > { BS7_W :: new (self , 7) } # [doc = "Bit 8 - Set bit 8"]
# [inline (always)]
# [must_use]
pub fn bs8 (& mut self) -> BS8_W < BSHR_SPEC > { BS8_W :: new (self , 8) } # [doc = "Bit 9 - Set bit 9"]
# [inline (always)]
# [must_use]
pub fn bs9 (& mut self) -> BS9_W < BSHR_SPEC > { BS9_W :: new (self , 9) } # [doc = "Bit 10 - Set bit 10"]
# [inline (always)]
# [must_use]
pub fn bs10 (& mut self) -> BS10_W < BSHR_SPEC > { BS10_W :: new (self , 10) } # [doc = "Bit 11 - Set bit 11"]
# [inline (always)]
# [must_use]
pub fn bs11 (& mut self) -> BS11_W < BSHR_SPEC > { BS11_W :: new (self , 11) } # [doc = "Bit 12 - Set bit 12"]
# [inline (always)]
# [must_use]
pub fn bs12 (& mut self) -> BS12_W < BSHR_SPEC > { BS12_W :: new (self , 12) } # [doc = "Bit 13 - Set bit 13"]
# [inline (always)]
# [must_use]
pub fn bs13 (& mut self) -> BS13_W < BSHR_SPEC > { BS13_W :: new (self , 13) } # [doc = "Bit 14 - Set bit 14"]
# [inline (always)]
# [must_use]
pub fn bs14 (& mut self) -> BS14_W < BSHR_SPEC > { BS14_W :: new (self , 14) } # [doc = "Bit 15 - Set bit 15"]
# [inline (always)]
# [must_use]
pub fn bs15 (& mut self) -> BS15_W < BSHR_SPEC > { BS15_W :: new (self , 15) } # [doc = "Bit 16 - Reset bit 0"]
# [inline (always)]
# [must_use]
pub fn br0 (& mut self) -> BR0_W < BSHR_SPEC > { BR0_W :: new (self , 16) } # [doc = "Bit 17 - Reset bit 1"]
# [inline (always)]
# [must_use]
pub fn br1 (& mut self) -> BR1_W < BSHR_SPEC > { BR1_W :: new (self , 17) } # [doc = "Bit 18 - Reset bit 2"]
# [inline (always)]
# [must_use]
pub fn br2 (& mut self) -> BR2_W < BSHR_SPEC > { BR2_W :: new (self , 18) } # [doc = "Bit 19 - Reset bit 3"]
# [inline (always)]
# [must_use]
pub fn br3 (& mut self) -> BR3_W < BSHR_SPEC > { BR3_W :: new (self , 19) } # [doc = "Bit 20 - Reset bit 4"]
# [inline (always)]
# [must_use]
pub fn br4 (& mut self) -> BR4_W < BSHR_SPEC > { BR4_W :: new (self , 20) } # [doc = "Bit 21 - Reset bit 5"]
# [inline (always)]
# [must_use]
pub fn br5 (& mut self) -> BR5_W < BSHR_SPEC > { BR5_W :: new (self , 21) } # [doc = "Bit 22 - Reset bit 6"]
# [inline (always)]
# [must_use]
pub fn br6 (& mut self) -> BR6_W < BSHR_SPEC > { BR6_W :: new (self , 22) } # [doc = "Bit 23 - Reset bit 7"]
# [inline (always)]
# [must_use]
pub fn br7 (& mut self) -> BR7_W < BSHR_SPEC > { BR7_W :: new (self , 23) } # [doc = "Bit 24 - Reset bit 8"]
# [inline (always)]
# [must_use]
pub fn br8 (& mut self) -> BR8_W < BSHR_SPEC > { BR8_W :: new (self , 24) } # [doc = "Bit 25 - Reset bit 9"]
# [inline (always)]
# [must_use]
pub fn br9 (& mut self) -> BR9_W < BSHR_SPEC > { BR9_W :: new (self , 25) } # [doc = "Bit 26 - Reset bit 10"]
# [inline (always)]
# [must_use]
pub fn br10 (& mut self) -> BR10_W < BSHR_SPEC > { BR10_W :: new (self , 26) } # [doc = "Bit 27 - Reset bit 11"]
# [inline (always)]
# [must_use]
pub fn br11 (& mut self) -> BR11_W < BSHR_SPEC > { BR11_W :: new (self , 27) } # [doc = "Bit 28 - Reset bit 12"]
# [inline (always)]
# [must_use]
pub fn br12 (& mut self) -> BR12_W < BSHR_SPEC > { BR12_W :: new (self , 28) } # [doc = "Bit 29 - Reset bit 13"]
# [inline (always)]
# [must_use]
pub fn br13 (& mut self) -> BR13_W < BSHR_SPEC > { BR13_W :: new (self , 29) } # [doc = "Bit 30 - Reset bit 14"]
# [inline (always)]
# [must_use]
pub fn br14 (& mut self) -> BR14_W < BSHR_SPEC > { BR14_W :: new (self , 30) } # [doc = "Bit 31 - Reset bit 15"]
# [inline (always)]
# [must_use]
pub fn br15 (& mut self) -> BR15_W < BSHR_SPEC > { BR15_W :: new (self , 31) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Port bit set/reset register (GPIOn_BSHR)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bshr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BSHR_SPEC ; impl crate :: RegisterSpec for BSHR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`bshr::W`](W) writer structure"]
impl crate :: Writable for BSHR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets BSHR to value 0"]
impl crate :: Resettable for BSHR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "BCR (w) register accessor: Port bit reset register (GPIOn_BCR)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bcr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bcr`]
module"]
pub type BCR = crate :: Reg < bcr :: BCR_SPEC > ; # [doc = "Port bit reset register (GPIOn_BCR)"]
pub mod bcr { # [doc = "Register `BCR` writer"]
pub type W = crate :: W < BCR_SPEC > ; # [doc = "Field `BR0` writer - Reset bit 0"]
pub type BR0_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR1` writer - Reset bit 1"]
pub type BR1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR2` writer - Reset bit 1"]
pub type BR2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR3` writer - Reset bit 3"]
pub type BR3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR4` writer - Reset bit 4"]
pub type BR4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR5` writer - Reset bit 5"]
pub type BR5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR6` writer - Reset bit 6"]
pub type BR6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR7` writer - Reset bit 7"]
pub type BR7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR8` writer - Reset bit 8"]
pub type BR8_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR9` writer - Reset bit 9"]
pub type BR9_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR10` writer - Reset bit 10"]
pub type BR10_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR11` writer - Reset bit 11"]
pub type BR11_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR12` writer - Reset bit 12"]
pub type BR12_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR13` writer - Reset bit 13"]
pub type BR13_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR14` writer - Reset bit 14"]
pub type BR14_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR15` writer - Reset bit 15"]
pub type BR15_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W { # [doc = "Bit 0 - Reset bit 0"]
# [inline (always)]
# [must_use]
pub fn br0 (& mut self) -> BR0_W < BCR_SPEC > { BR0_W :: new (self , 0) } # [doc = "Bit 1 - Reset bit 1"]
# [inline (always)]
# [must_use]
pub fn br1 (& mut self) -> BR1_W < BCR_SPEC > { BR1_W :: new (self , 1) } # [doc = "Bit 2 - Reset bit 1"]
# [inline (always)]
# [must_use]
pub fn br2 (& mut self) -> BR2_W < BCR_SPEC > { BR2_W :: new (self , 2) } # [doc = "Bit 3 - Reset bit 3"]
# [inline (always)]
# [must_use]
pub fn br3 (& mut self) -> BR3_W < BCR_SPEC > { BR3_W :: new (self , 3) } # [doc = "Bit 4 - Reset bit 4"]
# [inline (always)]
# [must_use]
pub fn br4 (& mut self) -> BR4_W < BCR_SPEC > { BR4_W :: new (self , 4) } # [doc = "Bit 5 - Reset bit 5"]
# [inline (always)]
# [must_use]
pub fn br5 (& mut self) -> BR5_W < BCR_SPEC > { BR5_W :: new (self , 5) } # [doc = "Bit 6 - Reset bit 6"]
# [inline (always)]
# [must_use]
pub fn br6 (& mut self) -> BR6_W < BCR_SPEC > { BR6_W :: new (self , 6) } # [doc = "Bit 7 - Reset bit 7"]
# [inline (always)]
# [must_use]
pub fn br7 (& mut self) -> BR7_W < BCR_SPEC > { BR7_W :: new (self , 7) } # [doc = "Bit 8 - Reset bit 8"]
# [inline (always)]
# [must_use]
pub fn br8 (& mut self) -> BR8_W < BCR_SPEC > { BR8_W :: new (self , 8) } # [doc = "Bit 9 - Reset bit 9"]
# [inline (always)]
# [must_use]
pub fn br9 (& mut self) -> BR9_W < BCR_SPEC > { BR9_W :: new (self , 9) } # [doc = "Bit 10 - Reset bit 10"]
# [inline (always)]
# [must_use]
pub fn br10 (& mut self) -> BR10_W < BCR_SPEC > { BR10_W :: new (self , 10) } # [doc = "Bit 11 - Reset bit 11"]
# [inline (always)]
# [must_use]
pub fn br11 (& mut self) -> BR11_W < BCR_SPEC > { BR11_W :: new (self , 11) } # [doc = "Bit 12 - Reset bit 12"]
# [inline (always)]
# [must_use]
pub fn br12 (& mut self) -> BR12_W < BCR_SPEC > { BR12_W :: new (self , 12) } # [doc = "Bit 13 - Reset bit 13"]
# [inline (always)]
# [must_use]
pub fn br13 (& mut self) -> BR13_W < BCR_SPEC > { BR13_W :: new (self , 13) } # [doc = "Bit 14 - Reset bit 14"]
# [inline (always)]
# [must_use]
pub fn br14 (& mut self) -> BR14_W < BCR_SPEC > { BR14_W :: new (self , 14) } # [doc = "Bit 15 - Reset bit 15"]
# [inline (always)]
# [must_use]
pub fn br15 (& mut self) -> BR15_W < BCR_SPEC > { BR15_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Port bit reset register (GPIOn_BCR)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BCR_SPEC ; impl crate :: RegisterSpec for BCR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"]
impl crate :: Writable for BCR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets BCR to value 0"]
impl crate :: Resettable for BCR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "LCKR (rw) register accessor: Port configuration lock register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lckr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lckr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lckr`]
module"]
pub type LCKR = crate :: Reg < lckr :: LCKR_SPEC > ; # [doc = "Port configuration lock register"]
pub mod lckr { # [doc = "Register `LCKR` reader"]
pub type R = crate :: R < LCKR_SPEC > ; # [doc = "Register `LCKR` writer"]
pub type W = crate :: W < LCKR_SPEC > ; # [doc = "Field `LCK0` reader - Port A Lock bit 0"]
pub type LCK0_R = crate :: BitReader ; # [doc = "Field `LCK0` writer - Port A Lock bit 0"]
pub type LCK0_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK1` reader - Port A Lock bit 1"]
pub type LCK1_R = crate :: BitReader ; # [doc = "Field `LCK1` writer - Port A Lock bit 1"]
pub type LCK1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK2` reader - Port A Lock bit 2"]
pub type LCK2_R = crate :: BitReader ; # [doc = "Field `LCK2` writer - Port A Lock bit 2"]
pub type LCK2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK3` reader - Port A Lock bit 3"]
pub type LCK3_R = crate :: BitReader ; # [doc = "Field `LCK3` writer - Port A Lock bit 3"]
pub type LCK3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK4` reader - Port A Lock bit 4"]
pub type LCK4_R = crate :: BitReader ; # [doc = "Field `LCK4` writer - Port A Lock bit 4"]
pub type LCK4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK5` reader - Port A Lock bit 5"]
pub type LCK5_R = crate :: BitReader ; # [doc = "Field `LCK5` writer - Port A Lock bit 5"]
pub type LCK5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK6` reader - Port A Lock bit 6"]
pub type LCK6_R = crate :: BitReader ; # [doc = "Field `LCK6` writer - Port A Lock bit 6"]
pub type LCK6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK7` reader - Port A Lock bit 7"]
pub type LCK7_R = crate :: BitReader ; # [doc = "Field `LCK7` writer - Port A Lock bit 7"]
pub type LCK7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK8` reader - Port A Lock bit 8"]
pub type LCK8_R = crate :: BitReader ; # [doc = "Field `LCK8` writer - Port A Lock bit 8"]
pub type LCK8_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK9` reader - Port A Lock bit 9"]
pub type LCK9_R = crate :: BitReader ; # [doc = "Field `LCK9` writer - Port A Lock bit 9"]
pub type LCK9_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK10` reader - Port A Lock bit 10"]
pub type LCK10_R = crate :: BitReader ; # [doc = "Field `LCK10` writer - Port A Lock bit 10"]
pub type LCK10_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK11` reader - Port A Lock bit 11"]
pub type LCK11_R = crate :: BitReader ; # [doc = "Field `LCK11` writer - Port A Lock bit 11"]
pub type LCK11_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK12` reader - Port A Lock bit 12"]
pub type LCK12_R = crate :: BitReader ; # [doc = "Field `LCK12` writer - Port A Lock bit 12"]
pub type LCK12_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK13` reader - Port A Lock bit 13"]
pub type LCK13_R = crate :: BitReader ; # [doc = "Field `LCK13` writer - Port A Lock bit 13"]
pub type LCK13_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK14` reader - Port A Lock bit 14"]
pub type LCK14_R = crate :: BitReader ; # [doc = "Field `LCK14` writer - Port A Lock bit 14"]
pub type LCK14_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCK15` reader - Port A Lock bit 15"]
pub type LCK15_R = crate :: BitReader ; # [doc = "Field `LCK15` writer - Port A Lock bit 15"]
pub type LCK15_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LCKK` reader - Lock key"]
pub type LCKK_R = crate :: BitReader ; # [doc = "Field `LCKK` writer - Lock key"]
pub type LCKK_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Port A Lock bit 0"]
# [inline (always)]
pub fn lck0 (& self) -> LCK0_R { LCK0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Port A Lock bit 1"]
# [inline (always)]
pub fn lck1 (& self) -> LCK1_R { LCK1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Port A Lock bit 2"]
# [inline (always)]
pub fn lck2 (& self) -> LCK2_R { LCK2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Port A Lock bit 3"]
# [inline (always)]
pub fn lck3 (& self) -> LCK3_R { LCK3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Port A Lock bit 4"]
# [inline (always)]
pub fn lck4 (& self) -> LCK4_R { LCK4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Port A Lock bit 5"]
# [inline (always)]
pub fn lck5 (& self) -> LCK5_R { LCK5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Port A Lock bit 6"]
# [inline (always)]
pub fn lck6 (& self) -> LCK6_R { LCK6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Port A Lock bit 7"]
# [inline (always)]
pub fn lck7 (& self) -> LCK7_R { LCK7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Port A Lock bit 8"]
# [inline (always)]
pub fn lck8 (& self) -> LCK8_R { LCK8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Port A Lock bit 9"]
# [inline (always)]
pub fn lck9 (& self) -> LCK9_R { LCK9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Port A Lock bit 10"]
# [inline (always)]
pub fn lck10 (& self) -> LCK10_R { LCK10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Port A Lock bit 11"]
# [inline (always)]
pub fn lck11 (& self) -> LCK11_R { LCK11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Port A Lock bit 12"]
# [inline (always)]
pub fn lck12 (& self) -> LCK12_R { LCK12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Port A Lock bit 13"]
# [inline (always)]
pub fn lck13 (& self) -> LCK13_R { LCK13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Port A Lock bit 14"]
# [inline (always)]
pub fn lck14 (& self) -> LCK14_R { LCK14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Port A Lock bit 15"]
# [inline (always)]
pub fn lck15 (& self) -> LCK15_R { LCK15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Lock key"]
# [inline (always)]
pub fn lckk (& self) -> LCKK_R { LCKK_R :: new (((self . bits >> 16) & 1) != 0) } } impl W { # [doc = "Bit 0 - Port A Lock bit 0"]
# [inline (always)]
# [must_use]
pub fn lck0 (& mut self) -> LCK0_W < LCKR_SPEC > { LCK0_W :: new (self , 0) } # [doc = "Bit 1 - Port A Lock bit 1"]
# [inline (always)]
# [must_use]
pub fn lck1 (& mut self) -> LCK1_W < LCKR_SPEC > { LCK1_W :: new (self , 1) } # [doc = "Bit 2 - Port A Lock bit 2"]
# [inline (always)]
# [must_use]
pub fn lck2 (& mut self) -> LCK2_W < LCKR_SPEC > { LCK2_W :: new (self , 2) } # [doc = "Bit 3 - Port A Lock bit 3"]
# [inline (always)]
# [must_use]
pub fn lck3 (& mut self) -> LCK3_W < LCKR_SPEC > { LCK3_W :: new (self , 3) } # [doc = "Bit 4 - Port A Lock bit 4"]
# [inline (always)]
# [must_use]
pub fn lck4 (& mut self) -> LCK4_W < LCKR_SPEC > { LCK4_W :: new (self , 4) } # [doc = "Bit 5 - Port A Lock bit 5"]
# [inline (always)]
# [must_use]
pub fn lck5 (& mut self) -> LCK5_W < LCKR_SPEC > { LCK5_W :: new (self , 5) } # [doc = "Bit 6 - Port A Lock bit 6"]
# [inline (always)]
# [must_use]
pub fn lck6 (& mut self) -> LCK6_W < LCKR_SPEC > { LCK6_W :: new (self , 6) } # [doc = "Bit 7 - Port A Lock bit 7"]
# [inline (always)]
# [must_use]
pub fn lck7 (& mut self) -> LCK7_W < LCKR_SPEC > { LCK7_W :: new (self , 7) } # [doc = "Bit 8 - Port A Lock bit 8"]
# [inline (always)]
# [must_use]
pub fn lck8 (& mut self) -> LCK8_W < LCKR_SPEC > { LCK8_W :: new (self , 8) } # [doc = "Bit 9 - Port A Lock bit 9"]
# [inline (always)]
# [must_use]
pub fn lck9 (& mut self) -> LCK9_W < LCKR_SPEC > { LCK9_W :: new (self , 9) } # [doc = "Bit 10 - Port A Lock bit 10"]
# [inline (always)]
# [must_use]
pub fn lck10 (& mut self) -> LCK10_W < LCKR_SPEC > { LCK10_W :: new (self , 10) } # [doc = "Bit 11 - Port A Lock bit 11"]
# [inline (always)]
# [must_use]
pub fn lck11 (& mut self) -> LCK11_W < LCKR_SPEC > { LCK11_W :: new (self , 11) } # [doc = "Bit 12 - Port A Lock bit 12"]
# [inline (always)]
# [must_use]
pub fn lck12 (& mut self) -> LCK12_W < LCKR_SPEC > { LCK12_W :: new (self , 12) } # [doc = "Bit 13 - Port A Lock bit 13"]
# [inline (always)]
# [must_use]
pub fn lck13 (& mut self) -> LCK13_W < LCKR_SPEC > { LCK13_W :: new (self , 13) } # [doc = "Bit 14 - Port A Lock bit 14"]
# [inline (always)]
# [must_use]
pub fn lck14 (& mut self) -> LCK14_W < LCKR_SPEC > { LCK14_W :: new (self , 14) } # [doc = "Bit 15 - Port A Lock bit 15"]
# [inline (always)]
# [must_use]
pub fn lck15 (& mut self) -> LCK15_W < LCKR_SPEC > { LCK15_W :: new (self , 15) } # [doc = "Bit 16 - Lock key"]
# [inline (always)]
# [must_use]
pub fn lckk (& mut self) -> LCKK_W < LCKR_SPEC > { LCKK_W :: new (self , 16) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Port configuration lock register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lckr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lckr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LCKR_SPEC ; impl crate :: RegisterSpec for LCKR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`lckr::R`](R) reader structure"]
impl crate :: Readable for LCKR_SPEC { } # [doc = "`write(|w| ..)` method takes [`lckr::W`](W) writer structure"]
impl crate :: Writable for LCKR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets LCKR to value 0"]
impl crate :: Resettable for LCKR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "General purpose I/O"]
pub struct GPIOB { _marker : PhantomData < * const () > } unsafe impl Send for GPIOB { } impl GPIOB { # [doc = r"Pointer to the register block"]
pub const PTR : * const gpioa :: RegisterBlock = 0x4001_0c00 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const gpioa :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for GPIOB { type Target = gpioa :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for GPIOB { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("GPIOB") . finish () } } # [doc = "General purpose I/O"]
pub use self :: gpioa as gpiob ; # [doc = "General purpose I/O"]
pub struct GPIOC { _marker : PhantomData < * const () > } unsafe impl Send for GPIOC { } impl GPIOC { # [doc = r"Pointer to the register block"]
pub const PTR : * const gpioa :: RegisterBlock = 0x4001_1000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const gpioa :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for GPIOC { type Target = gpioa :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for GPIOC { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("GPIOC") . finish () } } # [doc = "General purpose I/O"]
pub use self :: gpioa as gpioc ; # [doc = "General purpose I/O"]
pub struct GPIOD { _marker : PhantomData < * const () > } unsafe impl Send for GPIOD { } impl GPIOD { # [doc = r"Pointer to the register block"]
pub const PTR : * const gpioa :: RegisterBlock = 0x4001_1400 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const gpioa :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for GPIOD { type Target = gpioa :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for GPIOD { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("GPIOD") . finish () } } # [doc = "General purpose I/O"]
pub use self :: gpioa as gpiod ; # [doc = "Alternate function I/O"]
pub struct AFIO { _marker : PhantomData < * const () > } unsafe impl Send for AFIO { } impl AFIO { # [doc = r"Pointer to the register block"]
pub const PTR : * const afio :: RegisterBlock = 0x4001_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const afio :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for AFIO { type Target = afio :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for AFIO { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("AFIO") . finish () } } # [doc = "Alternate function I/O"]
pub mod afio { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { ecr : ECR , pcfr1 : PCFR1 , exticr1 : EXTICR1 , exticr2 : EXTICR2 , exticr3 : EXTICR3 , exticr4 : EXTICR4 , _reserved6 : [u8 ; 0x04]
, pcfr2 : PCFR2 , } impl RegisterBlock { # [doc = "0x00 - Event Control Register (AFIO_ECR)"]
# [inline (always)]
pub const fn ecr (& self) -> & ECR { & self . ecr } # [doc = "0x04 - AF remap and debug I/O configuration register (AFIO_PCFR1)"]
# [inline (always)]
pub const fn pcfr1 (& self) -> & PCFR1 { & self . pcfr1 } # [doc = "0x08 - External interrupt configuration register 1 (AFIO_EXTICR1)"]
# [inline (always)]
pub const fn exticr1 (& self) -> & EXTICR1 { & self . exticr1 } # [doc = "0x0c - External interrupt configuration register 2 (AFIO_EXTICR2)"]
# [inline (always)]
pub const fn exticr2 (& self) -> & EXTICR2 { & self . exticr2 } # [doc = "0x10 - External interrupt configuration register 3 (AFIO_EXTICR3)"]
# [inline (always)]
pub const fn exticr3 (& self) -> & EXTICR3 { & self . exticr3 } # [doc = "0x14 - External interrupt configuration register 4 (AFIO_EXTICR4)"]
# [inline (always)]
pub const fn exticr4 (& self) -> & EXTICR4 { & self . exticr4 } # [doc = "0x1c - AF remap and debug I/O configuration register"]
# [inline (always)]
pub const fn pcfr2 (& self) -> & PCFR2 { & self . pcfr2 } } # [doc = "ECR (rw) register accessor: Event Control Register (AFIO_ECR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr`]
module"]
pub type ECR = crate :: Reg < ecr :: ECR_SPEC > ; # [doc = "Event Control Register (AFIO_ECR)"]
pub mod ecr { # [doc = "Register `ECR` reader"]
pub type R = crate :: R < ECR_SPEC > ; # [doc = "Register `ECR` writer"]
pub type W = crate :: W < ECR_SPEC > ; # [doc = "Field `PIN` reader - Pin selection"]
pub type PIN_R = crate :: FieldReader ; # [doc = "Field `PIN` writer - Pin selection"]
pub type PIN_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `PORT` reader - Port selection"]
pub type PORT_R = crate :: FieldReader ; # [doc = "Field `PORT` writer - Port selection"]
pub type PORT_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `EVOE` reader - Event Output Enable"]
pub type EVOE_R = crate :: BitReader ; # [doc = "Field `EVOE` writer - Event Output Enable"]
pub type EVOE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - Pin selection"]
# [inline (always)]
pub fn pin (& self) -> PIN_R { PIN_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:6 - Port selection"]
# [inline (always)]
pub fn port (& self) -> PORT_R { PORT_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - Event Output Enable"]
# [inline (always)]
pub fn evoe (& self) -> EVOE_R { EVOE_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Pin selection"]
# [inline (always)]
# [must_use]
pub fn pin (& mut self) -> PIN_W < ECR_SPEC > { PIN_W :: new (self , 0) } # [doc = "Bits 4:6 - Port selection"]
# [inline (always)]
# [must_use]
pub fn port (& mut self) -> PORT_W < ECR_SPEC > { PORT_W :: new (self , 4) } # [doc = "Bit 7 - Event Output Enable"]
# [inline (always)]
# [must_use]
pub fn evoe (& mut self) -> EVOE_W < ECR_SPEC > { EVOE_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Control Register (AFIO_ECR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ECR_SPEC ; impl crate :: RegisterSpec for ECR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ecr::R`](R) reader structure"]
impl crate :: Readable for ECR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ecr::W`](W) writer structure"]
impl crate :: Writable for ECR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ECR to value 0"]
impl crate :: Resettable for ECR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "PCFR1 (rw) register accessor: AF remap and debug I/O configuration register (AFIO_PCFR1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcfr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcfr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcfr1`]
module"]
pub type PCFR1 = crate :: Reg < pcfr1 :: PCFR1_SPEC > ; # [doc = "AF remap and debug I/O configuration register (AFIO_PCFR1)"]
pub mod pcfr1 { # [doc = "Register `PCFR1` reader"]
pub type R = crate :: R < PCFR1_SPEC > ; # [doc = "Register `PCFR1` writer"]
pub type W = crate :: W < PCFR1_SPEC > ; # [doc = "Field `SPI1_REMAP` reader - SPI1 remapping"]
pub type SPI1_REMAP_R = crate :: BitReader ; # [doc = "Field `SPI1_REMAP` writer - SPI1 remapping"]
pub type SPI1_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2C1_REMAP` reader - I2C1 remapping"]
pub type I2C1_REMAP_R = crate :: BitReader ; # [doc = "Field `I2C1_REMAP` writer - I2C1 remapping"]
pub type I2C1_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USART1_REMAP` reader - USART1 remapping"]
pub type USART1_REMAP_R = crate :: BitReader ; # [doc = "Field `USART1_REMAP` writer - USART1 remapping"]
pub type USART1_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USART2_REMAP` reader - USART2 remapping"]
pub type USART2_REMAP_R = crate :: BitReader ; # [doc = "Field `USART2_REMAP` writer - USART2 remapping"]
pub type USART2_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `USART3_REMAP` reader - USART3 remapping"]
pub type USART3_REMAP_R = crate :: FieldReader ; # [doc = "Field `USART3_REMAP` writer - USART3 remapping"]
pub type USART3_REMAP_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TIM1_REMAP` reader - TIM1 remapping"]
pub type TIM1_REMAP_R = crate :: FieldReader ; # [doc = "Field `TIM1_REMAP` writer - TIM1 remapping"]
pub type TIM1_REMAP_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TIM2_REMAP` reader - TIM2 remapping"]
pub type TIM2_REMAP_R = crate :: FieldReader ; # [doc = "Field `TIM2_REMAP` writer - TIM2 remapping"]
pub type TIM2_REMAP_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TIM3_REMAP` reader - TIM3 remapping"]
pub type TIM3_REMAP_R = crate :: FieldReader ; # [doc = "Field `TIM3_REMAP` writer - TIM3 remapping"]
pub type TIM3_REMAP_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `TIM4_REMAP` reader - TIM4 remapping"]
pub type TIM4_REMAP_R = crate :: BitReader ; # [doc = "Field `TIM4_REMAP` writer - TIM4 remapping"]
pub type TIM4_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAN_REMAP` reader - CAN1 remapping"]
pub type CAN_REMAP_R = crate :: FieldReader ; # [doc = "Field `CAN_REMAP` writer - CAN1 remapping"]
pub type CAN_REMAP_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PD01_REMAP` reader - Port D0/Port D1 mapping on OSCIN/OSCOUT"]
pub type PD01_REMAP_R = crate :: BitReader ; # [doc = "Field `PD01_REMAP` writer - Port D0/Port D1 mapping on OSCIN/OSCOUT"]
pub type PD01_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIM5CH4_IREMAP` reader - Set and cleared by software"]
pub type TIM5CH4_IREMAP_R = crate :: BitReader ; # [doc = "Field `TIM5CH4_IREMAP` writer - Set and cleared by software"]
pub type TIM5CH4_IREMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADC1_ETRGINJ_REMAP` reader - ADC 1 External trigger injected conversion remapping"]
pub type ADC1_ETRGINJ_REMAP_R = crate :: BitReader ; # [doc = "Field `ADC1_ETRGINJ_REMAP` writer - ADC 1 External trigger injected conversion remapping"]
pub type ADC1_ETRGINJ_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADC1_ETRGREG_REMAP` reader - ADC 1 external trigger regular conversion remapping"]
pub type ADC1_ETRGREG_REMAP_R = crate :: BitReader ; # [doc = "Field `ADC1_ETRGREG_REMAP` writer - ADC 1 external trigger regular conversion remapping"]
pub type ADC1_ETRGREG_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADC2_ETRGINJ_REMAP` reader - ADC 2 external trigger injected conversion remapping"]
pub type ADC2_ETRGINJ_REMAP_R = crate :: BitReader ; # [doc = "Field `ADC2_ETRGINJ_REMAP` writer - ADC 2 external trigger injected conversion remapping"]
pub type ADC2_ETRGINJ_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADC2_ETRGREG_REMAP` reader - ADC 2 external trigger regular conversion remapping"]
pub type ADC2_ETRGREG_REMAP_R = crate :: BitReader ; # [doc = "Field `ADC2_ETRGREG_REMAP` writer - ADC 2 external trigger regular conversion remapping"]
pub type ADC2_ETRGREG_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWJ_CFG` writer - Serial wire JTAG configuration"]
pub type SWJ_CFG_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bit 0 - SPI1 remapping"]
# [inline (always)]
pub fn spi1_remap (& self) -> SPI1_REMAP_R { SPI1_REMAP_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - I2C1 remapping"]
# [inline (always)]
pub fn i2c1_remap (& self) -> I2C1_REMAP_R { I2C1_REMAP_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - USART1 remapping"]
# [inline (always)]
pub fn usart1_remap (& self) -> USART1_REMAP_R { USART1_REMAP_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - USART2 remapping"]
# [inline (always)]
pub fn usart2_remap (& self) -> USART2_REMAP_R { USART2_REMAP_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - USART3 remapping"]
# [inline (always)]
pub fn usart3_remap (& self) -> USART3_REMAP_R { USART3_REMAP_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 6:7 - TIM1 remapping"]
# [inline (always)]
pub fn tim1_remap (& self) -> TIM1_REMAP_R { TIM1_REMAP_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:9 - TIM2 remapping"]
# [inline (always)]
pub fn tim2_remap (& self) -> TIM2_REMAP_R { TIM2_REMAP_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - TIM3 remapping"]
# [inline (always)]
pub fn tim3_remap (& self) -> TIM3_REMAP_R { TIM3_REMAP_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bit 12 - TIM4 remapping"]
# [inline (always)]
pub fn tim4_remap (& self) -> TIM4_REMAP_R { TIM4_REMAP_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:14 - CAN1 remapping"]
# [inline (always)]
pub fn can_remap (& self) -> CAN_REMAP_R { CAN_REMAP_R :: new (((self . bits >> 13) & 3) as u8) } # [doc = "Bit 15 - Port D0/Port D1 mapping on OSCIN/OSCOUT"]
# [inline (always)]
pub fn pd01_remap (& self) -> PD01_REMAP_R { PD01_REMAP_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Set and cleared by software"]
# [inline (always)]
pub fn tim5ch4_iremap (& self) -> TIM5CH4_IREMAP_R { TIM5CH4_IREMAP_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - ADC 1 External trigger injected conversion remapping"]
# [inline (always)]
pub fn adc1_etrginj_remap (& self) -> ADC1_ETRGINJ_REMAP_R { ADC1_ETRGINJ_REMAP_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - ADC 1 external trigger regular conversion remapping"]
# [inline (always)]
pub fn adc1_etrgreg_remap (& self) -> ADC1_ETRGREG_REMAP_R { ADC1_ETRGREG_REMAP_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - ADC 2 external trigger injected conversion remapping"]
# [inline (always)]
pub fn adc2_etrginj_remap (& self) -> ADC2_ETRGINJ_REMAP_R { ADC2_ETRGINJ_REMAP_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - ADC 2 external trigger regular conversion remapping"]
# [inline (always)]
pub fn adc2_etrgreg_remap (& self) -> ADC2_ETRGREG_REMAP_R { ADC2_ETRGREG_REMAP_R :: new (((self . bits >> 20) & 1) != 0) } } impl W { # [doc = "Bit 0 - SPI1 remapping"]
# [inline (always)]
# [must_use]
pub fn spi1_remap (& mut self) -> SPI1_REMAP_W < PCFR1_SPEC > { SPI1_REMAP_W :: new (self , 0) } # [doc = "Bit 1 - I2C1 remapping"]
# [inline (always)]
# [must_use]
pub fn i2c1_remap (& mut self) -> I2C1_REMAP_W < PCFR1_SPEC > { I2C1_REMAP_W :: new (self , 1) } # [doc = "Bit 2 - USART1 remapping"]
# [inline (always)]
# [must_use]
pub fn usart1_remap (& mut self) -> USART1_REMAP_W < PCFR1_SPEC > { USART1_REMAP_W :: new (self , 2) } # [doc = "Bit 3 - USART2 remapping"]
# [inline (always)]
# [must_use]
pub fn usart2_remap (& mut self) -> USART2_REMAP_W < PCFR1_SPEC > { USART2_REMAP_W :: new (self , 3) } # [doc = "Bits 4:5 - USART3 remapping"]
# [inline (always)]
# [must_use]
pub fn usart3_remap (& mut self) -> USART3_REMAP_W < PCFR1_SPEC > { USART3_REMAP_W :: new (self , 4) } # [doc = "Bits 6:7 - TIM1 remapping"]
# [inline (always)]
# [must_use]
pub fn tim1_remap (& mut self) -> TIM1_REMAP_W < PCFR1_SPEC > { TIM1_REMAP_W :: new (self , 6) } # [doc = "Bits 8:9 - TIM2 remapping"]
# [inline (always)]
# [must_use]
pub fn tim2_remap (& mut self) -> TIM2_REMAP_W < PCFR1_SPEC > { TIM2_REMAP_W :: new (self , 8) } # [doc = "Bits 10:11 - TIM3 remapping"]
# [inline (always)]
# [must_use]
pub fn tim3_remap (& mut self) -> TIM3_REMAP_W < PCFR1_SPEC > { TIM3_REMAP_W :: new (self , 10) } # [doc = "Bit 12 - TIM4 remapping"]
# [inline (always)]
# [must_use]
pub fn tim4_remap (& mut self) -> TIM4_REMAP_W < PCFR1_SPEC > { TIM4_REMAP_W :: new (self , 12) } # [doc = "Bits 13:14 - CAN1 remapping"]
# [inline (always)]
# [must_use]
pub fn can_remap (& mut self) -> CAN_REMAP_W < PCFR1_SPEC > { CAN_REMAP_W :: new (self , 13) } # [doc = "Bit 15 - Port D0/Port D1 mapping on OSCIN/OSCOUT"]
# [inline (always)]
# [must_use]
pub fn pd01_remap (& mut self) -> PD01_REMAP_W < PCFR1_SPEC > { PD01_REMAP_W :: new (self , 15) } # [doc = "Bit 16 - Set and cleared by software"]
# [inline (always)]
# [must_use]
pub fn tim5ch4_iremap (& mut self) -> TIM5CH4_IREMAP_W < PCFR1_SPEC > { TIM5CH4_IREMAP_W :: new (self , 16) } # [doc = "Bit 17 - ADC 1 External trigger injected conversion remapping"]
# [inline (always)]
# [must_use]
pub fn adc1_etrginj_remap (& mut self) -> ADC1_ETRGINJ_REMAP_W < PCFR1_SPEC > { ADC1_ETRGINJ_REMAP_W :: new (self , 17) } # [doc = "Bit 18 - ADC 1 external trigger regular conversion remapping"]
# [inline (always)]
# [must_use]
pub fn adc1_etrgreg_remap (& mut self) -> ADC1_ETRGREG_REMAP_W < PCFR1_SPEC > { ADC1_ETRGREG_REMAP_W :: new (self , 18) } # [doc = "Bit 19 - ADC 2 external trigger injected conversion remapping"]
# [inline (always)]
# [must_use]
pub fn adc2_etrginj_remap (& mut self) -> ADC2_ETRGINJ_REMAP_W < PCFR1_SPEC > { ADC2_ETRGINJ_REMAP_W :: new (self , 19) } # [doc = "Bit 20 - ADC 2 external trigger regular conversion remapping"]
# [inline (always)]
# [must_use]
pub fn adc2_etrgreg_remap (& mut self) -> ADC2_ETRGREG_REMAP_W < PCFR1_SPEC > { ADC2_ETRGREG_REMAP_W :: new (self , 20) } # [doc = "Bits 24:26 - Serial wire JTAG configuration"]
# [inline (always)]
# [must_use]
pub fn swj_cfg (& mut self) -> SWJ_CFG_W < PCFR1_SPEC > { SWJ_CFG_W :: new (self , 24) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "AF remap and debug I/O configuration register (AFIO_PCFR1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcfr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcfr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PCFR1_SPEC ; impl crate :: RegisterSpec for PCFR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pcfr1::R`](R) reader structure"]
impl crate :: Readable for PCFR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`pcfr1::W`](W) writer structure"]
impl crate :: Writable for PCFR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PCFR1 to value 0"]
impl crate :: Resettable for PCFR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "EXTICR1 (rw) register accessor: External interrupt configuration register 1 (AFIO_EXTICR1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exticr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exticr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exticr1`]
module"]
pub type EXTICR1 = crate :: Reg < exticr1 :: EXTICR1_SPEC > ; # [doc = "External interrupt configuration register 1 (AFIO_EXTICR1)"]
pub mod exticr1 { # [doc = "Register `EXTICR1` reader"]
pub type R = crate :: R < EXTICR1_SPEC > ; # [doc = "Register `EXTICR1` writer"]
pub type W = crate :: W < EXTICR1_SPEC > ; # [doc = "Field `EXTI0` reader - EXTI0 configuration"]
pub type EXTI0_R = crate :: FieldReader ; # [doc = "Field `EXTI0` writer - EXTI0 configuration"]
pub type EXTI0_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EXTI1` reader - EXTI1 configuration"]
pub type EXTI1_R = crate :: FieldReader ; # [doc = "Field `EXTI1` writer - EXTI1 configuration"]
pub type EXTI1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EXTI2` reader - EXTI2 configuration"]
pub type EXTI2_R = crate :: FieldReader ; # [doc = "Field `EXTI2` writer - EXTI2 configuration"]
pub type EXTI2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EXTI3` reader - EXTI3 configuration"]
pub type EXTI3_R = crate :: FieldReader ; # [doc = "Field `EXTI3` writer - EXTI3 configuration"]
pub type EXTI3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - EXTI0 configuration"]
# [inline (always)]
pub fn exti0 (& self) -> EXTI0_R { EXTI0_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - EXTI1 configuration"]
# [inline (always)]
pub fn exti1 (& self) -> EXTI1_R { EXTI1_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - EXTI2 configuration"]
# [inline (always)]
pub fn exti2 (& self) -> EXTI2_R { EXTI2_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - EXTI3 configuration"]
# [inline (always)]
pub fn exti3 (& self) -> EXTI3_R { EXTI3_R :: new (((self . bits >> 12) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - EXTI0 configuration"]
# [inline (always)]
# [must_use]
pub fn exti0 (& mut self) -> EXTI0_W < EXTICR1_SPEC > { EXTI0_W :: new (self , 0) } # [doc = "Bits 4:7 - EXTI1 configuration"]
# [inline (always)]
# [must_use]
pub fn exti1 (& mut self) -> EXTI1_W < EXTICR1_SPEC > { EXTI1_W :: new (self , 4) } # [doc = "Bits 8:11 - EXTI2 configuration"]
# [inline (always)]
# [must_use]
pub fn exti2 (& mut self) -> EXTI2_W < EXTICR1_SPEC > { EXTI2_W :: new (self , 8) } # [doc = "Bits 12:15 - EXTI3 configuration"]
# [inline (always)]
# [must_use]
pub fn exti3 (& mut self) -> EXTI3_W < EXTICR1_SPEC > { EXTI3_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "External interrupt configuration register 1 (AFIO_EXTICR1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exticr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exticr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EXTICR1_SPEC ; impl crate :: RegisterSpec for EXTICR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`exticr1::R`](R) reader structure"]
impl crate :: Readable for EXTICR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`exticr1::W`](W) writer structure"]
impl crate :: Writable for EXTICR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EXTICR1 to value 0"]
impl crate :: Resettable for EXTICR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "EXTICR2 (rw) register accessor: External interrupt configuration register 2 (AFIO_EXTICR2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exticr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exticr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exticr2`]
module"]
pub type EXTICR2 = crate :: Reg < exticr2 :: EXTICR2_SPEC > ; # [doc = "External interrupt configuration register 2 (AFIO_EXTICR2)"]
pub mod exticr2 { # [doc = "Register `EXTICR2` reader"]
pub type R = crate :: R < EXTICR2_SPEC > ; # [doc = "Register `EXTICR2` writer"]
pub type W = crate :: W < EXTICR2_SPEC > ; # [doc = "Field `EXTI4` reader - EXTI4 configuration"]
pub type EXTI4_R = crate :: FieldReader ; # [doc = "Field `EXTI4` writer - EXTI4 configuration"]
pub type EXTI4_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EXTI5` reader - EXTI5 configuration"]
pub type EXTI5_R = crate :: FieldReader ; # [doc = "Field `EXTI5` writer - EXTI5 configuration"]
pub type EXTI5_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EXTI6` reader - EXTI6 configuration"]
pub type EXTI6_R = crate :: FieldReader ; # [doc = "Field `EXTI6` writer - EXTI6 configuration"]
pub type EXTI6_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EXTI7` reader - EXTI7 configuration"]
pub type EXTI7_R = crate :: FieldReader ; # [doc = "Field `EXTI7` writer - EXTI7 configuration"]
pub type EXTI7_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - EXTI4 configuration"]
# [inline (always)]
pub fn exti4 (& self) -> EXTI4_R { EXTI4_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - EXTI5 configuration"]
# [inline (always)]
pub fn exti5 (& self) -> EXTI5_R { EXTI5_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - EXTI6 configuration"]
# [inline (always)]
pub fn exti6 (& self) -> EXTI6_R { EXTI6_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - EXTI7 configuration"]
# [inline (always)]
pub fn exti7 (& self) -> EXTI7_R { EXTI7_R :: new (((self . bits >> 12) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - EXTI4 configuration"]
# [inline (always)]
# [must_use]
pub fn exti4 (& mut self) -> EXTI4_W < EXTICR2_SPEC > { EXTI4_W :: new (self , 0) } # [doc = "Bits 4:7 - EXTI5 configuration"]
# [inline (always)]
# [must_use]
pub fn exti5 (& mut self) -> EXTI5_W < EXTICR2_SPEC > { EXTI5_W :: new (self , 4) } # [doc = "Bits 8:11 - EXTI6 configuration"]
# [inline (always)]
# [must_use]
pub fn exti6 (& mut self) -> EXTI6_W < EXTICR2_SPEC > { EXTI6_W :: new (self , 8) } # [doc = "Bits 12:15 - EXTI7 configuration"]
# [inline (always)]
# [must_use]
pub fn exti7 (& mut self) -> EXTI7_W < EXTICR2_SPEC > { EXTI7_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "External interrupt configuration register 2 (AFIO_EXTICR2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exticr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exticr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EXTICR2_SPEC ; impl crate :: RegisterSpec for EXTICR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`exticr2::R`](R) reader structure"]
impl crate :: Readable for EXTICR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`exticr2::W`](W) writer structure"]
impl crate :: Writable for EXTICR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EXTICR2 to value 0"]
impl crate :: Resettable for EXTICR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "EXTICR3 (rw) register accessor: External interrupt configuration register 3 (AFIO_EXTICR3)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exticr3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exticr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exticr3`]
module"]
pub type EXTICR3 = crate :: Reg < exticr3 :: EXTICR3_SPEC > ; # [doc = "External interrupt configuration register 3 (AFIO_EXTICR3)"]
pub mod exticr3 { # [doc = "Register `EXTICR3` reader"]
pub type R = crate :: R < EXTICR3_SPEC > ; # [doc = "Register `EXTICR3` writer"]
pub type W = crate :: W < EXTICR3_SPEC > ; # [doc = "Field `EXTI8` reader - EXTI8 configuration"]
pub type EXTI8_R = crate :: FieldReader ; # [doc = "Field `EXTI8` writer - EXTI8 configuration"]
pub type EXTI8_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EXTI9` reader - EXTI9 configuration"]
pub type EXTI9_R = crate :: FieldReader ; # [doc = "Field `EXTI9` writer - EXTI9 configuration"]
pub type EXTI9_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EXTI10` reader - EXTI10 configuration"]
pub type EXTI10_R = crate :: FieldReader ; # [doc = "Field `EXTI10` writer - EXTI10 configuration"]
pub type EXTI10_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EXTI11` reader - EXTI11 configuration"]
pub type EXTI11_R = crate :: FieldReader ; # [doc = "Field `EXTI11` writer - EXTI11 configuration"]
pub type EXTI11_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - EXTI8 configuration"]
# [inline (always)]
pub fn exti8 (& self) -> EXTI8_R { EXTI8_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - EXTI9 configuration"]
# [inline (always)]
pub fn exti9 (& self) -> EXTI9_R { EXTI9_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - EXTI10 configuration"]
# [inline (always)]
pub fn exti10 (& self) -> EXTI10_R { EXTI10_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - EXTI11 configuration"]
# [inline (always)]
pub fn exti11 (& self) -> EXTI11_R { EXTI11_R :: new (((self . bits >> 12) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - EXTI8 configuration"]
# [inline (always)]
# [must_use]
pub fn exti8 (& mut self) -> EXTI8_W < EXTICR3_SPEC > { EXTI8_W :: new (self , 0) } # [doc = "Bits 4:7 - EXTI9 configuration"]
# [inline (always)]
# [must_use]
pub fn exti9 (& mut self) -> EXTI9_W < EXTICR3_SPEC > { EXTI9_W :: new (self , 4) } # [doc = "Bits 8:11 - EXTI10 configuration"]
# [inline (always)]
# [must_use]
pub fn exti10 (& mut self) -> EXTI10_W < EXTICR3_SPEC > { EXTI10_W :: new (self , 8) } # [doc = "Bits 12:15 - EXTI11 configuration"]
# [inline (always)]
# [must_use]
pub fn exti11 (& mut self) -> EXTI11_W < EXTICR3_SPEC > { EXTI11_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "External interrupt configuration register 3 (AFIO_EXTICR3)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exticr3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exticr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EXTICR3_SPEC ; impl crate :: RegisterSpec for EXTICR3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`exticr3::R`](R) reader structure"]
impl crate :: Readable for EXTICR3_SPEC { } # [doc = "`write(|w| ..)` method takes [`exticr3::W`](W) writer structure"]
impl crate :: Writable for EXTICR3_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EXTICR3 to value 0"]
impl crate :: Resettable for EXTICR3_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "EXTICR4 (rw) register accessor: External interrupt configuration register 4 (AFIO_EXTICR4)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exticr4::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exticr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exticr4`]
module"]
pub type EXTICR4 = crate :: Reg < exticr4 :: EXTICR4_SPEC > ; # [doc = "External interrupt configuration register 4 (AFIO_EXTICR4)"]
pub mod exticr4 { # [doc = "Register `EXTICR4` reader"]
pub type R = crate :: R < EXTICR4_SPEC > ; # [doc = "Register `EXTICR4` writer"]
pub type W = crate :: W < EXTICR4_SPEC > ; # [doc = "Field `EXTI12` reader - EXTI12 configuration"]
pub type EXTI12_R = crate :: FieldReader ; # [doc = "Field `EXTI12` writer - EXTI12 configuration"]
pub type EXTI12_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EXTI13` reader - EXTI13 configuration"]
pub type EXTI13_R = crate :: FieldReader ; # [doc = "Field `EXTI13` writer - EXTI13 configuration"]
pub type EXTI13_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EXTI14` reader - EXTI14 configuration"]
pub type EXTI14_R = crate :: FieldReader ; # [doc = "Field `EXTI14` writer - EXTI14 configuration"]
pub type EXTI14_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `EXTI15` reader - EXTI15 configuration"]
pub type EXTI15_R = crate :: FieldReader ; # [doc = "Field `EXTI15` writer - EXTI15 configuration"]
pub type EXTI15_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - EXTI12 configuration"]
# [inline (always)]
pub fn exti12 (& self) -> EXTI12_R { EXTI12_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - EXTI13 configuration"]
# [inline (always)]
pub fn exti13 (& self) -> EXTI13_R { EXTI13_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - EXTI14 configuration"]
# [inline (always)]
pub fn exti14 (& self) -> EXTI14_R { EXTI14_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - EXTI15 configuration"]
# [inline (always)]
pub fn exti15 (& self) -> EXTI15_R { EXTI15_R :: new (((self . bits >> 12) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - EXTI12 configuration"]
# [inline (always)]
# [must_use]
pub fn exti12 (& mut self) -> EXTI12_W < EXTICR4_SPEC > { EXTI12_W :: new (self , 0) } # [doc = "Bits 4:7 - EXTI13 configuration"]
# [inline (always)]
# [must_use]
pub fn exti13 (& mut self) -> EXTI13_W < EXTICR4_SPEC > { EXTI13_W :: new (self , 4) } # [doc = "Bits 8:11 - EXTI14 configuration"]
# [inline (always)]
# [must_use]
pub fn exti14 (& mut self) -> EXTI14_W < EXTICR4_SPEC > { EXTI14_W :: new (self , 8) } # [doc = "Bits 12:15 - EXTI15 configuration"]
# [inline (always)]
# [must_use]
pub fn exti15 (& mut self) -> EXTI15_W < EXTICR4_SPEC > { EXTI15_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "External interrupt configuration register 4 (AFIO_EXTICR4)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exticr4::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exticr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EXTICR4_SPEC ; impl crate :: RegisterSpec for EXTICR4_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`exticr4::R`](R) reader structure"]
impl crate :: Readable for EXTICR4_SPEC { } # [doc = "`write(|w| ..)` method takes [`exticr4::W`](W) writer structure"]
impl crate :: Writable for EXTICR4_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EXTICR4 to value 0"]
impl crate :: Resettable for EXTICR4_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "PCFR2 (rw) register accessor: AF remap and debug I/O configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcfr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcfr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcfr2`]
module"]
pub type PCFR2 = crate :: Reg < pcfr2 :: PCFR2_SPEC > ; # [doc = "AF remap and debug I/O configuration register"]
pub mod pcfr2 { # [doc = "Register `PCFR2` reader"]
pub type R = crate :: R < PCFR2_SPEC > ; # [doc = "Register `PCFR2` writer"]
pub type W = crate :: W < PCFR2_SPEC > ; # [doc = "Field `TIM9_REMAP` reader - TIM9 remapping"]
pub type TIM9_REMAP_R = crate :: BitReader ; # [doc = "Field `TIM9_REMAP` writer - TIM9 remapping"]
pub type TIM9_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIM10_REMAP` reader - TIM10 remapping"]
pub type TIM10_REMAP_R = crate :: BitReader ; # [doc = "Field `TIM10_REMAP` writer - TIM10 remapping"]
pub type TIM10_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIM11_REMAP` reader - TIM11 remapping"]
pub type TIM11_REMAP_R = crate :: BitReader ; # [doc = "Field `TIM11_REMAP` writer - TIM11 remapping"]
pub type TIM11_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIM13_REMAP` reader - TIM13 remapping"]
pub type TIM13_REMAP_R = crate :: BitReader ; # [doc = "Field `TIM13_REMAP` writer - TIM13 remapping"]
pub type TIM13_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIM14_REMAP` reader - TIM14 remapping"]
pub type TIM14_REMAP_R = crate :: BitReader ; # [doc = "Field `TIM14_REMAP` writer - TIM14 remapping"]
pub type TIM14_REMAP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FSMC_NADV` reader - NADV connect/disconnect"]
pub type FSMC_NADV_R = crate :: BitReader ; # [doc = "Field `FSMC_NADV` writer - NADV connect/disconnect"]
pub type FSMC_NADV_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 5 - TIM9 remapping"]
# [inline (always)]
pub fn tim9_remap (& self) -> TIM9_REMAP_R { TIM9_REMAP_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TIM10 remapping"]
# [inline (always)]
pub fn tim10_remap (& self) -> TIM10_REMAP_R { TIM10_REMAP_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - TIM11 remapping"]
# [inline (always)]
pub fn tim11_remap (& self) -> TIM11_REMAP_R { TIM11_REMAP_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - TIM13 remapping"]
# [inline (always)]
pub fn tim13_remap (& self) -> TIM13_REMAP_R { TIM13_REMAP_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - TIM14 remapping"]
# [inline (always)]
pub fn tim14_remap (& self) -> TIM14_REMAP_R { TIM14_REMAP_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - NADV connect/disconnect"]
# [inline (always)]
pub fn fsmc_nadv (& self) -> FSMC_NADV_R { FSMC_NADV_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 5 - TIM9 remapping"]
# [inline (always)]
# [must_use]
pub fn tim9_remap (& mut self) -> TIM9_REMAP_W < PCFR2_SPEC > { TIM9_REMAP_W :: new (self , 5) } # [doc = "Bit 6 - TIM10 remapping"]
# [inline (always)]
# [must_use]
pub fn tim10_remap (& mut self) -> TIM10_REMAP_W < PCFR2_SPEC > { TIM10_REMAP_W :: new (self , 6) } # [doc = "Bit 7 - TIM11 remapping"]
# [inline (always)]
# [must_use]
pub fn tim11_remap (& mut self) -> TIM11_REMAP_W < PCFR2_SPEC > { TIM11_REMAP_W :: new (self , 7) } # [doc = "Bit 8 - TIM13 remapping"]
# [inline (always)]
# [must_use]
pub fn tim13_remap (& mut self) -> TIM13_REMAP_W < PCFR2_SPEC > { TIM13_REMAP_W :: new (self , 8) } # [doc = "Bit 9 - TIM14 remapping"]
# [inline (always)]
# [must_use]
pub fn tim14_remap (& mut self) -> TIM14_REMAP_W < PCFR2_SPEC > { TIM14_REMAP_W :: new (self , 9) } # [doc = "Bit 10 - NADV connect/disconnect"]
# [inline (always)]
# [must_use]
pub fn fsmc_nadv (& mut self) -> FSMC_NADV_W < PCFR2_SPEC > { FSMC_NADV_W :: new (self , 10) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "AF remap and debug I/O configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcfr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcfr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PCFR2_SPEC ; impl crate :: RegisterSpec for PCFR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pcfr2::R`](R) reader structure"]
impl crate :: Readable for PCFR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`pcfr2::W`](W) writer structure"]
impl crate :: Writable for PCFR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PCFR2 to value 0"]
impl crate :: Resettable for PCFR2_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "EXTI"]
pub struct EXTI { _marker : PhantomData < * const () > } unsafe impl Send for EXTI { } impl EXTI { # [doc = r"Pointer to the register block"]
pub const PTR : * const exti :: RegisterBlock = 0x4001_0400 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const exti :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for EXTI { type Target = exti :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for EXTI { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("EXTI") . finish () } } # [doc = "EXTI"]
pub mod exti { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { intenr : INTENR , evenr : EVENR , rtenr : RTENR , ftenr : FTENR , swievr : SWIEVR , intfr : INTFR , } impl RegisterBlock { # [doc = "0x00 - Interrupt mask register(EXTI_INTENR)"]
# [inline (always)]
pub const fn intenr (& self) -> & INTENR { & self . intenr } # [doc = "0x04 - Event mask register (EXTI_EVENR)"]
# [inline (always)]
pub const fn evenr (& self) -> & EVENR { & self . evenr } # [doc = "0x08 - Rising Trigger selection register(EXTI_RTENR)"]
# [inline (always)]
pub const fn rtenr (& self) -> & RTENR { & self . rtenr } # [doc = "0x0c - Falling Trigger selection register(EXTI_FTENR)"]
# [inline (always)]
pub const fn ftenr (& self) -> & FTENR { & self . ftenr } # [doc = "0x10 - Software interrupt event register(EXTI_SWIEVR)"]
# [inline (always)]
pub const fn swievr (& self) -> & SWIEVR { & self . swievr } # [doc = "0x14 - Pending register (EXTI_INTFR)"]
# [inline (always)]
pub const fn intfr (& self) -> & INTFR { & self . intfr } } # [doc = "INTENR (rw) register accessor: Interrupt mask register(EXTI_INTENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intenr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intenr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intenr`]
module"]
pub type INTENR = crate :: Reg < intenr :: INTENR_SPEC > ; # [doc = "Interrupt mask register(EXTI_INTENR)"]
pub mod intenr { # [doc = "Register `INTENR` reader"]
pub type R = crate :: R < INTENR_SPEC > ; # [doc = "Register `INTENR` writer"]
pub type W = crate :: W < INTENR_SPEC > ; # [doc = "Field `MR0` reader - Interrupt Mask on line 0"]
pub type MR0_R = crate :: BitReader ; # [doc = "Field `MR0` writer - Interrupt Mask on line 0"]
pub type MR0_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR1` reader - Interrupt Mask on line 1"]
pub type MR1_R = crate :: BitReader ; # [doc = "Field `MR1` writer - Interrupt Mask on line 1"]
pub type MR1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR2` reader - Interrupt Mask on line 2"]
pub type MR2_R = crate :: BitReader ; # [doc = "Field `MR2` writer - Interrupt Mask on line 2"]
pub type MR2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR3` reader - Interrupt Mask on line 3"]
pub type MR3_R = crate :: BitReader ; # [doc = "Field `MR3` writer - Interrupt Mask on line 3"]
pub type MR3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR4` reader - Interrupt Mask on line 4"]
pub type MR4_R = crate :: BitReader ; # [doc = "Field `MR4` writer - Interrupt Mask on line 4"]
pub type MR4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR5` reader - Interrupt Mask on line 5"]
pub type MR5_R = crate :: BitReader ; # [doc = "Field `MR5` writer - Interrupt Mask on line 5"]
pub type MR5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR6` reader - Interrupt Mask on line 6"]
pub type MR6_R = crate :: BitReader ; # [doc = "Field `MR6` writer - Interrupt Mask on line 6"]
pub type MR6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR7` reader - Interrupt Mask on line 7"]
pub type MR7_R = crate :: BitReader ; # [doc = "Field `MR7` writer - Interrupt Mask on line 7"]
pub type MR7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR8` reader - Interrupt Mask on line 8"]
pub type MR8_R = crate :: BitReader ; # [doc = "Field `MR8` writer - Interrupt Mask on line 8"]
pub type MR8_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR9` reader - Interrupt Mask on line 9"]
pub type MR9_R = crate :: BitReader ; # [doc = "Field `MR9` writer - Interrupt Mask on line 9"]
pub type MR9_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR10` reader - Interrupt Mask on line 10"]
pub type MR10_R = crate :: BitReader ; # [doc = "Field `MR10` writer - Interrupt Mask on line 10"]
pub type MR10_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR11` reader - Interrupt Mask on line 11"]
pub type MR11_R = crate :: BitReader ; # [doc = "Field `MR11` writer - Interrupt Mask on line 11"]
pub type MR11_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR12` reader - Interrupt Mask on line 12"]
pub type MR12_R = crate :: BitReader ; # [doc = "Field `MR12` writer - Interrupt Mask on line 12"]
pub type MR12_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR13` reader - Interrupt Mask on line 13"]
pub type MR13_R = crate :: BitReader ; # [doc = "Field `MR13` writer - Interrupt Mask on line 13"]
pub type MR13_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR14` reader - Interrupt Mask on line 14"]
pub type MR14_R = crate :: BitReader ; # [doc = "Field `MR14` writer - Interrupt Mask on line 14"]
pub type MR14_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR15` reader - Interrupt Mask on line 15"]
pub type MR15_R = crate :: BitReader ; # [doc = "Field `MR15` writer - Interrupt Mask on line 15"]
pub type MR15_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR16` reader - Interrupt Mask on line 16"]
pub type MR16_R = crate :: BitReader ; # [doc = "Field `MR16` writer - Interrupt Mask on line 16"]
pub type MR16_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR17` reader - Interrupt Mask on line 17"]
pub type MR17_R = crate :: BitReader ; # [doc = "Field `MR17` writer - Interrupt Mask on line 17"]
pub type MR17_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR18` reader - Interrupt Mask on line 18"]
pub type MR18_R = crate :: BitReader ; # [doc = "Field `MR18` writer - Interrupt Mask on line 18"]
pub type MR18_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Interrupt Mask on line 0"]
# [inline (always)]
pub fn mr0 (& self) -> MR0_R { MR0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Interrupt Mask on line 1"]
# [inline (always)]
pub fn mr1 (& self) -> MR1_R { MR1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Interrupt Mask on line 2"]
# [inline (always)]
pub fn mr2 (& self) -> MR2_R { MR2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Interrupt Mask on line 3"]
# [inline (always)]
pub fn mr3 (& self) -> MR3_R { MR3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Interrupt Mask on line 4"]
# [inline (always)]
pub fn mr4 (& self) -> MR4_R { MR4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Interrupt Mask on line 5"]
# [inline (always)]
pub fn mr5 (& self) -> MR5_R { MR5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Interrupt Mask on line 6"]
# [inline (always)]
pub fn mr6 (& self) -> MR6_R { MR6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Interrupt Mask on line 7"]
# [inline (always)]
pub fn mr7 (& self) -> MR7_R { MR7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Interrupt Mask on line 8"]
# [inline (always)]
pub fn mr8 (& self) -> MR8_R { MR8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Interrupt Mask on line 9"]
# [inline (always)]
pub fn mr9 (& self) -> MR9_R { MR9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Interrupt Mask on line 10"]
# [inline (always)]
pub fn mr10 (& self) -> MR10_R { MR10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Interrupt Mask on line 11"]
# [inline (always)]
pub fn mr11 (& self) -> MR11_R { MR11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Interrupt Mask on line 12"]
# [inline (always)]
pub fn mr12 (& self) -> MR12_R { MR12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Interrupt Mask on line 13"]
# [inline (always)]
pub fn mr13 (& self) -> MR13_R { MR13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Interrupt Mask on line 14"]
# [inline (always)]
pub fn mr14 (& self) -> MR14_R { MR14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Interrupt Mask on line 15"]
# [inline (always)]
pub fn mr15 (& self) -> MR15_R { MR15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Interrupt Mask on line 16"]
# [inline (always)]
pub fn mr16 (& self) -> MR16_R { MR16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Interrupt Mask on line 17"]
# [inline (always)]
pub fn mr17 (& self) -> MR17_R { MR17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Interrupt Mask on line 18"]
# [inline (always)]
pub fn mr18 (& self) -> MR18_R { MR18_R :: new (((self . bits >> 18) & 1) != 0) } } impl W { # [doc = "Bit 0 - Interrupt Mask on line 0"]
# [inline (always)]
# [must_use]
pub fn mr0 (& mut self) -> MR0_W < INTENR_SPEC > { MR0_W :: new (self , 0) } # [doc = "Bit 1 - Interrupt Mask on line 1"]
# [inline (always)]
# [must_use]
pub fn mr1 (& mut self) -> MR1_W < INTENR_SPEC > { MR1_W :: new (self , 1) } # [doc = "Bit 2 - Interrupt Mask on line 2"]
# [inline (always)]
# [must_use]
pub fn mr2 (& mut self) -> MR2_W < INTENR_SPEC > { MR2_W :: new (self , 2) } # [doc = "Bit 3 - Interrupt Mask on line 3"]
# [inline (always)]
# [must_use]
pub fn mr3 (& mut self) -> MR3_W < INTENR_SPEC > { MR3_W :: new (self , 3) } # [doc = "Bit 4 - Interrupt Mask on line 4"]
# [inline (always)]
# [must_use]
pub fn mr4 (& mut self) -> MR4_W < INTENR_SPEC > { MR4_W :: new (self , 4) } # [doc = "Bit 5 - Interrupt Mask on line 5"]
# [inline (always)]
# [must_use]
pub fn mr5 (& mut self) -> MR5_W < INTENR_SPEC > { MR5_W :: new (self , 5) } # [doc = "Bit 6 - Interrupt Mask on line 6"]
# [inline (always)]
# [must_use]
pub fn mr6 (& mut self) -> MR6_W < INTENR_SPEC > { MR6_W :: new (self , 6) } # [doc = "Bit 7 - Interrupt Mask on line 7"]
# [inline (always)]
# [must_use]
pub fn mr7 (& mut self) -> MR7_W < INTENR_SPEC > { MR7_W :: new (self , 7) } # [doc = "Bit 8 - Interrupt Mask on line 8"]
# [inline (always)]
# [must_use]
pub fn mr8 (& mut self) -> MR8_W < INTENR_SPEC > { MR8_W :: new (self , 8) } # [doc = "Bit 9 - Interrupt Mask on line 9"]
# [inline (always)]
# [must_use]
pub fn mr9 (& mut self) -> MR9_W < INTENR_SPEC > { MR9_W :: new (self , 9) } # [doc = "Bit 10 - Interrupt Mask on line 10"]
# [inline (always)]
# [must_use]
pub fn mr10 (& mut self) -> MR10_W < INTENR_SPEC > { MR10_W :: new (self , 10) } # [doc = "Bit 11 - Interrupt Mask on line 11"]
# [inline (always)]
# [must_use]
pub fn mr11 (& mut self) -> MR11_W < INTENR_SPEC > { MR11_W :: new (self , 11) } # [doc = "Bit 12 - Interrupt Mask on line 12"]
# [inline (always)]
# [must_use]
pub fn mr12 (& mut self) -> MR12_W < INTENR_SPEC > { MR12_W :: new (self , 12) } # [doc = "Bit 13 - Interrupt Mask on line 13"]
# [inline (always)]
# [must_use]
pub fn mr13 (& mut self) -> MR13_W < INTENR_SPEC > { MR13_W :: new (self , 13) } # [doc = "Bit 14 - Interrupt Mask on line 14"]
# [inline (always)]
# [must_use]
pub fn mr14 (& mut self) -> MR14_W < INTENR_SPEC > { MR14_W :: new (self , 14) } # [doc = "Bit 15 - Interrupt Mask on line 15"]
# [inline (always)]
# [must_use]
pub fn mr15 (& mut self) -> MR15_W < INTENR_SPEC > { MR15_W :: new (self , 15) } # [doc = "Bit 16 - Interrupt Mask on line 16"]
# [inline (always)]
# [must_use]
pub fn mr16 (& mut self) -> MR16_W < INTENR_SPEC > { MR16_W :: new (self , 16) } # [doc = "Bit 17 - Interrupt Mask on line 17"]
# [inline (always)]
# [must_use]
pub fn mr17 (& mut self) -> MR17_W < INTENR_SPEC > { MR17_W :: new (self , 17) } # [doc = "Bit 18 - Interrupt Mask on line 18"]
# [inline (always)]
# [must_use]
pub fn mr18 (& mut self) -> MR18_W < INTENR_SPEC > { MR18_W :: new (self , 18) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask register(EXTI_INTENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intenr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intenr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTENR_SPEC ; impl crate :: RegisterSpec for INTENR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`intenr::R`](R) reader structure"]
impl crate :: Readable for INTENR_SPEC { } # [doc = "`write(|w| ..)` method takes [`intenr::W`](W) writer structure"]
impl crate :: Writable for INTENR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTENR to value 0"]
impl crate :: Resettable for INTENR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "EVENR (rw) register accessor: Event mask register (EXTI_EVENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evenr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evenr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evenr`]
module"]
pub type EVENR = crate :: Reg < evenr :: EVENR_SPEC > ; # [doc = "Event mask register (EXTI_EVENR)"]
pub mod evenr { # [doc = "Register `EVENR` reader"]
pub type R = crate :: R < EVENR_SPEC > ; # [doc = "Register `EVENR` writer"]
pub type W = crate :: W < EVENR_SPEC > ; # [doc = "Field `MR0` reader - Event Mask on line 0"]
pub type MR0_R = crate :: BitReader ; # [doc = "Field `MR0` writer - Event Mask on line 0"]
pub type MR0_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR1` reader - Event Mask on line 1"]
pub type MR1_R = crate :: BitReader ; # [doc = "Field `MR1` writer - Event Mask on line 1"]
pub type MR1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR2` reader - Event Mask on line 2"]
pub type MR2_R = crate :: BitReader ; # [doc = "Field `MR2` writer - Event Mask on line 2"]
pub type MR2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR3` reader - Event Mask on line 3"]
pub type MR3_R = crate :: BitReader ; # [doc = "Field `MR3` writer - Event Mask on line 3"]
pub type MR3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR4` reader - Event Mask on line 4"]
pub type MR4_R = crate :: BitReader ; # [doc = "Field `MR4` writer - Event Mask on line 4"]
pub type MR4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR5` reader - Event Mask on line 5"]
pub type MR5_R = crate :: BitReader ; # [doc = "Field `MR5` writer - Event Mask on line 5"]
pub type MR5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR6` reader - Event Mask on line 6"]
pub type MR6_R = crate :: BitReader ; # [doc = "Field `MR6` writer - Event Mask on line 6"]
pub type MR6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR7` reader - Event Mask on line 7"]
pub type MR7_R = crate :: BitReader ; # [doc = "Field `MR7` writer - Event Mask on line 7"]
pub type MR7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR8` reader - Event Mask on line 8"]
pub type MR8_R = crate :: BitReader ; # [doc = "Field `MR8` writer - Event Mask on line 8"]
pub type MR8_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR9` reader - Event Mask on line 9"]
pub type MR9_R = crate :: BitReader ; # [doc = "Field `MR9` writer - Event Mask on line 9"]
pub type MR9_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR10` reader - Event Mask on line 10"]
pub type MR10_R = crate :: BitReader ; # [doc = "Field `MR10` writer - Event Mask on line 10"]
pub type MR10_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR11` reader - Event Mask on line 11"]
pub type MR11_R = crate :: BitReader ; # [doc = "Field `MR11` writer - Event Mask on line 11"]
pub type MR11_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR12` reader - Event Mask on line 12"]
pub type MR12_R = crate :: BitReader ; # [doc = "Field `MR12` writer - Event Mask on line 12"]
pub type MR12_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR13` reader - Event Mask on line 13"]
pub type MR13_R = crate :: BitReader ; # [doc = "Field `MR13` writer - Event Mask on line 13"]
pub type MR13_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR14` reader - Event Mask on line 14"]
pub type MR14_R = crate :: BitReader ; # [doc = "Field `MR14` writer - Event Mask on line 14"]
pub type MR14_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR15` reader - Event Mask on line 15"]
pub type MR15_R = crate :: BitReader ; # [doc = "Field `MR15` writer - Event Mask on line 15"]
pub type MR15_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR16` reader - Event Mask on line 16"]
pub type MR16_R = crate :: BitReader ; # [doc = "Field `MR16` writer - Event Mask on line 16"]
pub type MR16_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR17` reader - Event Mask on line 17"]
pub type MR17_R = crate :: BitReader ; # [doc = "Field `MR17` writer - Event Mask on line 17"]
pub type MR17_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MR18` reader - Event Mask on line 18"]
pub type MR18_R = crate :: BitReader ; # [doc = "Field `MR18` writer - Event Mask on line 18"]
pub type MR18_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Event Mask on line 0"]
# [inline (always)]
pub fn mr0 (& self) -> MR0_R { MR0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Event Mask on line 1"]
# [inline (always)]
pub fn mr1 (& self) -> MR1_R { MR1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Event Mask on line 2"]
# [inline (always)]
pub fn mr2 (& self) -> MR2_R { MR2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Event Mask on line 3"]
# [inline (always)]
pub fn mr3 (& self) -> MR3_R { MR3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Event Mask on line 4"]
# [inline (always)]
pub fn mr4 (& self) -> MR4_R { MR4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Event Mask on line 5"]
# [inline (always)]
pub fn mr5 (& self) -> MR5_R { MR5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Event Mask on line 6"]
# [inline (always)]
pub fn mr6 (& self) -> MR6_R { MR6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Event Mask on line 7"]
# [inline (always)]
pub fn mr7 (& self) -> MR7_R { MR7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Event Mask on line 8"]
# [inline (always)]
pub fn mr8 (& self) -> MR8_R { MR8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Event Mask on line 9"]
# [inline (always)]
pub fn mr9 (& self) -> MR9_R { MR9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Event Mask on line 10"]
# [inline (always)]
pub fn mr10 (& self) -> MR10_R { MR10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Event Mask on line 11"]
# [inline (always)]
pub fn mr11 (& self) -> MR11_R { MR11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Event Mask on line 12"]
# [inline (always)]
pub fn mr12 (& self) -> MR12_R { MR12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Event Mask on line 13"]
# [inline (always)]
pub fn mr13 (& self) -> MR13_R { MR13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Event Mask on line 14"]
# [inline (always)]
pub fn mr14 (& self) -> MR14_R { MR14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Event Mask on line 15"]
# [inline (always)]
pub fn mr15 (& self) -> MR15_R { MR15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Event Mask on line 16"]
# [inline (always)]
pub fn mr16 (& self) -> MR16_R { MR16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Event Mask on line 17"]
# [inline (always)]
pub fn mr17 (& self) -> MR17_R { MR17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Event Mask on line 18"]
# [inline (always)]
pub fn mr18 (& self) -> MR18_R { MR18_R :: new (((self . bits >> 18) & 1) != 0) } } impl W { # [doc = "Bit 0 - Event Mask on line 0"]
# [inline (always)]
# [must_use]
pub fn mr0 (& mut self) -> MR0_W < EVENR_SPEC > { MR0_W :: new (self , 0) } # [doc = "Bit 1 - Event Mask on line 1"]
# [inline (always)]
# [must_use]
pub fn mr1 (& mut self) -> MR1_W < EVENR_SPEC > { MR1_W :: new (self , 1) } # [doc = "Bit 2 - Event Mask on line 2"]
# [inline (always)]
# [must_use]
pub fn mr2 (& mut self) -> MR2_W < EVENR_SPEC > { MR2_W :: new (self , 2) } # [doc = "Bit 3 - Event Mask on line 3"]
# [inline (always)]
# [must_use]
pub fn mr3 (& mut self) -> MR3_W < EVENR_SPEC > { MR3_W :: new (self , 3) } # [doc = "Bit 4 - Event Mask on line 4"]
# [inline (always)]
# [must_use]
pub fn mr4 (& mut self) -> MR4_W < EVENR_SPEC > { MR4_W :: new (self , 4) } # [doc = "Bit 5 - Event Mask on line 5"]
# [inline (always)]
# [must_use]
pub fn mr5 (& mut self) -> MR5_W < EVENR_SPEC > { MR5_W :: new (self , 5) } # [doc = "Bit 6 - Event Mask on line 6"]
# [inline (always)]
# [must_use]
pub fn mr6 (& mut self) -> MR6_W < EVENR_SPEC > { MR6_W :: new (self , 6) } # [doc = "Bit 7 - Event Mask on line 7"]
# [inline (always)]
# [must_use]
pub fn mr7 (& mut self) -> MR7_W < EVENR_SPEC > { MR7_W :: new (self , 7) } # [doc = "Bit 8 - Event Mask on line 8"]
# [inline (always)]
# [must_use]
pub fn mr8 (& mut self) -> MR8_W < EVENR_SPEC > { MR8_W :: new (self , 8) } # [doc = "Bit 9 - Event Mask on line 9"]
# [inline (always)]
# [must_use]
pub fn mr9 (& mut self) -> MR9_W < EVENR_SPEC > { MR9_W :: new (self , 9) } # [doc = "Bit 10 - Event Mask on line 10"]
# [inline (always)]
# [must_use]
pub fn mr10 (& mut self) -> MR10_W < EVENR_SPEC > { MR10_W :: new (self , 10) } # [doc = "Bit 11 - Event Mask on line 11"]
# [inline (always)]
# [must_use]
pub fn mr11 (& mut self) -> MR11_W < EVENR_SPEC > { MR11_W :: new (self , 11) } # [doc = "Bit 12 - Event Mask on line 12"]
# [inline (always)]
# [must_use]
pub fn mr12 (& mut self) -> MR12_W < EVENR_SPEC > { MR12_W :: new (self , 12) } # [doc = "Bit 13 - Event Mask on line 13"]
# [inline (always)]
# [must_use]
pub fn mr13 (& mut self) -> MR13_W < EVENR_SPEC > { MR13_W :: new (self , 13) } # [doc = "Bit 14 - Event Mask on line 14"]
# [inline (always)]
# [must_use]
pub fn mr14 (& mut self) -> MR14_W < EVENR_SPEC > { MR14_W :: new (self , 14) } # [doc = "Bit 15 - Event Mask on line 15"]
# [inline (always)]
# [must_use]
pub fn mr15 (& mut self) -> MR15_W < EVENR_SPEC > { MR15_W :: new (self , 15) } # [doc = "Bit 16 - Event Mask on line 16"]
# [inline (always)]
# [must_use]
pub fn mr16 (& mut self) -> MR16_W < EVENR_SPEC > { MR16_W :: new (self , 16) } # [doc = "Bit 17 - Event Mask on line 17"]
# [inline (always)]
# [must_use]
pub fn mr17 (& mut self) -> MR17_W < EVENR_SPEC > { MR17_W :: new (self , 17) } # [doc = "Bit 18 - Event Mask on line 18"]
# [inline (always)]
# [must_use]
pub fn mr18 (& mut self) -> MR18_W < EVENR_SPEC > { MR18_W :: new (self , 18) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event mask register (EXTI_EVENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evenr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evenr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVENR_SPEC ; impl crate :: RegisterSpec for EVENR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evenr::R`](R) reader structure"]
impl crate :: Readable for EVENR_SPEC { } # [doc = "`write(|w| ..)` method takes [`evenr::W`](W) writer structure"]
impl crate :: Writable for EVENR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets EVENR to value 0"]
impl crate :: Resettable for EVENR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTENR (rw) register accessor: Rising Trigger selection register(EXTI_RTENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtenr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtenr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtenr`]
module"]
pub type RTENR = crate :: Reg < rtenr :: RTENR_SPEC > ; # [doc = "Rising Trigger selection register(EXTI_RTENR)"]
pub mod rtenr { # [doc = "Register `RTENR` reader"]
pub type R = crate :: R < RTENR_SPEC > ; # [doc = "Register `RTENR` writer"]
pub type W = crate :: W < RTENR_SPEC > ; # [doc = "Field `TR0` reader - Rising trigger event configuration of line 0"]
pub type TR0_R = crate :: BitReader ; # [doc = "Field `TR0` writer - Rising trigger event configuration of line 0"]
pub type TR0_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR1` reader - Rising trigger event configuration of line 1"]
pub type TR1_R = crate :: BitReader ; # [doc = "Field `TR1` writer - Rising trigger event configuration of line 1"]
pub type TR1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR2` reader - Rising trigger event configuration of line 2"]
pub type TR2_R = crate :: BitReader ; # [doc = "Field `TR2` writer - Rising trigger event configuration of line 2"]
pub type TR2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR3` reader - Rising trigger event configuration of line 3"]
pub type TR3_R = crate :: BitReader ; # [doc = "Field `TR3` writer - Rising trigger event configuration of line 3"]
pub type TR3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR4` reader - Rising trigger event configuration of line 4"]
pub type TR4_R = crate :: BitReader ; # [doc = "Field `TR4` writer - Rising trigger event configuration of line 4"]
pub type TR4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR5` reader - Rising trigger event configuration of line 5"]
pub type TR5_R = crate :: BitReader ; # [doc = "Field `TR5` writer - Rising trigger event configuration of line 5"]
pub type TR5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR6` reader - Rising trigger event configuration of line 6"]
pub type TR6_R = crate :: BitReader ; # [doc = "Field `TR6` writer - Rising trigger event configuration of line 6"]
pub type TR6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR7` reader - Rising trigger event configuration of line 7"]
pub type TR7_R = crate :: BitReader ; # [doc = "Field `TR7` writer - Rising trigger event configuration of line 7"]
pub type TR7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR8` reader - Rising trigger event configuration of line 8"]
pub type TR8_R = crate :: BitReader ; # [doc = "Field `TR8` writer - Rising trigger event configuration of line 8"]
pub type TR8_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR9` reader - Rising trigger event configuration of line 9"]
pub type TR9_R = crate :: BitReader ; # [doc = "Field `TR9` writer - Rising trigger event configuration of line 9"]
pub type TR9_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR10` reader - Rising trigger event configuration of line 10"]
pub type TR10_R = crate :: BitReader ; # [doc = "Field `TR10` writer - Rising trigger event configuration of line 10"]
pub type TR10_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR11` reader - Rising trigger event configuration of line 11"]
pub type TR11_R = crate :: BitReader ; # [doc = "Field `TR11` writer - Rising trigger event configuration of line 11"]
pub type TR11_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR12` reader - Rising trigger event configuration of line 12"]
pub type TR12_R = crate :: BitReader ; # [doc = "Field `TR12` writer - Rising trigger event configuration of line 12"]
pub type TR12_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR13` reader - Rising trigger event configuration of line 13"]
pub type TR13_R = crate :: BitReader ; # [doc = "Field `TR13` writer - Rising trigger event configuration of line 13"]
pub type TR13_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR14` reader - Rising trigger event configuration of line 14"]
pub type TR14_R = crate :: BitReader ; # [doc = "Field `TR14` writer - Rising trigger event configuration of line 14"]
pub type TR14_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR15` reader - Rising trigger event configuration of line 15"]
pub type TR15_R = crate :: BitReader ; # [doc = "Field `TR15` writer - Rising trigger event configuration of line 15"]
pub type TR15_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR16` reader - Rising trigger event configuration of line 16"]
pub type TR16_R = crate :: BitReader ; # [doc = "Field `TR16` writer - Rising trigger event configuration of line 16"]
pub type TR16_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR17` reader - Rising trigger event configuration of line 17"]
pub type TR17_R = crate :: BitReader ; # [doc = "Field `TR17` writer - Rising trigger event configuration of line 17"]
pub type TR17_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR18` reader - Rising trigger event configuration of line 18"]
pub type TR18_R = crate :: BitReader ; # [doc = "Field `TR18` writer - Rising trigger event configuration of line 18"]
pub type TR18_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Rising trigger event configuration of line 0"]
# [inline (always)]
pub fn tr0 (& self) -> TR0_R { TR0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Rising trigger event configuration of line 1"]
# [inline (always)]
pub fn tr1 (& self) -> TR1_R { TR1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Rising trigger event configuration of line 2"]
# [inline (always)]
pub fn tr2 (& self) -> TR2_R { TR2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Rising trigger event configuration of line 3"]
# [inline (always)]
pub fn tr3 (& self) -> TR3_R { TR3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Rising trigger event configuration of line 4"]
# [inline (always)]
pub fn tr4 (& self) -> TR4_R { TR4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Rising trigger event configuration of line 5"]
# [inline (always)]
pub fn tr5 (& self) -> TR5_R { TR5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rising trigger event configuration of line 6"]
# [inline (always)]
pub fn tr6 (& self) -> TR6_R { TR6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Rising trigger event configuration of line 7"]
# [inline (always)]
pub fn tr7 (& self) -> TR7_R { TR7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Rising trigger event configuration of line 8"]
# [inline (always)]
pub fn tr8 (& self) -> TR8_R { TR8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Rising trigger event configuration of line 9"]
# [inline (always)]
pub fn tr9 (& self) -> TR9_R { TR9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Rising trigger event configuration of line 10"]
# [inline (always)]
pub fn tr10 (& self) -> TR10_R { TR10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Rising trigger event configuration of line 11"]
# [inline (always)]
pub fn tr11 (& self) -> TR11_R { TR11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Rising trigger event configuration of line 12"]
# [inline (always)]
pub fn tr12 (& self) -> TR12_R { TR12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Rising trigger event configuration of line 13"]
# [inline (always)]
pub fn tr13 (& self) -> TR13_R { TR13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Rising trigger event configuration of line 14"]
# [inline (always)]
pub fn tr14 (& self) -> TR14_R { TR14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Rising trigger event configuration of line 15"]
# [inline (always)]
pub fn tr15 (& self) -> TR15_R { TR15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Rising trigger event configuration of line 16"]
# [inline (always)]
pub fn tr16 (& self) -> TR16_R { TR16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Rising trigger event configuration of line 17"]
# [inline (always)]
pub fn tr17 (& self) -> TR17_R { TR17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Rising trigger event configuration of line 18"]
# [inline (always)]
pub fn tr18 (& self) -> TR18_R { TR18_R :: new (((self . bits >> 18) & 1) != 0) } } impl W { # [doc = "Bit 0 - Rising trigger event configuration of line 0"]
# [inline (always)]
# [must_use]
pub fn tr0 (& mut self) -> TR0_W < RTENR_SPEC > { TR0_W :: new (self , 0) } # [doc = "Bit 1 - Rising trigger event configuration of line 1"]
# [inline (always)]
# [must_use]
pub fn tr1 (& mut self) -> TR1_W < RTENR_SPEC > { TR1_W :: new (self , 1) } # [doc = "Bit 2 - Rising trigger event configuration of line 2"]
# [inline (always)]
# [must_use]
pub fn tr2 (& mut self) -> TR2_W < RTENR_SPEC > { TR2_W :: new (self , 2) } # [doc = "Bit 3 - Rising trigger event configuration of line 3"]
# [inline (always)]
# [must_use]
pub fn tr3 (& mut self) -> TR3_W < RTENR_SPEC > { TR3_W :: new (self , 3) } # [doc = "Bit 4 - Rising trigger event configuration of line 4"]
# [inline (always)]
# [must_use]
pub fn tr4 (& mut self) -> TR4_W < RTENR_SPEC > { TR4_W :: new (self , 4) } # [doc = "Bit 5 - Rising trigger event configuration of line 5"]
# [inline (always)]
# [must_use]
pub fn tr5 (& mut self) -> TR5_W < RTENR_SPEC > { TR5_W :: new (self , 5) } # [doc = "Bit 6 - Rising trigger event configuration of line 6"]
# [inline (always)]
# [must_use]
pub fn tr6 (& mut self) -> TR6_W < RTENR_SPEC > { TR6_W :: new (self , 6) } # [doc = "Bit 7 - Rising trigger event configuration of line 7"]
# [inline (always)]
# [must_use]
pub fn tr7 (& mut self) -> TR7_W < RTENR_SPEC > { TR7_W :: new (self , 7) } # [doc = "Bit 8 - Rising trigger event configuration of line 8"]
# [inline (always)]
# [must_use]
pub fn tr8 (& mut self) -> TR8_W < RTENR_SPEC > { TR8_W :: new (self , 8) } # [doc = "Bit 9 - Rising trigger event configuration of line 9"]
# [inline (always)]
# [must_use]
pub fn tr9 (& mut self) -> TR9_W < RTENR_SPEC > { TR9_W :: new (self , 9) } # [doc = "Bit 10 - Rising trigger event configuration of line 10"]
# [inline (always)]
# [must_use]
pub fn tr10 (& mut self) -> TR10_W < RTENR_SPEC > { TR10_W :: new (self , 10) } # [doc = "Bit 11 - Rising trigger event configuration of line 11"]
# [inline (always)]
# [must_use]
pub fn tr11 (& mut self) -> TR11_W < RTENR_SPEC > { TR11_W :: new (self , 11) } # [doc = "Bit 12 - Rising trigger event configuration of line 12"]
# [inline (always)]
# [must_use]
pub fn tr12 (& mut self) -> TR12_W < RTENR_SPEC > { TR12_W :: new (self , 12) } # [doc = "Bit 13 - Rising trigger event configuration of line 13"]
# [inline (always)]
# [must_use]
pub fn tr13 (& mut self) -> TR13_W < RTENR_SPEC > { TR13_W :: new (self , 13) } # [doc = "Bit 14 - Rising trigger event configuration of line 14"]
# [inline (always)]
# [must_use]
pub fn tr14 (& mut self) -> TR14_W < RTENR_SPEC > { TR14_W :: new (self , 14) } # [doc = "Bit 15 - Rising trigger event configuration of line 15"]
# [inline (always)]
# [must_use]
pub fn tr15 (& mut self) -> TR15_W < RTENR_SPEC > { TR15_W :: new (self , 15) } # [doc = "Bit 16 - Rising trigger event configuration of line 16"]
# [inline (always)]
# [must_use]
pub fn tr16 (& mut self) -> TR16_W < RTENR_SPEC > { TR16_W :: new (self , 16) } # [doc = "Bit 17 - Rising trigger event configuration of line 17"]
# [inline (always)]
# [must_use]
pub fn tr17 (& mut self) -> TR17_W < RTENR_SPEC > { TR17_W :: new (self , 17) } # [doc = "Bit 18 - Rising trigger event configuration of line 18"]
# [inline (always)]
# [must_use]
pub fn tr18 (& mut self) -> TR18_W < RTENR_SPEC > { TR18_W :: new (self , 18) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Rising Trigger selection register(EXTI_RTENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtenr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtenr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RTENR_SPEC ; impl crate :: RegisterSpec for RTENR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rtenr::R`](R) reader structure"]
impl crate :: Readable for RTENR_SPEC { } # [doc = "`write(|w| ..)` method takes [`rtenr::W`](W) writer structure"]
impl crate :: Writable for RTENR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTENR to value 0"]
impl crate :: Resettable for RTENR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "FTENR (rw) register accessor: Falling Trigger selection register(EXTI_FTENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ftenr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ftenr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ftenr`]
module"]
pub type FTENR = crate :: Reg < ftenr :: FTENR_SPEC > ; # [doc = "Falling Trigger selection register(EXTI_FTENR)"]
pub mod ftenr { # [doc = "Register `FTENR` reader"]
pub type R = crate :: R < FTENR_SPEC > ; # [doc = "Register `FTENR` writer"]
pub type W = crate :: W < FTENR_SPEC > ; # [doc = "Field `TR0` reader - Falling trigger event configuration of line 0"]
pub type TR0_R = crate :: BitReader ; # [doc = "Field `TR0` writer - Falling trigger event configuration of line 0"]
pub type TR0_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR1` reader - Falling trigger event configuration of line 1"]
pub type TR1_R = crate :: BitReader ; # [doc = "Field `TR1` writer - Falling trigger event configuration of line 1"]
pub type TR1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR2` reader - Falling trigger event configuration of line 2"]
pub type TR2_R = crate :: BitReader ; # [doc = "Field `TR2` writer - Falling trigger event configuration of line 2"]
pub type TR2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR3` reader - Falling trigger event configuration of line 3"]
pub type TR3_R = crate :: BitReader ; # [doc = "Field `TR3` writer - Falling trigger event configuration of line 3"]
pub type TR3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR4` reader - Falling trigger event configuration of line 4"]
pub type TR4_R = crate :: BitReader ; # [doc = "Field `TR4` writer - Falling trigger event configuration of line 4"]
pub type TR4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR5` reader - Falling trigger event configuration of line 5"]
pub type TR5_R = crate :: BitReader ; # [doc = "Field `TR5` writer - Falling trigger event configuration of line 5"]
pub type TR5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR6` reader - Falling trigger event configuration of line 6"]
pub type TR6_R = crate :: BitReader ; # [doc = "Field `TR6` writer - Falling trigger event configuration of line 6"]
pub type TR6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR7` reader - Falling trigger event configuration of line 7"]
pub type TR7_R = crate :: BitReader ; # [doc = "Field `TR7` writer - Falling trigger event configuration of line 7"]
pub type TR7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR8` reader - Falling trigger event configuration of line 8"]
pub type TR8_R = crate :: BitReader ; # [doc = "Field `TR8` writer - Falling trigger event configuration of line 8"]
pub type TR8_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR9` reader - Falling trigger event configuration of line 9"]
pub type TR9_R = crate :: BitReader ; # [doc = "Field `TR9` writer - Falling trigger event configuration of line 9"]
pub type TR9_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR10` reader - Falling trigger event configuration of line 10"]
pub type TR10_R = crate :: BitReader ; # [doc = "Field `TR10` writer - Falling trigger event configuration of line 10"]
pub type TR10_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR11` reader - Falling trigger event configuration of line 11"]
pub type TR11_R = crate :: BitReader ; # [doc = "Field `TR11` writer - Falling trigger event configuration of line 11"]
pub type TR11_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR12` reader - Falling trigger event configuration of line 12"]
pub type TR12_R = crate :: BitReader ; # [doc = "Field `TR12` writer - Falling trigger event configuration of line 12"]
pub type TR12_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR13` reader - Falling trigger event configuration of line 13"]
pub type TR13_R = crate :: BitReader ; # [doc = "Field `TR13` writer - Falling trigger event configuration of line 13"]
pub type TR13_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR14` reader - Falling trigger event configuration of line 14"]
pub type TR14_R = crate :: BitReader ; # [doc = "Field `TR14` writer - Falling trigger event configuration of line 14"]
pub type TR14_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR15` reader - Falling trigger event configuration of line 15"]
pub type TR15_R = crate :: BitReader ; # [doc = "Field `TR15` writer - Falling trigger event configuration of line 15"]
pub type TR15_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR16` reader - Falling trigger event configuration of line 16"]
pub type TR16_R = crate :: BitReader ; # [doc = "Field `TR16` writer - Falling trigger event configuration of line 16"]
pub type TR16_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR17` reader - Falling trigger event configuration of line 17"]
pub type TR17_R = crate :: BitReader ; # [doc = "Field `TR17` writer - Falling trigger event configuration of line 17"]
pub type TR17_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TR18` reader - Falling trigger event configuration of line 18"]
pub type TR18_R = crate :: BitReader ; # [doc = "Field `TR18` writer - Falling trigger event configuration of line 18"]
pub type TR18_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Falling trigger event configuration of line 0"]
# [inline (always)]
pub fn tr0 (& self) -> TR0_R { TR0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Falling trigger event configuration of line 1"]
# [inline (always)]
pub fn tr1 (& self) -> TR1_R { TR1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Falling trigger event configuration of line 2"]
# [inline (always)]
pub fn tr2 (& self) -> TR2_R { TR2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Falling trigger event configuration of line 3"]
# [inline (always)]
pub fn tr3 (& self) -> TR3_R { TR3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Falling trigger event configuration of line 4"]
# [inline (always)]
pub fn tr4 (& self) -> TR4_R { TR4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Falling trigger event configuration of line 5"]
# [inline (always)]
pub fn tr5 (& self) -> TR5_R { TR5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Falling trigger event configuration of line 6"]
# [inline (always)]
pub fn tr6 (& self) -> TR6_R { TR6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Falling trigger event configuration of line 7"]
# [inline (always)]
pub fn tr7 (& self) -> TR7_R { TR7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Falling trigger event configuration of line 8"]
# [inline (always)]
pub fn tr8 (& self) -> TR8_R { TR8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Falling trigger event configuration of line 9"]
# [inline (always)]
pub fn tr9 (& self) -> TR9_R { TR9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Falling trigger event configuration of line 10"]
# [inline (always)]
pub fn tr10 (& self) -> TR10_R { TR10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Falling trigger event configuration of line 11"]
# [inline (always)]
pub fn tr11 (& self) -> TR11_R { TR11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Falling trigger event configuration of line 12"]
# [inline (always)]
pub fn tr12 (& self) -> TR12_R { TR12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Falling trigger event configuration of line 13"]
# [inline (always)]
pub fn tr13 (& self) -> TR13_R { TR13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Falling trigger event configuration of line 14"]
# [inline (always)]
pub fn tr14 (& self) -> TR14_R { TR14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Falling trigger event configuration of line 15"]
# [inline (always)]
pub fn tr15 (& self) -> TR15_R { TR15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Falling trigger event configuration of line 16"]
# [inline (always)]
pub fn tr16 (& self) -> TR16_R { TR16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Falling trigger event configuration of line 17"]
# [inline (always)]
pub fn tr17 (& self) -> TR17_R { TR17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Falling trigger event configuration of line 18"]
# [inline (always)]
pub fn tr18 (& self) -> TR18_R { TR18_R :: new (((self . bits >> 18) & 1) != 0) } } impl W { # [doc = "Bit 0 - Falling trigger event configuration of line 0"]
# [inline (always)]
# [must_use]
pub fn tr0 (& mut self) -> TR0_W < FTENR_SPEC > { TR0_W :: new (self , 0) } # [doc = "Bit 1 - Falling trigger event configuration of line 1"]
# [inline (always)]
# [must_use]
pub fn tr1 (& mut self) -> TR1_W < FTENR_SPEC > { TR1_W :: new (self , 1) } # [doc = "Bit 2 - Falling trigger event configuration of line 2"]
# [inline (always)]
# [must_use]
pub fn tr2 (& mut self) -> TR2_W < FTENR_SPEC > { TR2_W :: new (self , 2) } # [doc = "Bit 3 - Falling trigger event configuration of line 3"]
# [inline (always)]
# [must_use]
pub fn tr3 (& mut self) -> TR3_W < FTENR_SPEC > { TR3_W :: new (self , 3) } # [doc = "Bit 4 - Falling trigger event configuration of line 4"]
# [inline (always)]
# [must_use]
pub fn tr4 (& mut self) -> TR4_W < FTENR_SPEC > { TR4_W :: new (self , 4) } # [doc = "Bit 5 - Falling trigger event configuration of line 5"]
# [inline (always)]
# [must_use]
pub fn tr5 (& mut self) -> TR5_W < FTENR_SPEC > { TR5_W :: new (self , 5) } # [doc = "Bit 6 - Falling trigger event configuration of line 6"]
# [inline (always)]
# [must_use]
pub fn tr6 (& mut self) -> TR6_W < FTENR_SPEC > { TR6_W :: new (self , 6) } # [doc = "Bit 7 - Falling trigger event configuration of line 7"]
# [inline (always)]
# [must_use]
pub fn tr7 (& mut self) -> TR7_W < FTENR_SPEC > { TR7_W :: new (self , 7) } # [doc = "Bit 8 - Falling trigger event configuration of line 8"]
# [inline (always)]
# [must_use]
pub fn tr8 (& mut self) -> TR8_W < FTENR_SPEC > { TR8_W :: new (self , 8) } # [doc = "Bit 9 - Falling trigger event configuration of line 9"]
# [inline (always)]
# [must_use]
pub fn tr9 (& mut self) -> TR9_W < FTENR_SPEC > { TR9_W :: new (self , 9) } # [doc = "Bit 10 - Falling trigger event configuration of line 10"]
# [inline (always)]
# [must_use]
pub fn tr10 (& mut self) -> TR10_W < FTENR_SPEC > { TR10_W :: new (self , 10) } # [doc = "Bit 11 - Falling trigger event configuration of line 11"]
# [inline (always)]
# [must_use]
pub fn tr11 (& mut self) -> TR11_W < FTENR_SPEC > { TR11_W :: new (self , 11) } # [doc = "Bit 12 - Falling trigger event configuration of line 12"]
# [inline (always)]
# [must_use]
pub fn tr12 (& mut self) -> TR12_W < FTENR_SPEC > { TR12_W :: new (self , 12) } # [doc = "Bit 13 - Falling trigger event configuration of line 13"]
# [inline (always)]
# [must_use]
pub fn tr13 (& mut self) -> TR13_W < FTENR_SPEC > { TR13_W :: new (self , 13) } # [doc = "Bit 14 - Falling trigger event configuration of line 14"]
# [inline (always)]
# [must_use]
pub fn tr14 (& mut self) -> TR14_W < FTENR_SPEC > { TR14_W :: new (self , 14) } # [doc = "Bit 15 - Falling trigger event configuration of line 15"]
# [inline (always)]
# [must_use]
pub fn tr15 (& mut self) -> TR15_W < FTENR_SPEC > { TR15_W :: new (self , 15) } # [doc = "Bit 16 - Falling trigger event configuration of line 16"]
# [inline (always)]
# [must_use]
pub fn tr16 (& mut self) -> TR16_W < FTENR_SPEC > { TR16_W :: new (self , 16) } # [doc = "Bit 17 - Falling trigger event configuration of line 17"]
# [inline (always)]
# [must_use]
pub fn tr17 (& mut self) -> TR17_W < FTENR_SPEC > { TR17_W :: new (self , 17) } # [doc = "Bit 18 - Falling trigger event configuration of line 18"]
# [inline (always)]
# [must_use]
pub fn tr18 (& mut self) -> TR18_W < FTENR_SPEC > { TR18_W :: new (self , 18) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Falling Trigger selection register(EXTI_FTENR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ftenr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ftenr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FTENR_SPEC ; impl crate :: RegisterSpec for FTENR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ftenr::R`](R) reader structure"]
impl crate :: Readable for FTENR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ftenr::W`](W) writer structure"]
impl crate :: Writable for FTENR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FTENR to value 0"]
impl crate :: Resettable for FTENR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "SWIEVR (rw) register accessor: Software interrupt event register(EXTI_SWIEVR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swievr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swievr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swievr`]
module"]
pub type SWIEVR = crate :: Reg < swievr :: SWIEVR_SPEC > ; # [doc = "Software interrupt event register(EXTI_SWIEVR)"]
pub mod swievr { # [doc = "Register `SWIEVR` reader"]
pub type R = crate :: R < SWIEVR_SPEC > ; # [doc = "Register `SWIEVR` writer"]
pub type W = crate :: W < SWIEVR_SPEC > ; # [doc = "Field `SWIER0` reader - Software Interrupt on line 0"]
pub type SWIER0_R = crate :: BitReader ; # [doc = "Field `SWIER0` writer - Software Interrupt on line 0"]
pub type SWIER0_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER1` reader - Software Interrupt on line 1"]
pub type SWIER1_R = crate :: BitReader ; # [doc = "Field `SWIER1` writer - Software Interrupt on line 1"]
pub type SWIER1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER2` reader - Software Interrupt on line 2"]
pub type SWIER2_R = crate :: BitReader ; # [doc = "Field `SWIER2` writer - Software Interrupt on line 2"]
pub type SWIER2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER3` reader - Software Interrupt on line 3"]
pub type SWIER3_R = crate :: BitReader ; # [doc = "Field `SWIER3` writer - Software Interrupt on line 3"]
pub type SWIER3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER4` reader - Software Interrupt on line 4"]
pub type SWIER4_R = crate :: BitReader ; # [doc = "Field `SWIER4` writer - Software Interrupt on line 4"]
pub type SWIER4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER5` reader - Software Interrupt on line 5"]
pub type SWIER5_R = crate :: BitReader ; # [doc = "Field `SWIER5` writer - Software Interrupt on line 5"]
pub type SWIER5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER6` reader - Software Interrupt on line 6"]
pub type SWIER6_R = crate :: BitReader ; # [doc = "Field `SWIER6` writer - Software Interrupt on line 6"]
pub type SWIER6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER7` reader - Software Interrupt on line 7"]
pub type SWIER7_R = crate :: BitReader ; # [doc = "Field `SWIER7` writer - Software Interrupt on line 7"]
pub type SWIER7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER8` reader - Software Interrupt on line 8"]
pub type SWIER8_R = crate :: BitReader ; # [doc = "Field `SWIER8` writer - Software Interrupt on line 8"]
pub type SWIER8_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER9` reader - Software Interrupt on line 9"]
pub type SWIER9_R = crate :: BitReader ; # [doc = "Field `SWIER9` writer - Software Interrupt on line 9"]
pub type SWIER9_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER10` reader - Software Interrupt on line 10"]
pub type SWIER10_R = crate :: BitReader ; # [doc = "Field `SWIER10` writer - Software Interrupt on line 10"]
pub type SWIER10_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER11` reader - Software Interrupt on line 11"]
pub type SWIER11_R = crate :: BitReader ; # [doc = "Field `SWIER11` writer - Software Interrupt on line 11"]
pub type SWIER11_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER12` reader - Software Interrupt on line 12"]
pub type SWIER12_R = crate :: BitReader ; # [doc = "Field `SWIER12` writer - Software Interrupt on line 12"]
pub type SWIER12_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER13` reader - Software Interrupt on line 13"]
pub type SWIER13_R = crate :: BitReader ; # [doc = "Field `SWIER13` writer - Software Interrupt on line 13"]
pub type SWIER13_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER14` reader - Software Interrupt on line 14"]
pub type SWIER14_R = crate :: BitReader ; # [doc = "Field `SWIER14` writer - Software Interrupt on line 14"]
pub type SWIER14_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER15` reader - Software Interrupt on line 15"]
pub type SWIER15_R = crate :: BitReader ; # [doc = "Field `SWIER15` writer - Software Interrupt on line 15"]
pub type SWIER15_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER16` reader - Software Interrupt on line 16"]
pub type SWIER16_R = crate :: BitReader ; # [doc = "Field `SWIER16` writer - Software Interrupt on line 16"]
pub type SWIER16_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER17` reader - Software Interrupt on line 17"]
pub type SWIER17_R = crate :: BitReader ; # [doc = "Field `SWIER17` writer - Software Interrupt on line 17"]
pub type SWIER17_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWIER18` reader - Software Interrupt on line 18"]
pub type SWIER18_R = crate :: BitReader ; # [doc = "Field `SWIER18` writer - Software Interrupt on line 18"]
pub type SWIER18_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Software Interrupt on line 0"]
# [inline (always)]
pub fn swier0 (& self) -> SWIER0_R { SWIER0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Software Interrupt on line 1"]
# [inline (always)]
pub fn swier1 (& self) -> SWIER1_R { SWIER1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Software Interrupt on line 2"]
# [inline (always)]
pub fn swier2 (& self) -> SWIER2_R { SWIER2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Software Interrupt on line 3"]
# [inline (always)]
pub fn swier3 (& self) -> SWIER3_R { SWIER3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Software Interrupt on line 4"]
# [inline (always)]
pub fn swier4 (& self) -> SWIER4_R { SWIER4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Software Interrupt on line 5"]
# [inline (always)]
pub fn swier5 (& self) -> SWIER5_R { SWIER5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Software Interrupt on line 6"]
# [inline (always)]
pub fn swier6 (& self) -> SWIER6_R { SWIER6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Software Interrupt on line 7"]
# [inline (always)]
pub fn swier7 (& self) -> SWIER7_R { SWIER7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Software Interrupt on line 8"]
# [inline (always)]
pub fn swier8 (& self) -> SWIER8_R { SWIER8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Software Interrupt on line 9"]
# [inline (always)]
pub fn swier9 (& self) -> SWIER9_R { SWIER9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Software Interrupt on line 10"]
# [inline (always)]
pub fn swier10 (& self) -> SWIER10_R { SWIER10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Software Interrupt on line 11"]
# [inline (always)]
pub fn swier11 (& self) -> SWIER11_R { SWIER11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Software Interrupt on line 12"]
# [inline (always)]
pub fn swier12 (& self) -> SWIER12_R { SWIER12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Software Interrupt on line 13"]
# [inline (always)]
pub fn swier13 (& self) -> SWIER13_R { SWIER13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Software Interrupt on line 14"]
# [inline (always)]
pub fn swier14 (& self) -> SWIER14_R { SWIER14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Software Interrupt on line 15"]
# [inline (always)]
pub fn swier15 (& self) -> SWIER15_R { SWIER15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Software Interrupt on line 16"]
# [inline (always)]
pub fn swier16 (& self) -> SWIER16_R { SWIER16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Software Interrupt on line 17"]
# [inline (always)]
pub fn swier17 (& self) -> SWIER17_R { SWIER17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Software Interrupt on line 18"]
# [inline (always)]
pub fn swier18 (& self) -> SWIER18_R { SWIER18_R :: new (((self . bits >> 18) & 1) != 0) } } impl W { # [doc = "Bit 0 - Software Interrupt on line 0"]
# [inline (always)]
# [must_use]
pub fn swier0 (& mut self) -> SWIER0_W < SWIEVR_SPEC > { SWIER0_W :: new (self , 0) } # [doc = "Bit 1 - Software Interrupt on line 1"]
# [inline (always)]
# [must_use]
pub fn swier1 (& mut self) -> SWIER1_W < SWIEVR_SPEC > { SWIER1_W :: new (self , 1) } # [doc = "Bit 2 - Software Interrupt on line 2"]
# [inline (always)]
# [must_use]
pub fn swier2 (& mut self) -> SWIER2_W < SWIEVR_SPEC > { SWIER2_W :: new (self , 2) } # [doc = "Bit 3 - Software Interrupt on line 3"]
# [inline (always)]
# [must_use]
pub fn swier3 (& mut self) -> SWIER3_W < SWIEVR_SPEC > { SWIER3_W :: new (self , 3) } # [doc = "Bit 4 - Software Interrupt on line 4"]
# [inline (always)]
# [must_use]
pub fn swier4 (& mut self) -> SWIER4_W < SWIEVR_SPEC > { SWIER4_W :: new (self , 4) } # [doc = "Bit 5 - Software Interrupt on line 5"]
# [inline (always)]
# [must_use]
pub fn swier5 (& mut self) -> SWIER5_W < SWIEVR_SPEC > { SWIER5_W :: new (self , 5) } # [doc = "Bit 6 - Software Interrupt on line 6"]
# [inline (always)]
# [must_use]
pub fn swier6 (& mut self) -> SWIER6_W < SWIEVR_SPEC > { SWIER6_W :: new (self , 6) } # [doc = "Bit 7 - Software Interrupt on line 7"]
# [inline (always)]
# [must_use]
pub fn swier7 (& mut self) -> SWIER7_W < SWIEVR_SPEC > { SWIER7_W :: new (self , 7) } # [doc = "Bit 8 - Software Interrupt on line 8"]
# [inline (always)]
# [must_use]
pub fn swier8 (& mut self) -> SWIER8_W < SWIEVR_SPEC > { SWIER8_W :: new (self , 8) } # [doc = "Bit 9 - Software Interrupt on line 9"]
# [inline (always)]
# [must_use]
pub fn swier9 (& mut self) -> SWIER9_W < SWIEVR_SPEC > { SWIER9_W :: new (self , 9) } # [doc = "Bit 10 - Software Interrupt on line 10"]
# [inline (always)]
# [must_use]
pub fn swier10 (& mut self) -> SWIER10_W < SWIEVR_SPEC > { SWIER10_W :: new (self , 10) } # [doc = "Bit 11 - Software Interrupt on line 11"]
# [inline (always)]
# [must_use]
pub fn swier11 (& mut self) -> SWIER11_W < SWIEVR_SPEC > { SWIER11_W :: new (self , 11) } # [doc = "Bit 12 - Software Interrupt on line 12"]
# [inline (always)]
# [must_use]
pub fn swier12 (& mut self) -> SWIER12_W < SWIEVR_SPEC > { SWIER12_W :: new (self , 12) } # [doc = "Bit 13 - Software Interrupt on line 13"]
# [inline (always)]
# [must_use]
pub fn swier13 (& mut self) -> SWIER13_W < SWIEVR_SPEC > { SWIER13_W :: new (self , 13) } # [doc = "Bit 14 - Software Interrupt on line 14"]
# [inline (always)]
# [must_use]
pub fn swier14 (& mut self) -> SWIER14_W < SWIEVR_SPEC > { SWIER14_W :: new (self , 14) } # [doc = "Bit 15 - Software Interrupt on line 15"]
# [inline (always)]
# [must_use]
pub fn swier15 (& mut self) -> SWIER15_W < SWIEVR_SPEC > { SWIER15_W :: new (self , 15) } # [doc = "Bit 16 - Software Interrupt on line 16"]
# [inline (always)]
# [must_use]
pub fn swier16 (& mut self) -> SWIER16_W < SWIEVR_SPEC > { SWIER16_W :: new (self , 16) } # [doc = "Bit 17 - Software Interrupt on line 17"]
# [inline (always)]
# [must_use]
pub fn swier17 (& mut self) -> SWIER17_W < SWIEVR_SPEC > { SWIER17_W :: new (self , 17) } # [doc = "Bit 18 - Software Interrupt on line 18"]
# [inline (always)]
# [must_use]
pub fn swier18 (& mut self) -> SWIER18_W < SWIEVR_SPEC > { SWIER18_W :: new (self , 18) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Software interrupt event register(EXTI_SWIEVR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swievr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swievr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SWIEVR_SPEC ; impl crate :: RegisterSpec for SWIEVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`swievr::R`](R) reader structure"]
impl crate :: Readable for SWIEVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`swievr::W`](W) writer structure"]
impl crate :: Writable for SWIEVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SWIEVR to value 0"]
impl crate :: Resettable for SWIEVR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTFR (rw) register accessor: Pending register (EXTI_INTFR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intfr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intfr`]
module"]
pub type INTFR = crate :: Reg < intfr :: INTFR_SPEC > ; # [doc = "Pending register (EXTI_INTFR)"]
pub mod intfr { # [doc = "Register `INTFR` reader"]
pub type R = crate :: R < INTFR_SPEC > ; # [doc = "Register `INTFR` writer"]
pub type W = crate :: W < INTFR_SPEC > ; # [doc = "Field `PR0` reader - Pending bit 0"]
pub type PR0_R = crate :: BitReader ; # [doc = "Field `PR0` writer - Pending bit 0"]
pub type PR0_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR1` reader - Pending bit 1"]
pub type PR1_R = crate :: BitReader ; # [doc = "Field `PR1` writer - Pending bit 1"]
pub type PR1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR2` reader - Pending bit 2"]
pub type PR2_R = crate :: BitReader ; # [doc = "Field `PR2` writer - Pending bit 2"]
pub type PR2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR3` reader - Pending bit 3"]
pub type PR3_R = crate :: BitReader ; # [doc = "Field `PR3` writer - Pending bit 3"]
pub type PR3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR4` reader - Pending bit 4"]
pub type PR4_R = crate :: BitReader ; # [doc = "Field `PR4` writer - Pending bit 4"]
pub type PR4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR5` reader - Pending bit 5"]
pub type PR5_R = crate :: BitReader ; # [doc = "Field `PR5` writer - Pending bit 5"]
pub type PR5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR6` reader - Pending bit 6"]
pub type PR6_R = crate :: BitReader ; # [doc = "Field `PR6` writer - Pending bit 6"]
pub type PR6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR7` reader - Pending bit 7"]
pub type PR7_R = crate :: BitReader ; # [doc = "Field `PR7` writer - Pending bit 7"]
pub type PR7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR8` reader - Pending bit 8"]
pub type PR8_R = crate :: BitReader ; # [doc = "Field `PR8` writer - Pending bit 8"]
pub type PR8_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR9` reader - Pending bit 9"]
pub type PR9_R = crate :: BitReader ; # [doc = "Field `PR9` writer - Pending bit 9"]
pub type PR9_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR10` reader - Pending bit 10"]
pub type PR10_R = crate :: BitReader ; # [doc = "Field `PR10` writer - Pending bit 10"]
pub type PR10_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR11` reader - Pending bit 11"]
pub type PR11_R = crate :: BitReader ; # [doc = "Field `PR11` writer - Pending bit 11"]
pub type PR11_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR12` reader - Pending bit 12"]
pub type PR12_R = crate :: BitReader ; # [doc = "Field `PR12` writer - Pending bit 12"]
pub type PR12_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR13` reader - Pending bit 13"]
pub type PR13_R = crate :: BitReader ; # [doc = "Field `PR13` writer - Pending bit 13"]
pub type PR13_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR14` reader - Pending bit 14"]
pub type PR14_R = crate :: BitReader ; # [doc = "Field `PR14` writer - Pending bit 14"]
pub type PR14_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR15` reader - Pending bit 15"]
pub type PR15_R = crate :: BitReader ; # [doc = "Field `PR15` writer - Pending bit 15"]
pub type PR15_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR16` reader - Pending bit 16"]
pub type PR16_R = crate :: BitReader ; # [doc = "Field `PR16` writer - Pending bit 16"]
pub type PR16_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR17` reader - Pending bit 17"]
pub type PR17_R = crate :: BitReader ; # [doc = "Field `PR17` writer - Pending bit 17"]
pub type PR17_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PR18` reader - Pending bit 18"]
pub type PR18_R = crate :: BitReader ; # [doc = "Field `PR18` writer - Pending bit 18"]
pub type PR18_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Pending bit 0"]
# [inline (always)]
pub fn pr0 (& self) -> PR0_R { PR0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Pending bit 1"]
# [inline (always)]
pub fn pr1 (& self) -> PR1_R { PR1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Pending bit 2"]
# [inline (always)]
pub fn pr2 (& self) -> PR2_R { PR2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Pending bit 3"]
# [inline (always)]
pub fn pr3 (& self) -> PR3_R { PR3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Pending bit 4"]
# [inline (always)]
pub fn pr4 (& self) -> PR4_R { PR4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Pending bit 5"]
# [inline (always)]
pub fn pr5 (& self) -> PR5_R { PR5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Pending bit 6"]
# [inline (always)]
pub fn pr6 (& self) -> PR6_R { PR6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Pending bit 7"]
# [inline (always)]
pub fn pr7 (& self) -> PR7_R { PR7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Pending bit 8"]
# [inline (always)]
pub fn pr8 (& self) -> PR8_R { PR8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Pending bit 9"]
# [inline (always)]
pub fn pr9 (& self) -> PR9_R { PR9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Pending bit 10"]
# [inline (always)]
pub fn pr10 (& self) -> PR10_R { PR10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Pending bit 11"]
# [inline (always)]
pub fn pr11 (& self) -> PR11_R { PR11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Pending bit 12"]
# [inline (always)]
pub fn pr12 (& self) -> PR12_R { PR12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Pending bit 13"]
# [inline (always)]
pub fn pr13 (& self) -> PR13_R { PR13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Pending bit 14"]
# [inline (always)]
pub fn pr14 (& self) -> PR14_R { PR14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Pending bit 15"]
# [inline (always)]
pub fn pr15 (& self) -> PR15_R { PR15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Pending bit 16"]
# [inline (always)]
pub fn pr16 (& self) -> PR16_R { PR16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Pending bit 17"]
# [inline (always)]
pub fn pr17 (& self) -> PR17_R { PR17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Pending bit 18"]
# [inline (always)]
pub fn pr18 (& self) -> PR18_R { PR18_R :: new (((self . bits >> 18) & 1) != 0) } } impl W { # [doc = "Bit 0 - Pending bit 0"]
# [inline (always)]
# [must_use]
pub fn pr0 (& mut self) -> PR0_W < INTFR_SPEC > { PR0_W :: new (self , 0) } # [doc = "Bit 1 - Pending bit 1"]
# [inline (always)]
# [must_use]
pub fn pr1 (& mut self) -> PR1_W < INTFR_SPEC > { PR1_W :: new (self , 1) } # [doc = "Bit 2 - Pending bit 2"]
# [inline (always)]
# [must_use]
pub fn pr2 (& mut self) -> PR2_W < INTFR_SPEC > { PR2_W :: new (self , 2) } # [doc = "Bit 3 - Pending bit 3"]
# [inline (always)]
# [must_use]
pub fn pr3 (& mut self) -> PR3_W < INTFR_SPEC > { PR3_W :: new (self , 3) } # [doc = "Bit 4 - Pending bit 4"]
# [inline (always)]
# [must_use]
pub fn pr4 (& mut self) -> PR4_W < INTFR_SPEC > { PR4_W :: new (self , 4) } # [doc = "Bit 5 - Pending bit 5"]
# [inline (always)]
# [must_use]
pub fn pr5 (& mut self) -> PR5_W < INTFR_SPEC > { PR5_W :: new (self , 5) } # [doc = "Bit 6 - Pending bit 6"]
# [inline (always)]
# [must_use]
pub fn pr6 (& mut self) -> PR6_W < INTFR_SPEC > { PR6_W :: new (self , 6) } # [doc = "Bit 7 - Pending bit 7"]
# [inline (always)]
# [must_use]
pub fn pr7 (& mut self) -> PR7_W < INTFR_SPEC > { PR7_W :: new (self , 7) } # [doc = "Bit 8 - Pending bit 8"]
# [inline (always)]
# [must_use]
pub fn pr8 (& mut self) -> PR8_W < INTFR_SPEC > { PR8_W :: new (self , 8) } # [doc = "Bit 9 - Pending bit 9"]
# [inline (always)]
# [must_use]
pub fn pr9 (& mut self) -> PR9_W < INTFR_SPEC > { PR9_W :: new (self , 9) } # [doc = "Bit 10 - Pending bit 10"]
# [inline (always)]
# [must_use]
pub fn pr10 (& mut self) -> PR10_W < INTFR_SPEC > { PR10_W :: new (self , 10) } # [doc = "Bit 11 - Pending bit 11"]
# [inline (always)]
# [must_use]
pub fn pr11 (& mut self) -> PR11_W < INTFR_SPEC > { PR11_W :: new (self , 11) } # [doc = "Bit 12 - Pending bit 12"]
# [inline (always)]
# [must_use]
pub fn pr12 (& mut self) -> PR12_W < INTFR_SPEC > { PR12_W :: new (self , 12) } # [doc = "Bit 13 - Pending bit 13"]
# [inline (always)]
# [must_use]
pub fn pr13 (& mut self) -> PR13_W < INTFR_SPEC > { PR13_W :: new (self , 13) } # [doc = "Bit 14 - Pending bit 14"]
# [inline (always)]
# [must_use]
pub fn pr14 (& mut self) -> PR14_W < INTFR_SPEC > { PR14_W :: new (self , 14) } # [doc = "Bit 15 - Pending bit 15"]
# [inline (always)]
# [must_use]
pub fn pr15 (& mut self) -> PR15_W < INTFR_SPEC > { PR15_W :: new (self , 15) } # [doc = "Bit 16 - Pending bit 16"]
# [inline (always)]
# [must_use]
pub fn pr16 (& mut self) -> PR16_W < INTFR_SPEC > { PR16_W :: new (self , 16) } # [doc = "Bit 17 - Pending bit 17"]
# [inline (always)]
# [must_use]
pub fn pr17 (& mut self) -> PR17_W < INTFR_SPEC > { PR17_W :: new (self , 17) } # [doc = "Bit 18 - Pending bit 18"]
# [inline (always)]
# [must_use]
pub fn pr18 (& mut self) -> PR18_W < INTFR_SPEC > { PR18_W :: new (self , 18) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Pending register (EXTI_INTFR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intfr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intfr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTFR_SPEC ; impl crate :: RegisterSpec for INTFR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`intfr::R`](R) reader structure"]
impl crate :: Readable for INTFR_SPEC { } # [doc = "`write(|w| ..)` method takes [`intfr::W`](W) writer structure"]
impl crate :: Writable for INTFR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTFR to value 0"]
impl crate :: Resettable for INTFR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "DMA controller"]
pub struct DMA { _marker : PhantomData < * const () > } unsafe impl Send for DMA { } impl DMA { # [doc = r"Pointer to the register block"]
pub const PTR : * const dma :: RegisterBlock = 0x4002_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const dma :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for DMA { type Target = dma :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for DMA { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("DMA") . finish () } } # [doc = "DMA controller"]
pub mod dma { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { intfr : INTFR , intfcr : INTFCR , cfgr1 : CFGR1 , cntr1 : CNTR1 , paddr1 : PADDR1 , maddr1 : MADDR1 , _reserved6 : [u8 ; 0x04]
, cfgr2 : CFGR2 , cntr2 : CNTR2 , paddr2 : PADDR2 , maddr2 : MADDR2 , _reserved10 : [u8 ; 0x04]
, cfgr3 : CFGR3 , cntr3 : CNTR3 , paddr3 : PADDR3 , maddr3 : MADDR3 , _reserved14 : [u8 ; 0x04]
, cfgr4 : CFGR4 , cntr4 : CNTR4 , paddr4 : PADDR4 , maddr4 : MADDR4 , _reserved18 : [u8 ; 0x04]
, cfgr5 : CFGR5 , cntr5 : CNTR5 , paddr5 : PADDR5 , maddr5 : MADDR5 , _reserved22 : [u8 ; 0x04]
, cfgr6 : CFGR6 , cntr6 : CNTR6 , paddr6 : PADDR6 , maddr6 : MADDR6 , _reserved26 : [u8 ; 0x04]
, cfgr7 : CFGR7 , cntr7 : CNTR7 , paddr7 : PADDR7 , maddr7 : MADDR7 , } impl RegisterBlock { # [doc = "0x00 - DMA interrupt status register (DMA_INTFR)"]
# [inline (always)]
pub const fn intfr (& self) -> & INTFR { & self . intfr } # [doc = "0x04 - DMA interrupt flag clear register (DMA_INTFCR)"]
# [inline (always)]
pub const fn intfcr (& self) -> & INTFCR { & self . intfcr } # [doc = "0x08 - DMA channel configuration register (DMA_CFGR)"]
# [inline (always)]
pub const fn cfgr1 (& self) -> & CFGR1 { & self . cfgr1 } # [doc = "0x0c - DMA channel 1 number of data register"]
# [inline (always)]
pub const fn cntr1 (& self) -> & CNTR1 { & self . cntr1 } # [doc = "0x10 - DMA channel 1 peripheral address register"]
# [inline (always)]
pub const fn paddr1 (& self) -> & PADDR1 { & self . paddr1 } # [doc = "0x14 - DMA channel 1 memory address register"]
# [inline (always)]
pub const fn maddr1 (& self) -> & MADDR1 { & self . maddr1 } # [doc = "0x1c - DMA channel configuration register (DMA_CFGR)"]
# [inline (always)]
pub const fn cfgr2 (& self) -> & CFGR2 { & self . cfgr2 } # [doc = "0x20 - DMA channel 2 number of data register"]
# [inline (always)]
pub const fn cntr2 (& self) -> & CNTR2 { & self . cntr2 } # [doc = "0x24 - DMA channel 2 peripheral address register"]
# [inline (always)]
pub const fn paddr2 (& self) -> & PADDR2 { & self . paddr2 } # [doc = "0x28 - DMA channel 2 memory address register"]
# [inline (always)]
pub const fn maddr2 (& self) -> & MADDR2 { & self . maddr2 } # [doc = "0x30 - DMA channel configuration register (DMA_CFGR)"]
# [inline (always)]
pub const fn cfgr3 (& self) -> & CFGR3 { & self . cfgr3 } # [doc = "0x34 - DMA channel 3 number of data register"]
# [inline (always)]
pub const fn cntr3 (& self) -> & CNTR3 { & self . cntr3 } # [doc = "0x38 - DMA channel 3 peripheral address register"]
# [inline (always)]
pub const fn paddr3 (& self) -> & PADDR3 { & self . paddr3 } # [doc = "0x3c - DMA channel 3 memory address register"]
# [inline (always)]
pub const fn maddr3 (& self) -> & MADDR3 { & self . maddr3 } # [doc = "0x44 - DMA channel configuration register (DMA_CFGR)"]
# [inline (always)]
pub const fn cfgr4 (& self) -> & CFGR4 { & self . cfgr4 } # [doc = "0x48 - DMA channel 4 number of data register"]
# [inline (always)]
pub const fn cntr4 (& self) -> & CNTR4 { & self . cntr4 } # [doc = "0x4c - DMA channel 4 peripheral address register"]
# [inline (always)]
pub const fn paddr4 (& self) -> & PADDR4 { & self . paddr4 } # [doc = "0x50 - DMA channel 4 memory address register"]
# [inline (always)]
pub const fn maddr4 (& self) -> & MADDR4 { & self . maddr4 } # [doc = "0x58 - DMA channel configuration register (DMA_CFGR)"]
# [inline (always)]
pub const fn cfgr5 (& self) -> & CFGR5 { & self . cfgr5 } # [doc = "0x5c - DMA channel 5 number of data register"]
# [inline (always)]
pub const fn cntr5 (& self) -> & CNTR5 { & self . cntr5 } # [doc = "0x60 - DMA channel 5 peripheral address register"]
# [inline (always)]
pub const fn paddr5 (& self) -> & PADDR5 { & self . paddr5 } # [doc = "0x64 - DMA channel 5 memory address register"]
# [inline (always)]
pub const fn maddr5 (& self) -> & MADDR5 { & self . maddr5 } # [doc = "0x6c - DMA channel configuration register (DMA_CFGR)"]
# [inline (always)]
pub const fn cfgr6 (& self) -> & CFGR6 { & self . cfgr6 } # [doc = "0x70 - DMA channel 6 number of data register"]
# [inline (always)]
pub const fn cntr6 (& self) -> & CNTR6 { & self . cntr6 } # [doc = "0x74 - DMA channel 6 peripheral address register"]
# [inline (always)]
pub const fn paddr6 (& self) -> & PADDR6 { & self . paddr6 } # [doc = "0x78 - DMA channel 6 memory address register"]
# [inline (always)]
pub const fn maddr6 (& self) -> & MADDR6 { & self . maddr6 } # [doc = "0x80 - DMA channel configuration register (DMA_CFGR)"]
# [inline (always)]
pub const fn cfgr7 (& self) -> & CFGR7 { & self . cfgr7 } # [doc = "0x84 - DMA channel 7 number of data register"]
# [inline (always)]
pub const fn cntr7 (& self) -> & CNTR7 { & self . cntr7 } # [doc = "0x88 - DMA channel 7 peripheral address register"]
# [inline (always)]
pub const fn paddr7 (& self) -> & PADDR7 { & self . paddr7 } # [doc = "0x8c - DMA channel 7 memory address register"]
# [inline (always)]
pub const fn maddr7 (& self) -> & MADDR7 { & self . maddr7 } } # [doc = "INTFR (r) register accessor: DMA interrupt status register (DMA_INTFR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intfr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intfr`]
module"]
pub type INTFR = crate :: Reg < intfr :: INTFR_SPEC > ; # [doc = "DMA interrupt status register (DMA_INTFR)"]
pub mod intfr { # [doc = "Register `INTFR` reader"]
pub type R = crate :: R < INTFR_SPEC > ; # [doc = "Field `GIF1` reader - Channel 1 Global interrupt flag"]
pub type GIF1_R = crate :: BitReader ; # [doc = "Field `TCIF1` reader - Channel 1 Transfer Complete flag"]
pub type TCIF1_R = crate :: BitReader ; # [doc = "Field `HTIF1` reader - Channel 1 Half Transfer Complete flag"]
pub type HTIF1_R = crate :: BitReader ; # [doc = "Field `TEIF1` reader - Channel 1 Transfer Error flag"]
pub type TEIF1_R = crate :: BitReader ; # [doc = "Field `GIF2` reader - Channel 2 Global interrupt flag"]
pub type GIF2_R = crate :: BitReader ; # [doc = "Field `TCIF2` reader - Channel 2 Transfer Complete flag"]
pub type TCIF2_R = crate :: BitReader ; # [doc = "Field `HTIF2` reader - Channel 2 Half Transfer Complete flag"]
pub type HTIF2_R = crate :: BitReader ; # [doc = "Field `TEIF2` reader - Channel 2 Transfer Error flag"]
pub type TEIF2_R = crate :: BitReader ; # [doc = "Field `GIF3` reader - Channel 3 Global interrupt flag"]
pub type GIF3_R = crate :: BitReader ; # [doc = "Field `TCIF3` reader - Channel 3 Transfer Complete flag"]
pub type TCIF3_R = crate :: BitReader ; # [doc = "Field `HTIF3` reader - Channel 3 Half Transfer Complete flag"]
pub type HTIF3_R = crate :: BitReader ; # [doc = "Field `TEIF3` reader - Channel 3 Transfer Error flag"]
pub type TEIF3_R = crate :: BitReader ; # [doc = "Field `GIF4` reader - Channel 4 Global interrupt flag"]
pub type GIF4_R = crate :: BitReader ; # [doc = "Field `TCIF4` reader - Channel 4 Transfer Complete flag"]
pub type TCIF4_R = crate :: BitReader ; # [doc = "Field `HTIF4` reader - Channel 4 Half Transfer Complete flag"]
pub type HTIF4_R = crate :: BitReader ; # [doc = "Field `TEIF4` reader - Channel 4 Transfer Error flag"]
pub type TEIF4_R = crate :: BitReader ; # [doc = "Field `GIF5` reader - Channel 5 Global interrupt flag"]
pub type GIF5_R = crate :: BitReader ; # [doc = "Field `TCIF5` reader - Channel 5 Transfer Complete flag"]
pub type TCIF5_R = crate :: BitReader ; # [doc = "Field `HTIF5` reader - Channel 5 Half Transfer Complete flag"]
pub type HTIF5_R = crate :: BitReader ; # [doc = "Field `TEIF5` reader - Channel 5 Transfer Error flag"]
pub type TEIF5_R = crate :: BitReader ; # [doc = "Field `GIF6` reader - Channel 6 Global interrupt flag"]
pub type GIF6_R = crate :: BitReader ; # [doc = "Field `TCIF6` reader - Channel 6 Transfer Complete flag"]
pub type TCIF6_R = crate :: BitReader ; # [doc = "Field `HTIF6` reader - Channel 6 Half Transfer Complete flag"]
pub type HTIF6_R = crate :: BitReader ; # [doc = "Field `TEIF6` reader - Channel 6 Transfer Error flag"]
pub type TEIF6_R = crate :: BitReader ; # [doc = "Field `GIF7` reader - Channel 7 Global interrupt flag"]
pub type GIF7_R = crate :: BitReader ; # [doc = "Field `TCIF7` reader - Channel 7 Transfer Complete flag"]
pub type TCIF7_R = crate :: BitReader ; # [doc = "Field `HTIF7` reader - Channel 7 Half Transfer Complete flag"]
pub type HTIF7_R = crate :: BitReader ; # [doc = "Field `TEIF7` reader - Channel 7 Transfer Error flag"]
pub type TEIF7_R = crate :: BitReader ; impl R { # [doc = "Bit 0 - Channel 1 Global interrupt flag"]
# [inline (always)]
pub fn gif1 (& self) -> GIF1_R { GIF1_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Channel 1 Transfer Complete flag"]
# [inline (always)]
pub fn tcif1 (& self) -> TCIF1_R { TCIF1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Channel 1 Half Transfer Complete flag"]
# [inline (always)]
pub fn htif1 (& self) -> HTIF1_R { HTIF1_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Channel 1 Transfer Error flag"]
# [inline (always)]
pub fn teif1 (& self) -> TEIF1_R { TEIF1_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Channel 2 Global interrupt flag"]
# [inline (always)]
pub fn gif2 (& self) -> GIF2_R { GIF2_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Channel 2 Transfer Complete flag"]
# [inline (always)]
pub fn tcif2 (& self) -> TCIF2_R { TCIF2_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Channel 2 Half Transfer Complete flag"]
# [inline (always)]
pub fn htif2 (& self) -> HTIF2_R { HTIF2_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Channel 2 Transfer Error flag"]
# [inline (always)]
pub fn teif2 (& self) -> TEIF2_R { TEIF2_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Channel 3 Global interrupt flag"]
# [inline (always)]
pub fn gif3 (& self) -> GIF3_R { GIF3_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Channel 3 Transfer Complete flag"]
# [inline (always)]
pub fn tcif3 (& self) -> TCIF3_R { TCIF3_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Channel 3 Half Transfer Complete flag"]
# [inline (always)]
pub fn htif3 (& self) -> HTIF3_R { HTIF3_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Channel 3 Transfer Error flag"]
# [inline (always)]
pub fn teif3 (& self) -> TEIF3_R { TEIF3_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Channel 4 Global interrupt flag"]
# [inline (always)]
pub fn gif4 (& self) -> GIF4_R { GIF4_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Channel 4 Transfer Complete flag"]
# [inline (always)]
pub fn tcif4 (& self) -> TCIF4_R { TCIF4_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Channel 4 Half Transfer Complete flag"]
# [inline (always)]
pub fn htif4 (& self) -> HTIF4_R { HTIF4_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Channel 4 Transfer Error flag"]
# [inline (always)]
pub fn teif4 (& self) -> TEIF4_R { TEIF4_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Channel 5 Global interrupt flag"]
# [inline (always)]
pub fn gif5 (& self) -> GIF5_R { GIF5_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Channel 5 Transfer Complete flag"]
# [inline (always)]
pub fn tcif5 (& self) -> TCIF5_R { TCIF5_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Channel 5 Half Transfer Complete flag"]
# [inline (always)]
pub fn htif5 (& self) -> HTIF5_R { HTIF5_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Channel 5 Transfer Error flag"]
# [inline (always)]
pub fn teif5 (& self) -> TEIF5_R { TEIF5_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - Channel 6 Global interrupt flag"]
# [inline (always)]
pub fn gif6 (& self) -> GIF6_R { GIF6_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - Channel 6 Transfer Complete flag"]
# [inline (always)]
pub fn tcif6 (& self) -> TCIF6_R { TCIF6_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - Channel 6 Half Transfer Complete flag"]
# [inline (always)]
pub fn htif6 (& self) -> HTIF6_R { HTIF6_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - Channel 6 Transfer Error flag"]
# [inline (always)]
pub fn teif6 (& self) -> TEIF6_R { TEIF6_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - Channel 7 Global interrupt flag"]
# [inline (always)]
pub fn gif7 (& self) -> GIF7_R { GIF7_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - Channel 7 Transfer Complete flag"]
# [inline (always)]
pub fn tcif7 (& self) -> TCIF7_R { TCIF7_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - Channel 7 Half Transfer Complete flag"]
# [inline (always)]
pub fn htif7 (& self) -> HTIF7_R { HTIF7_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - Channel 7 Transfer Error flag"]
# [inline (always)]
pub fn teif7 (& self) -> TEIF7_R { TEIF7_R :: new (((self . bits >> 27) & 1) != 0) } } # [doc = "DMA interrupt status register (DMA_INTFR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intfr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTFR_SPEC ; impl crate :: RegisterSpec for INTFR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`intfr::R`](R) reader structure"]
impl crate :: Readable for INTFR_SPEC { } # [doc = "`reset()` method sets INTFR to value 0"]
impl crate :: Resettable for INTFR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTFCR (w) register accessor: DMA interrupt flag clear register (DMA_INTFCR)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intfcr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intfcr`]
module"]
pub type INTFCR = crate :: Reg < intfcr :: INTFCR_SPEC > ; # [doc = "DMA interrupt flag clear register (DMA_INTFCR)"]
pub mod intfcr { # [doc = "Register `INTFCR` writer"]
pub type W = crate :: W < INTFCR_SPEC > ; # [doc = "Field `CGIF1` writer - Channel 1 Global interrupt clear"]
pub type CGIF1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTCIF1` writer - Channel 1 Transfer Complete clear"]
pub type CTCIF1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CHTIF1` writer - Channel 1 Half Transfer clear"]
pub type CHTIF1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTEIF1` writer - Channel 1 Transfer Error clear"]
pub type CTEIF1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CGIF2` writer - Channel 2 Global interrupt clear"]
pub type CGIF2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTCIF2` writer - Channel 2 Transfer Complete clear"]
pub type CTCIF2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CHTIF2` writer - Channel 2 Half Transfer clear"]
pub type CHTIF2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTEIF2` writer - Channel 2 Transfer Error clear"]
pub type CTEIF2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CGIF3` writer - Channel 3 Global interrupt clear"]
pub type CGIF3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTCIF3` writer - Channel 3 Transfer Complete clear"]
pub type CTCIF3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CHTIF3` writer - Channel 3 Half Transfer clear"]
pub type CHTIF3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTEIF3` writer - Channel 3 Transfer Error clear"]
pub type CTEIF3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CGIF4` writer - Channel 4 Global interrupt clear"]
pub type CGIF4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTCIF4` writer - Channel 4 Transfer Complete clear"]
pub type CTCIF4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CHTIF4` writer - Channel 4 Half Transfer clear"]
pub type CHTIF4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTEIF4` writer - Channel 4 Transfer Error clear"]
pub type CTEIF4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CGIF5` writer - Channel 5 Global interrupt clear"]
pub type CGIF5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTCIF5` writer - Channel 5 Transfer Complete clear"]
pub type CTCIF5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CHTIF5` writer - Channel 5 Half Transfer clear"]
pub type CHTIF5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTEIF5` writer - Channel 5 Transfer Error clear"]
pub type CTEIF5_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CGIF6` writer - Channel 6 Global interrupt clear"]
pub type CGIF6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTCIF6` writer - Channel 6 Transfer Complete clear"]
pub type CTCIF6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CHTIF6` writer - Channel 6 Half Transfer clear"]
pub type CHTIF6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTEIF6` writer - Channel 6 Transfer Error clear"]
pub type CTEIF6_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CGIF7` writer - Channel 7 Global interrupt clear"]
pub type CGIF7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTCIF7` writer - Channel 7 Transfer Complete clear"]
pub type CTCIF7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CHTIF7` writer - Channel 7 Half Transfer clear"]
pub type CHTIF7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTEIF7` writer - Channel 7 Transfer Error clear"]
pub type CTEIF7_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W { # [doc = "Bit 0 - Channel 1 Global interrupt clear"]
# [inline (always)]
# [must_use]
pub fn cgif1 (& mut self) -> CGIF1_W < INTFCR_SPEC > { CGIF1_W :: new (self , 0) } # [doc = "Bit 1 - Channel 1 Transfer Complete clear"]
# [inline (always)]
# [must_use]
pub fn ctcif1 (& mut self) -> CTCIF1_W < INTFCR_SPEC > { CTCIF1_W :: new (self , 1) } # [doc = "Bit 2 - Channel 1 Half Transfer clear"]
# [inline (always)]
# [must_use]
pub fn chtif1 (& mut self) -> CHTIF1_W < INTFCR_SPEC > { CHTIF1_W :: new (self , 2) } # [doc = "Bit 3 - Channel 1 Transfer Error clear"]
# [inline (always)]
# [must_use]
pub fn cteif1 (& mut self) -> CTEIF1_W < INTFCR_SPEC > { CTEIF1_W :: new (self , 3) } # [doc = "Bit 4 - Channel 2 Global interrupt clear"]
# [inline (always)]
# [must_use]
pub fn cgif2 (& mut self) -> CGIF2_W < INTFCR_SPEC > { CGIF2_W :: new (self , 4) } # [doc = "Bit 5 - Channel 2 Transfer Complete clear"]
# [inline (always)]
# [must_use]
pub fn ctcif2 (& mut self) -> CTCIF2_W < INTFCR_SPEC > { CTCIF2_W :: new (self , 5) } # [doc = "Bit 6 - Channel 2 Half Transfer clear"]
# [inline (always)]
# [must_use]
pub fn chtif2 (& mut self) -> CHTIF2_W < INTFCR_SPEC > { CHTIF2_W :: new (self , 6) } # [doc = "Bit 7 - Channel 2 Transfer Error clear"]
# [inline (always)]
# [must_use]
pub fn cteif2 (& mut self) -> CTEIF2_W < INTFCR_SPEC > { CTEIF2_W :: new (self , 7) } # [doc = "Bit 8 - Channel 3 Global interrupt clear"]
# [inline (always)]
# [must_use]
pub fn cgif3 (& mut self) -> CGIF3_W < INTFCR_SPEC > { CGIF3_W :: new (self , 8) } # [doc = "Bit 9 - Channel 3 Transfer Complete clear"]
# [inline (always)]
# [must_use]
pub fn ctcif3 (& mut self) -> CTCIF3_W < INTFCR_SPEC > { CTCIF3_W :: new (self , 9) } # [doc = "Bit 10 - Channel 3 Half Transfer clear"]
# [inline (always)]
# [must_use]
pub fn chtif3 (& mut self) -> CHTIF3_W < INTFCR_SPEC > { CHTIF3_W :: new (self , 10) } # [doc = "Bit 11 - Channel 3 Transfer Error clear"]
# [inline (always)]
# [must_use]
pub fn cteif3 (& mut self) -> CTEIF3_W < INTFCR_SPEC > { CTEIF3_W :: new (self , 11) } # [doc = "Bit 12 - Channel 4 Global interrupt clear"]
# [inline (always)]
# [must_use]
pub fn cgif4 (& mut self) -> CGIF4_W < INTFCR_SPEC > { CGIF4_W :: new (self , 12) } # [doc = "Bit 13 - Channel 4 Transfer Complete clear"]
# [inline (always)]
# [must_use]
pub fn ctcif4 (& mut self) -> CTCIF4_W < INTFCR_SPEC > { CTCIF4_W :: new (self , 13) } # [doc = "Bit 14 - Channel 4 Half Transfer clear"]
# [inline (always)]
# [must_use]
pub fn chtif4 (& mut self) -> CHTIF4_W < INTFCR_SPEC > { CHTIF4_W :: new (self , 14) } # [doc = "Bit 15 - Channel 4 Transfer Error clear"]
# [inline (always)]
# [must_use]
pub fn cteif4 (& mut self) -> CTEIF4_W < INTFCR_SPEC > { CTEIF4_W :: new (self , 15) } # [doc = "Bit 16 - Channel 5 Global interrupt clear"]
# [inline (always)]
# [must_use]
pub fn cgif5 (& mut self) -> CGIF5_W < INTFCR_SPEC > { CGIF5_W :: new (self , 16) } # [doc = "Bit 17 - Channel 5 Transfer Complete clear"]
# [inline (always)]
# [must_use]
pub fn ctcif5 (& mut self) -> CTCIF5_W < INTFCR_SPEC > { CTCIF5_W :: new (self , 17) } # [doc = "Bit 18 - Channel 5 Half Transfer clear"]
# [inline (always)]
# [must_use]
pub fn chtif5 (& mut self) -> CHTIF5_W < INTFCR_SPEC > { CHTIF5_W :: new (self , 18) } # [doc = "Bit 19 - Channel 5 Transfer Error clear"]
# [inline (always)]
# [must_use]
pub fn cteif5 (& mut self) -> CTEIF5_W < INTFCR_SPEC > { CTEIF5_W :: new (self , 19) } # [doc = "Bit 20 - Channel 6 Global interrupt clear"]
# [inline (always)]
# [must_use]
pub fn cgif6 (& mut self) -> CGIF6_W < INTFCR_SPEC > { CGIF6_W :: new (self , 20) } # [doc = "Bit 21 - Channel 6 Transfer Complete clear"]
# [inline (always)]
# [must_use]
pub fn ctcif6 (& mut self) -> CTCIF6_W < INTFCR_SPEC > { CTCIF6_W :: new (self , 21) } # [doc = "Bit 22 - Channel 6 Half Transfer clear"]
# [inline (always)]
# [must_use]
pub fn chtif6 (& mut self) -> CHTIF6_W < INTFCR_SPEC > { CHTIF6_W :: new (self , 22) } # [doc = "Bit 23 - Channel 6 Transfer Error clear"]
# [inline (always)]
# [must_use]
pub fn cteif6 (& mut self) -> CTEIF6_W < INTFCR_SPEC > { CTEIF6_W :: new (self , 23) } # [doc = "Bit 24 - Channel 7 Global interrupt clear"]
# [inline (always)]
# [must_use]
pub fn cgif7 (& mut self) -> CGIF7_W < INTFCR_SPEC > { CGIF7_W :: new (self , 24) } # [doc = "Bit 25 - Channel 7 Transfer Complete clear"]
# [inline (always)]
# [must_use]
pub fn ctcif7 (& mut self) -> CTCIF7_W < INTFCR_SPEC > { CTCIF7_W :: new (self , 25) } # [doc = "Bit 26 - Channel 7 Half Transfer clear"]
# [inline (always)]
# [must_use]
pub fn chtif7 (& mut self) -> CHTIF7_W < INTFCR_SPEC > { CHTIF7_W :: new (self , 26) } # [doc = "Bit 27 - Channel 7 Transfer Error clear"]
# [inline (always)]
# [must_use]
pub fn cteif7 (& mut self) -> CTEIF7_W < INTFCR_SPEC > { CTEIF7_W :: new (self , 27) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA interrupt flag clear register (DMA_INTFCR)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intfcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTFCR_SPEC ; impl crate :: RegisterSpec for INTFCR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`intfcr::W`](W) writer structure"]
impl crate :: Writable for INTFCR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTFCR to value 0"]
impl crate :: Resettable for INTFCR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFGR1 (rw) register accessor: DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr1`]
module"]
pub type CFGR1 = crate :: Reg < cfgr1 :: CFGR1_SPEC > ; # [doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr1 { # [doc = "Register `CFGR1` reader"]
pub type R = crate :: R < CFGR1_SPEC > ; # [doc = "Register `CFGR1` writer"]
pub type W = crate :: W < CFGR1_SPEC > ; # [doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate :: BitReader ; # [doc = "Field `EN` writer - Channel enable"]
pub type EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate :: BitReader ; # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate :: BitReader ; # [doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate :: BitReader ; # [doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate :: BitReader ; # [doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate :: BitReader ; # [doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate :: BitReader ; # [doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate :: BitReader ; # [doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate :: FieldReader ; # [doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate :: FieldReader ; # [doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate :: FieldReader ; # [doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate :: BitReader ; # [doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
pub fn en (& self) -> EN_R { EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
pub fn tcie (& self) -> TCIE_R { TCIE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
pub fn htie (& self) -> HTIE_R { HTIE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
pub fn teie (& self) -> TEIE_R { TEIE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
pub fn dir (& self) -> DIR_R { DIR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
pub fn circ (& self) -> CIRC_R { CIRC_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
pub fn pinc (& self) -> PINC_R { PINC_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
pub fn minc (& self) -> MINC_R { MINC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
pub fn psize (& self) -> PSIZE_R { PSIZE_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
pub fn msize (& self) -> MSIZE_R { MSIZE_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
pub fn pl (& self) -> PL_R { PL_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
pub fn mem2mem (& self) -> MEM2MEM_R { MEM2MEM_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EN_W < CFGR1_SPEC > { EN_W :: new (self , 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
# [must_use]
pub fn tcie (& mut self) -> TCIE_W < CFGR1_SPEC > { TCIE_W :: new (self , 1) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
# [must_use]
pub fn htie (& mut self) -> HTIE_W < CFGR1_SPEC > { HTIE_W :: new (self , 2) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
# [must_use]
pub fn teie (& mut self) -> TEIE_W < CFGR1_SPEC > { TEIE_W :: new (self , 3) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
# [must_use]
pub fn dir (& mut self) -> DIR_W < CFGR1_SPEC > { DIR_W :: new (self , 4) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
# [must_use]
pub fn circ (& mut self) -> CIRC_W < CFGR1_SPEC > { CIRC_W :: new (self , 5) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
# [must_use]
pub fn pinc (& mut self) -> PINC_W < CFGR1_SPEC > { PINC_W :: new (self , 6) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
# [must_use]
pub fn minc (& mut self) -> MINC_W < CFGR1_SPEC > { MINC_W :: new (self , 7) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
# [must_use]
pub fn psize (& mut self) -> PSIZE_W < CFGR1_SPEC > { PSIZE_W :: new (self , 8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
# [must_use]
pub fn msize (& mut self) -> MSIZE_W < CFGR1_SPEC > { MSIZE_W :: new (self , 10) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
# [must_use]
pub fn pl (& mut self) -> PL_W < CFGR1_SPEC > { PL_W :: new (self , 12) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
# [must_use]
pub fn mem2mem (& mut self) -> MEM2MEM_W < CFGR1_SPEC > { MEM2MEM_W :: new (self , 14) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGR1_SPEC ; impl crate :: RegisterSpec for CFGR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr1::R`](R) reader structure"]
impl crate :: Readable for CFGR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgr1::W`](W) writer structure"]
impl crate :: Writable for CFGR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFGR1 to value 0"]
impl crate :: Resettable for CFGR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CNTR1 (rw) register accessor: DMA channel 1 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntr1`]
module"]
pub type CNTR1 = crate :: Reg < cntr1 :: CNTR1_SPEC > ; # [doc = "DMA channel 1 number of data register"]
pub mod cntr1 { # [doc = "Register `CNTR1` reader"]
pub type R = crate :: R < CNTR1_SPEC > ; # [doc = "Register `CNTR1` writer"]
pub type W = crate :: W < CNTR1_SPEC > ; # [doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate :: FieldReader < u16 > ; # [doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
pub fn ndt (& self) -> NDT_R { NDT_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
# [must_use]
pub fn ndt (& mut self) -> NDT_W < CNTR1_SPEC > { NDT_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 1 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CNTR1_SPEC ; impl crate :: RegisterSpec for CNTR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cntr1::R`](R) reader structure"]
impl crate :: Readable for CNTR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`cntr1::W`](W) writer structure"]
impl crate :: Writable for CNTR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CNTR1 to value 0"]
impl crate :: Resettable for CNTR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADDR1 (rw) register accessor: DMA channel 1 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@paddr1`]
module"]
pub type PADDR1 = crate :: Reg < paddr1 :: PADDR1_SPEC > ; # [doc = "DMA channel 1 peripheral address register"]
pub mod paddr1 { # [doc = "Register `PADDR1` reader"]
pub type R = crate :: R < PADDR1_SPEC > ; # [doc = "Register `PADDR1` writer"]
pub type W = crate :: W < PADDR1_SPEC > ; # [doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate :: FieldReader < u32 > ; # [doc = "Field `PA` writer - Peripheral address"]
pub type PA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
pub fn pa (& self) -> PA_R { PA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
# [must_use]
pub fn pa (& mut self) -> PA_W < PADDR1_SPEC > { PA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 1 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PADDR1_SPEC ; impl crate :: RegisterSpec for PADDR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`paddr1::R`](R) reader structure"]
impl crate :: Readable for PADDR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`paddr1::W`](W) writer structure"]
impl crate :: Writable for PADDR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADDR1 to value 0"]
impl crate :: Resettable for PADDR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "MADDR1 (rw) register accessor: DMA channel 1 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@maddr1`]
module"]
pub type MADDR1 = crate :: Reg < maddr1 :: MADDR1_SPEC > ; # [doc = "DMA channel 1 memory address register"]
pub mod maddr1 { # [doc = "Register `MADDR1` reader"]
pub type R = crate :: R < MADDR1_SPEC > ; # [doc = "Register `MADDR1` writer"]
pub type W = crate :: W < MADDR1_SPEC > ; # [doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate :: FieldReader < u32 > ; # [doc = "Field `MA` writer - Memory address"]
pub type MA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
pub fn ma (& self) -> MA_R { MA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
# [must_use]
pub fn ma (& mut self) -> MA_W < MADDR1_SPEC > { MA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 1 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MADDR1_SPEC ; impl crate :: RegisterSpec for MADDR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`maddr1::R`](R) reader structure"]
impl crate :: Readable for MADDR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`maddr1::W`](W) writer structure"]
impl crate :: Writable for MADDR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MADDR1 to value 0"]
impl crate :: Resettable for MADDR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFGR2 (rw) register accessor: DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr2`]
module"]
pub type CFGR2 = crate :: Reg < cfgr2 :: CFGR2_SPEC > ; # [doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr2 { # [doc = "Register `CFGR2` reader"]
pub type R = crate :: R < CFGR2_SPEC > ; # [doc = "Register `CFGR2` writer"]
pub type W = crate :: W < CFGR2_SPEC > ; # [doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate :: BitReader ; # [doc = "Field `EN` writer - Channel enable"]
pub type EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate :: BitReader ; # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate :: BitReader ; # [doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate :: BitReader ; # [doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate :: BitReader ; # [doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate :: BitReader ; # [doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate :: BitReader ; # [doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate :: BitReader ; # [doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate :: FieldReader ; # [doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate :: FieldReader ; # [doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate :: FieldReader ; # [doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate :: BitReader ; # [doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
pub fn en (& self) -> EN_R { EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
pub fn tcie (& self) -> TCIE_R { TCIE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
pub fn htie (& self) -> HTIE_R { HTIE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
pub fn teie (& self) -> TEIE_R { TEIE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
pub fn dir (& self) -> DIR_R { DIR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
pub fn circ (& self) -> CIRC_R { CIRC_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
pub fn pinc (& self) -> PINC_R { PINC_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
pub fn minc (& self) -> MINC_R { MINC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
pub fn psize (& self) -> PSIZE_R { PSIZE_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
pub fn msize (& self) -> MSIZE_R { MSIZE_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
pub fn pl (& self) -> PL_R { PL_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
pub fn mem2mem (& self) -> MEM2MEM_R { MEM2MEM_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EN_W < CFGR2_SPEC > { EN_W :: new (self , 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
# [must_use]
pub fn tcie (& mut self) -> TCIE_W < CFGR2_SPEC > { TCIE_W :: new (self , 1) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
# [must_use]
pub fn htie (& mut self) -> HTIE_W < CFGR2_SPEC > { HTIE_W :: new (self , 2) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
# [must_use]
pub fn teie (& mut self) -> TEIE_W < CFGR2_SPEC > { TEIE_W :: new (self , 3) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
# [must_use]
pub fn dir (& mut self) -> DIR_W < CFGR2_SPEC > { DIR_W :: new (self , 4) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
# [must_use]
pub fn circ (& mut self) -> CIRC_W < CFGR2_SPEC > { CIRC_W :: new (self , 5) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
# [must_use]
pub fn pinc (& mut self) -> PINC_W < CFGR2_SPEC > { PINC_W :: new (self , 6) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
# [must_use]
pub fn minc (& mut self) -> MINC_W < CFGR2_SPEC > { MINC_W :: new (self , 7) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
# [must_use]
pub fn psize (& mut self) -> PSIZE_W < CFGR2_SPEC > { PSIZE_W :: new (self , 8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
# [must_use]
pub fn msize (& mut self) -> MSIZE_W < CFGR2_SPEC > { MSIZE_W :: new (self , 10) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
# [must_use]
pub fn pl (& mut self) -> PL_W < CFGR2_SPEC > { PL_W :: new (self , 12) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
# [must_use]
pub fn mem2mem (& mut self) -> MEM2MEM_W < CFGR2_SPEC > { MEM2MEM_W :: new (self , 14) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGR2_SPEC ; impl crate :: RegisterSpec for CFGR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr2::R`](R) reader structure"]
impl crate :: Readable for CFGR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgr2::W`](W) writer structure"]
impl crate :: Writable for CFGR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFGR2 to value 0"]
impl crate :: Resettable for CFGR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CNTR2 (rw) register accessor: DMA channel 2 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntr2`]
module"]
pub type CNTR2 = crate :: Reg < cntr2 :: CNTR2_SPEC > ; # [doc = "DMA channel 2 number of data register"]
pub mod cntr2 { # [doc = "Register `CNTR2` reader"]
pub type R = crate :: R < CNTR2_SPEC > ; # [doc = "Register `CNTR2` writer"]
pub type W = crate :: W < CNTR2_SPEC > ; # [doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate :: FieldReader < u16 > ; # [doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
pub fn ndt (& self) -> NDT_R { NDT_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
# [must_use]
pub fn ndt (& mut self) -> NDT_W < CNTR2_SPEC > { NDT_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 2 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CNTR2_SPEC ; impl crate :: RegisterSpec for CNTR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cntr2::R`](R) reader structure"]
impl crate :: Readable for CNTR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`cntr2::W`](W) writer structure"]
impl crate :: Writable for CNTR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CNTR2 to value 0"]
impl crate :: Resettable for CNTR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADDR2 (rw) register accessor: DMA channel 2 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@paddr2`]
module"]
pub type PADDR2 = crate :: Reg < paddr2 :: PADDR2_SPEC > ; # [doc = "DMA channel 2 peripheral address register"]
pub mod paddr2 { # [doc = "Register `PADDR2` reader"]
pub type R = crate :: R < PADDR2_SPEC > ; # [doc = "Register `PADDR2` writer"]
pub type W = crate :: W < PADDR2_SPEC > ; # [doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate :: FieldReader < u32 > ; # [doc = "Field `PA` writer - Peripheral address"]
pub type PA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
pub fn pa (& self) -> PA_R { PA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
# [must_use]
pub fn pa (& mut self) -> PA_W < PADDR2_SPEC > { PA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 2 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PADDR2_SPEC ; impl crate :: RegisterSpec for PADDR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`paddr2::R`](R) reader structure"]
impl crate :: Readable for PADDR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`paddr2::W`](W) writer structure"]
impl crate :: Writable for PADDR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADDR2 to value 0"]
impl crate :: Resettable for PADDR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "MADDR2 (rw) register accessor: DMA channel 2 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@maddr2`]
module"]
pub type MADDR2 = crate :: Reg < maddr2 :: MADDR2_SPEC > ; # [doc = "DMA channel 2 memory address register"]
pub mod maddr2 { # [doc = "Register `MADDR2` reader"]
pub type R = crate :: R < MADDR2_SPEC > ; # [doc = "Register `MADDR2` writer"]
pub type W = crate :: W < MADDR2_SPEC > ; # [doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate :: FieldReader < u32 > ; # [doc = "Field `MA` writer - Memory address"]
pub type MA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
pub fn ma (& self) -> MA_R { MA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
# [must_use]
pub fn ma (& mut self) -> MA_W < MADDR2_SPEC > { MA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 2 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MADDR2_SPEC ; impl crate :: RegisterSpec for MADDR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`maddr2::R`](R) reader structure"]
impl crate :: Readable for MADDR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`maddr2::W`](W) writer structure"]
impl crate :: Writable for MADDR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MADDR2 to value 0"]
impl crate :: Resettable for MADDR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFGR3 (rw) register accessor: DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr3`]
module"]
pub type CFGR3 = crate :: Reg < cfgr3 :: CFGR3_SPEC > ; # [doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr3 { # [doc = "Register `CFGR3` reader"]
pub type R = crate :: R < CFGR3_SPEC > ; # [doc = "Register `CFGR3` writer"]
pub type W = crate :: W < CFGR3_SPEC > ; # [doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate :: BitReader ; # [doc = "Field `EN` writer - Channel enable"]
pub type EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate :: BitReader ; # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate :: BitReader ; # [doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate :: BitReader ; # [doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate :: BitReader ; # [doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate :: BitReader ; # [doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate :: BitReader ; # [doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate :: BitReader ; # [doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate :: FieldReader ; # [doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate :: FieldReader ; # [doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate :: FieldReader ; # [doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate :: BitReader ; # [doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
pub fn en (& self) -> EN_R { EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
pub fn tcie (& self) -> TCIE_R { TCIE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
pub fn htie (& self) -> HTIE_R { HTIE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
pub fn teie (& self) -> TEIE_R { TEIE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
pub fn dir (& self) -> DIR_R { DIR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
pub fn circ (& self) -> CIRC_R { CIRC_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
pub fn pinc (& self) -> PINC_R { PINC_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
pub fn minc (& self) -> MINC_R { MINC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
pub fn psize (& self) -> PSIZE_R { PSIZE_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
pub fn msize (& self) -> MSIZE_R { MSIZE_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
pub fn pl (& self) -> PL_R { PL_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
pub fn mem2mem (& self) -> MEM2MEM_R { MEM2MEM_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EN_W < CFGR3_SPEC > { EN_W :: new (self , 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
# [must_use]
pub fn tcie (& mut self) -> TCIE_W < CFGR3_SPEC > { TCIE_W :: new (self , 1) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
# [must_use]
pub fn htie (& mut self) -> HTIE_W < CFGR3_SPEC > { HTIE_W :: new (self , 2) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
# [must_use]
pub fn teie (& mut self) -> TEIE_W < CFGR3_SPEC > { TEIE_W :: new (self , 3) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
# [must_use]
pub fn dir (& mut self) -> DIR_W < CFGR3_SPEC > { DIR_W :: new (self , 4) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
# [must_use]
pub fn circ (& mut self) -> CIRC_W < CFGR3_SPEC > { CIRC_W :: new (self , 5) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
# [must_use]
pub fn pinc (& mut self) -> PINC_W < CFGR3_SPEC > { PINC_W :: new (self , 6) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
# [must_use]
pub fn minc (& mut self) -> MINC_W < CFGR3_SPEC > { MINC_W :: new (self , 7) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
# [must_use]
pub fn psize (& mut self) -> PSIZE_W < CFGR3_SPEC > { PSIZE_W :: new (self , 8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
# [must_use]
pub fn msize (& mut self) -> MSIZE_W < CFGR3_SPEC > { MSIZE_W :: new (self , 10) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
# [must_use]
pub fn pl (& mut self) -> PL_W < CFGR3_SPEC > { PL_W :: new (self , 12) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
# [must_use]
pub fn mem2mem (& mut self) -> MEM2MEM_W < CFGR3_SPEC > { MEM2MEM_W :: new (self , 14) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGR3_SPEC ; impl crate :: RegisterSpec for CFGR3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr3::R`](R) reader structure"]
impl crate :: Readable for CFGR3_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgr3::W`](W) writer structure"]
impl crate :: Writable for CFGR3_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFGR3 to value 0"]
impl crate :: Resettable for CFGR3_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CNTR3 (rw) register accessor: DMA channel 3 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntr3`]
module"]
pub type CNTR3 = crate :: Reg < cntr3 :: CNTR3_SPEC > ; # [doc = "DMA channel 3 number of data register"]
pub mod cntr3 { # [doc = "Register `CNTR3` reader"]
pub type R = crate :: R < CNTR3_SPEC > ; # [doc = "Register `CNTR3` writer"]
pub type W = crate :: W < CNTR3_SPEC > ; # [doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate :: FieldReader < u16 > ; # [doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
pub fn ndt (& self) -> NDT_R { NDT_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
# [must_use]
pub fn ndt (& mut self) -> NDT_W < CNTR3_SPEC > { NDT_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 3 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CNTR3_SPEC ; impl crate :: RegisterSpec for CNTR3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cntr3::R`](R) reader structure"]
impl crate :: Readable for CNTR3_SPEC { } # [doc = "`write(|w| ..)` method takes [`cntr3::W`](W) writer structure"]
impl crate :: Writable for CNTR3_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CNTR3 to value 0"]
impl crate :: Resettable for CNTR3_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADDR3 (rw) register accessor: DMA channel 3 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@paddr3`]
module"]
pub type PADDR3 = crate :: Reg < paddr3 :: PADDR3_SPEC > ; # [doc = "DMA channel 3 peripheral address register"]
pub mod paddr3 { # [doc = "Register `PADDR3` reader"]
pub type R = crate :: R < PADDR3_SPEC > ; # [doc = "Register `PADDR3` writer"]
pub type W = crate :: W < PADDR3_SPEC > ; # [doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate :: FieldReader < u32 > ; # [doc = "Field `PA` writer - Peripheral address"]
pub type PA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
pub fn pa (& self) -> PA_R { PA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
# [must_use]
pub fn pa (& mut self) -> PA_W < PADDR3_SPEC > { PA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 3 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PADDR3_SPEC ; impl crate :: RegisterSpec for PADDR3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`paddr3::R`](R) reader structure"]
impl crate :: Readable for PADDR3_SPEC { } # [doc = "`write(|w| ..)` method takes [`paddr3::W`](W) writer structure"]
impl crate :: Writable for PADDR3_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADDR3 to value 0"]
impl crate :: Resettable for PADDR3_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "MADDR3 (rw) register accessor: DMA channel 3 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@maddr3`]
module"]
pub type MADDR3 = crate :: Reg < maddr3 :: MADDR3_SPEC > ; # [doc = "DMA channel 3 memory address register"]
pub mod maddr3 { # [doc = "Register `MADDR3` reader"]
pub type R = crate :: R < MADDR3_SPEC > ; # [doc = "Register `MADDR3` writer"]
pub type W = crate :: W < MADDR3_SPEC > ; # [doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate :: FieldReader < u32 > ; # [doc = "Field `MA` writer - Memory address"]
pub type MA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
pub fn ma (& self) -> MA_R { MA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
# [must_use]
pub fn ma (& mut self) -> MA_W < MADDR3_SPEC > { MA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 3 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MADDR3_SPEC ; impl crate :: RegisterSpec for MADDR3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`maddr3::R`](R) reader structure"]
impl crate :: Readable for MADDR3_SPEC { } # [doc = "`write(|w| ..)` method takes [`maddr3::W`](W) writer structure"]
impl crate :: Writable for MADDR3_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MADDR3 to value 0"]
impl crate :: Resettable for MADDR3_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFGR4 (rw) register accessor: DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr4::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr4`]
module"]
pub type CFGR4 = crate :: Reg < cfgr4 :: CFGR4_SPEC > ; # [doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr4 { # [doc = "Register `CFGR4` reader"]
pub type R = crate :: R < CFGR4_SPEC > ; # [doc = "Register `CFGR4` writer"]
pub type W = crate :: W < CFGR4_SPEC > ; # [doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate :: BitReader ; # [doc = "Field `EN` writer - Channel enable"]
pub type EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate :: BitReader ; # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate :: BitReader ; # [doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate :: BitReader ; # [doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate :: BitReader ; # [doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate :: BitReader ; # [doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate :: BitReader ; # [doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate :: BitReader ; # [doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate :: FieldReader ; # [doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate :: FieldReader ; # [doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate :: FieldReader ; # [doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate :: BitReader ; # [doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
pub fn en (& self) -> EN_R { EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
pub fn tcie (& self) -> TCIE_R { TCIE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
pub fn htie (& self) -> HTIE_R { HTIE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
pub fn teie (& self) -> TEIE_R { TEIE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
pub fn dir (& self) -> DIR_R { DIR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
pub fn circ (& self) -> CIRC_R { CIRC_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
pub fn pinc (& self) -> PINC_R { PINC_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
pub fn minc (& self) -> MINC_R { MINC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
pub fn psize (& self) -> PSIZE_R { PSIZE_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
pub fn msize (& self) -> MSIZE_R { MSIZE_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
pub fn pl (& self) -> PL_R { PL_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
pub fn mem2mem (& self) -> MEM2MEM_R { MEM2MEM_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EN_W < CFGR4_SPEC > { EN_W :: new (self , 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
# [must_use]
pub fn tcie (& mut self) -> TCIE_W < CFGR4_SPEC > { TCIE_W :: new (self , 1) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
# [must_use]
pub fn htie (& mut self) -> HTIE_W < CFGR4_SPEC > { HTIE_W :: new (self , 2) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
# [must_use]
pub fn teie (& mut self) -> TEIE_W < CFGR4_SPEC > { TEIE_W :: new (self , 3) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
# [must_use]
pub fn dir (& mut self) -> DIR_W < CFGR4_SPEC > { DIR_W :: new (self , 4) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
# [must_use]
pub fn circ (& mut self) -> CIRC_W < CFGR4_SPEC > { CIRC_W :: new (self , 5) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
# [must_use]
pub fn pinc (& mut self) -> PINC_W < CFGR4_SPEC > { PINC_W :: new (self , 6) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
# [must_use]
pub fn minc (& mut self) -> MINC_W < CFGR4_SPEC > { MINC_W :: new (self , 7) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
# [must_use]
pub fn psize (& mut self) -> PSIZE_W < CFGR4_SPEC > { PSIZE_W :: new (self , 8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
# [must_use]
pub fn msize (& mut self) -> MSIZE_W < CFGR4_SPEC > { MSIZE_W :: new (self , 10) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
# [must_use]
pub fn pl (& mut self) -> PL_W < CFGR4_SPEC > { PL_W :: new (self , 12) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
# [must_use]
pub fn mem2mem (& mut self) -> MEM2MEM_W < CFGR4_SPEC > { MEM2MEM_W :: new (self , 14) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr4::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGR4_SPEC ; impl crate :: RegisterSpec for CFGR4_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr4::R`](R) reader structure"]
impl crate :: Readable for CFGR4_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgr4::W`](W) writer structure"]
impl crate :: Writable for CFGR4_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFGR4 to value 0"]
impl crate :: Resettable for CFGR4_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CNTR4 (rw) register accessor: DMA channel 4 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr4::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntr4`]
module"]
pub type CNTR4 = crate :: Reg < cntr4 :: CNTR4_SPEC > ; # [doc = "DMA channel 4 number of data register"]
pub mod cntr4 { # [doc = "Register `CNTR4` reader"]
pub type R = crate :: R < CNTR4_SPEC > ; # [doc = "Register `CNTR4` writer"]
pub type W = crate :: W < CNTR4_SPEC > ; # [doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate :: FieldReader < u16 > ; # [doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
pub fn ndt (& self) -> NDT_R { NDT_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
# [must_use]
pub fn ndt (& mut self) -> NDT_W < CNTR4_SPEC > { NDT_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 4 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr4::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CNTR4_SPEC ; impl crate :: RegisterSpec for CNTR4_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cntr4::R`](R) reader structure"]
impl crate :: Readable for CNTR4_SPEC { } # [doc = "`write(|w| ..)` method takes [`cntr4::W`](W) writer structure"]
impl crate :: Writable for CNTR4_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CNTR4 to value 0"]
impl crate :: Resettable for CNTR4_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADDR4 (rw) register accessor: DMA channel 4 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr4::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@paddr4`]
module"]
pub type PADDR4 = crate :: Reg < paddr4 :: PADDR4_SPEC > ; # [doc = "DMA channel 4 peripheral address register"]
pub mod paddr4 { # [doc = "Register `PADDR4` reader"]
pub type R = crate :: R < PADDR4_SPEC > ; # [doc = "Register `PADDR4` writer"]
pub type W = crate :: W < PADDR4_SPEC > ; # [doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate :: FieldReader < u32 > ; # [doc = "Field `PA` writer - Peripheral address"]
pub type PA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
pub fn pa (& self) -> PA_R { PA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
# [must_use]
pub fn pa (& mut self) -> PA_W < PADDR4_SPEC > { PA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 4 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr4::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PADDR4_SPEC ; impl crate :: RegisterSpec for PADDR4_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`paddr4::R`](R) reader structure"]
impl crate :: Readable for PADDR4_SPEC { } # [doc = "`write(|w| ..)` method takes [`paddr4::W`](W) writer structure"]
impl crate :: Writable for PADDR4_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADDR4 to value 0"]
impl crate :: Resettable for PADDR4_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "MADDR4 (rw) register accessor: DMA channel 4 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr4::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@maddr4`]
module"]
pub type MADDR4 = crate :: Reg < maddr4 :: MADDR4_SPEC > ; # [doc = "DMA channel 4 memory address register"]
pub mod maddr4 { # [doc = "Register `MADDR4` reader"]
pub type R = crate :: R < MADDR4_SPEC > ; # [doc = "Register `MADDR4` writer"]
pub type W = crate :: W < MADDR4_SPEC > ; # [doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate :: FieldReader < u32 > ; # [doc = "Field `MA` writer - Memory address"]
pub type MA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
pub fn ma (& self) -> MA_R { MA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
# [must_use]
pub fn ma (& mut self) -> MA_W < MADDR4_SPEC > { MA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 4 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr4::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MADDR4_SPEC ; impl crate :: RegisterSpec for MADDR4_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`maddr4::R`](R) reader structure"]
impl crate :: Readable for MADDR4_SPEC { } # [doc = "`write(|w| ..)` method takes [`maddr4::W`](W) writer structure"]
impl crate :: Writable for MADDR4_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MADDR4 to value 0"]
impl crate :: Resettable for MADDR4_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFGR5 (rw) register accessor: DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr5::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr5`]
module"]
pub type CFGR5 = crate :: Reg < cfgr5 :: CFGR5_SPEC > ; # [doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr5 { # [doc = "Register `CFGR5` reader"]
pub type R = crate :: R < CFGR5_SPEC > ; # [doc = "Register `CFGR5` writer"]
pub type W = crate :: W < CFGR5_SPEC > ; # [doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate :: BitReader ; # [doc = "Field `EN` writer - Channel enable"]
pub type EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate :: BitReader ; # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate :: BitReader ; # [doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate :: BitReader ; # [doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate :: BitReader ; # [doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate :: BitReader ; # [doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate :: BitReader ; # [doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate :: BitReader ; # [doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate :: FieldReader ; # [doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate :: FieldReader ; # [doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate :: FieldReader ; # [doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate :: BitReader ; # [doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
pub fn en (& self) -> EN_R { EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
pub fn tcie (& self) -> TCIE_R { TCIE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
pub fn htie (& self) -> HTIE_R { HTIE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
pub fn teie (& self) -> TEIE_R { TEIE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
pub fn dir (& self) -> DIR_R { DIR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
pub fn circ (& self) -> CIRC_R { CIRC_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
pub fn pinc (& self) -> PINC_R { PINC_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
pub fn minc (& self) -> MINC_R { MINC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
pub fn psize (& self) -> PSIZE_R { PSIZE_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
pub fn msize (& self) -> MSIZE_R { MSIZE_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
pub fn pl (& self) -> PL_R { PL_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
pub fn mem2mem (& self) -> MEM2MEM_R { MEM2MEM_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EN_W < CFGR5_SPEC > { EN_W :: new (self , 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
# [must_use]
pub fn tcie (& mut self) -> TCIE_W < CFGR5_SPEC > { TCIE_W :: new (self , 1) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
# [must_use]
pub fn htie (& mut self) -> HTIE_W < CFGR5_SPEC > { HTIE_W :: new (self , 2) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
# [must_use]
pub fn teie (& mut self) -> TEIE_W < CFGR5_SPEC > { TEIE_W :: new (self , 3) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
# [must_use]
pub fn dir (& mut self) -> DIR_W < CFGR5_SPEC > { DIR_W :: new (self , 4) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
# [must_use]
pub fn circ (& mut self) -> CIRC_W < CFGR5_SPEC > { CIRC_W :: new (self , 5) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
# [must_use]
pub fn pinc (& mut self) -> PINC_W < CFGR5_SPEC > { PINC_W :: new (self , 6) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
# [must_use]
pub fn minc (& mut self) -> MINC_W < CFGR5_SPEC > { MINC_W :: new (self , 7) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
# [must_use]
pub fn psize (& mut self) -> PSIZE_W < CFGR5_SPEC > { PSIZE_W :: new (self , 8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
# [must_use]
pub fn msize (& mut self) -> MSIZE_W < CFGR5_SPEC > { MSIZE_W :: new (self , 10) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
# [must_use]
pub fn pl (& mut self) -> PL_W < CFGR5_SPEC > { PL_W :: new (self , 12) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
# [must_use]
pub fn mem2mem (& mut self) -> MEM2MEM_W < CFGR5_SPEC > { MEM2MEM_W :: new (self , 14) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr5::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGR5_SPEC ; impl crate :: RegisterSpec for CFGR5_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr5::R`](R) reader structure"]
impl crate :: Readable for CFGR5_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgr5::W`](W) writer structure"]
impl crate :: Writable for CFGR5_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFGR5 to value 0"]
impl crate :: Resettable for CFGR5_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CNTR5 (rw) register accessor: DMA channel 5 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr5::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntr5`]
module"]
pub type CNTR5 = crate :: Reg < cntr5 :: CNTR5_SPEC > ; # [doc = "DMA channel 5 number of data register"]
pub mod cntr5 { # [doc = "Register `CNTR5` reader"]
pub type R = crate :: R < CNTR5_SPEC > ; # [doc = "Register `CNTR5` writer"]
pub type W = crate :: W < CNTR5_SPEC > ; # [doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate :: FieldReader < u16 > ; # [doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
pub fn ndt (& self) -> NDT_R { NDT_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
# [must_use]
pub fn ndt (& mut self) -> NDT_W < CNTR5_SPEC > { NDT_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 5 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr5::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CNTR5_SPEC ; impl crate :: RegisterSpec for CNTR5_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cntr5::R`](R) reader structure"]
impl crate :: Readable for CNTR5_SPEC { } # [doc = "`write(|w| ..)` method takes [`cntr5::W`](W) writer structure"]
impl crate :: Writable for CNTR5_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CNTR5 to value 0"]
impl crate :: Resettable for CNTR5_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADDR5 (rw) register accessor: DMA channel 5 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr5::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@paddr5`]
module"]
pub type PADDR5 = crate :: Reg < paddr5 :: PADDR5_SPEC > ; # [doc = "DMA channel 5 peripheral address register"]
pub mod paddr5 { # [doc = "Register `PADDR5` reader"]
pub type R = crate :: R < PADDR5_SPEC > ; # [doc = "Register `PADDR5` writer"]
pub type W = crate :: W < PADDR5_SPEC > ; # [doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate :: FieldReader < u32 > ; # [doc = "Field `PA` writer - Peripheral address"]
pub type PA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
pub fn pa (& self) -> PA_R { PA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
# [must_use]
pub fn pa (& mut self) -> PA_W < PADDR5_SPEC > { PA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 5 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr5::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PADDR5_SPEC ; impl crate :: RegisterSpec for PADDR5_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`paddr5::R`](R) reader structure"]
impl crate :: Readable for PADDR5_SPEC { } # [doc = "`write(|w| ..)` method takes [`paddr5::W`](W) writer structure"]
impl crate :: Writable for PADDR5_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADDR5 to value 0"]
impl crate :: Resettable for PADDR5_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "MADDR5 (rw) register accessor: DMA channel 5 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr5::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@maddr5`]
module"]
pub type MADDR5 = crate :: Reg < maddr5 :: MADDR5_SPEC > ; # [doc = "DMA channel 5 memory address register"]
pub mod maddr5 { # [doc = "Register `MADDR5` reader"]
pub type R = crate :: R < MADDR5_SPEC > ; # [doc = "Register `MADDR5` writer"]
pub type W = crate :: W < MADDR5_SPEC > ; # [doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate :: FieldReader < u32 > ; # [doc = "Field `MA` writer - Memory address"]
pub type MA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
pub fn ma (& self) -> MA_R { MA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
# [must_use]
pub fn ma (& mut self) -> MA_W < MADDR5_SPEC > { MA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 5 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr5::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MADDR5_SPEC ; impl crate :: RegisterSpec for MADDR5_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`maddr5::R`](R) reader structure"]
impl crate :: Readable for MADDR5_SPEC { } # [doc = "`write(|w| ..)` method takes [`maddr5::W`](W) writer structure"]
impl crate :: Writable for MADDR5_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MADDR5 to value 0"]
impl crate :: Resettable for MADDR5_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFGR6 (rw) register accessor: DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr6::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr6`]
module"]
pub type CFGR6 = crate :: Reg < cfgr6 :: CFGR6_SPEC > ; # [doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr6 { # [doc = "Register `CFGR6` reader"]
pub type R = crate :: R < CFGR6_SPEC > ; # [doc = "Register `CFGR6` writer"]
pub type W = crate :: W < CFGR6_SPEC > ; # [doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate :: BitReader ; # [doc = "Field `EN` writer - Channel enable"]
pub type EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate :: BitReader ; # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate :: BitReader ; # [doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate :: BitReader ; # [doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate :: BitReader ; # [doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate :: BitReader ; # [doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate :: BitReader ; # [doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate :: BitReader ; # [doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate :: FieldReader ; # [doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate :: FieldReader ; # [doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate :: FieldReader ; # [doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate :: BitReader ; # [doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
pub fn en (& self) -> EN_R { EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
pub fn tcie (& self) -> TCIE_R { TCIE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
pub fn htie (& self) -> HTIE_R { HTIE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
pub fn teie (& self) -> TEIE_R { TEIE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
pub fn dir (& self) -> DIR_R { DIR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
pub fn circ (& self) -> CIRC_R { CIRC_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
pub fn pinc (& self) -> PINC_R { PINC_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
pub fn minc (& self) -> MINC_R { MINC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
pub fn psize (& self) -> PSIZE_R { PSIZE_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
pub fn msize (& self) -> MSIZE_R { MSIZE_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
pub fn pl (& self) -> PL_R { PL_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
pub fn mem2mem (& self) -> MEM2MEM_R { MEM2MEM_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EN_W < CFGR6_SPEC > { EN_W :: new (self , 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
# [must_use]
pub fn tcie (& mut self) -> TCIE_W < CFGR6_SPEC > { TCIE_W :: new (self , 1) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
# [must_use]
pub fn htie (& mut self) -> HTIE_W < CFGR6_SPEC > { HTIE_W :: new (self , 2) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
# [must_use]
pub fn teie (& mut self) -> TEIE_W < CFGR6_SPEC > { TEIE_W :: new (self , 3) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
# [must_use]
pub fn dir (& mut self) -> DIR_W < CFGR6_SPEC > { DIR_W :: new (self , 4) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
# [must_use]
pub fn circ (& mut self) -> CIRC_W < CFGR6_SPEC > { CIRC_W :: new (self , 5) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
# [must_use]
pub fn pinc (& mut self) -> PINC_W < CFGR6_SPEC > { PINC_W :: new (self , 6) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
# [must_use]
pub fn minc (& mut self) -> MINC_W < CFGR6_SPEC > { MINC_W :: new (self , 7) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
# [must_use]
pub fn psize (& mut self) -> PSIZE_W < CFGR6_SPEC > { PSIZE_W :: new (self , 8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
# [must_use]
pub fn msize (& mut self) -> MSIZE_W < CFGR6_SPEC > { MSIZE_W :: new (self , 10) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
# [must_use]
pub fn pl (& mut self) -> PL_W < CFGR6_SPEC > { PL_W :: new (self , 12) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
# [must_use]
pub fn mem2mem (& mut self) -> MEM2MEM_W < CFGR6_SPEC > { MEM2MEM_W :: new (self , 14) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr6::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGR6_SPEC ; impl crate :: RegisterSpec for CFGR6_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr6::R`](R) reader structure"]
impl crate :: Readable for CFGR6_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgr6::W`](W) writer structure"]
impl crate :: Writable for CFGR6_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFGR6 to value 0"]
impl crate :: Resettable for CFGR6_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CNTR6 (rw) register accessor: DMA channel 6 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr6::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntr6`]
module"]
pub type CNTR6 = crate :: Reg < cntr6 :: CNTR6_SPEC > ; # [doc = "DMA channel 6 number of data register"]
pub mod cntr6 { # [doc = "Register `CNTR6` reader"]
pub type R = crate :: R < CNTR6_SPEC > ; # [doc = "Register `CNTR6` writer"]
pub type W = crate :: W < CNTR6_SPEC > ; # [doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate :: FieldReader < u16 > ; # [doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
pub fn ndt (& self) -> NDT_R { NDT_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
# [must_use]
pub fn ndt (& mut self) -> NDT_W < CNTR6_SPEC > { NDT_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 6 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr6::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CNTR6_SPEC ; impl crate :: RegisterSpec for CNTR6_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cntr6::R`](R) reader structure"]
impl crate :: Readable for CNTR6_SPEC { } # [doc = "`write(|w| ..)` method takes [`cntr6::W`](W) writer structure"]
impl crate :: Writable for CNTR6_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CNTR6 to value 0"]
impl crate :: Resettable for CNTR6_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADDR6 (rw) register accessor: DMA channel 6 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr6::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@paddr6`]
module"]
pub type PADDR6 = crate :: Reg < paddr6 :: PADDR6_SPEC > ; # [doc = "DMA channel 6 peripheral address register"]
pub mod paddr6 { # [doc = "Register `PADDR6` reader"]
pub type R = crate :: R < PADDR6_SPEC > ; # [doc = "Register `PADDR6` writer"]
pub type W = crate :: W < PADDR6_SPEC > ; # [doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate :: FieldReader < u32 > ; # [doc = "Field `PA` writer - Peripheral address"]
pub type PA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
pub fn pa (& self) -> PA_R { PA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
# [must_use]
pub fn pa (& mut self) -> PA_W < PADDR6_SPEC > { PA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 6 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr6::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PADDR6_SPEC ; impl crate :: RegisterSpec for PADDR6_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`paddr6::R`](R) reader structure"]
impl crate :: Readable for PADDR6_SPEC { } # [doc = "`write(|w| ..)` method takes [`paddr6::W`](W) writer structure"]
impl crate :: Writable for PADDR6_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADDR6 to value 0"]
impl crate :: Resettable for PADDR6_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "MADDR6 (rw) register accessor: DMA channel 6 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr6::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@maddr6`]
module"]
pub type MADDR6 = crate :: Reg < maddr6 :: MADDR6_SPEC > ; # [doc = "DMA channel 6 memory address register"]
pub mod maddr6 { # [doc = "Register `MADDR6` reader"]
pub type R = crate :: R < MADDR6_SPEC > ; # [doc = "Register `MADDR6` writer"]
pub type W = crate :: W < MADDR6_SPEC > ; # [doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate :: FieldReader < u32 > ; # [doc = "Field `MA` writer - Memory address"]
pub type MA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
pub fn ma (& self) -> MA_R { MA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
# [must_use]
pub fn ma (& mut self) -> MA_W < MADDR6_SPEC > { MA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 6 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr6::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MADDR6_SPEC ; impl crate :: RegisterSpec for MADDR6_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`maddr6::R`](R) reader structure"]
impl crate :: Readable for MADDR6_SPEC { } # [doc = "`write(|w| ..)` method takes [`maddr6::W`](W) writer structure"]
impl crate :: Writable for MADDR6_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MADDR6 to value 0"]
impl crate :: Resettable for MADDR6_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFGR7 (rw) register accessor: DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr7::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr7`]
module"]
pub type CFGR7 = crate :: Reg < cfgr7 :: CFGR7_SPEC > ; # [doc = "DMA channel configuration register (DMA_CFGR)"]
pub mod cfgr7 { # [doc = "Register `CFGR7` reader"]
pub type R = crate :: R < CFGR7_SPEC > ; # [doc = "Register `CFGR7` writer"]
pub type W = crate :: W < CFGR7_SPEC > ; # [doc = "Field `EN` reader - Channel enable"]
pub type EN_R = crate :: BitReader ; # [doc = "Field `EN` writer - Channel enable"]
pub type EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TCIE_R = crate :: BitReader ; # [doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TCIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
pub type HTIE_R = crate :: BitReader ; # [doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
pub type HTIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEIE` reader - Transfer error interrupt enable"]
pub type TEIE_R = crate :: BitReader ; # [doc = "Field `TEIE` writer - Transfer error interrupt enable"]
pub type TEIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DIR` reader - Data transfer direction"]
pub type DIR_R = crate :: BitReader ; # [doc = "Field `DIR` writer - Data transfer direction"]
pub type DIR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CIRC` reader - Circular mode"]
pub type CIRC_R = crate :: BitReader ; # [doc = "Field `CIRC` writer - Circular mode"]
pub type CIRC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PINC` reader - Peripheral increment mode"]
pub type PINC_R = crate :: BitReader ; # [doc = "Field `PINC` writer - Peripheral increment mode"]
pub type PINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MINC` reader - Memory increment mode"]
pub type MINC_R = crate :: BitReader ; # [doc = "Field `MINC` writer - Memory increment mode"]
pub type MINC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PSIZE` reader - Peripheral size"]
pub type PSIZE_R = crate :: FieldReader ; # [doc = "Field `PSIZE` writer - Peripheral size"]
pub type PSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MSIZE` reader - Memory size"]
pub type MSIZE_R = crate :: FieldReader ; # [doc = "Field `MSIZE` writer - Memory size"]
pub type MSIZE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PL` reader - Channel Priority level"]
pub type PL_R = crate :: FieldReader ; # [doc = "Field `PL` writer - Channel Priority level"]
pub type PL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MEM2MEM` reader - Memory to memory mode"]
pub type MEM2MEM_R = crate :: BitReader ; # [doc = "Field `MEM2MEM` writer - Memory to memory mode"]
pub type MEM2MEM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
pub fn en (& self) -> EN_R { EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
pub fn tcie (& self) -> TCIE_R { TCIE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
pub fn htie (& self) -> HTIE_R { HTIE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
pub fn teie (& self) -> TEIE_R { TEIE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
pub fn dir (& self) -> DIR_R { DIR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
pub fn circ (& self) -> CIRC_R { CIRC_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
pub fn pinc (& self) -> PINC_R { PINC_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
pub fn minc (& self) -> MINC_R { MINC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
pub fn psize (& self) -> PSIZE_R { PSIZE_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
pub fn msize (& self) -> MSIZE_R { MSIZE_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
pub fn pl (& self) -> PL_R { PL_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
pub fn mem2mem (& self) -> MEM2MEM_R { MEM2MEM_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Channel enable"]
# [inline (always)]
# [must_use]
pub fn en (& mut self) -> EN_W < CFGR7_SPEC > { EN_W :: new (self , 0) } # [doc = "Bit 1 - Transfer complete interrupt enable"]
# [inline (always)]
# [must_use]
pub fn tcie (& mut self) -> TCIE_W < CFGR7_SPEC > { TCIE_W :: new (self , 1) } # [doc = "Bit 2 - Half Transfer interrupt enable"]
# [inline (always)]
# [must_use]
pub fn htie (& mut self) -> HTIE_W < CFGR7_SPEC > { HTIE_W :: new (self , 2) } # [doc = "Bit 3 - Transfer error interrupt enable"]
# [inline (always)]
# [must_use]
pub fn teie (& mut self) -> TEIE_W < CFGR7_SPEC > { TEIE_W :: new (self , 3) } # [doc = "Bit 4 - Data transfer direction"]
# [inline (always)]
# [must_use]
pub fn dir (& mut self) -> DIR_W < CFGR7_SPEC > { DIR_W :: new (self , 4) } # [doc = "Bit 5 - Circular mode"]
# [inline (always)]
# [must_use]
pub fn circ (& mut self) -> CIRC_W < CFGR7_SPEC > { CIRC_W :: new (self , 5) } # [doc = "Bit 6 - Peripheral increment mode"]
# [inline (always)]
# [must_use]
pub fn pinc (& mut self) -> PINC_W < CFGR7_SPEC > { PINC_W :: new (self , 6) } # [doc = "Bit 7 - Memory increment mode"]
# [inline (always)]
# [must_use]
pub fn minc (& mut self) -> MINC_W < CFGR7_SPEC > { MINC_W :: new (self , 7) } # [doc = "Bits 8:9 - Peripheral size"]
# [inline (always)]
# [must_use]
pub fn psize (& mut self) -> PSIZE_W < CFGR7_SPEC > { PSIZE_W :: new (self , 8) } # [doc = "Bits 10:11 - Memory size"]
# [inline (always)]
# [must_use]
pub fn msize (& mut self) -> MSIZE_W < CFGR7_SPEC > { MSIZE_W :: new (self , 10) } # [doc = "Bits 12:13 - Channel Priority level"]
# [inline (always)]
# [must_use]
pub fn pl (& mut self) -> PL_W < CFGR7_SPEC > { PL_W :: new (self , 12) } # [doc = "Bit 14 - Memory to memory mode"]
# [inline (always)]
# [must_use]
pub fn mem2mem (& mut self) -> MEM2MEM_W < CFGR7_SPEC > { MEM2MEM_W :: new (self , 14) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel configuration register (DMA_CFGR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr7::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGR7_SPEC ; impl crate :: RegisterSpec for CFGR7_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr7::R`](R) reader structure"]
impl crate :: Readable for CFGR7_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgr7::W`](W) writer structure"]
impl crate :: Writable for CFGR7_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFGR7 to value 0"]
impl crate :: Resettable for CFGR7_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CNTR7 (rw) register accessor: DMA channel 7 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr7::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntr7`]
module"]
pub type CNTR7 = crate :: Reg < cntr7 :: CNTR7_SPEC > ; # [doc = "DMA channel 7 number of data register"]
pub mod cntr7 { # [doc = "Register `CNTR7` reader"]
pub type R = crate :: R < CNTR7_SPEC > ; # [doc = "Register `CNTR7` writer"]
pub type W = crate :: W < CNTR7_SPEC > ; # [doc = "Field `NDT` reader - Number of data to transfer"]
pub type NDT_R = crate :: FieldReader < u16 > ; # [doc = "Field `NDT` writer - Number of data to transfer"]
pub type NDT_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
pub fn ndt (& self) -> NDT_R { NDT_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Number of data to transfer"]
# [inline (always)]
# [must_use]
pub fn ndt (& mut self) -> NDT_W < CNTR7_SPEC > { NDT_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 7 number of data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr7::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CNTR7_SPEC ; impl crate :: RegisterSpec for CNTR7_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cntr7::R`](R) reader structure"]
impl crate :: Readable for CNTR7_SPEC { } # [doc = "`write(|w| ..)` method takes [`cntr7::W`](W) writer structure"]
impl crate :: Writable for CNTR7_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CNTR7 to value 0"]
impl crate :: Resettable for CNTR7_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "PADDR7 (rw) register accessor: DMA channel 7 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr7::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@paddr7`]
module"]
pub type PADDR7 = crate :: Reg < paddr7 :: PADDR7_SPEC > ; # [doc = "DMA channel 7 peripheral address register"]
pub mod paddr7 { # [doc = "Register `PADDR7` reader"]
pub type R = crate :: R < PADDR7_SPEC > ; # [doc = "Register `PADDR7` writer"]
pub type W = crate :: W < PADDR7_SPEC > ; # [doc = "Field `PA` reader - Peripheral address"]
pub type PA_R = crate :: FieldReader < u32 > ; # [doc = "Field `PA` writer - Peripheral address"]
pub type PA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
pub fn pa (& self) -> PA_R { PA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Peripheral address"]
# [inline (always)]
# [must_use]
pub fn pa (& mut self) -> PA_W < PADDR7_SPEC > { PA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 7 peripheral address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`paddr7::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`paddr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PADDR7_SPEC ; impl crate :: RegisterSpec for PADDR7_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`paddr7::R`](R) reader structure"]
impl crate :: Readable for PADDR7_SPEC { } # [doc = "`write(|w| ..)` method takes [`paddr7::W`](W) writer structure"]
impl crate :: Writable for PADDR7_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PADDR7 to value 0"]
impl crate :: Resettable for PADDR7_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "MADDR7 (rw) register accessor: DMA channel 7 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr7::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@maddr7`]
module"]
pub type MADDR7 = crate :: Reg < maddr7 :: MADDR7_SPEC > ; # [doc = "DMA channel 7 memory address register"]
pub mod maddr7 { # [doc = "Register `MADDR7` reader"]
pub type R = crate :: R < MADDR7_SPEC > ; # [doc = "Register `MADDR7` writer"]
pub type W = crate :: W < MADDR7_SPEC > ; # [doc = "Field `MA` reader - Memory address"]
pub type MA_R = crate :: FieldReader < u32 > ; # [doc = "Field `MA` writer - Memory address"]
pub type MA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
pub fn ma (& self) -> MA_R { MA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Memory address"]
# [inline (always)]
# [must_use]
pub fn ma (& mut self) -> MA_W < MADDR7_SPEC > { MA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA channel 7 memory address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`maddr7::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`maddr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MADDR7_SPEC ; impl crate :: RegisterSpec for MADDR7_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`maddr7::R`](R) reader structure"]
impl crate :: Readable for MADDR7_SPEC { } # [doc = "`write(|w| ..)` method takes [`maddr7::W`](W) writer structure"]
impl crate :: Writable for MADDR7_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MADDR7 to value 0"]
impl crate :: Resettable for MADDR7_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Real time clock"]
pub struct RTC { _marker : PhantomData < * const () > } unsafe impl Send for RTC { } impl RTC { # [doc = r"Pointer to the register block"]
pub const PTR : * const rtc :: RegisterBlock = 0x4000_2800 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const rtc :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for RTC { type Target = rtc :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for RTC { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("RTC") . finish () } } # [doc = "Real time clock"]
pub mod rtc { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { ctlrh : CTLRH , ctlrl : CTLRL , pscrh : PSCRH , pscrl : PSCRL , divh : DIVH , divl : DIVL , cnth : CNTH , cntl : CNTL , alrmh : ALRMH , alrml : ALRML , } impl RegisterBlock { # [doc = "0x00 - RTC Control Register High"]
# [inline (always)]
pub const fn ctlrh (& self) -> & CTLRH { & self . ctlrh } # [doc = "0x04 - RTC Control Register Low"]
# [inline (always)]
pub const fn ctlrl (& self) -> & CTLRL { & self . ctlrl } # [doc = "0x08 - RTC Prescaler Load Register High"]
# [inline (always)]
pub const fn pscrh (& self) -> & PSCRH { & self . pscrh } # [doc = "0x0c - RTC Prescaler Load Register Low"]
# [inline (always)]
pub const fn pscrl (& self) -> & PSCRL { & self . pscrl } # [doc = "0x10 - RTC Prescaler Divider Register High"]
# [inline (always)]
pub const fn divh (& self) -> & DIVH { & self . divh } # [doc = "0x14 - RTC Prescaler Divider Register Low"]
# [inline (always)]
pub const fn divl (& self) -> & DIVL { & self . divl } # [doc = "0x18 - RTC Counter Register High"]
# [inline (always)]
pub const fn cnth (& self) -> & CNTH { & self . cnth } # [doc = "0x1c - RTC Counter Register Low"]
# [inline (always)]
pub const fn cntl (& self) -> & CNTL { & self . cntl } # [doc = "0x20 - RTC Alarm Register High"]
# [inline (always)]
pub const fn alrmh (& self) -> & ALRMH { & self . alrmh } # [doc = "0x24 - RTC Alarm Register Low"]
# [inline (always)]
pub const fn alrml (& self) -> & ALRML { & self . alrml } } # [doc = "CTLRH (rw) register accessor: RTC Control Register High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlrh::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlrh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlrh`]
module"]
pub type CTLRH = crate :: Reg < ctlrh :: CTLRH_SPEC > ; # [doc = "RTC Control Register High"]
pub mod ctlrh { # [doc = "Register `CTLRH` reader"]
pub type R = crate :: R < CTLRH_SPEC > ; # [doc = "Register `CTLRH` writer"]
pub type W = crate :: W < CTLRH_SPEC > ; # [doc = "Field `SECIE` reader - Second interrupt Enable"]
pub type SECIE_R = crate :: BitReader ; # [doc = "Field `SECIE` writer - Second interrupt Enable"]
pub type SECIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ALRIE` reader - Alarm interrupt Enable"]
pub type ALRIE_R = crate :: BitReader ; # [doc = "Field `ALRIE` writer - Alarm interrupt Enable"]
pub type ALRIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OWIE` reader - Overflow interrupt Enable"]
pub type OWIE_R = crate :: BitReader ; # [doc = "Field `OWIE` writer - Overflow interrupt Enable"]
pub type OWIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Second interrupt Enable"]
# [inline (always)]
pub fn secie (& self) -> SECIE_R { SECIE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Alarm interrupt Enable"]
# [inline (always)]
pub fn alrie (& self) -> ALRIE_R { ALRIE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Overflow interrupt Enable"]
# [inline (always)]
pub fn owie (& self) -> OWIE_R { OWIE_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Second interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn secie (& mut self) -> SECIE_W < CTLRH_SPEC > { SECIE_W :: new (self , 0) } # [doc = "Bit 1 - Alarm interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn alrie (& mut self) -> ALRIE_W < CTLRH_SPEC > { ALRIE_W :: new (self , 1) } # [doc = "Bit 2 - Overflow interrupt Enable"]
# [inline (always)]
# [must_use]
pub fn owie (& mut self) -> OWIE_W < CTLRH_SPEC > { OWIE_W :: new (self , 2) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "RTC Control Register High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlrh::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlrh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLRH_SPEC ; impl crate :: RegisterSpec for CTLRH_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlrh::R`](R) reader structure"]
impl crate :: Readable for CTLRH_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlrh::W`](W) writer structure"]
impl crate :: Writable for CTLRH_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLRH to value 0"]
impl crate :: Resettable for CTLRH_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTLRL (rw) register accessor: RTC Control Register Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlrl`]
module"]
pub type CTLRL = crate :: Reg < ctlrl :: CTLRL_SPEC > ; # [doc = "RTC Control Register Low"]
pub mod ctlrl { # [doc = "Register `CTLRL` reader"]
pub type R = crate :: R < CTLRL_SPEC > ; # [doc = "Register `CTLRL` writer"]
pub type W = crate :: W < CTLRL_SPEC > ; # [doc = "Field `SECF` reader - Second Flag"]
pub type SECF_R = crate :: BitReader ; # [doc = "Field `SECF` writer - Second Flag"]
pub type SECF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ALRF` reader - Alarm Flag"]
pub type ALRF_R = crate :: BitReader ; # [doc = "Field `ALRF` writer - Alarm Flag"]
pub type ALRF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OWF` reader - Overflow Flag"]
pub type OWF_R = crate :: BitReader ; # [doc = "Field `OWF` writer - Overflow Flag"]
pub type OWF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RSF` reader - Registers Synchronized Flag"]
pub type RSF_R = crate :: BitReader ; # [doc = "Field `RSF` writer - Registers Synchronized Flag"]
pub type RSF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CNF` reader - Configuration Flag"]
pub type CNF_R = crate :: BitReader ; # [doc = "Field `CNF` writer - Configuration Flag"]
pub type CNF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RTOFF` reader - RTC operation OFF"]
pub type RTOFF_R = crate :: BitReader ; impl R { # [doc = "Bit 0 - Second Flag"]
# [inline (always)]
pub fn secf (& self) -> SECF_R { SECF_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Alarm Flag"]
# [inline (always)]
pub fn alrf (& self) -> ALRF_R { ALRF_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Overflow Flag"]
# [inline (always)]
pub fn owf (& self) -> OWF_R { OWF_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Registers Synchronized Flag"]
# [inline (always)]
pub fn rsf (& self) -> RSF_R { RSF_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Configuration Flag"]
# [inline (always)]
pub fn cnf (& self) -> CNF_R { CNF_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - RTC operation OFF"]
# [inline (always)]
pub fn rtoff (& self) -> RTOFF_R { RTOFF_R :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bit 0 - Second Flag"]
# [inline (always)]
# [must_use]
pub fn secf (& mut self) -> SECF_W < CTLRL_SPEC > { SECF_W :: new (self , 0) } # [doc = "Bit 1 - Alarm Flag"]
# [inline (always)]
# [must_use]
pub fn alrf (& mut self) -> ALRF_W < CTLRL_SPEC > { ALRF_W :: new (self , 1) } # [doc = "Bit 2 - Overflow Flag"]
# [inline (always)]
# [must_use]
pub fn owf (& mut self) -> OWF_W < CTLRL_SPEC > { OWF_W :: new (self , 2) } # [doc = "Bit 3 - Registers Synchronized Flag"]
# [inline (always)]
# [must_use]
pub fn rsf (& mut self) -> RSF_W < CTLRL_SPEC > { RSF_W :: new (self , 3) } # [doc = "Bit 4 - Configuration Flag"]
# [inline (always)]
# [must_use]
pub fn cnf (& mut self) -> CNF_W < CTLRL_SPEC > { CNF_W :: new (self , 4) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "RTC Control Register Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLRL_SPEC ; impl crate :: RegisterSpec for CTLRL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlrl::R`](R) reader structure"]
impl crate :: Readable for CTLRL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlrl::W`](W) writer structure"]
impl crate :: Writable for CTLRL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLRL to value 0x20"]
impl crate :: Resettable for CTLRL_SPEC { const RESET_VALUE : u32 = 0x20 ; } } # [doc = "PSCRH (w) register accessor: RTC Prescaler Load Register High\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pscrh::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pscrh`]
module"]
pub type PSCRH = crate :: Reg < pscrh :: PSCRH_SPEC > ; # [doc = "RTC Prescaler Load Register High"]
pub mod pscrh { # [doc = "Register `PSCRH` writer"]
pub type W = crate :: W < PSCRH_SPEC > ; # [doc = "Field `PRLH` writer - RTC Prescaler Load Register High"]
pub type PRLH_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl W { # [doc = "Bits 0:3 - RTC Prescaler Load Register High"]
# [inline (always)]
# [must_use]
pub fn prlh (& mut self) -> PRLH_W < PSCRH_SPEC > { PRLH_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "RTC Prescaler Load Register High\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pscrh::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PSCRH_SPEC ; impl crate :: RegisterSpec for PSCRH_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`pscrh::W`](W) writer structure"]
impl crate :: Writable for PSCRH_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSCRH to value 0"]
impl crate :: Resettable for PSCRH_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSCRL (w) register accessor: RTC Prescaler Load Register Low\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pscrl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pscrl`]
module"]
pub type PSCRL = crate :: Reg < pscrl :: PSCRL_SPEC > ; # [doc = "RTC Prescaler Load Register Low"]
pub mod pscrl { # [doc = "Register `PSCRL` writer"]
pub type W = crate :: W < PSCRL_SPEC > ; # [doc = "Field `PRLL` writer - RTC Prescaler Divider Register Low"]
pub type PRLL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl W { # [doc = "Bits 0:15 - RTC Prescaler Divider Register Low"]
# [inline (always)]
# [must_use]
pub fn prll (& mut self) -> PRLL_W < PSCRL_SPEC > { PRLL_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "RTC Prescaler Load Register Low\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pscrl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PSCRL_SPEC ; impl crate :: RegisterSpec for PSCRL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`pscrl::W`](W) writer structure"]
impl crate :: Writable for PSCRL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSCRL to value 0x8000"]
impl crate :: Resettable for PSCRL_SPEC { const RESET_VALUE : u32 = 0x8000 ; } } # [doc = "DIVH (r) register accessor: RTC Prescaler Divider Register High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`divh::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@divh`]
module"]
pub type DIVH = crate :: Reg < divh :: DIVH_SPEC > ; # [doc = "RTC Prescaler Divider Register High"]
pub mod divh { # [doc = "Register `DIVH` reader"]
pub type R = crate :: R < DIVH_SPEC > ; # [doc = "Field `DIVH` reader - RTC prescaler divider register high"]
pub type DIVH_R = crate :: FieldReader ; impl R { # [doc = "Bits 0:3 - RTC prescaler divider register high"]
# [inline (always)]
pub fn divh (& self) -> DIVH_R { DIVH_R :: new ((self . bits & 0x0f) as u8) } } # [doc = "RTC Prescaler Divider Register High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`divh::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DIVH_SPEC ; impl crate :: RegisterSpec for DIVH_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`divh::R`](R) reader structure"]
impl crate :: Readable for DIVH_SPEC { } # [doc = "`reset()` method sets DIVH to value 0"]
impl crate :: Resettable for DIVH_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DIVL (r) register accessor: RTC Prescaler Divider Register Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`divl::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@divl`]
module"]
pub type DIVL = crate :: Reg < divl :: DIVL_SPEC > ; # [doc = "RTC Prescaler Divider Register Low"]
pub mod divl { # [doc = "Register `DIVL` reader"]
pub type R = crate :: R < DIVL_SPEC > ; # [doc = "Field `DIVL` reader - RTC prescaler divider register Low"]
pub type DIVL_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:15 - RTC prescaler divider register Low"]
# [inline (always)]
pub fn divl (& self) -> DIVL_R { DIVL_R :: new ((self . bits & 0xffff) as u16) } } # [doc = "RTC Prescaler Divider Register Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`divl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DIVL_SPEC ; impl crate :: RegisterSpec for DIVL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`divl::R`](R) reader structure"]
impl crate :: Readable for DIVL_SPEC { } # [doc = "`reset()` method sets DIVL to value 0x8000"]
impl crate :: Resettable for DIVL_SPEC { const RESET_VALUE : u32 = 0x8000 ; } } # [doc = "CNTH (rw) register accessor: RTC Counter Register High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnth::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnth::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnth`]
module"]
pub type CNTH = crate :: Reg < cnth :: CNTH_SPEC > ; # [doc = "RTC Counter Register High"]
pub mod cnth { # [doc = "Register `CNTH` reader"]
pub type R = crate :: R < CNTH_SPEC > ; # [doc = "Register `CNTH` writer"]
pub type W = crate :: W < CNTH_SPEC > ; # [doc = "Field `CNTH` reader - RTC counter register high"]
pub type CNTH_R = crate :: FieldReader < u16 > ; # [doc = "Field `CNTH` writer - RTC counter register high"]
pub type CNTH_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - RTC counter register high"]
# [inline (always)]
pub fn cnth (& self) -> CNTH_R { CNTH_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - RTC counter register high"]
# [inline (always)]
# [must_use]
pub fn cnth (& mut self) -> CNTH_W < CNTH_SPEC > { CNTH_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "RTC Counter Register High\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnth::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnth::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CNTH_SPEC ; impl crate :: RegisterSpec for CNTH_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cnth::R`](R) reader structure"]
impl crate :: Readable for CNTH_SPEC { } # [doc = "`write(|w| ..)` method takes [`cnth::W`](W) writer structure"]
impl crate :: Writable for CNTH_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CNTH to value 0"]
impl crate :: Resettable for CNTH_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CNTL (rw) register accessor: RTC Counter Register Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntl`]
module"]
pub type CNTL = crate :: Reg < cntl :: CNTL_SPEC > ; # [doc = "RTC Counter Register Low"]
pub mod cntl { # [doc = "Register `CNTL` reader"]
pub type R = crate :: R < CNTL_SPEC > ; # [doc = "Register `CNTL` writer"]
pub type W = crate :: W < CNTL_SPEC > ; # [doc = "Field `CNTL` reader - RTC counter register Low"]
pub type CNTL_R = crate :: FieldReader < u16 > ; # [doc = "Field `CNTL` writer - RTC counter register Low"]
pub type CNTL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - RTC counter register Low"]
# [inline (always)]
pub fn cntl (& self) -> CNTL_R { CNTL_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - RTC counter register Low"]
# [inline (always)]
# [must_use]
pub fn cntl (& mut self) -> CNTL_W < CNTL_SPEC > { CNTL_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "RTC Counter Register Low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CNTL_SPEC ; impl crate :: RegisterSpec for CNTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cntl::R`](R) reader structure"]
impl crate :: Readable for CNTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`cntl::W`](W) writer structure"]
impl crate :: Writable for CNTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CNTL to value 0"]
impl crate :: Resettable for CNTL_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "ALRMH (w) register accessor: RTC Alarm Register High\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alrmh::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@alrmh`]
module"]
pub type ALRMH = crate :: Reg < alrmh :: ALRMH_SPEC > ; # [doc = "RTC Alarm Register High"]
pub mod alrmh { # [doc = "Register `ALRMH` writer"]
pub type W = crate :: W < ALRMH_SPEC > ; # [doc = "Field `ALRMH` writer - RTC alarm register high"]
pub type ALRMH_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl W { # [doc = "Bits 0:15 - RTC alarm register high"]
# [inline (always)]
# [must_use]
pub fn alrmh (& mut self) -> ALRMH_W < ALRMH_SPEC > { ALRMH_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "RTC Alarm Register High\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alrmh::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ALRMH_SPEC ; impl crate :: RegisterSpec for ALRMH_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`alrmh::W`](W) writer structure"]
impl crate :: Writable for ALRMH_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ALRMH to value 0xffff"]
impl crate :: Resettable for ALRMH_SPEC { const RESET_VALUE : u32 = 0xffff ; } } # [doc = "ALRML (w) register accessor: RTC Alarm Register Low\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alrml::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@alrml`]
module"]
pub type ALRML = crate :: Reg < alrml :: ALRML_SPEC > ; # [doc = "RTC Alarm Register Low"]
pub mod alrml { # [doc = "Register `ALRML` writer"]
pub type W = crate :: W < ALRML_SPEC > ; # [doc = "Field `ALRML` writer - RTC alarm register low"]
pub type ALRML_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl W { # [doc = "Bits 0:15 - RTC alarm register low"]
# [inline (always)]
# [must_use]
pub fn alrml (& mut self) -> ALRML_W < ALRML_SPEC > { ALRML_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "RTC Alarm Register Low\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alrml::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ALRML_SPEC ; impl crate :: RegisterSpec for ALRML_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`alrml::W`](W) writer structure"]
impl crate :: Writable for ALRML_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ALRML to value 0xffff"]
impl crate :: Resettable for ALRML_SPEC { const RESET_VALUE : u32 = 0xffff ; } } } # [doc = "Backup registers"]
pub struct BKP { _marker : PhantomData < * const () > } unsafe impl Send for BKP { } impl BKP { # [doc = r"Pointer to the register block"]
pub const PTR : * const bkp :: RegisterBlock = 0x4000_6c00 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const bkp :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for BKP { type Target = bkp :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for BKP { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("BKP") . finish () } } # [doc = "Backup registers"]
pub mod bkp { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x04]
, datar1 : DATAR1 , datar2 : DATAR2 , datar3 : DATAR3 , datar4 : DATAR4 , datar5 : DATAR5 , datar6 : DATAR6 , datar7 : DATAR7 , datar8 : DATAR8 , datar9 : DATAR9 , datar10 : DATAR10 , octlr : OCTLR , tpctlr : TPCTLR , tpcsr : TPCSR , } impl RegisterBlock { # [doc = "0x04 - Backup data register (BKP_DR)"]
# [inline (always)]
pub const fn datar1 (& self) -> & DATAR1 { & self . datar1 } # [doc = "0x08 - Backup data register (BKP_DR)"]
# [inline (always)]
pub const fn datar2 (& self) -> & DATAR2 { & self . datar2 } # [doc = "0x0c - Backup data register (BKP_DR)"]
# [inline (always)]
pub const fn datar3 (& self) -> & DATAR3 { & self . datar3 } # [doc = "0x10 - Backup data register (BKP_DR)"]
# [inline (always)]
pub const fn datar4 (& self) -> & DATAR4 { & self . datar4 } # [doc = "0x14 - Backup data register (BKP_DR)"]
# [inline (always)]
pub const fn datar5 (& self) -> & DATAR5 { & self . datar5 } # [doc = "0x18 - Backup data register (BKP_DR)"]
# [inline (always)]
pub const fn datar6 (& self) -> & DATAR6 { & self . datar6 } # [doc = "0x1c - Backup data register (BKP_DR)"]
# [inline (always)]
pub const fn datar7 (& self) -> & DATAR7 { & self . datar7 } # [doc = "0x20 - Backup data register (BKP_DR)"]
# [inline (always)]
pub const fn datar8 (& self) -> & DATAR8 { & self . datar8 } # [doc = "0x24 - Backup data register (BKP_DR)"]
# [inline (always)]
pub const fn datar9 (& self) -> & DATAR9 { & self . datar9 } # [doc = "0x28 - Backup data register (BKP_DR)"]
# [inline (always)]
pub const fn datar10 (& self) -> & DATAR10 { & self . datar10 } # [doc = "0x2c - RTC clock calibration register (BKP_OCTLR)"]
# [inline (always)]
pub const fn octlr (& self) -> & OCTLR { & self . octlr } # [doc = "0x30 - Backup control register (BKP_TPCTLR)"]
# [inline (always)]
pub const fn tpctlr (& self) -> & TPCTLR { & self . tpctlr } # [doc = "0x34 - BKP_TPCSR control/status register (BKP_CSR)"]
# [inline (always)]
pub const fn tpcsr (& self) -> & TPCSR { & self . tpcsr } } # [doc = "DATAR1 (rw) register accessor: Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar1`]
module"]
pub type DATAR1 = crate :: Reg < datar1 :: DATAR1_SPEC > ; # [doc = "Backup data register (BKP_DR)"]
pub mod datar1 { # [doc = "Register `DATAR1` reader"]
pub type R = crate :: R < DATAR1_SPEC > ; # [doc = "Register `DATAR1` writer"]
pub type W = crate :: W < DATAR1_SPEC > ; # [doc = "Field `D1` reader - Backup data"]
pub type D1_R = crate :: FieldReader < u16 > ; # [doc = "Field `D1` writer - Backup data"]
pub type D1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
pub fn d1 (& self) -> D1_R { D1_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
# [must_use]
pub fn d1 (& mut self) -> D1_W < DATAR1_SPEC > { D1_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR1_SPEC ; impl crate :: RegisterSpec for DATAR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar1::R`](R) reader structure"]
impl crate :: Readable for DATAR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar1::W`](W) writer structure"]
impl crate :: Writable for DATAR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR1 to value 0"]
impl crate :: Resettable for DATAR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DATAR2 (rw) register accessor: Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar2`]
module"]
pub type DATAR2 = crate :: Reg < datar2 :: DATAR2_SPEC > ; # [doc = "Backup data register (BKP_DR)"]
pub mod datar2 { # [doc = "Register `DATAR2` reader"]
pub type R = crate :: R < DATAR2_SPEC > ; # [doc = "Register `DATAR2` writer"]
pub type W = crate :: W < DATAR2_SPEC > ; # [doc = "Field `D2` reader - Backup data"]
pub type D2_R = crate :: FieldReader < u16 > ; # [doc = "Field `D2` writer - Backup data"]
pub type D2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
pub fn d2 (& self) -> D2_R { D2_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
# [must_use]
pub fn d2 (& mut self) -> D2_W < DATAR2_SPEC > { D2_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR2_SPEC ; impl crate :: RegisterSpec for DATAR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar2::R`](R) reader structure"]
impl crate :: Readable for DATAR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar2::W`](W) writer structure"]
impl crate :: Writable for DATAR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR2 to value 0"]
impl crate :: Resettable for DATAR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DATAR3 (rw) register accessor: Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar3`]
module"]
pub type DATAR3 = crate :: Reg < datar3 :: DATAR3_SPEC > ; # [doc = "Backup data register (BKP_DR)"]
pub mod datar3 { # [doc = "Register `DATAR3` reader"]
pub type R = crate :: R < DATAR3_SPEC > ; # [doc = "Register `DATAR3` writer"]
pub type W = crate :: W < DATAR3_SPEC > ; # [doc = "Field `D3` reader - Backup data"]
pub type D3_R = crate :: FieldReader < u16 > ; # [doc = "Field `D3` writer - Backup data"]
pub type D3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
pub fn d3 (& self) -> D3_R { D3_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
# [must_use]
pub fn d3 (& mut self) -> D3_W < DATAR3_SPEC > { D3_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR3_SPEC ; impl crate :: RegisterSpec for DATAR3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar3::R`](R) reader structure"]
impl crate :: Readable for DATAR3_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar3::W`](W) writer structure"]
impl crate :: Writable for DATAR3_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR3 to value 0"]
impl crate :: Resettable for DATAR3_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DATAR4 (rw) register accessor: Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar4::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar4`]
module"]
pub type DATAR4 = crate :: Reg < datar4 :: DATAR4_SPEC > ; # [doc = "Backup data register (BKP_DR)"]
pub mod datar4 { # [doc = "Register `DATAR4` reader"]
pub type R = crate :: R < DATAR4_SPEC > ; # [doc = "Register `DATAR4` writer"]
pub type W = crate :: W < DATAR4_SPEC > ; # [doc = "Field `D4` reader - Backup data"]
pub type D4_R = crate :: FieldReader < u16 > ; # [doc = "Field `D4` writer - Backup data"]
pub type D4_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
pub fn d4 (& self) -> D4_R { D4_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
# [must_use]
pub fn d4 (& mut self) -> D4_W < DATAR4_SPEC > { D4_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar4::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR4_SPEC ; impl crate :: RegisterSpec for DATAR4_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar4::R`](R) reader structure"]
impl crate :: Readable for DATAR4_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar4::W`](W) writer structure"]
impl crate :: Writable for DATAR4_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR4 to value 0"]
impl crate :: Resettable for DATAR4_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DATAR5 (rw) register accessor: Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar5::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar5`]
module"]
pub type DATAR5 = crate :: Reg < datar5 :: DATAR5_SPEC > ; # [doc = "Backup data register (BKP_DR)"]
pub mod datar5 { # [doc = "Register `DATAR5` reader"]
pub type R = crate :: R < DATAR5_SPEC > ; # [doc = "Register `DATAR5` writer"]
pub type W = crate :: W < DATAR5_SPEC > ; # [doc = "Field `D5` reader - Backup data"]
pub type D5_R = crate :: FieldReader < u16 > ; # [doc = "Field `D5` writer - Backup data"]
pub type D5_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
pub fn d5 (& self) -> D5_R { D5_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
# [must_use]
pub fn d5 (& mut self) -> D5_W < DATAR5_SPEC > { D5_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar5::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR5_SPEC ; impl crate :: RegisterSpec for DATAR5_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar5::R`](R) reader structure"]
impl crate :: Readable for DATAR5_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar5::W`](W) writer structure"]
impl crate :: Writable for DATAR5_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR5 to value 0"]
impl crate :: Resettable for DATAR5_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DATAR6 (rw) register accessor: Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar6::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar6`]
module"]
pub type DATAR6 = crate :: Reg < datar6 :: DATAR6_SPEC > ; # [doc = "Backup data register (BKP_DR)"]
pub mod datar6 { # [doc = "Register `DATAR6` reader"]
pub type R = crate :: R < DATAR6_SPEC > ; # [doc = "Register `DATAR6` writer"]
pub type W = crate :: W < DATAR6_SPEC > ; # [doc = "Field `D6` reader - Backup data"]
pub type D6_R = crate :: FieldReader < u16 > ; # [doc = "Field `D6` writer - Backup data"]
pub type D6_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
pub fn d6 (& self) -> D6_R { D6_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
# [must_use]
pub fn d6 (& mut self) -> D6_W < DATAR6_SPEC > { D6_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar6::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR6_SPEC ; impl crate :: RegisterSpec for DATAR6_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar6::R`](R) reader structure"]
impl crate :: Readable for DATAR6_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar6::W`](W) writer structure"]
impl crate :: Writable for DATAR6_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR6 to value 0"]
impl crate :: Resettable for DATAR6_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DATAR7 (rw) register accessor: Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar7::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar7`]
module"]
pub type DATAR7 = crate :: Reg < datar7 :: DATAR7_SPEC > ; # [doc = "Backup data register (BKP_DR)"]
pub mod datar7 { # [doc = "Register `DATAR7` reader"]
pub type R = crate :: R < DATAR7_SPEC > ; # [doc = "Register `DATAR7` writer"]
pub type W = crate :: W < DATAR7_SPEC > ; # [doc = "Field `D7` reader - Backup data"]
pub type D7_R = crate :: FieldReader < u16 > ; # [doc = "Field `D7` writer - Backup data"]
pub type D7_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
pub fn d7 (& self) -> D7_R { D7_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
# [must_use]
pub fn d7 (& mut self) -> D7_W < DATAR7_SPEC > { D7_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar7::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR7_SPEC ; impl crate :: RegisterSpec for DATAR7_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar7::R`](R) reader structure"]
impl crate :: Readable for DATAR7_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar7::W`](W) writer structure"]
impl crate :: Writable for DATAR7_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR7 to value 0"]
impl crate :: Resettable for DATAR7_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DATAR8 (rw) register accessor: Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar8::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar8`]
module"]
pub type DATAR8 = crate :: Reg < datar8 :: DATAR8_SPEC > ; # [doc = "Backup data register (BKP_DR)"]
pub mod datar8 { # [doc = "Register `DATAR8` reader"]
pub type R = crate :: R < DATAR8_SPEC > ; # [doc = "Register `DATAR8` writer"]
pub type W = crate :: W < DATAR8_SPEC > ; # [doc = "Field `D8` reader - Backup data"]
pub type D8_R = crate :: FieldReader < u16 > ; # [doc = "Field `D8` writer - Backup data"]
pub type D8_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
pub fn d8 (& self) -> D8_R { D8_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
# [must_use]
pub fn d8 (& mut self) -> D8_W < DATAR8_SPEC > { D8_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar8::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR8_SPEC ; impl crate :: RegisterSpec for DATAR8_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar8::R`](R) reader structure"]
impl crate :: Readable for DATAR8_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar8::W`](W) writer structure"]
impl crate :: Writable for DATAR8_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR8 to value 0"]
impl crate :: Resettable for DATAR8_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DATAR9 (rw) register accessor: Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar9::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar9`]
module"]
pub type DATAR9 = crate :: Reg < datar9 :: DATAR9_SPEC > ; # [doc = "Backup data register (BKP_DR)"]
pub mod datar9 { # [doc = "Register `DATAR9` reader"]
pub type R = crate :: R < DATAR9_SPEC > ; # [doc = "Register `DATAR9` writer"]
pub type W = crate :: W < DATAR9_SPEC > ; # [doc = "Field `D9` reader - Backup data"]
pub type D9_R = crate :: FieldReader < u16 > ; # [doc = "Field `D9` writer - Backup data"]
pub type D9_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
pub fn d9 (& self) -> D9_R { D9_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
# [must_use]
pub fn d9 (& mut self) -> D9_W < DATAR9_SPEC > { D9_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar9::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR9_SPEC ; impl crate :: RegisterSpec for DATAR9_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar9::R`](R) reader structure"]
impl crate :: Readable for DATAR9_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar9::W`](W) writer structure"]
impl crate :: Writable for DATAR9_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR9 to value 0"]
impl crate :: Resettable for DATAR9_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DATAR10 (rw) register accessor: Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar10::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar10`]
module"]
pub type DATAR10 = crate :: Reg < datar10 :: DATAR10_SPEC > ; # [doc = "Backup data register (BKP_DR)"]
pub mod datar10 { # [doc = "Register `DATAR10` reader"]
pub type R = crate :: R < DATAR10_SPEC > ; # [doc = "Register `DATAR10` writer"]
pub type W = crate :: W < DATAR10_SPEC > ; # [doc = "Field `D10` reader - Backup data"]
pub type D10_R = crate :: FieldReader < u16 > ; # [doc = "Field `D10` writer - Backup data"]
pub type D10_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
pub fn d10 (& self) -> D10_R { D10_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Backup data"]
# [inline (always)]
# [must_use]
pub fn d10 (& mut self) -> D10_W < DATAR10_SPEC > { D10_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Backup data register (BKP_DR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar10::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR10_SPEC ; impl crate :: RegisterSpec for DATAR10_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar10::R`](R) reader structure"]
impl crate :: Readable for DATAR10_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar10::W`](W) writer structure"]
impl crate :: Writable for DATAR10_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR10 to value 0"]
impl crate :: Resettable for DATAR10_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "OCTLR (rw) register accessor: RTC clock calibration register (BKP_OCTLR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`octlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`octlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@octlr`]
module"]
pub type OCTLR = crate :: Reg < octlr :: OCTLR_SPEC > ; # [doc = "RTC clock calibration register (BKP_OCTLR)"]
pub mod octlr { # [doc = "Register `OCTLR` reader"]
pub type R = crate :: R < OCTLR_SPEC > ; # [doc = "Register `OCTLR` writer"]
pub type W = crate :: W < OCTLR_SPEC > ; # [doc = "Field `CAL` reader - Calibration value"]
pub type CAL_R = crate :: FieldReader ; # [doc = "Field `CAL` writer - Calibration value"]
pub type CAL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `CCO` reader - Calibration Clock Output"]
pub type CCO_R = crate :: BitReader ; # [doc = "Field `CCO` writer - Calibration Clock Output"]
pub type CCO_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ASOE` reader - Alarm or second output enable"]
pub type ASOE_R = crate :: BitReader ; # [doc = "Field `ASOE` writer - Alarm or second output enable"]
pub type ASOE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ASOS` reader - Alarm or second output selection"]
pub type ASOS_R = crate :: BitReader ; # [doc = "Field `ASOS` writer - Alarm or second output selection"]
pub type ASOS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:6 - Calibration value"]
# [inline (always)]
pub fn cal (& self) -> CAL_R { CAL_R :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - Calibration Clock Output"]
# [inline (always)]
pub fn cco (& self) -> CCO_R { CCO_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Alarm or second output enable"]
# [inline (always)]
pub fn asoe (& self) -> ASOE_R { ASOE_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Alarm or second output selection"]
# [inline (always)]
pub fn asos (& self) -> ASOS_R { ASOS_R :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:6 - Calibration value"]
# [inline (always)]
# [must_use]
pub fn cal (& mut self) -> CAL_W < OCTLR_SPEC > { CAL_W :: new (self , 0) } # [doc = "Bit 7 - Calibration Clock Output"]
# [inline (always)]
# [must_use]
pub fn cco (& mut self) -> CCO_W < OCTLR_SPEC > { CCO_W :: new (self , 7) } # [doc = "Bit 8 - Alarm or second output enable"]
# [inline (always)]
# [must_use]
pub fn asoe (& mut self) -> ASOE_W < OCTLR_SPEC > { ASOE_W :: new (self , 8) } # [doc = "Bit 9 - Alarm or second output selection"]
# [inline (always)]
# [must_use]
pub fn asos (& mut self) -> ASOS_W < OCTLR_SPEC > { ASOS_W :: new (self , 9) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "RTC clock calibration register (BKP_OCTLR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`octlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`octlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OCTLR_SPEC ; impl crate :: RegisterSpec for OCTLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`octlr::R`](R) reader structure"]
impl crate :: Readable for OCTLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`octlr::W`](W) writer structure"]
impl crate :: Writable for OCTLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets OCTLR to value 0"]
impl crate :: Resettable for OCTLR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "TPCTLR (rw) register accessor: Backup control register (BKP_TPCTLR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpctlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpctlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tpctlr`]
module"]
pub type TPCTLR = crate :: Reg < tpctlr :: TPCTLR_SPEC > ; # [doc = "Backup control register (BKP_TPCTLR)"]
pub mod tpctlr { # [doc = "Register `TPCTLR` reader"]
pub type R = crate :: R < TPCTLR_SPEC > ; # [doc = "Register `TPCTLR` writer"]
pub type W = crate :: W < TPCTLR_SPEC > ; # [doc = "Field `TPE` reader - Tamper pin enable"]
pub type TPE_R = crate :: BitReader ; # [doc = "Field `TPE` writer - Tamper pin enable"]
pub type TPE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TPAL` reader - Tamper pin active level"]
pub type TPAL_R = crate :: BitReader ; # [doc = "Field `TPAL` writer - Tamper pin active level"]
pub type TPAL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Tamper pin enable"]
# [inline (always)]
pub fn tpe (& self) -> TPE_R { TPE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Tamper pin active level"]
# [inline (always)]
pub fn tpal (& self) -> TPAL_R { TPAL_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Tamper pin enable"]
# [inline (always)]
# [must_use]
pub fn tpe (& mut self) -> TPE_W < TPCTLR_SPEC > { TPE_W :: new (self , 0) } # [doc = "Bit 1 - Tamper pin active level"]
# [inline (always)]
# [must_use]
pub fn tpal (& mut self) -> TPAL_W < TPCTLR_SPEC > { TPAL_W :: new (self , 1) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Backup control register (BKP_TPCTLR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpctlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpctlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TPCTLR_SPEC ; impl crate :: RegisterSpec for TPCTLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`tpctlr::R`](R) reader structure"]
impl crate :: Readable for TPCTLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`tpctlr::W`](W) writer structure"]
impl crate :: Writable for TPCTLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TPCTLR to value 0"]
impl crate :: Resettable for TPCTLR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "TPCSR (rw) register accessor: BKP_TPCSR control/status register (BKP_CSR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpcsr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpcsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tpcsr`]
module"]
pub type TPCSR = crate :: Reg < tpcsr :: TPCSR_SPEC > ; # [doc = "BKP_TPCSR control/status register (BKP_CSR)"]
pub mod tpcsr { # [doc = "Register `TPCSR` reader"]
pub type R = crate :: R < TPCSR_SPEC > ; # [doc = "Register `TPCSR` writer"]
pub type W = crate :: W < TPCSR_SPEC > ; # [doc = "Field `CTE` writer - Clear Tamper event"]
pub type CTE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTI` writer - Clear Tamper Interrupt"]
pub type CTI_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TPIE` reader - Tamper Pin interrupt enable"]
pub type TPIE_R = crate :: BitReader ; # [doc = "Field `TPIE` writer - Tamper Pin interrupt enable"]
pub type TPIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEF` reader - Tamper Event Flag"]
pub type TEF_R = crate :: BitReader ; # [doc = "Field `TIF` reader - Tamper Interrupt Flag"]
pub type TIF_R = crate :: BitReader ; impl R { # [doc = "Bit 2 - Tamper Pin interrupt enable"]
# [inline (always)]
pub fn tpie (& self) -> TPIE_R { TPIE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 8 - Tamper Event Flag"]
# [inline (always)]
pub fn tef (& self) -> TEF_R { TEF_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Tamper Interrupt Flag"]
# [inline (always)]
pub fn tif (& self) -> TIF_R { TIF_R :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bit 0 - Clear Tamper event"]
# [inline (always)]
# [must_use]
pub fn cte (& mut self) -> CTE_W < TPCSR_SPEC > { CTE_W :: new (self , 0) } # [doc = "Bit 1 - Clear Tamper Interrupt"]
# [inline (always)]
# [must_use]
pub fn cti (& mut self) -> CTI_W < TPCSR_SPEC > { CTI_W :: new (self , 1) } # [doc = "Bit 2 - Tamper Pin interrupt enable"]
# [inline (always)]
# [must_use]
pub fn tpie (& mut self) -> TPIE_W < TPCSR_SPEC > { TPIE_W :: new (self , 2) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "BKP_TPCSR control/status register (BKP_CSR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpcsr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpcsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TPCSR_SPEC ; impl crate :: RegisterSpec for TPCSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`tpcsr::R`](R) reader structure"]
impl crate :: Readable for TPCSR_SPEC { } # [doc = "`write(|w| ..)` method takes [`tpcsr::W`](W) writer structure"]
impl crate :: Writable for TPCSR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets TPCSR to value 0"]
impl crate :: Resettable for TPCSR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Independent watchdog"]
pub struct IWDG { _marker : PhantomData < * const () > } unsafe impl Send for IWDG { } impl IWDG { # [doc = r"Pointer to the register block"]
pub const PTR : * const iwdg :: RegisterBlock = 0x4000_3000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const iwdg :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for IWDG { type Target = iwdg :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for IWDG { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("IWDG") . finish () } } # [doc = "Independent watchdog"]
pub mod iwdg { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { ctlr : CTLR , pscr : PSCR , rldr : RLDR , statr : STATR , } impl RegisterBlock { # [doc = "0x00 - Key register (IWDG_CTLR)"]
# [inline (always)]
pub const fn ctlr (& self) -> & CTLR { & self . ctlr } # [doc = "0x04 - Prescaler register (IWDG_PSCR)"]
# [inline (always)]
pub const fn pscr (& self) -> & PSCR { & self . pscr } # [doc = "0x08 - Reload register (IWDG_RLDR)"]
# [inline (always)]
pub const fn rldr (& self) -> & RLDR { & self . rldr } # [doc = "0x0c - Status register (IWDG_SR)"]
# [inline (always)]
pub const fn statr (& self) -> & STATR { & self . statr } } # [doc = "CTLR (w) register accessor: Key register (IWDG_CTLR)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr`]
module"]
pub type CTLR = crate :: Reg < ctlr :: CTLR_SPEC > ; # [doc = "Key register (IWDG_CTLR)"]
pub mod ctlr { # [doc = "Register `CTLR` writer"]
pub type W = crate :: W < CTLR_SPEC > ; # [doc = "Field `KEY` writer - Key value"]
pub type KEY_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl W { # [doc = "Bits 0:15 - Key value"]
# [inline (always)]
# [must_use]
pub fn key (& mut self) -> KEY_W < CTLR_SPEC > { KEY_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Key register (IWDG_CTLR)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR_SPEC ; impl crate :: RegisterSpec for CTLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`ctlr::W`](W) writer structure"]
impl crate :: Writable for CTLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR to value 0"]
impl crate :: Resettable for CTLR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSCR (rw) register accessor: Prescaler register (IWDG_PSCR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pscr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pscr`]
module"]
pub type PSCR = crate :: Reg < pscr :: PSCR_SPEC > ; # [doc = "Prescaler register (IWDG_PSCR)"]
pub mod pscr { # [doc = "Register `PSCR` reader"]
pub type R = crate :: R < PSCR_SPEC > ; # [doc = "Register `PSCR` writer"]
pub type W = crate :: W < PSCR_SPEC > ; # [doc = "Field `PR` reader - Prescaler divider"]
pub type PR_R = crate :: FieldReader ; # [doc = "Field `PR` writer - Prescaler divider"]
pub type PR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - Prescaler divider"]
# [inline (always)]
pub fn pr (& self) -> PR_R { PR_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Prescaler divider"]
# [inline (always)]
# [must_use]
pub fn pr (& mut self) -> PR_W < PSCR_SPEC > { PR_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Prescaler register (IWDG_PSCR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pscr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PSCR_SPEC ; impl crate :: RegisterSpec for PSCR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pscr::R`](R) reader structure"]
impl crate :: Readable for PSCR_SPEC { } # [doc = "`write(|w| ..)` method takes [`pscr::W`](W) writer structure"]
impl crate :: Writable for PSCR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSCR to value 0"]
impl crate :: Resettable for PSCR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "RLDR (rw) register accessor: Reload register (IWDG_RLDR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rldr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rldr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rldr`]
module"]
pub type RLDR = crate :: Reg < rldr :: RLDR_SPEC > ; # [doc = "Reload register (IWDG_RLDR)"]
pub mod rldr { # [doc = "Register `RLDR` reader"]
pub type R = crate :: R < RLDR_SPEC > ; # [doc = "Register `RLDR` writer"]
pub type W = crate :: W < RLDR_SPEC > ; # [doc = "Field `RL` reader - Watchdog counter reload value"]
pub type RL_R = crate :: FieldReader < u16 > ; # [doc = "Field `RL` writer - Watchdog counter reload value"]
pub type RL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:11 - Watchdog counter reload value"]
# [inline (always)]
pub fn rl (& self) -> RL_R { RL_R :: new ((self . bits & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:11 - Watchdog counter reload value"]
# [inline (always)]
# [must_use]
pub fn rl (& mut self) -> RL_W < RLDR_SPEC > { RL_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reload register (IWDG_RLDR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rldr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rldr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RLDR_SPEC ; impl crate :: RegisterSpec for RLDR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rldr::R`](R) reader structure"]
impl crate :: Readable for RLDR_SPEC { } # [doc = "`write(|w| ..)` method takes [`rldr::W`](W) writer structure"]
impl crate :: Writable for RLDR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RLDR to value 0x0fff"]
impl crate :: Resettable for RLDR_SPEC { const RESET_VALUE : u32 = 0x0fff ; } } # [doc = "STATR (r) register accessor: Status register (IWDG_SR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@statr`]
module"]
pub type STATR = crate :: Reg < statr :: STATR_SPEC > ; # [doc = "Status register (IWDG_SR)"]
pub mod statr { # [doc = "Register `STATR` reader"]
pub type R = crate :: R < STATR_SPEC > ; # [doc = "Field `PVU` reader - Watchdog prescaler value update"]
pub type PVU_R = crate :: BitReader ; # [doc = "Field `RVU` reader - Watchdog counter reload value update"]
pub type RVU_R = crate :: BitReader ; impl R { # [doc = "Bit 0 - Watchdog prescaler value update"]
# [inline (always)]
pub fn pvu (& self) -> PVU_R { PVU_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Watchdog counter reload value update"]
# [inline (always)]
pub fn rvu (& self) -> RVU_R { RVU_R :: new (((self . bits >> 1) & 1) != 0) } } # [doc = "Status register (IWDG_SR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STATR_SPEC ; impl crate :: RegisterSpec for STATR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`statr::R`](R) reader structure"]
impl crate :: Readable for STATR_SPEC { } # [doc = "`reset()` method sets STATR to value 0"]
impl crate :: Resettable for STATR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Window watchdog"]
pub struct WWDG { _marker : PhantomData < * const () > } unsafe impl Send for WWDG { } impl WWDG { # [doc = r"Pointer to the register block"]
pub const PTR : * const wwdg :: RegisterBlock = 0x4000_2c00 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const wwdg :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for WWDG { type Target = wwdg :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for WWDG { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("WWDG") . finish () } } # [doc = "Window watchdog"]
pub mod wwdg { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { ctlr : CTLR , cfgr : CFGR , statr : STATR , } impl RegisterBlock { # [doc = "0x00 - Control register (WWDG_CR)"]
# [inline (always)]
pub const fn ctlr (& self) -> & CTLR { & self . ctlr } # [doc = "0x04 - Configuration register (WWDG_CFR)"]
# [inline (always)]
pub const fn cfgr (& self) -> & CFGR { & self . cfgr } # [doc = "0x08 - Status register (WWDG_SR)"]
# [inline (always)]
pub const fn statr (& self) -> & STATR { & self . statr } } # [doc = "CTLR (rw) register accessor: Control register (WWDG_CR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr`]
module"]
pub type CTLR = crate :: Reg < ctlr :: CTLR_SPEC > ; # [doc = "Control register (WWDG_CR)"]
pub mod ctlr { # [doc = "Register `CTLR` reader"]
pub type R = crate :: R < CTLR_SPEC > ; # [doc = "Register `CTLR` writer"]
pub type W = crate :: W < CTLR_SPEC > ; # [doc = "Field `T` reader - 7-bit counter (MSB to LSB)"]
pub type T_R = crate :: FieldReader ; # [doc = "Field `T` writer - 7-bit counter (MSB to LSB)"]
pub type T_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `WDGA` reader - Activation bit"]
pub type WDGA_R = crate :: BitReader ; # [doc = "Field `WDGA` writer - Activation bit"]
pub type WDGA_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:6 - 7-bit counter (MSB to LSB)"]
# [inline (always)]
pub fn t (& self) -> T_R { T_R :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - Activation bit"]
# [inline (always)]
pub fn wdga (& self) -> WDGA_R { WDGA_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:6 - 7-bit counter (MSB to LSB)"]
# [inline (always)]
# [must_use]
pub fn t (& mut self) -> T_W < CTLR_SPEC > { T_W :: new (self , 0) } # [doc = "Bit 7 - Activation bit"]
# [inline (always)]
# [must_use]
pub fn wdga (& mut self) -> WDGA_W < CTLR_SPEC > { WDGA_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control register (WWDG_CR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR_SPEC ; impl crate :: RegisterSpec for CTLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr::R`](R) reader structure"]
impl crate :: Readable for CTLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr::W`](W) writer structure"]
impl crate :: Writable for CTLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR to value 0x7f"]
impl crate :: Resettable for CTLR_SPEC { const RESET_VALUE : u32 = 0x7f ; } } # [doc = "CFGR (rw) register accessor: Configuration register (WWDG_CFR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr`]
module"]
pub type CFGR = crate :: Reg < cfgr :: CFGR_SPEC > ; # [doc = "Configuration register (WWDG_CFR)"]
pub mod cfgr { # [doc = "Register `CFGR` reader"]
pub type R = crate :: R < CFGR_SPEC > ; # [doc = "Register `CFGR` writer"]
pub type W = crate :: W < CFGR_SPEC > ; # [doc = "Field `W` reader - 7-bit window value"]
pub type W_R = crate :: FieldReader ; # [doc = "Field `W` writer - 7-bit window value"]
pub type W_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `WDGTB` reader - Timer Base"]
pub type WDGTB_R = crate :: FieldReader ; # [doc = "Field `WDGTB` writer - Timer Base"]
pub type WDGTB_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `EWI` reader - Early Wakeup Interrupt"]
pub type EWI_R = crate :: BitReader ; # [doc = "Field `EWI` writer - Early Wakeup Interrupt"]
pub type EWI_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:6 - 7-bit window value"]
# [inline (always)]
pub fn w (& self) -> W_R { W_R :: new ((self . bits & 0x7f) as u8) } # [doc = "Bits 7:8 - Timer Base"]
# [inline (always)]
pub fn wdgtb (& self) -> WDGTB_R { WDGTB_R :: new (((self . bits >> 7) & 3) as u8) } # [doc = "Bit 9 - Early Wakeup Interrupt"]
# [inline (always)]
pub fn ewi (& self) -> EWI_R { EWI_R :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:6 - 7-bit window value"]
# [inline (always)]
# [must_use]
pub fn w (& mut self) -> W_W < CFGR_SPEC > { W_W :: new (self , 0) } # [doc = "Bits 7:8 - Timer Base"]
# [inline (always)]
# [must_use]
pub fn wdgtb (& mut self) -> WDGTB_W < CFGR_SPEC > { WDGTB_W :: new (self , 7) } # [doc = "Bit 9 - Early Wakeup Interrupt"]
# [inline (always)]
# [must_use]
pub fn ewi (& mut self) -> EWI_W < CFGR_SPEC > { EWI_W :: new (self , 9) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration register (WWDG_CFR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGR_SPEC ; impl crate :: RegisterSpec for CFGR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr::R`](R) reader structure"]
impl crate :: Readable for CFGR_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"]
impl crate :: Writable for CFGR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFGR to value 0x7f"]
impl crate :: Resettable for CFGR_SPEC { const RESET_VALUE : u32 = 0x7f ; } } # [doc = "STATR (rw) register accessor: Status register (WWDG_SR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`statr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@statr`]
module"]
pub type STATR = crate :: Reg < statr :: STATR_SPEC > ; # [doc = "Status register (WWDG_SR)"]
pub mod statr { # [doc = "Register `STATR` reader"]
pub type R = crate :: R < STATR_SPEC > ; # [doc = "Register `STATR` writer"]
pub type W = crate :: W < STATR_SPEC > ; # [doc = "Field `WEIF` reader - Early Wakeup Interrupt Flag"]
pub type WEIF_R = crate :: BitReader ; # [doc = "Field `WEIF` writer - Early Wakeup Interrupt Flag"]
pub type WEIF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Early Wakeup Interrupt Flag"]
# [inline (always)]
pub fn weif (& self) -> WEIF_R { WEIF_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Early Wakeup Interrupt Flag"]
# [inline (always)]
# [must_use]
pub fn weif (& mut self) -> WEIF_W < STATR_SPEC > { WEIF_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Status register (WWDG_SR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`statr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STATR_SPEC ; impl crate :: RegisterSpec for STATR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`statr::R`](R) reader structure"]
impl crate :: Readable for STATR_SPEC { } # [doc = "`write(|w| ..)` method takes [`statr::W`](W) writer structure"]
impl crate :: Writable for STATR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets STATR to value 0"]
impl crate :: Resettable for STATR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Advanced timer"]
pub struct TIM1 { _marker : PhantomData < * const () > } unsafe impl Send for TIM1 { } impl TIM1 { # [doc = r"Pointer to the register block"]
pub const PTR : * const tim1 :: RegisterBlock = 0x4001_2c00 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const tim1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TIM1 { type Target = tim1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TIM1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TIM1") . finish () } } # [doc = "Advanced timer"]
pub mod tim1 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { ctlr1 : CTLR1 , ctlr2 : CTLR2 , smcfgr : SMCFGR , dmaintenr : DMAINTENR , intfr : INTFR , swevgr : SWEVGR , _reserved_6_chctlr1 : [u8 ; 0x04]
, _reserved_7_chctlr2 : [u8 ; 0x04]
, ccer : CCER , cnt : CNT , psc : PSC , atrlr : ATRLR , rptcr : RPTCR , ch1cvr : CH1CVR , ch2cvr : CH2CVR , ch3cvr : CH3CVR , ch4cvr : CH4CVR , bdtr : BDTR , dmacfgr : DMACFGR , dmar : DMAR , } impl RegisterBlock { # [doc = "0x00 - control register 1"]
# [inline (always)]
pub const fn ctlr1 (& self) -> & CTLR1 { & self . ctlr1 } # [doc = "0x04 - control register 2"]
# [inline (always)]
pub const fn ctlr2 (& self) -> & CTLR2 { & self . ctlr2 } # [doc = "0x08 - slave mode control register"]
# [inline (always)]
pub const fn smcfgr (& self) -> & SMCFGR { & self . smcfgr } # [doc = "0x0c - DMA/Interrupt enable register"]
# [inline (always)]
pub const fn dmaintenr (& self) -> & DMAINTENR { & self . dmaintenr } # [doc = "0x10 - status register"]
# [inline (always)]
pub const fn intfr (& self) -> & INTFR { & self . intfr } # [doc = "0x14 - event generation register"]
# [inline (always)]
pub const fn swevgr (& self) -> & SWEVGR { & self . swevgr } # [doc = "0x18 - capture/compare mode register 1 (input mode)"]
# [inline (always)]
pub const fn chctlr1_input (& self) -> & CHCTLR1_INPUT { unsafe { & * (self as * const Self) . cast :: < u8 > () . add (24) . cast () } } # [doc = "0x18 - capture/compare mode register (output mode)"]
# [inline (always)]
pub const fn chctlr1_output (& self) -> & CHCTLR1_OUTPUT { unsafe { & * (self as * const Self) . cast :: < u8 > () . add (24) . cast () } } # [doc = "0x1c - capture/compare mode register 2 (input mode)"]
# [inline (always)]
pub const fn chctlr2_input (& self) -> & CHCTLR2_INPUT { unsafe { & * (self as * const Self) . cast :: < u8 > () . add (28) . cast () } } # [doc = "0x1c - capture/compare mode register (output mode)"]
# [inline (always)]
pub const fn chctlr2_output (& self) -> & CHCTLR2_OUTPUT { unsafe { & * (self as * const Self) . cast :: < u8 > () . add (28) . cast () } } # [doc = "0x20 - capture/compare enable register"]
# [inline (always)]
pub const fn ccer (& self) -> & CCER { & self . ccer } # [doc = "0x24 - counter"]
# [inline (always)]
pub const fn cnt (& self) -> & CNT { & self . cnt } # [doc = "0x28 - prescaler"]
# [inline (always)]
pub const fn psc (& self) -> & PSC { & self . psc } # [doc = "0x2c - auto-reload register"]
# [inline (always)]
pub const fn atrlr (& self) -> & ATRLR { & self . atrlr } # [doc = "0x30 - repetition counter register"]
# [inline (always)]
pub const fn rptcr (& self) -> & RPTCR { & self . rptcr } # [doc = "0x34 - capture/compare register 1"]
# [inline (always)]
pub const fn ch1cvr (& self) -> & CH1CVR { & self . ch1cvr } # [doc = "0x38 - capture/compare register 2"]
# [inline (always)]
pub const fn ch2cvr (& self) -> & CH2CVR { & self . ch2cvr } # [doc = "0x3c - capture/compare register 3"]
# [inline (always)]
pub const fn ch3cvr (& self) -> & CH3CVR { & self . ch3cvr } # [doc = "0x40 - capture/compare register 4"]
# [inline (always)]
pub const fn ch4cvr (& self) -> & CH4CVR { & self . ch4cvr } # [doc = "0x44 - break and dead-time register"]
# [inline (always)]
pub const fn bdtr (& self) -> & BDTR { & self . bdtr } # [doc = "0x48 - DMA control register"]
# [inline (always)]
pub const fn dmacfgr (& self) -> & DMACFGR { & self . dmacfgr } # [doc = "0x4c - DMA address for full transfer"]
# [inline (always)]
pub const fn dmar (& self) -> & DMAR { & self . dmar } } # [doc = "CTLR1 (rw) register accessor: control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr1`]
module"]
pub type CTLR1 = crate :: Reg < ctlr1 :: CTLR1_SPEC > ; # [doc = "control register 1"]
pub mod ctlr1 { # [doc = "Register `CTLR1` reader"]
pub type R = crate :: R < CTLR1_SPEC > ; # [doc = "Register `CTLR1` writer"]
pub type W = crate :: W < CTLR1_SPEC > ; # [doc = "Field `CEN` reader - Counter enable"]
pub type CEN_R = crate :: BitReader ; # [doc = "Field `CEN` writer - Counter enable"]
pub type CEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `UDIS` reader - Update disable"]
pub type UDIS_R = crate :: BitReader ; # [doc = "Field `UDIS` writer - Update disable"]
pub type UDIS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `URS` reader - Update request source"]
pub type URS_R = crate :: BitReader ; # [doc = "Field `URS` writer - Update request source"]
pub type URS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OPM` reader - One-pulse mode"]
pub type OPM_R = crate :: BitReader ; # [doc = "Field `OPM` writer - One-pulse mode"]
pub type OPM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DIR` reader - Direction"]
pub type DIR_R = crate :: BitReader ; # [doc = "Field `DIR` writer - Direction"]
pub type DIR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CMS` reader - Center-aligned mode selection"]
pub type CMS_R = crate :: FieldReader ; # [doc = "Field `CMS` writer - Center-aligned mode selection"]
pub type CMS_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ARPE` reader - Auto-reload preload enable"]
pub type ARPE_R = crate :: BitReader ; # [doc = "Field `ARPE` writer - Auto-reload preload enable"]
pub type ARPE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CKD` reader - Clock division"]
pub type CKD_R = crate :: FieldReader ; # [doc = "Field `CKD` writer - Clock division"]
pub type CKD_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - Counter enable"]
# [inline (always)]
pub fn cen (& self) -> CEN_R { CEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Update disable"]
# [inline (always)]
pub fn udis (& self) -> UDIS_R { UDIS_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Update request source"]
# [inline (always)]
pub fn urs (& self) -> URS_R { URS_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - One-pulse mode"]
# [inline (always)]
pub fn opm (& self) -> OPM_R { OPM_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Direction"]
# [inline (always)]
pub fn dir (& self) -> DIR_R { DIR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:6 - Center-aligned mode selection"]
# [inline (always)]
pub fn cms (& self) -> CMS_R { CMS_R :: new (((self . bits >> 5) & 3) as u8) } # [doc = "Bit 7 - Auto-reload preload enable"]
# [inline (always)]
pub fn arpe (& self) -> ARPE_R { ARPE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Clock division"]
# [inline (always)]
pub fn ckd (& self) -> CKD_R { CKD_R :: new (((self . bits >> 8) & 3) as u8) } } impl W { # [doc = "Bit 0 - Counter enable"]
# [inline (always)]
# [must_use]
pub fn cen (& mut self) -> CEN_W < CTLR1_SPEC > { CEN_W :: new (self , 0) } # [doc = "Bit 1 - Update disable"]
# [inline (always)]
# [must_use]
pub fn udis (& mut self) -> UDIS_W < CTLR1_SPEC > { UDIS_W :: new (self , 1) } # [doc = "Bit 2 - Update request source"]
# [inline (always)]
# [must_use]
pub fn urs (& mut self) -> URS_W < CTLR1_SPEC > { URS_W :: new (self , 2) } # [doc = "Bit 3 - One-pulse mode"]
# [inline (always)]
# [must_use]
pub fn opm (& mut self) -> OPM_W < CTLR1_SPEC > { OPM_W :: new (self , 3) } # [doc = "Bit 4 - Direction"]
# [inline (always)]
# [must_use]
pub fn dir (& mut self) -> DIR_W < CTLR1_SPEC > { DIR_W :: new (self , 4) } # [doc = "Bits 5:6 - Center-aligned mode selection"]
# [inline (always)]
# [must_use]
pub fn cms (& mut self) -> CMS_W < CTLR1_SPEC > { CMS_W :: new (self , 5) } # [doc = "Bit 7 - Auto-reload preload enable"]
# [inline (always)]
# [must_use]
pub fn arpe (& mut self) -> ARPE_W < CTLR1_SPEC > { ARPE_W :: new (self , 7) } # [doc = "Bits 8:9 - Clock division"]
# [inline (always)]
# [must_use]
pub fn ckd (& mut self) -> CKD_W < CTLR1_SPEC > { CKD_W :: new (self , 8) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR1_SPEC ; impl crate :: RegisterSpec for CTLR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr1::R`](R) reader structure"]
impl crate :: Readable for CTLR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr1::W`](W) writer structure"]
impl crate :: Writable for CTLR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR1 to value 0"]
impl crate :: Resettable for CTLR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTLR2 (rw) register accessor: control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr2`]
module"]
pub type CTLR2 = crate :: Reg < ctlr2 :: CTLR2_SPEC > ; # [doc = "control register 2"]
pub mod ctlr2 { # [doc = "Register `CTLR2` reader"]
pub type R = crate :: R < CTLR2_SPEC > ; # [doc = "Register `CTLR2` writer"]
pub type W = crate :: W < CTLR2_SPEC > ; # [doc = "Field `CCPC` reader - Capture/compare preloaded control"]
pub type CCPC_R = crate :: BitReader ; # [doc = "Field `CCPC` writer - Capture/compare preloaded control"]
pub type CCPC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CCUS` reader - Capture/compare control update selection"]
pub type CCUS_R = crate :: BitReader ; # [doc = "Field `CCUS` writer - Capture/compare control update selection"]
pub type CCUS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CCDS` reader - Capture/compare DMA selection"]
pub type CCDS_R = crate :: BitReader ; # [doc = "Field `CCDS` writer - Capture/compare DMA selection"]
pub type CCDS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MMS` reader - Master mode selection"]
pub type MMS_R = crate :: FieldReader ; # [doc = "Field `MMS` writer - Master mode selection"]
pub type MMS_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TI1S` reader - TI1 selection"]
pub type TI1S_R = crate :: BitReader ; # [doc = "Field `TI1S` writer - TI1 selection"]
pub type TI1S_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OIS1` reader - Output Idle state 1"]
pub type OIS1_R = crate :: BitReader ; # [doc = "Field `OIS1` writer - Output Idle state 1"]
pub type OIS1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OIS1N` reader - Output Idle state 1"]
pub type OIS1N_R = crate :: BitReader ; # [doc = "Field `OIS1N` writer - Output Idle state 1"]
pub type OIS1N_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OIS2` reader - Output Idle state 2"]
pub type OIS2_R = crate :: BitReader ; # [doc = "Field `OIS2` writer - Output Idle state 2"]
pub type OIS2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OIS2N` reader - Output Idle state 2"]
pub type OIS2N_R = crate :: BitReader ; # [doc = "Field `OIS2N` writer - Output Idle state 2"]
pub type OIS2N_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OIS3` reader - Output Idle state 3"]
pub type OIS3_R = crate :: BitReader ; # [doc = "Field `OIS3` writer - Output Idle state 3"]
pub type OIS3_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OIS3N` reader - Output Idle state 3"]
pub type OIS3N_R = crate :: BitReader ; # [doc = "Field `OIS3N` writer - Output Idle state 3"]
pub type OIS3N_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OIS4` reader - Output Idle state 4"]
pub type OIS4_R = crate :: BitReader ; # [doc = "Field `OIS4` writer - Output Idle state 4"]
pub type OIS4_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture/compare preloaded control"]
# [inline (always)]
pub fn ccpc (& self) -> CCPC_R { CCPC_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - Capture/compare control update selection"]
# [inline (always)]
pub fn ccus (& self) -> CCUS_R { CCUS_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Capture/compare DMA selection"]
# [inline (always)]
pub fn ccds (& self) -> CCDS_R { CCDS_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - Master mode selection"]
# [inline (always)]
pub fn mms (& self) -> MMS_R { MMS_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - TI1 selection"]
# [inline (always)]
pub fn ti1s (& self) -> TI1S_R { TI1S_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Output Idle state 1"]
# [inline (always)]
pub fn ois1 (& self) -> OIS1_R { OIS1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Output Idle state 1"]
# [inline (always)]
pub fn ois1n (& self) -> OIS1N_R { OIS1N_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Output Idle state 2"]
# [inline (always)]
pub fn ois2 (& self) -> OIS2_R { OIS2_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Output Idle state 2"]
# [inline (always)]
pub fn ois2n (& self) -> OIS2N_R { OIS2N_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Output Idle state 3"]
# [inline (always)]
pub fn ois3 (& self) -> OIS3_R { OIS3_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Output Idle state 3"]
# [inline (always)]
pub fn ois3n (& self) -> OIS3N_R { OIS3N_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Output Idle state 4"]
# [inline (always)]
pub fn ois4 (& self) -> OIS4_R { OIS4_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture/compare preloaded control"]
# [inline (always)]
# [must_use]
pub fn ccpc (& mut self) -> CCPC_W < CTLR2_SPEC > { CCPC_W :: new (self , 0) } # [doc = "Bit 2 - Capture/compare control update selection"]
# [inline (always)]
# [must_use]
pub fn ccus (& mut self) -> CCUS_W < CTLR2_SPEC > { CCUS_W :: new (self , 2) } # [doc = "Bit 3 - Capture/compare DMA selection"]
# [inline (always)]
# [must_use]
pub fn ccds (& mut self) -> CCDS_W < CTLR2_SPEC > { CCDS_W :: new (self , 3) } # [doc = "Bits 4:6 - Master mode selection"]
# [inline (always)]
# [must_use]
pub fn mms (& mut self) -> MMS_W < CTLR2_SPEC > { MMS_W :: new (self , 4) } # [doc = "Bit 7 - TI1 selection"]
# [inline (always)]
# [must_use]
pub fn ti1s (& mut self) -> TI1S_W < CTLR2_SPEC > { TI1S_W :: new (self , 7) } # [doc = "Bit 8 - Output Idle state 1"]
# [inline (always)]
# [must_use]
pub fn ois1 (& mut self) -> OIS1_W < CTLR2_SPEC > { OIS1_W :: new (self , 8) } # [doc = "Bit 9 - Output Idle state 1"]
# [inline (always)]
# [must_use]
pub fn ois1n (& mut self) -> OIS1N_W < CTLR2_SPEC > { OIS1N_W :: new (self , 9) } # [doc = "Bit 10 - Output Idle state 2"]
# [inline (always)]
# [must_use]
pub fn ois2 (& mut self) -> OIS2_W < CTLR2_SPEC > { OIS2_W :: new (self , 10) } # [doc = "Bit 11 - Output Idle state 2"]
# [inline (always)]
# [must_use]
pub fn ois2n (& mut self) -> OIS2N_W < CTLR2_SPEC > { OIS2N_W :: new (self , 11) } # [doc = "Bit 12 - Output Idle state 3"]
# [inline (always)]
# [must_use]
pub fn ois3 (& mut self) -> OIS3_W < CTLR2_SPEC > { OIS3_W :: new (self , 12) } # [doc = "Bit 13 - Output Idle state 3"]
# [inline (always)]
# [must_use]
pub fn ois3n (& mut self) -> OIS3N_W < CTLR2_SPEC > { OIS3N_W :: new (self , 13) } # [doc = "Bit 14 - Output Idle state 4"]
# [inline (always)]
# [must_use]
pub fn ois4 (& mut self) -> OIS4_W < CTLR2_SPEC > { OIS4_W :: new (self , 14) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR2_SPEC ; impl crate :: RegisterSpec for CTLR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr2::R`](R) reader structure"]
impl crate :: Readable for CTLR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr2::W`](W) writer structure"]
impl crate :: Writable for CTLR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR2 to value 0"]
impl crate :: Resettable for CTLR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "SMCFGR (rw) register accessor: slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcfgr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smcfgr`]
module"]
pub type SMCFGR = crate :: Reg < smcfgr :: SMCFGR_SPEC > ; # [doc = "slave mode control register"]
pub mod smcfgr { # [doc = "Register `SMCFGR` reader"]
pub type R = crate :: R < SMCFGR_SPEC > ; # [doc = "Register `SMCFGR` writer"]
pub type W = crate :: W < SMCFGR_SPEC > ; # [doc = "Field `SMS` reader - Slave mode selection"]
pub type SMS_R = crate :: FieldReader ; # [doc = "Field `SMS` writer - Slave mode selection"]
pub type SMS_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TS` reader - Trigger selection"]
pub type TS_R = crate :: FieldReader ; # [doc = "Field `TS` writer - Trigger selection"]
pub type TS_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `MSM` reader - Master/Slave mode"]
pub type MSM_R = crate :: BitReader ; # [doc = "Field `MSM` writer - Master/Slave mode"]
pub type MSM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ETF` reader - External trigger filter"]
pub type ETF_R = crate :: FieldReader ; # [doc = "Field `ETF` writer - External trigger filter"]
pub type ETF_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ETPS` reader - External trigger prescaler"]
pub type ETPS_R = crate :: FieldReader ; # [doc = "Field `ETPS` writer - External trigger prescaler"]
pub type ETPS_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ECE` reader - External clock enable"]
pub type ECE_R = crate :: BitReader ; # [doc = "Field `ECE` writer - External clock enable"]
pub type ECE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ETP` reader - External trigger polarity"]
pub type ETP_R = crate :: BitReader ; # [doc = "Field `ETP` writer - External trigger polarity"]
pub type ETP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:2 - Slave mode selection"]
# [inline (always)]
pub fn sms (& self) -> SMS_R { SMS_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Trigger selection"]
# [inline (always)]
pub fn ts (& self) -> TS_R { TS_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - Master/Slave mode"]
# [inline (always)]
pub fn msm (& self) -> MSM_R { MSM_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:11 - External trigger filter"]
# [inline (always)]
pub fn etf (& self) -> ETF_R { ETF_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:13 - External trigger prescaler"]
# [inline (always)]
pub fn etps (& self) -> ETPS_R { ETPS_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - External clock enable"]
# [inline (always)]
pub fn ece (& self) -> ECE_R { ECE_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - External trigger polarity"]
# [inline (always)]
pub fn etp (& self) -> ETP_R { ETP_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - Slave mode selection"]
# [inline (always)]
# [must_use]
pub fn sms (& mut self) -> SMS_W < SMCFGR_SPEC > { SMS_W :: new (self , 0) } # [doc = "Bits 4:6 - Trigger selection"]
# [inline (always)]
# [must_use]
pub fn ts (& mut self) -> TS_W < SMCFGR_SPEC > { TS_W :: new (self , 4) } # [doc = "Bit 7 - Master/Slave mode"]
# [inline (always)]
# [must_use]
pub fn msm (& mut self) -> MSM_W < SMCFGR_SPEC > { MSM_W :: new (self , 7) } # [doc = "Bits 8:11 - External trigger filter"]
# [inline (always)]
# [must_use]
pub fn etf (& mut self) -> ETF_W < SMCFGR_SPEC > { ETF_W :: new (self , 8) } # [doc = "Bits 12:13 - External trigger prescaler"]
# [inline (always)]
# [must_use]
pub fn etps (& mut self) -> ETPS_W < SMCFGR_SPEC > { ETPS_W :: new (self , 12) } # [doc = "Bit 14 - External clock enable"]
# [inline (always)]
# [must_use]
pub fn ece (& mut self) -> ECE_W < SMCFGR_SPEC > { ECE_W :: new (self , 14) } # [doc = "Bit 15 - External trigger polarity"]
# [inline (always)]
# [must_use]
pub fn etp (& mut self) -> ETP_W < SMCFGR_SPEC > { ETP_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcfgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SMCFGR_SPEC ; impl crate :: RegisterSpec for SMCFGR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`smcfgr::R`](R) reader structure"]
impl crate :: Readable for SMCFGR_SPEC { } # [doc = "`write(|w| ..)` method takes [`smcfgr::W`](W) writer structure"]
impl crate :: Writable for SMCFGR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SMCFGR to value 0"]
impl crate :: Resettable for SMCFGR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DMAINTENR (rw) register accessor: DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaintenr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaintenr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmaintenr`]
module"]
pub type DMAINTENR = crate :: Reg < dmaintenr :: DMAINTENR_SPEC > ; # [doc = "DMA/Interrupt enable register"]
pub mod dmaintenr { # [doc = "Register `DMAINTENR` reader"]
pub type R = crate :: R < DMAINTENR_SPEC > ; # [doc = "Register `DMAINTENR` writer"]
pub type W = crate :: W < DMAINTENR_SPEC > ; # [doc = "Field `UIE` reader - Update interrupt enable"]
pub type UIE_R = crate :: BitReader ; # [doc = "Field `UIE` writer - Update interrupt enable"]
pub type UIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1IE` reader - Capture/Compare 1 interrupt enable"]
pub type CC1IE_R = crate :: BitReader ; # [doc = "Field `CC1IE` writer - Capture/Compare 1 interrupt enable"]
pub type CC1IE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2IE` reader - Capture/Compare 2 interrupt enable"]
pub type CC2IE_R = crate :: BitReader ; # [doc = "Field `CC2IE` writer - Capture/Compare 2 interrupt enable"]
pub type CC2IE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3IE` reader - Capture/Compare 3 interrupt enable"]
pub type CC3IE_R = crate :: BitReader ; # [doc = "Field `CC3IE` writer - Capture/Compare 3 interrupt enable"]
pub type CC3IE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4IE` reader - Capture/Compare 4 interrupt enable"]
pub type CC4IE_R = crate :: BitReader ; # [doc = "Field `CC4IE` writer - Capture/Compare 4 interrupt enable"]
pub type CC4IE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `COMIE` reader - COM interrupt enable"]
pub type COMIE_R = crate :: BitReader ; # [doc = "Field `COMIE` writer - COM interrupt enable"]
pub type COMIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIE` reader - Trigger interrupt enable"]
pub type TIE_R = crate :: BitReader ; # [doc = "Field `TIE` writer - Trigger interrupt enable"]
pub type TIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BIE` reader - Break interrupt enable"]
pub type BIE_R = crate :: BitReader ; # [doc = "Field `BIE` writer - Break interrupt enable"]
pub type BIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `UDE` reader - Update DMA request enable"]
pub type UDE_R = crate :: BitReader ; # [doc = "Field `UDE` writer - Update DMA request enable"]
pub type UDE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1DE` reader - Capture/Compare 1 DMA request enable"]
pub type CC1DE_R = crate :: BitReader ; # [doc = "Field `CC1DE` writer - Capture/Compare 1 DMA request enable"]
pub type CC1DE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2DE` reader - Capture/Compare 2 DMA request enable"]
pub type CC2DE_R = crate :: BitReader ; # [doc = "Field `CC2DE` writer - Capture/Compare 2 DMA request enable"]
pub type CC2DE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3DE` reader - Capture/Compare 3 DMA request enable"]
pub type CC3DE_R = crate :: BitReader ; # [doc = "Field `CC3DE` writer - Capture/Compare 3 DMA request enable"]
pub type CC3DE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4DE` reader - Capture/Compare 4 DMA request enable"]
pub type CC4DE_R = crate :: BitReader ; # [doc = "Field `CC4DE` writer - Capture/Compare 4 DMA request enable"]
pub type CC4DE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `COMDE` reader - COM DMA request enable"]
pub type COMDE_R = crate :: BitReader ; # [doc = "Field `COMDE` writer - COM DMA request enable"]
pub type COMDE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TDE` reader - Trigger DMA request enable"]
pub type TDE_R = crate :: BitReader ; # [doc = "Field `TDE` writer - Trigger DMA request enable"]
pub type TDE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Update interrupt enable"]
# [inline (always)]
pub fn uie (& self) -> UIE_R { UIE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture/Compare 1 interrupt enable"]
# [inline (always)]
pub fn cc1ie (& self) -> CC1IE_R { CC1IE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Capture/Compare 2 interrupt enable"]
# [inline (always)]
pub fn cc2ie (& self) -> CC2IE_R { CC2IE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Capture/Compare 3 interrupt enable"]
# [inline (always)]
pub fn cc3ie (& self) -> CC3IE_R { CC3IE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Capture/Compare 4 interrupt enable"]
# [inline (always)]
pub fn cc4ie (& self) -> CC4IE_R { CC4IE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - COM interrupt enable"]
# [inline (always)]
pub fn comie (& self) -> COMIE_R { COMIE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Trigger interrupt enable"]
# [inline (always)]
pub fn tie (& self) -> TIE_R { TIE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Break interrupt enable"]
# [inline (always)]
pub fn bie (& self) -> BIE_R { BIE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Update DMA request enable"]
# [inline (always)]
pub fn ude (& self) -> UDE_R { UDE_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture/Compare 1 DMA request enable"]
# [inline (always)]
pub fn cc1de (& self) -> CC1DE_R { CC1DE_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Capture/Compare 2 DMA request enable"]
# [inline (always)]
pub fn cc2de (& self) -> CC2DE_R { CC2DE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Capture/Compare 3 DMA request enable"]
# [inline (always)]
pub fn cc3de (& self) -> CC3DE_R { CC3DE_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Capture/Compare 4 DMA request enable"]
# [inline (always)]
pub fn cc4de (& self) -> CC4DE_R { CC4DE_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - COM DMA request enable"]
# [inline (always)]
pub fn comde (& self) -> COMDE_R { COMDE_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Trigger DMA request enable"]
# [inline (always)]
pub fn tde (& self) -> TDE_R { TDE_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Update interrupt enable"]
# [inline (always)]
# [must_use]
pub fn uie (& mut self) -> UIE_W < DMAINTENR_SPEC > { UIE_W :: new (self , 0) } # [doc = "Bit 1 - Capture/Compare 1 interrupt enable"]
# [inline (always)]
# [must_use]
pub fn cc1ie (& mut self) -> CC1IE_W < DMAINTENR_SPEC > { CC1IE_W :: new (self , 1) } # [doc = "Bit 2 - Capture/Compare 2 interrupt enable"]
# [inline (always)]
# [must_use]
pub fn cc2ie (& mut self) -> CC2IE_W < DMAINTENR_SPEC > { CC2IE_W :: new (self , 2) } # [doc = "Bit 3 - Capture/Compare 3 interrupt enable"]
# [inline (always)]
# [must_use]
pub fn cc3ie (& mut self) -> CC3IE_W < DMAINTENR_SPEC > { CC3IE_W :: new (self , 3) } # [doc = "Bit 4 - Capture/Compare 4 interrupt enable"]
# [inline (always)]
# [must_use]
pub fn cc4ie (& mut self) -> CC4IE_W < DMAINTENR_SPEC > { CC4IE_W :: new (self , 4) } # [doc = "Bit 5 - COM interrupt enable"]
# [inline (always)]
# [must_use]
pub fn comie (& mut self) -> COMIE_W < DMAINTENR_SPEC > { COMIE_W :: new (self , 5) } # [doc = "Bit 6 - Trigger interrupt enable"]
# [inline (always)]
# [must_use]
pub fn tie (& mut self) -> TIE_W < DMAINTENR_SPEC > { TIE_W :: new (self , 6) } # [doc = "Bit 7 - Break interrupt enable"]
# [inline (always)]
# [must_use]
pub fn bie (& mut self) -> BIE_W < DMAINTENR_SPEC > { BIE_W :: new (self , 7) } # [doc = "Bit 8 - Update DMA request enable"]
# [inline (always)]
# [must_use]
pub fn ude (& mut self) -> UDE_W < DMAINTENR_SPEC > { UDE_W :: new (self , 8) } # [doc = "Bit 9 - Capture/Compare 1 DMA request enable"]
# [inline (always)]
# [must_use]
pub fn cc1de (& mut self) -> CC1DE_W < DMAINTENR_SPEC > { CC1DE_W :: new (self , 9) } # [doc = "Bit 10 - Capture/Compare 2 DMA request enable"]
# [inline (always)]
# [must_use]
pub fn cc2de (& mut self) -> CC2DE_W < DMAINTENR_SPEC > { CC2DE_W :: new (self , 10) } # [doc = "Bit 11 - Capture/Compare 3 DMA request enable"]
# [inline (always)]
# [must_use]
pub fn cc3de (& mut self) -> CC3DE_W < DMAINTENR_SPEC > { CC3DE_W :: new (self , 11) } # [doc = "Bit 12 - Capture/Compare 4 DMA request enable"]
# [inline (always)]
# [must_use]
pub fn cc4de (& mut self) -> CC4DE_W < DMAINTENR_SPEC > { CC4DE_W :: new (self , 12) } # [doc = "Bit 13 - COM DMA request enable"]
# [inline (always)]
# [must_use]
pub fn comde (& mut self) -> COMDE_W < DMAINTENR_SPEC > { COMDE_W :: new (self , 13) } # [doc = "Bit 14 - Trigger DMA request enable"]
# [inline (always)]
# [must_use]
pub fn tde (& mut self) -> TDE_W < DMAINTENR_SPEC > { TDE_W :: new (self , 14) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaintenr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaintenr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMAINTENR_SPEC ; impl crate :: RegisterSpec for DMAINTENR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dmaintenr::R`](R) reader structure"]
impl crate :: Readable for DMAINTENR_SPEC { } # [doc = "`write(|w| ..)` method takes [`dmaintenr::W`](W) writer structure"]
impl crate :: Writable for DMAINTENR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DMAINTENR to value 0"]
impl crate :: Resettable for DMAINTENR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTFR (rw) register accessor: status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intfr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intfr`]
module"]
pub type INTFR = crate :: Reg < intfr :: INTFR_SPEC > ; # [doc = "status register"]
pub mod intfr { # [doc = "Register `INTFR` reader"]
pub type R = crate :: R < INTFR_SPEC > ; # [doc = "Register `INTFR` writer"]
pub type W = crate :: W < INTFR_SPEC > ; # [doc = "Field `UIF` reader - Update interrupt flag"]
pub type UIF_R = crate :: BitReader ; # [doc = "Field `UIF` writer - Update interrupt flag"]
pub type UIF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1IF` reader - Capture/compare 1 interrupt flag"]
pub type CC1IF_R = crate :: BitReader ; # [doc = "Field `CC1IF` writer - Capture/compare 1 interrupt flag"]
pub type CC1IF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2IF` reader - Capture/Compare 2 interrupt flag"]
pub type CC2IF_R = crate :: BitReader ; # [doc = "Field `CC2IF` writer - Capture/Compare 2 interrupt flag"]
pub type CC2IF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3IF` reader - Capture/Compare 3 interrupt flag"]
pub type CC3IF_R = crate :: BitReader ; # [doc = "Field `CC3IF` writer - Capture/Compare 3 interrupt flag"]
pub type CC3IF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4IF` reader - Capture/Compare 4 interrupt flag"]
pub type CC4IF_R = crate :: BitReader ; # [doc = "Field `CC4IF` writer - Capture/Compare 4 interrupt flag"]
pub type CC4IF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `COMIF` reader - COM interrupt flag"]
pub type COMIF_R = crate :: BitReader ; # [doc = "Field `COMIF` writer - COM interrupt flag"]
pub type COMIF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIF` reader - Trigger interrupt flag"]
pub type TIF_R = crate :: BitReader ; # [doc = "Field `TIF` writer - Trigger interrupt flag"]
pub type TIF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BIF` reader - Break interrupt flag"]
pub type BIF_R = crate :: BitReader ; # [doc = "Field `BIF` writer - Break interrupt flag"]
pub type BIF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1OF` reader - Capture/Compare 1 overcapture flag"]
pub type CC1OF_R = crate :: BitReader ; # [doc = "Field `CC1OF` writer - Capture/Compare 1 overcapture flag"]
pub type CC1OF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2OF` reader - Capture/compare 2 overcapture flag"]
pub type CC2OF_R = crate :: BitReader ; # [doc = "Field `CC2OF` writer - Capture/compare 2 overcapture flag"]
pub type CC2OF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3OF` reader - Capture/Compare 3 overcapture flag"]
pub type CC3OF_R = crate :: BitReader ; # [doc = "Field `CC3OF` writer - Capture/Compare 3 overcapture flag"]
pub type CC3OF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4OF` reader - Capture/Compare 4 overcapture flag"]
pub type CC4OF_R = crate :: BitReader ; # [doc = "Field `CC4OF` writer - Capture/Compare 4 overcapture flag"]
pub type CC4OF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Update interrupt flag"]
# [inline (always)]
pub fn uif (& self) -> UIF_R { UIF_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture/compare 1 interrupt flag"]
# [inline (always)]
pub fn cc1if (& self) -> CC1IF_R { CC1IF_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Capture/Compare 2 interrupt flag"]
# [inline (always)]
pub fn cc2if (& self) -> CC2IF_R { CC2IF_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Capture/Compare 3 interrupt flag"]
# [inline (always)]
pub fn cc3if (& self) -> CC3IF_R { CC3IF_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Capture/Compare 4 interrupt flag"]
# [inline (always)]
pub fn cc4if (& self) -> CC4IF_R { CC4IF_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - COM interrupt flag"]
# [inline (always)]
pub fn comif (& self) -> COMIF_R { COMIF_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Trigger interrupt flag"]
# [inline (always)]
pub fn tif (& self) -> TIF_R { TIF_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Break interrupt flag"]
# [inline (always)]
pub fn bif (& self) -> BIF_R { BIF_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 9 - Capture/Compare 1 overcapture flag"]
# [inline (always)]
pub fn cc1of (& self) -> CC1OF_R { CC1OF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Capture/compare 2 overcapture flag"]
# [inline (always)]
pub fn cc2of (& self) -> CC2OF_R { CC2OF_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Capture/Compare 3 overcapture flag"]
# [inline (always)]
pub fn cc3of (& self) -> CC3OF_R { CC3OF_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Capture/Compare 4 overcapture flag"]
# [inline (always)]
pub fn cc4of (& self) -> CC4OF_R { CC4OF_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bit 0 - Update interrupt flag"]
# [inline (always)]
# [must_use]
pub fn uif (& mut self) -> UIF_W < INTFR_SPEC > { UIF_W :: new (self , 0) } # [doc = "Bit 1 - Capture/compare 1 interrupt flag"]
# [inline (always)]
# [must_use]
pub fn cc1if (& mut self) -> CC1IF_W < INTFR_SPEC > { CC1IF_W :: new (self , 1) } # [doc = "Bit 2 - Capture/Compare 2 interrupt flag"]
# [inline (always)]
# [must_use]
pub fn cc2if (& mut self) -> CC2IF_W < INTFR_SPEC > { CC2IF_W :: new (self , 2) } # [doc = "Bit 3 - Capture/Compare 3 interrupt flag"]
# [inline (always)]
# [must_use]
pub fn cc3if (& mut self) -> CC3IF_W < INTFR_SPEC > { CC3IF_W :: new (self , 3) } # [doc = "Bit 4 - Capture/Compare 4 interrupt flag"]
# [inline (always)]
# [must_use]
pub fn cc4if (& mut self) -> CC4IF_W < INTFR_SPEC > { CC4IF_W :: new (self , 4) } # [doc = "Bit 5 - COM interrupt flag"]
# [inline (always)]
# [must_use]
pub fn comif (& mut self) -> COMIF_W < INTFR_SPEC > { COMIF_W :: new (self , 5) } # [doc = "Bit 6 - Trigger interrupt flag"]
# [inline (always)]
# [must_use]
pub fn tif (& mut self) -> TIF_W < INTFR_SPEC > { TIF_W :: new (self , 6) } # [doc = "Bit 7 - Break interrupt flag"]
# [inline (always)]
# [must_use]
pub fn bif (& mut self) -> BIF_W < INTFR_SPEC > { BIF_W :: new (self , 7) } # [doc = "Bit 9 - Capture/Compare 1 overcapture flag"]
# [inline (always)]
# [must_use]
pub fn cc1of (& mut self) -> CC1OF_W < INTFR_SPEC > { CC1OF_W :: new (self , 9) } # [doc = "Bit 10 - Capture/compare 2 overcapture flag"]
# [inline (always)]
# [must_use]
pub fn cc2of (& mut self) -> CC2OF_W < INTFR_SPEC > { CC2OF_W :: new (self , 10) } # [doc = "Bit 11 - Capture/Compare 3 overcapture flag"]
# [inline (always)]
# [must_use]
pub fn cc3of (& mut self) -> CC3OF_W < INTFR_SPEC > { CC3OF_W :: new (self , 11) } # [doc = "Bit 12 - Capture/Compare 4 overcapture flag"]
# [inline (always)]
# [must_use]
pub fn cc4of (& mut self) -> CC4OF_W < INTFR_SPEC > { CC4OF_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intfr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intfr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTFR_SPEC ; impl crate :: RegisterSpec for INTFR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`intfr::R`](R) reader structure"]
impl crate :: Readable for INTFR_SPEC { } # [doc = "`write(|w| ..)` method takes [`intfr::W`](W) writer structure"]
impl crate :: Writable for INTFR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTFR to value 0"]
impl crate :: Resettable for INTFR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "SWEVGR (w) register accessor: event generation register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swevgr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swevgr`]
module"]
pub type SWEVGR = crate :: Reg < swevgr :: SWEVGR_SPEC > ; # [doc = "event generation register"]
pub mod swevgr { # [doc = "Register `SWEVGR` writer"]
pub type W = crate :: W < SWEVGR_SPEC > ; # [doc = "Field `UG` writer - Update generation"]
pub type UG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1G` writer - Capture/compare 1 generation"]
pub type CC1G_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2G` writer - Capture/compare 2 generation"]
pub type CC2G_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3G` writer - Capture/compare 3 generation"]
pub type CC3G_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4G` writer - Capture/compare 4 generation"]
pub type CC4G_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `COMG` writer - Capture/Compare control update generation"]
pub type COMG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TG` writer - Trigger generation"]
pub type TG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BG` writer - Break generation"]
pub type BG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W { # [doc = "Bit 0 - Update generation"]
# [inline (always)]
# [must_use]
pub fn ug (& mut self) -> UG_W < SWEVGR_SPEC > { UG_W :: new (self , 0) } # [doc = "Bit 1 - Capture/compare 1 generation"]
# [inline (always)]
# [must_use]
pub fn cc1g (& mut self) -> CC1G_W < SWEVGR_SPEC > { CC1G_W :: new (self , 1) } # [doc = "Bit 2 - Capture/compare 2 generation"]
# [inline (always)]
# [must_use]
pub fn cc2g (& mut self) -> CC2G_W < SWEVGR_SPEC > { CC2G_W :: new (self , 2) } # [doc = "Bit 3 - Capture/compare 3 generation"]
# [inline (always)]
# [must_use]
pub fn cc3g (& mut self) -> CC3G_W < SWEVGR_SPEC > { CC3G_W :: new (self , 3) } # [doc = "Bit 4 - Capture/compare 4 generation"]
# [inline (always)]
# [must_use]
pub fn cc4g (& mut self) -> CC4G_W < SWEVGR_SPEC > { CC4G_W :: new (self , 4) } # [doc = "Bit 5 - Capture/Compare control update generation"]
# [inline (always)]
# [must_use]
pub fn comg (& mut self) -> COMG_W < SWEVGR_SPEC > { COMG_W :: new (self , 5) } # [doc = "Bit 6 - Trigger generation"]
# [inline (always)]
# [must_use]
pub fn tg (& mut self) -> TG_W < SWEVGR_SPEC > { TG_W :: new (self , 6) } # [doc = "Bit 7 - Break generation"]
# [inline (always)]
# [must_use]
pub fn bg (& mut self) -> BG_W < SWEVGR_SPEC > { BG_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "event generation register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swevgr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SWEVGR_SPEC ; impl crate :: RegisterSpec for SWEVGR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`swevgr::W`](W) writer structure"]
impl crate :: Writable for SWEVGR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SWEVGR to value 0"]
impl crate :: Resettable for SWEVGR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CHCTLR1_Output (rw) register accessor: capture/compare mode register (output mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr1_output::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr1_output::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chctlr1_output`]
module"]
pub type CHCTLR1_OUTPUT = crate :: Reg < chctlr1_output :: CHCTLR1_OUTPUT_SPEC > ; # [doc = "capture/compare mode register (output mode)"]
pub mod chctlr1_output { # [doc = "Register `CHCTLR1_Output` reader"]
pub type R = crate :: R < CHCTLR1_OUTPUT_SPEC > ; # [doc = "Register `CHCTLR1_Output` writer"]
pub type W = crate :: W < CHCTLR1_OUTPUT_SPEC > ; # [doc = "Field `CC1S` reader - Capture/Compare 1 selection"]
pub type CC1S_R = crate :: FieldReader ; # [doc = "Field `CC1S` writer - Capture/Compare 1 selection"]
pub type CC1S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `OC1FE` reader - Output Compare 1 fast enable"]
pub type OC1FE_R = crate :: BitReader ; # [doc = "Field `OC1FE` writer - Output Compare 1 fast enable"]
pub type OC1FE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC1PE` reader - Output Compare 1 preload enable"]
pub type OC1PE_R = crate :: BitReader ; # [doc = "Field `OC1PE` writer - Output Compare 1 preload enable"]
pub type OC1PE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC1M` reader - Output Compare 1 mode"]
pub type OC1M_R = crate :: FieldReader ; # [doc = "Field `OC1M` writer - Output Compare 1 mode"]
pub type OC1M_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `OC1CE` reader - Output Compare 1 clear enable"]
pub type OC1CE_R = crate :: BitReader ; # [doc = "Field `OC1CE` writer - Output Compare 1 clear enable"]
pub type OC1CE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2S` reader - Capture/Compare 2 selection"]
pub type CC2S_R = crate :: FieldReader ; # [doc = "Field `CC2S` writer - Capture/Compare 2 selection"]
pub type CC2S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `OC2FE` reader - Output Compare 2 fast enable"]
pub type OC2FE_R = crate :: BitReader ; # [doc = "Field `OC2FE` writer - Output Compare 2 fast enable"]
pub type OC2FE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC2PE` reader - Output Compare 2 preload enable"]
pub type OC2PE_R = crate :: BitReader ; # [doc = "Field `OC2PE` writer - Output Compare 2 preload enable"]
pub type OC2PE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC2M` reader - Output Compare 2 mode"]
pub type OC2M_R = crate :: FieldReader ; # [doc = "Field `OC2M` writer - Output Compare 2 mode"]
pub type OC2M_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `OC2CE` reader - Output Compare 2 clear enable"]
pub type OC2CE_R = crate :: BitReader ; # [doc = "Field `OC2CE` writer - Output Compare 2 clear enable"]
pub type OC2CE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - Capture/Compare 1 selection"]
# [inline (always)]
pub fn cc1s (& self) -> CC1S_R { CC1S_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Output Compare 1 fast enable"]
# [inline (always)]
pub fn oc1fe (& self) -> OC1FE_R { OC1FE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Output Compare 1 preload enable"]
# [inline (always)]
pub fn oc1pe (& self) -> OC1PE_R { OC1PE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - Output Compare 1 mode"]
# [inline (always)]
pub fn oc1m (& self) -> OC1M_R { OC1M_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - Output Compare 1 clear enable"]
# [inline (always)]
pub fn oc1ce (& self) -> OC1CE_R { OC1CE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Capture/Compare 2 selection"]
# [inline (always)]
pub fn cc2s (& self) -> CC2S_R { CC2S_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 10 - Output Compare 2 fast enable"]
# [inline (always)]
pub fn oc2fe (& self) -> OC2FE_R { OC2FE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Output Compare 2 preload enable"]
# [inline (always)]
pub fn oc2pe (& self) -> OC2PE_R { OC2PE_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:14 - Output Compare 2 mode"]
# [inline (always)]
pub fn oc2m (& self) -> OC2M_R { OC2M_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 15 - Output Compare 2 clear enable"]
# [inline (always)]
pub fn oc2ce (& self) -> OC2CE_R { OC2CE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - Capture/Compare 1 selection"]
# [inline (always)]
# [must_use]
pub fn cc1s (& mut self) -> CC1S_W < CHCTLR1_OUTPUT_SPEC > { CC1S_W :: new (self , 0) } # [doc = "Bit 2 - Output Compare 1 fast enable"]
# [inline (always)]
# [must_use]
pub fn oc1fe (& mut self) -> OC1FE_W < CHCTLR1_OUTPUT_SPEC > { OC1FE_W :: new (self , 2) } # [doc = "Bit 3 - Output Compare 1 preload enable"]
# [inline (always)]
# [must_use]
pub fn oc1pe (& mut self) -> OC1PE_W < CHCTLR1_OUTPUT_SPEC > { OC1PE_W :: new (self , 3) } # [doc = "Bits 4:6 - Output Compare 1 mode"]
# [inline (always)]
# [must_use]
pub fn oc1m (& mut self) -> OC1M_W < CHCTLR1_OUTPUT_SPEC > { OC1M_W :: new (self , 4) } # [doc = "Bit 7 - Output Compare 1 clear enable"]
# [inline (always)]
# [must_use]
pub fn oc1ce (& mut self) -> OC1CE_W < CHCTLR1_OUTPUT_SPEC > { OC1CE_W :: new (self , 7) } # [doc = "Bits 8:9 - Capture/Compare 2 selection"]
# [inline (always)]
# [must_use]
pub fn cc2s (& mut self) -> CC2S_W < CHCTLR1_OUTPUT_SPEC > { CC2S_W :: new (self , 8) } # [doc = "Bit 10 - Output Compare 2 fast enable"]
# [inline (always)]
# [must_use]
pub fn oc2fe (& mut self) -> OC2FE_W < CHCTLR1_OUTPUT_SPEC > { OC2FE_W :: new (self , 10) } # [doc = "Bit 11 - Output Compare 2 preload enable"]
# [inline (always)]
# [must_use]
pub fn oc2pe (& mut self) -> OC2PE_W < CHCTLR1_OUTPUT_SPEC > { OC2PE_W :: new (self , 11) } # [doc = "Bits 12:14 - Output Compare 2 mode"]
# [inline (always)]
# [must_use]
pub fn oc2m (& mut self) -> OC2M_W < CHCTLR1_OUTPUT_SPEC > { OC2M_W :: new (self , 12) } # [doc = "Bit 15 - Output Compare 2 clear enable"]
# [inline (always)]
# [must_use]
pub fn oc2ce (& mut self) -> OC2CE_W < CHCTLR1_OUTPUT_SPEC > { OC2CE_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare mode register (output mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr1_output::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr1_output::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CHCTLR1_OUTPUT_SPEC ; impl crate :: RegisterSpec for CHCTLR1_OUTPUT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`chctlr1_output::R`](R) reader structure"]
impl crate :: Readable for CHCTLR1_OUTPUT_SPEC { } # [doc = "`write(|w| ..)` method takes [`chctlr1_output::W`](W) writer structure"]
impl crate :: Writable for CHCTLR1_OUTPUT_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CHCTLR1_Output to value 0"]
impl crate :: Resettable for CHCTLR1_OUTPUT_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CHCTLR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr1_input::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr1_input::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chctlr1_input`]
module"]
pub type CHCTLR1_INPUT = crate :: Reg < chctlr1_input :: CHCTLR1_INPUT_SPEC > ; # [doc = "capture/compare mode register 1 (input mode)"]
pub mod chctlr1_input { # [doc = "Register `CHCTLR1_Input` reader"]
pub type R = crate :: R < CHCTLR1_INPUT_SPEC > ; # [doc = "Register `CHCTLR1_Input` writer"]
pub type W = crate :: W < CHCTLR1_INPUT_SPEC > ; # [doc = "Field `CC1S` reader - Capture/Compare 1 selection"]
pub type CC1S_R = crate :: FieldReader ; # [doc = "Field `CC1S` writer - Capture/Compare 1 selection"]
pub type CC1S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC1PSC` reader - Input capture 1 prescaler"]
pub type IC1PSC_R = crate :: FieldReader ; # [doc = "Field `IC1PSC` writer - Input capture 1 prescaler"]
pub type IC1PSC_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC1F` reader - Input capture 1 filter"]
pub type IC1F_R = crate :: FieldReader ; # [doc = "Field `IC1F` writer - Input capture 1 filter"]
pub type IC1F_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `CC2S` reader - Capture/Compare 2 selection"]
pub type CC2S_R = crate :: FieldReader ; # [doc = "Field `CC2S` writer - Capture/Compare 2 selection"]
pub type CC2S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC2PSC` reader - Input capture 2 prescaler"]
pub type IC2PSC_R = crate :: FieldReader ; # [doc = "Field `IC2PSC` writer - Input capture 2 prescaler"]
pub type IC2PSC_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC2F` reader - Input capture 2 filter"]
pub type IC2F_R = crate :: FieldReader ; # [doc = "Field `IC2F` writer - Input capture 2 filter"]
pub type IC2F_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:1 - Capture/Compare 1 selection"]
# [inline (always)]
pub fn cc1s (& self) -> CC1S_R { CC1S_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Input capture 1 prescaler"]
# [inline (always)]
pub fn ic1psc (& self) -> IC1PSC_R { IC1PSC_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - Input capture 1 filter"]
# [inline (always)]
pub fn ic1f (& self) -> IC1F_R { IC1F_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:9 - Capture/Compare 2 selection"]
# [inline (always)]
pub fn cc2s (& self) -> CC2S_R { CC2S_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Input capture 2 prescaler"]
# [inline (always)]
pub fn ic2psc (& self) -> IC2PSC_R { IC2PSC_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:15 - Input capture 2 filter"]
# [inline (always)]
pub fn ic2f (& self) -> IC2F_R { IC2F_R :: new (((self . bits >> 12) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:1 - Capture/Compare 1 selection"]
# [inline (always)]
# [must_use]
pub fn cc1s (& mut self) -> CC1S_W < CHCTLR1_INPUT_SPEC > { CC1S_W :: new (self , 0) } # [doc = "Bits 2:3 - Input capture 1 prescaler"]
# [inline (always)]
# [must_use]
pub fn ic1psc (& mut self) -> IC1PSC_W < CHCTLR1_INPUT_SPEC > { IC1PSC_W :: new (self , 2) } # [doc = "Bits 4:7 - Input capture 1 filter"]
# [inline (always)]
# [must_use]
pub fn ic1f (& mut self) -> IC1F_W < CHCTLR1_INPUT_SPEC > { IC1F_W :: new (self , 4) } # [doc = "Bits 8:9 - Capture/Compare 2 selection"]
# [inline (always)]
# [must_use]
pub fn cc2s (& mut self) -> CC2S_W < CHCTLR1_INPUT_SPEC > { CC2S_W :: new (self , 8) } # [doc = "Bits 10:11 - Input capture 2 prescaler"]
# [inline (always)]
# [must_use]
pub fn ic2psc (& mut self) -> IC2PSC_W < CHCTLR1_INPUT_SPEC > { IC2PSC_W :: new (self , 10) } # [doc = "Bits 12:15 - Input capture 2 filter"]
# [inline (always)]
# [must_use]
pub fn ic2f (& mut self) -> IC2F_W < CHCTLR1_INPUT_SPEC > { IC2F_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare mode register 1 (input mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr1_input::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr1_input::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CHCTLR1_INPUT_SPEC ; impl crate :: RegisterSpec for CHCTLR1_INPUT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`chctlr1_input::R`](R) reader structure"]
impl crate :: Readable for CHCTLR1_INPUT_SPEC { } # [doc = "`write(|w| ..)` method takes [`chctlr1_input::W`](W) writer structure"]
impl crate :: Writable for CHCTLR1_INPUT_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CHCTLR1_Input to value 0"]
impl crate :: Resettable for CHCTLR1_INPUT_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CHCTLR2_Output (rw) register accessor: capture/compare mode register (output mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr2_output::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr2_output::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chctlr2_output`]
module"]
pub type CHCTLR2_OUTPUT = crate :: Reg < chctlr2_output :: CHCTLR2_OUTPUT_SPEC > ; # [doc = "capture/compare mode register (output mode)"]
pub mod chctlr2_output { # [doc = "Register `CHCTLR2_Output` reader"]
pub type R = crate :: R < CHCTLR2_OUTPUT_SPEC > ; # [doc = "Register `CHCTLR2_Output` writer"]
pub type W = crate :: W < CHCTLR2_OUTPUT_SPEC > ; # [doc = "Field `CC3S` reader - Capture/Compare 3 selection"]
pub type CC3S_R = crate :: FieldReader ; # [doc = "Field `CC3S` writer - Capture/Compare 3 selection"]
pub type CC3S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `OC3FE` reader - Output compare 3 fast enable"]
pub type OC3FE_R = crate :: BitReader ; # [doc = "Field `OC3FE` writer - Output compare 3 fast enable"]
pub type OC3FE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC3PE` reader - Output compare 3 preload enable"]
pub type OC3PE_R = crate :: BitReader ; # [doc = "Field `OC3PE` writer - Output compare 3 preload enable"]
pub type OC3PE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC3M` reader - Output compare 3 mode"]
pub type OC3M_R = crate :: FieldReader ; # [doc = "Field `OC3M` writer - Output compare 3 mode"]
pub type OC3M_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `OC3CE` reader - Output compare 3 clear enable"]
pub type OC3CE_R = crate :: BitReader ; # [doc = "Field `OC3CE` writer - Output compare 3 clear enable"]
pub type OC3CE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4S` reader - Capture/Compare 4 selection"]
pub type CC4S_R = crate :: FieldReader ; # [doc = "Field `CC4S` writer - Capture/Compare 4 selection"]
pub type CC4S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `OC4FE` reader - Output compare 4 fast enable"]
pub type OC4FE_R = crate :: BitReader ; # [doc = "Field `OC4FE` writer - Output compare 4 fast enable"]
pub type OC4FE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC4PE` reader - Output compare 4 preload enable"]
pub type OC4PE_R = crate :: BitReader ; # [doc = "Field `OC4PE` writer - Output compare 4 preload enable"]
pub type OC4PE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC4M` reader - Output compare 4 mode"]
pub type OC4M_R = crate :: FieldReader ; # [doc = "Field `OC4M` writer - Output compare 4 mode"]
pub type OC4M_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `OC4CE` reader - Output compare 4 clear enable"]
pub type OC4CE_R = crate :: BitReader ; # [doc = "Field `OC4CE` writer - Output compare 4 clear enable"]
pub type OC4CE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - Capture/Compare 3 selection"]
# [inline (always)]
pub fn cc3s (& self) -> CC3S_R { CC3S_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Output compare 3 fast enable"]
# [inline (always)]
pub fn oc3fe (& self) -> OC3FE_R { OC3FE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Output compare 3 preload enable"]
# [inline (always)]
pub fn oc3pe (& self) -> OC3PE_R { OC3PE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - Output compare 3 mode"]
# [inline (always)]
pub fn oc3m (& self) -> OC3M_R { OC3M_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - Output compare 3 clear enable"]
# [inline (always)]
pub fn oc3ce (& self) -> OC3CE_R { OC3CE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Capture/Compare 4 selection"]
# [inline (always)]
pub fn cc4s (& self) -> CC4S_R { CC4S_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 10 - Output compare 4 fast enable"]
# [inline (always)]
pub fn oc4fe (& self) -> OC4FE_R { OC4FE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Output compare 4 preload enable"]
# [inline (always)]
pub fn oc4pe (& self) -> OC4PE_R { OC4PE_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:14 - Output compare 4 mode"]
# [inline (always)]
pub fn oc4m (& self) -> OC4M_R { OC4M_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 15 - Output compare 4 clear enable"]
# [inline (always)]
pub fn oc4ce (& self) -> OC4CE_R { OC4CE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - Capture/Compare 3 selection"]
# [inline (always)]
# [must_use]
pub fn cc3s (& mut self) -> CC3S_W < CHCTLR2_OUTPUT_SPEC > { CC3S_W :: new (self , 0) } # [doc = "Bit 2 - Output compare 3 fast enable"]
# [inline (always)]
# [must_use]
pub fn oc3fe (& mut self) -> OC3FE_W < CHCTLR2_OUTPUT_SPEC > { OC3FE_W :: new (self , 2) } # [doc = "Bit 3 - Output compare 3 preload enable"]
# [inline (always)]
# [must_use]
pub fn oc3pe (& mut self) -> OC3PE_W < CHCTLR2_OUTPUT_SPEC > { OC3PE_W :: new (self , 3) } # [doc = "Bits 4:6 - Output compare 3 mode"]
# [inline (always)]
# [must_use]
pub fn oc3m (& mut self) -> OC3M_W < CHCTLR2_OUTPUT_SPEC > { OC3M_W :: new (self , 4) } # [doc = "Bit 7 - Output compare 3 clear enable"]
# [inline (always)]
# [must_use]
pub fn oc3ce (& mut self) -> OC3CE_W < CHCTLR2_OUTPUT_SPEC > { OC3CE_W :: new (self , 7) } # [doc = "Bits 8:9 - Capture/Compare 4 selection"]
# [inline (always)]
# [must_use]
pub fn cc4s (& mut self) -> CC4S_W < CHCTLR2_OUTPUT_SPEC > { CC4S_W :: new (self , 8) } # [doc = "Bit 10 - Output compare 4 fast enable"]
# [inline (always)]
# [must_use]
pub fn oc4fe (& mut self) -> OC4FE_W < CHCTLR2_OUTPUT_SPEC > { OC4FE_W :: new (self , 10) } # [doc = "Bit 11 - Output compare 4 preload enable"]
# [inline (always)]
# [must_use]
pub fn oc4pe (& mut self) -> OC4PE_W < CHCTLR2_OUTPUT_SPEC > { OC4PE_W :: new (self , 11) } # [doc = "Bits 12:14 - Output compare 4 mode"]
# [inline (always)]
# [must_use]
pub fn oc4m (& mut self) -> OC4M_W < CHCTLR2_OUTPUT_SPEC > { OC4M_W :: new (self , 12) } # [doc = "Bit 15 - Output compare 4 clear enable"]
# [inline (always)]
# [must_use]
pub fn oc4ce (& mut self) -> OC4CE_W < CHCTLR2_OUTPUT_SPEC > { OC4CE_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare mode register (output mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr2_output::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr2_output::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CHCTLR2_OUTPUT_SPEC ; impl crate :: RegisterSpec for CHCTLR2_OUTPUT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`chctlr2_output::R`](R) reader structure"]
impl crate :: Readable for CHCTLR2_OUTPUT_SPEC { } # [doc = "`write(|w| ..)` method takes [`chctlr2_output::W`](W) writer structure"]
impl crate :: Writable for CHCTLR2_OUTPUT_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CHCTLR2_Output to value 0"]
impl crate :: Resettable for CHCTLR2_OUTPUT_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CHCTLR2_Input (rw) register accessor: capture/compare mode register 2 (input mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr2_input::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr2_input::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chctlr2_input`]
module"]
pub type CHCTLR2_INPUT = crate :: Reg < chctlr2_input :: CHCTLR2_INPUT_SPEC > ; # [doc = "capture/compare mode register 2 (input mode)"]
pub mod chctlr2_input { # [doc = "Register `CHCTLR2_Input` reader"]
pub type R = crate :: R < CHCTLR2_INPUT_SPEC > ; # [doc = "Register `CHCTLR2_Input` writer"]
pub type W = crate :: W < CHCTLR2_INPUT_SPEC > ; # [doc = "Field `CC3S` reader - Capture/compare 3 selection"]
pub type CC3S_R = crate :: FieldReader ; # [doc = "Field `CC3S` writer - Capture/compare 3 selection"]
pub type CC3S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC3PSC` reader - Input capture 3 prescaler"]
pub type IC3PSC_R = crate :: FieldReader ; # [doc = "Field `IC3PSC` writer - Input capture 3 prescaler"]
pub type IC3PSC_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC3F` reader - Input capture 3 filter"]
pub type IC3F_R = crate :: FieldReader ; # [doc = "Field `IC3F` writer - Input capture 3 filter"]
pub type IC3F_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `CC4S` reader - Capture/Compare 4 selection"]
pub type CC4S_R = crate :: FieldReader ; # [doc = "Field `CC4S` writer - Capture/Compare 4 selection"]
pub type CC4S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC4PSC` reader - Input capture 4 prescaler"]
pub type IC4PSC_R = crate :: FieldReader ; # [doc = "Field `IC4PSC` writer - Input capture 4 prescaler"]
pub type IC4PSC_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC4F` reader - Input capture 4 filter"]
pub type IC4F_R = crate :: FieldReader ; # [doc = "Field `IC4F` writer - Input capture 4 filter"]
pub type IC4F_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:1 - Capture/compare 3 selection"]
# [inline (always)]
pub fn cc3s (& self) -> CC3S_R { CC3S_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Input capture 3 prescaler"]
# [inline (always)]
pub fn ic3psc (& self) -> IC3PSC_R { IC3PSC_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - Input capture 3 filter"]
# [inline (always)]
pub fn ic3f (& self) -> IC3F_R { IC3F_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:9 - Capture/Compare 4 selection"]
# [inline (always)]
pub fn cc4s (& self) -> CC4S_R { CC4S_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Input capture 4 prescaler"]
# [inline (always)]
pub fn ic4psc (& self) -> IC4PSC_R { IC4PSC_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:15 - Input capture 4 filter"]
# [inline (always)]
pub fn ic4f (& self) -> IC4F_R { IC4F_R :: new (((self . bits >> 12) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:1 - Capture/compare 3 selection"]
# [inline (always)]
# [must_use]
pub fn cc3s (& mut self) -> CC3S_W < CHCTLR2_INPUT_SPEC > { CC3S_W :: new (self , 0) } # [doc = "Bits 2:3 - Input capture 3 prescaler"]
# [inline (always)]
# [must_use]
pub fn ic3psc (& mut self) -> IC3PSC_W < CHCTLR2_INPUT_SPEC > { IC3PSC_W :: new (self , 2) } # [doc = "Bits 4:7 - Input capture 3 filter"]
# [inline (always)]
# [must_use]
pub fn ic3f (& mut self) -> IC3F_W < CHCTLR2_INPUT_SPEC > { IC3F_W :: new (self , 4) } # [doc = "Bits 8:9 - Capture/Compare 4 selection"]
# [inline (always)]
# [must_use]
pub fn cc4s (& mut self) -> CC4S_W < CHCTLR2_INPUT_SPEC > { CC4S_W :: new (self , 8) } # [doc = "Bits 10:11 - Input capture 4 prescaler"]
# [inline (always)]
# [must_use]
pub fn ic4psc (& mut self) -> IC4PSC_W < CHCTLR2_INPUT_SPEC > { IC4PSC_W :: new (self , 10) } # [doc = "Bits 12:15 - Input capture 4 filter"]
# [inline (always)]
# [must_use]
pub fn ic4f (& mut self) -> IC4F_W < CHCTLR2_INPUT_SPEC > { IC4F_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare mode register 2 (input mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr2_input::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr2_input::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CHCTLR2_INPUT_SPEC ; impl crate :: RegisterSpec for CHCTLR2_INPUT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`chctlr2_input::R`](R) reader structure"]
impl crate :: Readable for CHCTLR2_INPUT_SPEC { } # [doc = "`write(|w| ..)` method takes [`chctlr2_input::W`](W) writer structure"]
impl crate :: Writable for CHCTLR2_INPUT_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CHCTLR2_Input to value 0"]
impl crate :: Resettable for CHCTLR2_INPUT_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CCER (rw) register accessor: capture/compare enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccer::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccer`]
module"]
pub type CCER = crate :: Reg < ccer :: CCER_SPEC > ; # [doc = "capture/compare enable register"]
pub mod ccer { # [doc = "Register `CCER` reader"]
pub type R = crate :: R < CCER_SPEC > ; # [doc = "Register `CCER` writer"]
pub type W = crate :: W < CCER_SPEC > ; # [doc = "Field `CC1E` reader - Capture/Compare 1 output enable"]
pub type CC1E_R = crate :: BitReader ; # [doc = "Field `CC1E` writer - Capture/Compare 1 output enable"]
pub type CC1E_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1P` reader - Capture/Compare 1 output Polarity"]
pub type CC1P_R = crate :: BitReader ; # [doc = "Field `CC1P` writer - Capture/Compare 1 output Polarity"]
pub type CC1P_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1NE` reader - Capture/Compare 1 complementary output enable"]
pub type CC1NE_R = crate :: BitReader ; # [doc = "Field `CC1NE` writer - Capture/Compare 1 complementary output enable"]
pub type CC1NE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1NP` reader - Capture/Compare 1 output Polarity"]
pub type CC1NP_R = crate :: BitReader ; # [doc = "Field `CC1NP` writer - Capture/Compare 1 output Polarity"]
pub type CC1NP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2E` reader - Capture/Compare 2 output enable"]
pub type CC2E_R = crate :: BitReader ; # [doc = "Field `CC2E` writer - Capture/Compare 2 output enable"]
pub type CC2E_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2P` reader - Capture/Compare 2 output Polarity"]
pub type CC2P_R = crate :: BitReader ; # [doc = "Field `CC2P` writer - Capture/Compare 2 output Polarity"]
pub type CC2P_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2NE` reader - Capture/Compare 2 complementary output enable"]
pub type CC2NE_R = crate :: BitReader ; # [doc = "Field `CC2NE` writer - Capture/Compare 2 complementary output enable"]
pub type CC2NE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2NP` reader - Capture/Compare 2 output Polarity"]
pub type CC2NP_R = crate :: BitReader ; # [doc = "Field `CC2NP` writer - Capture/Compare 2 output Polarity"]
pub type CC2NP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3E` reader - Capture/Compare 3 output enable"]
pub type CC3E_R = crate :: BitReader ; # [doc = "Field `CC3E` writer - Capture/Compare 3 output enable"]
pub type CC3E_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3P` reader - Capture/Compare 3 output Polarity"]
pub type CC3P_R = crate :: BitReader ; # [doc = "Field `CC3P` writer - Capture/Compare 3 output Polarity"]
pub type CC3P_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3NE` reader - Capture/Compare 3 complementary output enable"]
pub type CC3NE_R = crate :: BitReader ; # [doc = "Field `CC3NE` writer - Capture/Compare 3 complementary output enable"]
pub type CC3NE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3NP` reader - Capture/Compare 3 output Polarity"]
pub type CC3NP_R = crate :: BitReader ; # [doc = "Field `CC3NP` writer - Capture/Compare 3 output Polarity"]
pub type CC3NP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4E` reader - Capture/Compare 4 output enable"]
pub type CC4E_R = crate :: BitReader ; # [doc = "Field `CC4E` writer - Capture/Compare 4 output enable"]
pub type CC4E_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4P` reader - Capture/Compare 3 output Polarity"]
pub type CC4P_R = crate :: BitReader ; # [doc = "Field `CC4P` writer - Capture/Compare 3 output Polarity"]
pub type CC4P_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture/Compare 1 output enable"]
# [inline (always)]
pub fn cc1e (& self) -> CC1E_R { CC1E_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture/Compare 1 output Polarity"]
# [inline (always)]
pub fn cc1p (& self) -> CC1P_R { CC1P_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Capture/Compare 1 complementary output enable"]
# [inline (always)]
pub fn cc1ne (& self) -> CC1NE_R { CC1NE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Capture/Compare 1 output Polarity"]
# [inline (always)]
pub fn cc1np (& self) -> CC1NP_R { CC1NP_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Capture/Compare 2 output enable"]
# [inline (always)]
pub fn cc2e (& self) -> CC2E_R { CC2E_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture/Compare 2 output Polarity"]
# [inline (always)]
pub fn cc2p (& self) -> CC2P_R { CC2P_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Capture/Compare 2 complementary output enable"]
# [inline (always)]
pub fn cc2ne (& self) -> CC2NE_R { CC2NE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Capture/Compare 2 output Polarity"]
# [inline (always)]
pub fn cc2np (& self) -> CC2NP_R { CC2NP_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Capture/Compare 3 output enable"]
# [inline (always)]
pub fn cc3e (& self) -> CC3E_R { CC3E_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture/Compare 3 output Polarity"]
# [inline (always)]
pub fn cc3p (& self) -> CC3P_R { CC3P_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Capture/Compare 3 complementary output enable"]
# [inline (always)]
pub fn cc3ne (& self) -> CC3NE_R { CC3NE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Capture/Compare 3 output Polarity"]
# [inline (always)]
pub fn cc3np (& self) -> CC3NP_R { CC3NP_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Capture/Compare 4 output enable"]
# [inline (always)]
pub fn cc4e (& self) -> CC4E_R { CC4E_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Capture/Compare 3 output Polarity"]
# [inline (always)]
pub fn cc4p (& self) -> CC4P_R { CC4P_R :: new (((self . bits >> 13) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture/Compare 1 output enable"]
# [inline (always)]
# [must_use]
pub fn cc1e (& mut self) -> CC1E_W < CCER_SPEC > { CC1E_W :: new (self , 0) } # [doc = "Bit 1 - Capture/Compare 1 output Polarity"]
# [inline (always)]
# [must_use]
pub fn cc1p (& mut self) -> CC1P_W < CCER_SPEC > { CC1P_W :: new (self , 1) } # [doc = "Bit 2 - Capture/Compare 1 complementary output enable"]
# [inline (always)]
# [must_use]
pub fn cc1ne (& mut self) -> CC1NE_W < CCER_SPEC > { CC1NE_W :: new (self , 2) } # [doc = "Bit 3 - Capture/Compare 1 output Polarity"]
# [inline (always)]
# [must_use]
pub fn cc1np (& mut self) -> CC1NP_W < CCER_SPEC > { CC1NP_W :: new (self , 3) } # [doc = "Bit 4 - Capture/Compare 2 output enable"]
# [inline (always)]
# [must_use]
pub fn cc2e (& mut self) -> CC2E_W < CCER_SPEC > { CC2E_W :: new (self , 4) } # [doc = "Bit 5 - Capture/Compare 2 output Polarity"]
# [inline (always)]
# [must_use]
pub fn cc2p (& mut self) -> CC2P_W < CCER_SPEC > { CC2P_W :: new (self , 5) } # [doc = "Bit 6 - Capture/Compare 2 complementary output enable"]
# [inline (always)]
# [must_use]
pub fn cc2ne (& mut self) -> CC2NE_W < CCER_SPEC > { CC2NE_W :: new (self , 6) } # [doc = "Bit 7 - Capture/Compare 2 output Polarity"]
# [inline (always)]
# [must_use]
pub fn cc2np (& mut self) -> CC2NP_W < CCER_SPEC > { CC2NP_W :: new (self , 7) } # [doc = "Bit 8 - Capture/Compare 3 output enable"]
# [inline (always)]
# [must_use]
pub fn cc3e (& mut self) -> CC3E_W < CCER_SPEC > { CC3E_W :: new (self , 8) } # [doc = "Bit 9 - Capture/Compare 3 output Polarity"]
# [inline (always)]
# [must_use]
pub fn cc3p (& mut self) -> CC3P_W < CCER_SPEC > { CC3P_W :: new (self , 9) } # [doc = "Bit 10 - Capture/Compare 3 complementary output enable"]
# [inline (always)]
# [must_use]
pub fn cc3ne (& mut self) -> CC3NE_W < CCER_SPEC > { CC3NE_W :: new (self , 10) } # [doc = "Bit 11 - Capture/Compare 3 output Polarity"]
# [inline (always)]
# [must_use]
pub fn cc3np (& mut self) -> CC3NP_W < CCER_SPEC > { CC3NP_W :: new (self , 11) } # [doc = "Bit 12 - Capture/Compare 4 output enable"]
# [inline (always)]
# [must_use]
pub fn cc4e (& mut self) -> CC4E_W < CCER_SPEC > { CC4E_W :: new (self , 12) } # [doc = "Bit 13 - Capture/Compare 3 output Polarity"]
# [inline (always)]
# [must_use]
pub fn cc4p (& mut self) -> CC4P_W < CCER_SPEC > { CC4P_W :: new (self , 13) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccer::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccer::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCER_SPEC ; impl crate :: RegisterSpec for CCER_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccer::R`](R) reader structure"]
impl crate :: Readable for CCER_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccer::W`](W) writer structure"]
impl crate :: Writable for CCER_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CCER to value 0"]
impl crate :: Resettable for CCER_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CNT (rw) register accessor: counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`]
module"]
pub type CNT = crate :: Reg < cnt :: CNT_SPEC > ; # [doc = "counter"]
pub mod cnt { # [doc = "Register `CNT` reader"]
pub type R = crate :: R < CNT_SPEC > ; # [doc = "Register `CNT` writer"]
pub type W = crate :: W < CNT_SPEC > ; # [doc = "Field `CNT` reader - counter value"]
pub type CNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `CNT` writer - counter value"]
pub type CNT_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - counter value"]
# [inline (always)]
pub fn cnt (& self) -> CNT_R { CNT_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - counter value"]
# [inline (always)]
# [must_use]
pub fn cnt (& mut self) -> CNT_W < CNT_SPEC > { CNT_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CNT_SPEC ; impl crate :: RegisterSpec for CNT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cnt::R`](R) reader structure"]
impl crate :: Readable for CNT_SPEC { } # [doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
impl crate :: Writable for CNT_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CNT to value 0"]
impl crate :: Resettable for CNT_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSC (rw) register accessor: prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psc`]
module"]
pub type PSC = crate :: Reg < psc :: PSC_SPEC > ; # [doc = "prescaler"]
pub mod psc { # [doc = "Register `PSC` reader"]
pub type R = crate :: R < PSC_SPEC > ; # [doc = "Register `PSC` writer"]
pub type W = crate :: W < PSC_SPEC > ; # [doc = "Field `PSC` reader - Prescaler value"]
pub type PSC_R = crate :: FieldReader < u16 > ; # [doc = "Field `PSC` writer - Prescaler value"]
pub type PSC_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Prescaler value"]
# [inline (always)]
pub fn psc (& self) -> PSC_R { PSC_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Prescaler value"]
# [inline (always)]
# [must_use]
pub fn psc (& mut self) -> PSC_W < PSC_SPEC > { PSC_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PSC_SPEC ; impl crate :: RegisterSpec for PSC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`psc::R`](R) reader structure"]
impl crate :: Readable for PSC_SPEC { } # [doc = "`write(|w| ..)` method takes [`psc::W`](W) writer structure"]
impl crate :: Writable for PSC_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSC to value 0"]
impl crate :: Resettable for PSC_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "ATRLR (rw) register accessor: auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atrlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atrlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@atrlr`]
module"]
pub type ATRLR = crate :: Reg < atrlr :: ATRLR_SPEC > ; # [doc = "auto-reload register"]
pub mod atrlr { # [doc = "Register `ATRLR` reader"]
pub type R = crate :: R < ATRLR_SPEC > ; # [doc = "Register `ATRLR` writer"]
pub type W = crate :: W < ATRLR_SPEC > ; # [doc = "Field `ARR` reader - Auto-reload value"]
pub type ARR_R = crate :: FieldReader < u16 > ; # [doc = "Field `ARR` writer - Auto-reload value"]
pub type ARR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Auto-reload value"]
# [inline (always)]
pub fn arr (& self) -> ARR_R { ARR_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Auto-reload value"]
# [inline (always)]
# [must_use]
pub fn arr (& mut self) -> ARR_W < ATRLR_SPEC > { ARR_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atrlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atrlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ATRLR_SPEC ; impl crate :: RegisterSpec for ATRLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`atrlr::R`](R) reader structure"]
impl crate :: Readable for ATRLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`atrlr::W`](W) writer structure"]
impl crate :: Writable for ATRLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ATRLR to value 0"]
impl crate :: Resettable for ATRLR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH1CVR (rw) register accessor: capture/compare register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1cvr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1cvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1cvr`]
module"]
pub type CH1CVR = crate :: Reg < ch1cvr :: CH1CVR_SPEC > ; # [doc = "capture/compare register 1"]
pub mod ch1cvr { # [doc = "Register `CH1CVR` reader"]
pub type R = crate :: R < CH1CVR_SPEC > ; # [doc = "Register `CH1CVR` writer"]
pub type W = crate :: W < CH1CVR_SPEC > ; # [doc = "Field `CCR1` reader - Capture/Compare 1 value"]
pub type CCR1_R = crate :: FieldReader < u16 > ; # [doc = "Field `CCR1` writer - Capture/Compare 1 value"]
pub type CCR1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Capture/Compare 1 value"]
# [inline (always)]
pub fn ccr1 (& self) -> CCR1_R { CCR1_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Capture/Compare 1 value"]
# [inline (always)]
# [must_use]
pub fn ccr1 (& mut self) -> CCR1_W < CH1CVR_SPEC > { CCR1_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1cvr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1cvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CH1CVR_SPEC ; impl crate :: RegisterSpec for CH1CVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ch1cvr::R`](R) reader structure"]
impl crate :: Readable for CH1CVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ch1cvr::W`](W) writer structure"]
impl crate :: Writable for CH1CVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH1CVR to value 0"]
impl crate :: Resettable for CH1CVR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH2CVR (rw) register accessor: capture/compare register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2cvr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2cvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2cvr`]
module"]
pub type CH2CVR = crate :: Reg < ch2cvr :: CH2CVR_SPEC > ; # [doc = "capture/compare register 2"]
pub mod ch2cvr { # [doc = "Register `CH2CVR` reader"]
pub type R = crate :: R < CH2CVR_SPEC > ; # [doc = "Register `CH2CVR` writer"]
pub type W = crate :: W < CH2CVR_SPEC > ; # [doc = "Field `CCR2` reader - Capture/Compare 2 value"]
pub type CCR2_R = crate :: FieldReader < u16 > ; # [doc = "Field `CCR2` writer - Capture/Compare 2 value"]
pub type CCR2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Capture/Compare 2 value"]
# [inline (always)]
pub fn ccr2 (& self) -> CCR2_R { CCR2_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Capture/Compare 2 value"]
# [inline (always)]
# [must_use]
pub fn ccr2 (& mut self) -> CCR2_W < CH2CVR_SPEC > { CCR2_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2cvr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2cvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CH2CVR_SPEC ; impl crate :: RegisterSpec for CH2CVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ch2cvr::R`](R) reader structure"]
impl crate :: Readable for CH2CVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ch2cvr::W`](W) writer structure"]
impl crate :: Writable for CH2CVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH2CVR to value 0"]
impl crate :: Resettable for CH2CVR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH3CVR (rw) register accessor: capture/compare register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3cvr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3cvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3cvr`]
module"]
pub type CH3CVR = crate :: Reg < ch3cvr :: CH3CVR_SPEC > ; # [doc = "capture/compare register 3"]
pub mod ch3cvr { # [doc = "Register `CH3CVR` reader"]
pub type R = crate :: R < CH3CVR_SPEC > ; # [doc = "Register `CH3CVR` writer"]
pub type W = crate :: W < CH3CVR_SPEC > ; # [doc = "Field `CCR3` reader - Capture/Compare value"]
pub type CCR3_R = crate :: FieldReader < u16 > ; # [doc = "Field `CCR3` writer - Capture/Compare value"]
pub type CCR3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Capture/Compare value"]
# [inline (always)]
pub fn ccr3 (& self) -> CCR3_R { CCR3_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Capture/Compare value"]
# [inline (always)]
# [must_use]
pub fn ccr3 (& mut self) -> CCR3_W < CH3CVR_SPEC > { CCR3_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3cvr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3cvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CH3CVR_SPEC ; impl crate :: RegisterSpec for CH3CVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ch3cvr::R`](R) reader structure"]
impl crate :: Readable for CH3CVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ch3cvr::W`](W) writer structure"]
impl crate :: Writable for CH3CVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH3CVR to value 0"]
impl crate :: Resettable for CH3CVR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH4CVR (rw) register accessor: capture/compare register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4cvr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4cvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4cvr`]
module"]
pub type CH4CVR = crate :: Reg < ch4cvr :: CH4CVR_SPEC > ; # [doc = "capture/compare register 4"]
pub mod ch4cvr { # [doc = "Register `CH4CVR` reader"]
pub type R = crate :: R < CH4CVR_SPEC > ; # [doc = "Register `CH4CVR` writer"]
pub type W = crate :: W < CH4CVR_SPEC > ; # [doc = "Field `CCR4` reader - Capture/Compare value"]
pub type CCR4_R = crate :: FieldReader < u16 > ; # [doc = "Field `CCR4` writer - Capture/Compare value"]
pub type CCR4_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Capture/Compare value"]
# [inline (always)]
pub fn ccr4 (& self) -> CCR4_R { CCR4_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Capture/Compare value"]
# [inline (always)]
# [must_use]
pub fn ccr4 (& mut self) -> CCR4_W < CH4CVR_SPEC > { CCR4_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4cvr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4cvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CH4CVR_SPEC ; impl crate :: RegisterSpec for CH4CVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ch4cvr::R`](R) reader structure"]
impl crate :: Readable for CH4CVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ch4cvr::W`](W) writer structure"]
impl crate :: Writable for CH4CVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH4CVR to value 0"]
impl crate :: Resettable for CH4CVR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DMACFGR (rw) register accessor: DMA control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacfgr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmacfgr`]
module"]
pub type DMACFGR = crate :: Reg < dmacfgr :: DMACFGR_SPEC > ; # [doc = "DMA control register"]
pub mod dmacfgr { # [doc = "Register `DMACFGR` reader"]
pub type R = crate :: R < DMACFGR_SPEC > ; # [doc = "Register `DMACFGR` writer"]
pub type W = crate :: W < DMACFGR_SPEC > ; # [doc = "Field `DBA` reader - DMA base address"]
pub type DBA_R = crate :: FieldReader ; # [doc = "Field `DBA` writer - DMA base address"]
pub type DBA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `DBL` reader - DMA burst length"]
pub type DBL_R = crate :: FieldReader ; # [doc = "Field `DBL` writer - DMA burst length"]
pub type DBL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bits 0:4 - DMA base address"]
# [inline (always)]
pub fn dba (& self) -> DBA_R { DBA_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 8:12 - DMA burst length"]
# [inline (always)]
pub fn dbl (& self) -> DBL_R { DBL_R :: new (((self . bits >> 8) & 0x1f) as u8) } } impl W { # [doc = "Bits 0:4 - DMA base address"]
# [inline (always)]
# [must_use]
pub fn dba (& mut self) -> DBA_W < DMACFGR_SPEC > { DBA_W :: new (self , 0) } # [doc = "Bits 8:12 - DMA burst length"]
# [inline (always)]
# [must_use]
pub fn dbl (& mut self) -> DBL_W < DMACFGR_SPEC > { DBL_W :: new (self , 8) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacfgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMACFGR_SPEC ; impl crate :: RegisterSpec for DMACFGR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dmacfgr::R`](R) reader structure"]
impl crate :: Readable for DMACFGR_SPEC { } # [doc = "`write(|w| ..)` method takes [`dmacfgr::W`](W) writer structure"]
impl crate :: Writable for DMACFGR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DMACFGR to value 0"]
impl crate :: Resettable for DMACFGR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DMAR (rw) register accessor: DMA address for full transfer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmar::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmar`]
module"]
pub type DMAR = crate :: Reg < dmar :: DMAR_SPEC > ; # [doc = "DMA address for full transfer"]
pub mod dmar { # [doc = "Register `DMAR` reader"]
pub type R = crate :: R < DMAR_SPEC > ; # [doc = "Register `DMAR` writer"]
pub type W = crate :: W < DMAR_SPEC > ; # [doc = "Field `DMAB` reader - DMA register for burst accesses"]
pub type DMAB_R = crate :: FieldReader < u16 > ; # [doc = "Field `DMAB` writer - DMA register for burst accesses"]
pub type DMAB_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - DMA register for burst accesses"]
# [inline (always)]
pub fn dmab (& self) -> DMAB_R { DMAB_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - DMA register for burst accesses"]
# [inline (always)]
# [must_use]
pub fn dmab (& mut self) -> DMAB_W < DMAR_SPEC > { DMAB_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA address for full transfer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMAR_SPEC ; impl crate :: RegisterSpec for DMAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dmar::R`](R) reader structure"]
impl crate :: Readable for DMAR_SPEC { } # [doc = "`write(|w| ..)` method takes [`dmar::W`](W) writer structure"]
impl crate :: Writable for DMAR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DMAR to value 0"]
impl crate :: Resettable for DMAR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "RPTCR (rw) register accessor: repetition counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rptcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rptcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rptcr`]
module"]
pub type RPTCR = crate :: Reg < rptcr :: RPTCR_SPEC > ; # [doc = "repetition counter register"]
pub mod rptcr { # [doc = "Register `RPTCR` reader"]
pub type R = crate :: R < RPTCR_SPEC > ; # [doc = "Register `RPTCR` writer"]
pub type W = crate :: W < RPTCR_SPEC > ; # [doc = "Field `REP` reader - Repetition counter value"]
pub type REP_R = crate :: FieldReader ; # [doc = "Field `REP` writer - Repetition counter value"]
pub type REP_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - Repetition counter value"]
# [inline (always)]
pub fn rep (& self) -> REP_R { REP_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Repetition counter value"]
# [inline (always)]
# [must_use]
pub fn rep (& mut self) -> REP_W < RPTCR_SPEC > { REP_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "repetition counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rptcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rptcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RPTCR_SPEC ; impl crate :: RegisterSpec for RPTCR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rptcr::R`](R) reader structure"]
impl crate :: Readable for RPTCR_SPEC { } # [doc = "`write(|w| ..)` method takes [`rptcr::W`](W) writer structure"]
impl crate :: Writable for RPTCR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RPTCR to value 0"]
impl crate :: Resettable for RPTCR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "BDTR (rw) register accessor: break and dead-time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bdtr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bdtr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bdtr`]
module"]
pub type BDTR = crate :: Reg < bdtr :: BDTR_SPEC > ; # [doc = "break and dead-time register"]
pub mod bdtr { # [doc = "Register `BDTR` reader"]
pub type R = crate :: R < BDTR_SPEC > ; # [doc = "Register `BDTR` writer"]
pub type W = crate :: W < BDTR_SPEC > ; # [doc = "Field `DTG` reader - Dead-time generator setup"]
pub type DTG_R = crate :: FieldReader ; # [doc = "Field `DTG` writer - Dead-time generator setup"]
pub type DTG_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `LOCK` reader - Lock configuration"]
pub type LOCK_R = crate :: FieldReader ; # [doc = "Field `LOCK` writer - Lock configuration"]
pub type LOCK_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `OSSI` reader - Off-state selection for Idle mode"]
pub type OSSI_R = crate :: BitReader ; # [doc = "Field `OSSI` writer - Off-state selection for Idle mode"]
pub type OSSI_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OSSR` reader - Off-state selection for Run mode"]
pub type OSSR_R = crate :: BitReader ; # [doc = "Field `OSSR` writer - Off-state selection for Run mode"]
pub type OSSR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BKE` reader - Break enable"]
pub type BKE_R = crate :: BitReader ; # [doc = "Field `BKE` writer - Break enable"]
pub type BKE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BKP` reader - Break polarity"]
pub type BKP_R = crate :: BitReader ; # [doc = "Field `BKP` writer - Break polarity"]
pub type BKP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `AOE` reader - Automatic output enable"]
pub type AOE_R = crate :: BitReader ; # [doc = "Field `AOE` writer - Automatic output enable"]
pub type AOE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MOE` reader - Main output enable"]
pub type MOE_R = crate :: BitReader ; # [doc = "Field `MOE` writer - Main output enable"]
pub type MOE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:7 - Dead-time generator setup"]
# [inline (always)]
pub fn dtg (& self) -> DTG_R { DTG_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:9 - Lock configuration"]
# [inline (always)]
pub fn lock (& self) -> LOCK_R { LOCK_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 10 - Off-state selection for Idle mode"]
# [inline (always)]
pub fn ossi (& self) -> OSSI_R { OSSI_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Off-state selection for Run mode"]
# [inline (always)]
pub fn ossr (& self) -> OSSR_R { OSSR_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Break enable"]
# [inline (always)]
pub fn bke (& self) -> BKE_R { BKE_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Break polarity"]
# [inline (always)]
pub fn bkp (& self) -> BKP_R { BKP_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Automatic output enable"]
# [inline (always)]
pub fn aoe (& self) -> AOE_R { AOE_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Main output enable"]
# [inline (always)]
pub fn moe (& self) -> MOE_R { MOE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:7 - Dead-time generator setup"]
# [inline (always)]
# [must_use]
pub fn dtg (& mut self) -> DTG_W < BDTR_SPEC > { DTG_W :: new (self , 0) } # [doc = "Bits 8:9 - Lock configuration"]
# [inline (always)]
# [must_use]
pub fn lock (& mut self) -> LOCK_W < BDTR_SPEC > { LOCK_W :: new (self , 8) } # [doc = "Bit 10 - Off-state selection for Idle mode"]
# [inline (always)]
# [must_use]
pub fn ossi (& mut self) -> OSSI_W < BDTR_SPEC > { OSSI_W :: new (self , 10) } # [doc = "Bit 11 - Off-state selection for Run mode"]
# [inline (always)]
# [must_use]
pub fn ossr (& mut self) -> OSSR_W < BDTR_SPEC > { OSSR_W :: new (self , 11) } # [doc = "Bit 12 - Break enable"]
# [inline (always)]
# [must_use]
pub fn bke (& mut self) -> BKE_W < BDTR_SPEC > { BKE_W :: new (self , 12) } # [doc = "Bit 13 - Break polarity"]
# [inline (always)]
# [must_use]
pub fn bkp (& mut self) -> BKP_W < BDTR_SPEC > { BKP_W :: new (self , 13) } # [doc = "Bit 14 - Automatic output enable"]
# [inline (always)]
# [must_use]
pub fn aoe (& mut self) -> AOE_W < BDTR_SPEC > { AOE_W :: new (self , 14) } # [doc = "Bit 15 - Main output enable"]
# [inline (always)]
# [must_use]
pub fn moe (& mut self) -> MOE_W < BDTR_SPEC > { MOE_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "break and dead-time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bdtr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bdtr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BDTR_SPEC ; impl crate :: RegisterSpec for BDTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`bdtr::R`](R) reader structure"]
impl crate :: Readable for BDTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`bdtr::W`](W) writer structure"]
impl crate :: Writable for BDTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets BDTR to value 0"]
impl crate :: Resettable for BDTR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "General purpose timer"]
pub struct TIM2 { _marker : PhantomData < * const () > } unsafe impl Send for TIM2 { } impl TIM2 { # [doc = r"Pointer to the register block"]
pub const PTR : * const tim2 :: RegisterBlock = 0x4000_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const tim2 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TIM2 { type Target = tim2 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TIM2 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TIM2") . finish () } } # [doc = "General purpose timer"]
pub mod tim2 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { ctlr1 : CTLR1 , ctlr2 : CTLR2 , smcfgr : SMCFGR , dmaintenr : DMAINTENR , intfr : INTFR , swevgr : SWEVGR , _reserved_6_chctlr1 : [u8 ; 0x04]
, _reserved_7_chctlr2 : [u8 ; 0x04]
, ccer : CCER , cnt : CNT , psc : PSC , atrlr : ATRLR , _reserved12 : [u8 ; 0x04]
, ch1cvr : CH1CVR , ch2cvr : CH2CVR , ch3cvr : CH3CVR , ch4cvr : CH4CVR , _reserved16 : [u8 ; 0x04]
, dmacfgr : DMACFGR , dmar : DMAR , } impl RegisterBlock { # [doc = "0x00 - control register 1"]
# [inline (always)]
pub const fn ctlr1 (& self) -> & CTLR1 { & self . ctlr1 } # [doc = "0x04 - control register 2"]
# [inline (always)]
pub const fn ctlr2 (& self) -> & CTLR2 { & self . ctlr2 } # [doc = "0x08 - slave mode control register"]
# [inline (always)]
pub const fn smcfgr (& self) -> & SMCFGR { & self . smcfgr } # [doc = "0x0c - DMA/Interrupt enable register"]
# [inline (always)]
pub const fn dmaintenr (& self) -> & DMAINTENR { & self . dmaintenr } # [doc = "0x10 - status register"]
# [inline (always)]
pub const fn intfr (& self) -> & INTFR { & self . intfr } # [doc = "0x14 - event generation register"]
# [inline (always)]
pub const fn swevgr (& self) -> & SWEVGR { & self . swevgr } # [doc = "0x18 - capture/compare mode register 1 (input mode)"]
# [inline (always)]
pub const fn chctlr1_input (& self) -> & CHCTLR1_INPUT { unsafe { & * (self as * const Self) . cast :: < u8 > () . add (24) . cast () } } # [doc = "0x18 - capture/compare mode register 1 (output mode)"]
# [inline (always)]
pub const fn chctlr1_output (& self) -> & CHCTLR1_OUTPUT { unsafe { & * (self as * const Self) . cast :: < u8 > () . add (24) . cast () } } # [doc = "0x1c - capture/compare mode register 2 (input mode)"]
# [inline (always)]
pub const fn chctlr2_input (& self) -> & CHCTLR2_INPUT { unsafe { & * (self as * const Self) . cast :: < u8 > () . add (28) . cast () } } # [doc = "0x1c - capture/compare mode register 2 (output mode)"]
# [inline (always)]
pub const fn chctlr2_output (& self) -> & CHCTLR2_OUTPUT { unsafe { & * (self as * const Self) . cast :: < u8 > () . add (28) . cast () } } # [doc = "0x20 - capture/compare enable register"]
# [inline (always)]
pub const fn ccer (& self) -> & CCER { & self . ccer } # [doc = "0x24 - counter"]
# [inline (always)]
pub const fn cnt (& self) -> & CNT { & self . cnt } # [doc = "0x28 - prescaler"]
# [inline (always)]
pub const fn psc (& self) -> & PSC { & self . psc } # [doc = "0x2c - auto-reload register"]
# [inline (always)]
pub const fn atrlr (& self) -> & ATRLR { & self . atrlr } # [doc = "0x34 - capture/compare register 1"]
# [inline (always)]
pub const fn ch1cvr (& self) -> & CH1CVR { & self . ch1cvr } # [doc = "0x38 - capture/compare register 2"]
# [inline (always)]
pub const fn ch2cvr (& self) -> & CH2CVR { & self . ch2cvr } # [doc = "0x3c - capture/compare register 3"]
# [inline (always)]
pub const fn ch3cvr (& self) -> & CH3CVR { & self . ch3cvr } # [doc = "0x40 - capture/compare register 4"]
# [inline (always)]
pub const fn ch4cvr (& self) -> & CH4CVR { & self . ch4cvr } # [doc = "0x48 - DMA control register"]
# [inline (always)]
pub const fn dmacfgr (& self) -> & DMACFGR { & self . dmacfgr } # [doc = "0x4c - DMA address for full transfer"]
# [inline (always)]
pub const fn dmar (& self) -> & DMAR { & self . dmar } } # [doc = "CTLR1 (rw) register accessor: control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr1`]
module"]
pub type CTLR1 = crate :: Reg < ctlr1 :: CTLR1_SPEC > ; # [doc = "control register 1"]
pub mod ctlr1 { # [doc = "Register `CTLR1` reader"]
pub type R = crate :: R < CTLR1_SPEC > ; # [doc = "Register `CTLR1` writer"]
pub type W = crate :: W < CTLR1_SPEC > ; # [doc = "Field `CEN` reader - Counter enable"]
pub type CEN_R = crate :: BitReader ; # [doc = "Field `CEN` writer - Counter enable"]
pub type CEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `UDIS` reader - Update disable"]
pub type UDIS_R = crate :: BitReader ; # [doc = "Field `UDIS` writer - Update disable"]
pub type UDIS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `URS` reader - Update request source"]
pub type URS_R = crate :: BitReader ; # [doc = "Field `URS` writer - Update request source"]
pub type URS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OPM` reader - One-pulse mode"]
pub type OPM_R = crate :: BitReader ; # [doc = "Field `OPM` writer - One-pulse mode"]
pub type OPM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DIR` reader - Direction"]
pub type DIR_R = crate :: BitReader ; # [doc = "Field `DIR` writer - Direction"]
pub type DIR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CMS` reader - Center-aligned mode selection"]
pub type CMS_R = crate :: FieldReader ; # [doc = "Field `CMS` writer - Center-aligned mode selection"]
pub type CMS_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ARPE` reader - Auto-reload preload enable"]
pub type ARPE_R = crate :: BitReader ; # [doc = "Field `ARPE` writer - Auto-reload preload enable"]
pub type ARPE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CKD` reader - Clock division"]
pub type CKD_R = crate :: FieldReader ; # [doc = "Field `CKD` writer - Clock division"]
pub type CKD_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bit 0 - Counter enable"]
# [inline (always)]
pub fn cen (& self) -> CEN_R { CEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Update disable"]
# [inline (always)]
pub fn udis (& self) -> UDIS_R { UDIS_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Update request source"]
# [inline (always)]
pub fn urs (& self) -> URS_R { URS_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - One-pulse mode"]
# [inline (always)]
pub fn opm (& self) -> OPM_R { OPM_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Direction"]
# [inline (always)]
pub fn dir (& self) -> DIR_R { DIR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:6 - Center-aligned mode selection"]
# [inline (always)]
pub fn cms (& self) -> CMS_R { CMS_R :: new (((self . bits >> 5) & 3) as u8) } # [doc = "Bit 7 - Auto-reload preload enable"]
# [inline (always)]
pub fn arpe (& self) -> ARPE_R { ARPE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Clock division"]
# [inline (always)]
pub fn ckd (& self) -> CKD_R { CKD_R :: new (((self . bits >> 8) & 3) as u8) } } impl W { # [doc = "Bit 0 - Counter enable"]
# [inline (always)]
# [must_use]
pub fn cen (& mut self) -> CEN_W < CTLR1_SPEC > { CEN_W :: new (self , 0) } # [doc = "Bit 1 - Update disable"]
# [inline (always)]
# [must_use]
pub fn udis (& mut self) -> UDIS_W < CTLR1_SPEC > { UDIS_W :: new (self , 1) } # [doc = "Bit 2 - Update request source"]
# [inline (always)]
# [must_use]
pub fn urs (& mut self) -> URS_W < CTLR1_SPEC > { URS_W :: new (self , 2) } # [doc = "Bit 3 - One-pulse mode"]
# [inline (always)]
# [must_use]
pub fn opm (& mut self) -> OPM_W < CTLR1_SPEC > { OPM_W :: new (self , 3) } # [doc = "Bit 4 - Direction"]
# [inline (always)]
# [must_use]
pub fn dir (& mut self) -> DIR_W < CTLR1_SPEC > { DIR_W :: new (self , 4) } # [doc = "Bits 5:6 - Center-aligned mode selection"]
# [inline (always)]
# [must_use]
pub fn cms (& mut self) -> CMS_W < CTLR1_SPEC > { CMS_W :: new (self , 5) } # [doc = "Bit 7 - Auto-reload preload enable"]
# [inline (always)]
# [must_use]
pub fn arpe (& mut self) -> ARPE_W < CTLR1_SPEC > { ARPE_W :: new (self , 7) } # [doc = "Bits 8:9 - Clock division"]
# [inline (always)]
# [must_use]
pub fn ckd (& mut self) -> CKD_W < CTLR1_SPEC > { CKD_W :: new (self , 8) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR1_SPEC ; impl crate :: RegisterSpec for CTLR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr1::R`](R) reader structure"]
impl crate :: Readable for CTLR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr1::W`](W) writer structure"]
impl crate :: Writable for CTLR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR1 to value 0"]
impl crate :: Resettable for CTLR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTLR2 (rw) register accessor: control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr2`]
module"]
pub type CTLR2 = crate :: Reg < ctlr2 :: CTLR2_SPEC > ; # [doc = "control register 2"]
pub mod ctlr2 { # [doc = "Register `CTLR2` reader"]
pub type R = crate :: R < CTLR2_SPEC > ; # [doc = "Register `CTLR2` writer"]
pub type W = crate :: W < CTLR2_SPEC > ; # [doc = "Field `CCPC` reader - Capture/compare preloaded control"]
pub type CCPC_R = crate :: BitReader ; # [doc = "Field `CCPC` writer - Capture/compare preloaded control"]
pub type CCPC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CCUS` reader - Capture/compare control update selection"]
pub type CCUS_R = crate :: BitReader ; # [doc = "Field `CCUS` writer - Capture/compare control update selection"]
pub type CCUS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CCDS` reader - Capture/compare DMA selection"]
pub type CCDS_R = crate :: BitReader ; # [doc = "Field `CCDS` writer - Capture/compare DMA selection"]
pub type CCDS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MMS` reader - Master mode selection"]
pub type MMS_R = crate :: FieldReader ; # [doc = "Field `MMS` writer - Master mode selection"]
pub type MMS_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TI1S` reader - TI1 selection"]
pub type TI1S_R = crate :: BitReader ; # [doc = "Field `TI1S` writer - TI1 selection"]
pub type TI1S_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture/compare preloaded control"]
# [inline (always)]
pub fn ccpc (& self) -> CCPC_R { CCPC_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - Capture/compare control update selection"]
# [inline (always)]
pub fn ccus (& self) -> CCUS_R { CCUS_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Capture/compare DMA selection"]
# [inline (always)]
pub fn ccds (& self) -> CCDS_R { CCDS_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - Master mode selection"]
# [inline (always)]
pub fn mms (& self) -> MMS_R { MMS_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - TI1 selection"]
# [inline (always)]
pub fn ti1s (& self) -> TI1S_R { TI1S_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture/compare preloaded control"]
# [inline (always)]
# [must_use]
pub fn ccpc (& mut self) -> CCPC_W < CTLR2_SPEC > { CCPC_W :: new (self , 0) } # [doc = "Bit 2 - Capture/compare control update selection"]
# [inline (always)]
# [must_use]
pub fn ccus (& mut self) -> CCUS_W < CTLR2_SPEC > { CCUS_W :: new (self , 2) } # [doc = "Bit 3 - Capture/compare DMA selection"]
# [inline (always)]
# [must_use]
pub fn ccds (& mut self) -> CCDS_W < CTLR2_SPEC > { CCDS_W :: new (self , 3) } # [doc = "Bits 4:6 - Master mode selection"]
# [inline (always)]
# [must_use]
pub fn mms (& mut self) -> MMS_W < CTLR2_SPEC > { MMS_W :: new (self , 4) } # [doc = "Bit 7 - TI1 selection"]
# [inline (always)]
# [must_use]
pub fn ti1s (& mut self) -> TI1S_W < CTLR2_SPEC > { TI1S_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR2_SPEC ; impl crate :: RegisterSpec for CTLR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr2::R`](R) reader structure"]
impl crate :: Readable for CTLR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr2::W`](W) writer structure"]
impl crate :: Writable for CTLR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR2 to value 0"]
impl crate :: Resettable for CTLR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "SMCFGR (rw) register accessor: slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcfgr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smcfgr`]
module"]
pub type SMCFGR = crate :: Reg < smcfgr :: SMCFGR_SPEC > ; # [doc = "slave mode control register"]
pub mod smcfgr { # [doc = "Register `SMCFGR` reader"]
pub type R = crate :: R < SMCFGR_SPEC > ; # [doc = "Register `SMCFGR` writer"]
pub type W = crate :: W < SMCFGR_SPEC > ; # [doc = "Field `SMS` reader - Slave mode selection"]
pub type SMS_R = crate :: FieldReader ; # [doc = "Field `SMS` writer - Slave mode selection"]
pub type SMS_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `TS` reader - Trigger selection"]
pub type TS_R = crate :: FieldReader ; # [doc = "Field `TS` writer - Trigger selection"]
pub type TS_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `MSM` reader - Master/Slave mode"]
pub type MSM_R = crate :: BitReader ; # [doc = "Field `MSM` writer - Master/Slave mode"]
pub type MSM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ETF` reader - External trigger filter"]
pub type ETF_R = crate :: FieldReader ; # [doc = "Field `ETF` writer - External trigger filter"]
pub type ETF_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `ETPS` reader - External trigger prescaler"]
pub type ETPS_R = crate :: FieldReader ; # [doc = "Field `ETPS` writer - External trigger prescaler"]
pub type ETPS_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `ECE` reader - External clock enable"]
pub type ECE_R = crate :: BitReader ; # [doc = "Field `ECE` writer - External clock enable"]
pub type ECE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ETP` reader - External trigger polarity"]
pub type ETP_R = crate :: BitReader ; # [doc = "Field `ETP` writer - External trigger polarity"]
pub type ETP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:2 - Slave mode selection"]
# [inline (always)]
pub fn sms (& self) -> SMS_R { SMS_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Trigger selection"]
# [inline (always)]
pub fn ts (& self) -> TS_R { TS_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - Master/Slave mode"]
# [inline (always)]
pub fn msm (& self) -> MSM_R { MSM_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:11 - External trigger filter"]
# [inline (always)]
pub fn etf (& self) -> ETF_R { ETF_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:13 - External trigger prescaler"]
# [inline (always)]
pub fn etps (& self) -> ETPS_R { ETPS_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - External clock enable"]
# [inline (always)]
pub fn ece (& self) -> ECE_R { ECE_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - External trigger polarity"]
# [inline (always)]
pub fn etp (& self) -> ETP_R { ETP_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - Slave mode selection"]
# [inline (always)]
# [must_use]
pub fn sms (& mut self) -> SMS_W < SMCFGR_SPEC > { SMS_W :: new (self , 0) } # [doc = "Bits 4:6 - Trigger selection"]
# [inline (always)]
# [must_use]
pub fn ts (& mut self) -> TS_W < SMCFGR_SPEC > { TS_W :: new (self , 4) } # [doc = "Bit 7 - Master/Slave mode"]
# [inline (always)]
# [must_use]
pub fn msm (& mut self) -> MSM_W < SMCFGR_SPEC > { MSM_W :: new (self , 7) } # [doc = "Bits 8:11 - External trigger filter"]
# [inline (always)]
# [must_use]
pub fn etf (& mut self) -> ETF_W < SMCFGR_SPEC > { ETF_W :: new (self , 8) } # [doc = "Bits 12:13 - External trigger prescaler"]
# [inline (always)]
# [must_use]
pub fn etps (& mut self) -> ETPS_W < SMCFGR_SPEC > { ETPS_W :: new (self , 12) } # [doc = "Bit 14 - External clock enable"]
# [inline (always)]
# [must_use]
pub fn ece (& mut self) -> ECE_W < SMCFGR_SPEC > { ECE_W :: new (self , 14) } # [doc = "Bit 15 - External trigger polarity"]
# [inline (always)]
# [must_use]
pub fn etp (& mut self) -> ETP_W < SMCFGR_SPEC > { ETP_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcfgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SMCFGR_SPEC ; impl crate :: RegisterSpec for SMCFGR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`smcfgr::R`](R) reader structure"]
impl crate :: Readable for SMCFGR_SPEC { } # [doc = "`write(|w| ..)` method takes [`smcfgr::W`](W) writer structure"]
impl crate :: Writable for SMCFGR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SMCFGR to value 0"]
impl crate :: Resettable for SMCFGR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DMAINTENR (rw) register accessor: DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaintenr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaintenr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmaintenr`]
module"]
pub type DMAINTENR = crate :: Reg < dmaintenr :: DMAINTENR_SPEC > ; # [doc = "DMA/Interrupt enable register"]
pub mod dmaintenr { # [doc = "Register `DMAINTENR` reader"]
pub type R = crate :: R < DMAINTENR_SPEC > ; # [doc = "Register `DMAINTENR` writer"]
pub type W = crate :: W < DMAINTENR_SPEC > ; # [doc = "Field `UIE` reader - Update interrupt enable"]
pub type UIE_R = crate :: BitReader ; # [doc = "Field `UIE` writer - Update interrupt enable"]
pub type UIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1IE` reader - Capture/Compare 1 interrupt enable"]
pub type CC1IE_R = crate :: BitReader ; # [doc = "Field `CC1IE` writer - Capture/Compare 1 interrupt enable"]
pub type CC1IE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2IE` reader - Capture/Compare 2 interrupt enable"]
pub type CC2IE_R = crate :: BitReader ; # [doc = "Field `CC2IE` writer - Capture/Compare 2 interrupt enable"]
pub type CC2IE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3IE` reader - Capture/Compare 3 interrupt enable"]
pub type CC3IE_R = crate :: BitReader ; # [doc = "Field `CC3IE` writer - Capture/Compare 3 interrupt enable"]
pub type CC3IE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4IE` reader - Capture/Compare 4 interrupt enable"]
pub type CC4IE_R = crate :: BitReader ; # [doc = "Field `CC4IE` writer - Capture/Compare 4 interrupt enable"]
pub type CC4IE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIE` reader - Trigger interrupt enable"]
pub type TIE_R = crate :: BitReader ; # [doc = "Field `TIE` writer - Trigger interrupt enable"]
pub type TIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `UDE` reader - Update DMA request enable"]
pub type UDE_R = crate :: BitReader ; # [doc = "Field `UDE` writer - Update DMA request enable"]
pub type UDE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1DE` reader - Capture/Compare 1 DMA request enable"]
pub type CC1DE_R = crate :: BitReader ; # [doc = "Field `CC1DE` writer - Capture/Compare 1 DMA request enable"]
pub type CC1DE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2DE` reader - Capture/Compare 2 DMA request enable"]
pub type CC2DE_R = crate :: BitReader ; # [doc = "Field `CC2DE` writer - Capture/Compare 2 DMA request enable"]
pub type CC2DE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3DE` reader - Capture/Compare 3 DMA request enable"]
pub type CC3DE_R = crate :: BitReader ; # [doc = "Field `CC3DE` writer - Capture/Compare 3 DMA request enable"]
pub type CC3DE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4DE` reader - Capture/Compare 4 DMA request enable"]
pub type CC4DE_R = crate :: BitReader ; # [doc = "Field `CC4DE` writer - Capture/Compare 4 DMA request enable"]
pub type CC4DE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TDE` reader - Trigger DMA request enable"]
pub type TDE_R = crate :: BitReader ; # [doc = "Field `TDE` writer - Trigger DMA request enable"]
pub type TDE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Update interrupt enable"]
# [inline (always)]
pub fn uie (& self) -> UIE_R { UIE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture/Compare 1 interrupt enable"]
# [inline (always)]
pub fn cc1ie (& self) -> CC1IE_R { CC1IE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Capture/Compare 2 interrupt enable"]
# [inline (always)]
pub fn cc2ie (& self) -> CC2IE_R { CC2IE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Capture/Compare 3 interrupt enable"]
# [inline (always)]
pub fn cc3ie (& self) -> CC3IE_R { CC3IE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Capture/Compare 4 interrupt enable"]
# [inline (always)]
pub fn cc4ie (& self) -> CC4IE_R { CC4IE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 6 - Trigger interrupt enable"]
# [inline (always)]
pub fn tie (& self) -> TIE_R { TIE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - Update DMA request enable"]
# [inline (always)]
pub fn ude (& self) -> UDE_R { UDE_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture/Compare 1 DMA request enable"]
# [inline (always)]
pub fn cc1de (& self) -> CC1DE_R { CC1DE_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Capture/Compare 2 DMA request enable"]
# [inline (always)]
pub fn cc2de (& self) -> CC2DE_R { CC2DE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Capture/Compare 3 DMA request enable"]
# [inline (always)]
pub fn cc3de (& self) -> CC3DE_R { CC3DE_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Capture/Compare 4 DMA request enable"]
# [inline (always)]
pub fn cc4de (& self) -> CC4DE_R { CC4DE_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 14 - Trigger DMA request enable"]
# [inline (always)]
pub fn tde (& self) -> TDE_R { TDE_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bit 0 - Update interrupt enable"]
# [inline (always)]
# [must_use]
pub fn uie (& mut self) -> UIE_W < DMAINTENR_SPEC > { UIE_W :: new (self , 0) } # [doc = "Bit 1 - Capture/Compare 1 interrupt enable"]
# [inline (always)]
# [must_use]
pub fn cc1ie (& mut self) -> CC1IE_W < DMAINTENR_SPEC > { CC1IE_W :: new (self , 1) } # [doc = "Bit 2 - Capture/Compare 2 interrupt enable"]
# [inline (always)]
# [must_use]
pub fn cc2ie (& mut self) -> CC2IE_W < DMAINTENR_SPEC > { CC2IE_W :: new (self , 2) } # [doc = "Bit 3 - Capture/Compare 3 interrupt enable"]
# [inline (always)]
# [must_use]
pub fn cc3ie (& mut self) -> CC3IE_W < DMAINTENR_SPEC > { CC3IE_W :: new (self , 3) } # [doc = "Bit 4 - Capture/Compare 4 interrupt enable"]
# [inline (always)]
# [must_use]
pub fn cc4ie (& mut self) -> CC4IE_W < DMAINTENR_SPEC > { CC4IE_W :: new (self , 4) } # [doc = "Bit 6 - Trigger interrupt enable"]
# [inline (always)]
# [must_use]
pub fn tie (& mut self) -> TIE_W < DMAINTENR_SPEC > { TIE_W :: new (self , 6) } # [doc = "Bit 8 - Update DMA request enable"]
# [inline (always)]
# [must_use]
pub fn ude (& mut self) -> UDE_W < DMAINTENR_SPEC > { UDE_W :: new (self , 8) } # [doc = "Bit 9 - Capture/Compare 1 DMA request enable"]
# [inline (always)]
# [must_use]
pub fn cc1de (& mut self) -> CC1DE_W < DMAINTENR_SPEC > { CC1DE_W :: new (self , 9) } # [doc = "Bit 10 - Capture/Compare 2 DMA request enable"]
# [inline (always)]
# [must_use]
pub fn cc2de (& mut self) -> CC2DE_W < DMAINTENR_SPEC > { CC2DE_W :: new (self , 10) } # [doc = "Bit 11 - Capture/Compare 3 DMA request enable"]
# [inline (always)]
# [must_use]
pub fn cc3de (& mut self) -> CC3DE_W < DMAINTENR_SPEC > { CC3DE_W :: new (self , 11) } # [doc = "Bit 12 - Capture/Compare 4 DMA request enable"]
# [inline (always)]
# [must_use]
pub fn cc4de (& mut self) -> CC4DE_W < DMAINTENR_SPEC > { CC4DE_W :: new (self , 12) } # [doc = "Bit 14 - Trigger DMA request enable"]
# [inline (always)]
# [must_use]
pub fn tde (& mut self) -> TDE_W < DMAINTENR_SPEC > { TDE_W :: new (self , 14) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaintenr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaintenr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMAINTENR_SPEC ; impl crate :: RegisterSpec for DMAINTENR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dmaintenr::R`](R) reader structure"]
impl crate :: Readable for DMAINTENR_SPEC { } # [doc = "`write(|w| ..)` method takes [`dmaintenr::W`](W) writer structure"]
impl crate :: Writable for DMAINTENR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DMAINTENR to value 0"]
impl crate :: Resettable for DMAINTENR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "INTFR (w) register accessor: status register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intfr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intfr`]
module"]
pub type INTFR = crate :: Reg < intfr :: INTFR_SPEC > ; # [doc = "status register"]
pub mod intfr { # [doc = "Register `INTFR` writer"]
pub type W = crate :: W < INTFR_SPEC > ; # [doc = "Field `UIF` writer - Update interrupt flag"]
pub type UIF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1IF` writer - Capture/compare 1 interrupt flag"]
pub type CC1IF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2IF` writer - Capture/Compare 2 interrupt flag"]
pub type CC2IF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3IF` writer - Capture/Compare 3 interrupt flag"]
pub type CC3IF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4IF` writer - Capture/Compare 4 interrupt flag"]
pub type CC4IF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIF` writer - Trigger interrupt flag"]
pub type TIF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1OF` writer - Capture/Compare 1 overcapture flag"]
pub type CC1OF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2OF` writer - Capture/compare 2 overcapture flag"]
pub type CC2OF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3OF` writer - Capture/Compare 3 overcapture flag"]
pub type CC3OF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4OF` writer - Capture/Compare 4 overcapture flag"]
pub type CC4OF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W { # [doc = "Bit 0 - Update interrupt flag"]
# [inline (always)]
# [must_use]
pub fn uif (& mut self) -> UIF_W < INTFR_SPEC > { UIF_W :: new (self , 0) } # [doc = "Bit 1 - Capture/compare 1 interrupt flag"]
# [inline (always)]
# [must_use]
pub fn cc1if (& mut self) -> CC1IF_W < INTFR_SPEC > { CC1IF_W :: new (self , 1) } # [doc = "Bit 2 - Capture/Compare 2 interrupt flag"]
# [inline (always)]
# [must_use]
pub fn cc2if (& mut self) -> CC2IF_W < INTFR_SPEC > { CC2IF_W :: new (self , 2) } # [doc = "Bit 3 - Capture/Compare 3 interrupt flag"]
# [inline (always)]
# [must_use]
pub fn cc3if (& mut self) -> CC3IF_W < INTFR_SPEC > { CC3IF_W :: new (self , 3) } # [doc = "Bit 4 - Capture/Compare 4 interrupt flag"]
# [inline (always)]
# [must_use]
pub fn cc4if (& mut self) -> CC4IF_W < INTFR_SPEC > { CC4IF_W :: new (self , 4) } # [doc = "Bit 6 - Trigger interrupt flag"]
# [inline (always)]
# [must_use]
pub fn tif (& mut self) -> TIF_W < INTFR_SPEC > { TIF_W :: new (self , 6) } # [doc = "Bit 9 - Capture/Compare 1 overcapture flag"]
# [inline (always)]
# [must_use]
pub fn cc1of (& mut self) -> CC1OF_W < INTFR_SPEC > { CC1OF_W :: new (self , 9) } # [doc = "Bit 10 - Capture/compare 2 overcapture flag"]
# [inline (always)]
# [must_use]
pub fn cc2of (& mut self) -> CC2OF_W < INTFR_SPEC > { CC2OF_W :: new (self , 10) } # [doc = "Bit 11 - Capture/Compare 3 overcapture flag"]
# [inline (always)]
# [must_use]
pub fn cc3of (& mut self) -> CC3OF_W < INTFR_SPEC > { CC3OF_W :: new (self , 11) } # [doc = "Bit 12 - Capture/Compare 4 overcapture flag"]
# [inline (always)]
# [must_use]
pub fn cc4of (& mut self) -> CC4OF_W < INTFR_SPEC > { CC4OF_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "status register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intfr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTFR_SPEC ; impl crate :: RegisterSpec for INTFR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`intfr::W`](W) writer structure"]
impl crate :: Writable for INTFR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets INTFR to value 0"]
impl crate :: Resettable for INTFR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "SWEVGR (w) register accessor: event generation register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swevgr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swevgr`]
module"]
pub type SWEVGR = crate :: Reg < swevgr :: SWEVGR_SPEC > ; # [doc = "event generation register"]
pub mod swevgr { # [doc = "Register `SWEVGR` writer"]
pub type W = crate :: W < SWEVGR_SPEC > ; # [doc = "Field `UG` writer - Update generation"]
pub type UG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1G` writer - Capture/compare 1 generation"]
pub type CC1G_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2G` writer - Capture/compare 2 generation"]
pub type CC2G_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3G` writer - Capture/compare 3 generation"]
pub type CC3G_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4G` writer - Capture/compare 4 generation"]
pub type CC4G_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `COMG` writer - Capture/Compare control update generation"]
pub type COMG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TG` writer - Trigger generation"]
pub type TG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BG` writer - Break generation"]
pub type BG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W { # [doc = "Bit 0 - Update generation"]
# [inline (always)]
# [must_use]
pub fn ug (& mut self) -> UG_W < SWEVGR_SPEC > { UG_W :: new (self , 0) } # [doc = "Bit 1 - Capture/compare 1 generation"]
# [inline (always)]
# [must_use]
pub fn cc1g (& mut self) -> CC1G_W < SWEVGR_SPEC > { CC1G_W :: new (self , 1) } # [doc = "Bit 2 - Capture/compare 2 generation"]
# [inline (always)]
# [must_use]
pub fn cc2g (& mut self) -> CC2G_W < SWEVGR_SPEC > { CC2G_W :: new (self , 2) } # [doc = "Bit 3 - Capture/compare 3 generation"]
# [inline (always)]
# [must_use]
pub fn cc3g (& mut self) -> CC3G_W < SWEVGR_SPEC > { CC3G_W :: new (self , 3) } # [doc = "Bit 4 - Capture/compare 4 generation"]
# [inline (always)]
# [must_use]
pub fn cc4g (& mut self) -> CC4G_W < SWEVGR_SPEC > { CC4G_W :: new (self , 4) } # [doc = "Bit 5 - Capture/Compare control update generation"]
# [inline (always)]
# [must_use]
pub fn comg (& mut self) -> COMG_W < SWEVGR_SPEC > { COMG_W :: new (self , 5) } # [doc = "Bit 6 - Trigger generation"]
# [inline (always)]
# [must_use]
pub fn tg (& mut self) -> TG_W < SWEVGR_SPEC > { TG_W :: new (self , 6) } # [doc = "Bit 7 - Break generation"]
# [inline (always)]
# [must_use]
pub fn bg (& mut self) -> BG_W < SWEVGR_SPEC > { BG_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "event generation register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swevgr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SWEVGR_SPEC ; impl crate :: RegisterSpec for SWEVGR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`swevgr::W`](W) writer structure"]
impl crate :: Writable for SWEVGR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SWEVGR to value 0"]
impl crate :: Resettable for SWEVGR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CHCTLR1_Output (rw) register accessor: capture/compare mode register 1 (output mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr1_output::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr1_output::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chctlr1_output`]
module"]
pub type CHCTLR1_OUTPUT = crate :: Reg < chctlr1_output :: CHCTLR1_OUTPUT_SPEC > ; # [doc = "capture/compare mode register 1 (output mode)"]
pub mod chctlr1_output { # [doc = "Register `CHCTLR1_Output` reader"]
pub type R = crate :: R < CHCTLR1_OUTPUT_SPEC > ; # [doc = "Register `CHCTLR1_Output` writer"]
pub type W = crate :: W < CHCTLR1_OUTPUT_SPEC > ; # [doc = "Field `CC1S` reader - Capture/Compare 1 selection"]
pub type CC1S_R = crate :: FieldReader ; # [doc = "Field `CC1S` writer - Capture/Compare 1 selection"]
pub type CC1S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `OC1FE` reader - Output compare 1 fast enable"]
pub type OC1FE_R = crate :: BitReader ; # [doc = "Field `OC1FE` writer - Output compare 1 fast enable"]
pub type OC1FE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC1PE` reader - Output compare 1 preload enable"]
pub type OC1PE_R = crate :: BitReader ; # [doc = "Field `OC1PE` writer - Output compare 1 preload enable"]
pub type OC1PE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC1M` reader - Output compare 1 mode"]
pub type OC1M_R = crate :: FieldReader ; # [doc = "Field `OC1M` writer - Output compare 1 mode"]
pub type OC1M_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `OC1CE` reader - Output compare 1 clear enable"]
pub type OC1CE_R = crate :: BitReader ; # [doc = "Field `OC1CE` writer - Output compare 1 clear enable"]
pub type OC1CE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2S` reader - Capture/Compare 2 selection"]
pub type CC2S_R = crate :: FieldReader ; # [doc = "Field `CC2S` writer - Capture/Compare 2 selection"]
pub type CC2S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `OC2FE` reader - Output compare 2 fast enable"]
pub type OC2FE_R = crate :: BitReader ; # [doc = "Field `OC2FE` writer - Output compare 2 fast enable"]
pub type OC2FE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC2PE` reader - Output compare 2 preload enable"]
pub type OC2PE_R = crate :: BitReader ; # [doc = "Field `OC2PE` writer - Output compare 2 preload enable"]
pub type OC2PE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC2M` reader - Output compare 2 mode"]
pub type OC2M_R = crate :: FieldReader ; # [doc = "Field `OC2M` writer - Output compare 2 mode"]
pub type OC2M_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `OC2CE` reader - Output compare 2 clear enable"]
pub type OC2CE_R = crate :: BitReader ; # [doc = "Field `OC2CE` writer - Output compare 2 clear enable"]
pub type OC2CE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - Capture/Compare 1 selection"]
# [inline (always)]
pub fn cc1s (& self) -> CC1S_R { CC1S_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Output compare 1 fast enable"]
# [inline (always)]
pub fn oc1fe (& self) -> OC1FE_R { OC1FE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Output compare 1 preload enable"]
# [inline (always)]
pub fn oc1pe (& self) -> OC1PE_R { OC1PE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - Output compare 1 mode"]
# [inline (always)]
pub fn oc1m (& self) -> OC1M_R { OC1M_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - Output compare 1 clear enable"]
# [inline (always)]
pub fn oc1ce (& self) -> OC1CE_R { OC1CE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Capture/Compare 2 selection"]
# [inline (always)]
pub fn cc2s (& self) -> CC2S_R { CC2S_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 10 - Output compare 2 fast enable"]
# [inline (always)]
pub fn oc2fe (& self) -> OC2FE_R { OC2FE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Output compare 2 preload enable"]
# [inline (always)]
pub fn oc2pe (& self) -> OC2PE_R { OC2PE_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:14 - Output compare 2 mode"]
# [inline (always)]
pub fn oc2m (& self) -> OC2M_R { OC2M_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 15 - Output compare 2 clear enable"]
# [inline (always)]
pub fn oc2ce (& self) -> OC2CE_R { OC2CE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - Capture/Compare 1 selection"]
# [inline (always)]
# [must_use]
pub fn cc1s (& mut self) -> CC1S_W < CHCTLR1_OUTPUT_SPEC > { CC1S_W :: new (self , 0) } # [doc = "Bit 2 - Output compare 1 fast enable"]
# [inline (always)]
# [must_use]
pub fn oc1fe (& mut self) -> OC1FE_W < CHCTLR1_OUTPUT_SPEC > { OC1FE_W :: new (self , 2) } # [doc = "Bit 3 - Output compare 1 preload enable"]
# [inline (always)]
# [must_use]
pub fn oc1pe (& mut self) -> OC1PE_W < CHCTLR1_OUTPUT_SPEC > { OC1PE_W :: new (self , 3) } # [doc = "Bits 4:6 - Output compare 1 mode"]
# [inline (always)]
# [must_use]
pub fn oc1m (& mut self) -> OC1M_W < CHCTLR1_OUTPUT_SPEC > { OC1M_W :: new (self , 4) } # [doc = "Bit 7 - Output compare 1 clear enable"]
# [inline (always)]
# [must_use]
pub fn oc1ce (& mut self) -> OC1CE_W < CHCTLR1_OUTPUT_SPEC > { OC1CE_W :: new (self , 7) } # [doc = "Bits 8:9 - Capture/Compare 2 selection"]
# [inline (always)]
# [must_use]
pub fn cc2s (& mut self) -> CC2S_W < CHCTLR1_OUTPUT_SPEC > { CC2S_W :: new (self , 8) } # [doc = "Bit 10 - Output compare 2 fast enable"]
# [inline (always)]
# [must_use]
pub fn oc2fe (& mut self) -> OC2FE_W < CHCTLR1_OUTPUT_SPEC > { OC2FE_W :: new (self , 10) } # [doc = "Bit 11 - Output compare 2 preload enable"]
# [inline (always)]
# [must_use]
pub fn oc2pe (& mut self) -> OC2PE_W < CHCTLR1_OUTPUT_SPEC > { OC2PE_W :: new (self , 11) } # [doc = "Bits 12:14 - Output compare 2 mode"]
# [inline (always)]
# [must_use]
pub fn oc2m (& mut self) -> OC2M_W < CHCTLR1_OUTPUT_SPEC > { OC2M_W :: new (self , 12) } # [doc = "Bit 15 - Output compare 2 clear enable"]
# [inline (always)]
# [must_use]
pub fn oc2ce (& mut self) -> OC2CE_W < CHCTLR1_OUTPUT_SPEC > { OC2CE_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare mode register 1 (output mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr1_output::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr1_output::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CHCTLR1_OUTPUT_SPEC ; impl crate :: RegisterSpec for CHCTLR1_OUTPUT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`chctlr1_output::R`](R) reader structure"]
impl crate :: Readable for CHCTLR1_OUTPUT_SPEC { } # [doc = "`write(|w| ..)` method takes [`chctlr1_output::W`](W) writer structure"]
impl crate :: Writable for CHCTLR1_OUTPUT_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CHCTLR1_Output to value 0"]
impl crate :: Resettable for CHCTLR1_OUTPUT_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CHCTLR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr1_input::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr1_input::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chctlr1_input`]
module"]
pub type CHCTLR1_INPUT = crate :: Reg < chctlr1_input :: CHCTLR1_INPUT_SPEC > ; # [doc = "capture/compare mode register 1 (input mode)"]
pub mod chctlr1_input { # [doc = "Register `CHCTLR1_Input` reader"]
pub type R = crate :: R < CHCTLR1_INPUT_SPEC > ; # [doc = "Register `CHCTLR1_Input` writer"]
pub type W = crate :: W < CHCTLR1_INPUT_SPEC > ; # [doc = "Field `CC1S` reader - Capture/Compare 1 selection"]
pub type CC1S_R = crate :: FieldReader ; # [doc = "Field `CC1S` writer - Capture/Compare 1 selection"]
pub type CC1S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC1PSC` reader - Input capture 1 prescaler"]
pub type IC1PSC_R = crate :: FieldReader ; # [doc = "Field `IC1PSC` writer - Input capture 1 prescaler"]
pub type IC1PSC_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC1F` reader - Input capture 1 filter"]
pub type IC1F_R = crate :: FieldReader ; # [doc = "Field `IC1F` writer - Input capture 1 filter"]
pub type IC1F_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `CC2S` reader - Capture/compare 2 selection"]
pub type CC2S_R = crate :: FieldReader ; # [doc = "Field `CC2S` writer - Capture/compare 2 selection"]
pub type CC2S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC2PSC` reader - Input capture 2 prescaler"]
pub type IC2PSC_R = crate :: FieldReader ; # [doc = "Field `IC2PSC` writer - Input capture 2 prescaler"]
pub type IC2PSC_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC2F` reader - Input capture 2 filter"]
pub type IC2F_R = crate :: FieldReader ; # [doc = "Field `IC2F` writer - Input capture 2 filter"]
pub type IC2F_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:1 - Capture/Compare 1 selection"]
# [inline (always)]
pub fn cc1s (& self) -> CC1S_R { CC1S_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Input capture 1 prescaler"]
# [inline (always)]
pub fn ic1psc (& self) -> IC1PSC_R { IC1PSC_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - Input capture 1 filter"]
# [inline (always)]
pub fn ic1f (& self) -> IC1F_R { IC1F_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:9 - Capture/compare 2 selection"]
# [inline (always)]
pub fn cc2s (& self) -> CC2S_R { CC2S_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Input capture 2 prescaler"]
# [inline (always)]
pub fn ic2psc (& self) -> IC2PSC_R { IC2PSC_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:15 - Input capture 2 filter"]
# [inline (always)]
pub fn ic2f (& self) -> IC2F_R { IC2F_R :: new (((self . bits >> 12) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:1 - Capture/Compare 1 selection"]
# [inline (always)]
# [must_use]
pub fn cc1s (& mut self) -> CC1S_W < CHCTLR1_INPUT_SPEC > { CC1S_W :: new (self , 0) } # [doc = "Bits 2:3 - Input capture 1 prescaler"]
# [inline (always)]
# [must_use]
pub fn ic1psc (& mut self) -> IC1PSC_W < CHCTLR1_INPUT_SPEC > { IC1PSC_W :: new (self , 2) } # [doc = "Bits 4:7 - Input capture 1 filter"]
# [inline (always)]
# [must_use]
pub fn ic1f (& mut self) -> IC1F_W < CHCTLR1_INPUT_SPEC > { IC1F_W :: new (self , 4) } # [doc = "Bits 8:9 - Capture/compare 2 selection"]
# [inline (always)]
# [must_use]
pub fn cc2s (& mut self) -> CC2S_W < CHCTLR1_INPUT_SPEC > { CC2S_W :: new (self , 8) } # [doc = "Bits 10:11 - Input capture 2 prescaler"]
# [inline (always)]
# [must_use]
pub fn ic2psc (& mut self) -> IC2PSC_W < CHCTLR1_INPUT_SPEC > { IC2PSC_W :: new (self , 10) } # [doc = "Bits 12:15 - Input capture 2 filter"]
# [inline (always)]
# [must_use]
pub fn ic2f (& mut self) -> IC2F_W < CHCTLR1_INPUT_SPEC > { IC2F_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare mode register 1 (input mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr1_input::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr1_input::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CHCTLR1_INPUT_SPEC ; impl crate :: RegisterSpec for CHCTLR1_INPUT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`chctlr1_input::R`](R) reader structure"]
impl crate :: Readable for CHCTLR1_INPUT_SPEC { } # [doc = "`write(|w| ..)` method takes [`chctlr1_input::W`](W) writer structure"]
impl crate :: Writable for CHCTLR1_INPUT_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CHCTLR1_Input to value 0"]
impl crate :: Resettable for CHCTLR1_INPUT_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CHCTLR2_Output (rw) register accessor: capture/compare mode register 2 (output mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr2_output::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr2_output::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chctlr2_output`]
module"]
pub type CHCTLR2_OUTPUT = crate :: Reg < chctlr2_output :: CHCTLR2_OUTPUT_SPEC > ; # [doc = "capture/compare mode register 2 (output mode)"]
pub mod chctlr2_output { # [doc = "Register `CHCTLR2_Output` reader"]
pub type R = crate :: R < CHCTLR2_OUTPUT_SPEC > ; # [doc = "Register `CHCTLR2_Output` writer"]
pub type W = crate :: W < CHCTLR2_OUTPUT_SPEC > ; # [doc = "Field `CC3S` reader - Capture/Compare 3 selection"]
pub type CC3S_R = crate :: FieldReader ; # [doc = "Field `CC3S` writer - Capture/Compare 3 selection"]
pub type CC3S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `OC3FE` reader - Output compare 3 fast enable"]
pub type OC3FE_R = crate :: BitReader ; # [doc = "Field `OC3FE` writer - Output compare 3 fast enable"]
pub type OC3FE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC3PE` reader - Output compare 3 preload enable"]
pub type OC3PE_R = crate :: BitReader ; # [doc = "Field `OC3PE` writer - Output compare 3 preload enable"]
pub type OC3PE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC3M` reader - Output compare 3 mode"]
pub type OC3M_R = crate :: FieldReader ; # [doc = "Field `OC3M` writer - Output compare 3 mode"]
pub type OC3M_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `OC3CE` reader - Output compare 3 clear enable"]
pub type OC3CE_R = crate :: BitReader ; # [doc = "Field `OC3CE` writer - Output compare 3 clear enable"]
pub type OC3CE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4S` reader - Capture/Compare 4 selection"]
pub type CC4S_R = crate :: FieldReader ; # [doc = "Field `CC4S` writer - Capture/Compare 4 selection"]
pub type CC4S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `OC4FE` reader - Output compare 4 fast enable"]
pub type OC4FE_R = crate :: BitReader ; # [doc = "Field `OC4FE` writer - Output compare 4 fast enable"]
pub type OC4FE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC4PE` reader - Output compare 4 preload enable"]
pub type OC4PE_R = crate :: BitReader ; # [doc = "Field `OC4PE` writer - Output compare 4 preload enable"]
pub type OC4PE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OC4M` reader - Output compare 4 mode"]
pub type OC4M_R = crate :: FieldReader ; # [doc = "Field `OC4M` writer - Output compare 4 mode"]
pub type OC4M_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `OC4CE` reader - Output compare 4 clear enable"]
pub type OC4CE_R = crate :: BitReader ; # [doc = "Field `OC4CE` writer - Output compare 4 clear enable"]
pub type OC4CE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - Capture/Compare 3 selection"]
# [inline (always)]
pub fn cc3s (& self) -> CC3S_R { CC3S_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Output compare 3 fast enable"]
# [inline (always)]
pub fn oc3fe (& self) -> OC3FE_R { OC3FE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Output compare 3 preload enable"]
# [inline (always)]
pub fn oc3pe (& self) -> OC3PE_R { OC3PE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:6 - Output compare 3 mode"]
# [inline (always)]
pub fn oc3m (& self) -> OC3M_R { OC3M_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - Output compare 3 clear enable"]
# [inline (always)]
pub fn oc3ce (& self) -> OC3CE_R { OC3CE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Capture/Compare 4 selection"]
# [inline (always)]
pub fn cc4s (& self) -> CC4S_R { CC4S_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 10 - Output compare 4 fast enable"]
# [inline (always)]
pub fn oc4fe (& self) -> OC4FE_R { OC4FE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Output compare 4 preload enable"]
# [inline (always)]
pub fn oc4pe (& self) -> OC4PE_R { OC4PE_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:14 - Output compare 4 mode"]
# [inline (always)]
pub fn oc4m (& self) -> OC4M_R { OC4M_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 15 - Output compare 4 clear enable"]
# [inline (always)]
pub fn oc4ce (& self) -> OC4CE_R { OC4CE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - Capture/Compare 3 selection"]
# [inline (always)]
# [must_use]
pub fn cc3s (& mut self) -> CC3S_W < CHCTLR2_OUTPUT_SPEC > { CC3S_W :: new (self , 0) } # [doc = "Bit 2 - Output compare 3 fast enable"]
# [inline (always)]
# [must_use]
pub fn oc3fe (& mut self) -> OC3FE_W < CHCTLR2_OUTPUT_SPEC > { OC3FE_W :: new (self , 2) } # [doc = "Bit 3 - Output compare 3 preload enable"]
# [inline (always)]
# [must_use]
pub fn oc3pe (& mut self) -> OC3PE_W < CHCTLR2_OUTPUT_SPEC > { OC3PE_W :: new (self , 3) } # [doc = "Bits 4:6 - Output compare 3 mode"]
# [inline (always)]
# [must_use]
pub fn oc3m (& mut self) -> OC3M_W < CHCTLR2_OUTPUT_SPEC > { OC3M_W :: new (self , 4) } # [doc = "Bit 7 - Output compare 3 clear enable"]
# [inline (always)]
# [must_use]
pub fn oc3ce (& mut self) -> OC3CE_W < CHCTLR2_OUTPUT_SPEC > { OC3CE_W :: new (self , 7) } # [doc = "Bits 8:9 - Capture/Compare 4 selection"]
# [inline (always)]
# [must_use]
pub fn cc4s (& mut self) -> CC4S_W < CHCTLR2_OUTPUT_SPEC > { CC4S_W :: new (self , 8) } # [doc = "Bit 10 - Output compare 4 fast enable"]
# [inline (always)]
# [must_use]
pub fn oc4fe (& mut self) -> OC4FE_W < CHCTLR2_OUTPUT_SPEC > { OC4FE_W :: new (self , 10) } # [doc = "Bit 11 - Output compare 4 preload enable"]
# [inline (always)]
# [must_use]
pub fn oc4pe (& mut self) -> OC4PE_W < CHCTLR2_OUTPUT_SPEC > { OC4PE_W :: new (self , 11) } # [doc = "Bits 12:14 - Output compare 4 mode"]
# [inline (always)]
# [must_use]
pub fn oc4m (& mut self) -> OC4M_W < CHCTLR2_OUTPUT_SPEC > { OC4M_W :: new (self , 12) } # [doc = "Bit 15 - Output compare 4 clear enable"]
# [inline (always)]
# [must_use]
pub fn oc4ce (& mut self) -> OC4CE_W < CHCTLR2_OUTPUT_SPEC > { OC4CE_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare mode register 2 (output mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr2_output::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr2_output::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CHCTLR2_OUTPUT_SPEC ; impl crate :: RegisterSpec for CHCTLR2_OUTPUT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`chctlr2_output::R`](R) reader structure"]
impl crate :: Readable for CHCTLR2_OUTPUT_SPEC { } # [doc = "`write(|w| ..)` method takes [`chctlr2_output::W`](W) writer structure"]
impl crate :: Writable for CHCTLR2_OUTPUT_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CHCTLR2_Output to value 0"]
impl crate :: Resettable for CHCTLR2_OUTPUT_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CHCTLR2_Input (rw) register accessor: capture/compare mode register 2 (input mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr2_input::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr2_input::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chctlr2_input`]
module"]
pub type CHCTLR2_INPUT = crate :: Reg < chctlr2_input :: CHCTLR2_INPUT_SPEC > ; # [doc = "capture/compare mode register 2 (input mode)"]
pub mod chctlr2_input { # [doc = "Register `CHCTLR2_Input` reader"]
pub type R = crate :: R < CHCTLR2_INPUT_SPEC > ; # [doc = "Register `CHCTLR2_Input` writer"]
pub type W = crate :: W < CHCTLR2_INPUT_SPEC > ; # [doc = "Field `CC3S` reader - Capture/Compare 3 selection"]
pub type CC3S_R = crate :: FieldReader ; # [doc = "Field `CC3S` writer - Capture/Compare 3 selection"]
pub type CC3S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC3PSC` reader - Input capture 3 prescaler"]
pub type IC3PSC_R = crate :: FieldReader ; # [doc = "Field `IC3PSC` writer - Input capture 3 prescaler"]
pub type IC3PSC_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC3F` reader - Input capture 3 filter"]
pub type IC3F_R = crate :: FieldReader ; # [doc = "Field `IC3F` writer - Input capture 3 filter"]
pub type IC3F_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `CC4S` reader - Capture/Compare 4 selection"]
pub type CC4S_R = crate :: FieldReader ; # [doc = "Field `CC4S` writer - Capture/Compare 4 selection"]
pub type CC4S_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC4PSC` reader - Input capture 4 prescaler"]
pub type IC4PSC_R = crate :: FieldReader ; # [doc = "Field `IC4PSC` writer - Input capture 4 prescaler"]
pub type IC4PSC_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `IC4F` reader - Input capture 4 filter"]
pub type IC4F_R = crate :: FieldReader ; # [doc = "Field `IC4F` writer - Input capture 4 filter"]
pub type IC4F_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:1 - Capture/Compare 3 selection"]
# [inline (always)]
pub fn cc3s (& self) -> CC3S_R { CC3S_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Input capture 3 prescaler"]
# [inline (always)]
pub fn ic3psc (& self) -> IC3PSC_R { IC3PSC_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:7 - Input capture 3 filter"]
# [inline (always)]
pub fn ic3f (& self) -> IC3F_R { IC3F_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:9 - Capture/Compare 4 selection"]
# [inline (always)]
pub fn cc4s (& self) -> CC4S_R { CC4S_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Input capture 4 prescaler"]
# [inline (always)]
pub fn ic4psc (& self) -> IC4PSC_R { IC4PSC_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:15 - Input capture 4 filter"]
# [inline (always)]
pub fn ic4f (& self) -> IC4F_R { IC4F_R :: new (((self . bits >> 12) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:1 - Capture/Compare 3 selection"]
# [inline (always)]
# [must_use]
pub fn cc3s (& mut self) -> CC3S_W < CHCTLR2_INPUT_SPEC > { CC3S_W :: new (self , 0) } # [doc = "Bits 2:3 - Input capture 3 prescaler"]
# [inline (always)]
# [must_use]
pub fn ic3psc (& mut self) -> IC3PSC_W < CHCTLR2_INPUT_SPEC > { IC3PSC_W :: new (self , 2) } # [doc = "Bits 4:7 - Input capture 3 filter"]
# [inline (always)]
# [must_use]
pub fn ic3f (& mut self) -> IC3F_W < CHCTLR2_INPUT_SPEC > { IC3F_W :: new (self , 4) } # [doc = "Bits 8:9 - Capture/Compare 4 selection"]
# [inline (always)]
# [must_use]
pub fn cc4s (& mut self) -> CC4S_W < CHCTLR2_INPUT_SPEC > { CC4S_W :: new (self , 8) } # [doc = "Bits 10:11 - Input capture 4 prescaler"]
# [inline (always)]
# [must_use]
pub fn ic4psc (& mut self) -> IC4PSC_W < CHCTLR2_INPUT_SPEC > { IC4PSC_W :: new (self , 10) } # [doc = "Bits 12:15 - Input capture 4 filter"]
# [inline (always)]
# [must_use]
pub fn ic4f (& mut self) -> IC4F_W < CHCTLR2_INPUT_SPEC > { IC4F_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare mode register 2 (input mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctlr2_input::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctlr2_input::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CHCTLR2_INPUT_SPEC ; impl crate :: RegisterSpec for CHCTLR2_INPUT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`chctlr2_input::R`](R) reader structure"]
impl crate :: Readable for CHCTLR2_INPUT_SPEC { } # [doc = "`write(|w| ..)` method takes [`chctlr2_input::W`](W) writer structure"]
impl crate :: Writable for CHCTLR2_INPUT_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CHCTLR2_Input to value 0"]
impl crate :: Resettable for CHCTLR2_INPUT_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CCER (rw) register accessor: capture/compare enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccer::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccer`]
module"]
pub type CCER = crate :: Reg < ccer :: CCER_SPEC > ; # [doc = "capture/compare enable register"]
pub mod ccer { # [doc = "Register `CCER` reader"]
pub type R = crate :: R < CCER_SPEC > ; # [doc = "Register `CCER` writer"]
pub type W = crate :: W < CCER_SPEC > ; # [doc = "Field `CC1E` reader - Capture/Compare 1 output enable"]
pub type CC1E_R = crate :: BitReader ; # [doc = "Field `CC1E` writer - Capture/Compare 1 output enable"]
pub type CC1E_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC1P` reader - Capture/Compare 1 output Polarity"]
pub type CC1P_R = crate :: BitReader ; # [doc = "Field `CC1P` writer - Capture/Compare 1 output Polarity"]
pub type CC1P_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2E` reader - Capture/Compare 2 output enable"]
pub type CC2E_R = crate :: BitReader ; # [doc = "Field `CC2E` writer - Capture/Compare 2 output enable"]
pub type CC2E_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC2P` reader - Capture/Compare 2 output Polarity"]
pub type CC2P_R = crate :: BitReader ; # [doc = "Field `CC2P` writer - Capture/Compare 2 output Polarity"]
pub type CC2P_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3E` reader - Capture/Compare 3 output enable"]
pub type CC3E_R = crate :: BitReader ; # [doc = "Field `CC3E` writer - Capture/Compare 3 output enable"]
pub type CC3E_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC3P` reader - Capture/Compare 3 output Polarity"]
pub type CC3P_R = crate :: BitReader ; # [doc = "Field `CC3P` writer - Capture/Compare 3 output Polarity"]
pub type CC3P_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4E` reader - Capture/Compare 4 output enable"]
pub type CC4E_R = crate :: BitReader ; # [doc = "Field `CC4E` writer - Capture/Compare 4 output enable"]
pub type CC4E_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CC4P` reader - Capture/Compare 3 output Polarity"]
pub type CC4P_R = crate :: BitReader ; # [doc = "Field `CC4P` writer - Capture/Compare 3 output Polarity"]
pub type CC4P_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Capture/Compare 1 output enable"]
# [inline (always)]
pub fn cc1e (& self) -> CC1E_R { CC1E_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Capture/Compare 1 output Polarity"]
# [inline (always)]
pub fn cc1p (& self) -> CC1P_R { CC1P_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - Capture/Compare 2 output enable"]
# [inline (always)]
pub fn cc2e (& self) -> CC2E_R { CC2E_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture/Compare 2 output Polarity"]
# [inline (always)]
pub fn cc2p (& self) -> CC2P_R { CC2P_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 8 - Capture/Compare 3 output enable"]
# [inline (always)]
pub fn cc3e (& self) -> CC3E_R { CC3E_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture/Compare 3 output Polarity"]
# [inline (always)]
pub fn cc3p (& self) -> CC3P_R { CC3P_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 12 - Capture/Compare 4 output enable"]
# [inline (always)]
pub fn cc4e (& self) -> CC4E_R { CC4E_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Capture/Compare 3 output Polarity"]
# [inline (always)]
pub fn cc4p (& self) -> CC4P_R { CC4P_R :: new (((self . bits >> 13) & 1) != 0) } } impl W { # [doc = "Bit 0 - Capture/Compare 1 output enable"]
# [inline (always)]
# [must_use]
pub fn cc1e (& mut self) -> CC1E_W < CCER_SPEC > { CC1E_W :: new (self , 0) } # [doc = "Bit 1 - Capture/Compare 1 output Polarity"]
# [inline (always)]
# [must_use]
pub fn cc1p (& mut self) -> CC1P_W < CCER_SPEC > { CC1P_W :: new (self , 1) } # [doc = "Bit 4 - Capture/Compare 2 output enable"]
# [inline (always)]
# [must_use]
pub fn cc2e (& mut self) -> CC2E_W < CCER_SPEC > { CC2E_W :: new (self , 4) } # [doc = "Bit 5 - Capture/Compare 2 output Polarity"]
# [inline (always)]
# [must_use]
pub fn cc2p (& mut self) -> CC2P_W < CCER_SPEC > { CC2P_W :: new (self , 5) } # [doc = "Bit 8 - Capture/Compare 3 output enable"]
# [inline (always)]
# [must_use]
pub fn cc3e (& mut self) -> CC3E_W < CCER_SPEC > { CC3E_W :: new (self , 8) } # [doc = "Bit 9 - Capture/Compare 3 output Polarity"]
# [inline (always)]
# [must_use]
pub fn cc3p (& mut self) -> CC3P_W < CCER_SPEC > { CC3P_W :: new (self , 9) } # [doc = "Bit 12 - Capture/Compare 4 output enable"]
# [inline (always)]
# [must_use]
pub fn cc4e (& mut self) -> CC4E_W < CCER_SPEC > { CC4E_W :: new (self , 12) } # [doc = "Bit 13 - Capture/Compare 3 output Polarity"]
# [inline (always)]
# [must_use]
pub fn cc4p (& mut self) -> CC4P_W < CCER_SPEC > { CC4P_W :: new (self , 13) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccer::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccer::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCER_SPEC ; impl crate :: RegisterSpec for CCER_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccer::R`](R) reader structure"]
impl crate :: Readable for CCER_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccer::W`](W) writer structure"]
impl crate :: Writable for CCER_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CCER to value 0"]
impl crate :: Resettable for CCER_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CNT (rw) register accessor: counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`]
module"]
pub type CNT = crate :: Reg < cnt :: CNT_SPEC > ; # [doc = "counter"]
pub mod cnt { # [doc = "Register `CNT` reader"]
pub type R = crate :: R < CNT_SPEC > ; # [doc = "Register `CNT` writer"]
pub type W = crate :: W < CNT_SPEC > ; # [doc = "Field `CNT` reader - counter value"]
pub type CNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `CNT` writer - counter value"]
pub type CNT_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - counter value"]
# [inline (always)]
pub fn cnt (& self) -> CNT_R { CNT_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - counter value"]
# [inline (always)]
# [must_use]
pub fn cnt (& mut self) -> CNT_W < CNT_SPEC > { CNT_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CNT_SPEC ; impl crate :: RegisterSpec for CNT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cnt::R`](R) reader structure"]
impl crate :: Readable for CNT_SPEC { } # [doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
impl crate :: Writable for CNT_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CNT to value 0"]
impl crate :: Resettable for CNT_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "PSC (rw) register accessor: prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psc`]
module"]
pub type PSC = crate :: Reg < psc :: PSC_SPEC > ; # [doc = "prescaler"]
pub mod psc { # [doc = "Register `PSC` reader"]
pub type R = crate :: R < PSC_SPEC > ; # [doc = "Register `PSC` writer"]
pub type W = crate :: W < PSC_SPEC > ; # [doc = "Field `PSC` reader - Prescaler value"]
pub type PSC_R = crate :: FieldReader < u16 > ; # [doc = "Field `PSC` writer - Prescaler value"]
pub type PSC_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Prescaler value"]
# [inline (always)]
pub fn psc (& self) -> PSC_R { PSC_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Prescaler value"]
# [inline (always)]
# [must_use]
pub fn psc (& mut self) -> PSC_W < PSC_SPEC > { PSC_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PSC_SPEC ; impl crate :: RegisterSpec for PSC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`psc::R`](R) reader structure"]
impl crate :: Readable for PSC_SPEC { } # [doc = "`write(|w| ..)` method takes [`psc::W`](W) writer structure"]
impl crate :: Writable for PSC_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets PSC to value 0"]
impl crate :: Resettable for PSC_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "ATRLR (rw) register accessor: auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atrlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atrlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@atrlr`]
module"]
pub type ATRLR = crate :: Reg < atrlr :: ATRLR_SPEC > ; # [doc = "auto-reload register"]
pub mod atrlr { # [doc = "Register `ATRLR` reader"]
pub type R = crate :: R < ATRLR_SPEC > ; # [doc = "Register `ATRLR` writer"]
pub type W = crate :: W < ATRLR_SPEC > ; # [doc = "Field `ARR` reader - Auto-reload value"]
pub type ARR_R = crate :: FieldReader < u16 > ; # [doc = "Field `ARR` writer - Auto-reload value"]
pub type ARR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Auto-reload value"]
# [inline (always)]
pub fn arr (& self) -> ARR_R { ARR_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Auto-reload value"]
# [inline (always)]
# [must_use]
pub fn arr (& mut self) -> ARR_W < ATRLR_SPEC > { ARR_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atrlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atrlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ATRLR_SPEC ; impl crate :: RegisterSpec for ATRLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`atrlr::R`](R) reader structure"]
impl crate :: Readable for ATRLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`atrlr::W`](W) writer structure"]
impl crate :: Writable for ATRLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ATRLR to value 0"]
impl crate :: Resettable for ATRLR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH1CVR (rw) register accessor: capture/compare register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1cvr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1cvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1cvr`]
module"]
pub type CH1CVR = crate :: Reg < ch1cvr :: CH1CVR_SPEC > ; # [doc = "capture/compare register 1"]
pub mod ch1cvr { # [doc = "Register `CH1CVR` reader"]
pub type R = crate :: R < CH1CVR_SPEC > ; # [doc = "Register `CH1CVR` writer"]
pub type W = crate :: W < CH1CVR_SPEC > ; # [doc = "Field `CCR1` reader - Capture/Compare 1 value"]
pub type CCR1_R = crate :: FieldReader < u16 > ; # [doc = "Field `CCR1` writer - Capture/Compare 1 value"]
pub type CCR1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Capture/Compare 1 value"]
# [inline (always)]
pub fn ccr1 (& self) -> CCR1_R { CCR1_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Capture/Compare 1 value"]
# [inline (always)]
# [must_use]
pub fn ccr1 (& mut self) -> CCR1_W < CH1CVR_SPEC > { CCR1_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1cvr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1cvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CH1CVR_SPEC ; impl crate :: RegisterSpec for CH1CVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ch1cvr::R`](R) reader structure"]
impl crate :: Readable for CH1CVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ch1cvr::W`](W) writer structure"]
impl crate :: Writable for CH1CVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH1CVR to value 0"]
impl crate :: Resettable for CH1CVR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH2CVR (rw) register accessor: capture/compare register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2cvr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2cvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2cvr`]
module"]
pub type CH2CVR = crate :: Reg < ch2cvr :: CH2CVR_SPEC > ; # [doc = "capture/compare register 2"]
pub mod ch2cvr { # [doc = "Register `CH2CVR` reader"]
pub type R = crate :: R < CH2CVR_SPEC > ; # [doc = "Register `CH2CVR` writer"]
pub type W = crate :: W < CH2CVR_SPEC > ; # [doc = "Field `CCR2` reader - Capture/Compare 2 value"]
pub type CCR2_R = crate :: FieldReader < u16 > ; # [doc = "Field `CCR2` writer - Capture/Compare 2 value"]
pub type CCR2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Capture/Compare 2 value"]
# [inline (always)]
pub fn ccr2 (& self) -> CCR2_R { CCR2_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Capture/Compare 2 value"]
# [inline (always)]
# [must_use]
pub fn ccr2 (& mut self) -> CCR2_W < CH2CVR_SPEC > { CCR2_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2cvr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2cvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CH2CVR_SPEC ; impl crate :: RegisterSpec for CH2CVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ch2cvr::R`](R) reader structure"]
impl crate :: Readable for CH2CVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ch2cvr::W`](W) writer structure"]
impl crate :: Writable for CH2CVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH2CVR to value 0"]
impl crate :: Resettable for CH2CVR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH3CVR (rw) register accessor: capture/compare register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3cvr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3cvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3cvr`]
module"]
pub type CH3CVR = crate :: Reg < ch3cvr :: CH3CVR_SPEC > ; # [doc = "capture/compare register 3"]
pub mod ch3cvr { # [doc = "Register `CH3CVR` reader"]
pub type R = crate :: R < CH3CVR_SPEC > ; # [doc = "Register `CH3CVR` writer"]
pub type W = crate :: W < CH3CVR_SPEC > ; # [doc = "Field `CCR3` reader - Capture/Compare value"]
pub type CCR3_R = crate :: FieldReader < u16 > ; # [doc = "Field `CCR3` writer - Capture/Compare value"]
pub type CCR3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Capture/Compare value"]
# [inline (always)]
pub fn ccr3 (& self) -> CCR3_R { CCR3_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Capture/Compare value"]
# [inline (always)]
# [must_use]
pub fn ccr3 (& mut self) -> CCR3_W < CH3CVR_SPEC > { CCR3_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3cvr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3cvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CH3CVR_SPEC ; impl crate :: RegisterSpec for CH3CVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ch3cvr::R`](R) reader structure"]
impl crate :: Readable for CH3CVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ch3cvr::W`](W) writer structure"]
impl crate :: Writable for CH3CVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH3CVR to value 0"]
impl crate :: Resettable for CH3CVR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CH4CVR (rw) register accessor: capture/compare register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4cvr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4cvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4cvr`]
module"]
pub type CH4CVR = crate :: Reg < ch4cvr :: CH4CVR_SPEC > ; # [doc = "capture/compare register 4"]
pub mod ch4cvr { # [doc = "Register `CH4CVR` reader"]
pub type R = crate :: R < CH4CVR_SPEC > ; # [doc = "Register `CH4CVR` writer"]
pub type W = crate :: W < CH4CVR_SPEC > ; # [doc = "Field `CCR4` reader - Capture/Compare value"]
pub type CCR4_R = crate :: FieldReader < u16 > ; # [doc = "Field `CCR4` writer - Capture/Compare value"]
pub type CCR4_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Capture/Compare value"]
# [inline (always)]
pub fn ccr4 (& self) -> CCR4_R { CCR4_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Capture/Compare value"]
# [inline (always)]
# [must_use]
pub fn ccr4 (& mut self) -> CCR4_W < CH4CVR_SPEC > { CCR4_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "capture/compare register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4cvr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4cvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CH4CVR_SPEC ; impl crate :: RegisterSpec for CH4CVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ch4cvr::R`](R) reader structure"]
impl crate :: Readable for CH4CVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ch4cvr::W`](W) writer structure"]
impl crate :: Writable for CH4CVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CH4CVR to value 0"]
impl crate :: Resettable for CH4CVR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DMACFGR (rw) register accessor: DMA control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacfgr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmacfgr`]
module"]
pub type DMACFGR = crate :: Reg < dmacfgr :: DMACFGR_SPEC > ; # [doc = "DMA control register"]
pub mod dmacfgr { # [doc = "Register `DMACFGR` reader"]
pub type R = crate :: R < DMACFGR_SPEC > ; # [doc = "Register `DMACFGR` writer"]
pub type W = crate :: W < DMACFGR_SPEC > ; # [doc = "Field `DBA` reader - DMA base address"]
pub type DBA_R = crate :: FieldReader ; # [doc = "Field `DBA` writer - DMA base address"]
pub type DBA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `DBL` reader - DMA burst length"]
pub type DBL_R = crate :: FieldReader ; # [doc = "Field `DBL` writer - DMA burst length"]
pub type DBL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bits 0:4 - DMA base address"]
# [inline (always)]
pub fn dba (& self) -> DBA_R { DBA_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 8:12 - DMA burst length"]
# [inline (always)]
pub fn dbl (& self) -> DBL_R { DBL_R :: new (((self . bits >> 8) & 0x1f) as u8) } } impl W { # [doc = "Bits 0:4 - DMA base address"]
# [inline (always)]
# [must_use]
pub fn dba (& mut self) -> DBA_W < DMACFGR_SPEC > { DBA_W :: new (self , 0) } # [doc = "Bits 8:12 - DMA burst length"]
# [inline (always)]
# [must_use]
pub fn dbl (& mut self) -> DBL_W < DMACFGR_SPEC > { DBL_W :: new (self , 8) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacfgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMACFGR_SPEC ; impl crate :: RegisterSpec for DMACFGR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dmacfgr::R`](R) reader structure"]
impl crate :: Readable for DMACFGR_SPEC { } # [doc = "`write(|w| ..)` method takes [`dmacfgr::W`](W) writer structure"]
impl crate :: Writable for DMACFGR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DMACFGR to value 0"]
impl crate :: Resettable for DMACFGR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DMAR (rw) register accessor: DMA address for full transfer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmar::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmar`]
module"]
pub type DMAR = crate :: Reg < dmar :: DMAR_SPEC > ; # [doc = "DMA address for full transfer"]
pub mod dmar { # [doc = "Register `DMAR` reader"]
pub type R = crate :: R < DMAR_SPEC > ; # [doc = "Register `DMAR` writer"]
pub type W = crate :: W < DMAR_SPEC > ; # [doc = "Field `DMAB` reader - DMA register for burst accesses"]
pub type DMAB_R = crate :: FieldReader < u16 > ; # [doc = "Field `DMAB` writer - DMA register for burst accesses"]
pub type DMAB_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - DMA register for burst accesses"]
# [inline (always)]
pub fn dmab (& self) -> DMAB_R { DMAB_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - DMA register for burst accesses"]
# [inline (always)]
# [must_use]
pub fn dmab (& mut self) -> DMAB_W < DMAR_SPEC > { DMAB_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA address for full transfer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMAR_SPEC ; impl crate :: RegisterSpec for DMAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dmar::R`](R) reader structure"]
impl crate :: Readable for DMAR_SPEC { } # [doc = "`write(|w| ..)` method takes [`dmar::W`](W) writer structure"]
impl crate :: Writable for DMAR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DMAR to value 0"]
impl crate :: Resettable for DMAR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "General purpose timer"]
pub struct TIM3 { _marker : PhantomData < * const () > } unsafe impl Send for TIM3 { } impl TIM3 { # [doc = r"Pointer to the register block"]
pub const PTR : * const tim2 :: RegisterBlock = 0x4000_0400 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const tim2 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TIM3 { type Target = tim2 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TIM3 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TIM3") . finish () } } # [doc = "General purpose timer"]
pub use self :: tim2 as tim3 ; # [doc = "General purpose timer"]
pub struct TIM4 { _marker : PhantomData < * const () > } unsafe impl Send for TIM4 { } impl TIM4 { # [doc = r"Pointer to the register block"]
pub const PTR : * const tim2 :: RegisterBlock = 0x4000_0800 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const tim2 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TIM4 { type Target = tim2 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TIM4 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TIM4") . finish () } } # [doc = "General purpose timer"]
pub use self :: tim2 as tim4 ; # [doc = "Inter integrated circuit"]
pub struct I2C1 { _marker : PhantomData < * const () > } unsafe impl Send for I2C1 { } impl I2C1 { # [doc = r"Pointer to the register block"]
pub const PTR : * const i2c1 :: RegisterBlock = 0x4000_5400 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const i2c1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for I2C1 { type Target = i2c1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for I2C1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("I2C1") . finish () } } # [doc = "Inter integrated circuit"]
pub mod i2c1 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { ctlr1 : CTLR1 , ctlr2 : CTLR2 , oaddr1 : OADDR1 , oaddr2 : OADDR2 , datar : DATAR , star1 : STAR1 , star2 : STAR2 , ckcfgr : CKCFGR , rtr : RTR , } impl RegisterBlock { # [doc = "0x00 - Control register 1"]
# [inline (always)]
pub const fn ctlr1 (& self) -> & CTLR1 { & self . ctlr1 } # [doc = "0x04 - Control register 2"]
# [inline (always)]
pub const fn ctlr2 (& self) -> & CTLR2 { & self . ctlr2 } # [doc = "0x08 - Own address register 1"]
# [inline (always)]
pub const fn oaddr1 (& self) -> & OADDR1 { & self . oaddr1 } # [doc = "0x0c - Own address register 2"]
# [inline (always)]
pub const fn oaddr2 (& self) -> & OADDR2 { & self . oaddr2 } # [doc = "0x10 - Data register"]
# [inline (always)]
pub const fn datar (& self) -> & DATAR { & self . datar } # [doc = "0x14 - Status register 1"]
# [inline (always)]
pub const fn star1 (& self) -> & STAR1 { & self . star1 } # [doc = "0x18 - Status register 2"]
# [inline (always)]
pub const fn star2 (& self) -> & STAR2 { & self . star2 } # [doc = "0x1c - Clock control register"]
# [inline (always)]
pub const fn ckcfgr (& self) -> & CKCFGR { & self . ckcfgr } # [doc = "0x20 - RTR register"]
# [inline (always)]
pub const fn rtr (& self) -> & RTR { & self . rtr } } # [doc = "CTLR1 (rw) register accessor: Control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr1`]
module"]
pub type CTLR1 = crate :: Reg < ctlr1 :: CTLR1_SPEC > ; # [doc = "Control register 1"]
pub mod ctlr1 { # [doc = "Register `CTLR1` reader"]
pub type R = crate :: R < CTLR1_SPEC > ; # [doc = "Register `CTLR1` writer"]
pub type W = crate :: W < CTLR1_SPEC > ; # [doc = "Field `PE` reader - Peripheral enable"]
pub type PE_R = crate :: BitReader ; # [doc = "Field `PE` writer - Peripheral enable"]
pub type PE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SMBUS` reader - SMBus mode"]
pub type SMBUS_R = crate :: BitReader ; # [doc = "Field `SMBUS` writer - SMBus mode"]
pub type SMBUS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SMBTYPE` reader - SMBus type"]
pub type SMBTYPE_R = crate :: BitReader ; # [doc = "Field `SMBTYPE` writer - SMBus type"]
pub type SMBTYPE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ENARP` reader - ARP enable"]
pub type ENARP_R = crate :: BitReader ; # [doc = "Field `ENARP` writer - ARP enable"]
pub type ENARP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ENPEC` reader - PEC enable"]
pub type ENPEC_R = crate :: BitReader ; # [doc = "Field `ENPEC` writer - PEC enable"]
pub type ENPEC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ENGC` reader - General call enable"]
pub type ENGC_R = crate :: BitReader ; # [doc = "Field `ENGC` writer - General call enable"]
pub type ENGC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NOSTRETCH` reader - Clock stretching disable (Slave mode)"]
pub type NOSTRETCH_R = crate :: BitReader ; # [doc = "Field `NOSTRETCH` writer - Clock stretching disable (Slave mode)"]
pub type NOSTRETCH_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `START` reader - Start generation"]
pub type START_R = crate :: BitReader ; # [doc = "Field `START` writer - Start generation"]
pub type START_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STOP` reader - Stop generation"]
pub type STOP_R = crate :: BitReader ; # [doc = "Field `STOP` writer - Stop generation"]
pub type STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ACK` reader - Acknowledge enable"]
pub type ACK_R = crate :: BitReader ; # [doc = "Field `ACK` writer - Acknowledge enable"]
pub type ACK_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `POS` reader - Acknowledge/PEC Position (for data reception)"]
pub type POS_R = crate :: BitReader ; # [doc = "Field `POS` writer - Acknowledge/PEC Position (for data reception)"]
pub type POS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PEC` reader - Packet error checking"]
pub type PEC_R = crate :: BitReader ; # [doc = "Field `PEC` writer - Packet error checking"]
pub type PEC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ALERT` reader - SMBus alert"]
pub type ALERT_R = crate :: BitReader ; # [doc = "Field `ALERT` writer - SMBus alert"]
pub type ALERT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWRST` reader - Software reset"]
pub type SWRST_R = crate :: BitReader ; # [doc = "Field `SWRST` writer - Software reset"]
pub type SWRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Peripheral enable"]
# [inline (always)]
pub fn pe (& self) -> PE_R { PE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - SMBus mode"]
# [inline (always)]
pub fn smbus (& self) -> SMBUS_R { SMBUS_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 3 - SMBus type"]
# [inline (always)]
pub fn smbtype (& self) -> SMBTYPE_R { SMBTYPE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - ARP enable"]
# [inline (always)]
pub fn enarp (& self) -> ENARP_R { ENARP_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - PEC enable"]
# [inline (always)]
pub fn enpec (& self) -> ENPEC_R { ENPEC_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - General call enable"]
# [inline (always)]
pub fn engc (& self) -> ENGC_R { ENGC_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Clock stretching disable (Slave mode)"]
# [inline (always)]
pub fn nostretch (& self) -> NOSTRETCH_R { NOSTRETCH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Start generation"]
# [inline (always)]
pub fn start (& self) -> START_R { START_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Stop generation"]
# [inline (always)]
pub fn stop (& self) -> STOP_R { STOP_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Acknowledge enable"]
# [inline (always)]
pub fn ack (& self) -> ACK_R { ACK_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Acknowledge/PEC Position (for data reception)"]
# [inline (always)]
pub fn pos (& self) -> POS_R { POS_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Packet error checking"]
# [inline (always)]
pub fn pec (& self) -> PEC_R { PEC_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - SMBus alert"]
# [inline (always)]
pub fn alert (& self) -> ALERT_R { ALERT_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 15 - Software reset"]
# [inline (always)]
pub fn swrst (& self) -> SWRST_R { SWRST_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bit 0 - Peripheral enable"]
# [inline (always)]
# [must_use]
pub fn pe (& mut self) -> PE_W < CTLR1_SPEC > { PE_W :: new (self , 0) } # [doc = "Bit 1 - SMBus mode"]
# [inline (always)]
# [must_use]
pub fn smbus (& mut self) -> SMBUS_W < CTLR1_SPEC > { SMBUS_W :: new (self , 1) } # [doc = "Bit 3 - SMBus type"]
# [inline (always)]
# [must_use]
pub fn smbtype (& mut self) -> SMBTYPE_W < CTLR1_SPEC > { SMBTYPE_W :: new (self , 3) } # [doc = "Bit 4 - ARP enable"]
# [inline (always)]
# [must_use]
pub fn enarp (& mut self) -> ENARP_W < CTLR1_SPEC > { ENARP_W :: new (self , 4) } # [doc = "Bit 5 - PEC enable"]
# [inline (always)]
# [must_use]
pub fn enpec (& mut self) -> ENPEC_W < CTLR1_SPEC > { ENPEC_W :: new (self , 5) } # [doc = "Bit 6 - General call enable"]
# [inline (always)]
# [must_use]
pub fn engc (& mut self) -> ENGC_W < CTLR1_SPEC > { ENGC_W :: new (self , 6) } # [doc = "Bit 7 - Clock stretching disable (Slave mode)"]
# [inline (always)]
# [must_use]
pub fn nostretch (& mut self) -> NOSTRETCH_W < CTLR1_SPEC > { NOSTRETCH_W :: new (self , 7) } # [doc = "Bit 8 - Start generation"]
# [inline (always)]
# [must_use]
pub fn start (& mut self) -> START_W < CTLR1_SPEC > { START_W :: new (self , 8) } # [doc = "Bit 9 - Stop generation"]
# [inline (always)]
# [must_use]
pub fn stop (& mut self) -> STOP_W < CTLR1_SPEC > { STOP_W :: new (self , 9) } # [doc = "Bit 10 - Acknowledge enable"]
# [inline (always)]
# [must_use]
pub fn ack (& mut self) -> ACK_W < CTLR1_SPEC > { ACK_W :: new (self , 10) } # [doc = "Bit 11 - Acknowledge/PEC Position (for data reception)"]
# [inline (always)]
# [must_use]
pub fn pos (& mut self) -> POS_W < CTLR1_SPEC > { POS_W :: new (self , 11) } # [doc = "Bit 12 - Packet error checking"]
# [inline (always)]
# [must_use]
pub fn pec (& mut self) -> PEC_W < CTLR1_SPEC > { PEC_W :: new (self , 12) } # [doc = "Bit 13 - SMBus alert"]
# [inline (always)]
# [must_use]
pub fn alert (& mut self) -> ALERT_W < CTLR1_SPEC > { ALERT_W :: new (self , 13) } # [doc = "Bit 15 - Software reset"]
# [inline (always)]
# [must_use]
pub fn swrst (& mut self) -> SWRST_W < CTLR1_SPEC > { SWRST_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR1_SPEC ; impl crate :: RegisterSpec for CTLR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr1::R`](R) reader structure"]
impl crate :: Readable for CTLR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr1::W`](W) writer structure"]
impl crate :: Writable for CTLR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR1 to value 0"]
impl crate :: Resettable for CTLR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTLR2 (rw) register accessor: Control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr2`]
module"]
pub type CTLR2 = crate :: Reg < ctlr2 :: CTLR2_SPEC > ; # [doc = "Control register 2"]
pub mod ctlr2 { # [doc = "Register `CTLR2` reader"]
pub type R = crate :: R < CTLR2_SPEC > ; # [doc = "Register `CTLR2` writer"]
pub type W = crate :: W < CTLR2_SPEC > ; # [doc = "Field `FREQ` reader - Peripheral clock frequency"]
pub type FREQ_R = crate :: FieldReader ; # [doc = "Field `FREQ` writer - Peripheral clock frequency"]
pub type FREQ_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; # [doc = "Field `ITERREN` reader - Error interrupt enable"]
pub type ITERREN_R = crate :: BitReader ; # [doc = "Field `ITERREN` writer - Error interrupt enable"]
pub type ITERREN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ITEVTEN` reader - Event interrupt enable"]
pub type ITEVTEN_R = crate :: BitReader ; # [doc = "Field `ITEVTEN` writer - Event interrupt enable"]
pub type ITEVTEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ITBUFEN` reader - Buffer interrupt enable"]
pub type ITBUFEN_R = crate :: BitReader ; # [doc = "Field `ITBUFEN` writer - Buffer interrupt enable"]
pub type ITBUFEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DMAEN` reader - DMA requests enable"]
pub type DMAEN_R = crate :: BitReader ; # [doc = "Field `DMAEN` writer - DMA requests enable"]
pub type DMAEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LAST` reader - DMA last transfer"]
pub type LAST_R = crate :: BitReader ; # [doc = "Field `LAST` writer - DMA last transfer"]
pub type LAST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:5 - Peripheral clock frequency"]
# [inline (always)]
pub fn freq (& self) -> FREQ_R { FREQ_R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bit 8 - Error interrupt enable"]
# [inline (always)]
pub fn iterren (& self) -> ITERREN_R { ITERREN_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Event interrupt enable"]
# [inline (always)]
pub fn itevten (& self) -> ITEVTEN_R { ITEVTEN_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Buffer interrupt enable"]
# [inline (always)]
pub fn itbufen (& self) -> ITBUFEN_R { ITBUFEN_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DMA requests enable"]
# [inline (always)]
pub fn dmaen (& self) -> DMAEN_R { DMAEN_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DMA last transfer"]
# [inline (always)]
pub fn last (& self) -> LAST_R { LAST_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:5 - Peripheral clock frequency"]
# [inline (always)]
# [must_use]
pub fn freq (& mut self) -> FREQ_W < CTLR2_SPEC > { FREQ_W :: new (self , 0) } # [doc = "Bit 8 - Error interrupt enable"]
# [inline (always)]
# [must_use]
pub fn iterren (& mut self) -> ITERREN_W < CTLR2_SPEC > { ITERREN_W :: new (self , 8) } # [doc = "Bit 9 - Event interrupt enable"]
# [inline (always)]
# [must_use]
pub fn itevten (& mut self) -> ITEVTEN_W < CTLR2_SPEC > { ITEVTEN_W :: new (self , 9) } # [doc = "Bit 10 - Buffer interrupt enable"]
# [inline (always)]
# [must_use]
pub fn itbufen (& mut self) -> ITBUFEN_W < CTLR2_SPEC > { ITBUFEN_W :: new (self , 10) } # [doc = "Bit 11 - DMA requests enable"]
# [inline (always)]
# [must_use]
pub fn dmaen (& mut self) -> DMAEN_W < CTLR2_SPEC > { DMAEN_W :: new (self , 11) } # [doc = "Bit 12 - DMA last transfer"]
# [inline (always)]
# [must_use]
pub fn last (& mut self) -> LAST_W < CTLR2_SPEC > { LAST_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR2_SPEC ; impl crate :: RegisterSpec for CTLR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr2::R`](R) reader structure"]
impl crate :: Readable for CTLR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr2::W`](W) writer structure"]
impl crate :: Writable for CTLR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR2 to value 0"]
impl crate :: Resettable for CTLR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "OADDR1 (rw) register accessor: Own address register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oaddr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oaddr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@oaddr1`]
module"]
pub type OADDR1 = crate :: Reg < oaddr1 :: OADDR1_SPEC > ; # [doc = "Own address register 1"]
pub mod oaddr1 { # [doc = "Register `OADDR1` reader"]
pub type R = crate :: R < OADDR1_SPEC > ; # [doc = "Register `OADDR1` writer"]
pub type W = crate :: W < OADDR1_SPEC > ; # [doc = "Field `ADD0` reader - Interface address"]
pub type ADD0_R = crate :: BitReader ; # [doc = "Field `ADD0` writer - Interface address"]
pub type ADD0_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADD7_1` reader - Interface address"]
pub type ADD7_1_R = crate :: FieldReader ; # [doc = "Field `ADD7_1` writer - Interface address"]
pub type ADD7_1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `ADD9_8` reader - Interface address"]
pub type ADD9_8_R = crate :: FieldReader ; # [doc = "Field `ADD9_8` writer - Interface address"]
pub type ADD9_8_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MUST1` reader - must set 1 bit"]
pub type MUST1_R = crate :: BitReader ; # [doc = "Field `MUST1` writer - must set 1 bit"]
pub type MUST1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADDMODE` reader - Addressing mode (slave mode)"]
pub type ADDMODE_R = crate :: BitReader ; # [doc = "Field `ADDMODE` writer - Addressing mode (slave mode)"]
pub type ADDMODE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Interface address"]
# [inline (always)]
pub fn add0 (& self) -> ADD0_R { ADD0_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - Interface address"]
# [inline (always)]
pub fn add7_1 (& self) -> ADD7_1_R { ADD7_1_R :: new (((self . bits >> 1) & 0x7f) as u8) } # [doc = "Bits 8:9 - Interface address"]
# [inline (always)]
pub fn add9_8 (& self) -> ADD9_8_R { ADD9_8_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 14 - must set 1 bit"]
# [inline (always)]
pub fn must1 (& self) -> MUST1_R { MUST1_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Addressing mode (slave mode)"]
# [inline (always)]
pub fn addmode (& self) -> ADDMODE_R { ADDMODE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bit 0 - Interface address"]
# [inline (always)]
# [must_use]
pub fn add0 (& mut self) -> ADD0_W < OADDR1_SPEC > { ADD0_W :: new (self , 0) } # [doc = "Bits 1:7 - Interface address"]
# [inline (always)]
# [must_use]
pub fn add7_1 (& mut self) -> ADD7_1_W < OADDR1_SPEC > { ADD7_1_W :: new (self , 1) } # [doc = "Bits 8:9 - Interface address"]
# [inline (always)]
# [must_use]
pub fn add9_8 (& mut self) -> ADD9_8_W < OADDR1_SPEC > { ADD9_8_W :: new (self , 8) } # [doc = "Bit 14 - must set 1 bit"]
# [inline (always)]
# [must_use]
pub fn must1 (& mut self) -> MUST1_W < OADDR1_SPEC > { MUST1_W :: new (self , 14) } # [doc = "Bit 15 - Addressing mode (slave mode)"]
# [inline (always)]
# [must_use]
pub fn addmode (& mut self) -> ADDMODE_W < OADDR1_SPEC > { ADDMODE_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Own address register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oaddr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oaddr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OADDR1_SPEC ; impl crate :: RegisterSpec for OADDR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`oaddr1::R`](R) reader structure"]
impl crate :: Readable for OADDR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`oaddr1::W`](W) writer structure"]
impl crate :: Writable for OADDR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets OADDR1 to value 0"]
impl crate :: Resettable for OADDR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "OADDR2 (rw) register accessor: Own address register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oaddr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oaddr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@oaddr2`]
module"]
pub type OADDR2 = crate :: Reg < oaddr2 :: OADDR2_SPEC > ; # [doc = "Own address register 2"]
pub mod oaddr2 { # [doc = "Register `OADDR2` reader"]
pub type R = crate :: R < OADDR2_SPEC > ; # [doc = "Register `OADDR2` writer"]
pub type W = crate :: W < OADDR2_SPEC > ; # [doc = "Field `ENDUAL` reader - Dual addressing mode enable"]
pub type ENDUAL_R = crate :: BitReader ; # [doc = "Field `ENDUAL` writer - Dual addressing mode enable"]
pub type ENDUAL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ADD2` reader - Interface address"]
pub type ADD2_R = crate :: FieldReader ; # [doc = "Field `ADD2` writer - Interface address"]
pub type ADD2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; impl R { # [doc = "Bit 0 - Dual addressing mode enable"]
# [inline (always)]
pub fn endual (& self) -> ENDUAL_R { ENDUAL_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - Interface address"]
# [inline (always)]
pub fn add2 (& self) -> ADD2_R { ADD2_R :: new (((self . bits >> 1) & 0x7f) as u8) } } impl W { # [doc = "Bit 0 - Dual addressing mode enable"]
# [inline (always)]
# [must_use]
pub fn endual (& mut self) -> ENDUAL_W < OADDR2_SPEC > { ENDUAL_W :: new (self , 0) } # [doc = "Bits 1:7 - Interface address"]
# [inline (always)]
# [must_use]
pub fn add2 (& mut self) -> ADD2_W < OADDR2_SPEC > { ADD2_W :: new (self , 1) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Own address register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oaddr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oaddr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OADDR2_SPEC ; impl crate :: RegisterSpec for OADDR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`oaddr2::R`](R) reader structure"]
impl crate :: Readable for OADDR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`oaddr2::W`](W) writer structure"]
impl crate :: Writable for OADDR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets OADDR2 to value 0"]
impl crate :: Resettable for OADDR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DATAR (rw) register accessor: Data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar`]
module"]
pub type DATAR = crate :: Reg < datar :: DATAR_SPEC > ; # [doc = "Data register"]
pub mod datar { # [doc = "Register `DATAR` reader"]
pub type R = crate :: R < DATAR_SPEC > ; # [doc = "Register `DATAR` writer"]
pub type W = crate :: W < DATAR_SPEC > ; # [doc = "Field `DR` reader - 8-bit data register"]
pub type DR_R = crate :: FieldReader ; # [doc = "Field `DR` writer - 8-bit data register"]
pub type DR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - 8-bit data register"]
# [inline (always)]
pub fn dr (& self) -> DR_R { DR_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - 8-bit data register"]
# [inline (always)]
# [must_use]
pub fn dr (& mut self) -> DR_W < DATAR_SPEC > { DR_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR_SPEC ; impl crate :: RegisterSpec for DATAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar::R`](R) reader structure"]
impl crate :: Readable for DATAR_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar::W`](W) writer structure"]
impl crate :: Writable for DATAR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR to value 0"]
impl crate :: Resettable for DATAR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "STAR1 (rw) register accessor: Status register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`star1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`star1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@star1`]
module"]
pub type STAR1 = crate :: Reg < star1 :: STAR1_SPEC > ; # [doc = "Status register 1"]
pub mod star1 { # [doc = "Register `STAR1` reader"]
pub type R = crate :: R < STAR1_SPEC > ; # [doc = "Register `STAR1` writer"]
pub type W = crate :: W < STAR1_SPEC > ; # [doc = "Field `SB` reader - Start bit (Master mode)"]
pub type SB_R = crate :: BitReader ; # [doc = "Field `ADDR` reader - Address sent (master mode)/matched (slave mode)"]
pub type ADDR_R = crate :: BitReader ; # [doc = "Field `BTF` reader - Byte transfer finished"]
pub type BTF_R = crate :: BitReader ; # [doc = "Field `ADD10` reader - 10-bit header sent (Master mode)"]
pub type ADD10_R = crate :: BitReader ; # [doc = "Field `STOPF` reader - Stop detection (slave mode)"]
pub type STOPF_R = crate :: BitReader ; # [doc = "Field `RxNE` reader - Data register not empty (receivers)"]
pub type RX_NE_R = crate :: BitReader ; # [doc = "Field `TxE` reader - Data register empty (transmitters)"]
pub type TX_E_R = crate :: BitReader ; # [doc = "Field `BERR` reader - Bus error"]
pub type BERR_R = crate :: BitReader ; # [doc = "Field `BERR` writer - Bus error"]
pub type BERR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ARLO` reader - Arbitration lost (master mode)"]
pub type ARLO_R = crate :: BitReader ; # [doc = "Field `ARLO` writer - Arbitration lost (master mode)"]
pub type ARLO_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `AF` reader - Acknowledge failure"]
pub type AF_R = crate :: BitReader ; # [doc = "Field `AF` writer - Acknowledge failure"]
pub type AF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OVR` reader - Overrun/Underrun"]
pub type OVR_R = crate :: BitReader ; # [doc = "Field `OVR` writer - Overrun/Underrun"]
pub type OVR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PECERR` reader - PEC Error in reception"]
pub type PECERR_R = crate :: BitReader ; # [doc = "Field `PECERR` writer - PEC Error in reception"]
pub type PECERR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TIMEOUT` reader - Timeout or Tlow error"]
pub type TIMEOUT_R = crate :: BitReader ; # [doc = "Field `TIMEOUT` writer - Timeout or Tlow error"]
pub type TIMEOUT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SMBALERT` reader - SMBus alert"]
pub type SMBALERT_R = crate :: BitReader ; # [doc = "Field `SMBALERT` writer - SMBus alert"]
pub type SMBALERT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Start bit (Master mode)"]
# [inline (always)]
pub fn sb (& self) -> SB_R { SB_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Address sent (master mode)/matched (slave mode)"]
# [inline (always)]
pub fn addr (& self) -> ADDR_R { ADDR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Byte transfer finished"]
# [inline (always)]
pub fn btf (& self) -> BTF_R { BTF_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - 10-bit header sent (Master mode)"]
# [inline (always)]
pub fn add10 (& self) -> ADD10_R { ADD10_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Stop detection (slave mode)"]
# [inline (always)]
pub fn stopf (& self) -> STOPF_R { STOPF_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 6 - Data register not empty (receivers)"]
# [inline (always)]
pub fn rx_ne (& self) -> RX_NE_R { RX_NE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Data register empty (transmitters)"]
# [inline (always)]
pub fn tx_e (& self) -> TX_E_R { TX_E_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Bus error"]
# [inline (always)]
pub fn berr (& self) -> BERR_R { BERR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Arbitration lost (master mode)"]
# [inline (always)]
pub fn arlo (& self) -> ARLO_R { ARLO_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Acknowledge failure"]
# [inline (always)]
pub fn af (& self) -> AF_R { AF_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Overrun/Underrun"]
# [inline (always)]
pub fn ovr (& self) -> OVR_R { OVR_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - PEC Error in reception"]
# [inline (always)]
pub fn pecerr (& self) -> PECERR_R { PECERR_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 14 - Timeout or Tlow error"]
# [inline (always)]
pub fn timeout (& self) -> TIMEOUT_R { TIMEOUT_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - SMBus alert"]
# [inline (always)]
pub fn smbalert (& self) -> SMBALERT_R { SMBALERT_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bit 8 - Bus error"]
# [inline (always)]
# [must_use]
pub fn berr (& mut self) -> BERR_W < STAR1_SPEC > { BERR_W :: new (self , 8) } # [doc = "Bit 9 - Arbitration lost (master mode)"]
# [inline (always)]
# [must_use]
pub fn arlo (& mut self) -> ARLO_W < STAR1_SPEC > { ARLO_W :: new (self , 9) } # [doc = "Bit 10 - Acknowledge failure"]
# [inline (always)]
# [must_use]
pub fn af (& mut self) -> AF_W < STAR1_SPEC > { AF_W :: new (self , 10) } # [doc = "Bit 11 - Overrun/Underrun"]
# [inline (always)]
# [must_use]
pub fn ovr (& mut self) -> OVR_W < STAR1_SPEC > { OVR_W :: new (self , 11) } # [doc = "Bit 12 - PEC Error in reception"]
# [inline (always)]
# [must_use]
pub fn pecerr (& mut self) -> PECERR_W < STAR1_SPEC > { PECERR_W :: new (self , 12) } # [doc = "Bit 14 - Timeout or Tlow error"]
# [inline (always)]
# [must_use]
pub fn timeout (& mut self) -> TIMEOUT_W < STAR1_SPEC > { TIMEOUT_W :: new (self , 14) } # [doc = "Bit 15 - SMBus alert"]
# [inline (always)]
# [must_use]
pub fn smbalert (& mut self) -> SMBALERT_W < STAR1_SPEC > { SMBALERT_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Status register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`star1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`star1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAR1_SPEC ; impl crate :: RegisterSpec for STAR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`star1::R`](R) reader structure"]
impl crate :: Readable for STAR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`star1::W`](W) writer structure"]
impl crate :: Writable for STAR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets STAR1 to value 0"]
impl crate :: Resettable for STAR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "STAR2 (r) register accessor: Status register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`star2::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@star2`]
module"]
pub type STAR2 = crate :: Reg < star2 :: STAR2_SPEC > ; # [doc = "Status register 2"]
pub mod star2 { # [doc = "Register `STAR2` reader"]
pub type R = crate :: R < STAR2_SPEC > ; # [doc = "Field `MSL` reader - Master/slave"]
pub type MSL_R = crate :: BitReader ; # [doc = "Field `BUSY` reader - Bus busy"]
pub type BUSY_R = crate :: BitReader ; # [doc = "Field `TRA` reader - Transmitter/receiver"]
pub type TRA_R = crate :: BitReader ; # [doc = "Field `GENCALL` reader - General call address (Slave mode)"]
pub type GENCALL_R = crate :: BitReader ; # [doc = "Field `SMBDEFAULT` reader - SMBus device default address (Slave mode)"]
pub type SMBDEFAULT_R = crate :: BitReader ; # [doc = "Field `SMBHOST` reader - SMBus host header (Slave mode)"]
pub type SMBHOST_R = crate :: BitReader ; # [doc = "Field `DUALF` reader - Dual flag (Slave mode)"]
pub type DUALF_R = crate :: BitReader ; # [doc = "Field `PEC` reader - acket error checking register"]
pub type PEC_R = crate :: FieldReader ; impl R { # [doc = "Bit 0 - Master/slave"]
# [inline (always)]
pub fn msl (& self) -> MSL_R { MSL_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Bus busy"]
# [inline (always)]
pub fn busy (& self) -> BUSY_R { BUSY_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Transmitter/receiver"]
# [inline (always)]
pub fn tra (& self) -> TRA_R { TRA_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 4 - General call address (Slave mode)"]
# [inline (always)]
pub fn gencall (& self) -> GENCALL_R { GENCALL_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - SMBus device default address (Slave mode)"]
# [inline (always)]
pub fn smbdefault (& self) -> SMBDEFAULT_R { SMBDEFAULT_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - SMBus host header (Slave mode)"]
# [inline (always)]
pub fn smbhost (& self) -> SMBHOST_R { SMBHOST_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Dual flag (Slave mode)"]
# [inline (always)]
pub fn dualf (& self) -> DUALF_R { DUALF_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:15 - acket error checking register"]
# [inline (always)]
pub fn pec (& self) -> PEC_R { PEC_R :: new (((self . bits >> 8) & 0xff) as u8) } } # [doc = "Status register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`star2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAR2_SPEC ; impl crate :: RegisterSpec for STAR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`star2::R`](R) reader structure"]
impl crate :: Readable for STAR2_SPEC { } # [doc = "`reset()` method sets STAR2 to value 0"]
impl crate :: Resettable for STAR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CKCFGR (rw) register accessor: Clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ckcfgr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ckcfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ckcfgr`]
module"]
pub type CKCFGR = crate :: Reg < ckcfgr :: CKCFGR_SPEC > ; # [doc = "Clock control register"]
pub mod ckcfgr { # [doc = "Register `CKCFGR` reader"]
pub type R = crate :: R < CKCFGR_SPEC > ; # [doc = "Register `CKCFGR` writer"]
pub type W = crate :: W < CKCFGR_SPEC > ; # [doc = "Field `CCR` reader - Clock control register in Fast/Standard mode (Master mode)"]
pub type CCR_R = crate :: FieldReader < u16 > ; # [doc = "Field `CCR` writer - Clock control register in Fast/Standard mode (Master mode)"]
pub type CCR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; # [doc = "Field `DUTY` reader - Fast mode duty cycle"]
pub type DUTY_R = crate :: BitReader ; # [doc = "Field `DUTY` writer - Fast mode duty cycle"]
pub type DUTY_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `F_S` reader - I2C master mode selection"]
pub type F_S_R = crate :: BitReader ; # [doc = "Field `F_S` writer - I2C master mode selection"]
pub type F_S_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)"]
# [inline (always)]
pub fn ccr (& self) -> CCR_R { CCR_R :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bit 14 - Fast mode duty cycle"]
# [inline (always)]
pub fn duty (& self) -> DUTY_R { DUTY_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - I2C master mode selection"]
# [inline (always)]
pub fn f_s (& self) -> F_S_R { F_S_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)"]
# [inline (always)]
# [must_use]
pub fn ccr (& mut self) -> CCR_W < CKCFGR_SPEC > { CCR_W :: new (self , 0) } # [doc = "Bit 14 - Fast mode duty cycle"]
# [inline (always)]
# [must_use]
pub fn duty (& mut self) -> DUTY_W < CKCFGR_SPEC > { DUTY_W :: new (self , 14) } # [doc = "Bit 15 - I2C master mode selection"]
# [inline (always)]
# [must_use]
pub fn f_s (& mut self) -> F_S_W < CKCFGR_SPEC > { F_S_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ckcfgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ckcfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CKCFGR_SPEC ; impl crate :: RegisterSpec for CKCFGR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ckcfgr::R`](R) reader structure"]
impl crate :: Readable for CKCFGR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ckcfgr::W`](W) writer structure"]
impl crate :: Writable for CKCFGR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CKCFGR to value 0"]
impl crate :: Resettable for CKCFGR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "RTR (rw) register accessor: RTR register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtr`]
module"]
pub type RTR = crate :: Reg < rtr :: RTR_SPEC > ; # [doc = "RTR register"]
pub mod rtr { # [doc = "Register `RTR` reader"]
pub type R = crate :: R < RTR_SPEC > ; # [doc = "Register `RTR` writer"]
pub type W = crate :: W < RTR_SPEC > ; # [doc = "Field `TRISE` reader - Maximum rise time in Fast/Standard mode (Master mode)"]
pub type TRISE_R = crate :: FieldReader ; # [doc = "Field `TRISE` writer - Maximum rise time in Fast/Standard mode (Master mode)"]
pub type TRISE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 6 > ; impl R { # [doc = "Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)"]
# [inline (always)]
pub fn trise (& self) -> TRISE_R { TRISE_R :: new ((self . bits & 0x3f) as u8) } } impl W { # [doc = "Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)"]
# [inline (always)]
# [must_use]
pub fn trise (& mut self) -> TRISE_W < RTR_SPEC > { TRISE_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "RTR register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RTR_SPEC ; impl crate :: RegisterSpec for RTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rtr::R`](R) reader structure"]
impl crate :: Readable for RTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`rtr::W`](W) writer structure"]
impl crate :: Writable for RTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RTR to value 0x02"]
impl crate :: Resettable for RTR_SPEC { const RESET_VALUE : u32 = 0x02 ; } } } # [doc = "Inter integrated circuit"]
pub struct I2C2 { _marker : PhantomData < * const () > } unsafe impl Send for I2C2 { } impl I2C2 { # [doc = r"Pointer to the register block"]
pub const PTR : * const i2c1 :: RegisterBlock = 0x4000_5800 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const i2c1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for I2C2 { type Target = i2c1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for I2C2 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("I2C2") . finish () } } # [doc = "Inter integrated circuit"]
pub use self :: i2c1 as i2c2 ; # [doc = "Serial peripheral interface"]
pub struct SPI1 { _marker : PhantomData < * const () > } unsafe impl Send for SPI1 { } impl SPI1 { # [doc = r"Pointer to the register block"]
pub const PTR : * const spi1 :: RegisterBlock = 0x4001_3000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const spi1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for SPI1 { type Target = spi1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for SPI1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("SPI1") . finish () } } # [doc = "Serial peripheral interface"]
pub mod spi1 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { ctlr1 : CTLR1 , ctlr2 : CTLR2 , statr : STATR , datar : DATAR , crcr : CRCR , rcrcr : RCRCR , tcrcr : TCRCR , i2scfgr : I2SCFGR , i2spr : I2SPR , } impl RegisterBlock { # [doc = "0x00 - control register 1"]
# [inline (always)]
pub const fn ctlr1 (& self) -> & CTLR1 { & self . ctlr1 } # [doc = "0x04 - control register 2"]
# [inline (always)]
pub const fn ctlr2 (& self) -> & CTLR2 { & self . ctlr2 } # [doc = "0x08 - status register"]
# [inline (always)]
pub const fn statr (& self) -> & STATR { & self . statr } # [doc = "0x0c - data register"]
# [inline (always)]
pub const fn datar (& self) -> & DATAR { & self . datar } # [doc = "0x10 - CRCR polynomial register"]
# [inline (always)]
pub const fn crcr (& self) -> & CRCR { & self . crcr } # [doc = "0x14 - RX CRC register"]
# [inline (always)]
pub const fn rcrcr (& self) -> & RCRCR { & self . rcrcr } # [doc = "0x18 - TX CRC register"]
# [inline (always)]
pub const fn tcrcr (& self) -> & TCRCR { & self . tcrcr } # [doc = "0x1c - I2S configuration register"]
# [inline (always)]
pub const fn i2scfgr (& self) -> & I2SCFGR { & self . i2scfgr } # [doc = "0x20 - I2S prescaler register"]
# [inline (always)]
pub const fn i2spr (& self) -> & I2SPR { & self . i2spr } } # [doc = "CTLR1 (rw) register accessor: control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr1`]
module"]
pub type CTLR1 = crate :: Reg < ctlr1 :: CTLR1_SPEC > ; # [doc = "control register 1"]
pub mod ctlr1 { # [doc = "Register `CTLR1` reader"]
pub type R = crate :: R < CTLR1_SPEC > ; # [doc = "Register `CTLR1` writer"]
pub type W = crate :: W < CTLR1_SPEC > ; # [doc = "Field `CPHA` reader - Clock phase"]
pub type CPHA_R = crate :: BitReader ; # [doc = "Field `CPHA` writer - Clock phase"]
pub type CPHA_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CPOL` reader - Clock polarity"]
pub type CPOL_R = crate :: BitReader ; # [doc = "Field `CPOL` writer - Clock polarity"]
pub type CPOL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MSTR` reader - Master selection"]
pub type MSTR_R = crate :: BitReader ; # [doc = "Field `MSTR` writer - Master selection"]
pub type MSTR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BR` reader - Baud rate control"]
pub type BR_R = crate :: FieldReader ; # [doc = "Field `BR` writer - Baud rate control"]
pub type BR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SPE` reader - SPI enable"]
pub type SPE_R = crate :: BitReader ; # [doc = "Field `SPE` writer - SPI enable"]
pub type SPE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LSBFIRST` reader - Frame format"]
pub type LSBFIRST_R = crate :: BitReader ; # [doc = "Field `LSBFIRST` writer - Frame format"]
pub type LSBFIRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SSI` reader - Internal slave select"]
pub type SSI_R = crate :: BitReader ; # [doc = "Field `SSI` writer - Internal slave select"]
pub type SSI_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SSM` reader - Software slave management"]
pub type SSM_R = crate :: BitReader ; # [doc = "Field `SSM` writer - Software slave management"]
pub type SSM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXONLY` reader - Receive only"]
pub type RXONLY_R = crate :: BitReader ; # [doc = "Field `RXONLY` writer - Receive only"]
pub type RXONLY_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DFF` reader - Data frame format"]
pub type DFF_R = crate :: BitReader ; # [doc = "Field `DFF` writer - Data frame format"]
pub type DFF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CRCNEXT` reader - CRC transfer next"]
pub type CRCNEXT_R = crate :: BitReader ; # [doc = "Field `CRCNEXT` writer - CRC transfer next"]
pub type CRCNEXT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CRCEN` reader - Hardware CRC calculation enable"]
pub type CRCEN_R = crate :: BitReader ; # [doc = "Field `CRCEN` writer - Hardware CRC calculation enable"]
pub type CRCEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BIDIOE` reader - Output enable in bidirectional mode"]
pub type BIDIOE_R = crate :: BitReader ; # [doc = "Field `BIDIOE` writer - Output enable in bidirectional mode"]
pub type BIDIOE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BIDIMODE` reader - Bidirectional data mode enable"]
pub type BIDIMODE_R = crate :: BitReader ; # [doc = "Field `BIDIMODE` writer - Bidirectional data mode enable"]
pub type BIDIMODE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Clock phase"]
# [inline (always)]
pub fn cpha (& self) -> CPHA_R { CPHA_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Clock polarity"]
# [inline (always)]
pub fn cpol (& self) -> CPOL_R { CPOL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Master selection"]
# [inline (always)]
pub fn mstr (& self) -> MSTR_R { MSTR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:5 - Baud rate control"]
# [inline (always)]
pub fn br (& self) -> BR_R { BR_R :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bit 6 - SPI enable"]
# [inline (always)]
pub fn spe (& self) -> SPE_R { SPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Frame format"]
# [inline (always)]
pub fn lsbfirst (& self) -> LSBFIRST_R { LSBFIRST_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Internal slave select"]
# [inline (always)]
pub fn ssi (& self) -> SSI_R { SSI_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Software slave management"]
# [inline (always)]
pub fn ssm (& self) -> SSM_R { SSM_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Receive only"]
# [inline (always)]
pub fn rxonly (& self) -> RXONLY_R { RXONLY_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Data frame format"]
# [inline (always)]
pub fn dff (& self) -> DFF_R { DFF_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - CRC transfer next"]
# [inline (always)]
pub fn crcnext (& self) -> CRCNEXT_R { CRCNEXT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Hardware CRC calculation enable"]
# [inline (always)]
pub fn crcen (& self) -> CRCEN_R { CRCEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Output enable in bidirectional mode"]
# [inline (always)]
pub fn bidioe (& self) -> BIDIOE_R { BIDIOE_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Bidirectional data mode enable"]
# [inline (always)]
pub fn bidimode (& self) -> BIDIMODE_R { BIDIMODE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bit 0 - Clock phase"]
# [inline (always)]
# [must_use]
pub fn cpha (& mut self) -> CPHA_W < CTLR1_SPEC > { CPHA_W :: new (self , 0) } # [doc = "Bit 1 - Clock polarity"]
# [inline (always)]
# [must_use]
pub fn cpol (& mut self) -> CPOL_W < CTLR1_SPEC > { CPOL_W :: new (self , 1) } # [doc = "Bit 2 - Master selection"]
# [inline (always)]
# [must_use]
pub fn mstr (& mut self) -> MSTR_W < CTLR1_SPEC > { MSTR_W :: new (self , 2) } # [doc = "Bits 3:5 - Baud rate control"]
# [inline (always)]
# [must_use]
pub fn br (& mut self) -> BR_W < CTLR1_SPEC > { BR_W :: new (self , 3) } # [doc = "Bit 6 - SPI enable"]
# [inline (always)]
# [must_use]
pub fn spe (& mut self) -> SPE_W < CTLR1_SPEC > { SPE_W :: new (self , 6) } # [doc = "Bit 7 - Frame format"]
# [inline (always)]
# [must_use]
pub fn lsbfirst (& mut self) -> LSBFIRST_W < CTLR1_SPEC > { LSBFIRST_W :: new (self , 7) } # [doc = "Bit 8 - Internal slave select"]
# [inline (always)]
# [must_use]
pub fn ssi (& mut self) -> SSI_W < CTLR1_SPEC > { SSI_W :: new (self , 8) } # [doc = "Bit 9 - Software slave management"]
# [inline (always)]
# [must_use]
pub fn ssm (& mut self) -> SSM_W < CTLR1_SPEC > { SSM_W :: new (self , 9) } # [doc = "Bit 10 - Receive only"]
# [inline (always)]
# [must_use]
pub fn rxonly (& mut self) -> RXONLY_W < CTLR1_SPEC > { RXONLY_W :: new (self , 10) } # [doc = "Bit 11 - Data frame format"]
# [inline (always)]
# [must_use]
pub fn dff (& mut self) -> DFF_W < CTLR1_SPEC > { DFF_W :: new (self , 11) } # [doc = "Bit 12 - CRC transfer next"]
# [inline (always)]
# [must_use]
pub fn crcnext (& mut self) -> CRCNEXT_W < CTLR1_SPEC > { CRCNEXT_W :: new (self , 12) } # [doc = "Bit 13 - Hardware CRC calculation enable"]
# [inline (always)]
# [must_use]
pub fn crcen (& mut self) -> CRCEN_W < CTLR1_SPEC > { CRCEN_W :: new (self , 13) } # [doc = "Bit 14 - Output enable in bidirectional mode"]
# [inline (always)]
# [must_use]
pub fn bidioe (& mut self) -> BIDIOE_W < CTLR1_SPEC > { BIDIOE_W :: new (self , 14) } # [doc = "Bit 15 - Bidirectional data mode enable"]
# [inline (always)]
# [must_use]
pub fn bidimode (& mut self) -> BIDIMODE_W < CTLR1_SPEC > { BIDIMODE_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR1_SPEC ; impl crate :: RegisterSpec for CTLR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr1::R`](R) reader structure"]
impl crate :: Readable for CTLR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr1::W`](W) writer structure"]
impl crate :: Writable for CTLR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR1 to value 0"]
impl crate :: Resettable for CTLR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTLR2 (rw) register accessor: control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr2`]
module"]
pub type CTLR2 = crate :: Reg < ctlr2 :: CTLR2_SPEC > ; # [doc = "control register 2"]
pub mod ctlr2 { # [doc = "Register `CTLR2` reader"]
pub type R = crate :: R < CTLR2_SPEC > ; # [doc = "Register `CTLR2` writer"]
pub type W = crate :: W < CTLR2_SPEC > ; # [doc = "Field `RXDMAEN` reader - Rx buffer DMA enable"]
pub type RXDMAEN_R = crate :: BitReader ; # [doc = "Field `RXDMAEN` writer - Rx buffer DMA enable"]
pub type RXDMAEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXDMAEN` reader - Tx buffer DMA enable"]
pub type TXDMAEN_R = crate :: BitReader ; # [doc = "Field `TXDMAEN` writer - Tx buffer DMA enable"]
pub type TXDMAEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SSOE` reader - SS output enable"]
pub type SSOE_R = crate :: BitReader ; # [doc = "Field `SSOE` writer - SS output enable"]
pub type SSOE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERRIE` reader - Error interrupt enable"]
pub type ERRIE_R = crate :: BitReader ; # [doc = "Field `ERRIE` writer - Error interrupt enable"]
pub type ERRIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXNEIE` reader - RX buffer not empty interrupt enable"]
pub type RXNEIE_R = crate :: BitReader ; # [doc = "Field `RXNEIE` writer - RX buffer not empty interrupt enable"]
pub type RXNEIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXEIE` reader - Tx buffer empty interrupt enable"]
pub type TXEIE_R = crate :: BitReader ; # [doc = "Field `TXEIE` writer - Tx buffer empty interrupt enable"]
pub type TXEIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Rx buffer DMA enable"]
# [inline (always)]
pub fn rxdmaen (& self) -> RXDMAEN_R { RXDMAEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Tx buffer DMA enable"]
# [inline (always)]
pub fn txdmaen (& self) -> TXDMAEN_R { TXDMAEN_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - SS output enable"]
# [inline (always)]
pub fn ssoe (& self) -> SSOE_R { SSOE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - Error interrupt enable"]
# [inline (always)]
pub fn errie (& self) -> ERRIE_R { ERRIE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - RX buffer not empty interrupt enable"]
# [inline (always)]
pub fn rxneie (& self) -> RXNEIE_R { RXNEIE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Tx buffer empty interrupt enable"]
# [inline (always)]
pub fn txeie (& self) -> TXEIE_R { TXEIE_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bit 0 - Rx buffer DMA enable"]
# [inline (always)]
# [must_use]
pub fn rxdmaen (& mut self) -> RXDMAEN_W < CTLR2_SPEC > { RXDMAEN_W :: new (self , 0) } # [doc = "Bit 1 - Tx buffer DMA enable"]
# [inline (always)]
# [must_use]
pub fn txdmaen (& mut self) -> TXDMAEN_W < CTLR2_SPEC > { TXDMAEN_W :: new (self , 1) } # [doc = "Bit 2 - SS output enable"]
# [inline (always)]
# [must_use]
pub fn ssoe (& mut self) -> SSOE_W < CTLR2_SPEC > { SSOE_W :: new (self , 2) } # [doc = "Bit 5 - Error interrupt enable"]
# [inline (always)]
# [must_use]
pub fn errie (& mut self) -> ERRIE_W < CTLR2_SPEC > { ERRIE_W :: new (self , 5) } # [doc = "Bit 6 - RX buffer not empty interrupt enable"]
# [inline (always)]
# [must_use]
pub fn rxneie (& mut self) -> RXNEIE_W < CTLR2_SPEC > { RXNEIE_W :: new (self , 6) } # [doc = "Bit 7 - Tx buffer empty interrupt enable"]
# [inline (always)]
# [must_use]
pub fn txeie (& mut self) -> TXEIE_W < CTLR2_SPEC > { TXEIE_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR2_SPEC ; impl crate :: RegisterSpec for CTLR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr2::R`](R) reader structure"]
impl crate :: Readable for CTLR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr2::W`](W) writer structure"]
impl crate :: Writable for CTLR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR2 to value 0"]
impl crate :: Resettable for CTLR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "STATR (rw) register accessor: status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`statr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@statr`]
module"]
pub type STATR = crate :: Reg < statr :: STATR_SPEC > ; # [doc = "status register"]
pub mod statr { # [doc = "Register `STATR` reader"]
pub type R = crate :: R < STATR_SPEC > ; # [doc = "Register `STATR` writer"]
pub type W = crate :: W < STATR_SPEC > ; # [doc = "Field `RXNE` reader - Receive buffer not empty"]
pub type RXNE_R = crate :: BitReader ; # [doc = "Field `TXE` reader - Transmit buffer empty"]
pub type TXE_R = crate :: BitReader ; # [doc = "Field `CRCERR` reader - CRC error flag"]
pub type CRCERR_R = crate :: BitReader ; # [doc = "Field `CRCERR` writer - CRC error flag"]
pub type CRCERR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MODF` reader - Mode fault"]
pub type MODF_R = crate :: BitReader ; # [doc = "Field `OVR` reader - Overrun flag"]
pub type OVR_R = crate :: BitReader ; # [doc = "Field `BSY` reader - Busy flag"]
pub type BSY_R = crate :: BitReader ; impl R { # [doc = "Bit 0 - Receive buffer not empty"]
# [inline (always)]
pub fn rxne (& self) -> RXNE_R { RXNE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Transmit buffer empty"]
# [inline (always)]
pub fn txe (& self) -> TXE_R { TXE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - CRC error flag"]
# [inline (always)]
pub fn crcerr (& self) -> CRCERR_R { CRCERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Mode fault"]
# [inline (always)]
pub fn modf (& self) -> MODF_R { MODF_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Overrun flag"]
# [inline (always)]
pub fn ovr (& self) -> OVR_R { OVR_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Busy flag"]
# [inline (always)]
pub fn bsy (& self) -> BSY_R { BSY_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bit 4 - CRC error flag"]
# [inline (always)]
# [must_use]
pub fn crcerr (& mut self) -> CRCERR_W < STATR_SPEC > { CRCERR_W :: new (self , 4) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`statr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STATR_SPEC ; impl crate :: RegisterSpec for STATR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`statr::R`](R) reader structure"]
impl crate :: Readable for STATR_SPEC { } # [doc = "`write(|w| ..)` method takes [`statr::W`](W) writer structure"]
impl crate :: Writable for STATR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets STATR to value 0x02"]
impl crate :: Resettable for STATR_SPEC { const RESET_VALUE : u32 = 0x02 ; } } # [doc = "DATAR (rw) register accessor: data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar`]
module"]
pub type DATAR = crate :: Reg < datar :: DATAR_SPEC > ; # [doc = "data register"]
pub mod datar { # [doc = "Register `DATAR` reader"]
pub type R = crate :: R < DATAR_SPEC > ; # [doc = "Register `DATAR` writer"]
pub type W = crate :: W < DATAR_SPEC > ; # [doc = "Field `DATAR` reader - Data register"]
pub type DATAR_R = crate :: FieldReader < u16 > ; # [doc = "Field `DATAR` writer - Data register"]
pub type DATAR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - Data register"]
# [inline (always)]
pub fn datar (& self) -> DATAR_R { DATAR_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Data register"]
# [inline (always)]
# [must_use]
pub fn datar (& mut self) -> DATAR_W < DATAR_SPEC > { DATAR_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR_SPEC ; impl crate :: RegisterSpec for DATAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar::R`](R) reader structure"]
impl crate :: Readable for DATAR_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar::W`](W) writer structure"]
impl crate :: Writable for DATAR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR to value 0"]
impl crate :: Resettable for DATAR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CRCR (rw) register accessor: CRCR polynomial register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcr`]
module"]
pub type CRCR = crate :: Reg < crcr :: CRCR_SPEC > ; # [doc = "CRCR polynomial register"]
pub mod crcr { # [doc = "Register `CRCR` reader"]
pub type R = crate :: R < CRCR_SPEC > ; # [doc = "Register `CRCR` writer"]
pub type W = crate :: W < CRCR_SPEC > ; # [doc = "Field `CRCPOLY` reader - CRC polynomial register"]
pub type CRCPOLY_R = crate :: FieldReader < u16 > ; # [doc = "Field `CRCPOLY` writer - CRC polynomial register"]
pub type CRCPOLY_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bits 0:15 - CRC polynomial register"]
# [inline (always)]
pub fn crcpoly (& self) -> CRCPOLY_R { CRCPOLY_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - CRC polynomial register"]
# [inline (always)]
# [must_use]
pub fn crcpoly (& mut self) -> CRCPOLY_W < CRCR_SPEC > { CRCPOLY_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CRCR polynomial register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CRCR_SPEC ; impl crate :: RegisterSpec for CRCR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`crcr::R`](R) reader structure"]
impl crate :: Readable for CRCR_SPEC { } # [doc = "`write(|w| ..)` method takes [`crcr::W`](W) writer structure"]
impl crate :: Writable for CRCR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CRCR to value 0x07"]
impl crate :: Resettable for CRCR_SPEC { const RESET_VALUE : u32 = 0x07 ; } } # [doc = "RCRCR (r) register accessor: RX CRC register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rcrcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rcrcr`]
module"]
pub type RCRCR = crate :: Reg < rcrcr :: RCRCR_SPEC > ; # [doc = "RX CRC register"]
pub mod rcrcr { # [doc = "Register `RCRCR` reader"]
pub type R = crate :: R < RCRCR_SPEC > ; # [doc = "Field `RxCRC` reader - Rx CRC register"]
pub type RX_CRC_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:15 - Rx CRC register"]
# [inline (always)]
pub fn rx_crc (& self) -> RX_CRC_R { RX_CRC_R :: new ((self . bits & 0xffff) as u16) } } # [doc = "RX CRC register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rcrcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RCRCR_SPEC ; impl crate :: RegisterSpec for RCRCR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rcrcr::R`](R) reader structure"]
impl crate :: Readable for RCRCR_SPEC { } # [doc = "`reset()` method sets RCRCR to value 0"]
impl crate :: Resettable for RCRCR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "TCRCR (r) register accessor: TX CRC register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcrcr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcrcr`]
module"]
pub type TCRCR = crate :: Reg < tcrcr :: TCRCR_SPEC > ; # [doc = "TX CRC register"]
pub mod tcrcr { # [doc = "Register `TCRCR` reader"]
pub type R = crate :: R < TCRCR_SPEC > ; # [doc = "Field `TxCRC` reader - Tx CRC register"]
pub type TX_CRC_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:15 - Tx CRC register"]
# [inline (always)]
pub fn tx_crc (& self) -> TX_CRC_R { TX_CRC_R :: new ((self . bits & 0xffff) as u16) } } # [doc = "TX CRC register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcrcr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TCRCR_SPEC ; impl crate :: RegisterSpec for TCRCR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`tcrcr::R`](R) reader structure"]
impl crate :: Readable for TCRCR_SPEC { } # [doc = "`reset()` method sets TCRCR to value 0"]
impl crate :: Resettable for TCRCR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "I2SCFGR (rw) register accessor: I2S configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2scfgr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2scfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2scfgr`]
module"]
pub type I2SCFGR = crate :: Reg < i2scfgr :: I2SCFGR_SPEC > ; # [doc = "I2S configuration register"]
pub mod i2scfgr { # [doc = "Register `I2SCFGR` reader"]
pub type R = crate :: R < I2SCFGR_SPEC > ; # [doc = "Register `I2SCFGR` writer"]
pub type W = crate :: W < I2SCFGR_SPEC > ; # [doc = "Field `CHLEN` reader - Channel length (number of bits per audio channel)"]
pub type CHLEN_R = crate :: BitReader ; # [doc = "Field `CHLEN` writer - Channel length (number of bits per audio channel)"]
pub type CHLEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DATLEN` reader - Data length to be transferred"]
pub type DATLEN_R = crate :: FieldReader ; # [doc = "Field `DATLEN` writer - Data length to be transferred"]
pub type DATLEN_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `CKPOL` reader - Steady state clock polarity"]
pub type CKPOL_R = crate :: BitReader ; # [doc = "Field `CKPOL` writer - Steady state clock polarity"]
pub type CKPOL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2SSTD` reader - I2S standard selection"]
pub type I2SSTD_R = crate :: FieldReader ; # [doc = "Field `I2SSTD` writer - I2S standard selection"]
pub type I2SSTD_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PCMSYNC` reader - PCM frame synchronization"]
pub type PCMSYNC_R = crate :: BitReader ; # [doc = "Field `PCMSYNC` writer - PCM frame synchronization"]
pub type PCMSYNC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2SCFG` reader - I2S configuration mode"]
pub type I2SCFG_R = crate :: FieldReader ; # [doc = "Field `I2SCFG` writer - I2S configuration mode"]
pub type I2SCFG_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `I2SE` reader - I2S Enable"]
pub type I2SE_R = crate :: BitReader ; # [doc = "Field `I2SE` writer - I2S Enable"]
pub type I2SE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `I2SMOD` reader - I2S mode selection"]
pub type I2SMOD_R = crate :: BitReader ; # [doc = "Field `I2SMOD` writer - I2S mode selection"]
pub type I2SMOD_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Channel length (number of bits per audio channel)"]
# [inline (always)]
pub fn chlen (& self) -> CHLEN_R { CHLEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:2 - Data length to be transferred"]
# [inline (always)]
pub fn datlen (& self) -> DATLEN_R { DATLEN_R :: new (((self . bits >> 1) & 3) as u8) } # [doc = "Bit 3 - Steady state clock polarity"]
# [inline (always)]
pub fn ckpol (& self) -> CKPOL_R { CKPOL_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - I2S standard selection"]
# [inline (always)]
pub fn i2sstd (& self) -> I2SSTD_R { I2SSTD_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 7 - PCM frame synchronization"]
# [inline (always)]
pub fn pcmsync (& self) -> PCMSYNC_R { PCMSYNC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - I2S configuration mode"]
# [inline (always)]
pub fn i2scfg (& self) -> I2SCFG_R { I2SCFG_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 10 - I2S Enable"]
# [inline (always)]
pub fn i2se (& self) -> I2SE_R { I2SE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - I2S mode selection"]
# [inline (always)]
pub fn i2smod (& self) -> I2SMOD_R { I2SMOD_R :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bit 0 - Channel length (number of bits per audio channel)"]
# [inline (always)]
# [must_use]
pub fn chlen (& mut self) -> CHLEN_W < I2SCFGR_SPEC > { CHLEN_W :: new (self , 0) } # [doc = "Bits 1:2 - Data length to be transferred"]
# [inline (always)]
# [must_use]
pub fn datlen (& mut self) -> DATLEN_W < I2SCFGR_SPEC > { DATLEN_W :: new (self , 1) } # [doc = "Bit 3 - Steady state clock polarity"]
# [inline (always)]
# [must_use]
pub fn ckpol (& mut self) -> CKPOL_W < I2SCFGR_SPEC > { CKPOL_W :: new (self , 3) } # [doc = "Bits 4:5 - I2S standard selection"]
# [inline (always)]
# [must_use]
pub fn i2sstd (& mut self) -> I2SSTD_W < I2SCFGR_SPEC > { I2SSTD_W :: new (self , 4) } # [doc = "Bit 7 - PCM frame synchronization"]
# [inline (always)]
# [must_use]
pub fn pcmsync (& mut self) -> PCMSYNC_W < I2SCFGR_SPEC > { PCMSYNC_W :: new (self , 7) } # [doc = "Bits 8:9 - I2S configuration mode"]
# [inline (always)]
# [must_use]
pub fn i2scfg (& mut self) -> I2SCFG_W < I2SCFGR_SPEC > { I2SCFG_W :: new (self , 8) } # [doc = "Bit 10 - I2S Enable"]
# [inline (always)]
# [must_use]
pub fn i2se (& mut self) -> I2SE_W < I2SCFGR_SPEC > { I2SE_W :: new (self , 10) } # [doc = "Bit 11 - I2S mode selection"]
# [inline (always)]
# [must_use]
pub fn i2smod (& mut self) -> I2SMOD_W < I2SCFGR_SPEC > { I2SMOD_W :: new (self , 11) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2S configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2scfgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2scfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2SCFGR_SPEC ; impl crate :: RegisterSpec for I2SCFGR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`i2scfgr::R`](R) reader structure"]
impl crate :: Readable for I2SCFGR_SPEC { } # [doc = "`write(|w| ..)` method takes [`i2scfgr::W`](W) writer structure"]
impl crate :: Writable for I2SCFGR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets I2SCFGR to value 0"]
impl crate :: Resettable for I2SCFGR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "I2SPR (rw) register accessor: I2S prescaler register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2spr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2spr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2spr`]
module"]
pub type I2SPR = crate :: Reg < i2spr :: I2SPR_SPEC > ; # [doc = "I2S prescaler register"]
pub mod i2spr { # [doc = "Register `I2SPR` reader"]
pub type R = crate :: R < I2SPR_SPEC > ; # [doc = "Register `I2SPR` writer"]
pub type W = crate :: W < I2SPR_SPEC > ; # [doc = "Field `I2SDIV` reader - I2S Linear prescaler"]
pub type I2SDIV_R = crate :: FieldReader ; # [doc = "Field `I2SDIV` writer - I2S Linear prescaler"]
pub type I2SDIV_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `ODD` reader - Odd factor for the prescaler"]
pub type ODD_R = crate :: BitReader ; # [doc = "Field `ODD` writer - Odd factor for the prescaler"]
pub type ODD_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MCKOE` reader - Master clock output enable"]
pub type MCKOE_R = crate :: BitReader ; # [doc = "Field `MCKOE` writer - Master clock output enable"]
pub type MCKOE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:7 - I2S Linear prescaler"]
# [inline (always)]
pub fn i2sdiv (& self) -> I2SDIV_R { I2SDIV_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bit 8 - Odd factor for the prescaler"]
# [inline (always)]
pub fn odd (& self) -> ODD_R { ODD_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Master clock output enable"]
# [inline (always)]
pub fn mckoe (& self) -> MCKOE_R { MCKOE_R :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:7 - I2S Linear prescaler"]
# [inline (always)]
# [must_use]
pub fn i2sdiv (& mut self) -> I2SDIV_W < I2SPR_SPEC > { I2SDIV_W :: new (self , 0) } # [doc = "Bit 8 - Odd factor for the prescaler"]
# [inline (always)]
# [must_use]
pub fn odd (& mut self) -> ODD_W < I2SPR_SPEC > { ODD_W :: new (self , 8) } # [doc = "Bit 9 - Master clock output enable"]
# [inline (always)]
# [must_use]
pub fn mckoe (& mut self) -> MCKOE_W < I2SPR_SPEC > { MCKOE_W :: new (self , 9) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2S prescaler register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2spr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2spr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2SPR_SPEC ; impl crate :: RegisterSpec for I2SPR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`i2spr::R`](R) reader structure"]
impl crate :: Readable for I2SPR_SPEC { } # [doc = "`write(|w| ..)` method takes [`i2spr::W`](W) writer structure"]
impl crate :: Writable for I2SPR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets I2SPR to value 0x0a"]
impl crate :: Resettable for I2SPR_SPEC { const RESET_VALUE : u32 = 0x0a ; } } } # [doc = "Serial peripheral interface"]
pub struct SPI2 { _marker : PhantomData < * const () > } unsafe impl Send for SPI2 { } impl SPI2 { # [doc = r"Pointer to the register block"]
pub const PTR : * const spi1 :: RegisterBlock = 0x4000_3800 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const spi1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for SPI2 { type Target = spi1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for SPI2 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("SPI2") . finish () } } # [doc = "Serial peripheral interface"]
pub use self :: spi1 as spi2 ; # [doc = "Universal synchronous asynchronous receiver transmitter"]
pub struct USART1 { _marker : PhantomData < * const () > } unsafe impl Send for USART1 { } impl USART1 { # [doc = r"Pointer to the register block"]
pub const PTR : * const usart1 :: RegisterBlock = 0x4001_3800 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const usart1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for USART1 { type Target = usart1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for USART1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("USART1") . finish () } } # [doc = "Universal synchronous asynchronous receiver transmitter"]
pub mod usart1 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { statr : STATR , datar : DATAR , brr : BRR , ctlr1 : CTLR1 , ctlr2 : CTLR2 , ctlr3 : CTLR3 , gpr : GPR , } impl RegisterBlock { # [doc = "0x00 - Status register"]
# [inline (always)]
pub const fn statr (& self) -> & STATR { & self . statr } # [doc = "0x04 - Data register"]
# [inline (always)]
pub const fn datar (& self) -> & DATAR { & self . datar } # [doc = "0x08 - Baud rate register"]
# [inline (always)]
pub const fn brr (& self) -> & BRR { & self . brr } # [doc = "0x0c - Control register 1"]
# [inline (always)]
pub const fn ctlr1 (& self) -> & CTLR1 { & self . ctlr1 } # [doc = "0x10 - Control register 2"]
# [inline (always)]
pub const fn ctlr2 (& self) -> & CTLR2 { & self . ctlr2 } # [doc = "0x14 - Control register 3"]
# [inline (always)]
pub const fn ctlr3 (& self) -> & CTLR3 { & self . ctlr3 } # [doc = "0x18 - Guard time and prescaler register"]
# [inline (always)]
pub const fn gpr (& self) -> & GPR { & self . gpr } } # [doc = "STATR (rw) register accessor: Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`statr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@statr`]
module"]
pub type STATR = crate :: Reg < statr :: STATR_SPEC > ; # [doc = "Status register"]
pub mod statr { # [doc = "Register `STATR` reader"]
pub type R = crate :: R < STATR_SPEC > ; # [doc = "Register `STATR` writer"]
pub type W = crate :: W < STATR_SPEC > ; # [doc = "Field `PE` reader - Parity error"]
pub type PE_R = crate :: BitReader ; # [doc = "Field `FE` reader - Framing error"]
pub type FE_R = crate :: BitReader ; # [doc = "Field `NE` reader - Noise error flag"]
pub type NE_R = crate :: BitReader ; # [doc = "Field `ORE` reader - Overrun error"]
pub type ORE_R = crate :: BitReader ; # [doc = "Field `IDLE` reader - IDLE line detected"]
pub type IDLE_R = crate :: BitReader ; # [doc = "Field `RXNE` reader - Read data register not empty"]
pub type RXNE_R = crate :: BitReader ; # [doc = "Field `RXNE` writer - Read data register not empty"]
pub type RXNE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TC` reader - Transmission complete"]
pub type TC_R = crate :: BitReader ; # [doc = "Field `TC` writer - Transmission complete"]
pub type TC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXE` reader - Transmit data register empty"]
pub type TXE_R = crate :: BitReader ; # [doc = "Field `LBD` reader - LIN break detection flag"]
pub type LBD_R = crate :: BitReader ; # [doc = "Field `LBD` writer - LIN break detection flag"]
pub type LBD_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTS` reader - CTS flag"]
pub type CTS_R = crate :: BitReader ; # [doc = "Field `CTS` writer - CTS flag"]
pub type CTS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Parity error"]
# [inline (always)]
pub fn pe (& self) -> PE_R { PE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Framing error"]
# [inline (always)]
pub fn fe (& self) -> FE_R { FE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Noise error flag"]
# [inline (always)]
pub fn ne (& self) -> NE_R { NE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Overrun error"]
# [inline (always)]
pub fn ore (& self) -> ORE_R { ORE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - IDLE line detected"]
# [inline (always)]
pub fn idle (& self) -> IDLE_R { IDLE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Read data register not empty"]
# [inline (always)]
pub fn rxne (& self) -> RXNE_R { RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Transmission complete"]
# [inline (always)]
pub fn tc (& self) -> TC_R { TC_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Transmit data register empty"]
# [inline (always)]
pub fn txe (& self) -> TXE_R { TXE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - LIN break detection flag"]
# [inline (always)]
pub fn lbd (& self) -> LBD_R { LBD_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - CTS flag"]
# [inline (always)]
pub fn cts (& self) -> CTS_R { CTS_R :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bit 5 - Read data register not empty"]
# [inline (always)]
# [must_use]
pub fn rxne (& mut self) -> RXNE_W < STATR_SPEC > { RXNE_W :: new (self , 5) } # [doc = "Bit 6 - Transmission complete"]
# [inline (always)]
# [must_use]
pub fn tc (& mut self) -> TC_W < STATR_SPEC > { TC_W :: new (self , 6) } # [doc = "Bit 8 - LIN break detection flag"]
# [inline (always)]
# [must_use]
pub fn lbd (& mut self) -> LBD_W < STATR_SPEC > { LBD_W :: new (self , 8) } # [doc = "Bit 9 - CTS flag"]
# [inline (always)]
# [must_use]
pub fn cts (& mut self) -> CTS_W < STATR_SPEC > { CTS_W :: new (self , 9) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`statr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STATR_SPEC ; impl crate :: RegisterSpec for STATR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`statr::R`](R) reader structure"]
impl crate :: Readable for STATR_SPEC { } # [doc = "`write(|w| ..)` method takes [`statr::W`](W) writer structure"]
impl crate :: Writable for STATR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets STATR to value 0xc0"]
impl crate :: Resettable for STATR_SPEC { const RESET_VALUE : u32 = 0xc0 ; } } # [doc = "DATAR (rw) register accessor: Data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar`]
module"]
pub type DATAR = crate :: Reg < datar :: DATAR_SPEC > ; # [doc = "Data register"]
pub mod datar { # [doc = "Register `DATAR` reader"]
pub type R = crate :: R < DATAR_SPEC > ; # [doc = "Register `DATAR` writer"]
pub type W = crate :: W < DATAR_SPEC > ; # [doc = "Field `DR` reader - Data value"]
pub type DR_R = crate :: FieldReader < u16 > ; # [doc = "Field `DR` writer - Data value"]
pub type DR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 9 , u16 > ; impl R { # [doc = "Bits 0:8 - Data value"]
# [inline (always)]
pub fn dr (& self) -> DR_R { DR_R :: new ((self . bits & 0x01ff) as u16) } } impl W { # [doc = "Bits 0:8 - Data value"]
# [inline (always)]
# [must_use]
pub fn dr (& mut self) -> DR_W < DATAR_SPEC > { DR_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR_SPEC ; impl crate :: RegisterSpec for DATAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar::R`](R) reader structure"]
impl crate :: Readable for DATAR_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar::W`](W) writer structure"]
impl crate :: Writable for DATAR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR to value 0"]
impl crate :: Resettable for DATAR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "BRR (rw) register accessor: Baud rate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@brr`]
module"]
pub type BRR = crate :: Reg < brr :: BRR_SPEC > ; # [doc = "Baud rate register"]
pub mod brr { # [doc = "Register `BRR` reader"]
pub type R = crate :: R < BRR_SPEC > ; # [doc = "Register `BRR` writer"]
pub type W = crate :: W < BRR_SPEC > ; # [doc = "Field `DIV_Fraction` reader - fraction of USARTDIV"]
pub type DIV_FRACTION_R = crate :: FieldReader ; # [doc = "Field `DIV_Fraction` writer - fraction of USARTDIV"]
pub type DIV_FRACTION_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DIV_Mantissa` reader - mantissa of USARTDIV"]
pub type DIV_MANTISSA_R = crate :: FieldReader < u16 > ; # [doc = "Field `DIV_Mantissa` writer - mantissa of USARTDIV"]
pub type DIV_MANTISSA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:3 - fraction of USARTDIV"]
# [inline (always)]
pub fn div_fraction (& self) -> DIV_FRACTION_R { DIV_FRACTION_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:15 - mantissa of USARTDIV"]
# [inline (always)]
pub fn div_mantissa (& self) -> DIV_MANTISSA_R { DIV_MANTISSA_R :: new (((self . bits >> 4) & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:3 - fraction of USARTDIV"]
# [inline (always)]
# [must_use]
pub fn div_fraction (& mut self) -> DIV_FRACTION_W < BRR_SPEC > { DIV_FRACTION_W :: new (self , 0) } # [doc = "Bits 4:15 - mantissa of USARTDIV"]
# [inline (always)]
# [must_use]
pub fn div_mantissa (& mut self) -> DIV_MANTISSA_W < BRR_SPEC > { DIV_MANTISSA_W :: new (self , 4) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Baud rate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BRR_SPEC ; impl crate :: RegisterSpec for BRR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`brr::R`](R) reader structure"]
impl crate :: Readable for BRR_SPEC { } # [doc = "`write(|w| ..)` method takes [`brr::W`](W) writer structure"]
impl crate :: Writable for BRR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets BRR to value 0"]
impl crate :: Resettable for BRR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTLR1 (rw) register accessor: Control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr1`]
module"]
pub type CTLR1 = crate :: Reg < ctlr1 :: CTLR1_SPEC > ; # [doc = "Control register 1"]
pub mod ctlr1 { # [doc = "Register `CTLR1` reader"]
pub type R = crate :: R < CTLR1_SPEC > ; # [doc = "Register `CTLR1` writer"]
pub type W = crate :: W < CTLR1_SPEC > ; # [doc = "Field `SBK` reader - Send break"]
pub type SBK_R = crate :: BitReader ; # [doc = "Field `SBK` writer - Send break"]
pub type SBK_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RWU` reader - Receiver wakeup"]
pub type RWU_R = crate :: BitReader ; # [doc = "Field `RWU` writer - Receiver wakeup"]
pub type RWU_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RE` reader - Receiver enable"]
pub type RE_R = crate :: BitReader ; # [doc = "Field `RE` writer - Receiver enable"]
pub type RE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TE` reader - Transmitter enable"]
pub type TE_R = crate :: BitReader ; # [doc = "Field `TE` writer - Transmitter enable"]
pub type TE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IDLEIE` reader - IDLE interrupt enable"]
pub type IDLEIE_R = crate :: BitReader ; # [doc = "Field `IDLEIE` writer - IDLE interrupt enable"]
pub type IDLEIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RXNEIE` reader - RXNE interrupt enable"]
pub type RXNEIE_R = crate :: BitReader ; # [doc = "Field `RXNEIE` writer - RXNE interrupt enable"]
pub type RXNEIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TCIE` reader - Transmission complete interrupt enable"]
pub type TCIE_R = crate :: BitReader ; # [doc = "Field `TCIE` writer - Transmission complete interrupt enable"]
pub type TCIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TXEIE` reader - TXE interrupt enable"]
pub type TXEIE_R = crate :: BitReader ; # [doc = "Field `TXEIE` writer - TXE interrupt enable"]
pub type TXEIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PEIE` reader - PE interrupt enable"]
pub type PEIE_R = crate :: BitReader ; # [doc = "Field `PEIE` writer - PE interrupt enable"]
pub type PEIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PS` reader - Parity selection"]
pub type PS_R = crate :: BitReader ; # [doc = "Field `PS` writer - Parity selection"]
pub type PS_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PCE` reader - Parity control enable"]
pub type PCE_R = crate :: BitReader ; # [doc = "Field `PCE` writer - Parity control enable"]
pub type PCE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WAKE` reader - Wakeup method"]
pub type WAKE_R = crate :: BitReader ; # [doc = "Field `WAKE` writer - Wakeup method"]
pub type WAKE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `M` reader - Word length"]
pub type M_R = crate :: BitReader ; # [doc = "Field `M` writer - Word length"]
pub type M_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `UE` reader - USART enable"]
pub type UE_R = crate :: BitReader ; # [doc = "Field `UE` writer - USART enable"]
pub type UE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Send break"]
# [inline (always)]
pub fn sbk (& self) -> SBK_R { SBK_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Receiver wakeup"]
# [inline (always)]
pub fn rwu (& self) -> RWU_R { RWU_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Receiver enable"]
# [inline (always)]
pub fn re (& self) -> RE_R { RE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Transmitter enable"]
# [inline (always)]
pub fn te (& self) -> TE_R { TE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - IDLE interrupt enable"]
# [inline (always)]
pub fn idleie (& self) -> IDLEIE_R { IDLEIE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - RXNE interrupt enable"]
# [inline (always)]
pub fn rxneie (& self) -> RXNEIE_R { RXNEIE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Transmission complete interrupt enable"]
# [inline (always)]
pub fn tcie (& self) -> TCIE_R { TCIE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - TXE interrupt enable"]
# [inline (always)]
pub fn txeie (& self) -> TXEIE_R { TXEIE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - PE interrupt enable"]
# [inline (always)]
pub fn peie (& self) -> PEIE_R { PEIE_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Parity selection"]
# [inline (always)]
pub fn ps (& self) -> PS_R { PS_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Parity control enable"]
# [inline (always)]
pub fn pce (& self) -> PCE_R { PCE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Wakeup method"]
# [inline (always)]
pub fn wake (& self) -> WAKE_R { WAKE_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Word length"]
# [inline (always)]
pub fn m (& self) -> M_R { M_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - USART enable"]
# [inline (always)]
pub fn ue (& self) -> UE_R { UE_R :: new (((self . bits >> 13) & 1) != 0) } } impl W { # [doc = "Bit 0 - Send break"]
# [inline (always)]
# [must_use]
pub fn sbk (& mut self) -> SBK_W < CTLR1_SPEC > { SBK_W :: new (self , 0) } # [doc = "Bit 1 - Receiver wakeup"]
# [inline (always)]
# [must_use]
pub fn rwu (& mut self) -> RWU_W < CTLR1_SPEC > { RWU_W :: new (self , 1) } # [doc = "Bit 2 - Receiver enable"]
# [inline (always)]
# [must_use]
pub fn re (& mut self) -> RE_W < CTLR1_SPEC > { RE_W :: new (self , 2) } # [doc = "Bit 3 - Transmitter enable"]
# [inline (always)]
# [must_use]
pub fn te (& mut self) -> TE_W < CTLR1_SPEC > { TE_W :: new (self , 3) } # [doc = "Bit 4 - IDLE interrupt enable"]
# [inline (always)]
# [must_use]
pub fn idleie (& mut self) -> IDLEIE_W < CTLR1_SPEC > { IDLEIE_W :: new (self , 4) } # [doc = "Bit 5 - RXNE interrupt enable"]
# [inline (always)]
# [must_use]
pub fn rxneie (& mut self) -> RXNEIE_W < CTLR1_SPEC > { RXNEIE_W :: new (self , 5) } # [doc = "Bit 6 - Transmission complete interrupt enable"]
# [inline (always)]
# [must_use]
pub fn tcie (& mut self) -> TCIE_W < CTLR1_SPEC > { TCIE_W :: new (self , 6) } # [doc = "Bit 7 - TXE interrupt enable"]
# [inline (always)]
# [must_use]
pub fn txeie (& mut self) -> TXEIE_W < CTLR1_SPEC > { TXEIE_W :: new (self , 7) } # [doc = "Bit 8 - PE interrupt enable"]
# [inline (always)]
# [must_use]
pub fn peie (& mut self) -> PEIE_W < CTLR1_SPEC > { PEIE_W :: new (self , 8) } # [doc = "Bit 9 - Parity selection"]
# [inline (always)]
# [must_use]
pub fn ps (& mut self) -> PS_W < CTLR1_SPEC > { PS_W :: new (self , 9) } # [doc = "Bit 10 - Parity control enable"]
# [inline (always)]
# [must_use]
pub fn pce (& mut self) -> PCE_W < CTLR1_SPEC > { PCE_W :: new (self , 10) } # [doc = "Bit 11 - Wakeup method"]
# [inline (always)]
# [must_use]
pub fn wake (& mut self) -> WAKE_W < CTLR1_SPEC > { WAKE_W :: new (self , 11) } # [doc = "Bit 12 - Word length"]
# [inline (always)]
# [must_use]
pub fn m (& mut self) -> M_W < CTLR1_SPEC > { M_W :: new (self , 12) } # [doc = "Bit 13 - USART enable"]
# [inline (always)]
# [must_use]
pub fn ue (& mut self) -> UE_W < CTLR1_SPEC > { UE_W :: new (self , 13) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR1_SPEC ; impl crate :: RegisterSpec for CTLR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr1::R`](R) reader structure"]
impl crate :: Readable for CTLR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr1::W`](W) writer structure"]
impl crate :: Writable for CTLR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR1 to value 0"]
impl crate :: Resettable for CTLR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTLR2 (rw) register accessor: Control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr2`]
module"]
pub type CTLR2 = crate :: Reg < ctlr2 :: CTLR2_SPEC > ; # [doc = "Control register 2"]
pub mod ctlr2 { # [doc = "Register `CTLR2` reader"]
pub type R = crate :: R < CTLR2_SPEC > ; # [doc = "Register `CTLR2` writer"]
pub type W = crate :: W < CTLR2_SPEC > ; # [doc = "Field `ADD` reader - Address of the USART node"]
pub type ADD_R = crate :: FieldReader ; # [doc = "Field `ADD` writer - Address of the USART node"]
pub type ADD_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `LBDL` reader - lin break detection length"]
pub type LBDL_R = crate :: BitReader ; # [doc = "Field `LBDL` writer - lin break detection length"]
pub type LBDL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LBDIE` reader - LIN break detection interrupt enable"]
pub type LBDIE_R = crate :: BitReader ; # [doc = "Field `LBDIE` writer - LIN break detection interrupt enable"]
pub type LBDIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LBCL` reader - Last bit clock pulse"]
pub type LBCL_R = crate :: BitReader ; # [doc = "Field `LBCL` writer - Last bit clock pulse"]
pub type LBCL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CPHA` reader - Clock phase"]
pub type CPHA_R = crate :: BitReader ; # [doc = "Field `CPHA` writer - Clock phase"]
pub type CPHA_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CPOL` reader - Clock polarity"]
pub type CPOL_R = crate :: BitReader ; # [doc = "Field `CPOL` writer - Clock polarity"]
pub type CPOL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CLKEN` reader - Clock enable"]
pub type CLKEN_R = crate :: BitReader ; # [doc = "Field `CLKEN` writer - Clock enable"]
pub type CLKEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STOP` reader - STOP bits"]
pub type STOP_R = crate :: FieldReader ; # [doc = "Field `STOP` writer - STOP bits"]
pub type STOP_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `LINEN` reader - LIN mode enable"]
pub type LINEN_R = crate :: BitReader ; # [doc = "Field `LINEN` writer - LIN mode enable"]
pub type LINEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - Address of the USART node"]
# [inline (always)]
pub fn add (& self) -> ADD_R { ADD_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 5 - lin break detection length"]
# [inline (always)]
pub fn lbdl (& self) -> LBDL_R { LBDL_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - LIN break detection interrupt enable"]
# [inline (always)]
pub fn lbdie (& self) -> LBDIE_R { LBDIE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - Last bit clock pulse"]
# [inline (always)]
pub fn lbcl (& self) -> LBCL_R { LBCL_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Clock phase"]
# [inline (always)]
pub fn cpha (& self) -> CPHA_R { CPHA_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Clock polarity"]
# [inline (always)]
pub fn cpol (& self) -> CPOL_R { CPOL_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Clock enable"]
# [inline (always)]
pub fn clken (& self) -> CLKEN_R { CLKEN_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:13 - STOP bits"]
# [inline (always)]
pub fn stop (& self) -> STOP_R { STOP_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - LIN mode enable"]
# [inline (always)]
pub fn linen (& self) -> LINEN_R { LINEN_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Address of the USART node"]
# [inline (always)]
# [must_use]
pub fn add (& mut self) -> ADD_W < CTLR2_SPEC > { ADD_W :: new (self , 0) } # [doc = "Bit 5 - lin break detection length"]
# [inline (always)]
# [must_use]
pub fn lbdl (& mut self) -> LBDL_W < CTLR2_SPEC > { LBDL_W :: new (self , 5) } # [doc = "Bit 6 - LIN break detection interrupt enable"]
# [inline (always)]
# [must_use]
pub fn lbdie (& mut self) -> LBDIE_W < CTLR2_SPEC > { LBDIE_W :: new (self , 6) } # [doc = "Bit 8 - Last bit clock pulse"]
# [inline (always)]
# [must_use]
pub fn lbcl (& mut self) -> LBCL_W < CTLR2_SPEC > { LBCL_W :: new (self , 8) } # [doc = "Bit 9 - Clock phase"]
# [inline (always)]
# [must_use]
pub fn cpha (& mut self) -> CPHA_W < CTLR2_SPEC > { CPHA_W :: new (self , 9) } # [doc = "Bit 10 - Clock polarity"]
# [inline (always)]
# [must_use]
pub fn cpol (& mut self) -> CPOL_W < CTLR2_SPEC > { CPOL_W :: new (self , 10) } # [doc = "Bit 11 - Clock enable"]
# [inline (always)]
# [must_use]
pub fn clken (& mut self) -> CLKEN_W < CTLR2_SPEC > { CLKEN_W :: new (self , 11) } # [doc = "Bits 12:13 - STOP bits"]
# [inline (always)]
# [must_use]
pub fn stop (& mut self) -> STOP_W < CTLR2_SPEC > { STOP_W :: new (self , 12) } # [doc = "Bit 14 - LIN mode enable"]
# [inline (always)]
# [must_use]
pub fn linen (& mut self) -> LINEN_W < CTLR2_SPEC > { LINEN_W :: new (self , 14) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR2_SPEC ; impl crate :: RegisterSpec for CTLR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr2::R`](R) reader structure"]
impl crate :: Readable for CTLR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr2::W`](W) writer structure"]
impl crate :: Writable for CTLR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR2 to value 0"]
impl crate :: Resettable for CTLR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTLR3 (rw) register accessor: Control register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr3`]
module"]
pub type CTLR3 = crate :: Reg < ctlr3 :: CTLR3_SPEC > ; # [doc = "Control register 3"]
pub mod ctlr3 { # [doc = "Register `CTLR3` reader"]
pub type R = crate :: R < CTLR3_SPEC > ; # [doc = "Register `CTLR3` writer"]
pub type W = crate :: W < CTLR3_SPEC > ; # [doc = "Field `EIE` reader - Error interrupt enable"]
pub type EIE_R = crate :: BitReader ; # [doc = "Field `EIE` writer - Error interrupt enable"]
pub type EIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IREN` reader - IrDA mode enable"]
pub type IREN_R = crate :: BitReader ; # [doc = "Field `IREN` writer - IrDA mode enable"]
pub type IREN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `IRLP` reader - IrDA low-power"]
pub type IRLP_R = crate :: BitReader ; # [doc = "Field `IRLP` writer - IrDA low-power"]
pub type IRLP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `HDSEL` reader - Half-duplex selection"]
pub type HDSEL_R = crate :: BitReader ; # [doc = "Field `HDSEL` writer - Half-duplex selection"]
pub type HDSEL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NACK` reader - Smartcard NACK enable"]
pub type NACK_R = crate :: BitReader ; # [doc = "Field `NACK` writer - Smartcard NACK enable"]
pub type NACK_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SCEN` reader - Smartcard mode enable"]
pub type SCEN_R = crate :: BitReader ; # [doc = "Field `SCEN` writer - Smartcard mode enable"]
pub type SCEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DMAR` reader - DMA enable receiver"]
pub type DMAR_R = crate :: BitReader ; # [doc = "Field `DMAR` writer - DMA enable receiver"]
pub type DMAR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DMAT` reader - DMA enable transmitter"]
pub type DMAT_R = crate :: BitReader ; # [doc = "Field `DMAT` writer - DMA enable transmitter"]
pub type DMAT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RTSE` reader - RTS enable"]
pub type RTSE_R = crate :: BitReader ; # [doc = "Field `RTSE` writer - RTS enable"]
pub type RTSE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTSE` reader - CTS enable"]
pub type CTSE_R = crate :: BitReader ; # [doc = "Field `CTSE` writer - CTS enable"]
pub type CTSE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTSIE` reader - CTS interrupt enable"]
pub type CTSIE_R = crate :: BitReader ; # [doc = "Field `CTSIE` writer - CTS interrupt enable"]
pub type CTSIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Error interrupt enable"]
# [inline (always)]
pub fn eie (& self) -> EIE_R { EIE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - IrDA mode enable"]
# [inline (always)]
pub fn iren (& self) -> IREN_R { IREN_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - IrDA low-power"]
# [inline (always)]
pub fn irlp (& self) -> IRLP_R { IRLP_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Half-duplex selection"]
# [inline (always)]
pub fn hdsel (& self) -> HDSEL_R { HDSEL_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Smartcard NACK enable"]
# [inline (always)]
pub fn nack (& self) -> NACK_R { NACK_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Smartcard mode enable"]
# [inline (always)]
pub fn scen (& self) -> SCEN_R { SCEN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DMA enable receiver"]
# [inline (always)]
pub fn dmar (& self) -> DMAR_R { DMAR_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DMA enable transmitter"]
# [inline (always)]
pub fn dmat (& self) -> DMAT_R { DMAT_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - RTS enable"]
# [inline (always)]
pub fn rtse (& self) -> RTSE_R { RTSE_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - CTS enable"]
# [inline (always)]
pub fn ctse (& self) -> CTSE_R { CTSE_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - CTS interrupt enable"]
# [inline (always)]
pub fn ctsie (& self) -> CTSIE_R { CTSIE_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Error interrupt enable"]
# [inline (always)]
# [must_use]
pub fn eie (& mut self) -> EIE_W < CTLR3_SPEC > { EIE_W :: new (self , 0) } # [doc = "Bit 1 - IrDA mode enable"]
# [inline (always)]
# [must_use]
pub fn iren (& mut self) -> IREN_W < CTLR3_SPEC > { IREN_W :: new (self , 1) } # [doc = "Bit 2 - IrDA low-power"]
# [inline (always)]
# [must_use]
pub fn irlp (& mut self) -> IRLP_W < CTLR3_SPEC > { IRLP_W :: new (self , 2) } # [doc = "Bit 3 - Half-duplex selection"]
# [inline (always)]
# [must_use]
pub fn hdsel (& mut self) -> HDSEL_W < CTLR3_SPEC > { HDSEL_W :: new (self , 3) } # [doc = "Bit 4 - Smartcard NACK enable"]
# [inline (always)]
# [must_use]
pub fn nack (& mut self) -> NACK_W < CTLR3_SPEC > { NACK_W :: new (self , 4) } # [doc = "Bit 5 - Smartcard mode enable"]
# [inline (always)]
# [must_use]
pub fn scen (& mut self) -> SCEN_W < CTLR3_SPEC > { SCEN_W :: new (self , 5) } # [doc = "Bit 6 - DMA enable receiver"]
# [inline (always)]
# [must_use]
pub fn dmar (& mut self) -> DMAR_W < CTLR3_SPEC > { DMAR_W :: new (self , 6) } # [doc = "Bit 7 - DMA enable transmitter"]
# [inline (always)]
# [must_use]
pub fn dmat (& mut self) -> DMAT_W < CTLR3_SPEC > { DMAT_W :: new (self , 7) } # [doc = "Bit 8 - RTS enable"]
# [inline (always)]
# [must_use]
pub fn rtse (& mut self) -> RTSE_W < CTLR3_SPEC > { RTSE_W :: new (self , 8) } # [doc = "Bit 9 - CTS enable"]
# [inline (always)]
# [must_use]
pub fn ctse (& mut self) -> CTSE_W < CTLR3_SPEC > { CTSE_W :: new (self , 9) } # [doc = "Bit 10 - CTS interrupt enable"]
# [inline (always)]
# [must_use]
pub fn ctsie (& mut self) -> CTSIE_W < CTLR3_SPEC > { CTSIE_W :: new (self , 10) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR3_SPEC ; impl crate :: RegisterSpec for CTLR3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr3::R`](R) reader structure"]
impl crate :: Readable for CTLR3_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr3::W`](W) writer structure"]
impl crate :: Writable for CTLR3_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR3 to value 0"]
impl crate :: Resettable for CTLR3_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "GPR (rw) register accessor: Guard time and prescaler register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpr`]
module"]
pub type GPR = crate :: Reg < gpr :: GPR_SPEC > ; # [doc = "Guard time and prescaler register"]
pub mod gpr { # [doc = "Register `GPR` reader"]
pub type R = crate :: R < GPR_SPEC > ; # [doc = "Register `GPR` writer"]
pub type W = crate :: W < GPR_SPEC > ; # [doc = "Field `PSC` reader - Prescaler value"]
pub type PSC_R = crate :: FieldReader ; # [doc = "Field `PSC` writer - Prescaler value"]
pub type PSC_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; # [doc = "Field `GT` reader - Guard time value"]
pub type GT_R = crate :: FieldReader ; # [doc = "Field `GT` writer - Guard time value"]
pub type GT_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - Prescaler value"]
# [inline (always)]
pub fn psc (& self) -> PSC_R { PSC_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - Guard time value"]
# [inline (always)]
pub fn gt (& self) -> GT_R { GT_R :: new (((self . bits >> 8) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Prescaler value"]
# [inline (always)]
# [must_use]
pub fn psc (& mut self) -> PSC_W < GPR_SPEC > { PSC_W :: new (self , 0) } # [doc = "Bits 8:15 - Guard time value"]
# [inline (always)]
# [must_use]
pub fn gt (& mut self) -> GT_W < GPR_SPEC > { GT_W :: new (self , 8) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Guard time and prescaler register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GPR_SPEC ; impl crate :: RegisterSpec for GPR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gpr::R`](R) reader structure"]
impl crate :: Readable for GPR_SPEC { } # [doc = "`write(|w| ..)` method takes [`gpr::W`](W) writer structure"]
impl crate :: Writable for GPR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets GPR to value 0"]
impl crate :: Resettable for GPR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Universal synchronous asynchronous receiver transmitter"]
pub struct USART2 { _marker : PhantomData < * const () > } unsafe impl Send for USART2 { } impl USART2 { # [doc = r"Pointer to the register block"]
pub const PTR : * const usart1 :: RegisterBlock = 0x4000_4400 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const usart1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for USART2 { type Target = usart1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for USART2 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("USART2") . finish () } } # [doc = "Universal synchronous asynchronous receiver transmitter"]
pub use self :: usart1 as usart2 ; # [doc = "Universal synchronous asynchronous receiver transmitter"]
pub struct USART3 { _marker : PhantomData < * const () > } unsafe impl Send for USART3 { } impl USART3 { # [doc = r"Pointer to the register block"]
pub const PTR : * const usart1 :: RegisterBlock = 0x4000_4800 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const usart1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for USART3 { type Target = usart1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for USART3 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("USART3") . finish () } } # [doc = "Universal synchronous asynchronous receiver transmitter"]
pub use self :: usart1 as usart3 ; # [doc = "Analog to digital converter"]
pub struct ADC { _marker : PhantomData < * const () > } unsafe impl Send for ADC { } impl ADC { # [doc = r"Pointer to the register block"]
pub const PTR : * const adc :: RegisterBlock = 0x4001_2400 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const adc :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for ADC { type Target = adc :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for ADC { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("ADC") . finish () } } # [doc = "Analog to digital converter"]
pub mod adc { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { statr : STATR , ctlr1 : CTLR1 , ctlr2 : CTLR2 , samptr1 : SAMPTR1 , samptr2 : SAMPTR2 , iofr1 : IOFR1 , iofr2 : IOFR2 , iofr3 : IOFR3 , iofr4 : IOFR4 , wdhtr : WDHTR , wdltr : WDLTR , rsqr1 : RSQR1 , rsqr2 : RSQR2 , rsqr3 : RSQR3 , isqr : ISQR , idatar1 : IDATAR1 , idatar2 : IDATAR2 , idatar3 : IDATAR3 , idatar4 : IDATAR4 , rdatar : RDATAR , } impl RegisterBlock { # [doc = "0x00 - status register"]
# [inline (always)]
pub const fn statr (& self) -> & STATR { & self . statr } # [doc = "0x04 - control register 1"]
# [inline (always)]
pub const fn ctlr1 (& self) -> & CTLR1 { & self . ctlr1 } # [doc = "0x08 - control register 2"]
# [inline (always)]
pub const fn ctlr2 (& self) -> & CTLR2 { & self . ctlr2 } # [doc = "0x0c - sample time register 1"]
# [inline (always)]
pub const fn samptr1 (& self) -> & SAMPTR1 { & self . samptr1 } # [doc = "0x10 - sample time register 2"]
# [inline (always)]
pub const fn samptr2 (& self) -> & SAMPTR2 { & self . samptr2 } # [doc = "0x14 - injected channel data offset register x"]
# [inline (always)]
pub const fn iofr1 (& self) -> & IOFR1 { & self . iofr1 } # [doc = "0x18 - injected channel data offset register x"]
# [inline (always)]
pub const fn iofr2 (& self) -> & IOFR2 { & self . iofr2 } # [doc = "0x1c - injected channel data offset register x"]
# [inline (always)]
pub const fn iofr3 (& self) -> & IOFR3 { & self . iofr3 } # [doc = "0x20 - injected channel data offset register x"]
# [inline (always)]
pub const fn iofr4 (& self) -> & IOFR4 { & self . iofr4 } # [doc = "0x24 - watchdog higher threshold register"]
# [inline (always)]
pub const fn wdhtr (& self) -> & WDHTR { & self . wdhtr } # [doc = "0x28 - watchdog lower threshold register"]
# [inline (always)]
pub const fn wdltr (& self) -> & WDLTR { & self . wdltr } # [doc = "0x2c - regular sequence register 1"]
# [inline (always)]
pub const fn rsqr1 (& self) -> & RSQR1 { & self . rsqr1 } # [doc = "0x30 - regular sequence register 2"]
# [inline (always)]
pub const fn rsqr2 (& self) -> & RSQR2 { & self . rsqr2 } # [doc = "0x34 - regular sequence register 3"]
# [inline (always)]
pub const fn rsqr3 (& self) -> & RSQR3 { & self . rsqr3 } # [doc = "0x38 - injected sequence register"]
# [inline (always)]
pub const fn isqr (& self) -> & ISQR { & self . isqr } # [doc = "0x3c - injected data register x"]
# [inline (always)]
pub const fn idatar1 (& self) -> & IDATAR1 { & self . idatar1 } # [doc = "0x40 - injected data register x"]
# [inline (always)]
pub const fn idatar2 (& self) -> & IDATAR2 { & self . idatar2 } # [doc = "0x44 - injected data register x"]
# [inline (always)]
pub const fn idatar3 (& self) -> & IDATAR3 { & self . idatar3 } # [doc = "0x48 - injected data register x"]
# [inline (always)]
pub const fn idatar4 (& self) -> & IDATAR4 { & self . idatar4 } # [doc = "0x4c - regular data register"]
# [inline (always)]
pub const fn rdatar (& self) -> & RDATAR { & self . rdatar } } # [doc = "STATR (rw) register accessor: status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`statr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@statr`]
module"]
pub type STATR = crate :: Reg < statr :: STATR_SPEC > ; # [doc = "status register"]
pub mod statr { # [doc = "Register `STATR` reader"]
pub type R = crate :: R < STATR_SPEC > ; # [doc = "Register `STATR` writer"]
pub type W = crate :: W < STATR_SPEC > ; # [doc = "Field `AWD` reader - Analog watchdog flag"]
pub type AWD_R = crate :: BitReader ; # [doc = "Field `AWD` writer - Analog watchdog flag"]
pub type AWD_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOC` reader - Regular channel end of conversion"]
pub type EOC_R = crate :: BitReader ; # [doc = "Field `EOC` writer - Regular channel end of conversion"]
pub type EOC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JEOC` reader - Injected channel end of conversion"]
pub type JEOC_R = crate :: BitReader ; # [doc = "Field `JEOC` writer - Injected channel end of conversion"]
pub type JEOC_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JSTRT` reader - Injected channel start flag"]
pub type JSTRT_R = crate :: BitReader ; # [doc = "Field `JSTRT` writer - Injected channel start flag"]
pub type JSTRT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STRT` reader - Regular channel start flag"]
pub type STRT_R = crate :: BitReader ; # [doc = "Field `STRT` writer - Regular channel start flag"]
pub type STRT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Analog watchdog flag"]
# [inline (always)]
pub fn awd (& self) -> AWD_R { AWD_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Regular channel end of conversion"]
# [inline (always)]
pub fn eoc (& self) -> EOC_R { EOC_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Injected channel end of conversion"]
# [inline (always)]
pub fn jeoc (& self) -> JEOC_R { JEOC_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Injected channel start flag"]
# [inline (always)]
pub fn jstrt (& self) -> JSTRT_R { JSTRT_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Regular channel start flag"]
# [inline (always)]
pub fn strt (& self) -> STRT_R { STRT_R :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - Analog watchdog flag"]
# [inline (always)]
# [must_use]
pub fn awd (& mut self) -> AWD_W < STATR_SPEC > { AWD_W :: new (self , 0) } # [doc = "Bit 1 - Regular channel end of conversion"]
# [inline (always)]
# [must_use]
pub fn eoc (& mut self) -> EOC_W < STATR_SPEC > { EOC_W :: new (self , 1) } # [doc = "Bit 2 - Injected channel end of conversion"]
# [inline (always)]
# [must_use]
pub fn jeoc (& mut self) -> JEOC_W < STATR_SPEC > { JEOC_W :: new (self , 2) } # [doc = "Bit 3 - Injected channel start flag"]
# [inline (always)]
# [must_use]
pub fn jstrt (& mut self) -> JSTRT_W < STATR_SPEC > { JSTRT_W :: new (self , 3) } # [doc = "Bit 4 - Regular channel start flag"]
# [inline (always)]
# [must_use]
pub fn strt (& mut self) -> STRT_W < STATR_SPEC > { STRT_W :: new (self , 4) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`statr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STATR_SPEC ; impl crate :: RegisterSpec for STATR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`statr::R`](R) reader structure"]
impl crate :: Readable for STATR_SPEC { } # [doc = "`write(|w| ..)` method takes [`statr::W`](W) writer structure"]
impl crate :: Writable for STATR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets STATR to value 0"]
impl crate :: Resettable for STATR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTLR1 (rw) register accessor: control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr1`]
module"]
pub type CTLR1 = crate :: Reg < ctlr1 :: CTLR1_SPEC > ; # [doc = "control register 1"]
pub mod ctlr1 { # [doc = "Register `CTLR1` reader"]
pub type R = crate :: R < CTLR1_SPEC > ; # [doc = "Register `CTLR1` writer"]
pub type W = crate :: W < CTLR1_SPEC > ; # [doc = "Field `AWDCH` reader - Analog watchdog channel select bits"]
pub type AWDCH_R = crate :: FieldReader ; # [doc = "Field `AWDCH` writer - Analog watchdog channel select bits"]
pub type AWDCH_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `EOCIE` reader - Interrupt enable for EOC"]
pub type EOCIE_R = crate :: BitReader ; # [doc = "Field `EOCIE` writer - Interrupt enable for EOC"]
pub type EOCIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `AWDIE` reader - Analog watchdog interrupt enable"]
pub type AWDIE_R = crate :: BitReader ; # [doc = "Field `AWDIE` writer - Analog watchdog interrupt enable"]
pub type AWDIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JEOCIE` reader - Interrupt enable for injected channels"]
pub type JEOCIE_R = crate :: BitReader ; # [doc = "Field `JEOCIE` writer - Interrupt enable for injected channels"]
pub type JEOCIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SCAN` reader - Scan mode"]
pub type SCAN_R = crate :: BitReader ; # [doc = "Field `SCAN` writer - Scan mode"]
pub type SCAN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `AWDSGL` reader - Enable the watchdog on a single channel in scan mode"]
pub type AWDSGL_R = crate :: BitReader ; # [doc = "Field `AWDSGL` writer - Enable the watchdog on a single channel in scan mode"]
pub type AWDSGL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JAUTO` reader - Automatic injected group conversion"]
pub type JAUTO_R = crate :: BitReader ; # [doc = "Field `JAUTO` writer - Automatic injected group conversion"]
pub type JAUTO_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DISCEN` reader - Discontinuous mode on regular channels"]
pub type DISCEN_R = crate :: BitReader ; # [doc = "Field `DISCEN` writer - Discontinuous mode on regular channels"]
pub type DISCEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JDISCEN` reader - Discontinuous mode on injected channels"]
pub type JDISCEN_R = crate :: BitReader ; # [doc = "Field `JDISCEN` writer - Discontinuous mode on injected channels"]
pub type JDISCEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DISCNUM` reader - Discontinuous mode channel count"]
pub type DISCNUM_R = crate :: FieldReader ; # [doc = "Field `DISCNUM` writer - Discontinuous mode channel count"]
pub type DISCNUM_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `DUALMOD` reader - Dual mode selection"]
pub type DUALMOD_R = crate :: FieldReader ; # [doc = "Field `DUALMOD` writer - Dual mode selection"]
pub type DUALMOD_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `JAWDEN` reader - Analog watchdog enable on injected channels"]
pub type JAWDEN_R = crate :: BitReader ; # [doc = "Field `JAWDEN` writer - Analog watchdog enable on injected channels"]
pub type JAWDEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `AWDEN` reader - Analog watchdog enable on regular channels"]
pub type AWDEN_R = crate :: BitReader ; # [doc = "Field `AWDEN` writer - Analog watchdog enable on regular channels"]
pub type AWDEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TKENABLE` reader - Touch key enable, including TKEY_F and TKEY_V"]
pub type TKENABLE_R = crate :: BitReader ; # [doc = "Field `TKENABLE` writer - Touch key enable, including TKEY_F and TKEY_V"]
pub type TKENABLE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:4 - Analog watchdog channel select bits"]
# [inline (always)]
pub fn awdch (& self) -> AWDCH_R { AWDCH_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bit 5 - Interrupt enable for EOC"]
# [inline (always)]
pub fn eocie (& self) -> EOCIE_R { EOCIE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Analog watchdog interrupt enable"]
# [inline (always)]
pub fn awdie (& self) -> AWDIE_R { AWDIE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Interrupt enable for injected channels"]
# [inline (always)]
pub fn jeocie (& self) -> JEOCIE_R { JEOCIE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Scan mode"]
# [inline (always)]
pub fn scan (& self) -> SCAN_R { SCAN_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable the watchdog on a single channel in scan mode"]
# [inline (always)]
pub fn awdsgl (& self) -> AWDSGL_R { AWDSGL_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Automatic injected group conversion"]
# [inline (always)]
pub fn jauto (& self) -> JAUTO_R { JAUTO_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Discontinuous mode on regular channels"]
# [inline (always)]
pub fn discen (& self) -> DISCEN_R { DISCEN_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Discontinuous mode on injected channels"]
# [inline (always)]
pub fn jdiscen (& self) -> JDISCEN_R { JDISCEN_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bits 13:15 - Discontinuous mode channel count"]
# [inline (always)]
pub fn discnum (& self) -> DISCNUM_R { DISCNUM_R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bits 16:19 - Dual mode selection"]
# [inline (always)]
pub fn dualmod (& self) -> DUALMOD_R { DUALMOD_R :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bit 22 - Analog watchdog enable on injected channels"]
# [inline (always)]
pub fn jawden (& self) -> JAWDEN_R { JAWDEN_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - Analog watchdog enable on regular channels"]
# [inline (always)]
pub fn awden (& self) -> AWDEN_R { AWDEN_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - Touch key enable, including TKEY_F and TKEY_V"]
# [inline (always)]
pub fn tkenable (& self) -> TKENABLE_R { TKENABLE_R :: new (((self . bits >> 24) & 1) != 0) } } impl W { # [doc = "Bits 0:4 - Analog watchdog channel select bits"]
# [inline (always)]
# [must_use]
pub fn awdch (& mut self) -> AWDCH_W < CTLR1_SPEC > { AWDCH_W :: new (self , 0) } # [doc = "Bit 5 - Interrupt enable for EOC"]
# [inline (always)]
# [must_use]
pub fn eocie (& mut self) -> EOCIE_W < CTLR1_SPEC > { EOCIE_W :: new (self , 5) } # [doc = "Bit 6 - Analog watchdog interrupt enable"]
# [inline (always)]
# [must_use]
pub fn awdie (& mut self) -> AWDIE_W < CTLR1_SPEC > { AWDIE_W :: new (self , 6) } # [doc = "Bit 7 - Interrupt enable for injected channels"]
# [inline (always)]
# [must_use]
pub fn jeocie (& mut self) -> JEOCIE_W < CTLR1_SPEC > { JEOCIE_W :: new (self , 7) } # [doc = "Bit 8 - Scan mode"]
# [inline (always)]
# [must_use]
pub fn scan (& mut self) -> SCAN_W < CTLR1_SPEC > { SCAN_W :: new (self , 8) } # [doc = "Bit 9 - Enable the watchdog on a single channel in scan mode"]
# [inline (always)]
# [must_use]
pub fn awdsgl (& mut self) -> AWDSGL_W < CTLR1_SPEC > { AWDSGL_W :: new (self , 9) } # [doc = "Bit 10 - Automatic injected group conversion"]
# [inline (always)]
# [must_use]
pub fn jauto (& mut self) -> JAUTO_W < CTLR1_SPEC > { JAUTO_W :: new (self , 10) } # [doc = "Bit 11 - Discontinuous mode on regular channels"]
# [inline (always)]
# [must_use]
pub fn discen (& mut self) -> DISCEN_W < CTLR1_SPEC > { DISCEN_W :: new (self , 11) } # [doc = "Bit 12 - Discontinuous mode on injected channels"]
# [inline (always)]
# [must_use]
pub fn jdiscen (& mut self) -> JDISCEN_W < CTLR1_SPEC > { JDISCEN_W :: new (self , 12) } # [doc = "Bits 13:15 - Discontinuous mode channel count"]
# [inline (always)]
# [must_use]
pub fn discnum (& mut self) -> DISCNUM_W < CTLR1_SPEC > { DISCNUM_W :: new (self , 13) } # [doc = "Bits 16:19 - Dual mode selection"]
# [inline (always)]
# [must_use]
pub fn dualmod (& mut self) -> DUALMOD_W < CTLR1_SPEC > { DUALMOD_W :: new (self , 16) } # [doc = "Bit 22 - Analog watchdog enable on injected channels"]
# [inline (always)]
# [must_use]
pub fn jawden (& mut self) -> JAWDEN_W < CTLR1_SPEC > { JAWDEN_W :: new (self , 22) } # [doc = "Bit 23 - Analog watchdog enable on regular channels"]
# [inline (always)]
# [must_use]
pub fn awden (& mut self) -> AWDEN_W < CTLR1_SPEC > { AWDEN_W :: new (self , 23) } # [doc = "Bit 24 - Touch key enable, including TKEY_F and TKEY_V"]
# [inline (always)]
# [must_use]
pub fn tkenable (& mut self) -> TKENABLE_W < CTLR1_SPEC > { TKENABLE_W :: new (self , 24) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR1_SPEC ; impl crate :: RegisterSpec for CTLR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr1::R`](R) reader structure"]
impl crate :: Readable for CTLR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr1::W`](W) writer structure"]
impl crate :: Writable for CTLR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR1 to value 0"]
impl crate :: Resettable for CTLR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTLR2 (rw) register accessor: control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr2`]
module"]
pub type CTLR2 = crate :: Reg < ctlr2 :: CTLR2_SPEC > ; # [doc = "control register 2"]
pub mod ctlr2 { # [doc = "Register `CTLR2` reader"]
pub type R = crate :: R < CTLR2_SPEC > ; # [doc = "Register `CTLR2` writer"]
pub type W = crate :: W < CTLR2_SPEC > ; # [doc = "Field `ADON` reader - A/D converter ON / OFF"]
pub type ADON_R = crate :: BitReader ; # [doc = "Field `ADON` writer - A/D converter ON / OFF"]
pub type ADON_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CONT` reader - Continuous conversion"]
pub type CONT_R = crate :: BitReader ; # [doc = "Field `CONT` writer - Continuous conversion"]
pub type CONT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CAL` reader - A/D calibration"]
pub type CAL_R = crate :: BitReader ; # [doc = "Field `CAL` writer - A/D calibration"]
pub type CAL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RSTCAL` reader - Reset calibration"]
pub type RSTCAL_R = crate :: BitReader ; # [doc = "Field `RSTCAL` writer - Reset calibration"]
pub type RSTCAL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DMA` reader - Direct memory access mode"]
pub type DMA_R = crate :: BitReader ; # [doc = "Field `DMA` writer - Direct memory access mode"]
pub type DMA_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ALIGN` reader - Data alignment"]
pub type ALIGN_R = crate :: BitReader ; # [doc = "Field `ALIGN` writer - Data alignment"]
pub type ALIGN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JEXTSEL` reader - External event select for injected group"]
pub type JEXTSEL_R = crate :: FieldReader ; # [doc = "Field `JEXTSEL` writer - External event select for injected group"]
pub type JEXTSEL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `JEXTTRIG` reader - External trigger conversion mode for injected channels"]
pub type JEXTTRIG_R = crate :: BitReader ; # [doc = "Field `JEXTTRIG` writer - External trigger conversion mode for injected channels"]
pub type JEXTTRIG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EXTSEL` reader - External event select for regular group"]
pub type EXTSEL_R = crate :: FieldReader ; # [doc = "Field `EXTSEL` writer - External event select for regular group"]
pub type EXTSEL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `EXTTRIG` reader - External trigger conversion mode for regular channels"]
pub type EXTTRIG_R = crate :: BitReader ; # [doc = "Field `EXTTRIG` writer - External trigger conversion mode for regular channels"]
pub type EXTTRIG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `JSWSTART` reader - Start conversion of injected channels"]
pub type JSWSTART_R = crate :: BitReader ; # [doc = "Field `JSWSTART` writer - Start conversion of injected channels"]
pub type JSWSTART_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWSTART` reader - Start conversion of regular channels"]
pub type SWSTART_R = crate :: BitReader ; # [doc = "Field `SWSTART` writer - Start conversion of regular channels"]
pub type SWSTART_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TSVREFE` reader - Temperature sensor and VREFINT enable"]
pub type TSVREFE_R = crate :: BitReader ; # [doc = "Field `TSVREFE` writer - Temperature sensor and VREFINT enable"]
pub type TSVREFE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - A/D converter ON / OFF"]
# [inline (always)]
pub fn adon (& self) -> ADON_R { ADON_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Continuous conversion"]
# [inline (always)]
pub fn cont (& self) -> CONT_R { CONT_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - A/D calibration"]
# [inline (always)]
pub fn cal (& self) -> CAL_R { CAL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Reset calibration"]
# [inline (always)]
pub fn rstcal (& self) -> RSTCAL_R { RSTCAL_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 8 - Direct memory access mode"]
# [inline (always)]
pub fn dma (& self) -> DMA_R { DMA_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - Data alignment"]
# [inline (always)]
pub fn align (& self) -> ALIGN_R { ALIGN_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:14 - External event select for injected group"]
# [inline (always)]
pub fn jextsel (& self) -> JEXTSEL_R { JEXTSEL_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 15 - External trigger conversion mode for injected channels"]
# [inline (always)]
pub fn jexttrig (& self) -> JEXTTRIG_R { JEXTTRIG_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 17:19 - External event select for regular group"]
# [inline (always)]
pub fn extsel (& self) -> EXTSEL_R { EXTSEL_R :: new (((self . bits >> 17) & 7) as u8) } # [doc = "Bit 20 - External trigger conversion mode for regular channels"]
# [inline (always)]
pub fn exttrig (& self) -> EXTTRIG_R { EXTTRIG_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - Start conversion of injected channels"]
# [inline (always)]
pub fn jswstart (& self) -> JSWSTART_R { JSWSTART_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - Start conversion of regular channels"]
# [inline (always)]
pub fn swstart (& self) -> SWSTART_R { SWSTART_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - Temperature sensor and VREFINT enable"]
# [inline (always)]
pub fn tsvrefe (& self) -> TSVREFE_R { TSVREFE_R :: new (((self . bits >> 23) & 1) != 0) } } impl W { # [doc = "Bit 0 - A/D converter ON / OFF"]
# [inline (always)]
# [must_use]
pub fn adon (& mut self) -> ADON_W < CTLR2_SPEC > { ADON_W :: new (self , 0) } # [doc = "Bit 1 - Continuous conversion"]
# [inline (always)]
# [must_use]
pub fn cont (& mut self) -> CONT_W < CTLR2_SPEC > { CONT_W :: new (self , 1) } # [doc = "Bit 2 - A/D calibration"]
# [inline (always)]
# [must_use]
pub fn cal (& mut self) -> CAL_W < CTLR2_SPEC > { CAL_W :: new (self , 2) } # [doc = "Bit 3 - Reset calibration"]
# [inline (always)]
# [must_use]
pub fn rstcal (& mut self) -> RSTCAL_W < CTLR2_SPEC > { RSTCAL_W :: new (self , 3) } # [doc = "Bit 8 - Direct memory access mode"]
# [inline (always)]
# [must_use]
pub fn dma (& mut self) -> DMA_W < CTLR2_SPEC > { DMA_W :: new (self , 8) } # [doc = "Bit 11 - Data alignment"]
# [inline (always)]
# [must_use]
pub fn align (& mut self) -> ALIGN_W < CTLR2_SPEC > { ALIGN_W :: new (self , 11) } # [doc = "Bits 12:14 - External event select for injected group"]
# [inline (always)]
# [must_use]
pub fn jextsel (& mut self) -> JEXTSEL_W < CTLR2_SPEC > { JEXTSEL_W :: new (self , 12) } # [doc = "Bit 15 - External trigger conversion mode for injected channels"]
# [inline (always)]
# [must_use]
pub fn jexttrig (& mut self) -> JEXTTRIG_W < CTLR2_SPEC > { JEXTTRIG_W :: new (self , 15) } # [doc = "Bits 17:19 - External event select for regular group"]
# [inline (always)]
# [must_use]
pub fn extsel (& mut self) -> EXTSEL_W < CTLR2_SPEC > { EXTSEL_W :: new (self , 17) } # [doc = "Bit 20 - External trigger conversion mode for regular channels"]
# [inline (always)]
# [must_use]
pub fn exttrig (& mut self) -> EXTTRIG_W < CTLR2_SPEC > { EXTTRIG_W :: new (self , 20) } # [doc = "Bit 21 - Start conversion of injected channels"]
# [inline (always)]
# [must_use]
pub fn jswstart (& mut self) -> JSWSTART_W < CTLR2_SPEC > { JSWSTART_W :: new (self , 21) } # [doc = "Bit 22 - Start conversion of regular channels"]
# [inline (always)]
# [must_use]
pub fn swstart (& mut self) -> SWSTART_W < CTLR2_SPEC > { SWSTART_W :: new (self , 22) } # [doc = "Bit 23 - Temperature sensor and VREFINT enable"]
# [inline (always)]
# [must_use]
pub fn tsvrefe (& mut self) -> TSVREFE_W < CTLR2_SPEC > { TSVREFE_W :: new (self , 23) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR2_SPEC ; impl crate :: RegisterSpec for CTLR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr2::R`](R) reader structure"]
impl crate :: Readable for CTLR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr2::W`](W) writer structure"]
impl crate :: Writable for CTLR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR2 to value 0"]
impl crate :: Resettable for CTLR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "SAMPTR1 (rw) register accessor: sample time register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`samptr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`samptr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@samptr1`]
module"]
pub type SAMPTR1 = crate :: Reg < samptr1 :: SAMPTR1_SPEC > ; # [doc = "sample time register 1"]
pub mod samptr1 { # [doc = "Register `SAMPTR1` reader"]
pub type R = crate :: R < SAMPTR1_SPEC > ; # [doc = "Register `SAMPTR1` writer"]
pub type W = crate :: W < SAMPTR1_SPEC > ; # [doc = "Field `SMP10` reader - Channel 10 sample time selection"]
pub type SMP10_R = crate :: FieldReader ; # [doc = "Field `SMP10` writer - Channel 10 sample time selection"]
pub type SMP10_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP11` reader - Channel 11 sample time selection"]
pub type SMP11_R = crate :: FieldReader ; # [doc = "Field `SMP11` writer - Channel 11 sample time selection"]
pub type SMP11_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP12` reader - Channel 12 sample time selection"]
pub type SMP12_R = crate :: FieldReader ; # [doc = "Field `SMP12` writer - Channel 12 sample time selection"]
pub type SMP12_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP13` reader - Channel 13 sample time selection"]
pub type SMP13_R = crate :: FieldReader ; # [doc = "Field `SMP13` writer - Channel 13 sample time selection"]
pub type SMP13_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP14` reader - Channel 14 sample time selection"]
pub type SMP14_R = crate :: FieldReader ; # [doc = "Field `SMP14` writer - Channel 14 sample time selection"]
pub type SMP14_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP15` reader - Channel 15 sample time selection"]
pub type SMP15_R = crate :: FieldReader ; # [doc = "Field `SMP15` writer - Channel 15 sample time selection"]
pub type SMP15_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP16` reader - Channel 16 sample time selection"]
pub type SMP16_R = crate :: FieldReader ; # [doc = "Field `SMP16` writer - Channel 16 sample time selection"]
pub type SMP16_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP17` reader - Channel 17 sample time selection"]
pub type SMP17_R = crate :: FieldReader ; # [doc = "Field `SMP17` writer - Channel 17 sample time selection"]
pub type SMP17_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - Channel 10 sample time selection"]
# [inline (always)]
pub fn smp10 (& self) -> SMP10_R { SMP10_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - Channel 11 sample time selection"]
# [inline (always)]
pub fn smp11 (& self) -> SMP11_R { SMP11_R :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - Channel 12 sample time selection"]
# [inline (always)]
pub fn smp12 (& self) -> SMP12_R { SMP12_R :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - Channel 13 sample time selection"]
# [inline (always)]
pub fn smp13 (& self) -> SMP13_R { SMP13_R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - Channel 14 sample time selection"]
# [inline (always)]
pub fn smp14 (& self) -> SMP14_R { SMP14_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bits 15:17 - Channel 15 sample time selection"]
# [inline (always)]
pub fn smp15 (& self) -> SMP15_R { SMP15_R :: new (((self . bits >> 15) & 7) as u8) } # [doc = "Bits 18:20 - Channel 16 sample time selection"]
# [inline (always)]
pub fn smp16 (& self) -> SMP16_R { SMP16_R :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 21:23 - Channel 17 sample time selection"]
# [inline (always)]
pub fn smp17 (& self) -> SMP17_R { SMP17_R :: new (((self . bits >> 21) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Channel 10 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp10 (& mut self) -> SMP10_W < SAMPTR1_SPEC > { SMP10_W :: new (self , 0) } # [doc = "Bits 3:5 - Channel 11 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp11 (& mut self) -> SMP11_W < SAMPTR1_SPEC > { SMP11_W :: new (self , 3) } # [doc = "Bits 6:8 - Channel 12 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp12 (& mut self) -> SMP12_W < SAMPTR1_SPEC > { SMP12_W :: new (self , 6) } # [doc = "Bits 9:11 - Channel 13 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp13 (& mut self) -> SMP13_W < SAMPTR1_SPEC > { SMP13_W :: new (self , 9) } # [doc = "Bits 12:14 - Channel 14 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp14 (& mut self) -> SMP14_W < SAMPTR1_SPEC > { SMP14_W :: new (self , 12) } # [doc = "Bits 15:17 - Channel 15 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp15 (& mut self) -> SMP15_W < SAMPTR1_SPEC > { SMP15_W :: new (self , 15) } # [doc = "Bits 18:20 - Channel 16 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp16 (& mut self) -> SMP16_W < SAMPTR1_SPEC > { SMP16_W :: new (self , 18) } # [doc = "Bits 21:23 - Channel 17 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp17 (& mut self) -> SMP17_W < SAMPTR1_SPEC > { SMP17_W :: new (self , 21) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "sample time register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`samptr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`samptr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SAMPTR1_SPEC ; impl crate :: RegisterSpec for SAMPTR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`samptr1::R`](R) reader structure"]
impl crate :: Readable for SAMPTR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`samptr1::W`](W) writer structure"]
impl crate :: Writable for SAMPTR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SAMPTR1 to value 0"]
impl crate :: Resettable for SAMPTR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "SAMPTR2 (rw) register accessor: sample time register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`samptr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`samptr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@samptr2`]
module"]
pub type SAMPTR2 = crate :: Reg < samptr2 :: SAMPTR2_SPEC > ; # [doc = "sample time register 2"]
pub mod samptr2 { # [doc = "Register `SAMPTR2` reader"]
pub type R = crate :: R < SAMPTR2_SPEC > ; # [doc = "Register `SAMPTR2` writer"]
pub type W = crate :: W < SAMPTR2_SPEC > ; # [doc = "Field `SMP0` reader - Channel 0 sample time selection"]
pub type SMP0_R = crate :: FieldReader ; # [doc = "Field `SMP0` writer - Channel 0 sample time selection"]
pub type SMP0_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP1` reader - Channel 1 sample time selection"]
pub type SMP1_R = crate :: FieldReader ; # [doc = "Field `SMP1` writer - Channel 1 sample time selection"]
pub type SMP1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP2` reader - Channel 2 sample time selection"]
pub type SMP2_R = crate :: FieldReader ; # [doc = "Field `SMP2` writer - Channel 2 sample time selection"]
pub type SMP2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP3` reader - Channel 3 sample time selection"]
pub type SMP3_R = crate :: FieldReader ; # [doc = "Field `SMP3` writer - Channel 3 sample time selection"]
pub type SMP3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP4` reader - Channel 4 sample time selection"]
pub type SMP4_R = crate :: FieldReader ; # [doc = "Field `SMP4` writer - Channel 4 sample time selection"]
pub type SMP4_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP5` reader - Channel 5 sample time selection"]
pub type SMP5_R = crate :: FieldReader ; # [doc = "Field `SMP5` writer - Channel 5 sample time selection"]
pub type SMP5_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP6` reader - Channel 6 sample time selection"]
pub type SMP6_R = crate :: FieldReader ; # [doc = "Field `SMP6` writer - Channel 6 sample time selection"]
pub type SMP6_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP7` reader - Channel 7 sample time selection"]
pub type SMP7_R = crate :: FieldReader ; # [doc = "Field `SMP7` writer - Channel 7 sample time selection"]
pub type SMP7_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP8` reader - Channel 8 sample time selection"]
pub type SMP8_R = crate :: FieldReader ; # [doc = "Field `SMP8` writer - Channel 8 sample time selection"]
pub type SMP8_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `SMP9` reader - Channel 9 sample time selection"]
pub type SMP9_R = crate :: FieldReader ; # [doc = "Field `SMP9` writer - Channel 9 sample time selection"]
pub type SMP9_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; impl R { # [doc = "Bits 0:2 - Channel 0 sample time selection"]
# [inline (always)]
pub fn smp0 (& self) -> SMP0_R { SMP0_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - Channel 1 sample time selection"]
# [inline (always)]
pub fn smp1 (& self) -> SMP1_R { SMP1_R :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:8 - Channel 2 sample time selection"]
# [inline (always)]
pub fn smp2 (& self) -> SMP2_R { SMP2_R :: new (((self . bits >> 6) & 7) as u8) } # [doc = "Bits 9:11 - Channel 3 sample time selection"]
# [inline (always)]
pub fn smp3 (& self) -> SMP3_R { SMP3_R :: new (((self . bits >> 9) & 7) as u8) } # [doc = "Bits 12:14 - Channel 4 sample time selection"]
# [inline (always)]
pub fn smp4 (& self) -> SMP4_R { SMP4_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bits 15:17 - Channel 5 sample time selection"]
# [inline (always)]
pub fn smp5 (& self) -> SMP5_R { SMP5_R :: new (((self . bits >> 15) & 7) as u8) } # [doc = "Bits 18:20 - Channel 6 sample time selection"]
# [inline (always)]
pub fn smp6 (& self) -> SMP6_R { SMP6_R :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 21:23 - Channel 7 sample time selection"]
# [inline (always)]
pub fn smp7 (& self) -> SMP7_R { SMP7_R :: new (((self . bits >> 21) & 7) as u8) } # [doc = "Bits 24:26 - Channel 8 sample time selection"]
# [inline (always)]
pub fn smp8 (& self) -> SMP8_R { SMP8_R :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 27:29 - Channel 9 sample time selection"]
# [inline (always)]
pub fn smp9 (& self) -> SMP9_R { SMP9_R :: new (((self . bits >> 27) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Channel 0 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp0 (& mut self) -> SMP0_W < SAMPTR2_SPEC > { SMP0_W :: new (self , 0) } # [doc = "Bits 3:5 - Channel 1 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp1 (& mut self) -> SMP1_W < SAMPTR2_SPEC > { SMP1_W :: new (self , 3) } # [doc = "Bits 6:8 - Channel 2 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp2 (& mut self) -> SMP2_W < SAMPTR2_SPEC > { SMP2_W :: new (self , 6) } # [doc = "Bits 9:11 - Channel 3 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp3 (& mut self) -> SMP3_W < SAMPTR2_SPEC > { SMP3_W :: new (self , 9) } # [doc = "Bits 12:14 - Channel 4 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp4 (& mut self) -> SMP4_W < SAMPTR2_SPEC > { SMP4_W :: new (self , 12) } # [doc = "Bits 15:17 - Channel 5 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp5 (& mut self) -> SMP5_W < SAMPTR2_SPEC > { SMP5_W :: new (self , 15) } # [doc = "Bits 18:20 - Channel 6 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp6 (& mut self) -> SMP6_W < SAMPTR2_SPEC > { SMP6_W :: new (self , 18) } # [doc = "Bits 21:23 - Channel 7 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp7 (& mut self) -> SMP7_W < SAMPTR2_SPEC > { SMP7_W :: new (self , 21) } # [doc = "Bits 24:26 - Channel 8 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp8 (& mut self) -> SMP8_W < SAMPTR2_SPEC > { SMP8_W :: new (self , 24) } # [doc = "Bits 27:29 - Channel 9 sample time selection"]
# [inline (always)]
# [must_use]
pub fn smp9 (& mut self) -> SMP9_W < SAMPTR2_SPEC > { SMP9_W :: new (self , 27) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "sample time register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`samptr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`samptr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SAMPTR2_SPEC ; impl crate :: RegisterSpec for SAMPTR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`samptr2::R`](R) reader structure"]
impl crate :: Readable for SAMPTR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`samptr2::W`](W) writer structure"]
impl crate :: Writable for SAMPTR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SAMPTR2 to value 0"]
impl crate :: Resettable for SAMPTR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IOFR1 (rw) register accessor: injected channel data offset register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iofr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iofr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iofr1`]
module"]
pub type IOFR1 = crate :: Reg < iofr1 :: IOFR1_SPEC > ; # [doc = "injected channel data offset register x"]
pub mod iofr1 { # [doc = "Register `IOFR1` reader"]
pub type R = crate :: R < IOFR1_SPEC > ; # [doc = "Register `IOFR1` writer"]
pub type W = crate :: W < IOFR1_SPEC > ; # [doc = "Field `JOFFSET1` reader - Data offset for injected channel x"]
pub type JOFFSET1_R = crate :: FieldReader < u16 > ; # [doc = "Field `JOFFSET1` writer - Data offset for injected channel x"]
pub type JOFFSET1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:11 - Data offset for injected channel x"]
# [inline (always)]
pub fn joffset1 (& self) -> JOFFSET1_R { JOFFSET1_R :: new ((self . bits & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:11 - Data offset for injected channel x"]
# [inline (always)]
# [must_use]
pub fn joffset1 (& mut self) -> JOFFSET1_W < IOFR1_SPEC > { JOFFSET1_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "injected channel data offset register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iofr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iofr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IOFR1_SPEC ; impl crate :: RegisterSpec for IOFR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iofr1::R`](R) reader structure"]
impl crate :: Readable for IOFR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`iofr1::W`](W) writer structure"]
impl crate :: Writable for IOFR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IOFR1 to value 0"]
impl crate :: Resettable for IOFR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IOFR2 (rw) register accessor: injected channel data offset register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iofr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iofr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iofr2`]
module"]
pub type IOFR2 = crate :: Reg < iofr2 :: IOFR2_SPEC > ; # [doc = "injected channel data offset register x"]
pub mod iofr2 { # [doc = "Register `IOFR2` reader"]
pub type R = crate :: R < IOFR2_SPEC > ; # [doc = "Register `IOFR2` writer"]
pub type W = crate :: W < IOFR2_SPEC > ; # [doc = "Field `JOFFSET2` reader - Data offset for injected channel x"]
pub type JOFFSET2_R = crate :: FieldReader < u16 > ; # [doc = "Field `JOFFSET2` writer - Data offset for injected channel x"]
pub type JOFFSET2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:11 - Data offset for injected channel x"]
# [inline (always)]
pub fn joffset2 (& self) -> JOFFSET2_R { JOFFSET2_R :: new ((self . bits & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:11 - Data offset for injected channel x"]
# [inline (always)]
# [must_use]
pub fn joffset2 (& mut self) -> JOFFSET2_W < IOFR2_SPEC > { JOFFSET2_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "injected channel data offset register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iofr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iofr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IOFR2_SPEC ; impl crate :: RegisterSpec for IOFR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iofr2::R`](R) reader structure"]
impl crate :: Readable for IOFR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`iofr2::W`](W) writer structure"]
impl crate :: Writable for IOFR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IOFR2 to value 0"]
impl crate :: Resettable for IOFR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IOFR3 (rw) register accessor: injected channel data offset register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iofr3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iofr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iofr3`]
module"]
pub type IOFR3 = crate :: Reg < iofr3 :: IOFR3_SPEC > ; # [doc = "injected channel data offset register x"]
pub mod iofr3 { # [doc = "Register `IOFR3` reader"]
pub type R = crate :: R < IOFR3_SPEC > ; # [doc = "Register `IOFR3` writer"]
pub type W = crate :: W < IOFR3_SPEC > ; # [doc = "Field `JOFFSET3` reader - Data offset for injected channel x"]
pub type JOFFSET3_R = crate :: FieldReader < u16 > ; # [doc = "Field `JOFFSET3` writer - Data offset for injected channel x"]
pub type JOFFSET3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:11 - Data offset for injected channel x"]
# [inline (always)]
pub fn joffset3 (& self) -> JOFFSET3_R { JOFFSET3_R :: new ((self . bits & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:11 - Data offset for injected channel x"]
# [inline (always)]
# [must_use]
pub fn joffset3 (& mut self) -> JOFFSET3_W < IOFR3_SPEC > { JOFFSET3_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "injected channel data offset register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iofr3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iofr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IOFR3_SPEC ; impl crate :: RegisterSpec for IOFR3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iofr3::R`](R) reader structure"]
impl crate :: Readable for IOFR3_SPEC { } # [doc = "`write(|w| ..)` method takes [`iofr3::W`](W) writer structure"]
impl crate :: Writable for IOFR3_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IOFR3 to value 0"]
impl crate :: Resettable for IOFR3_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IOFR4 (rw) register accessor: injected channel data offset register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iofr4::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iofr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iofr4`]
module"]
pub type IOFR4 = crate :: Reg < iofr4 :: IOFR4_SPEC > ; # [doc = "injected channel data offset register x"]
pub mod iofr4 { # [doc = "Register `IOFR4` reader"]
pub type R = crate :: R < IOFR4_SPEC > ; # [doc = "Register `IOFR4` writer"]
pub type W = crate :: W < IOFR4_SPEC > ; # [doc = "Field `JOFFSET4` reader - Data offset for injected channel x"]
pub type JOFFSET4_R = crate :: FieldReader < u16 > ; # [doc = "Field `JOFFSET4` writer - Data offset for injected channel x"]
pub type JOFFSET4_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:11 - Data offset for injected channel x"]
# [inline (always)]
pub fn joffset4 (& self) -> JOFFSET4_R { JOFFSET4_R :: new ((self . bits & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:11 - Data offset for injected channel x"]
# [inline (always)]
# [must_use]
pub fn joffset4 (& mut self) -> JOFFSET4_W < IOFR4_SPEC > { JOFFSET4_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "injected channel data offset register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iofr4::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iofr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IOFR4_SPEC ; impl crate :: RegisterSpec for IOFR4_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iofr4::R`](R) reader structure"]
impl crate :: Readable for IOFR4_SPEC { } # [doc = "`write(|w| ..)` method takes [`iofr4::W`](W) writer structure"]
impl crate :: Writable for IOFR4_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IOFR4 to value 0"]
impl crate :: Resettable for IOFR4_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "WDHTR (rw) register accessor: watchdog higher threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdhtr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdhtr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdhtr`]
module"]
pub type WDHTR = crate :: Reg < wdhtr :: WDHTR_SPEC > ; # [doc = "watchdog higher threshold register"]
pub mod wdhtr { # [doc = "Register `WDHTR` reader"]
pub type R = crate :: R < WDHTR_SPEC > ; # [doc = "Register `WDHTR` writer"]
pub type W = crate :: W < WDHTR_SPEC > ; # [doc = "Field `HT` reader - Analog watchdog higher threshold"]
pub type HT_R = crate :: FieldReader < u16 > ; # [doc = "Field `HT` writer - Analog watchdog higher threshold"]
pub type HT_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:11 - Analog watchdog higher threshold"]
# [inline (always)]
pub fn ht (& self) -> HT_R { HT_R :: new ((self . bits & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:11 - Analog watchdog higher threshold"]
# [inline (always)]
# [must_use]
pub fn ht (& mut self) -> HT_W < WDHTR_SPEC > { HT_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "watchdog higher threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdhtr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdhtr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WDHTR_SPEC ; impl crate :: RegisterSpec for WDHTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wdhtr::R`](R) reader structure"]
impl crate :: Readable for WDHTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`wdhtr::W`](W) writer structure"]
impl crate :: Writable for WDHTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets WDHTR to value 0"]
impl crate :: Resettable for WDHTR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "WDLTR (rw) register accessor: watchdog lower threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdltr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdltr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdltr`]
module"]
pub type WDLTR = crate :: Reg < wdltr :: WDLTR_SPEC > ; # [doc = "watchdog lower threshold register"]
pub mod wdltr { # [doc = "Register `WDLTR` reader"]
pub type R = crate :: R < WDLTR_SPEC > ; # [doc = "Register `WDLTR` writer"]
pub type W = crate :: W < WDLTR_SPEC > ; # [doc = "Field `LT` reader - Analog watchdog lower threshold"]
pub type LT_R = crate :: FieldReader < u16 > ; # [doc = "Field `LT` writer - Analog watchdog lower threshold"]
pub type LT_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:11 - Analog watchdog lower threshold"]
# [inline (always)]
pub fn lt (& self) -> LT_R { LT_R :: new ((self . bits & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:11 - Analog watchdog lower threshold"]
# [inline (always)]
# [must_use]
pub fn lt (& mut self) -> LT_W < WDLTR_SPEC > { LT_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "watchdog lower threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdltr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdltr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WDLTR_SPEC ; impl crate :: RegisterSpec for WDLTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wdltr::R`](R) reader structure"]
impl crate :: Readable for WDLTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`wdltr::W`](W) writer structure"]
impl crate :: Writable for WDLTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets WDLTR to value 0"]
impl crate :: Resettable for WDLTR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "RSQR1 (rw) register accessor: regular sequence register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsqr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsqr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsqr1`]
module"]
pub type RSQR1 = crate :: Reg < rsqr1 :: RSQR1_SPEC > ; # [doc = "regular sequence register 1"]
pub mod rsqr1 { # [doc = "Register `RSQR1` reader"]
pub type R = crate :: R < RSQR1_SPEC > ; # [doc = "Register `RSQR1` writer"]
pub type W = crate :: W < RSQR1_SPEC > ; # [doc = "Field `SQ13` reader - 13th conversion in regular sequence"]
pub type SQ13_R = crate :: FieldReader ; # [doc = "Field `SQ13` writer - 13th conversion in regular sequence"]
pub type SQ13_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SQ14` reader - 14th conversion in regular sequence"]
pub type SQ14_R = crate :: FieldReader ; # [doc = "Field `SQ14` writer - 14th conversion in regular sequence"]
pub type SQ14_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SQ15` reader - 15th conversion in regular sequence"]
pub type SQ15_R = crate :: FieldReader ; # [doc = "Field `SQ15` writer - 15th conversion in regular sequence"]
pub type SQ15_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SQ16` reader - 16th conversion in regular sequence"]
pub type SQ16_R = crate :: FieldReader ; # [doc = "Field `SQ16` writer - 16th conversion in regular sequence"]
pub type SQ16_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `L` reader - Regular channel sequence length"]
pub type L_R = crate :: FieldReader ; # [doc = "Field `L` writer - Regular channel sequence length"]
pub type L_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:4 - 13th conversion in regular sequence"]
# [inline (always)]
pub fn sq13 (& self) -> SQ13_R { SQ13_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 5:9 - 14th conversion in regular sequence"]
# [inline (always)]
pub fn sq14 (& self) -> SQ14_R { SQ14_R :: new (((self . bits >> 5) & 0x1f) as u8) } # [doc = "Bits 10:14 - 15th conversion in regular sequence"]
# [inline (always)]
pub fn sq15 (& self) -> SQ15_R { SQ15_R :: new (((self . bits >> 10) & 0x1f) as u8) } # [doc = "Bits 15:19 - 16th conversion in regular sequence"]
# [inline (always)]
pub fn sq16 (& self) -> SQ16_R { SQ16_R :: new (((self . bits >> 15) & 0x1f) as u8) } # [doc = "Bits 20:23 - Regular channel sequence length"]
# [inline (always)]
pub fn l (& self) -> L_R { L_R :: new (((self . bits >> 20) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:4 - 13th conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq13 (& mut self) -> SQ13_W < RSQR1_SPEC > { SQ13_W :: new (self , 0) } # [doc = "Bits 5:9 - 14th conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq14 (& mut self) -> SQ14_W < RSQR1_SPEC > { SQ14_W :: new (self , 5) } # [doc = "Bits 10:14 - 15th conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq15 (& mut self) -> SQ15_W < RSQR1_SPEC > { SQ15_W :: new (self , 10) } # [doc = "Bits 15:19 - 16th conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq16 (& mut self) -> SQ16_W < RSQR1_SPEC > { SQ16_W :: new (self , 15) } # [doc = "Bits 20:23 - Regular channel sequence length"]
# [inline (always)]
# [must_use]
pub fn l (& mut self) -> L_W < RSQR1_SPEC > { L_W :: new (self , 20) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "regular sequence register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsqr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsqr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSQR1_SPEC ; impl crate :: RegisterSpec for RSQR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rsqr1::R`](R) reader structure"]
impl crate :: Readable for RSQR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`rsqr1::W`](W) writer structure"]
impl crate :: Writable for RSQR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RSQR1 to value 0"]
impl crate :: Resettable for RSQR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "RSQR2 (rw) register accessor: regular sequence register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsqr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsqr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsqr2`]
module"]
pub type RSQR2 = crate :: Reg < rsqr2 :: RSQR2_SPEC > ; # [doc = "regular sequence register 2"]
pub mod rsqr2 { # [doc = "Register `RSQR2` reader"]
pub type R = crate :: R < RSQR2_SPEC > ; # [doc = "Register `RSQR2` writer"]
pub type W = crate :: W < RSQR2_SPEC > ; # [doc = "Field `SQ7` reader - 7th conversion in regular sequence"]
pub type SQ7_R = crate :: FieldReader ; # [doc = "Field `SQ7` writer - 7th conversion in regular sequence"]
pub type SQ7_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SQ8` reader - 8th conversion in regular sequence"]
pub type SQ8_R = crate :: FieldReader ; # [doc = "Field `SQ8` writer - 8th conversion in regular sequence"]
pub type SQ8_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SQ9` reader - 9th conversion in regular sequence"]
pub type SQ9_R = crate :: FieldReader ; # [doc = "Field `SQ9` writer - 9th conversion in regular sequence"]
pub type SQ9_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SQ10` reader - 10th conversion in regular sequence"]
pub type SQ10_R = crate :: FieldReader ; # [doc = "Field `SQ10` writer - 10th conversion in regular sequence"]
pub type SQ10_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SQ11` reader - 11th conversion in regular sequence"]
pub type SQ11_R = crate :: FieldReader ; # [doc = "Field `SQ11` writer - 11th conversion in regular sequence"]
pub type SQ11_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SQ12` reader - 12th conversion in regular sequence"]
pub type SQ12_R = crate :: FieldReader ; # [doc = "Field `SQ12` writer - 12th conversion in regular sequence"]
pub type SQ12_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bits 0:4 - 7th conversion in regular sequence"]
# [inline (always)]
pub fn sq7 (& self) -> SQ7_R { SQ7_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 5:9 - 8th conversion in regular sequence"]
# [inline (always)]
pub fn sq8 (& self) -> SQ8_R { SQ8_R :: new (((self . bits >> 5) & 0x1f) as u8) } # [doc = "Bits 10:14 - 9th conversion in regular sequence"]
# [inline (always)]
pub fn sq9 (& self) -> SQ9_R { SQ9_R :: new (((self . bits >> 10) & 0x1f) as u8) } # [doc = "Bits 15:19 - 10th conversion in regular sequence"]
# [inline (always)]
pub fn sq10 (& self) -> SQ10_R { SQ10_R :: new (((self . bits >> 15) & 0x1f) as u8) } # [doc = "Bits 20:24 - 11th conversion in regular sequence"]
# [inline (always)]
pub fn sq11 (& self) -> SQ11_R { SQ11_R :: new (((self . bits >> 20) & 0x1f) as u8) } # [doc = "Bits 25:29 - 12th conversion in regular sequence"]
# [inline (always)]
pub fn sq12 (& self) -> SQ12_R { SQ12_R :: new (((self . bits >> 25) & 0x1f) as u8) } } impl W { # [doc = "Bits 0:4 - 7th conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq7 (& mut self) -> SQ7_W < RSQR2_SPEC > { SQ7_W :: new (self , 0) } # [doc = "Bits 5:9 - 8th conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq8 (& mut self) -> SQ8_W < RSQR2_SPEC > { SQ8_W :: new (self , 5) } # [doc = "Bits 10:14 - 9th conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq9 (& mut self) -> SQ9_W < RSQR2_SPEC > { SQ9_W :: new (self , 10) } # [doc = "Bits 15:19 - 10th conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq10 (& mut self) -> SQ10_W < RSQR2_SPEC > { SQ10_W :: new (self , 15) } # [doc = "Bits 20:24 - 11th conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq11 (& mut self) -> SQ11_W < RSQR2_SPEC > { SQ11_W :: new (self , 20) } # [doc = "Bits 25:29 - 12th conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq12 (& mut self) -> SQ12_W < RSQR2_SPEC > { SQ12_W :: new (self , 25) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "regular sequence register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsqr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsqr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSQR2_SPEC ; impl crate :: RegisterSpec for RSQR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rsqr2::R`](R) reader structure"]
impl crate :: Readable for RSQR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`rsqr2::W`](W) writer structure"]
impl crate :: Writable for RSQR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RSQR2 to value 0"]
impl crate :: Resettable for RSQR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "RSQR3 (rw) register accessor: regular sequence register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsqr3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsqr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsqr3`]
module"]
pub type RSQR3 = crate :: Reg < rsqr3 :: RSQR3_SPEC > ; # [doc = "regular sequence register 3"]
pub mod rsqr3 { # [doc = "Register `RSQR3` reader"]
pub type R = crate :: R < RSQR3_SPEC > ; # [doc = "Register `RSQR3` writer"]
pub type W = crate :: W < RSQR3_SPEC > ; # [doc = "Field `SQ1` reader - 1st conversion in regular sequence"]
pub type SQ1_R = crate :: FieldReader ; # [doc = "Field `SQ1` writer - 1st conversion in regular sequence"]
pub type SQ1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SQ2` reader - 2nd conversion in regular sequence"]
pub type SQ2_R = crate :: FieldReader ; # [doc = "Field `SQ2` writer - 2nd conversion in regular sequence"]
pub type SQ2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SQ3` reader - 3rd conversion in regular sequence"]
pub type SQ3_R = crate :: FieldReader ; # [doc = "Field `SQ3` writer - 3rd conversion in regular sequence"]
pub type SQ3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SQ4` reader - 4th conversion in regular sequence"]
pub type SQ4_R = crate :: FieldReader ; # [doc = "Field `SQ4` writer - 4th conversion in regular sequence"]
pub type SQ4_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SQ5` reader - 5th conversion in regular sequence"]
pub type SQ5_R = crate :: FieldReader ; # [doc = "Field `SQ5` writer - 5th conversion in regular sequence"]
pub type SQ5_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `SQ6` reader - 6th conversion in regular sequence"]
pub type SQ6_R = crate :: FieldReader ; # [doc = "Field `SQ6` writer - 6th conversion in regular sequence"]
pub type SQ6_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; impl R { # [doc = "Bits 0:4 - 1st conversion in regular sequence"]
# [inline (always)]
pub fn sq1 (& self) -> SQ1_R { SQ1_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 5:9 - 2nd conversion in regular sequence"]
# [inline (always)]
pub fn sq2 (& self) -> SQ2_R { SQ2_R :: new (((self . bits >> 5) & 0x1f) as u8) } # [doc = "Bits 10:14 - 3rd conversion in regular sequence"]
# [inline (always)]
pub fn sq3 (& self) -> SQ3_R { SQ3_R :: new (((self . bits >> 10) & 0x1f) as u8) } # [doc = "Bits 15:19 - 4th conversion in regular sequence"]
# [inline (always)]
pub fn sq4 (& self) -> SQ4_R { SQ4_R :: new (((self . bits >> 15) & 0x1f) as u8) } # [doc = "Bits 20:24 - 5th conversion in regular sequence"]
# [inline (always)]
pub fn sq5 (& self) -> SQ5_R { SQ5_R :: new (((self . bits >> 20) & 0x1f) as u8) } # [doc = "Bits 25:29 - 6th conversion in regular sequence"]
# [inline (always)]
pub fn sq6 (& self) -> SQ6_R { SQ6_R :: new (((self . bits >> 25) & 0x1f) as u8) } } impl W { # [doc = "Bits 0:4 - 1st conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq1 (& mut self) -> SQ1_W < RSQR3_SPEC > { SQ1_W :: new (self , 0) } # [doc = "Bits 5:9 - 2nd conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq2 (& mut self) -> SQ2_W < RSQR3_SPEC > { SQ2_W :: new (self , 5) } # [doc = "Bits 10:14 - 3rd conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq3 (& mut self) -> SQ3_W < RSQR3_SPEC > { SQ3_W :: new (self , 10) } # [doc = "Bits 15:19 - 4th conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq4 (& mut self) -> SQ4_W < RSQR3_SPEC > { SQ4_W :: new (self , 15) } # [doc = "Bits 20:24 - 5th conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq5 (& mut self) -> SQ5_W < RSQR3_SPEC > { SQ5_W :: new (self , 20) } # [doc = "Bits 25:29 - 6th conversion in regular sequence"]
# [inline (always)]
# [must_use]
pub fn sq6 (& mut self) -> SQ6_W < RSQR3_SPEC > { SQ6_W :: new (self , 25) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "regular sequence register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsqr3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsqr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSQR3_SPEC ; impl crate :: RegisterSpec for RSQR3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rsqr3::R`](R) reader structure"]
impl crate :: Readable for RSQR3_SPEC { } # [doc = "`write(|w| ..)` method takes [`rsqr3::W`](W) writer structure"]
impl crate :: Writable for RSQR3_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets RSQR3 to value 0"]
impl crate :: Resettable for RSQR3_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "ISQR (rw) register accessor: injected sequence register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isqr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isqr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isqr`]
module"]
pub type ISQR = crate :: Reg < isqr :: ISQR_SPEC > ; # [doc = "injected sequence register"]
pub mod isqr { # [doc = "Register `ISQR` reader"]
pub type R = crate :: R < ISQR_SPEC > ; # [doc = "Register `ISQR` writer"]
pub type W = crate :: W < ISQR_SPEC > ; # [doc = "Field `JSQ1` reader - 1st conversion in injected sequence"]
pub type JSQ1_R = crate :: FieldReader ; # [doc = "Field `JSQ1` writer - 1st conversion in injected sequence"]
pub type JSQ1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `JSQ2` reader - 2nd conversion in injected sequence"]
pub type JSQ2_R = crate :: FieldReader ; # [doc = "Field `JSQ2` writer - 2nd conversion in injected sequence"]
pub type JSQ2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `JSQ3` reader - 3rd conversion in injected sequence"]
pub type JSQ3_R = crate :: FieldReader ; # [doc = "Field `JSQ3` writer - 3rd conversion in injected sequence"]
pub type JSQ3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `JSQ4` reader - 4th conversion in injected sequence"]
pub type JSQ4_R = crate :: FieldReader ; # [doc = "Field `JSQ4` writer - 4th conversion in injected sequence"]
pub type JSQ4_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 5 > ; # [doc = "Field `JL` reader - Injected sequence length"]
pub type JL_R = crate :: FieldReader ; # [doc = "Field `JL` writer - Injected sequence length"]
pub type JL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; impl R { # [doc = "Bits 0:4 - 1st conversion in injected sequence"]
# [inline (always)]
pub fn jsq1 (& self) -> JSQ1_R { JSQ1_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 5:9 - 2nd conversion in injected sequence"]
# [inline (always)]
pub fn jsq2 (& self) -> JSQ2_R { JSQ2_R :: new (((self . bits >> 5) & 0x1f) as u8) } # [doc = "Bits 10:14 - 3rd conversion in injected sequence"]
# [inline (always)]
pub fn jsq3 (& self) -> JSQ3_R { JSQ3_R :: new (((self . bits >> 10) & 0x1f) as u8) } # [doc = "Bits 15:19 - 4th conversion in injected sequence"]
# [inline (always)]
pub fn jsq4 (& self) -> JSQ4_R { JSQ4_R :: new (((self . bits >> 15) & 0x1f) as u8) } # [doc = "Bits 20:21 - Injected sequence length"]
# [inline (always)]
pub fn jl (& self) -> JL_R { JL_R :: new (((self . bits >> 20) & 3) as u8) } } impl W { # [doc = "Bits 0:4 - 1st conversion in injected sequence"]
# [inline (always)]
# [must_use]
pub fn jsq1 (& mut self) -> JSQ1_W < ISQR_SPEC > { JSQ1_W :: new (self , 0) } # [doc = "Bits 5:9 - 2nd conversion in injected sequence"]
# [inline (always)]
# [must_use]
pub fn jsq2 (& mut self) -> JSQ2_W < ISQR_SPEC > { JSQ2_W :: new (self , 5) } # [doc = "Bits 10:14 - 3rd conversion in injected sequence"]
# [inline (always)]
# [must_use]
pub fn jsq3 (& mut self) -> JSQ3_W < ISQR_SPEC > { JSQ3_W :: new (self , 10) } # [doc = "Bits 15:19 - 4th conversion in injected sequence"]
# [inline (always)]
# [must_use]
pub fn jsq4 (& mut self) -> JSQ4_W < ISQR_SPEC > { JSQ4_W :: new (self , 15) } # [doc = "Bits 20:21 - Injected sequence length"]
# [inline (always)]
# [must_use]
pub fn jl (& mut self) -> JL_W < ISQR_SPEC > { JL_W :: new (self , 20) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "injected sequence register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isqr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isqr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISQR_SPEC ; impl crate :: RegisterSpec for ISQR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`isqr::R`](R) reader structure"]
impl crate :: Readable for ISQR_SPEC { } # [doc = "`write(|w| ..)` method takes [`isqr::W`](W) writer structure"]
impl crate :: Writable for ISQR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ISQR to value 0"]
impl crate :: Resettable for ISQR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IDATAR1 (r) register accessor: injected data register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idatar1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idatar1`]
module"]
pub type IDATAR1 = crate :: Reg < idatar1 :: IDATAR1_SPEC > ; # [doc = "injected data register x"]
pub mod idatar1 { # [doc = "Register `IDATAR1` reader"]
pub type R = crate :: R < IDATAR1_SPEC > ; # [doc = "Field `JDATA` reader - Injected data"]
pub type JDATA_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:15 - Injected data"]
# [inline (always)]
pub fn jdata (& self) -> JDATA_R { JDATA_R :: new ((self . bits & 0xffff) as u16) } } # [doc = "injected data register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idatar1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IDATAR1_SPEC ; impl crate :: RegisterSpec for IDATAR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`idatar1::R`](R) reader structure"]
impl crate :: Readable for IDATAR1_SPEC { } # [doc = "`reset()` method sets IDATAR1 to value 0"]
impl crate :: Resettable for IDATAR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IDATAR2 (r) register accessor: injected data register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idatar2::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idatar2`]
module"]
pub type IDATAR2 = crate :: Reg < idatar2 :: IDATAR2_SPEC > ; # [doc = "injected data register x"]
pub mod idatar2 { # [doc = "Register `IDATAR2` reader"]
pub type R = crate :: R < IDATAR2_SPEC > ; # [doc = "Field `JDATA` reader - Injected data"]
pub type JDATA_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:15 - Injected data"]
# [inline (always)]
pub fn jdata (& self) -> JDATA_R { JDATA_R :: new ((self . bits & 0xffff) as u16) } } # [doc = "injected data register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idatar2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IDATAR2_SPEC ; impl crate :: RegisterSpec for IDATAR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`idatar2::R`](R) reader structure"]
impl crate :: Readable for IDATAR2_SPEC { } # [doc = "`reset()` method sets IDATAR2 to value 0"]
impl crate :: Resettable for IDATAR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IDATAR3 (r) register accessor: injected data register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idatar3::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idatar3`]
module"]
pub type IDATAR3 = crate :: Reg < idatar3 :: IDATAR3_SPEC > ; # [doc = "injected data register x"]
pub mod idatar3 { # [doc = "Register `IDATAR3` reader"]
pub type R = crate :: R < IDATAR3_SPEC > ; # [doc = "Field `JDATA` reader - Injected data"]
pub type JDATA_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:15 - Injected data"]
# [inline (always)]
pub fn jdata (& self) -> JDATA_R { JDATA_R :: new ((self . bits & 0xffff) as u16) } } # [doc = "injected data register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idatar3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IDATAR3_SPEC ; impl crate :: RegisterSpec for IDATAR3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`idatar3::R`](R) reader structure"]
impl crate :: Readable for IDATAR3_SPEC { } # [doc = "`reset()` method sets IDATAR3 to value 0"]
impl crate :: Resettable for IDATAR3_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IDATAR4 (r) register accessor: injected data register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idatar4::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idatar4`]
module"]
pub type IDATAR4 = crate :: Reg < idatar4 :: IDATAR4_SPEC > ; # [doc = "injected data register x"]
pub mod idatar4 { # [doc = "Register `IDATAR4` reader"]
pub type R = crate :: R < IDATAR4_SPEC > ; # [doc = "Field `JDATA` reader - Injected data"]
pub type JDATA_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:15 - Injected data"]
# [inline (always)]
pub fn jdata (& self) -> JDATA_R { JDATA_R :: new ((self . bits & 0xffff) as u16) } } # [doc = "injected data register x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idatar4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IDATAR4_SPEC ; impl crate :: RegisterSpec for IDATAR4_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`idatar4::R`](R) reader structure"]
impl crate :: Readable for IDATAR4_SPEC { } # [doc = "`reset()` method sets IDATAR4 to value 0"]
impl crate :: Resettable for IDATAR4_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "RDATAR (r) register accessor: regular data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdatar::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdatar`]
module"]
pub type RDATAR = crate :: Reg < rdatar :: RDATAR_SPEC > ; # [doc = "regular data register"]
pub mod rdatar { # [doc = "Register `RDATAR` reader"]
pub type R = crate :: R < RDATAR_SPEC > ; # [doc = "Field `DATA` reader - Regular data"]
pub type DATA_R = crate :: FieldReader < u16 > ; # [doc = "Field `ADC2DATA` reader - ADC2 data"]
pub type ADC2DATA_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:15 - Regular data"]
# [inline (always)]
pub fn data (& self) -> DATA_R { DATA_R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - ADC2 data"]
# [inline (always)]
pub fn adc2data (& self) -> ADC2DATA_R { ADC2DATA_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "regular data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdatar::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RDATAR_SPEC ; impl crate :: RegisterSpec for RDATAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rdatar::R`](R) reader structure"]
impl crate :: Readable for RDATAR_SPEC { } # [doc = "`reset()` method sets RDATAR to value 0"]
impl crate :: Resettable for RDATAR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Digital to analog converter"]
pub struct DAC1 { _marker : PhantomData < * const () > } unsafe impl Send for DAC1 { } impl DAC1 { # [doc = r"Pointer to the register block"]
pub const PTR : * const dac1 :: RegisterBlock = 0x4000_7400 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const dac1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for DAC1 { type Target = dac1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for DAC1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("DAC1") . finish () } } # [doc = "Digital to analog converter"]
pub mod dac1 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { ctlr : CTLR , swtr : SWTR , r12bdhr1 : R12BDHR1 , l12bdhr1 : L12BDHR1 , _reserved4 : [u8 ; 0x04]
, r12bdhr2 : R12BDHR2 , l12bdhr2 : L12BDHR2 , _reserved6 : [u8 ; 0x10]
, dor1 : DOR1 , dor2 : DOR2 , } impl RegisterBlock { # [doc = "0x00 - Control register (DAC_CTLR)"]
# [inline (always)]
pub const fn ctlr (& self) -> & CTLR { & self . ctlr } # [doc = "0x04 - DAC software trigger register (DAC_SWTR)"]
# [inline (always)]
pub const fn swtr (& self) -> & SWTR { & self . swtr } # [doc = "0x08 - DAC channel1 12-bit right-aligned data holding register(DAC_R12BDHR1)"]
# [inline (always)]
pub const fn r12bdhr1 (& self) -> & R12BDHR1 { & self . r12bdhr1 } # [doc = "0x0c - DAC channel1 12-bit left aligned data holding register (DAC_L12BDHR1)"]
# [inline (always)]
pub const fn l12bdhr1 (& self) -> & L12BDHR1 { & self . l12bdhr1 } # [doc = "0x14 - DAC channel2 12-bit right aligned data holding register (DAC_R12BDHR2)"]
# [inline (always)]
pub const fn r12bdhr2 (& self) -> & R12BDHR2 { & self . r12bdhr2 } # [doc = "0x18 - DAC channel2 12-bit left aligned data holding register (DAC_L12BDHR2)"]
# [inline (always)]
pub const fn l12bdhr2 (& self) -> & L12BDHR2 { & self . l12bdhr2 } # [doc = "0x2c - DAC channel1 data output register (DAC_DOR1)"]
# [inline (always)]
pub const fn dor1 (& self) -> & DOR1 { & self . dor1 } # [doc = "0x30 - DAC channel2 data output register (DAC_DOR2)"]
# [inline (always)]
pub const fn dor2 (& self) -> & DOR2 { & self . dor2 } } # [doc = "CTLR (rw) register accessor: Control register (DAC_CTLR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr`]
module"]
pub type CTLR = crate :: Reg < ctlr :: CTLR_SPEC > ; # [doc = "Control register (DAC_CTLR)"]
pub mod ctlr { # [doc = "Register `CTLR` reader"]
pub type R = crate :: R < CTLR_SPEC > ; # [doc = "Register `CTLR` writer"]
pub type W = crate :: W < CTLR_SPEC > ; # [doc = "Field `EN1` reader - DAC channel1 enable"]
pub type EN1_R = crate :: BitReader ; # [doc = "Field `EN1` writer - DAC channel1 enable"]
pub type EN1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BOFF1` reader - DAC channel1 output buffer disable"]
pub type BOFF1_R = crate :: BitReader ; # [doc = "Field `BOFF1` writer - DAC channel1 output buffer disable"]
pub type BOFF1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEN1` reader - DAC channel1 trigger enable"]
pub type TEN1_R = crate :: BitReader ; # [doc = "Field `TEN1` writer - DAC channel1 trigger enable"]
pub type TEN1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TSEL1` reader - DAC channel1 trigger selection"]
pub type TSEL1_R = crate :: FieldReader ; # [doc = "Field `TSEL1` writer - DAC channel1 trigger selection"]
pub type TSEL1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `WAVE1` reader - DAC channel1 noise/triangle wave generation enable"]
pub type WAVE1_R = crate :: FieldReader ; # [doc = "Field `WAVE1` writer - DAC channel1 noise/triangle wave generation enable"]
pub type WAVE1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MAMP1` reader - DAC channel1 mask/amplitude selector"]
pub type MAMP1_R = crate :: FieldReader ; # [doc = "Field `MAMP1` writer - DAC channel1 mask/amplitude selector"]
pub type MAMP1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DMAEN1` reader - DAC channel1 DMA enable"]
pub type DMAEN1_R = crate :: BitReader ; # [doc = "Field `DMAEN1` writer - DAC channel1 DMA enable"]
pub type DMAEN1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EN2` reader - DAC channel2 enable"]
pub type EN2_R = crate :: BitReader ; # [doc = "Field `EN2` writer - DAC channel2 enable"]
pub type EN2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BOFF2` reader - DAC channel2 output buffer disable"]
pub type BOFF2_R = crate :: BitReader ; # [doc = "Field `BOFF2` writer - DAC channel2 output buffer disable"]
pub type BOFF2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TEN2` reader - DAC channel2 trigger enable"]
pub type TEN2_R = crate :: BitReader ; # [doc = "Field `TEN2` writer - DAC channel2 trigger enable"]
pub type TEN2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TSEL2` reader - DAC channel2 trigger selection"]
pub type TSEL2_R = crate :: FieldReader ; # [doc = "Field `TSEL2` writer - DAC channel2 trigger selection"]
pub type TSEL2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `WAVE2` reader - DAC channel2 noise/triangle wave generation enable"]
pub type WAVE2_R = crate :: FieldReader ; # [doc = "Field `WAVE2` writer - DAC channel2 noise/triangle wave generation enable"]
pub type WAVE2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MAMP2` reader - DAC channel2 mask/amplitude selector"]
pub type MAMP2_R = crate :: FieldReader ; # [doc = "Field `MAMP2` writer - DAC channel2 mask/amplitude selector"]
pub type MAMP2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DMAEN2` reader - DAC channel2 DMA enable"]
pub type DMAEN2_R = crate :: BitReader ; # [doc = "Field `DMAEN2` writer - DAC channel2 DMA enable"]
pub type DMAEN2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DAC channel1 enable"]
# [inline (always)]
pub fn en1 (& self) -> EN1_R { EN1_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DAC channel1 output buffer disable"]
# [inline (always)]
pub fn boff1 (& self) -> BOFF1_R { BOFF1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DAC channel1 trigger enable"]
# [inline (always)]
pub fn ten1 (& self) -> TEN1_R { TEN1_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:5 - DAC channel1 trigger selection"]
# [inline (always)]
pub fn tsel1 (& self) -> TSEL1_R { TSEL1_R :: new (((self . bits >> 3) & 7) as u8) } # [doc = "Bits 6:7 - DAC channel1 noise/triangle wave generation enable"]
# [inline (always)]
pub fn wave1 (& self) -> WAVE1_R { WAVE1_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:11 - DAC channel1 mask/amplitude selector"]
# [inline (always)]
pub fn mamp1 (& self) -> MAMP1_R { MAMP1_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 12 - DAC channel1 DMA enable"]
# [inline (always)]
pub fn dmaen1 (& self) -> DMAEN1_R { DMAEN1_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 16 - DAC channel2 enable"]
# [inline (always)]
pub fn en2 (& self) -> EN2_R { EN2_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DAC channel2 output buffer disable"]
# [inline (always)]
pub fn boff2 (& self) -> BOFF2_R { BOFF2_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DAC channel2 trigger enable"]
# [inline (always)]
pub fn ten2 (& self) -> TEN2_R { TEN2_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bits 19:21 - DAC channel2 trigger selection"]
# [inline (always)]
pub fn tsel2 (& self) -> TSEL2_R { TSEL2_R :: new (((self . bits >> 19) & 7) as u8) } # [doc = "Bits 22:23 - DAC channel2 noise/triangle wave generation enable"]
# [inline (always)]
pub fn wave2 (& self) -> WAVE2_R { WAVE2_R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bits 24:27 - DAC channel2 mask/amplitude selector"]
# [inline (always)]
pub fn mamp2 (& self) -> MAMP2_R { MAMP2_R :: new (((self . bits >> 24) & 0x0f) as u8) } # [doc = "Bit 28 - DAC channel2 DMA enable"]
# [inline (always)]
pub fn dmaen2 (& self) -> DMAEN2_R { DMAEN2_R :: new (((self . bits >> 28) & 1) != 0) } } impl W { # [doc = "Bit 0 - DAC channel1 enable"]
# [inline (always)]
# [must_use]
pub fn en1 (& mut self) -> EN1_W < CTLR_SPEC > { EN1_W :: new (self , 0) } # [doc = "Bit 1 - DAC channel1 output buffer disable"]
# [inline (always)]
# [must_use]
pub fn boff1 (& mut self) -> BOFF1_W < CTLR_SPEC > { BOFF1_W :: new (self , 1) } # [doc = "Bit 2 - DAC channel1 trigger enable"]
# [inline (always)]
# [must_use]
pub fn ten1 (& mut self) -> TEN1_W < CTLR_SPEC > { TEN1_W :: new (self , 2) } # [doc = "Bits 3:5 - DAC channel1 trigger selection"]
# [inline (always)]
# [must_use]
pub fn tsel1 (& mut self) -> TSEL1_W < CTLR_SPEC > { TSEL1_W :: new (self , 3) } # [doc = "Bits 6:7 - DAC channel1 noise/triangle wave generation enable"]
# [inline (always)]
# [must_use]
pub fn wave1 (& mut self) -> WAVE1_W < CTLR_SPEC > { WAVE1_W :: new (self , 6) } # [doc = "Bits 8:11 - DAC channel1 mask/amplitude selector"]
# [inline (always)]
# [must_use]
pub fn mamp1 (& mut self) -> MAMP1_W < CTLR_SPEC > { MAMP1_W :: new (self , 8) } # [doc = "Bit 12 - DAC channel1 DMA enable"]
# [inline (always)]
# [must_use]
pub fn dmaen1 (& mut self) -> DMAEN1_W < CTLR_SPEC > { DMAEN1_W :: new (self , 12) } # [doc = "Bit 16 - DAC channel2 enable"]
# [inline (always)]
# [must_use]
pub fn en2 (& mut self) -> EN2_W < CTLR_SPEC > { EN2_W :: new (self , 16) } # [doc = "Bit 17 - DAC channel2 output buffer disable"]
# [inline (always)]
# [must_use]
pub fn boff2 (& mut self) -> BOFF2_W < CTLR_SPEC > { BOFF2_W :: new (self , 17) } # [doc = "Bit 18 - DAC channel2 trigger enable"]
# [inline (always)]
# [must_use]
pub fn ten2 (& mut self) -> TEN2_W < CTLR_SPEC > { TEN2_W :: new (self , 18) } # [doc = "Bits 19:21 - DAC channel2 trigger selection"]
# [inline (always)]
# [must_use]
pub fn tsel2 (& mut self) -> TSEL2_W < CTLR_SPEC > { TSEL2_W :: new (self , 19) } # [doc = "Bits 22:23 - DAC channel2 noise/triangle wave generation enable"]
# [inline (always)]
# [must_use]
pub fn wave2 (& mut self) -> WAVE2_W < CTLR_SPEC > { WAVE2_W :: new (self , 22) } # [doc = "Bits 24:27 - DAC channel2 mask/amplitude selector"]
# [inline (always)]
# [must_use]
pub fn mamp2 (& mut self) -> MAMP2_W < CTLR_SPEC > { MAMP2_W :: new (self , 24) } # [doc = "Bit 28 - DAC channel2 DMA enable"]
# [inline (always)]
# [must_use]
pub fn dmaen2 (& mut self) -> DMAEN2_W < CTLR_SPEC > { DMAEN2_W :: new (self , 28) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control register (DAC_CTLR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR_SPEC ; impl crate :: RegisterSpec for CTLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr::R`](R) reader structure"]
impl crate :: Readable for CTLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr::W`](W) writer structure"]
impl crate :: Writable for CTLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR to value 0"]
impl crate :: Resettable for CTLR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "SWTR (w) register accessor: DAC software trigger register (DAC_SWTR)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swtr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swtr`]
module"]
pub type SWTR = crate :: Reg < swtr :: SWTR_SPEC > ; # [doc = "DAC software trigger register (DAC_SWTR)"]
pub mod swtr { # [doc = "Register `SWTR` writer"]
pub type W = crate :: W < SWTR_SPEC > ; # [doc = "Field `SWTRIG1` writer - DAC channel1 software trigger"]
pub type SWTRIG1_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SWTRIG2` writer - DAC channel2 software trigger"]
pub type SWTRIG2_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W { # [doc = "Bit 0 - DAC channel1 software trigger"]
# [inline (always)]
# [must_use]
pub fn swtrig1 (& mut self) -> SWTRIG1_W < SWTR_SPEC > { SWTRIG1_W :: new (self , 0) } # [doc = "Bit 1 - DAC channel2 software trigger"]
# [inline (always)]
# [must_use]
pub fn swtrig2 (& mut self) -> SWTRIG2_W < SWTR_SPEC > { SWTRIG2_W :: new (self , 1) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DAC software trigger register (DAC_SWTR)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swtr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SWTR_SPEC ; impl crate :: RegisterSpec for SWTR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`swtr::W`](W) writer structure"]
impl crate :: Writable for SWTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SWTR to value 0"]
impl crate :: Resettable for SWTR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "R12BDHR1 (rw) register accessor: DAC channel1 12-bit right-aligned data holding register(DAC_R12BDHR1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r12bdhr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r12bdhr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r12bdhr1`]
module"]
pub type R12BDHR1 = crate :: Reg < r12bdhr1 :: R12BDHR1_SPEC > ; # [doc = "DAC channel1 12-bit right-aligned data holding register(DAC_R12BDHR1)"]
pub mod r12bdhr1 { # [doc = "Register `R12BDHR1` reader"]
pub type R = crate :: R < R12BDHR1_SPEC > ; # [doc = "Register `R12BDHR1` writer"]
pub type W = crate :: W < R12BDHR1_SPEC > ; # [doc = "Field `DACC1DHR` reader - DAC channel1 12-bit right-aligned data"]
pub type DACC1DHR_R = crate :: FieldReader < u16 > ; # [doc = "Field `DACC1DHR` writer - DAC channel1 12-bit right-aligned data"]
pub type DACC1DHR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:11 - DAC channel1 12-bit right-aligned data"]
# [inline (always)]
pub fn dacc1dhr (& self) -> DACC1DHR_R { DACC1DHR_R :: new ((self . bits & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:11 - DAC channel1 12-bit right-aligned data"]
# [inline (always)]
# [must_use]
pub fn dacc1dhr (& mut self) -> DACC1DHR_W < R12BDHR1_SPEC > { DACC1DHR_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DAC channel1 12-bit right-aligned data holding register(DAC_R12BDHR1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r12bdhr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r12bdhr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R12BDHR1_SPEC ; impl crate :: RegisterSpec for R12BDHR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`r12bdhr1::R`](R) reader structure"]
impl crate :: Readable for R12BDHR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`r12bdhr1::W`](W) writer structure"]
impl crate :: Writable for R12BDHR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets R12BDHR1 to value 0"]
impl crate :: Resettable for R12BDHR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "L12BDHR1 (rw) register accessor: DAC channel1 12-bit left aligned data holding register (DAC_L12BDHR1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l12bdhr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l12bdhr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l12bdhr1`]
module"]
pub type L12BDHR1 = crate :: Reg < l12bdhr1 :: L12BDHR1_SPEC > ; # [doc = "DAC channel1 12-bit left aligned data holding register (DAC_L12BDHR1)"]
pub mod l12bdhr1 { # [doc = "Register `L12BDHR1` reader"]
pub type R = crate :: R < L12BDHR1_SPEC > ; # [doc = "Register `L12BDHR1` writer"]
pub type W = crate :: W < L12BDHR1_SPEC > ; # [doc = "Field `DACC1DHR` reader - DAC channel1 12-bit left-aligned data"]
pub type DACC1DHR_R = crate :: FieldReader < u16 > ; # [doc = "Field `DACC1DHR` writer - DAC channel1 12-bit left-aligned data"]
pub type DACC1DHR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 4:15 - DAC channel1 12-bit left-aligned data"]
# [inline (always)]
pub fn dacc1dhr (& self) -> DACC1DHR_R { DACC1DHR_R :: new (((self . bits >> 4) & 0x0fff) as u16) } } impl W { # [doc = "Bits 4:15 - DAC channel1 12-bit left-aligned data"]
# [inline (always)]
# [must_use]
pub fn dacc1dhr (& mut self) -> DACC1DHR_W < L12BDHR1_SPEC > { DACC1DHR_W :: new (self , 4) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DAC channel1 12-bit left aligned data holding register (DAC_L12BDHR1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l12bdhr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l12bdhr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct L12BDHR1_SPEC ; impl crate :: RegisterSpec for L12BDHR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`l12bdhr1::R`](R) reader structure"]
impl crate :: Readable for L12BDHR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`l12bdhr1::W`](W) writer structure"]
impl crate :: Writable for L12BDHR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets L12BDHR1 to value 0"]
impl crate :: Resettable for L12BDHR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "R12BDHR2 (rw) register accessor: DAC channel2 12-bit right aligned data holding register (DAC_R12BDHR2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r12bdhr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r12bdhr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r12bdhr2`]
module"]
pub type R12BDHR2 = crate :: Reg < r12bdhr2 :: R12BDHR2_SPEC > ; # [doc = "DAC channel2 12-bit right aligned data holding register (DAC_R12BDHR2)"]
pub mod r12bdhr2 { # [doc = "Register `R12BDHR2` reader"]
pub type R = crate :: R < R12BDHR2_SPEC > ; # [doc = "Register `R12BDHR2` writer"]
pub type W = crate :: W < R12BDHR2_SPEC > ; # [doc = "Field `DACC2DHR` reader - DAC channel2 12-bit right-aligned data"]
pub type DACC2DHR_R = crate :: FieldReader < u16 > ; # [doc = "Field `DACC2DHR` writer - DAC channel2 12-bit right-aligned data"]
pub type DACC2DHR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 0:11 - DAC channel2 12-bit right-aligned data"]
# [inline (always)]
pub fn dacc2dhr (& self) -> DACC2DHR_R { DACC2DHR_R :: new ((self . bits & 0x0fff) as u16) } } impl W { # [doc = "Bits 0:11 - DAC channel2 12-bit right-aligned data"]
# [inline (always)]
# [must_use]
pub fn dacc2dhr (& mut self) -> DACC2DHR_W < R12BDHR2_SPEC > { DACC2DHR_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DAC channel2 12-bit right aligned data holding register (DAC_R12BDHR2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r12bdhr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r12bdhr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R12BDHR2_SPEC ; impl crate :: RegisterSpec for R12BDHR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`r12bdhr2::R`](R) reader structure"]
impl crate :: Readable for R12BDHR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`r12bdhr2::W`](W) writer structure"]
impl crate :: Writable for R12BDHR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets R12BDHR2 to value 0"]
impl crate :: Resettable for R12BDHR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "L12BDHR2 (rw) register accessor: DAC channel2 12-bit left aligned data holding register (DAC_L12BDHR2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l12bdhr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l12bdhr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l12bdhr2`]
module"]
pub type L12BDHR2 = crate :: Reg < l12bdhr2 :: L12BDHR2_SPEC > ; # [doc = "DAC channel2 12-bit left aligned data holding register (DAC_L12BDHR2)"]
pub mod l12bdhr2 { # [doc = "Register `L12BDHR2` reader"]
pub type R = crate :: R < L12BDHR2_SPEC > ; # [doc = "Register `L12BDHR2` writer"]
pub type W = crate :: W < L12BDHR2_SPEC > ; # [doc = "Field `DACC2DHR` reader - DAC channel2 12-bit left-aligned data"]
pub type DACC2DHR_R = crate :: FieldReader < u16 > ; # [doc = "Field `DACC2DHR` writer - DAC channel2 12-bit left-aligned data"]
pub type DACC2DHR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 12 , u16 > ; impl R { # [doc = "Bits 4:15 - DAC channel2 12-bit left-aligned data"]
# [inline (always)]
pub fn dacc2dhr (& self) -> DACC2DHR_R { DACC2DHR_R :: new (((self . bits >> 4) & 0x0fff) as u16) } } impl W { # [doc = "Bits 4:15 - DAC channel2 12-bit left-aligned data"]
# [inline (always)]
# [must_use]
pub fn dacc2dhr (& mut self) -> DACC2DHR_W < L12BDHR2_SPEC > { DACC2DHR_W :: new (self , 4) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DAC channel2 12-bit left aligned data holding register (DAC_L12BDHR2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l12bdhr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l12bdhr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct L12BDHR2_SPEC ; impl crate :: RegisterSpec for L12BDHR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`l12bdhr2::R`](R) reader structure"]
impl crate :: Readable for L12BDHR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`l12bdhr2::W`](W) writer structure"]
impl crate :: Writable for L12BDHR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets L12BDHR2 to value 0"]
impl crate :: Resettable for L12BDHR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DOR1 (r) register accessor: DAC channel1 data output register (DAC_DOR1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dor1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dor1`]
module"]
pub type DOR1 = crate :: Reg < dor1 :: DOR1_SPEC > ; # [doc = "DAC channel1 data output register (DAC_DOR1)"]
pub mod dor1 { # [doc = "Register `DOR1` reader"]
pub type R = crate :: R < DOR1_SPEC > ; # [doc = "Field `DACC1DOR` reader - DAC channel1 data output"]
pub type DACC1DOR_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:11 - DAC channel1 data output"]
# [inline (always)]
pub fn dacc1dor (& self) -> DACC1DOR_R { DACC1DOR_R :: new ((self . bits & 0x0fff) as u16) } } # [doc = "DAC channel1 data output register (DAC_DOR1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dor1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOR1_SPEC ; impl crate :: RegisterSpec for DOR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dor1::R`](R) reader structure"]
impl crate :: Readable for DOR1_SPEC { } # [doc = "`reset()` method sets DOR1 to value 0"]
impl crate :: Resettable for DOR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "DOR2 (r) register accessor: DAC channel2 data output register (DAC_DOR2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dor2::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dor2`]
module"]
pub type DOR2 = crate :: Reg < dor2 :: DOR2_SPEC > ; # [doc = "DAC channel2 data output register (DAC_DOR2)"]
pub mod dor2 { # [doc = "Register `DOR2` reader"]
pub type R = crate :: R < DOR2_SPEC > ; # [doc = "Field `DACC2DOR` reader - DAC channel2 data output"]
pub type DACC2DOR_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:11 - DAC channel2 data output"]
# [inline (always)]
pub fn dacc2dor (& self) -> DACC2DOR_R { DACC2DOR_R :: new ((self . bits & 0x0fff) as u16) } } # [doc = "DAC channel2 data output register (DAC_DOR2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dor2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOR2_SPEC ; impl crate :: RegisterSpec for DOR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dor2::R`](R) reader structure"]
impl crate :: Readable for DOR2_SPEC { } # [doc = "`reset()` method sets DOR2 to value 0"]
impl crate :: Resettable for DOR2_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Debug support"]
pub struct DBG { _marker : PhantomData < * const () > } unsafe impl Send for DBG { } impl DBG { # [doc = r"Pointer to the register block"]
pub const PTR : * const dbg :: RegisterBlock = 0xe004_2000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const dbg :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for DBG { type Target = dbg :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for DBG { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("DBG") . finish () } } # [doc = "Debug support"]
pub mod dbg { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { idcode : IDCODE , cfgr : CFGR , } impl RegisterBlock { # [doc = "0x00 - DBGMCU_IDCODE"]
# [inline (always)]
pub const fn idcode (& self) -> & IDCODE { & self . idcode } # [doc = "0x04 - DBGMCU_CFGR"]
# [inline (always)]
pub const fn cfgr (& self) -> & CFGR { & self . cfgr } } # [doc = "IDCODE (r) register accessor: DBGMCU_IDCODE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idcode::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idcode`]
module"]
pub type IDCODE = crate :: Reg < idcode :: IDCODE_SPEC > ; # [doc = "DBGMCU_IDCODE"]
pub mod idcode { # [doc = "Register `IDCODE` reader"]
pub type R = crate :: R < IDCODE_SPEC > ; # [doc = "Field `DEV_ID` reader - DEV_ID"]
pub type DEV_ID_R = crate :: FieldReader < u16 > ; # [doc = "Field `REV_ID` reader - REV_ID"]
pub type REV_ID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:11 - DEV_ID"]
# [inline (always)]
pub fn dev_id (& self) -> DEV_ID_R { DEV_ID_R :: new ((self . bits & 0x0fff) as u16) } # [doc = "Bits 16:31 - REV_ID"]
# [inline (always)]
pub fn rev_id (& self) -> REV_ID_R { REV_ID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "DBGMCU_IDCODE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idcode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IDCODE_SPEC ; impl crate :: RegisterSpec for IDCODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`idcode::R`](R) reader structure"]
impl crate :: Readable for IDCODE_SPEC { } # [doc = "`reset()` method sets IDCODE to value 0"]
impl crate :: Resettable for IDCODE_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFGR (rw) register accessor: DBGMCU_CFGR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr`]
module"]
pub type CFGR = crate :: Reg < cfgr :: CFGR_SPEC > ; # [doc = "DBGMCU_CFGR"]
pub mod cfgr { # [doc = "Register `CFGR` reader"]
pub type R = crate :: R < CFGR_SPEC > ; # [doc = "Register `CFGR` writer"]
pub type W = crate :: W < CFGR_SPEC > ; # [doc = "Field `DBG_SLEEP` reader - DBG_SLEEP"]
pub type DBG_SLEEP_R = crate :: BitReader ; # [doc = "Field `DBG_SLEEP` writer - DBG_SLEEP"]
pub type DBG_SLEEP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STOP` reader - DBG_STOP"]
pub type DBG_STOP_R = crate :: BitReader ; # [doc = "Field `DBG_STOP` writer - DBG_STOP"]
pub type DBG_STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_STANDBY` reader - DBG_STANDBY"]
pub type DBG_STANDBY_R = crate :: BitReader ; # [doc = "Field `DBG_STANDBY` writer - DBG_STANDBY"]
pub type DBG_STANDBY_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_IOEN` reader - TRACE_IOEN"]
pub type TRACE_IOEN_R = crate :: BitReader ; # [doc = "Field `TRACE_IOEN` writer - TRACE_IOEN"]
pub type TRACE_IOEN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `TRACE_MODE` reader - TRACE_MODE"]
pub type TRACE_MODE_R = crate :: FieldReader ; # [doc = "Field `TRACE_MODE` writer - TRACE_MODE"]
pub type TRACE_MODE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DBG_IWDG_STOP` reader - DBG_IWDG_STOP"]
pub type DBG_IWDG_STOP_R = crate :: BitReader ; # [doc = "Field `DBG_IWDG_STOP` writer - DBG_IWDG_STOP"]
pub type DBG_IWDG_STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP"]
pub type DBG_WWDG_STOP_R = crate :: BitReader ; # [doc = "Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP"]
pub type DBG_WWDG_STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM1_STOP` reader - DBG_TIM1_STOP"]
pub type DBG_TIM1_STOP_R = crate :: BitReader ; # [doc = "Field `DBG_TIM1_STOP` writer - DBG_TIM1_STOP"]
pub type DBG_TIM1_STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP"]
pub type DBG_TIM2_STOP_R = crate :: BitReader ; # [doc = "Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP"]
pub type DBG_TIM2_STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM3_STOP` reader - DBG_TIM3_STOP"]
pub type DBG_TIM3_STOP_R = crate :: BitReader ; # [doc = "Field `DBG_TIM3_STOP` writer - DBG_TIM3_STOP"]
pub type DBG_TIM3_STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP"]
pub type DBG_TIM4_STOP_R = crate :: BitReader ; # [doc = "Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP"]
pub type DBG_TIM4_STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP"]
pub type DBG_CAN1_STOP_R = crate :: BitReader ; # [doc = "Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP"]
pub type DBG_CAN1_STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_I2C1_SMBUS_TIMEOUT` reader - DBG_I2C1_SMBUS_TIMEOUT"]
pub type DBG_I2C1_SMBUS_TIMEOUT_R = crate :: BitReader ; # [doc = "Field `DBG_I2C1_SMBUS_TIMEOUT` writer - DBG_I2C1_SMBUS_TIMEOUT"]
pub type DBG_I2C1_SMBUS_TIMEOUT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` reader - DBG_I2C2_SMBUS_TIMEOUT"]
pub type DBG_I2C2_SMBUS_TIMEOUT_R = crate :: BitReader ; # [doc = "Field `DBG_I2C2_SMBUS_TIMEOUT` writer - DBG_I2C2_SMBUS_TIMEOUT"]
pub type DBG_I2C2_SMBUS_TIMEOUT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM8_STOP` reader - DBG_TIM8_STOP"]
pub type DBG_TIM8_STOP_R = crate :: BitReader ; # [doc = "Field `DBG_TIM8_STOP` writer - DBG_TIM8_STOP"]
pub type DBG_TIM8_STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP"]
pub type DBG_TIM5_STOP_R = crate :: BitReader ; # [doc = "Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP"]
pub type DBG_TIM5_STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP"]
pub type DBG_TIM6_STOP_R = crate :: BitReader ; # [doc = "Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP"]
pub type DBG_TIM6_STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP"]
pub type DBG_TIM7_STOP_R = crate :: BitReader ; # [doc = "Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP"]
pub type DBG_TIM7_STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP"]
pub type DBG_CAN2_STOP_R = crate :: BitReader ; # [doc = "Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP"]
pub type DBG_CAN2_STOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DBG_SLEEP"]
# [inline (always)]
pub fn dbg_sleep (& self) -> DBG_SLEEP_R { DBG_SLEEP_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DBG_STOP"]
# [inline (always)]
pub fn dbg_stop (& self) -> DBG_STOP_R { DBG_STOP_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DBG_STANDBY"]
# [inline (always)]
pub fn dbg_standby (& self) -> DBG_STANDBY_R { DBG_STANDBY_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 5 - TRACE_IOEN"]
# [inline (always)]
pub fn trace_ioen (& self) -> TRACE_IOEN_R { TRACE_IOEN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 6:7 - TRACE_MODE"]
# [inline (always)]
pub fn trace_mode (& self) -> TRACE_MODE_R { TRACE_MODE_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bit 8 - DBG_IWDG_STOP"]
# [inline (always)]
pub fn dbg_iwdg_stop (& self) -> DBG_IWDG_STOP_R { DBG_IWDG_STOP_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DBG_WWDG_STOP"]
# [inline (always)]
pub fn dbg_wwdg_stop (& self) -> DBG_WWDG_STOP_R { DBG_WWDG_STOP_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DBG_TIM1_STOP"]
# [inline (always)]
pub fn dbg_tim1_stop (& self) -> DBG_TIM1_STOP_R { DBG_TIM1_STOP_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DBG_TIM2_STOP"]
# [inline (always)]
pub fn dbg_tim2_stop (& self) -> DBG_TIM2_STOP_R { DBG_TIM2_STOP_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DBG_TIM3_STOP"]
# [inline (always)]
pub fn dbg_tim3_stop (& self) -> DBG_TIM3_STOP_R { DBG_TIM3_STOP_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DBG_TIM4_STOP"]
# [inline (always)]
pub fn dbg_tim4_stop (& self) -> DBG_TIM4_STOP_R { DBG_TIM4_STOP_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DBG_CAN1_STOP"]
# [inline (always)]
pub fn dbg_can1_stop (& self) -> DBG_CAN1_STOP_R { DBG_CAN1_STOP_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DBG_I2C1_SMBUS_TIMEOUT"]
# [inline (always)]
pub fn dbg_i2c1_smbus_timeout (& self) -> DBG_I2C1_SMBUS_TIMEOUT_R { DBG_I2C1_SMBUS_TIMEOUT_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"]
# [inline (always)]
pub fn dbg_i2c2_smbus_timeout (& self) -> DBG_I2C2_SMBUS_TIMEOUT_R { DBG_I2C2_SMBUS_TIMEOUT_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DBG_TIM8_STOP"]
# [inline (always)]
pub fn dbg_tim8_stop (& self) -> DBG_TIM8_STOP_R { DBG_TIM8_STOP_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DBG_TIM5_STOP"]
# [inline (always)]
pub fn dbg_tim5_stop (& self) -> DBG_TIM5_STOP_R { DBG_TIM5_STOP_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DBG_TIM6_STOP"]
# [inline (always)]
pub fn dbg_tim6_stop (& self) -> DBG_TIM6_STOP_R { DBG_TIM6_STOP_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DBG_TIM7_STOP"]
# [inline (always)]
pub fn dbg_tim7_stop (& self) -> DBG_TIM7_STOP_R { DBG_TIM7_STOP_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DBG_CAN2_STOP"]
# [inline (always)]
pub fn dbg_can2_stop (& self) -> DBG_CAN2_STOP_R { DBG_CAN2_STOP_R :: new (((self . bits >> 21) & 1) != 0) } } impl W { # [doc = "Bit 0 - DBG_SLEEP"]
# [inline (always)]
# [must_use]
pub fn dbg_sleep (& mut self) -> DBG_SLEEP_W < CFGR_SPEC > { DBG_SLEEP_W :: new (self , 0) } # [doc = "Bit 1 - DBG_STOP"]
# [inline (always)]
# [must_use]
pub fn dbg_stop (& mut self) -> DBG_STOP_W < CFGR_SPEC > { DBG_STOP_W :: new (self , 1) } # [doc = "Bit 2 - DBG_STANDBY"]
# [inline (always)]
# [must_use]
pub fn dbg_standby (& mut self) -> DBG_STANDBY_W < CFGR_SPEC > { DBG_STANDBY_W :: new (self , 2) } # [doc = "Bit 5 - TRACE_IOEN"]
# [inline (always)]
# [must_use]
pub fn trace_ioen (& mut self) -> TRACE_IOEN_W < CFGR_SPEC > { TRACE_IOEN_W :: new (self , 5) } # [doc = "Bits 6:7 - TRACE_MODE"]
# [inline (always)]
# [must_use]
pub fn trace_mode (& mut self) -> TRACE_MODE_W < CFGR_SPEC > { TRACE_MODE_W :: new (self , 6) } # [doc = "Bit 8 - DBG_IWDG_STOP"]
# [inline (always)]
# [must_use]
pub fn dbg_iwdg_stop (& mut self) -> DBG_IWDG_STOP_W < CFGR_SPEC > { DBG_IWDG_STOP_W :: new (self , 8) } # [doc = "Bit 9 - DBG_WWDG_STOP"]
# [inline (always)]
# [must_use]
pub fn dbg_wwdg_stop (& mut self) -> DBG_WWDG_STOP_W < CFGR_SPEC > { DBG_WWDG_STOP_W :: new (self , 9) } # [doc = "Bit 10 - DBG_TIM1_STOP"]
# [inline (always)]
# [must_use]
pub fn dbg_tim1_stop (& mut self) -> DBG_TIM1_STOP_W < CFGR_SPEC > { DBG_TIM1_STOP_W :: new (self , 10) } # [doc = "Bit 11 - DBG_TIM2_STOP"]
# [inline (always)]
# [must_use]
pub fn dbg_tim2_stop (& mut self) -> DBG_TIM2_STOP_W < CFGR_SPEC > { DBG_TIM2_STOP_W :: new (self , 11) } # [doc = "Bit 12 - DBG_TIM3_STOP"]
# [inline (always)]
# [must_use]
pub fn dbg_tim3_stop (& mut self) -> DBG_TIM3_STOP_W < CFGR_SPEC > { DBG_TIM3_STOP_W :: new (self , 12) } # [doc = "Bit 13 - DBG_TIM4_STOP"]
# [inline (always)]
# [must_use]
pub fn dbg_tim4_stop (& mut self) -> DBG_TIM4_STOP_W < CFGR_SPEC > { DBG_TIM4_STOP_W :: new (self , 13) } # [doc = "Bit 14 - DBG_CAN1_STOP"]
# [inline (always)]
# [must_use]
pub fn dbg_can1_stop (& mut self) -> DBG_CAN1_STOP_W < CFGR_SPEC > { DBG_CAN1_STOP_W :: new (self , 14) } # [doc = "Bit 15 - DBG_I2C1_SMBUS_TIMEOUT"]
# [inline (always)]
# [must_use]
pub fn dbg_i2c1_smbus_timeout (& mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W < CFGR_SPEC > { DBG_I2C1_SMBUS_TIMEOUT_W :: new (self , 15) } # [doc = "Bit 16 - DBG_I2C2_SMBUS_TIMEOUT"]
# [inline (always)]
# [must_use]
pub fn dbg_i2c2_smbus_timeout (& mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W < CFGR_SPEC > { DBG_I2C2_SMBUS_TIMEOUT_W :: new (self , 16) } # [doc = "Bit 17 - DBG_TIM8_STOP"]
# [inline (always)]
# [must_use]
pub fn dbg_tim8_stop (& mut self) -> DBG_TIM8_STOP_W < CFGR_SPEC > { DBG_TIM8_STOP_W :: new (self , 17) } # [doc = "Bit 18 - DBG_TIM5_STOP"]
# [inline (always)]
# [must_use]
pub fn dbg_tim5_stop (& mut self) -> DBG_TIM5_STOP_W < CFGR_SPEC > { DBG_TIM5_STOP_W :: new (self , 18) } # [doc = "Bit 19 - DBG_TIM6_STOP"]
# [inline (always)]
# [must_use]
pub fn dbg_tim6_stop (& mut self) -> DBG_TIM6_STOP_W < CFGR_SPEC > { DBG_TIM6_STOP_W :: new (self , 19) } # [doc = "Bit 20 - DBG_TIM7_STOP"]
# [inline (always)]
# [must_use]
pub fn dbg_tim7_stop (& mut self) -> DBG_TIM7_STOP_W < CFGR_SPEC > { DBG_TIM7_STOP_W :: new (self , 20) } # [doc = "Bit 21 - DBG_CAN2_STOP"]
# [inline (always)]
# [must_use]
pub fn dbg_can2_stop (& mut self) -> DBG_CAN2_STOP_W < CFGR_SPEC > { DBG_CAN2_STOP_W :: new (self , 21) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DBGMCU_CFGR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGR_SPEC ; impl crate :: RegisterSpec for CFGR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr::R`](R) reader structure"]
impl crate :: Readable for CFGR_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"]
impl crate :: Writable for CFGR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFGR to value 0"]
impl crate :: Resettable for CFGR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "USB register"]
pub struct USBHD { _marker : PhantomData < * const () > } unsafe impl Send for USBHD { } impl USBHD { # [doc = r"Pointer to the register block"]
pub const PTR : * const usbhd :: RegisterBlock = 0x4002_3400 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const usbhd :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for USBHD { type Target = usbhd :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for USBHD { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("USBHD") . finish () } } # [doc = "USB register"]
pub mod usbhd { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { r8_usb_ctrl : R8_USB_CTRL , r8_udev_ctrl__r8_uhost_ctrl : R8_UDEV_CTRL__R8_UHOST_CTRL , r8_usb_int_en : R8_USB_INT_EN , r8_usb_dev_ad : R8_USB_DEV_AD , _reserved4 : [u8 ; 0x01]
, r8_usb_mis_st : R8_USB_MIS_ST , r8_usb_int_fg : R8_USB_INT_FG , r8_usb_int_st : R8_USB_INT_ST , r8_usb_rx_len : R8_USB_RX_LEN , _reserved8 : [u8 ; 0x03]
, r8_uep4_1_mod : R8_UEP4_1_MOD , r8_uep2_3_mod__r8_uh_ep_mod : R8_UEP2_3_MOD__R8_UH_EP_MOD , _reserved10 : [u8 ; 0x02]
, r16_uep0_dma : R16_UEP0_DMA , _reserved11 : [u8 ; 0x02]
, r16_uep1_dma : R16_UEP1_DMA , _reserved12 : [u8 ; 0x02]
, r16_uep2_dma__r16_uh_rx_dma : R16_UEP2_DMA__R16_UH_RX_DMA , _reserved13 : [u8 ; 0x02]
, r16_uep3_dma__r16_uh_tx_dma : R16_UEP3_DMA__R16_UH_TX_DMA , _reserved14 : [u8 ; 0x02]
, r8_uep0_t_len : R8_UEP0_T_LEN , _reserved15 : [u8 ; 0x01]
, r8_uep0_ctrl : R8_UEP0_CTRL , _reserved16 : [u8 ; 0x01]
, r8_uep1_t_len : R8_UEP1_T_LEN , _reserved17 : [u8 ; 0x01]
, r8_uep1_ctrl__r8_uh_setup : R8_UEP1_CTRL__R8_UH_SETUP , _reserved18 : [u8 ; 0x01]
, r8_uep2_t_len__r8_uh_ep_pid : R8_UEP2_T_LEN__R8_UH_EP_PID , _reserved19 : [u8 ; 0x01]
, r8_uep2_ctrl__r8_uh_rx_ctrl : R8_UEP2_CTRL__R8_UH_RX_CTRL , _reserved20 : [u8 ; 0x01]
, r8_uep3_t_len__r8_uh_tx_len : R8_UEP3_T_LEN__R8_UH_TX_LEN , _reserved21 : [u8 ; 0x01]
, r8_uep3_ctrl__r8_uh_tx_ctrl : R8_UEP3_CTRL__R8_UH_TX_CTRL , _reserved22 : [u8 ; 0x01]
, r8_uep4_t_len : R8_UEP4_T_LEN , _reserved23 : [u8 ; 0x01]
, r8_uep4_ctrl : R8_UEP4_CTRL , _reserved24 : [u8 ; 0x05]
, r8_usb_type_c_ctrl : R8_USB_TYPE_C_CTRL , } impl RegisterBlock { # [doc = "0x00 - USB base control"]
# [inline (always)]
pub const fn r8_usb_ctrl (& self) -> & R8_USB_CTRL { & self . r8_usb_ctrl } # [doc = "0x01 - USB device physical prot control"]
# [inline (always)]
pub const fn r8_udev_ctrl__r8_uhost_ctrl (& self) -> & R8_UDEV_CTRL__R8_UHOST_CTRL { & self . r8_udev_ctrl__r8_uhost_ctrl } # [doc = "0x02 - USB interrupt enable"]
# [inline (always)]
pub const fn r8_usb_int_en (& self) -> & R8_USB_INT_EN { & self . r8_usb_int_en } # [doc = "0x03 - USB device address"]
# [inline (always)]
pub const fn r8_usb_dev_ad (& self) -> & R8_USB_DEV_AD { & self . r8_usb_dev_ad } # [doc = "0x05 - USB miscellaneous status"]
# [inline (always)]
pub const fn r8_usb_mis_st (& self) -> & R8_USB_MIS_ST { & self . r8_usb_mis_st } # [doc = "0x06 - USB interrupt flag"]
# [inline (always)]
pub const fn r8_usb_int_fg (& self) -> & R8_USB_INT_FG { & self . r8_usb_int_fg } # [doc = "0x07 - USB interrupt status"]
# [inline (always)]
pub const fn r8_usb_int_st (& self) -> & R8_USB_INT_ST { & self . r8_usb_int_st } # [doc = "0x08 - USB receiving length"]
# [inline (always)]
pub const fn r8_usb_rx_len (& self) -> & R8_USB_RX_LEN { & self . r8_usb_rx_len } # [doc = "0x0c - endpoint 4/1 mode"]
# [inline (always)]
pub const fn r8_uep4_1_mod (& self) -> & R8_UEP4_1_MOD { & self . r8_uep4_1_mod } # [doc = "0x0d - endpoint 2/3 mode;host endpoint mode"]
# [inline (always)]
pub const fn r8_uep2_3_mod__r8_uh_ep_mod (& self) -> & R8_UEP2_3_MOD__R8_UH_EP_MOD { & self . r8_uep2_3_mod__r8_uh_ep_mod } # [doc = "0x10 - endpoint 0 DMA buffer address"]
# [inline (always)]
pub const fn r16_uep0_dma (& self) -> & R16_UEP0_DMA { & self . r16_uep0_dma } # [doc = "0x14 - endpoint 1 DMA buffer address"]
# [inline (always)]
pub const fn r16_uep1_dma (& self) -> & R16_UEP1_DMA { & self . r16_uep1_dma } # [doc = "0x18 - endpoint 2 DMA buffer address;host rx endpoint buffer high address"]
# [inline (always)]
pub const fn r16_uep2_dma__r16_uh_rx_dma (& self) -> & R16_UEP2_DMA__R16_UH_RX_DMA { & self . r16_uep2_dma__r16_uh_rx_dma } # [doc = "0x1c - endpoint 3 DMA buffer address;host tx endpoint buffer high address"]
# [inline (always)]
pub const fn r16_uep3_dma__r16_uh_tx_dma (& self) -> & R16_UEP3_DMA__R16_UH_TX_DMA { & self . r16_uep3_dma__r16_uh_tx_dma } # [doc = "0x20 - endpoint 0 transmittal length"]
# [inline (always)]
pub const fn r8_uep0_t_len (& self) -> & R8_UEP0_T_LEN { & self . r8_uep0_t_len } # [doc = "0x22 - endpoint 0 control"]
# [inline (always)]
pub const fn r8_uep0_ctrl (& self) -> & R8_UEP0_CTRL { & self . r8_uep0_ctrl } # [doc = "0x24 - endpoint 1 transmittal length"]
# [inline (always)]
pub const fn r8_uep1_t_len (& self) -> & R8_UEP1_T_LEN { & self . r8_uep1_t_len } # [doc = "0x26 - endpoint 1 control;host aux setup"]
# [inline (always)]
pub const fn r8_uep1_ctrl__r8_uh_setup (& self) -> & R8_UEP1_CTRL__R8_UH_SETUP { & self . r8_uep1_ctrl__r8_uh_setup } # [doc = "0x28 - endpoint 2 transmittal length;host endpoint and PID"]
# [inline (always)]
pub const fn r8_uep2_t_len__r8_uh_ep_pid (& self) -> & R8_UEP2_T_LEN__R8_UH_EP_PID { & self . r8_uep2_t_len__r8_uh_ep_pid } # [doc = "0x2a - endpoint 2 control;host receiver endpoint control"]
# [inline (always)]
pub const fn r8_uep2_ctrl__r8_uh_rx_ctrl (& self) -> & R8_UEP2_CTRL__R8_UH_RX_CTRL { & self . r8_uep2_ctrl__r8_uh_rx_ctrl } # [doc = "0x2c - endpoint 3 transmittal length;host transmittal endpoint transmittal length"]
# [inline (always)]
pub const fn r8_uep3_t_len__r8_uh_tx_len (& self) -> & R8_UEP3_T_LEN__R8_UH_TX_LEN { & self . r8_uep3_t_len__r8_uh_tx_len } # [doc = "0x2e - endpoint 3 control;host transmittal endpoint control"]
# [inline (always)]
pub const fn r8_uep3_ctrl__r8_uh_tx_ctrl (& self) -> & R8_UEP3_CTRL__R8_UH_TX_CTRL { & self . r8_uep3_ctrl__r8_uh_tx_ctrl } # [doc = "0x30 - endpoint 4 transmittal length"]
# [inline (always)]
pub const fn r8_uep4_t_len (& self) -> & R8_UEP4_T_LEN { & self . r8_uep4_t_len } # [doc = "0x32 - endpoint 4 control"]
# [inline (always)]
pub const fn r8_uep4_ctrl (& self) -> & R8_UEP4_CTRL { & self . r8_uep4_ctrl } # [doc = "0x38 - USB type-C control"]
# [inline (always)]
pub const fn r8_usb_type_c_ctrl (& self) -> & R8_USB_TYPE_C_CTRL { & self . r8_usb_type_c_ctrl } } # [doc = "R8_USB_CTRL (rw) register accessor: USB base control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_usb_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_ctrl`]
module"]
pub type R8_USB_CTRL = crate :: Reg < r8_usb_ctrl :: R8_USB_CTRL_SPEC > ; # [doc = "USB base control"]
pub mod r8_usb_ctrl { # [doc = "Register `R8_USB_CTRL` reader"]
pub type R = crate :: R < R8_USB_CTRL_SPEC > ; # [doc = "Register `R8_USB_CTRL` writer"]
pub type W = crate :: W < R8_USB_CTRL_SPEC > ; # [doc = "Field `RB_UC_DMA_EN` reader - DMA enable and DMA interrupt enable for USB"]
pub type RB_UC_DMA_EN_R = crate :: BitReader ; # [doc = "Field `RB_UC_DMA_EN` writer - DMA enable and DMA interrupt enable for USB"]
pub type RB_UC_DMA_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UC_CLR_ALL` reader - force clear FIFO and count of USB"]
pub type RB_UC_CLR_ALL_R = crate :: BitReader ; # [doc = "Field `RB_UC_CLR_ALL` writer - force clear FIFO and count of USB"]
pub type RB_UC_CLR_ALL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UC_RESET_SIE` reader - force reset USB SIE, need software clear"]
pub type RB_UC_RESET_SIE_R = crate :: BitReader ; # [doc = "Field `RB_UC_RESET_SIE` writer - force reset USB SIE, need software clear"]
pub type RB_UC_RESET_SIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UC_INT_BUSY` reader - enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid"]
pub type RB_UC_INT_BUSY_R = crate :: BitReader ; # [doc = "Field `RB_UC_INT_BUSY` writer - enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid"]
pub type RB_UC_INT_BUSY_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MASK_UC_SYS_CTRL` reader - bit mask of USB system control"]
pub type MASK_UC_SYS_CTRL_R = crate :: FieldReader ; # [doc = "Field `MASK_UC_SYS_CTRL` writer - bit mask of USB system control"]
pub type MASK_UC_SYS_CTRL_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RB_UC_LOW_SPEED` reader - enable USB low speed: 0=12Mbps, 1=1.5Mbps"]
pub type RB_UC_LOW_SPEED_R = crate :: BitReader ; # [doc = "Field `RB_UC_LOW_SPEED` writer - enable USB low speed: 0=12Mbps, 1=1.5Mbps"]
pub type RB_UC_LOW_SPEED_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UC_HOST_MODE` reader - enable USB host mode: 0=device mode, 1=host mode"]
pub type RB_UC_HOST_MODE_R = crate :: BitReader ; # [doc = "Field `RB_UC_HOST_MODE` writer - enable USB host mode: 0=device mode, 1=host mode"]
pub type RB_UC_HOST_MODE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - DMA enable and DMA interrupt enable for USB"]
# [inline (always)]
pub fn rb_uc_dma_en (& self) -> RB_UC_DMA_EN_R { RB_UC_DMA_EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - force clear FIFO and count of USB"]
# [inline (always)]
pub fn rb_uc_clr_all (& self) -> RB_UC_CLR_ALL_R { RB_UC_CLR_ALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - force reset USB SIE, need software clear"]
# [inline (always)]
pub fn rb_uc_reset_sie (& self) -> RB_UC_RESET_SIE_R { RB_UC_RESET_SIE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid"]
# [inline (always)]
pub fn rb_uc_int_busy (& self) -> RB_UC_INT_BUSY_R { RB_UC_INT_BUSY_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - bit mask of USB system control"]
# [inline (always)]
pub fn mask_uc_sys_ctrl (& self) -> MASK_UC_SYS_CTRL_R { MASK_UC_SYS_CTRL_R :: new ((self . bits >> 4) & 3) } # [doc = "Bit 6 - enable USB low speed: 0=12Mbps, 1=1.5Mbps"]
# [inline (always)]
pub fn rb_uc_low_speed (& self) -> RB_UC_LOW_SPEED_R { RB_UC_LOW_SPEED_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - enable USB host mode: 0=device mode, 1=host mode"]
# [inline (always)]
pub fn rb_uc_host_mode (& self) -> RB_UC_HOST_MODE_R { RB_UC_HOST_MODE_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bit 0 - DMA enable and DMA interrupt enable for USB"]
# [inline (always)]
# [must_use]
pub fn rb_uc_dma_en (& mut self) -> RB_UC_DMA_EN_W < R8_USB_CTRL_SPEC > { RB_UC_DMA_EN_W :: new (self , 0) } # [doc = "Bit 1 - force clear FIFO and count of USB"]
# [inline (always)]
# [must_use]
pub fn rb_uc_clr_all (& mut self) -> RB_UC_CLR_ALL_W < R8_USB_CTRL_SPEC > { RB_UC_CLR_ALL_W :: new (self , 1) } # [doc = "Bit 2 - force reset USB SIE, need software clear"]
# [inline (always)]
# [must_use]
pub fn rb_uc_reset_sie (& mut self) -> RB_UC_RESET_SIE_W < R8_USB_CTRL_SPEC > { RB_UC_RESET_SIE_W :: new (self , 2) } # [doc = "Bit 3 - enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid"]
# [inline (always)]
# [must_use]
pub fn rb_uc_int_busy (& mut self) -> RB_UC_INT_BUSY_W < R8_USB_CTRL_SPEC > { RB_UC_INT_BUSY_W :: new (self , 3) } # [doc = "Bits 4:5 - bit mask of USB system control"]
# [inline (always)]
# [must_use]
pub fn mask_uc_sys_ctrl (& mut self) -> MASK_UC_SYS_CTRL_W < R8_USB_CTRL_SPEC > { MASK_UC_SYS_CTRL_W :: new (self , 4) } # [doc = "Bit 6 - enable USB low speed: 0=12Mbps, 1=1.5Mbps"]
# [inline (always)]
# [must_use]
pub fn rb_uc_low_speed (& mut self) -> RB_UC_LOW_SPEED_W < R8_USB_CTRL_SPEC > { RB_UC_LOW_SPEED_W :: new (self , 6) } # [doc = "Bit 7 - enable USB host mode: 0=device mode, 1=host mode"]
# [inline (always)]
# [must_use]
pub fn rb_uc_host_mode (& mut self) -> RB_UC_HOST_MODE_W < R8_USB_CTRL_SPEC > { RB_UC_HOST_MODE_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "USB base control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_usb_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_USB_CTRL_SPEC ; impl crate :: RegisterSpec for R8_USB_CTRL_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_usb_ctrl::R`](R) reader structure"]
impl crate :: Readable for R8_USB_CTRL_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_usb_ctrl::W`](W) writer structure"]
impl crate :: Writable for R8_USB_CTRL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_USB_CTRL to value 0"]
impl crate :: Resettable for R8_USB_CTRL_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_UDEV_CTRL__R8_UHOST_CTRL (rw) register accessor: USB device physical prot control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_udev_ctrl__r8_uhost_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_udev_ctrl__r8_uhost_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_udev_ctrl__r8_uhost_ctrl`]
module"]
pub type R8_UDEV_CTRL__R8_UHOST_CTRL = crate :: Reg < r8_udev_ctrl__r8_uhost_ctrl :: R8_UDEV_CTRL__R8_UHOST_CTRL_SPEC > ; # [doc = "USB device physical prot control"]
pub mod r8_udev_ctrl__r8_uhost_ctrl { # [doc = "Register `R8_UDEV_CTRL__R8_UHOST_CTRL` reader"]
pub type R = crate :: R < R8_UDEV_CTRL__R8_UHOST_CTRL_SPEC > ; # [doc = "Register `R8_UDEV_CTRL__R8_UHOST_CTRL` writer"]
pub type W = crate :: W < R8_UDEV_CTRL__R8_UHOST_CTRL_SPEC > ; # [doc = "Field `RB_UD_PORT_EN__RB_UH_PORT_EN` reader - enable USB physical port I/O: 0=disable, 1=enable;enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached"]
pub type RB_UD_PORT_EN__RB_UH_PORT_EN_R = crate :: BitReader ; # [doc = "Field `RB_UD_PORT_EN__RB_UH_PORT_EN` writer - enable USB physical port I/O: 0=disable, 1=enable;enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached"]
pub type RB_UD_PORT_EN__RB_UH_PORT_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UD_GP_BIT__RB_UH_BUS_RESET` reader - general purpose bit;control USB bus reset: 0=normal, 1=force bus reset"]
pub type RB_UD_GP_BIT__RB_UH_BUS_RESET_R = crate :: BitReader ; # [doc = "Field `RB_UD_GP_BIT__RB_UH_BUS_RESET` writer - general purpose bit;control USB bus reset: 0=normal, 1=force bus reset"]
pub type RB_UD_GP_BIT__RB_UH_BUS_RESET_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UD_LOW_SPEED__RB_UH_LOW_SPEED` reader - enable USB physical port low speed: 0=full speed, 1=low speed;enable USB port low speed: 0=full speed, 1=low speed"]
pub type RB_UD_LOW_SPEED__RB_UH_LOW_SPEED_R = crate :: BitReader ; # [doc = "Field `RB_UD_LOW_SPEED__RB_UH_LOW_SPEED` writer - enable USB physical port low speed: 0=full speed, 1=low speed;enable USB port low speed: 0=full speed, 1=low speed"]
pub type RB_UD_LOW_SPEED__RB_UH_LOW_SPEED_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UD_DM_PIN__RB_UH_DM_PIN` reader - ReadOnly: indicate current UDM pin level"]
pub type RB_UD_DM_PIN__RB_UH_DM_PIN_R = crate :: BitReader ; # [doc = "Field `RB_UD_DP_PIN__RB_UH_DP_PIN` reader - ReadOnly: indicate current UDP pin level"]
pub type RB_UD_DP_PIN__RB_UH_DP_PIN_R = crate :: BitReader ; # [doc = "Field `RB_UD_PD_DIS__RB_UH_PD_DIS` reader - disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable"]
pub type RB_UD_PD_DIS__RB_UH_PD_DIS_R = crate :: BitReader ; impl R { # [doc = "Bit 0 - enable USB physical port I/O: 0=disable, 1=enable;enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached"]
# [inline (always)]
pub fn rb_ud_port_en__rb_uh_port_en (& self) -> RB_UD_PORT_EN__RB_UH_PORT_EN_R { RB_UD_PORT_EN__RB_UH_PORT_EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - general purpose bit;control USB bus reset: 0=normal, 1=force bus reset"]
# [inline (always)]
pub fn rb_ud_gp_bit__rb_uh_bus_reset (& self) -> RB_UD_GP_BIT__RB_UH_BUS_RESET_R { RB_UD_GP_BIT__RB_UH_BUS_RESET_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - enable USB physical port low speed: 0=full speed, 1=low speed;enable USB port low speed: 0=full speed, 1=low speed"]
# [inline (always)]
pub fn rb_ud_low_speed__rb_uh_low_speed (& self) -> RB_UD_LOW_SPEED__RB_UH_LOW_SPEED_R { RB_UD_LOW_SPEED__RB_UH_LOW_SPEED_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 4 - ReadOnly: indicate current UDM pin level"]
# [inline (always)]
pub fn rb_ud_dm_pin__rb_uh_dm_pin (& self) -> RB_UD_DM_PIN__RB_UH_DM_PIN_R { RB_UD_DM_PIN__RB_UH_DM_PIN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - ReadOnly: indicate current UDP pin level"]
# [inline (always)]
pub fn rb_ud_dp_pin__rb_uh_dp_pin (& self) -> RB_UD_DP_PIN__RB_UH_DP_PIN_R { RB_UD_DP_PIN__RB_UH_DP_PIN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 7 - disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable"]
# [inline (always)]
pub fn rb_ud_pd_dis__rb_uh_pd_dis (& self) -> RB_UD_PD_DIS__RB_UH_PD_DIS_R { RB_UD_PD_DIS__RB_UH_PD_DIS_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bit 0 - enable USB physical port I/O: 0=disable, 1=enable;enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached"]
# [inline (always)]
# [must_use]
pub fn rb_ud_port_en__rb_uh_port_en (& mut self) -> RB_UD_PORT_EN__RB_UH_PORT_EN_W < R8_UDEV_CTRL__R8_UHOST_CTRL_SPEC > { RB_UD_PORT_EN__RB_UH_PORT_EN_W :: new (self , 0) } # [doc = "Bit 1 - general purpose bit;control USB bus reset: 0=normal, 1=force bus reset"]
# [inline (always)]
# [must_use]
pub fn rb_ud_gp_bit__rb_uh_bus_reset (& mut self) -> RB_UD_GP_BIT__RB_UH_BUS_RESET_W < R8_UDEV_CTRL__R8_UHOST_CTRL_SPEC > { RB_UD_GP_BIT__RB_UH_BUS_RESET_W :: new (self , 1) } # [doc = "Bit 2 - enable USB physical port low speed: 0=full speed, 1=low speed;enable USB port low speed: 0=full speed, 1=low speed"]
# [inline (always)]
# [must_use]
pub fn rb_ud_low_speed__rb_uh_low_speed (& mut self) -> RB_UD_LOW_SPEED__RB_UH_LOW_SPEED_W < R8_UDEV_CTRL__R8_UHOST_CTRL_SPEC > { RB_UD_LOW_SPEED__RB_UH_LOW_SPEED_W :: new (self , 2) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "USB device physical prot control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_udev_ctrl__r8_uhost_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_udev_ctrl__r8_uhost_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_UDEV_CTRL__R8_UHOST_CTRL_SPEC ; impl crate :: RegisterSpec for R8_UDEV_CTRL__R8_UHOST_CTRL_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_udev_ctrl__r8_uhost_ctrl::R`](R) reader structure"]
impl crate :: Readable for R8_UDEV_CTRL__R8_UHOST_CTRL_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_udev_ctrl__r8_uhost_ctrl::W`](W) writer structure"]
impl crate :: Writable for R8_UDEV_CTRL__R8_UHOST_CTRL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_UDEV_CTRL__R8_UHOST_CTRL to value 0"]
impl crate :: Resettable for R8_UDEV_CTRL__R8_UHOST_CTRL_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_USB_INT_EN (rw) register accessor: USB interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_int_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_usb_int_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_int_en`]
module"]
pub type R8_USB_INT_EN = crate :: Reg < r8_usb_int_en :: R8_USB_INT_EN_SPEC > ; # [doc = "USB interrupt enable"]
pub mod r8_usb_int_en { # [doc = "Register `R8_USB_INT_EN` reader"]
pub type R = crate :: R < R8_USB_INT_EN_SPEC > ; # [doc = "Register `R8_USB_INT_EN` writer"]
pub type W = crate :: W < R8_USB_INT_EN_SPEC > ; # [doc = "Field `RB_UIE_BUS_RST__RB_UIE_DETECT` reader - enable interrupt for USB bus reset event for USB device mode;enable interrupt for USB device detected event for USB host mode"]
pub type RB_UIE_BUS_RST__RB_UIE_DETECT_R = crate :: BitReader ; # [doc = "Field `RB_UIE_BUS_RST__RB_UIE_DETECT` writer - enable interrupt for USB bus reset event for USB device mode;enable interrupt for USB device detected event for USB host mode"]
pub type RB_UIE_BUS_RST__RB_UIE_DETECT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UIE_TRANSFER` reader - enable interrupt for USB transfer completion"]
pub type RB_UIE_TRANSFER_R = crate :: BitReader ; # [doc = "Field `RB_UIE_TRANSFER` writer - enable interrupt for USB transfer completion"]
pub type RB_UIE_TRANSFER_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UIE_SUSPEND` reader - enable interrupt for USB suspend or resume event"]
pub type RB_UIE_SUSPEND_R = crate :: BitReader ; # [doc = "Field `RB_UIE_SUSPEND` writer - enable interrupt for USB suspend or resume event"]
pub type RB_UIE_SUSPEND_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UIE_HST_SOF` reader - enable interrupt for host SOF timer action for USB host mode"]
pub type RB_UIE_HST_SOF_R = crate :: BitReader ; # [doc = "Field `RB_UIE_HST_SOF` writer - enable interrupt for host SOF timer action for USB host mode"]
pub type RB_UIE_HST_SOF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UIE_FIFO_OV` reader - enable interrupt for FIFO overflow"]
pub type RB_UIE_FIFO_OV_R = crate :: BitReader ; # [doc = "Field `RB_UIE_FIFO_OV` writer - enable interrupt for FIFO overflow"]
pub type RB_UIE_FIFO_OV_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UIE_DEV_NAK` reader - enable interrupt for NAK responded for USB device mode"]
pub type RB_UIE_DEV_NAK_R = crate :: BitReader ; # [doc = "Field `RB_UIE_DEV_NAK` writer - enable interrupt for NAK responded for USB device mode"]
pub type RB_UIE_DEV_NAK_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UIE_DEV_SOF` reader - enable interrupt for SOF received for USB device mode"]
pub type RB_UIE_DEV_SOF_R = crate :: BitReader ; # [doc = "Field `RB_UIE_DEV_SOF` writer - enable interrupt for SOF received for USB device mode"]
pub type RB_UIE_DEV_SOF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - enable interrupt for USB bus reset event for USB device mode;enable interrupt for USB device detected event for USB host mode"]
# [inline (always)]
pub fn rb_uie_bus_rst__rb_uie_detect (& self) -> RB_UIE_BUS_RST__RB_UIE_DETECT_R { RB_UIE_BUS_RST__RB_UIE_DETECT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - enable interrupt for USB transfer completion"]
# [inline (always)]
pub fn rb_uie_transfer (& self) -> RB_UIE_TRANSFER_R { RB_UIE_TRANSFER_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - enable interrupt for USB suspend or resume event"]
# [inline (always)]
pub fn rb_uie_suspend (& self) -> RB_UIE_SUSPEND_R { RB_UIE_SUSPEND_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - enable interrupt for host SOF timer action for USB host mode"]
# [inline (always)]
pub fn rb_uie_hst_sof (& self) -> RB_UIE_HST_SOF_R { RB_UIE_HST_SOF_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - enable interrupt for FIFO overflow"]
# [inline (always)]
pub fn rb_uie_fifo_ov (& self) -> RB_UIE_FIFO_OV_R { RB_UIE_FIFO_OV_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 6 - enable interrupt for NAK responded for USB device mode"]
# [inline (always)]
pub fn rb_uie_dev_nak (& self) -> RB_UIE_DEV_NAK_R { RB_UIE_DEV_NAK_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - enable interrupt for SOF received for USB device mode"]
# [inline (always)]
pub fn rb_uie_dev_sof (& self) -> RB_UIE_DEV_SOF_R { RB_UIE_DEV_SOF_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bit 0 - enable interrupt for USB bus reset event for USB device mode;enable interrupt for USB device detected event for USB host mode"]
# [inline (always)]
# [must_use]
pub fn rb_uie_bus_rst__rb_uie_detect (& mut self) -> RB_UIE_BUS_RST__RB_UIE_DETECT_W < R8_USB_INT_EN_SPEC > { RB_UIE_BUS_RST__RB_UIE_DETECT_W :: new (self , 0) } # [doc = "Bit 1 - enable interrupt for USB transfer completion"]
# [inline (always)]
# [must_use]
pub fn rb_uie_transfer (& mut self) -> RB_UIE_TRANSFER_W < R8_USB_INT_EN_SPEC > { RB_UIE_TRANSFER_W :: new (self , 1) } # [doc = "Bit 2 - enable interrupt for USB suspend or resume event"]
# [inline (always)]
# [must_use]
pub fn rb_uie_suspend (& mut self) -> RB_UIE_SUSPEND_W < R8_USB_INT_EN_SPEC > { RB_UIE_SUSPEND_W :: new (self , 2) } # [doc = "Bit 3 - enable interrupt for host SOF timer action for USB host mode"]
# [inline (always)]
# [must_use]
pub fn rb_uie_hst_sof (& mut self) -> RB_UIE_HST_SOF_W < R8_USB_INT_EN_SPEC > { RB_UIE_HST_SOF_W :: new (self , 3) } # [doc = "Bit 4 - enable interrupt for FIFO overflow"]
# [inline (always)]
# [must_use]
pub fn rb_uie_fifo_ov (& mut self) -> RB_UIE_FIFO_OV_W < R8_USB_INT_EN_SPEC > { RB_UIE_FIFO_OV_W :: new (self , 4) } # [doc = "Bit 6 - enable interrupt for NAK responded for USB device mode"]
# [inline (always)]
# [must_use]
pub fn rb_uie_dev_nak (& mut self) -> RB_UIE_DEV_NAK_W < R8_USB_INT_EN_SPEC > { RB_UIE_DEV_NAK_W :: new (self , 6) } # [doc = "Bit 7 - enable interrupt for SOF received for USB device mode"]
# [inline (always)]
# [must_use]
pub fn rb_uie_dev_sof (& mut self) -> RB_UIE_DEV_SOF_W < R8_USB_INT_EN_SPEC > { RB_UIE_DEV_SOF_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "USB interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_int_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_usb_int_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_USB_INT_EN_SPEC ; impl crate :: RegisterSpec for R8_USB_INT_EN_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_usb_int_en::R`](R) reader structure"]
impl crate :: Readable for R8_USB_INT_EN_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_usb_int_en::W`](W) writer structure"]
impl crate :: Writable for R8_USB_INT_EN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_USB_INT_EN to value 0"]
impl crate :: Resettable for R8_USB_INT_EN_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_USB_DEV_AD (rw) register accessor: USB device address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_dev_ad::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_usb_dev_ad::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_dev_ad`]
module"]
pub type R8_USB_DEV_AD = crate :: Reg < r8_usb_dev_ad :: R8_USB_DEV_AD_SPEC > ; # [doc = "USB device address"]
pub mod r8_usb_dev_ad { # [doc = "Register `R8_USB_DEV_AD` reader"]
pub type R = crate :: R < R8_USB_DEV_AD_SPEC > ; # [doc = "Register `R8_USB_DEV_AD` writer"]
pub type W = crate :: W < R8_USB_DEV_AD_SPEC > ; # [doc = "Field `MASK_USB_ADDR` reader - bit mask for USB device address"]
pub type MASK_USB_ADDR_R = crate :: FieldReader ; # [doc = "Field `MASK_USB_ADDR` writer - bit mask for USB device address"]
pub type MASK_USB_ADDR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `RB_UDA_GP_BIT` reader - general purpose bit"]
pub type RB_UDA_GP_BIT_R = crate :: BitReader ; # [doc = "Field `RB_UDA_GP_BIT` writer - general purpose bit"]
pub type RB_UDA_GP_BIT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:6 - bit mask for USB device address"]
# [inline (always)]
pub fn mask_usb_addr (& self) -> MASK_USB_ADDR_R { MASK_USB_ADDR_R :: new (self . bits & 0x7f) } # [doc = "Bit 7 - general purpose bit"]
# [inline (always)]
pub fn rb_uda_gp_bit (& self) -> RB_UDA_GP_BIT_R { RB_UDA_GP_BIT_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:6 - bit mask for USB device address"]
# [inline (always)]
# [must_use]
pub fn mask_usb_addr (& mut self) -> MASK_USB_ADDR_W < R8_USB_DEV_AD_SPEC > { MASK_USB_ADDR_W :: new (self , 0) } # [doc = "Bit 7 - general purpose bit"]
# [inline (always)]
# [must_use]
pub fn rb_uda_gp_bit (& mut self) -> RB_UDA_GP_BIT_W < R8_USB_DEV_AD_SPEC > { RB_UDA_GP_BIT_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "USB device address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_dev_ad::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_usb_dev_ad::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_USB_DEV_AD_SPEC ; impl crate :: RegisterSpec for R8_USB_DEV_AD_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_usb_dev_ad::R`](R) reader structure"]
impl crate :: Readable for R8_USB_DEV_AD_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_usb_dev_ad::W`](W) writer structure"]
impl crate :: Writable for R8_USB_DEV_AD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_USB_DEV_AD to value 0"]
impl crate :: Resettable for R8_USB_DEV_AD_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_USB_MIS_ST (r) register accessor: USB miscellaneous status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_mis_st::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_mis_st`]
module"]
pub type R8_USB_MIS_ST = crate :: Reg < r8_usb_mis_st :: R8_USB_MIS_ST_SPEC > ; # [doc = "USB miscellaneous status"]
pub mod r8_usb_mis_st { # [doc = "Register `R8_USB_MIS_ST` reader"]
pub type R = crate :: R < R8_USB_MIS_ST_SPEC > ; # [doc = "Field `RB_UMS_DEV_ATTACH` reader - RO, indicate device attached status on USB host"]
pub type RB_UMS_DEV_ATTACH_R = crate :: BitReader ; # [doc = "Field `RB_UMS_DM_LEVEL` reader - RO, indicate UDM level saved at device attached to USB host"]
pub type RB_UMS_DM_LEVEL_R = crate :: BitReader ; # [doc = "Field `RB_UMS_SUSPEND` reader - RO, indicate USB suspend status"]
pub type RB_UMS_SUSPEND_R = crate :: BitReader ; # [doc = "Field `RB_UMS_BUS_RESET` reader - RO, indicate USB bus reset status"]
pub type RB_UMS_BUS_RESET_R = crate :: BitReader ; # [doc = "Field `RB_UMS_R_FIFO_RDY` reader - RO, indicate USB receiving FIFO ready status (not empty)"]
pub type RB_UMS_R_FIFO_RDY_R = crate :: BitReader ; # [doc = "Field `RB_UMS_SIE_FREE` reader - RO, indicate USB SIE free status"]
pub type RB_UMS_SIE_FREE_R = crate :: BitReader ; # [doc = "Field `RB_UMS_SOF_ACT` reader - RO, indicate host SOF timer action status for USB host"]
pub type RB_UMS_SOF_ACT_R = crate :: BitReader ; # [doc = "Field `RB_UMS_SOF_PRES` reader - RO, indicate host SOF timer presage status"]
pub type RB_UMS_SOF_PRES_R = crate :: BitReader ; impl R { # [doc = "Bit 0 - RO, indicate device attached status on USB host"]
# [inline (always)]
pub fn rb_ums_dev_attach (& self) -> RB_UMS_DEV_ATTACH_R { RB_UMS_DEV_ATTACH_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - RO, indicate UDM level saved at device attached to USB host"]
# [inline (always)]
pub fn rb_ums_dm_level (& self) -> RB_UMS_DM_LEVEL_R { RB_UMS_DM_LEVEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - RO, indicate USB suspend status"]
# [inline (always)]
pub fn rb_ums_suspend (& self) -> RB_UMS_SUSPEND_R { RB_UMS_SUSPEND_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - RO, indicate USB bus reset status"]
# [inline (always)]
pub fn rb_ums_bus_reset (& self) -> RB_UMS_BUS_RESET_R { RB_UMS_BUS_RESET_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - RO, indicate USB receiving FIFO ready status (not empty)"]
# [inline (always)]
pub fn rb_ums_r_fifo_rdy (& self) -> RB_UMS_R_FIFO_RDY_R { RB_UMS_R_FIFO_RDY_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - RO, indicate USB SIE free status"]
# [inline (always)]
pub fn rb_ums_sie_free (& self) -> RB_UMS_SIE_FREE_R { RB_UMS_SIE_FREE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - RO, indicate host SOF timer action status for USB host"]
# [inline (always)]
pub fn rb_ums_sof_act (& self) -> RB_UMS_SOF_ACT_R { RB_UMS_SOF_ACT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - RO, indicate host SOF timer presage status"]
# [inline (always)]
pub fn rb_ums_sof_pres (& self) -> RB_UMS_SOF_PRES_R { RB_UMS_SOF_PRES_R :: new (((self . bits >> 7) & 1) != 0) } } # [doc = "USB miscellaneous status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_mis_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_USB_MIS_ST_SPEC ; impl crate :: RegisterSpec for R8_USB_MIS_ST_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_usb_mis_st::R`](R) reader structure"]
impl crate :: Readable for R8_USB_MIS_ST_SPEC { } # [doc = "`reset()` method sets R8_USB_MIS_ST to value 0"]
impl crate :: Resettable for R8_USB_MIS_ST_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_USB_INT_FG (rw) register accessor: USB interrupt flag\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_int_fg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_usb_int_fg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_int_fg`]
module"]
pub type R8_USB_INT_FG = crate :: Reg < r8_usb_int_fg :: R8_USB_INT_FG_SPEC > ; # [doc = "USB interrupt flag"]
pub mod r8_usb_int_fg { # [doc = "Register `R8_USB_INT_FG` reader"]
pub type R = crate :: R < R8_USB_INT_FG_SPEC > ; # [doc = "Register `R8_USB_INT_FG` writer"]
pub type W = crate :: W < R8_USB_INT_FG_SPEC > ; # [doc = "Field `RB_UIF_BUS_RST__RB_UIF_DETECT` reader - bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear"]
pub type RB_UIF_BUS_RST__RB_UIF_DETECT_R = crate :: BitReader ; # [doc = "Field `RB_UIF_BUS_RST__RB_UIF_DETECT` writer - bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear"]
pub type RB_UIF_BUS_RST__RB_UIF_DETECT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UIF_TRANSFER` reader - USB transfer completion interrupt flag, direct bit address clear or write 1 to clear"]
pub type RB_UIF_TRANSFER_R = crate :: BitReader ; # [doc = "Field `RB_UIF_TRANSFER` writer - USB transfer completion interrupt flag, direct bit address clear or write 1 to clear"]
pub type RB_UIF_TRANSFER_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UIF_SUSPEND` reader - USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear"]
pub type RB_UIF_SUSPEND_R = crate :: BitReader ; # [doc = "Field `RB_UIF_SUSPEND` writer - USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear"]
pub type RB_UIF_SUSPEND_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UIF_HST_SOF` reader - host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear"]
pub type RB_UIF_HST_SOF_R = crate :: BitReader ; # [doc = "Field `RB_UIF_HST_SOF` writer - host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear"]
pub type RB_UIF_HST_SOF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UIF_FIFO_OV` reader - FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear"]
pub type RB_UIF_FIFO_OV_R = crate :: BitReader ; # [doc = "Field `RB_UIF_FIFO_OV` writer - FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear"]
pub type RB_UIF_FIFO_OV_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_U_SIE_FREE` reader - RO, indicate USB SIE free status"]
pub type RB_U_SIE_FREE_R = crate :: BitReader ; # [doc = "Field `RB_U_TOG_OK` reader - RO, indicate current USB transfer toggle is OK"]
pub type RB_U_TOG_OK_R = crate :: BitReader ; # [doc = "Field `RB_U_IS_NAK` reader - RO, indicate current USB transfer is NAK received"]
pub type RB_U_IS_NAK_R = crate :: BitReader ; impl R { # [doc = "Bit 0 - bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear"]
# [inline (always)]
pub fn rb_uif_bus_rst__rb_uif_detect (& self) -> RB_UIF_BUS_RST__RB_UIF_DETECT_R { RB_UIF_BUS_RST__RB_UIF_DETECT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - USB transfer completion interrupt flag, direct bit address clear or write 1 to clear"]
# [inline (always)]
pub fn rb_uif_transfer (& self) -> RB_UIF_TRANSFER_R { RB_UIF_TRANSFER_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear"]
# [inline (always)]
pub fn rb_uif_suspend (& self) -> RB_UIF_SUSPEND_R { RB_UIF_SUSPEND_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear"]
# [inline (always)]
pub fn rb_uif_hst_sof (& self) -> RB_UIF_HST_SOF_R { RB_UIF_HST_SOF_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear"]
# [inline (always)]
pub fn rb_uif_fifo_ov (& self) -> RB_UIF_FIFO_OV_R { RB_UIF_FIFO_OV_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - RO, indicate USB SIE free status"]
# [inline (always)]
pub fn rb_u_sie_free (& self) -> RB_U_SIE_FREE_R { RB_U_SIE_FREE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - RO, indicate current USB transfer toggle is OK"]
# [inline (always)]
pub fn rb_u_tog_ok (& self) -> RB_U_TOG_OK_R { RB_U_TOG_OK_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - RO, indicate current USB transfer is NAK received"]
# [inline (always)]
pub fn rb_u_is_nak (& self) -> RB_U_IS_NAK_R { RB_U_IS_NAK_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bit 0 - bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear"]
# [inline (always)]
# [must_use]
pub fn rb_uif_bus_rst__rb_uif_detect (& mut self) -> RB_UIF_BUS_RST__RB_UIF_DETECT_W < R8_USB_INT_FG_SPEC > { RB_UIF_BUS_RST__RB_UIF_DETECT_W :: new (self , 0) } # [doc = "Bit 1 - USB transfer completion interrupt flag, direct bit address clear or write 1 to clear"]
# [inline (always)]
# [must_use]
pub fn rb_uif_transfer (& mut self) -> RB_UIF_TRANSFER_W < R8_USB_INT_FG_SPEC > { RB_UIF_TRANSFER_W :: new (self , 1) } # [doc = "Bit 2 - USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear"]
# [inline (always)]
# [must_use]
pub fn rb_uif_suspend (& mut self) -> RB_UIF_SUSPEND_W < R8_USB_INT_FG_SPEC > { RB_UIF_SUSPEND_W :: new (self , 2) } # [doc = "Bit 3 - host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear"]
# [inline (always)]
# [must_use]
pub fn rb_uif_hst_sof (& mut self) -> RB_UIF_HST_SOF_W < R8_USB_INT_FG_SPEC > { RB_UIF_HST_SOF_W :: new (self , 3) } # [doc = "Bit 4 - FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear"]
# [inline (always)]
# [must_use]
pub fn rb_uif_fifo_ov (& mut self) -> RB_UIF_FIFO_OV_W < R8_USB_INT_FG_SPEC > { RB_UIF_FIFO_OV_W :: new (self , 4) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "USB interrupt flag\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_int_fg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_usb_int_fg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_USB_INT_FG_SPEC ; impl crate :: RegisterSpec for R8_USB_INT_FG_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_usb_int_fg::R`](R) reader structure"]
impl crate :: Readable for R8_USB_INT_FG_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_usb_int_fg::W`](W) writer structure"]
impl crate :: Writable for R8_USB_INT_FG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_USB_INT_FG to value 0"]
impl crate :: Resettable for R8_USB_INT_FG_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_USB_INT_ST (r) register accessor: USB interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_int_st::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_int_st`]
module"]
pub type R8_USB_INT_ST = crate :: Reg < r8_usb_int_st :: R8_USB_INT_ST_SPEC > ; # [doc = "USB interrupt status"]
pub mod r8_usb_int_st { # [doc = "Register `R8_USB_INT_ST` reader"]
pub type R = crate :: R < R8_USB_INT_ST_SPEC > ; # [doc = "Field `MASK_UIS_H_RES__MASK_UIS_ENDP` reader - RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received;RO, bit mask of current transfer endpoint number for USB device mode"]
pub type MASK_UIS_H_RES__MASK_UIS_ENDP_R = crate :: FieldReader ; # [doc = "Field `MASK_UIS_TOKEN` reader - RO, bit mask of current token PID code received for USB device mode"]
pub type MASK_UIS_TOKEN_R = crate :: FieldReader ; # [doc = "Field `RB_UIS_TOG_OK` reader - RO, indicate current USB transfer toggle is OK"]
pub type RB_UIS_TOG_OK_R = crate :: BitReader ; # [doc = "Field `RB_UIS_IS_NAK` reader - RO, indicate current USB transfer is NAK received for USB device mode"]
pub type RB_UIS_IS_NAK_R = crate :: BitReader ; impl R { # [doc = "Bits 0:3 - RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received;RO, bit mask of current transfer endpoint number for USB device mode"]
# [inline (always)]
pub fn mask_uis_h_res__mask_uis_endp (& self) -> MASK_UIS_H_RES__MASK_UIS_ENDP_R { MASK_UIS_H_RES__MASK_UIS_ENDP_R :: new (self . bits & 0x0f) } # [doc = "Bits 4:5 - RO, bit mask of current token PID code received for USB device mode"]
# [inline (always)]
pub fn mask_uis_token (& self) -> MASK_UIS_TOKEN_R { MASK_UIS_TOKEN_R :: new ((self . bits >> 4) & 3) } # [doc = "Bit 6 - RO, indicate current USB transfer toggle is OK"]
# [inline (always)]
pub fn rb_uis_tog_ok (& self) -> RB_UIS_TOG_OK_R { RB_UIS_TOG_OK_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - RO, indicate current USB transfer is NAK received for USB device mode"]
# [inline (always)]
pub fn rb_uis_is_nak (& self) -> RB_UIS_IS_NAK_R { RB_UIS_IS_NAK_R :: new (((self . bits >> 7) & 1) != 0) } } # [doc = "USB interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_USB_INT_ST_SPEC ; impl crate :: RegisterSpec for R8_USB_INT_ST_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_usb_int_st::R`](R) reader structure"]
impl crate :: Readable for R8_USB_INT_ST_SPEC { } # [doc = "`reset()` method sets R8_USB_INT_ST to value 0"]
impl crate :: Resettable for R8_USB_INT_ST_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_USB_RX_LEN (r) register accessor: USB receiving length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_rx_len::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_rx_len`]
module"]
pub type R8_USB_RX_LEN = crate :: Reg < r8_usb_rx_len :: R8_USB_RX_LEN_SPEC > ; # [doc = "USB receiving length"]
pub mod r8_usb_rx_len { # [doc = "Register `R8_USB_RX_LEN` reader"]
pub type R = crate :: R < R8_USB_RX_LEN_SPEC > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl core :: fmt :: Debug for crate :: generic :: Reg < R8_USB_RX_LEN_SPEC > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . read () , f) } } # [doc = "USB receiving length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_rx_len::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_USB_RX_LEN_SPEC ; impl crate :: RegisterSpec for R8_USB_RX_LEN_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_usb_rx_len::R`](R) reader structure"]
impl crate :: Readable for R8_USB_RX_LEN_SPEC { } # [doc = "`reset()` method sets R8_USB_RX_LEN to value 0"]
impl crate :: Resettable for R8_USB_RX_LEN_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_UEP4_1_MOD (rw) register accessor: endpoint 4/1 mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep4_1_mod::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep4_1_mod::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep4_1_mod`]
module"]
pub type R8_UEP4_1_MOD = crate :: Reg < r8_uep4_1_mod :: R8_UEP4_1_MOD_SPEC > ; # [doc = "endpoint 4/1 mode"]
pub mod r8_uep4_1_mod { # [doc = "Register `R8_UEP4_1_MOD` reader"]
pub type R = crate :: R < R8_UEP4_1_MOD_SPEC > ; # [doc = "Register `R8_UEP4_1_MOD` writer"]
pub type W = crate :: W < R8_UEP4_1_MOD_SPEC > ; # [doc = "Field `RB_UEP4_TX_EN` reader - enable USB endpoint 4 transmittal (IN)"]
pub type RB_UEP4_TX_EN_R = crate :: BitReader ; # [doc = "Field `RB_UEP4_TX_EN` writer - enable USB endpoint 4 transmittal (IN)"]
pub type RB_UEP4_TX_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP4_RX_EN` reader - enable USB endpoint 4 receiving (OUT)"]
pub type RB_UEP4_RX_EN_R = crate :: BitReader ; # [doc = "Field `RB_UEP4_RX_EN` writer - enable USB endpoint 4 receiving (OUT)"]
pub type RB_UEP4_RX_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP1_BUF_MOD` reader - buffer mode of USB endpoint 1"]
pub type RB_UEP1_BUF_MOD_R = crate :: BitReader ; # [doc = "Field `RB_UEP1_BUF_MOD` writer - buffer mode of USB endpoint 1"]
pub type RB_UEP1_BUF_MOD_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP1_TX_EN` reader - enable USB endpoint 1 transmittal (IN)"]
pub type RB_UEP1_TX_EN_R = crate :: BitReader ; # [doc = "Field `RB_UEP1_TX_EN` writer - enable USB endpoint 1 transmittal (IN)"]
pub type RB_UEP1_TX_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP1_RX_EN` reader - enable USB endpoint 1 receiving (OUT)"]
pub type RB_UEP1_RX_EN_R = crate :: BitReader ; # [doc = "Field `RB_UEP1_RX_EN` writer - enable USB endpoint 1 receiving (OUT)"]
pub type RB_UEP1_RX_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 2 - enable USB endpoint 4 transmittal (IN)"]
# [inline (always)]
pub fn rb_uep4_tx_en (& self) -> RB_UEP4_TX_EN_R { RB_UEP4_TX_EN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - enable USB endpoint 4 receiving (OUT)"]
# [inline (always)]
pub fn rb_uep4_rx_en (& self) -> RB_UEP4_RX_EN_R { RB_UEP4_RX_EN_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - buffer mode of USB endpoint 1"]
# [inline (always)]
pub fn rb_uep1_buf_mod (& self) -> RB_UEP1_BUF_MOD_R { RB_UEP1_BUF_MOD_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 6 - enable USB endpoint 1 transmittal (IN)"]
# [inline (always)]
pub fn rb_uep1_tx_en (& self) -> RB_UEP1_TX_EN_R { RB_UEP1_TX_EN_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - enable USB endpoint 1 receiving (OUT)"]
# [inline (always)]
pub fn rb_uep1_rx_en (& self) -> RB_UEP1_RX_EN_R { RB_UEP1_RX_EN_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bit 2 - enable USB endpoint 4 transmittal (IN)"]
# [inline (always)]
# [must_use]
pub fn rb_uep4_tx_en (& mut self) -> RB_UEP4_TX_EN_W < R8_UEP4_1_MOD_SPEC > { RB_UEP4_TX_EN_W :: new (self , 2) } # [doc = "Bit 3 - enable USB endpoint 4 receiving (OUT)"]
# [inline (always)]
# [must_use]
pub fn rb_uep4_rx_en (& mut self) -> RB_UEP4_RX_EN_W < R8_UEP4_1_MOD_SPEC > { RB_UEP4_RX_EN_W :: new (self , 3) } # [doc = "Bit 4 - buffer mode of USB endpoint 1"]
# [inline (always)]
# [must_use]
pub fn rb_uep1_buf_mod (& mut self) -> RB_UEP1_BUF_MOD_W < R8_UEP4_1_MOD_SPEC > { RB_UEP1_BUF_MOD_W :: new (self , 4) } # [doc = "Bit 6 - enable USB endpoint 1 transmittal (IN)"]
# [inline (always)]
# [must_use]
pub fn rb_uep1_tx_en (& mut self) -> RB_UEP1_TX_EN_W < R8_UEP4_1_MOD_SPEC > { RB_UEP1_TX_EN_W :: new (self , 6) } # [doc = "Bit 7 - enable USB endpoint 1 receiving (OUT)"]
# [inline (always)]
# [must_use]
pub fn rb_uep1_rx_en (& mut self) -> RB_UEP1_RX_EN_W < R8_UEP4_1_MOD_SPEC > { RB_UEP1_RX_EN_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 4/1 mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep4_1_mod::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep4_1_mod::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_UEP4_1_MOD_SPEC ; impl crate :: RegisterSpec for R8_UEP4_1_MOD_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_uep4_1_mod::R`](R) reader structure"]
impl crate :: Readable for R8_UEP4_1_MOD_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_uep4_1_mod::W`](W) writer structure"]
impl crate :: Writable for R8_UEP4_1_MOD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_UEP4_1_MOD to value 0"]
impl crate :: Resettable for R8_UEP4_1_MOD_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_UEP2_3_MOD__R8_UH_EP_MOD (rw) register accessor: endpoint 2/3 mode;host endpoint mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep2_3_mod__r8_uh_ep_mod::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep2_3_mod__r8_uh_ep_mod::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep2_3_mod__r8_uh_ep_mod`]
module"]
pub type R8_UEP2_3_MOD__R8_UH_EP_MOD = crate :: Reg < r8_uep2_3_mod__r8_uh_ep_mod :: R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC > ; # [doc = "endpoint 2/3 mode;host endpoint mode"]
pub mod r8_uep2_3_mod__r8_uh_ep_mod { # [doc = "Register `R8_UEP2_3_MOD__R8_UH_EP_MOD` reader"]
pub type R = crate :: R < R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC > ; # [doc = "Register `R8_UEP2_3_MOD__R8_UH_EP_MOD` writer"]
pub type W = crate :: W < R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC > ; # [doc = "Field `RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD` reader - buffer mode of USB endpoint 2;buffer mode of USB host IN endpoint"]
pub type RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD_R = crate :: BitReader ; # [doc = "Field `RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD` writer - buffer mode of USB endpoint 2;buffer mode of USB host IN endpoint"]
pub type RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP2_TX_EN` reader - enable USB endpoint 2 transmittal (IN)"]
pub type RB_UEP2_TX_EN_R = crate :: BitReader ; # [doc = "Field `RB_UEP2_TX_EN` writer - enable USB endpoint 2 transmittal (IN)"]
pub type RB_UEP2_TX_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP2_RX_EN__RB_UH_EP_RX_EN` reader - enable USB endpoint 2 receiving (OUT);enable USB host IN endpoint receiving"]
pub type RB_UEP2_RX_EN__RB_UH_EP_RX_EN_R = crate :: BitReader ; # [doc = "Field `RB_UEP2_RX_EN__RB_UH_EP_RX_EN` writer - enable USB endpoint 2 receiving (OUT);enable USB host IN endpoint receiving"]
pub type RB_UEP2_RX_EN__RB_UH_EP_RX_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD` reader - buffer mode of USB endpoint 3;buffer mode of USB host OUT endpoint"]
pub type RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD_R = crate :: BitReader ; # [doc = "Field `RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD` writer - buffer mode of USB endpoint 3;buffer mode of USB host OUT endpoint"]
pub type RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP3_TX_EN__RB_UH_EP_TX_EN` reader - enable USB endpoint 3 transmittal (IN);enable USB host OUT endpoint transmittal"]
pub type RB_UEP3_TX_EN__RB_UH_EP_TX_EN_R = crate :: BitReader ; # [doc = "Field `RB_UEP3_TX_EN__RB_UH_EP_TX_EN` writer - enable USB endpoint 3 transmittal (IN);enable USB host OUT endpoint transmittal"]
pub type RB_UEP3_TX_EN__RB_UH_EP_TX_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP3_RX_EN` reader - enable USB endpoint 3 receiving (OUT)"]
pub type RB_UEP3_RX_EN_R = crate :: BitReader ; # [doc = "Field `RB_UEP3_RX_EN` writer - enable USB endpoint 3 receiving (OUT)"]
pub type RB_UEP3_RX_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - buffer mode of USB endpoint 2;buffer mode of USB host IN endpoint"]
# [inline (always)]
pub fn rb_uep2_buf_mod__rb_uh_ep_rbuf_mod (& self) -> RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD_R { RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - enable USB endpoint 2 transmittal (IN)"]
# [inline (always)]
pub fn rb_uep2_tx_en (& self) -> RB_UEP2_TX_EN_R { RB_UEP2_TX_EN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - enable USB endpoint 2 receiving (OUT);enable USB host IN endpoint receiving"]
# [inline (always)]
pub fn rb_uep2_rx_en__rb_uh_ep_rx_en (& self) -> RB_UEP2_RX_EN__RB_UH_EP_RX_EN_R { RB_UEP2_RX_EN__RB_UH_EP_RX_EN_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - buffer mode of USB endpoint 3;buffer mode of USB host OUT endpoint"]
# [inline (always)]
pub fn rb_uep3_buf_mod__rb_uh_ep_tbuf_mod (& self) -> RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD_R { RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 6 - enable USB endpoint 3 transmittal (IN);enable USB host OUT endpoint transmittal"]
# [inline (always)]
pub fn rb_uep3_tx_en__rb_uh_ep_tx_en (& self) -> RB_UEP3_TX_EN__RB_UH_EP_TX_EN_R { RB_UEP3_TX_EN__RB_UH_EP_TX_EN_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - enable USB endpoint 3 receiving (OUT)"]
# [inline (always)]
pub fn rb_uep3_rx_en (& self) -> RB_UEP3_RX_EN_R { RB_UEP3_RX_EN_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bit 0 - buffer mode of USB endpoint 2;buffer mode of USB host IN endpoint"]
# [inline (always)]
# [must_use]
pub fn rb_uep2_buf_mod__rb_uh_ep_rbuf_mod (& mut self) -> RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD_W < R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC > { RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD_W :: new (self , 0) } # [doc = "Bit 2 - enable USB endpoint 2 transmittal (IN)"]
# [inline (always)]
# [must_use]
pub fn rb_uep2_tx_en (& mut self) -> RB_UEP2_TX_EN_W < R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC > { RB_UEP2_TX_EN_W :: new (self , 2) } # [doc = "Bit 3 - enable USB endpoint 2 receiving (OUT);enable USB host IN endpoint receiving"]
# [inline (always)]
# [must_use]
pub fn rb_uep2_rx_en__rb_uh_ep_rx_en (& mut self) -> RB_UEP2_RX_EN__RB_UH_EP_RX_EN_W < R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC > { RB_UEP2_RX_EN__RB_UH_EP_RX_EN_W :: new (self , 3) } # [doc = "Bit 4 - buffer mode of USB endpoint 3;buffer mode of USB host OUT endpoint"]
# [inline (always)]
# [must_use]
pub fn rb_uep3_buf_mod__rb_uh_ep_tbuf_mod (& mut self) -> RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD_W < R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC > { RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD_W :: new (self , 4) } # [doc = "Bit 6 - enable USB endpoint 3 transmittal (IN);enable USB host OUT endpoint transmittal"]
# [inline (always)]
# [must_use]
pub fn rb_uep3_tx_en__rb_uh_ep_tx_en (& mut self) -> RB_UEP3_TX_EN__RB_UH_EP_TX_EN_W < R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC > { RB_UEP3_TX_EN__RB_UH_EP_TX_EN_W :: new (self , 6) } # [doc = "Bit 7 - enable USB endpoint 3 receiving (OUT)"]
# [inline (always)]
# [must_use]
pub fn rb_uep3_rx_en (& mut self) -> RB_UEP3_RX_EN_W < R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC > { RB_UEP3_RX_EN_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 2/3 mode;host endpoint mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep2_3_mod__r8_uh_ep_mod::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep2_3_mod__r8_uh_ep_mod::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC ; impl crate :: RegisterSpec for R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_uep2_3_mod__r8_uh_ep_mod::R`](R) reader structure"]
impl crate :: Readable for R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_uep2_3_mod__r8_uh_ep_mod::W`](W) writer structure"]
impl crate :: Writable for R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_UEP2_3_MOD__R8_UH_EP_MOD to value 0"]
impl crate :: Resettable for R8_UEP2_3_MOD__R8_UH_EP_MOD_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R16_UEP0_DMA (rw) register accessor: endpoint 0 DMA buffer address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r16_uep0_dma::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r16_uep0_dma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uep0_dma`]
module"]
pub type R16_UEP0_DMA = crate :: Reg < r16_uep0_dma :: R16_UEP0_DMA_SPEC > ; # [doc = "endpoint 0 DMA buffer address"]
pub mod r16_uep0_dma { # [doc = "Register `R16_UEP0_DMA` reader"]
pub type R = crate :: R < R16_UEP0_DMA_SPEC > ; # [doc = "Register `R16_UEP0_DMA` writer"]
pub type W = crate :: W < R16_UEP0_DMA_SPEC > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl core :: fmt :: Debug for crate :: generic :: Reg < R16_UEP0_DMA_SPEC > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . read () , f) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 0 DMA buffer address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r16_uep0_dma::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r16_uep0_dma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16_UEP0_DMA_SPEC ; impl crate :: RegisterSpec for R16_UEP0_DMA_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`r16_uep0_dma::R`](R) reader structure"]
impl crate :: Readable for R16_UEP0_DMA_SPEC { } # [doc = "`write(|w| ..)` method takes [`r16_uep0_dma::W`](W) writer structure"]
impl crate :: Writable for R16_UEP0_DMA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets R16_UEP0_DMA to value 0"]
impl crate :: Resettable for R16_UEP0_DMA_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "R16_UEP1_DMA (rw) register accessor: endpoint 1 DMA buffer address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r16_uep1_dma::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r16_uep1_dma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uep1_dma`]
module"]
pub type R16_UEP1_DMA = crate :: Reg < r16_uep1_dma :: R16_UEP1_DMA_SPEC > ; # [doc = "endpoint 1 DMA buffer address"]
pub mod r16_uep1_dma { # [doc = "Register `R16_UEP1_DMA` reader"]
pub type R = crate :: R < R16_UEP1_DMA_SPEC > ; # [doc = "Register `R16_UEP1_DMA` writer"]
pub type W = crate :: W < R16_UEP1_DMA_SPEC > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl core :: fmt :: Debug for crate :: generic :: Reg < R16_UEP1_DMA_SPEC > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . read () , f) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 1 DMA buffer address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r16_uep1_dma::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r16_uep1_dma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16_UEP1_DMA_SPEC ; impl crate :: RegisterSpec for R16_UEP1_DMA_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`r16_uep1_dma::R`](R) reader structure"]
impl crate :: Readable for R16_UEP1_DMA_SPEC { } # [doc = "`write(|w| ..)` method takes [`r16_uep1_dma::W`](W) writer structure"]
impl crate :: Writable for R16_UEP1_DMA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets R16_UEP1_DMA to value 0"]
impl crate :: Resettable for R16_UEP1_DMA_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "R16_UEP2_DMA__R16_UH_RX_DMA (rw) register accessor: endpoint 2 DMA buffer address;host rx endpoint buffer high address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r16_uep2_dma__r16_uh_rx_dma::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r16_uep2_dma__r16_uh_rx_dma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uep2_dma__r16_uh_rx_dma`]
module"]
pub type R16_UEP2_DMA__R16_UH_RX_DMA = crate :: Reg < r16_uep2_dma__r16_uh_rx_dma :: R16_UEP2_DMA__R16_UH_RX_DMA_SPEC > ; # [doc = "endpoint 2 DMA buffer address;host rx endpoint buffer high address"]
pub mod r16_uep2_dma__r16_uh_rx_dma { # [doc = "Register `R16_UEP2_DMA__R16_UH_RX_DMA` reader"]
pub type R = crate :: R < R16_UEP2_DMA__R16_UH_RX_DMA_SPEC > ; # [doc = "Register `R16_UEP2_DMA__R16_UH_RX_DMA` writer"]
pub type W = crate :: W < R16_UEP2_DMA__R16_UH_RX_DMA_SPEC > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl core :: fmt :: Debug for crate :: generic :: Reg < R16_UEP2_DMA__R16_UH_RX_DMA_SPEC > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . read () , f) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 2 DMA buffer address;host rx endpoint buffer high address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r16_uep2_dma__r16_uh_rx_dma::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r16_uep2_dma__r16_uh_rx_dma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16_UEP2_DMA__R16_UH_RX_DMA_SPEC ; impl crate :: RegisterSpec for R16_UEP2_DMA__R16_UH_RX_DMA_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`r16_uep2_dma__r16_uh_rx_dma::R`](R) reader structure"]
impl crate :: Readable for R16_UEP2_DMA__R16_UH_RX_DMA_SPEC { } # [doc = "`write(|w| ..)` method takes [`r16_uep2_dma__r16_uh_rx_dma::W`](W) writer structure"]
impl crate :: Writable for R16_UEP2_DMA__R16_UH_RX_DMA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets R16_UEP2_DMA__R16_UH_RX_DMA to value 0"]
impl crate :: Resettable for R16_UEP2_DMA__R16_UH_RX_DMA_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "R16_UEP3_DMA__R16_UH_TX_DMA (rw) register accessor: endpoint 3 DMA buffer address;host tx endpoint buffer high address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r16_uep3_dma__r16_uh_tx_dma::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r16_uep3_dma__r16_uh_tx_dma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r16_uep3_dma__r16_uh_tx_dma`]
module"]
pub type R16_UEP3_DMA__R16_UH_TX_DMA = crate :: Reg < r16_uep3_dma__r16_uh_tx_dma :: R16_UEP3_DMA__R16_UH_TX_DMA_SPEC > ; # [doc = "endpoint 3 DMA buffer address;host tx endpoint buffer high address"]
pub mod r16_uep3_dma__r16_uh_tx_dma { # [doc = "Register `R16_UEP3_DMA__R16_UH_TX_DMA` reader"]
pub type R = crate :: R < R16_UEP3_DMA__R16_UH_TX_DMA_SPEC > ; # [doc = "Register `R16_UEP3_DMA__R16_UH_TX_DMA` writer"]
pub type W = crate :: W < R16_UEP3_DMA__R16_UH_TX_DMA_SPEC > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl core :: fmt :: Debug for crate :: generic :: Reg < R16_UEP3_DMA__R16_UH_TX_DMA_SPEC > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . read () , f) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 3 DMA buffer address;host tx endpoint buffer high address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r16_uep3_dma__r16_uh_tx_dma::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r16_uep3_dma__r16_uh_tx_dma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R16_UEP3_DMA__R16_UH_TX_DMA_SPEC ; impl crate :: RegisterSpec for R16_UEP3_DMA__R16_UH_TX_DMA_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`r16_uep3_dma__r16_uh_tx_dma::R`](R) reader structure"]
impl crate :: Readable for R16_UEP3_DMA__R16_UH_TX_DMA_SPEC { } # [doc = "`write(|w| ..)` method takes [`r16_uep3_dma__r16_uh_tx_dma::W`](W) writer structure"]
impl crate :: Writable for R16_UEP3_DMA__R16_UH_TX_DMA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets R16_UEP3_DMA__R16_UH_TX_DMA to value 0"]
impl crate :: Resettable for R16_UEP3_DMA__R16_UH_TX_DMA_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "R8_UEP0_T_LEN (rw) register accessor: endpoint 0 transmittal length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep0_t_len::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep0_t_len::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep0_t_len`]
module"]
pub type R8_UEP0_T_LEN = crate :: Reg < r8_uep0_t_len :: R8_UEP0_T_LEN_SPEC > ; # [doc = "endpoint 0 transmittal length"]
pub mod r8_uep0_t_len { # [doc = "Register `R8_UEP0_T_LEN` reader"]
pub type R = crate :: R < R8_UEP0_T_LEN_SPEC > ; # [doc = "Register `R8_UEP0_T_LEN` writer"]
pub type W = crate :: W < R8_UEP0_T_LEN_SPEC > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl core :: fmt :: Debug for crate :: generic :: Reg < R8_UEP0_T_LEN_SPEC > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . read () , f) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 0 transmittal length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep0_t_len::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep0_t_len::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_UEP0_T_LEN_SPEC ; impl crate :: RegisterSpec for R8_UEP0_T_LEN_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_uep0_t_len::R`](R) reader structure"]
impl crate :: Readable for R8_UEP0_T_LEN_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_uep0_t_len::W`](W) writer structure"]
impl crate :: Writable for R8_UEP0_T_LEN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_UEP0_T_LEN to value 0"]
impl crate :: Resettable for R8_UEP0_T_LEN_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_UEP0_CTRL (rw) register accessor: endpoint 0 control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep0_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep0_ctrl`]
module"]
pub type R8_UEP0_CTRL = crate :: Reg < r8_uep0_ctrl :: R8_UEP0_CTRL_SPEC > ; # [doc = "endpoint 0 control"]
pub mod r8_uep0_ctrl { # [doc = "Register `R8_UEP0_CTRL` reader"]
pub type R = crate :: R < R8_UEP0_CTRL_SPEC > ; # [doc = "Register `R8_UEP0_CTRL` writer"]
pub type W = crate :: W < R8_UEP0_CTRL_SPEC > ; # [doc = "Field `MASK_UEP_T_RES` reader - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MASK_UEP_T_RES_R = crate :: FieldReader ; # [doc = "Field `MASK_UEP_T_RES` writer - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MASK_UEP_T_RES_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MASK_UEP_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MASK_UEP_R_RES_R = crate :: FieldReader ; # [doc = "Field `MASK_UEP_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MASK_UEP_R_RES_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RB_UEP_AUTO_TOG` reader - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
pub type RB_UEP_AUTO_TOG_R = crate :: BitReader ; # [doc = "Field `RB_UEP_AUTO_TOG` writer - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
pub type RB_UEP_AUTO_TOG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP_T_TOG` reader - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RB_UEP_T_TOG_R = crate :: BitReader ; # [doc = "Field `RB_UEP_T_TOG` writer - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RB_UEP_T_TOG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP_R_TOG` reader - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RB_UEP_R_TOG_R = crate :: BitReader ; # [doc = "Field `RB_UEP_R_TOG` writer - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RB_UEP_R_TOG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
# [inline (always)]
pub fn mask_uep_t_res (& self) -> MASK_UEP_T_RES_R { MASK_UEP_T_RES_R :: new (self . bits & 3) } # [doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
# [inline (always)]
pub fn mask_uep_r_res (& self) -> MASK_UEP_R_RES_R { MASK_UEP_R_RES_R :: new ((self . bits >> 2) & 3) } # [doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
# [inline (always)]
pub fn rb_uep_auto_tog (& self) -> RB_UEP_AUTO_TOG_R { RB_UEP_AUTO_TOG_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
# [inline (always)]
pub fn rb_uep_t_tog (& self) -> RB_UEP_T_TOG_R { RB_UEP_T_TOG_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
# [inline (always)]
pub fn rb_uep_r_tog (& self) -> RB_UEP_R_TOG_R { RB_UEP_R_TOG_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
# [inline (always)]
# [must_use]
pub fn mask_uep_t_res (& mut self) -> MASK_UEP_T_RES_W < R8_UEP0_CTRL_SPEC > { MASK_UEP_T_RES_W :: new (self , 0) } # [doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
# [inline (always)]
# [must_use]
pub fn mask_uep_r_res (& mut self) -> MASK_UEP_R_RES_W < R8_UEP0_CTRL_SPEC > { MASK_UEP_R_RES_W :: new (self , 2) } # [doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
# [inline (always)]
# [must_use]
pub fn rb_uep_auto_tog (& mut self) -> RB_UEP_AUTO_TOG_W < R8_UEP0_CTRL_SPEC > { RB_UEP_AUTO_TOG_W :: new (self , 4) } # [doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
# [inline (always)]
# [must_use]
pub fn rb_uep_t_tog (& mut self) -> RB_UEP_T_TOG_W < R8_UEP0_CTRL_SPEC > { RB_UEP_T_TOG_W :: new (self , 6) } # [doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
# [inline (always)]
# [must_use]
pub fn rb_uep_r_tog (& mut self) -> RB_UEP_R_TOG_W < R8_UEP0_CTRL_SPEC > { RB_UEP_R_TOG_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 0 control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep0_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_UEP0_CTRL_SPEC ; impl crate :: RegisterSpec for R8_UEP0_CTRL_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_uep0_ctrl::R`](R) reader structure"]
impl crate :: Readable for R8_UEP0_CTRL_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_uep0_ctrl::W`](W) writer structure"]
impl crate :: Writable for R8_UEP0_CTRL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_UEP0_CTRL to value 0"]
impl crate :: Resettable for R8_UEP0_CTRL_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_UEP1_T_LEN (rw) register accessor: endpoint 1 transmittal length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep1_t_len::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep1_t_len::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep1_t_len`]
module"]
pub type R8_UEP1_T_LEN = crate :: Reg < r8_uep1_t_len :: R8_UEP1_T_LEN_SPEC > ; # [doc = "endpoint 1 transmittal length"]
pub mod r8_uep1_t_len { # [doc = "Register `R8_UEP1_T_LEN` reader"]
pub type R = crate :: R < R8_UEP1_T_LEN_SPEC > ; # [doc = "Register `R8_UEP1_T_LEN` writer"]
pub type W = crate :: W < R8_UEP1_T_LEN_SPEC > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl core :: fmt :: Debug for crate :: generic :: Reg < R8_UEP1_T_LEN_SPEC > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . read () , f) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 1 transmittal length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep1_t_len::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep1_t_len::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_UEP1_T_LEN_SPEC ; impl crate :: RegisterSpec for R8_UEP1_T_LEN_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_uep1_t_len::R`](R) reader structure"]
impl crate :: Readable for R8_UEP1_T_LEN_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_uep1_t_len::W`](W) writer structure"]
impl crate :: Writable for R8_UEP1_T_LEN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_UEP1_T_LEN to value 0"]
impl crate :: Resettable for R8_UEP1_T_LEN_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_UEP1_CTRL__R8_UH_SETUP (rw) register accessor: endpoint 1 control;host aux setup\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep1_ctrl__r8_uh_setup::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep1_ctrl__r8_uh_setup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep1_ctrl__r8_uh_setup`]
module"]
pub type R8_UEP1_CTRL__R8_UH_SETUP = crate :: Reg < r8_uep1_ctrl__r8_uh_setup :: R8_UEP1_CTRL__R8_UH_SETUP_SPEC > ; # [doc = "endpoint 1 control;host aux setup"]
pub mod r8_uep1_ctrl__r8_uh_setup { # [doc = "Register `R8_UEP1_CTRL__R8_UH_SETUP` reader"]
pub type R = crate :: R < R8_UEP1_CTRL__R8_UH_SETUP_SPEC > ; # [doc = "Register `R8_UEP1_CTRL__R8_UH_SETUP` writer"]
pub type W = crate :: W < R8_UEP1_CTRL__R8_UH_SETUP_SPEC > ; # [doc = "Field `MASK_UEP_T_RES` reader - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MASK_UEP_T_RES_R = crate :: FieldReader ; # [doc = "Field `MASK_UEP_T_RES` writer - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MASK_UEP_T_RES_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MASK_UEP_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MASK_UEP_R_RES_R = crate :: FieldReader ; # [doc = "Field `MASK_UEP_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MASK_UEP_R_RES_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RB_UEP_AUTO_TOG` reader - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
pub type RB_UEP_AUTO_TOG_R = crate :: BitReader ; # [doc = "Field `RB_UEP_AUTO_TOG` writer - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
pub type RB_UEP_AUTO_TOG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP_T_TOG__RB_UH_SOF_EN` reader - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1;USB host automatic SOF enable"]
pub type RB_UEP_T_TOG__RB_UH_SOF_EN_R = crate :: BitReader ; # [doc = "Field `RB_UEP_T_TOG__RB_UH_SOF_EN` writer - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1;USB host automatic SOF enable"]
pub type RB_UEP_T_TOG__RB_UH_SOF_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP_R_TOG__RB_UH_PRE_PID_EN` reader - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;RB_UH_PRE_PID_EN;USB host PRE PID enable for low speed device via hub"]
pub type RB_UEP_R_TOG__RB_UH_PRE_PID_EN_R = crate :: BitReader ; # [doc = "Field `RB_UEP_R_TOG__RB_UH_PRE_PID_EN` writer - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;RB_UH_PRE_PID_EN;USB host PRE PID enable for low speed device via hub"]
pub type RB_UEP_R_TOG__RB_UH_PRE_PID_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
# [inline (always)]
pub fn mask_uep_t_res (& self) -> MASK_UEP_T_RES_R { MASK_UEP_T_RES_R :: new (self . bits & 3) } # [doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
# [inline (always)]
pub fn mask_uep_r_res (& self) -> MASK_UEP_R_RES_R { MASK_UEP_R_RES_R :: new ((self . bits >> 2) & 3) } # [doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
# [inline (always)]
pub fn rb_uep_auto_tog (& self) -> RB_UEP_AUTO_TOG_R { RB_UEP_AUTO_TOG_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1;USB host automatic SOF enable"]
# [inline (always)]
pub fn rb_uep_t_tog__rb_uh_sof_en (& self) -> RB_UEP_T_TOG__RB_UH_SOF_EN_R { RB_UEP_T_TOG__RB_UH_SOF_EN_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;RB_UH_PRE_PID_EN;USB host PRE PID enable for low speed device via hub"]
# [inline (always)]
pub fn rb_uep_r_tog__rb_uh_pre_pid_en (& self) -> RB_UEP_R_TOG__RB_UH_PRE_PID_EN_R { RB_UEP_R_TOG__RB_UH_PRE_PID_EN_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
# [inline (always)]
# [must_use]
pub fn mask_uep_t_res (& mut self) -> MASK_UEP_T_RES_W < R8_UEP1_CTRL__R8_UH_SETUP_SPEC > { MASK_UEP_T_RES_W :: new (self , 0) } # [doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
# [inline (always)]
# [must_use]
pub fn mask_uep_r_res (& mut self) -> MASK_UEP_R_RES_W < R8_UEP1_CTRL__R8_UH_SETUP_SPEC > { MASK_UEP_R_RES_W :: new (self , 2) } # [doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
# [inline (always)]
# [must_use]
pub fn rb_uep_auto_tog (& mut self) -> RB_UEP_AUTO_TOG_W < R8_UEP1_CTRL__R8_UH_SETUP_SPEC > { RB_UEP_AUTO_TOG_W :: new (self , 4) } # [doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1;USB host automatic SOF enable"]
# [inline (always)]
# [must_use]
pub fn rb_uep_t_tog__rb_uh_sof_en (& mut self) -> RB_UEP_T_TOG__RB_UH_SOF_EN_W < R8_UEP1_CTRL__R8_UH_SETUP_SPEC > { RB_UEP_T_TOG__RB_UH_SOF_EN_W :: new (self , 6) } # [doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;RB_UH_PRE_PID_EN;USB host PRE PID enable for low speed device via hub"]
# [inline (always)]
# [must_use]
pub fn rb_uep_r_tog__rb_uh_pre_pid_en (& mut self) -> RB_UEP_R_TOG__RB_UH_PRE_PID_EN_W < R8_UEP1_CTRL__R8_UH_SETUP_SPEC > { RB_UEP_R_TOG__RB_UH_PRE_PID_EN_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 1 control;host aux setup\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep1_ctrl__r8_uh_setup::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep1_ctrl__r8_uh_setup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_UEP1_CTRL__R8_UH_SETUP_SPEC ; impl crate :: RegisterSpec for R8_UEP1_CTRL__R8_UH_SETUP_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_uep1_ctrl__r8_uh_setup::R`](R) reader structure"]
impl crate :: Readable for R8_UEP1_CTRL__R8_UH_SETUP_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_uep1_ctrl__r8_uh_setup::W`](W) writer structure"]
impl crate :: Writable for R8_UEP1_CTRL__R8_UH_SETUP_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_UEP1_CTRL__R8_UH_SETUP to value 0"]
impl crate :: Resettable for R8_UEP1_CTRL__R8_UH_SETUP_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_UEP2_T_LEN__R8_UH_EP_PID (rw) register accessor: endpoint 2 transmittal length;host endpoint and PID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep2_t_len__r8_uh_ep_pid::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep2_t_len__r8_uh_ep_pid::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep2_t_len__r8_uh_ep_pid`]
module"]
pub type R8_UEP2_T_LEN__R8_UH_EP_PID = crate :: Reg < r8_uep2_t_len__r8_uh_ep_pid :: R8_UEP2_T_LEN__R8_UH_EP_PID_SPEC > ; # [doc = "endpoint 2 transmittal length;host endpoint and PID"]
pub mod r8_uep2_t_len__r8_uh_ep_pid { # [doc = "Register `R8_UEP2_T_LEN__R8_UH_EP_PID` reader"]
pub type R = crate :: R < R8_UEP2_T_LEN__R8_UH_EP_PID_SPEC > ; # [doc = "Register `R8_UEP2_T_LEN__R8_UH_EP_PID` writer"]
pub type W = crate :: W < R8_UEP2_T_LEN__R8_UH_EP_PID_SPEC > ; # [doc = "Field `MASK_UH_ENDP` reader - bit mask of endpoint number for USB host transfer"]
pub type MASK_UH_ENDP_R = crate :: FieldReader ; # [doc = "Field `MASK_UH_ENDP` writer - bit mask of endpoint number for USB host transfer"]
pub type MASK_UH_ENDP_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `MASK_UH_TOKEN` reader - bit mask of token PID for USB host transfer"]
pub type MASK_UH_TOKEN_R = crate :: FieldReader ; # [doc = "Field `MASK_UH_TOKEN` writer - bit mask of token PID for USB host transfer"]
pub type MASK_UH_TOKEN_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 0:3 - bit mask of endpoint number for USB host transfer"]
# [inline (always)]
pub fn mask_uh_endp (& self) -> MASK_UH_ENDP_R { MASK_UH_ENDP_R :: new (self . bits & 0x0f) } # [doc = "Bits 4:7 - bit mask of token PID for USB host transfer"]
# [inline (always)]
pub fn mask_uh_token (& self) -> MASK_UH_TOKEN_R { MASK_UH_TOKEN_R :: new ((self . bits >> 4) & 0x0f) } } impl W { # [doc = "Bits 0:3 - bit mask of endpoint number for USB host transfer"]
# [inline (always)]
# [must_use]
pub fn mask_uh_endp (& mut self) -> MASK_UH_ENDP_W < R8_UEP2_T_LEN__R8_UH_EP_PID_SPEC > { MASK_UH_ENDP_W :: new (self , 0) } # [doc = "Bits 4:7 - bit mask of token PID for USB host transfer"]
# [inline (always)]
# [must_use]
pub fn mask_uh_token (& mut self) -> MASK_UH_TOKEN_W < R8_UEP2_T_LEN__R8_UH_EP_PID_SPEC > { MASK_UH_TOKEN_W :: new (self , 4) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 2 transmittal length;host endpoint and PID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep2_t_len__r8_uh_ep_pid::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep2_t_len__r8_uh_ep_pid::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_UEP2_T_LEN__R8_UH_EP_PID_SPEC ; impl crate :: RegisterSpec for R8_UEP2_T_LEN__R8_UH_EP_PID_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_uep2_t_len__r8_uh_ep_pid::R`](R) reader structure"]
impl crate :: Readable for R8_UEP2_T_LEN__R8_UH_EP_PID_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_uep2_t_len__r8_uh_ep_pid::W`](W) writer structure"]
impl crate :: Writable for R8_UEP2_T_LEN__R8_UH_EP_PID_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_UEP2_T_LEN__R8_UH_EP_PID to value 0"]
impl crate :: Resettable for R8_UEP2_T_LEN__R8_UH_EP_PID_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_UEP2_CTRL__R8_UH_RX_CTRL (rw) register accessor: endpoint 2 control;host receiver endpoint control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep2_ctrl__r8_uh_rx_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep2_ctrl__r8_uh_rx_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep2_ctrl__r8_uh_rx_ctrl`]
module"]
pub type R8_UEP2_CTRL__R8_UH_RX_CTRL = crate :: Reg < r8_uep2_ctrl__r8_uh_rx_ctrl :: R8_UEP2_CTRL__R8_UH_RX_CTRL_SPEC > ; # [doc = "endpoint 2 control;host receiver endpoint control"]
pub mod r8_uep2_ctrl__r8_uh_rx_ctrl { # [doc = "Register `R8_UEP2_CTRL__R8_UH_RX_CTRL` reader"]
pub type R = crate :: R < R8_UEP2_CTRL__R8_UH_RX_CTRL_SPEC > ; # [doc = "Register `R8_UEP2_CTRL__R8_UH_RX_CTRL` writer"]
pub type W = crate :: W < R8_UEP2_CTRL__R8_UH_RX_CTRL_SPEC > ; # [doc = "Field `MASK_UEP_T_RES` reader - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MASK_UEP_T_RES_R = crate :: FieldReader ; # [doc = "Field `MASK_UEP_T_RES` writer - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MASK_UEP_T_RES_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MASK_UEP_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MASK_UEP_R_RES_R = crate :: FieldReader ; # [doc = "Field `MASK_UEP_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MASK_UEP_R_RES_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RB_UEP_AUTO_TOG__RB_UH_R_AUTO_TOG` reader - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle;enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle"]
pub type RB_UEP_AUTO_TOG__RB_UH_R_AUTO_TOG_R = crate :: BitReader ; # [doc = "Field `RB_UEP_AUTO_TOG__RB_UH_R_AUTO_TOG` writer - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle;enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle"]
pub type RB_UEP_AUTO_TOG__RB_UH_R_AUTO_TOG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP_T_TOG` reader - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RB_UEP_T_TOG_R = crate :: BitReader ; # [doc = "Field `RB_UEP_T_TOG` writer - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RB_UEP_T_TOG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP_R_TOG__RB_UH_R_TOG` reader - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1"]
pub type RB_UEP_R_TOG__RB_UH_R_TOG_R = crate :: BitReader ; # [doc = "Field `RB_UEP_R_TOG__RB_UH_R_TOG` writer - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1"]
pub type RB_UEP_R_TOG__RB_UH_R_TOG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
# [inline (always)]
pub fn mask_uep_t_res (& self) -> MASK_UEP_T_RES_R { MASK_UEP_T_RES_R :: new (self . bits & 3) } # [doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
# [inline (always)]
pub fn mask_uep_r_res (& self) -> MASK_UEP_R_RES_R { MASK_UEP_R_RES_R :: new ((self . bits >> 2) & 3) } # [doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle;enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle"]
# [inline (always)]
pub fn rb_uep_auto_tog__rb_uh_r_auto_tog (& self) -> RB_UEP_AUTO_TOG__RB_UH_R_AUTO_TOG_R { RB_UEP_AUTO_TOG__RB_UH_R_AUTO_TOG_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
# [inline (always)]
pub fn rb_uep_t_tog (& self) -> RB_UEP_T_TOG_R { RB_UEP_T_TOG_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1"]
# [inline (always)]
pub fn rb_uep_r_tog__rb_uh_r_tog (& self) -> RB_UEP_R_TOG__RB_UH_R_TOG_R { RB_UEP_R_TOG__RB_UH_R_TOG_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
# [inline (always)]
# [must_use]
pub fn mask_uep_t_res (& mut self) -> MASK_UEP_T_RES_W < R8_UEP2_CTRL__R8_UH_RX_CTRL_SPEC > { MASK_UEP_T_RES_W :: new (self , 0) } # [doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
# [inline (always)]
# [must_use]
pub fn mask_uep_r_res (& mut self) -> MASK_UEP_R_RES_W < R8_UEP2_CTRL__R8_UH_RX_CTRL_SPEC > { MASK_UEP_R_RES_W :: new (self , 2) } # [doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle;enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle"]
# [inline (always)]
# [must_use]
pub fn rb_uep_auto_tog__rb_uh_r_auto_tog (& mut self) -> RB_UEP_AUTO_TOG__RB_UH_R_AUTO_TOG_W < R8_UEP2_CTRL__R8_UH_RX_CTRL_SPEC > { RB_UEP_AUTO_TOG__RB_UH_R_AUTO_TOG_W :: new (self , 4) } # [doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
# [inline (always)]
# [must_use]
pub fn rb_uep_t_tog (& mut self) -> RB_UEP_T_TOG_W < R8_UEP2_CTRL__R8_UH_RX_CTRL_SPEC > { RB_UEP_T_TOG_W :: new (self , 6) } # [doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1"]
# [inline (always)]
# [must_use]
pub fn rb_uep_r_tog__rb_uh_r_tog (& mut self) -> RB_UEP_R_TOG__RB_UH_R_TOG_W < R8_UEP2_CTRL__R8_UH_RX_CTRL_SPEC > { RB_UEP_R_TOG__RB_UH_R_TOG_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 2 control;host receiver endpoint control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep2_ctrl__r8_uh_rx_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep2_ctrl__r8_uh_rx_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_UEP2_CTRL__R8_UH_RX_CTRL_SPEC ; impl crate :: RegisterSpec for R8_UEP2_CTRL__R8_UH_RX_CTRL_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_uep2_ctrl__r8_uh_rx_ctrl::R`](R) reader structure"]
impl crate :: Readable for R8_UEP2_CTRL__R8_UH_RX_CTRL_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_uep2_ctrl__r8_uh_rx_ctrl::W`](W) writer structure"]
impl crate :: Writable for R8_UEP2_CTRL__R8_UH_RX_CTRL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_UEP2_CTRL__R8_UH_RX_CTRL to value 0"]
impl crate :: Resettable for R8_UEP2_CTRL__R8_UH_RX_CTRL_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_UEP3_T_LEN__R8_UH_TX_LEN (rw) register accessor: endpoint 3 transmittal length;host transmittal endpoint transmittal length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep3_t_len__r8_uh_tx_len::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep3_t_len__r8_uh_tx_len::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep3_t_len__r8_uh_tx_len`]
module"]
pub type R8_UEP3_T_LEN__R8_UH_TX_LEN = crate :: Reg < r8_uep3_t_len__r8_uh_tx_len :: R8_UEP3_T_LEN__R8_UH_TX_LEN_SPEC > ; # [doc = "endpoint 3 transmittal length;host transmittal endpoint transmittal length"]
pub mod r8_uep3_t_len__r8_uh_tx_len { # [doc = "Register `R8_UEP3_T_LEN__R8_UH_TX_LEN` reader"]
pub type R = crate :: R < R8_UEP3_T_LEN__R8_UH_TX_LEN_SPEC > ; # [doc = "Register `R8_UEP3_T_LEN__R8_UH_TX_LEN` writer"]
pub type W = crate :: W < R8_UEP3_T_LEN__R8_UH_TX_LEN_SPEC > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl core :: fmt :: Debug for crate :: generic :: Reg < R8_UEP3_T_LEN__R8_UH_TX_LEN_SPEC > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . read () , f) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 3 transmittal length;host transmittal endpoint transmittal length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep3_t_len__r8_uh_tx_len::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep3_t_len__r8_uh_tx_len::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_UEP3_T_LEN__R8_UH_TX_LEN_SPEC ; impl crate :: RegisterSpec for R8_UEP3_T_LEN__R8_UH_TX_LEN_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_uep3_t_len__r8_uh_tx_len::R`](R) reader structure"]
impl crate :: Readable for R8_UEP3_T_LEN__R8_UH_TX_LEN_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_uep3_t_len__r8_uh_tx_len::W`](W) writer structure"]
impl crate :: Writable for R8_UEP3_T_LEN__R8_UH_TX_LEN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_UEP3_T_LEN__R8_UH_TX_LEN to value 0"]
impl crate :: Resettable for R8_UEP3_T_LEN__R8_UH_TX_LEN_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_UEP3_CTRL__R8_UH_TX_CTRL (rw) register accessor: endpoint 3 control;host transmittal endpoint control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep3_ctrl__r8_uh_tx_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep3_ctrl__r8_uh_tx_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep3_ctrl__r8_uh_tx_ctrl`]
module"]
pub type R8_UEP3_CTRL__R8_UH_TX_CTRL = crate :: Reg < r8_uep3_ctrl__r8_uh_tx_ctrl :: R8_UEP3_CTRL__R8_UH_TX_CTRL_SPEC > ; # [doc = "endpoint 3 control;host transmittal endpoint control"]
pub mod r8_uep3_ctrl__r8_uh_tx_ctrl { # [doc = "Register `R8_UEP3_CTRL__R8_UH_TX_CTRL` reader"]
pub type R = crate :: R < R8_UEP3_CTRL__R8_UH_TX_CTRL_SPEC > ; # [doc = "Register `R8_UEP3_CTRL__R8_UH_TX_CTRL` writer"]
pub type W = crate :: W < R8_UEP3_CTRL__R8_UH_TX_CTRL_SPEC > ; # [doc = "Field `MASK_UEP_T_RES` reader - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MASK_UEP_T_RES_R = crate :: FieldReader ; # [doc = "Field `MASK_UEP_T_RES` writer - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MASK_UEP_T_RES_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MASK_UEP_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MASK_UEP_R_RES_R = crate :: FieldReader ; # [doc = "Field `MASK_UEP_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MASK_UEP_R_RES_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RB_UEP_AUTO_TOG` reader - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
pub type RB_UEP_AUTO_TOG_R = crate :: BitReader ; # [doc = "Field `RB_UEP_AUTO_TOG` writer - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
pub type RB_UEP_AUTO_TOG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP_T_TOG` reader - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RB_UEP_T_TOG_R = crate :: BitReader ; # [doc = "Field `RB_UEP_T_TOG` writer - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RB_UEP_T_TOG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP_R_TOG` reader - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RB_UEP_R_TOG_R = crate :: BitReader ; # [doc = "Field `RB_UEP_R_TOG` writer - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RB_UEP_R_TOG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
# [inline (always)]
pub fn mask_uep_t_res (& self) -> MASK_UEP_T_RES_R { MASK_UEP_T_RES_R :: new (self . bits & 3) } # [doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
# [inline (always)]
pub fn mask_uep_r_res (& self) -> MASK_UEP_R_RES_R { MASK_UEP_R_RES_R :: new ((self . bits >> 2) & 3) } # [doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
# [inline (always)]
pub fn rb_uep_auto_tog (& self) -> RB_UEP_AUTO_TOG_R { RB_UEP_AUTO_TOG_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
# [inline (always)]
pub fn rb_uep_t_tog (& self) -> RB_UEP_T_TOG_R { RB_UEP_T_TOG_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
# [inline (always)]
pub fn rb_uep_r_tog (& self) -> RB_UEP_R_TOG_R { RB_UEP_R_TOG_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
# [inline (always)]
# [must_use]
pub fn mask_uep_t_res (& mut self) -> MASK_UEP_T_RES_W < R8_UEP3_CTRL__R8_UH_TX_CTRL_SPEC > { MASK_UEP_T_RES_W :: new (self , 0) } # [doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
# [inline (always)]
# [must_use]
pub fn mask_uep_r_res (& mut self) -> MASK_UEP_R_RES_W < R8_UEP3_CTRL__R8_UH_TX_CTRL_SPEC > { MASK_UEP_R_RES_W :: new (self , 2) } # [doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
# [inline (always)]
# [must_use]
pub fn rb_uep_auto_tog (& mut self) -> RB_UEP_AUTO_TOG_W < R8_UEP3_CTRL__R8_UH_TX_CTRL_SPEC > { RB_UEP_AUTO_TOG_W :: new (self , 4) } # [doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
# [inline (always)]
# [must_use]
pub fn rb_uep_t_tog (& mut self) -> RB_UEP_T_TOG_W < R8_UEP3_CTRL__R8_UH_TX_CTRL_SPEC > { RB_UEP_T_TOG_W :: new (self , 6) } # [doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
# [inline (always)]
# [must_use]
pub fn rb_uep_r_tog (& mut self) -> RB_UEP_R_TOG_W < R8_UEP3_CTRL__R8_UH_TX_CTRL_SPEC > { RB_UEP_R_TOG_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 3 control;host transmittal endpoint control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep3_ctrl__r8_uh_tx_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep3_ctrl__r8_uh_tx_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_UEP3_CTRL__R8_UH_TX_CTRL_SPEC ; impl crate :: RegisterSpec for R8_UEP3_CTRL__R8_UH_TX_CTRL_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_uep3_ctrl__r8_uh_tx_ctrl::R`](R) reader structure"]
impl crate :: Readable for R8_UEP3_CTRL__R8_UH_TX_CTRL_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_uep3_ctrl__r8_uh_tx_ctrl::W`](W) writer structure"]
impl crate :: Writable for R8_UEP3_CTRL__R8_UH_TX_CTRL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_UEP3_CTRL__R8_UH_TX_CTRL to value 0"]
impl crate :: Resettable for R8_UEP3_CTRL__R8_UH_TX_CTRL_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_UEP4_T_LEN (rw) register accessor: endpoint 4 transmittal length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep4_t_len::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep4_t_len::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep4_t_len`]
module"]
pub type R8_UEP4_T_LEN = crate :: Reg < r8_uep4_t_len :: R8_UEP4_T_LEN_SPEC > ; # [doc = "endpoint 4 transmittal length"]
pub mod r8_uep4_t_len { # [doc = "Register `R8_UEP4_T_LEN` reader"]
pub type R = crate :: R < R8_UEP4_T_LEN_SPEC > ; # [doc = "Register `R8_UEP4_T_LEN` writer"]
pub type W = crate :: W < R8_UEP4_T_LEN_SPEC > ; impl core :: fmt :: Debug for R { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { write ! (f , "{}" , self . bits ()) } } impl core :: fmt :: Debug for crate :: generic :: Reg < R8_UEP4_T_LEN_SPEC > { fn fmt (& self , f : & mut core :: fmt :: Formatter < '_ >) -> core :: fmt :: Result { core :: fmt :: Debug :: fmt (& self . read () , f) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 4 transmittal length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep4_t_len::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep4_t_len::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_UEP4_T_LEN_SPEC ; impl crate :: RegisterSpec for R8_UEP4_T_LEN_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_uep4_t_len::R`](R) reader structure"]
impl crate :: Readable for R8_UEP4_T_LEN_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_uep4_t_len::W`](W) writer structure"]
impl crate :: Writable for R8_UEP4_T_LEN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_UEP4_T_LEN to value 0"]
impl crate :: Resettable for R8_UEP4_T_LEN_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_UEP4_CTRL (rw) register accessor: endpoint 4 control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep4_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep4_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_uep4_ctrl`]
module"]
pub type R8_UEP4_CTRL = crate :: Reg < r8_uep4_ctrl :: R8_UEP4_CTRL_SPEC > ; # [doc = "endpoint 4 control"]
pub mod r8_uep4_ctrl { # [doc = "Register `R8_UEP4_CTRL` reader"]
pub type R = crate :: R < R8_UEP4_CTRL_SPEC > ; # [doc = "Register `R8_UEP4_CTRL` writer"]
pub type W = crate :: W < R8_UEP4_CTRL_SPEC > ; # [doc = "Field `MASK_UEP_T_RES` reader - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MASK_UEP_T_RES_R = crate :: FieldReader ; # [doc = "Field `MASK_UEP_T_RES` writer - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
pub type MASK_UEP_T_RES_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `MASK_UEP_R_RES` reader - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MASK_UEP_R_RES_R = crate :: FieldReader ; # [doc = "Field `MASK_UEP_R_RES` writer - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
pub type MASK_UEP_R_RES_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RB_UEP_AUTO_TOG` reader - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
pub type RB_UEP_AUTO_TOG_R = crate :: BitReader ; # [doc = "Field `RB_UEP_AUTO_TOG` writer - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
pub type RB_UEP_AUTO_TOG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP_T_TOG` reader - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RB_UEP_T_TOG_R = crate :: BitReader ; # [doc = "Field `RB_UEP_T_TOG` writer - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
pub type RB_UEP_T_TOG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UEP_R_TOG` reader - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RB_UEP_R_TOG_R = crate :: BitReader ; # [doc = "Field `RB_UEP_R_TOG` writer - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
pub type RB_UEP_R_TOG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
# [inline (always)]
pub fn mask_uep_t_res (& self) -> MASK_UEP_T_RES_R { MASK_UEP_T_RES_R :: new (self . bits & 3) } # [doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
# [inline (always)]
pub fn mask_uep_r_res (& self) -> MASK_UEP_R_RES_R { MASK_UEP_R_RES_R :: new ((self . bits >> 2) & 3) } # [doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
# [inline (always)]
pub fn rb_uep_auto_tog (& self) -> RB_UEP_AUTO_TOG_R { RB_UEP_AUTO_TOG_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
# [inline (always)]
pub fn rb_uep_t_tog (& self) -> RB_UEP_T_TOG_R { RB_UEP_T_TOG_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
# [inline (always)]
pub fn rb_uep_r_tog (& self) -> RB_UEP_R_TOG_R { RB_UEP_R_TOG_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - bit mask of handshake response type for USB endpoint X transmittal (IN)"]
# [inline (always)]
# [must_use]
pub fn mask_uep_t_res (& mut self) -> MASK_UEP_T_RES_W < R8_UEP4_CTRL_SPEC > { MASK_UEP_T_RES_W :: new (self , 0) } # [doc = "Bits 2:3 - bit mask of handshake response type for USB endpoint X receiving (OUT)"]
# [inline (always)]
# [must_use]
pub fn mask_uep_r_res (& mut self) -> MASK_UEP_R_RES_W < R8_UEP4_CTRL_SPEC > { MASK_UEP_R_RES_W :: new (self , 2) } # [doc = "Bit 4 - enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle"]
# [inline (always)]
# [must_use]
pub fn rb_uep_auto_tog (& mut self) -> RB_UEP_AUTO_TOG_W < R8_UEP4_CTRL_SPEC > { RB_UEP_AUTO_TOG_W :: new (self , 4) } # [doc = "Bit 6 - prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1"]
# [inline (always)]
# [must_use]
pub fn rb_uep_t_tog (& mut self) -> RB_UEP_T_TOG_W < R8_UEP4_CTRL_SPEC > { RB_UEP_T_TOG_W :: new (self , 6) } # [doc = "Bit 7 - expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1"]
# [inline (always)]
# [must_use]
pub fn rb_uep_r_tog (& mut self) -> RB_UEP_R_TOG_W < R8_UEP4_CTRL_SPEC > { RB_UEP_R_TOG_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 4 control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_uep4_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_uep4_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_UEP4_CTRL_SPEC ; impl crate :: RegisterSpec for R8_UEP4_CTRL_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_uep4_ctrl::R`](R) reader structure"]
impl crate :: Readable for R8_UEP4_CTRL_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_uep4_ctrl::W`](W) writer structure"]
impl crate :: Writable for R8_UEP4_CTRL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_UEP4_CTRL to value 0"]
impl crate :: Resettable for R8_UEP4_CTRL_SPEC { const RESET_VALUE : u8 = 0 ; } } # [doc = "R8_USB_TYPE_C_CTRL (rw) register accessor: USB type-C control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_type_c_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_usb_type_c_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r8_usb_type_c_ctrl`]
module"]
pub type R8_USB_TYPE_C_CTRL = crate :: Reg < r8_usb_type_c_ctrl :: R8_USB_TYPE_C_CTRL_SPEC > ; # [doc = "USB type-C control"]
pub mod r8_usb_type_c_ctrl { # [doc = "Register `R8_USB_TYPE_C_CTRL` reader"]
pub type R = crate :: R < R8_USB_TYPE_C_CTRL_SPEC > ; # [doc = "Register `R8_USB_TYPE_C_CTRL` writer"]
pub type W = crate :: W < R8_USB_TYPE_C_CTRL_SPEC > ; # [doc = "Field `RB_UCC1_PU_EN` reader - USB CC1 pullup resistance control"]
pub type RB_UCC1_PU_EN_R = crate :: FieldReader ; # [doc = "Field `RB_UCC1_PU_EN` writer - USB CC1 pullup resistance control"]
pub type RB_UCC1_PU_EN_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RB_UCC1_PD_EN` reader - USB CC1 5.1K pulldown resistance: 0=disable, 1=enable pulldown"]
pub type RB_UCC1_PD_EN_R = crate :: BitReader ; # [doc = "Field `RB_UCC1_PD_EN` writer - USB CC1 5.1K pulldown resistance: 0=disable, 1=enable pulldown"]
pub type RB_UCC1_PD_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_VBUS_PD_EN` reader - USB VBUS 10K pulldown resistance: 0=disable, 1=enable pullup"]
pub type RB_VBUS_PD_EN_R = crate :: BitReader ; # [doc = "Field `RB_VBUS_PD_EN` writer - USB VBUS 10K pulldown resistance: 0=disable, 1=enable pullup"]
pub type RB_VBUS_PD_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UCC2_PU_EN` reader - USB CC2 pullup resistance control"]
pub type RB_UCC2_PU_EN_R = crate :: FieldReader ; # [doc = "Field `RB_UCC2_PU_EN` writer - USB CC2 pullup resistance control"]
pub type RB_UCC2_PU_EN_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `RB_UCC2_PD_EN` reader - USB CC2 5.1K pulldown resistance: 0=disable, 1=enable pulldown"]
pub type RB_UCC2_PD_EN_R = crate :: BitReader ; # [doc = "Field `RB_UCC2_PD_EN` writer - USB CC2 5.1K pulldown resistance: 0=disable, 1=enable pulldown"]
pub type RB_UCC2_PD_EN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RB_UTCC_GP_BIT` reader - USB general purpose bit"]
pub type RB_UTCC_GP_BIT_R = crate :: BitReader ; # [doc = "Field `RB_UTCC_GP_BIT` writer - USB general purpose bit"]
pub type RB_UTCC_GP_BIT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:1 - USB CC1 pullup resistance control"]
# [inline (always)]
pub fn rb_ucc1_pu_en (& self) -> RB_UCC1_PU_EN_R { RB_UCC1_PU_EN_R :: new (self . bits & 3) } # [doc = "Bit 2 - USB CC1 5.1K pulldown resistance: 0=disable, 1=enable pulldown"]
# [inline (always)]
pub fn rb_ucc1_pd_en (& self) -> RB_UCC1_PD_EN_R { RB_UCC1_PD_EN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - USB VBUS 10K pulldown resistance: 0=disable, 1=enable pullup"]
# [inline (always)]
pub fn rb_vbus_pd_en (& self) -> RB_VBUS_PD_EN_R { RB_VBUS_PD_EN_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - USB CC2 pullup resistance control"]
# [inline (always)]
pub fn rb_ucc2_pu_en (& self) -> RB_UCC2_PU_EN_R { RB_UCC2_PU_EN_R :: new ((self . bits >> 4) & 3) } # [doc = "Bit 6 - USB CC2 5.1K pulldown resistance: 0=disable, 1=enable pulldown"]
# [inline (always)]
pub fn rb_ucc2_pd_en (& self) -> RB_UCC2_PD_EN_R { RB_UCC2_PD_EN_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - USB general purpose bit"]
# [inline (always)]
pub fn rb_utcc_gp_bit (& self) -> RB_UTCC_GP_BIT_R { RB_UTCC_GP_BIT_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - USB CC1 pullup resistance control"]
# [inline (always)]
# [must_use]
pub fn rb_ucc1_pu_en (& mut self) -> RB_UCC1_PU_EN_W < R8_USB_TYPE_C_CTRL_SPEC > { RB_UCC1_PU_EN_W :: new (self , 0) } # [doc = "Bit 2 - USB CC1 5.1K pulldown resistance: 0=disable, 1=enable pulldown"]
# [inline (always)]
# [must_use]
pub fn rb_ucc1_pd_en (& mut self) -> RB_UCC1_PD_EN_W < R8_USB_TYPE_C_CTRL_SPEC > { RB_UCC1_PD_EN_W :: new (self , 2) } # [doc = "Bit 3 - USB VBUS 10K pulldown resistance: 0=disable, 1=enable pullup"]
# [inline (always)]
# [must_use]
pub fn rb_vbus_pd_en (& mut self) -> RB_VBUS_PD_EN_W < R8_USB_TYPE_C_CTRL_SPEC > { RB_VBUS_PD_EN_W :: new (self , 3) } # [doc = "Bits 4:5 - USB CC2 pullup resistance control"]
# [inline (always)]
# [must_use]
pub fn rb_ucc2_pu_en (& mut self) -> RB_UCC2_PU_EN_W < R8_USB_TYPE_C_CTRL_SPEC > { RB_UCC2_PU_EN_W :: new (self , 4) } # [doc = "Bit 6 - USB CC2 5.1K pulldown resistance: 0=disable, 1=enable pulldown"]
# [inline (always)]
# [must_use]
pub fn rb_ucc2_pd_en (& mut self) -> RB_UCC2_PD_EN_W < R8_USB_TYPE_C_CTRL_SPEC > { RB_UCC2_PD_EN_W :: new (self , 6) } # [doc = "Bit 7 - USB general purpose bit"]
# [inline (always)]
# [must_use]
pub fn rb_utcc_gp_bit (& mut self) -> RB_UTCC_GP_BIT_W < R8_USB_TYPE_C_CTRL_SPEC > { RB_UTCC_GP_BIT_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u8) -> & mut Self { self . bits = bits ; self } } # [doc = "USB type-C control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r8_usb_type_c_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r8_usb_type_c_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct R8_USB_TYPE_C_CTRL_SPEC ; impl crate :: RegisterSpec for R8_USB_TYPE_C_CTRL_SPEC { type Ux = u8 ; } # [doc = "`read()` method returns [`r8_usb_type_c_ctrl::R`](R) reader structure"]
impl crate :: Readable for R8_USB_TYPE_C_CTRL_SPEC { } # [doc = "`write(|w| ..)` method takes [`r8_usb_type_c_ctrl::W`](W) writer structure"]
impl crate :: Writable for R8_USB_TYPE_C_CTRL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u8 = 0 ; } # [doc = "`reset()` method sets R8_USB_TYPE_C_CTRL to value 0"]
impl crate :: Resettable for R8_USB_TYPE_C_CTRL_SPEC { const RESET_VALUE : u8 = 0 ; } } } # [doc = "CRC calculation unit"]
pub struct CRC { _marker : PhantomData < * const () > } unsafe impl Send for CRC { } impl CRC { # [doc = r"Pointer to the register block"]
pub const PTR : * const crc :: RegisterBlock = 0x4002_3000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const crc :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for CRC { type Target = crc :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for CRC { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("CRC") . finish () } } # [doc = "CRC calculation unit"]
pub mod crc { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { datar : DATAR , idatar : IDATAR , ctlr : CTLR , } impl RegisterBlock { # [doc = "0x00 - Data register"]
# [inline (always)]
pub const fn datar (& self) -> & DATAR { & self . datar } # [doc = "0x04 - Independent Data register"]
# [inline (always)]
pub const fn idatar (& self) -> & IDATAR { & self . idatar } # [doc = "0x08 - Control register"]
# [inline (always)]
pub const fn ctlr (& self) -> & CTLR { & self . ctlr } } # [doc = "DATAR (rw) register accessor: Data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datar`]
module"]
pub type DATAR = crate :: Reg < datar :: DATAR_SPEC > ; # [doc = "Data register"]
pub mod datar { # [doc = "Register `DATAR` reader"]
pub type R = crate :: R < DATAR_SPEC > ; # [doc = "Register `DATAR` writer"]
pub type W = crate :: W < DATAR_SPEC > ; # [doc = "Field `DATA` reader - Data Register"]
pub type DATA_R = crate :: FieldReader < u32 > ; # [doc = "Field `DATA` writer - Data Register"]
pub type DATA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl R { # [doc = "Bits 0:31 - Data Register"]
# [inline (always)]
pub fn data (& self) -> DATA_R { DATA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Data Register"]
# [inline (always)]
# [must_use]
pub fn data (& mut self) -> DATA_W < DATAR_SPEC > { DATA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATAR_SPEC ; impl crate :: RegisterSpec for DATAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`datar::R`](R) reader structure"]
impl crate :: Readable for DATAR_SPEC { } # [doc = "`write(|w| ..)` method takes [`datar::W`](W) writer structure"]
impl crate :: Writable for DATAR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets DATAR to value 0xffff_ffff"]
impl crate :: Resettable for DATAR_SPEC { const RESET_VALUE : u32 = 0xffff_ffff ; } } # [doc = "IDATAR (rw) register accessor: Independent Data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idatar::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idatar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idatar`]
module"]
pub type IDATAR = crate :: Reg < idatar :: IDATAR_SPEC > ; # [doc = "Independent Data register"]
pub mod idatar { # [doc = "Register `IDATAR` reader"]
pub type R = crate :: R < IDATAR_SPEC > ; # [doc = "Register `IDATAR` writer"]
pub type W = crate :: W < IDATAR_SPEC > ; # [doc = "Field `IDATA` reader - Independent Data register"]
pub type IDATA_R = crate :: FieldReader ; # [doc = "Field `IDATA` writer - Independent Data register"]
pub type IDATA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - Independent Data register"]
# [inline (always)]
pub fn idata (& self) -> IDATA_R { IDATA_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Independent Data register"]
# [inline (always)]
# [must_use]
pub fn idata (& mut self) -> IDATA_W < IDATAR_SPEC > { IDATA_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Independent Data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idatar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idatar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IDATAR_SPEC ; impl crate :: RegisterSpec for IDATAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`idatar::R`](R) reader structure"]
impl crate :: Readable for IDATAR_SPEC { } # [doc = "`write(|w| ..)` method takes [`idatar::W`](W) writer structure"]
impl crate :: Writable for IDATAR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IDATAR to value 0"]
impl crate :: Resettable for IDATAR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTLR (w) register accessor: Control register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr`]
module"]
pub type CTLR = crate :: Reg < ctlr :: CTLR_SPEC > ; # [doc = "Control register"]
pub mod ctlr { # [doc = "Register `CTLR` writer"]
pub type W = crate :: W < CTLR_SPEC > ; # [doc = "Field `RST` writer - Reset bit"]
pub type RST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl W { # [doc = "Bit 0 - Reset bit"]
# [inline (always)]
# [must_use]
pub fn rst (& mut self) -> RST_W < CTLR_SPEC > { RST_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR_SPEC ; impl crate :: RegisterSpec for CTLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`ctlr::W`](W) writer structure"]
impl crate :: Writable for CTLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR to value 0"]
impl crate :: Resettable for CTLR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "FLASH"]
pub struct FLASH { _marker : PhantomData < * const () > } unsafe impl Send for FLASH { } impl FLASH { # [doc = r"Pointer to the register block"]
pub const PTR : * const flash :: RegisterBlock = 0x4002_2000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const flash :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for FLASH { type Target = flash :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for FLASH { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("FLASH") . finish () } } # [doc = "FLASH"]
pub mod flash { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { actlr : ACTLR , keyr : KEYR , obkeyr : OBKEYR , statr : STATR , ctlr : CTLR , addr : ADDR , _reserved6 : [u8 ; 0x04]
, obr : OBR , wpr : WPR , modekeyr : MODEKEYR , } impl RegisterBlock { # [doc = "0x00 - Flash access control register"]
# [inline (always)]
pub const fn actlr (& self) -> & ACTLR { & self . actlr } # [doc = "0x04 - Flash key register"]
# [inline (always)]
pub const fn keyr (& self) -> & KEYR { & self . keyr } # [doc = "0x08 - Flash option key register"]
# [inline (always)]
pub const fn obkeyr (& self) -> & OBKEYR { & self . obkeyr } # [doc = "0x0c - Status register"]
# [inline (always)]
pub const fn statr (& self) -> & STATR { & self . statr } # [doc = "0x10 - Control register"]
# [inline (always)]
pub const fn ctlr (& self) -> & CTLR { & self . ctlr } # [doc = "0x14 - Flash address register"]
# [inline (always)]
pub const fn addr (& self) -> & ADDR { & self . addr } # [doc = "0x1c - Option byte register"]
# [inline (always)]
pub const fn obr (& self) -> & OBR { & self . obr } # [doc = "0x20 - Write protection register"]
# [inline (always)]
pub const fn wpr (& self) -> & WPR { & self . wpr } # [doc = "0x24 - Extension key register"]
# [inline (always)]
pub const fn modekeyr (& self) -> & MODEKEYR { & self . modekeyr } } # [doc = "ACTLR (rw) register accessor: Flash access control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`actlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`actlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@actlr`]
module"]
pub type ACTLR = crate :: Reg < actlr :: ACTLR_SPEC > ; # [doc = "Flash access control register"]
pub mod actlr { # [doc = "Register `ACTLR` reader"]
pub type R = crate :: R < ACTLR_SPEC > ; # [doc = "Register `ACTLR` writer"]
pub type W = crate :: W < ACTLR_SPEC > ; # [doc = "Field `LATENCY` reader - Latency"]
pub type LATENCY_R = crate :: FieldReader ; # [doc = "Field `LATENCY` writer - Latency"]
pub type LATENCY_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 3 > ; # [doc = "Field `PRFTBE` reader - Prefetch buffer enable"]
pub type PRFTBE_R = crate :: BitReader ; # [doc = "Field `PRFTBE` writer - Prefetch buffer enable"]
pub type PRFTBE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PRFTBS` reader - Prefetch buffer status"]
pub type PRFTBS_R = crate :: BitReader ; impl R { # [doc = "Bits 0:2 - Latency"]
# [inline (always)]
pub fn latency (& self) -> LATENCY_R { LATENCY_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 4 - Prefetch buffer enable"]
# [inline (always)]
pub fn prftbe (& self) -> PRFTBE_R { PRFTBE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Prefetch buffer status"]
# [inline (always)]
pub fn prftbs (& self) -> PRFTBS_R { PRFTBS_R :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - Latency"]
# [inline (always)]
# [must_use]
pub fn latency (& mut self) -> LATENCY_W < ACTLR_SPEC > { LATENCY_W :: new (self , 0) } # [doc = "Bit 4 - Prefetch buffer enable"]
# [inline (always)]
# [must_use]
pub fn prftbe (& mut self) -> PRFTBE_W < ACTLR_SPEC > { PRFTBE_W :: new (self , 4) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Flash access control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`actlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`actlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ACTLR_SPEC ; impl crate :: RegisterSpec for ACTLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`actlr::R`](R) reader structure"]
impl crate :: Readable for ACTLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`actlr::W`](W) writer structure"]
impl crate :: Writable for ACTLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ACTLR to value 0x30"]
impl crate :: Resettable for ACTLR_SPEC { const RESET_VALUE : u32 = 0x30 ; } } # [doc = "KEYR (w) register accessor: Flash key register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`keyr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyr`]
module"]
pub type KEYR = crate :: Reg < keyr :: KEYR_SPEC > ; # [doc = "Flash key register"]
pub mod keyr { # [doc = "Register `KEYR` writer"]
pub type W = crate :: W < KEYR_SPEC > ; # [doc = "Field `KEYR` writer - FPEC key"]
pub type KEYR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl W { # [doc = "Bits 0:31 - FPEC key"]
# [inline (always)]
# [must_use]
pub fn keyr (& mut self) -> KEYR_W < KEYR_SPEC > { KEYR_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Flash key register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`keyr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct KEYR_SPEC ; impl crate :: RegisterSpec for KEYR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`keyr::W`](W) writer structure"]
impl crate :: Writable for KEYR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets KEYR to value 0"]
impl crate :: Resettable for KEYR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "OBKEYR (w) register accessor: Flash option key register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`obkeyr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@obkeyr`]
module"]
pub type OBKEYR = crate :: Reg < obkeyr :: OBKEYR_SPEC > ; # [doc = "Flash option key register"]
pub mod obkeyr { # [doc = "Register `OBKEYR` writer"]
pub type W = crate :: W < OBKEYR_SPEC > ; # [doc = "Field `OBKEYR` writer - Option byte key"]
pub type OBKEYR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl W { # [doc = "Bits 0:31 - Option byte key"]
# [inline (always)]
# [must_use]
pub fn obkeyr (& mut self) -> OBKEYR_W < OBKEYR_SPEC > { OBKEYR_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Flash option key register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`obkeyr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OBKEYR_SPEC ; impl crate :: RegisterSpec for OBKEYR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`obkeyr::W`](W) writer structure"]
impl crate :: Writable for OBKEYR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets OBKEYR to value 0"]
impl crate :: Resettable for OBKEYR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "STATR (rw) register accessor: Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`statr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@statr`]
module"]
pub type STATR = crate :: Reg < statr :: STATR_SPEC > ; # [doc = "Status register"]
pub mod statr { # [doc = "Register `STATR` reader"]
pub type R = crate :: R < STATR_SPEC > ; # [doc = "Register `STATR` writer"]
pub type W = crate :: W < STATR_SPEC > ; # [doc = "Field `BSY` reader - Busy"]
pub type BSY_R = crate :: BitReader ; # [doc = "Field `PGERR` reader - Programming error"]
pub type PGERR_R = crate :: BitReader ; # [doc = "Field `PGERR` writer - Programming error"]
pub type PGERR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WRPRTERR` reader - Write protection error"]
pub type WRPRTERR_R = crate :: BitReader ; # [doc = "Field `WRPRTERR` writer - Write protection error"]
pub type WRPRTERR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOP` reader - End of operation"]
pub type EOP_R = crate :: BitReader ; # [doc = "Field `EOP` writer - End of operation"]
pub type EOP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Busy"]
# [inline (always)]
pub fn bsy (& self) -> BSY_R { BSY_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - Programming error"]
# [inline (always)]
pub fn pgerr (& self) -> PGERR_R { PGERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 4 - Write protection error"]
# [inline (always)]
pub fn wrprterr (& self) -> WRPRTERR_R { WRPRTERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - End of operation"]
# [inline (always)]
pub fn eop (& self) -> EOP_R { EOP_R :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bit 2 - Programming error"]
# [inline (always)]
# [must_use]
pub fn pgerr (& mut self) -> PGERR_W < STATR_SPEC > { PGERR_W :: new (self , 2) } # [doc = "Bit 4 - Write protection error"]
# [inline (always)]
# [must_use]
pub fn wrprterr (& mut self) -> WRPRTERR_W < STATR_SPEC > { WRPRTERR_W :: new (self , 4) } # [doc = "Bit 5 - End of operation"]
# [inline (always)]
# [must_use]
pub fn eop (& mut self) -> EOP_W < STATR_SPEC > { EOP_W :: new (self , 5) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`statr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STATR_SPEC ; impl crate :: RegisterSpec for STATR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`statr::R`](R) reader structure"]
impl crate :: Readable for STATR_SPEC { } # [doc = "`write(|w| ..)` method takes [`statr::W`](W) writer structure"]
impl crate :: Writable for STATR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets STATR to value 0"]
impl crate :: Resettable for STATR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CTLR (rw) register accessor: Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlr`]
module"]
pub type CTLR = crate :: Reg < ctlr :: CTLR_SPEC > ; # [doc = "Control register"]
pub mod ctlr { # [doc = "Register `CTLR` reader"]
pub type R = crate :: R < CTLR_SPEC > ; # [doc = "Register `CTLR` writer"]
pub type W = crate :: W < CTLR_SPEC > ; # [doc = "Field `PG` reader - Programming"]
pub type PG_R = crate :: BitReader ; # [doc = "Field `PG` writer - Programming"]
pub type PG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PER` reader - Page Erase"]
pub type PER_R = crate :: BitReader ; # [doc = "Field `PER` writer - Page Erase"]
pub type PER_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `MER` reader - Mass Erase"]
pub type MER_R = crate :: BitReader ; # [doc = "Field `MER` writer - Mass Erase"]
pub type MER_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OBPG` reader - Option byte programming"]
pub type OBPG_R = crate :: BitReader ; # [doc = "Field `OBPG` writer - Option byte programming"]
pub type OBPG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OBER` reader - Option byte erase"]
pub type OBER_R = crate :: BitReader ; # [doc = "Field `OBER` writer - Option byte erase"]
pub type OBER_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STRT` reader - Start"]
pub type STRT_R = crate :: BitReader ; # [doc = "Field `STRT` writer - Start"]
pub type STRT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LOCK` reader - Lock"]
pub type LOCK_R = crate :: BitReader ; # [doc = "Field `LOCK` writer - Lock"]
pub type LOCK_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `OBWRE` reader - Option bytes write enable"]
pub type OBWRE_R = crate :: BitReader ; # [doc = "Field `OBWRE` writer - Option bytes write enable"]
pub type OBWRE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERRIE` reader - Error interrupt enable"]
pub type ERRIE_R = crate :: BitReader ; # [doc = "Field `ERRIE` writer - Error interrupt enable"]
pub type ERRIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EOPIE` reader - End of operation interrupt enable"]
pub type EOPIE_R = crate :: BitReader ; # [doc = "Field `EOPIE` writer - End of operation interrupt enable"]
pub type EOPIE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FLOCK` reader - FAST programming lock"]
pub type FLOCK_R = crate :: BitReader ; # [doc = "Field `FLOCK` writer - FAST programming lock"]
pub type FLOCK_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FTPG` reader - execute fast programming"]
pub type FTPG_R = crate :: BitReader ; # [doc = "Field `FTPG` writer - execute fast programming"]
pub type FTPG_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FTER` reader - execute fast 128byte erase"]
pub type FTER_R = crate :: BitReader ; # [doc = "Field `FTER` writer - execute fast 128byte erase"]
pub type FTER_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BUFLOAD` reader - execute data load inner buffer"]
pub type BUFLOAD_R = crate :: BitReader ; # [doc = "Field `BUFLOAD` writer - execute data load inner buffer"]
pub type BUFLOAD_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `BUFRST` reader - execute inner buffer reset"]
pub type BUFRST_R = crate :: BitReader ; # [doc = "Field `BUFRST` writer - execute inner buffer reset"]
pub type BUFRST_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Programming"]
# [inline (always)]
pub fn pg (& self) -> PG_R { PG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Page Erase"]
# [inline (always)]
pub fn per (& self) -> PER_R { PER_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Mass Erase"]
# [inline (always)]
pub fn mer (& self) -> MER_R { MER_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 4 - Option byte programming"]
# [inline (always)]
pub fn obpg (& self) -> OBPG_R { OBPG_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Option byte erase"]
# [inline (always)]
pub fn ober (& self) -> OBER_R { OBER_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Start"]
# [inline (always)]
pub fn strt (& self) -> STRT_R { STRT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Lock"]
# [inline (always)]
pub fn lock (& self) -> LOCK_R { LOCK_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 9 - Option bytes write enable"]
# [inline (always)]
pub fn obwre (& self) -> OBWRE_R { OBWRE_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Error interrupt enable"]
# [inline (always)]
pub fn errie (& self) -> ERRIE_R { ERRIE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 12 - End of operation interrupt enable"]
# [inline (always)]
pub fn eopie (& self) -> EOPIE_R { EOPIE_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 15 - FAST programming lock"]
# [inline (always)]
pub fn flock (& self) -> FLOCK_R { FLOCK_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - execute fast programming"]
# [inline (always)]
pub fn ftpg (& self) -> FTPG_R { FTPG_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - execute fast 128byte erase"]
# [inline (always)]
pub fn fter (& self) -> FTER_R { FTER_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - execute data load inner buffer"]
# [inline (always)]
pub fn bufload (& self) -> BUFLOAD_R { BUFLOAD_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - execute inner buffer reset"]
# [inline (always)]
pub fn bufrst (& self) -> BUFRST_R { BUFRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - Programming"]
# [inline (always)]
# [must_use]
pub fn pg (& mut self) -> PG_W < CTLR_SPEC > { PG_W :: new (self , 0) } # [doc = "Bit 1 - Page Erase"]
# [inline (always)]
# [must_use]
pub fn per (& mut self) -> PER_W < CTLR_SPEC > { PER_W :: new (self , 1) } # [doc = "Bit 2 - Mass Erase"]
# [inline (always)]
# [must_use]
pub fn mer (& mut self) -> MER_W < CTLR_SPEC > { MER_W :: new (self , 2) } # [doc = "Bit 4 - Option byte programming"]
# [inline (always)]
# [must_use]
pub fn obpg (& mut self) -> OBPG_W < CTLR_SPEC > { OBPG_W :: new (self , 4) } # [doc = "Bit 5 - Option byte erase"]
# [inline (always)]
# [must_use]
pub fn ober (& mut self) -> OBER_W < CTLR_SPEC > { OBER_W :: new (self , 5) } # [doc = "Bit 6 - Start"]
# [inline (always)]
# [must_use]
pub fn strt (& mut self) -> STRT_W < CTLR_SPEC > { STRT_W :: new (self , 6) } # [doc = "Bit 7 - Lock"]
# [inline (always)]
# [must_use]
pub fn lock (& mut self) -> LOCK_W < CTLR_SPEC > { LOCK_W :: new (self , 7) } # [doc = "Bit 9 - Option bytes write enable"]
# [inline (always)]
# [must_use]
pub fn obwre (& mut self) -> OBWRE_W < CTLR_SPEC > { OBWRE_W :: new (self , 9) } # [doc = "Bit 10 - Error interrupt enable"]
# [inline (always)]
# [must_use]
pub fn errie (& mut self) -> ERRIE_W < CTLR_SPEC > { ERRIE_W :: new (self , 10) } # [doc = "Bit 12 - End of operation interrupt enable"]
# [inline (always)]
# [must_use]
pub fn eopie (& mut self) -> EOPIE_W < CTLR_SPEC > { EOPIE_W :: new (self , 12) } # [doc = "Bit 15 - FAST programming lock"]
# [inline (always)]
# [must_use]
pub fn flock (& mut self) -> FLOCK_W < CTLR_SPEC > { FLOCK_W :: new (self , 15) } # [doc = "Bit 16 - execute fast programming"]
# [inline (always)]
# [must_use]
pub fn ftpg (& mut self) -> FTPG_W < CTLR_SPEC > { FTPG_W :: new (self , 16) } # [doc = "Bit 17 - execute fast 128byte erase"]
# [inline (always)]
# [must_use]
pub fn fter (& mut self) -> FTER_W < CTLR_SPEC > { FTER_W :: new (self , 17) } # [doc = "Bit 18 - execute data load inner buffer"]
# [inline (always)]
# [must_use]
pub fn bufload (& mut self) -> BUFLOAD_W < CTLR_SPEC > { BUFLOAD_W :: new (self , 18) } # [doc = "Bit 19 - execute inner buffer reset"]
# [inline (always)]
# [must_use]
pub fn bufrst (& mut self) -> BUFRST_W < CTLR_SPEC > { BUFRST_W :: new (self , 19) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTLR_SPEC ; impl crate :: RegisterSpec for CTLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctlr::R`](R) reader structure"]
impl crate :: Readable for CTLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctlr::W`](W) writer structure"]
impl crate :: Writable for CTLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CTLR to value 0x80"]
impl crate :: Resettable for CTLR_SPEC { const RESET_VALUE : u32 = 0x80 ; } } # [doc = "ADDR (w) register accessor: Flash address register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`]
module"]
pub type ADDR = crate :: Reg < addr :: ADDR_SPEC > ; # [doc = "Flash address register"]
pub mod addr { # [doc = "Register `ADDR` writer"]
pub type W = crate :: W < ADDR_SPEC > ; # [doc = "Field `FAR` writer - Flash Address"]
pub type FAR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl W { # [doc = "Bits 0:31 - Flash Address"]
# [inline (always)]
# [must_use]
pub fn far (& mut self) -> FAR_W < ADDR_SPEC > { FAR_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Flash address register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ADDR_SPEC ; impl crate :: RegisterSpec for ADDR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`addr::W`](W) writer structure"]
impl crate :: Writable for ADDR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ADDR to value 0"]
impl crate :: Resettable for ADDR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "OBR (r) register accessor: Option byte register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`obr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@obr`]
module"]
pub type OBR = crate :: Reg < obr :: OBR_SPEC > ; # [doc = "Option byte register"]
pub mod obr { # [doc = "Register `OBR` reader"]
pub type R = crate :: R < OBR_SPEC > ; # [doc = "Field `OPTERR` reader - Option byte error"]
pub type OPTERR_R = crate :: BitReader ; # [doc = "Field `RDPRT` reader - Read protection"]
pub type RDPRT_R = crate :: BitReader ; # [doc = "Field `IWDG_SW` reader - IWDG_SW"]
pub type IWDG_SW_R = crate :: BitReader ; # [doc = "Field `nRST_STOP` reader - nRST_STOP"]
pub type N_RST_STOP_R = crate :: BitReader ; # [doc = "Field `nRST_STDBY` reader - nRST_STDBY"]
pub type N_RST_STDBY_R = crate :: BitReader ; # [doc = "Field `USBD_MODE` reader - USBD compatible speed mode configure"]
pub type USBD_MODE_R = crate :: BitReader ; # [doc = "Field `USBD_PU` reader - USBD compatible inner pull up resistance configure"]
pub type USBD_PU_R = crate :: BitReader ; # [doc = "Field `POR_CTR` reader - Power on reset time"]
pub type POR_CTR_R = crate :: BitReader ; # [doc = "Field `Data0` reader - Data0"]
pub type DATA0_R = crate :: FieldReader ; # [doc = "Field `Data1` reader - Data1"]
pub type DATA1_R = crate :: FieldReader ; impl R { # [doc = "Bit 0 - Option byte error"]
# [inline (always)]
pub fn opterr (& self) -> OPTERR_R { OPTERR_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Read protection"]
# [inline (always)]
pub fn rdprt (& self) -> RDPRT_R { RDPRT_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - IWDG_SW"]
# [inline (always)]
pub fn iwdg_sw (& self) -> IWDG_SW_R { IWDG_SW_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - nRST_STOP"]
# [inline (always)]
pub fn n_rst_stop (& self) -> N_RST_STOP_R { N_RST_STOP_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - nRST_STDBY"]
# [inline (always)]
pub fn n_rst_stdby (& self) -> N_RST_STDBY_R { N_RST_STDBY_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - USBD compatible speed mode configure"]
# [inline (always)]
pub fn usbd_mode (& self) -> USBD_MODE_R { USBD_MODE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - USBD compatible inner pull up resistance configure"]
# [inline (always)]
pub fn usbd_pu (& self) -> USBD_PU_R { USBD_PU_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Power on reset time"]
# [inline (always)]
pub fn por_ctr (& self) -> POR_CTR_R { POR_CTR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 10:17 - Data0"]
# [inline (always)]
pub fn data0 (& self) -> DATA0_R { DATA0_R :: new (((self . bits >> 10) & 0xff) as u8) } # [doc = "Bits 18:25 - Data1"]
# [inline (always)]
pub fn data1 (& self) -> DATA1_R { DATA1_R :: new (((self . bits >> 18) & 0xff) as u8) } } # [doc = "Option byte register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`obr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OBR_SPEC ; impl crate :: RegisterSpec for OBR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`obr::R`](R) reader structure"]
impl crate :: Readable for OBR_SPEC { } # [doc = "`reset()` method sets OBR to value 0x03ff_fffc"]
impl crate :: Resettable for OBR_SPEC { const RESET_VALUE : u32 = 0x03ff_fffc ; } } # [doc = "WPR (r) register accessor: Write protection register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wpr`]
module"]
pub type WPR = crate :: Reg < wpr :: WPR_SPEC > ; # [doc = "Write protection register"]
pub mod wpr { # [doc = "Register `WPR` reader"]
pub type R = crate :: R < WPR_SPEC > ; # [doc = "Field `WRP` reader - Write protect"]
pub type WRP_R = crate :: FieldReader < u32 > ; impl R { # [doc = "Bits 0:31 - Write protect"]
# [inline (always)]
pub fn wrp (& self) -> WRP_R { WRP_R :: new (self . bits) } } # [doc = "Write protection register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WPR_SPEC ; impl crate :: RegisterSpec for WPR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wpr::R`](R) reader structure"]
impl crate :: Readable for WPR_SPEC { } # [doc = "`reset()` method sets WPR to value 0xffff_ffff"]
impl crate :: Resettable for WPR_SPEC { const RESET_VALUE : u32 = 0xffff_ffff ; } } # [doc = "MODEKEYR (w) register accessor: Extension key register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`modekeyr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modekeyr`]
module"]
pub type MODEKEYR = crate :: Reg < modekeyr :: MODEKEYR_SPEC > ; # [doc = "Extension key register"]
pub mod modekeyr { # [doc = "Register `MODEKEYR` writer"]
pub type W = crate :: W < MODEKEYR_SPEC > ; # [doc = "Field `MODEKEYR` writer - high speed write /erase mode ENABLE"]
pub type MODEKEYR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 32 , u32 > ; impl W { # [doc = "Bits 0:31 - high speed write /erase mode ENABLE"]
# [inline (always)]
# [must_use]
pub fn modekeyr (& mut self) -> MODEKEYR_W < MODEKEYR_SPEC > { MODEKEYR_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Extension key register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`modekeyr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MODEKEYR_SPEC ; impl crate :: RegisterSpec for MODEKEYR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`modekeyr::W`](W) writer structure"]
impl crate :: Writable for MODEKEYR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets MODEKEYR to value 0"]
impl crate :: Resettable for MODEKEYR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Programmable Fast Interrupt Controller"]
pub struct PFIC { _marker : PhantomData < * const () > } unsafe impl Send for PFIC { } impl PFIC { # [doc = r"Pointer to the register block"]
pub const PTR : * const pfic :: RegisterBlock = 0xe000_e000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const pfic :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for PFIC { type Target = pfic :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for PFIC { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("PFIC") . finish () } } # [doc = "Programmable Fast Interrupt Controller"]
pub mod pfic { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { isr1 : ISR1 , isr2 : ISR2 , _reserved2 : [u8 ; 0x18]
, ipr1 : IPR1 , ipr2 : IPR2 , _reserved4 : [u8 ; 0x18]
, ithresdr : ITHRESDR , fibaddrr : FIBADDRR , cfgr : CFGR , gisr : GISR , _reserved8 : [u8 ; 0x10]
, fifoaddrr0 : FIFOADDRR0 , fifoaddrr1 : FIFOADDRR1 , fifoaddrr2 : FIFOADDRR2 , fifoaddrr3 : FIFOADDRR3 , _reserved12 : [u8 ; 0x90]
, ienr1 : IENR1 , ienr2 : IENR2 , _reserved14 : [u8 ; 0x78]
, irer1 : IRER1 , irer2 : IRER2 , _reserved16 : [u8 ; 0x78]
, ipsr1 : IPSR1 , ipsr2 : IPSR2 , _reserved18 : [u8 ; 0x78]
, iprr1 : IPRR1 , iprr2 : IPRR2 , _reserved20 : [u8 ; 0x78]
, iactr1 : IACTR1 , iactr2 : IACTR2 , _reserved22 : [u8 ; 0x0a08]
, sctlr : SCTLR , _reserved23 : [u8 ; 0x02ec]
, stk_ctlr : STK_CTLR , } impl RegisterBlock { # [doc = "0x00 - Interrupt Status Register"]
# [inline (always)]
pub const fn isr1 (& self) -> & ISR1 { & self . isr1 } # [doc = "0x04 - Interrupt Status Register"]
# [inline (always)]
pub const fn isr2 (& self) -> & ISR2 { & self . isr2 } # [doc = "0x20 - Interrupt Pending Register"]
# [inline (always)]
pub const fn ipr1 (& self) -> & IPR1 { & self . ipr1 } # [doc = "0x24 - Interrupt Pending Register"]
# [inline (always)]
pub const fn ipr2 (& self) -> & IPR2 { & self . ipr2 } # [doc = "0x40 - Interrupt Priority Register"]
# [inline (always)]
pub const fn ithresdr (& self) -> & ITHRESDR { & self . ithresdr } # [doc = "0x44 - Interrupt Fast Address Register"]
# [inline (always)]
pub const fn fibaddrr (& self) -> & FIBADDRR { & self . fibaddrr } # [doc = "0x48 - Interrupt Config Register"]
# [inline (always)]
pub const fn cfgr (& self) -> & CFGR { & self . cfgr } # [doc = "0x4c - Interrupt Global Register"]
# [inline (always)]
pub const fn gisr (& self) -> & GISR { & self . gisr } # [doc = "0x60 - Interrupt 0 address Register"]
# [inline (always)]
pub const fn fifoaddrr0 (& self) -> & FIFOADDRR0 { & self . fifoaddrr0 } # [doc = "0x64 - Interrupt 1 address Register"]
# [inline (always)]
pub const fn fifoaddrr1 (& self) -> & FIFOADDRR1 { & self . fifoaddrr1 } # [doc = "0x68 - Interrupt 2 address Register"]
# [inline (always)]
pub const fn fifoaddrr2 (& self) -> & FIFOADDRR2 { & self . fifoaddrr2 } # [doc = "0x6c - Interrupt 3 address Register"]
# [inline (always)]
pub const fn fifoaddrr3 (& self) -> & FIFOADDRR3 { & self . fifoaddrr3 } # [doc = "0x100 - Interrupt Setting Register"]
# [inline (always)]
pub const fn ienr1 (& self) -> & IENR1 { & self . ienr1 } # [doc = "0x104 - Interrupt Setting Register"]
# [inline (always)]
pub const fn ienr2 (& self) -> & IENR2 { & self . ienr2 } # [doc = "0x180 - Interrupt Clear Register"]
# [inline (always)]
pub const fn irer1 (& self) -> & IRER1 { & self . irer1 } # [doc = "0x184 - Interrupt Clear Register"]
# [inline (always)]
pub const fn irer2 (& self) -> & IRER2 { & self . irer2 } # [doc = "0x200 - Interrupt Pending Register"]
# [inline (always)]
pub const fn ipsr1 (& self) -> & IPSR1 { & self . ipsr1 } # [doc = "0x204 - Interrupt Pending Register"]
# [inline (always)]
pub const fn ipsr2 (& self) -> & IPSR2 { & self . ipsr2 } # [doc = "0x280 - Interrupt Pending Clear Register"]
# [inline (always)]
pub const fn iprr1 (& self) -> & IPRR1 { & self . iprr1 } # [doc = "0x284 - Interrupt Pending Clear Register"]
# [inline (always)]
pub const fn iprr2 (& self) -> & IPRR2 { & self . iprr2 } # [doc = "0x300 - Interrupt ACTIVE Register"]
# [inline (always)]
pub const fn iactr1 (& self) -> & IACTR1 { & self . iactr1 } # [doc = "0x304 - Interrupt ACTIVE Register"]
# [inline (always)]
pub const fn iactr2 (& self) -> & IACTR2 { & self . iactr2 } # [doc = "0xd10 - System Control Register"]
# [inline (always)]
pub const fn sctlr (& self) -> & SCTLR { & self . sctlr } # [doc = "0x1000 - STK_CTLR Register"]
# [inline (always)]
pub const fn stk_ctlr (& self) -> & STK_CTLR { & self . stk_ctlr } } # [doc = "ISR1 (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr1`]
module"]
pub type ISR1 = crate :: Reg < isr1 :: ISR1_SPEC > ; # [doc = "Interrupt Status Register"]
pub mod isr1 { # [doc = "Register `ISR1` reader"]
pub type R = crate :: R < ISR1_SPEC > ; # [doc = "Field `INTENSTA2_3` reader - Interrupt ID Status"]
pub type INTENSTA2_3_R = crate :: FieldReader ; # [doc = "Field `INTENSTA12_31` reader - Interrupt ID Status"]
pub type INTENSTA12_31_R = crate :: FieldReader < u32 > ; impl R { # [doc = "Bits 2:3 - Interrupt ID Status"]
# [inline (always)]
pub fn intensta2_3 (& self) -> INTENSTA2_3_R { INTENSTA2_3_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 12:31 - Interrupt ID Status"]
# [inline (always)]
pub fn intensta12_31 (& self) -> INTENSTA12_31_R { INTENSTA12_31_R :: new ((self . bits >> 12) & 0x000f_ffff) } } # [doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISR1_SPEC ; impl crate :: RegisterSpec for ISR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`isr1::R`](R) reader structure"]
impl crate :: Readable for ISR1_SPEC { } # [doc = "`reset()` method sets ISR1 to value 0"]
impl crate :: Resettable for ISR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "ISR2 (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr2::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr2`]
module"]
pub type ISR2 = crate :: Reg < isr2 :: ISR2_SPEC > ; # [doc = "Interrupt Status Register"]
pub mod isr2 { # [doc = "Register `ISR2` reader"]
pub type R = crate :: R < ISR2_SPEC > ; # [doc = "Field `INTENSTA` reader - Interrupt ID Status"]
pub type INTENSTA_R = crate :: FieldReader < u32 > ; impl R { # [doc = "Bits 0:27 - Interrupt ID Status"]
# [inline (always)]
pub fn intensta (& self) -> INTENSTA_R { INTENSTA_R :: new (self . bits & 0x0fff_ffff) } } # [doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISR2_SPEC ; impl crate :: RegisterSpec for ISR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`isr2::R`](R) reader structure"]
impl crate :: Readable for ISR2_SPEC { } # [doc = "`reset()` method sets ISR2 to value 0"]
impl crate :: Resettable for ISR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPR1 (r) register accessor: Interrupt Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ipr1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ipr1`]
module"]
pub type IPR1 = crate :: Reg < ipr1 :: IPR1_SPEC > ; # [doc = "Interrupt Pending Register"]
pub mod ipr1 { # [doc = "Register `IPR1` reader"]
pub type R = crate :: R < IPR1_SPEC > ; # [doc = "Field `PENDSTA2_3` reader - PENDSTA"]
pub type PENDSTA2_3_R = crate :: FieldReader ; # [doc = "Field `PENDSTA12_31` reader - PENDSTA"]
pub type PENDSTA12_31_R = crate :: FieldReader < u32 > ; impl R { # [doc = "Bits 2:3 - PENDSTA"]
# [inline (always)]
pub fn pendsta2_3 (& self) -> PENDSTA2_3_R { PENDSTA2_3_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 12:31 - PENDSTA"]
# [inline (always)]
pub fn pendsta12_31 (& self) -> PENDSTA12_31_R { PENDSTA12_31_R :: new ((self . bits >> 12) & 0x000f_ffff) } } # [doc = "Interrupt Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ipr1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IPR1_SPEC ; impl crate :: RegisterSpec for IPR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ipr1::R`](R) reader structure"]
impl crate :: Readable for IPR1_SPEC { } # [doc = "`reset()` method sets IPR1 to value 0"]
impl crate :: Resettable for IPR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPR2 (r) register accessor: Interrupt Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ipr2::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ipr2`]
module"]
pub type IPR2 = crate :: Reg < ipr2 :: IPR2_SPEC > ; # [doc = "Interrupt Pending Register"]
pub mod ipr2 { # [doc = "Register `IPR2` reader"]
pub type R = crate :: R < IPR2_SPEC > ; # [doc = "Field `PENDSTA` reader - PENDSTA"]
pub type PENDSTA_R = crate :: FieldReader < u32 > ; impl R { # [doc = "Bits 0:27 - PENDSTA"]
# [inline (always)]
pub fn pendsta (& self) -> PENDSTA_R { PENDSTA_R :: new (self . bits & 0x0fff_ffff) } } # [doc = "Interrupt Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ipr2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IPR2_SPEC ; impl crate :: RegisterSpec for IPR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ipr2::R`](R) reader structure"]
impl crate :: Readable for IPR2_SPEC { } # [doc = "`reset()` method sets IPR2 to value 0"]
impl crate :: Resettable for IPR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "ITHRESDR (rw) register accessor: Interrupt Priority Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ithresdr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ithresdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ithresdr`]
module"]
pub type ITHRESDR = crate :: Reg < ithresdr :: ITHRESDR_SPEC > ; # [doc = "Interrupt Priority Register"]
pub mod ithresdr { # [doc = "Register `ITHRESDR` reader"]
pub type R = crate :: R < ITHRESDR_SPEC > ; # [doc = "Register `ITHRESDR` writer"]
pub type W = crate :: W < ITHRESDR_SPEC > ; # [doc = "Field `THRESHOLD` reader - THRESHOLD"]
pub type THRESHOLD_R = crate :: FieldReader ; # [doc = "Field `THRESHOLD` writer - THRESHOLD"]
pub type THRESHOLD_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:7 - THRESHOLD"]
# [inline (always)]
pub fn threshold (& self) -> THRESHOLD_R { THRESHOLD_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - THRESHOLD"]
# [inline (always)]
# [must_use]
pub fn threshold (& mut self) -> THRESHOLD_W < ITHRESDR_SPEC > { THRESHOLD_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Priority Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ithresdr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ithresdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ITHRESDR_SPEC ; impl crate :: RegisterSpec for ITHRESDR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ithresdr::R`](R) reader structure"]
impl crate :: Readable for ITHRESDR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ithresdr::W`](W) writer structure"]
impl crate :: Writable for ITHRESDR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets ITHRESDR to value 0"]
impl crate :: Resettable for ITHRESDR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "FIBADDRR (rw) register accessor: Interrupt Fast Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fibaddrr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fibaddrr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fibaddrr`]
module"]
pub type FIBADDRR = crate :: Reg < fibaddrr :: FIBADDRR_SPEC > ; # [doc = "Interrupt Fast Address Register"]
pub mod fibaddrr { # [doc = "Register `FIBADDRR` reader"]
pub type R = crate :: R < FIBADDRR_SPEC > ; # [doc = "Register `FIBADDRR` writer"]
pub type W = crate :: W < FIBADDRR_SPEC > ; # [doc = "Field `BASEADDR` reader - BASEADDR"]
pub type BASEADDR_R = crate :: FieldReader ; # [doc = "Field `BASEADDR` writer - BASEADDR"]
pub type BASEADDR_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; impl R { # [doc = "Bits 28:31 - BASEADDR"]
# [inline (always)]
pub fn baseaddr (& self) -> BASEADDR_R { BASEADDR_R :: new (((self . bits >> 28) & 0x0f) as u8) } } impl W { # [doc = "Bits 28:31 - BASEADDR"]
# [inline (always)]
# [must_use]
pub fn baseaddr (& mut self) -> BASEADDR_W < FIBADDRR_SPEC > { BASEADDR_W :: new (self , 28) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Fast Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fibaddrr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fibaddrr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FIBADDRR_SPEC ; impl crate :: RegisterSpec for FIBADDRR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fibaddrr::R`](R) reader structure"]
impl crate :: Readable for FIBADDRR_SPEC { } # [doc = "`write(|w| ..)` method takes [`fibaddrr::W`](W) writer structure"]
impl crate :: Writable for FIBADDRR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FIBADDRR to value 0"]
impl crate :: Resettable for FIBADDRR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "CFGR (rw) register accessor: Interrupt Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr`]
module"]
pub type CFGR = crate :: Reg < cfgr :: CFGR_SPEC > ; # [doc = "Interrupt Config Register"]
pub mod cfgr { # [doc = "Register `CFGR` reader"]
pub type R = crate :: R < CFGR_SPEC > ; # [doc = "Register `CFGR` writer"]
pub type W = crate :: W < CFGR_SPEC > ; # [doc = "Field `HWSTKCTRL` reader - HWSTKCTRL"]
pub type HWSTKCTRL_R = crate :: BitReader ; # [doc = "Field `HWSTKCTRL` writer - HWSTKCTRL"]
pub type HWSTKCTRL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NESTCTRL` reader - NESTCTRL"]
pub type NESTCTRL_R = crate :: BitReader ; # [doc = "Field `NESTCTRL` writer - NESTCTRL"]
pub type NESTCTRL_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NMISET` writer - NMISET"]
pub type NMISET_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `NMIRESET` writer - NMIRESET"]
pub type NMIRESET_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EXCSET` writer - EXCSET"]
pub type EXCSET_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EXCRESET` writer - EXCRESET"]
pub type EXCRESET_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PFICRSET` writer - PFICRSET"]
pub type PFICRSET_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SYSRESET` writer - SYSRESET"]
pub type SYSRESET_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `KEYCODE` writer - KEYCODE"]
pub type KEYCODE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 16 , u16 > ; impl R { # [doc = "Bit 0 - HWSTKCTRL"]
# [inline (always)]
pub fn hwstkctrl (& self) -> HWSTKCTRL_R { HWSTKCTRL_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - NESTCTRL"]
# [inline (always)]
pub fn nestctrl (& self) -> NESTCTRL_R { NESTCTRL_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - HWSTKCTRL"]
# [inline (always)]
# [must_use]
pub fn hwstkctrl (& mut self) -> HWSTKCTRL_W < CFGR_SPEC > { HWSTKCTRL_W :: new (self , 0) } # [doc = "Bit 1 - NESTCTRL"]
# [inline (always)]
# [must_use]
pub fn nestctrl (& mut self) -> NESTCTRL_W < CFGR_SPEC > { NESTCTRL_W :: new (self , 1) } # [doc = "Bit 2 - NMISET"]
# [inline (always)]
# [must_use]
pub fn nmiset (& mut self) -> NMISET_W < CFGR_SPEC > { NMISET_W :: new (self , 2) } # [doc = "Bit 3 - NMIRESET"]
# [inline (always)]
# [must_use]
pub fn nmireset (& mut self) -> NMIRESET_W < CFGR_SPEC > { NMIRESET_W :: new (self , 3) } # [doc = "Bit 4 - EXCSET"]
# [inline (always)]
# [must_use]
pub fn excset (& mut self) -> EXCSET_W < CFGR_SPEC > { EXCSET_W :: new (self , 4) } # [doc = "Bit 5 - EXCRESET"]
# [inline (always)]
# [must_use]
pub fn excreset (& mut self) -> EXCRESET_W < CFGR_SPEC > { EXCRESET_W :: new (self , 5) } # [doc = "Bit 6 - PFICRSET"]
# [inline (always)]
# [must_use]
pub fn pficrset (& mut self) -> PFICRSET_W < CFGR_SPEC > { PFICRSET_W :: new (self , 6) } # [doc = "Bit 7 - SYSRESET"]
# [inline (always)]
# [must_use]
pub fn sysreset (& mut self) -> SYSRESET_W < CFGR_SPEC > { SYSRESET_W :: new (self , 7) } # [doc = "Bits 16:31 - KEYCODE"]
# [inline (always)]
# [must_use]
pub fn keycode (& mut self) -> KEYCODE_W < CFGR_SPEC > { KEYCODE_W :: new (self , 16) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGR_SPEC ; impl crate :: RegisterSpec for CFGR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgr::R`](R) reader structure"]
impl crate :: Readable for CFGR_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"]
impl crate :: Writable for CFGR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets CFGR to value 0"]
impl crate :: Resettable for CFGR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "GISR (r) register accessor: Interrupt Global Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gisr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gisr`]
module"]
pub type GISR = crate :: Reg < gisr :: GISR_SPEC > ; # [doc = "Interrupt Global Register"]
pub mod gisr { # [doc = "Register `GISR` reader"]
pub type R = crate :: R < GISR_SPEC > ; # [doc = "Field `NESTSTA` reader - NESTSTA"]
pub type NESTSTA_R = crate :: FieldReader ; # [doc = "Field `GACTSTA` reader - GACTSTA"]
pub type GACTSTA_R = crate :: BitReader ; # [doc = "Field `GPENDSTA` reader - GPENDSTA"]
pub type GPENDSTA_R = crate :: BitReader ; impl R { # [doc = "Bits 0:7 - NESTSTA"]
# [inline (always)]
pub fn neststa (& self) -> NESTSTA_R { NESTSTA_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bit 8 - GACTSTA"]
# [inline (always)]
pub fn gactsta (& self) -> GACTSTA_R { GACTSTA_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - GPENDSTA"]
# [inline (always)]
pub fn gpendsta (& self) -> GPENDSTA_R { GPENDSTA_R :: new (((self . bits >> 9) & 1) != 0) } } # [doc = "Interrupt Global Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gisr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GISR_SPEC ; impl crate :: RegisterSpec for GISR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gisr::R`](R) reader structure"]
impl crate :: Readable for GISR_SPEC { } # [doc = "`reset()` method sets GISR to value 0"]
impl crate :: Resettable for GISR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "FIFOADDRR0 (rw) register accessor: Interrupt 0 address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifoaddrr0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifoaddrr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifoaddrr0`]
module"]
pub type FIFOADDRR0 = crate :: Reg < fifoaddrr0 :: FIFOADDRR0_SPEC > ; # [doc = "Interrupt 0 address Register"]
pub mod fifoaddrr0 { # [doc = "Register `FIFOADDRR0` reader"]
pub type R = crate :: R < FIFOADDRR0_SPEC > ; # [doc = "Register `FIFOADDRR0` writer"]
pub type W = crate :: W < FIFOADDRR0_SPEC > ; # [doc = "Field `OFFADDR0` reader - OFFADDR0"]
pub type OFFADDR0_R = crate :: FieldReader < u32 > ; # [doc = "Field `OFFADDR0` writer - OFFADDR0"]
pub type OFFADDR0_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `IRQID0` reader - IRQID0"]
pub type IRQID0_R = crate :: FieldReader ; # [doc = "Field `IRQID0` writer - IRQID0"]
pub type IRQID0_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - OFFADDR0"]
# [inline (always)]
pub fn offaddr0 (& self) -> OFFADDR0_R { OFFADDR0_R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31 - IRQID0"]
# [inline (always)]
pub fn irqid0 (& self) -> IRQID0_R { IRQID0_R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - OFFADDR0"]
# [inline (always)]
# [must_use]
pub fn offaddr0 (& mut self) -> OFFADDR0_W < FIFOADDRR0_SPEC > { OFFADDR0_W :: new (self , 0) } # [doc = "Bits 24:31 - IRQID0"]
# [inline (always)]
# [must_use]
pub fn irqid0 (& mut self) -> IRQID0_W < FIFOADDRR0_SPEC > { IRQID0_W :: new (self , 24) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt 0 address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifoaddrr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifoaddrr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FIFOADDRR0_SPEC ; impl crate :: RegisterSpec for FIFOADDRR0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fifoaddrr0::R`](R) reader structure"]
impl crate :: Readable for FIFOADDRR0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fifoaddrr0::W`](W) writer structure"]
impl crate :: Writable for FIFOADDRR0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FIFOADDRR0 to value 0"]
impl crate :: Resettable for FIFOADDRR0_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "FIFOADDRR1 (rw) register accessor: Interrupt 1 address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifoaddrr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifoaddrr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifoaddrr1`]
module"]
pub type FIFOADDRR1 = crate :: Reg < fifoaddrr1 :: FIFOADDRR1_SPEC > ; # [doc = "Interrupt 1 address Register"]
pub mod fifoaddrr1 { # [doc = "Register `FIFOADDRR1` reader"]
pub type R = crate :: R < FIFOADDRR1_SPEC > ; # [doc = "Register `FIFOADDRR1` writer"]
pub type W = crate :: W < FIFOADDRR1_SPEC > ; # [doc = "Field `OFFADDR1` reader - OFFADDR1"]
pub type OFFADDR1_R = crate :: FieldReader < u32 > ; # [doc = "Field `OFFADDR1` writer - OFFADDR1"]
pub type OFFADDR1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `IRQID1` reader - IRQID1"]
pub type IRQID1_R = crate :: FieldReader ; # [doc = "Field `IRQID1` writer - IRQID1"]
pub type IRQID1_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - OFFADDR1"]
# [inline (always)]
pub fn offaddr1 (& self) -> OFFADDR1_R { OFFADDR1_R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31 - IRQID1"]
# [inline (always)]
pub fn irqid1 (& self) -> IRQID1_R { IRQID1_R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - OFFADDR1"]
# [inline (always)]
# [must_use]
pub fn offaddr1 (& mut self) -> OFFADDR1_W < FIFOADDRR1_SPEC > { OFFADDR1_W :: new (self , 0) } # [doc = "Bits 24:31 - IRQID1"]
# [inline (always)]
# [must_use]
pub fn irqid1 (& mut self) -> IRQID1_W < FIFOADDRR1_SPEC > { IRQID1_W :: new (self , 24) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt 1 address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifoaddrr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifoaddrr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FIFOADDRR1_SPEC ; impl crate :: RegisterSpec for FIFOADDRR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fifoaddrr1::R`](R) reader structure"]
impl crate :: Readable for FIFOADDRR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fifoaddrr1::W`](W) writer structure"]
impl crate :: Writable for FIFOADDRR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FIFOADDRR1 to value 0"]
impl crate :: Resettable for FIFOADDRR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "FIFOADDRR2 (rw) register accessor: Interrupt 2 address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifoaddrr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifoaddrr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifoaddrr2`]
module"]
pub type FIFOADDRR2 = crate :: Reg < fifoaddrr2 :: FIFOADDRR2_SPEC > ; # [doc = "Interrupt 2 address Register"]
pub mod fifoaddrr2 { # [doc = "Register `FIFOADDRR2` reader"]
pub type R = crate :: R < FIFOADDRR2_SPEC > ; # [doc = "Register `FIFOADDRR2` writer"]
pub type W = crate :: W < FIFOADDRR2_SPEC > ; # [doc = "Field `OFFADDR2` reader - OFFADDR2"]
pub type OFFADDR2_R = crate :: FieldReader < u32 > ; # [doc = "Field `OFFADDR2` writer - OFFADDR2"]
pub type OFFADDR2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `IRQID2` reader - IRQID2"]
pub type IRQID2_R = crate :: FieldReader ; # [doc = "Field `IRQID2` writer - IRQID2"]
pub type IRQID2_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - OFFADDR2"]
# [inline (always)]
pub fn offaddr2 (& self) -> OFFADDR2_R { OFFADDR2_R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31 - IRQID2"]
# [inline (always)]
pub fn irqid2 (& self) -> IRQID2_R { IRQID2_R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - OFFADDR2"]
# [inline (always)]
# [must_use]
pub fn offaddr2 (& mut self) -> OFFADDR2_W < FIFOADDRR2_SPEC > { OFFADDR2_W :: new (self , 0) } # [doc = "Bits 24:31 - IRQID2"]
# [inline (always)]
# [must_use]
pub fn irqid2 (& mut self) -> IRQID2_W < FIFOADDRR2_SPEC > { IRQID2_W :: new (self , 24) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt 2 address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifoaddrr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifoaddrr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FIFOADDRR2_SPEC ; impl crate :: RegisterSpec for FIFOADDRR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fifoaddrr2::R`](R) reader structure"]
impl crate :: Readable for FIFOADDRR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`fifoaddrr2::W`](W) writer structure"]
impl crate :: Writable for FIFOADDRR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FIFOADDRR2 to value 0"]
impl crate :: Resettable for FIFOADDRR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "FIFOADDRR3 (rw) register accessor: Interrupt 3 address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifoaddrr3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifoaddrr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifoaddrr3`]
module"]
pub type FIFOADDRR3 = crate :: Reg < fifoaddrr3 :: FIFOADDRR3_SPEC > ; # [doc = "Interrupt 3 address Register"]
pub mod fifoaddrr3 { # [doc = "Register `FIFOADDRR3` reader"]
pub type R = crate :: R < FIFOADDRR3_SPEC > ; # [doc = "Register `FIFOADDRR3` writer"]
pub type W = crate :: W < FIFOADDRR3_SPEC > ; # [doc = "Field `OFFADDR3` reader - OFFADDR3"]
pub type OFFADDR3_R = crate :: FieldReader < u32 > ; # [doc = "Field `OFFADDR3` writer - OFFADDR3"]
pub type OFFADDR3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 24 , u32 > ; # [doc = "Field `IRQID3` reader - IRQID3"]
pub type IRQID3_R = crate :: FieldReader ; # [doc = "Field `IRQID3` writer - IRQID3"]
pub type IRQID3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 8 > ; impl R { # [doc = "Bits 0:23 - OFFADDR3"]
# [inline (always)]
pub fn offaddr3 (& self) -> OFFADDR3_R { OFFADDR3_R :: new (self . bits & 0x00ff_ffff) } # [doc = "Bits 24:31 - IRQID3"]
# [inline (always)]
pub fn irqid3 (& self) -> IRQID3_R { IRQID3_R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:23 - OFFADDR3"]
# [inline (always)]
# [must_use]
pub fn offaddr3 (& mut self) -> OFFADDR3_W < FIFOADDRR3_SPEC > { OFFADDR3_W :: new (self , 0) } # [doc = "Bits 24:31 - IRQID3"]
# [inline (always)]
# [must_use]
pub fn irqid3 (& mut self) -> IRQID3_W < FIFOADDRR3_SPEC > { IRQID3_W :: new (self , 24) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt 3 address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifoaddrr3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifoaddrr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FIFOADDRR3_SPEC ; impl crate :: RegisterSpec for FIFOADDRR3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fifoaddrr3::R`](R) reader structure"]
impl crate :: Readable for FIFOADDRR3_SPEC { } # [doc = "`write(|w| ..)` method takes [`fifoaddrr3::W`](W) writer structure"]
impl crate :: Writable for FIFOADDRR3_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets FIFOADDRR3 to value 0"]
impl crate :: Resettable for FIFOADDRR3_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IENR1 (rw) register accessor: Interrupt Setting Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ienr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ienr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ienr1`]
module"]
pub type IENR1 = crate :: Reg < ienr1 :: IENR1_SPEC > ; # [doc = "Interrupt Setting Register"]
pub mod ienr1 { # [doc = "Register `IENR1` reader"]
pub type R = crate :: R < IENR1_SPEC > ; # [doc = "Register `IENR1` writer"]
pub type W = crate :: W < IENR1_SPEC > ; # [doc = "Field `INTEN` reader - INTEN"]
pub type INTEN_R = crate :: FieldReader < u32 > ; # [doc = "Field `INTEN` writer - INTEN"]
pub type INTEN_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 12:31 - INTEN"]
# [inline (always)]
pub fn inten (& self) -> INTEN_R { INTEN_R :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 12:31 - INTEN"]
# [inline (always)]
# [must_use]
pub fn inten (& mut self) -> INTEN_W < IENR1_SPEC > { INTEN_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Setting Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ienr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ienr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IENR1_SPEC ; impl crate :: RegisterSpec for IENR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ienr1::R`](R) reader structure"]
impl crate :: Readable for IENR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`ienr1::W`](W) writer structure"]
impl crate :: Writable for IENR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IENR1 to value 0"]
impl crate :: Resettable for IENR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IENR2 (rw) register accessor: Interrupt Setting Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ienr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ienr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ienr2`]
module"]
pub type IENR2 = crate :: Reg < ienr2 :: IENR2_SPEC > ; # [doc = "Interrupt Setting Register"]
pub mod ienr2 { # [doc = "Register `IENR2` reader"]
pub type R = crate :: R < IENR2_SPEC > ; # [doc = "Register `IENR2` writer"]
pub type W = crate :: W < IENR2_SPEC > ; # [doc = "Field `INTEN` reader - INTEN"]
pub type INTEN_R = crate :: FieldReader < u32 > ; # [doc = "Field `INTEN` writer - INTEN"]
pub type INTEN_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:27 - INTEN"]
# [inline (always)]
pub fn inten (& self) -> INTEN_R { INTEN_R :: new (self . bits & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:27 - INTEN"]
# [inline (always)]
# [must_use]
pub fn inten (& mut self) -> INTEN_W < IENR2_SPEC > { INTEN_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Setting Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ienr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ienr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IENR2_SPEC ; impl crate :: RegisterSpec for IENR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ienr2::R`](R) reader structure"]
impl crate :: Readable for IENR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`ienr2::W`](W) writer structure"]
impl crate :: Writable for IENR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IENR2 to value 0"]
impl crate :: Resettable for IENR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IRER1 (rw) register accessor: Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irer1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irer1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irer1`]
module"]
pub type IRER1 = crate :: Reg < irer1 :: IRER1_SPEC > ; # [doc = "Interrupt Clear Register"]
pub mod irer1 { # [doc = "Register `IRER1` reader"]
pub type R = crate :: R < IRER1_SPEC > ; # [doc = "Register `IRER1` writer"]
pub type W = crate :: W < IRER1_SPEC > ; # [doc = "Field `INTRSET` reader - INTRSET"]
pub type INTRSET_R = crate :: FieldReader < u32 > ; # [doc = "Field `INTRSET` writer - INTRSET"]
pub type INTRSET_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 12:31 - INTRSET"]
# [inline (always)]
pub fn intrset (& self) -> INTRSET_R { INTRSET_R :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 12:31 - INTRSET"]
# [inline (always)]
# [must_use]
pub fn intrset (& mut self) -> INTRSET_W < IRER1_SPEC > { INTRSET_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irer1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irer1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IRER1_SPEC ; impl crate :: RegisterSpec for IRER1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`irer1::R`](R) reader structure"]
impl crate :: Readable for IRER1_SPEC { } # [doc = "`write(|w| ..)` method takes [`irer1::W`](W) writer structure"]
impl crate :: Writable for IRER1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IRER1 to value 0"]
impl crate :: Resettable for IRER1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IRER2 (rw) register accessor: Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irer2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irer2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irer2`]
module"]
pub type IRER2 = crate :: Reg < irer2 :: IRER2_SPEC > ; # [doc = "Interrupt Clear Register"]
pub mod irer2 { # [doc = "Register `IRER2` reader"]
pub type R = crate :: R < IRER2_SPEC > ; # [doc = "Register `IRER2` writer"]
pub type W = crate :: W < IRER2_SPEC > ; # [doc = "Field `INTRSET` reader - INTRSET"]
pub type INTRSET_R = crate :: FieldReader < u32 > ; # [doc = "Field `INTRSET` writer - INTRSET"]
pub type INTRSET_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:27 - INTRSET"]
# [inline (always)]
pub fn intrset (& self) -> INTRSET_R { INTRSET_R :: new (self . bits & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:27 - INTRSET"]
# [inline (always)]
# [must_use]
pub fn intrset (& mut self) -> INTRSET_W < IRER2_SPEC > { INTRSET_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irer2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irer2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IRER2_SPEC ; impl crate :: RegisterSpec for IRER2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`irer2::R`](R) reader structure"]
impl crate :: Readable for IRER2_SPEC { } # [doc = "`write(|w| ..)` method takes [`irer2::W`](W) writer structure"]
impl crate :: Writable for IRER2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IRER2 to value 0"]
impl crate :: Resettable for IRER2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPSR1 (rw) register accessor: Interrupt Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ipsr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ipsr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ipsr1`]
module"]
pub type IPSR1 = crate :: Reg < ipsr1 :: IPSR1_SPEC > ; # [doc = "Interrupt Pending Register"]
pub mod ipsr1 { # [doc = "Register `IPSR1` reader"]
pub type R = crate :: R < IPSR1_SPEC > ; # [doc = "Register `IPSR1` writer"]
pub type W = crate :: W < IPSR1_SPEC > ; # [doc = "Field `PENDSET2_3` reader - PENDSET"]
pub type PENDSET2_3_R = crate :: FieldReader ; # [doc = "Field `PENDSET2_3` writer - PENDSET"]
pub type PENDSET2_3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PENDSET12_31` reader - PENDSET"]
pub type PENDSET12_31_R = crate :: FieldReader < u32 > ; # [doc = "Field `PENDSET12_31` writer - PENDSET"]
pub type PENDSET12_31_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 2:3 - PENDSET"]
# [inline (always)]
pub fn pendset2_3 (& self) -> PENDSET2_3_R { PENDSET2_3_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 12:31 - PENDSET"]
# [inline (always)]
pub fn pendset12_31 (& self) -> PENDSET12_31_R { PENDSET12_31_R :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 2:3 - PENDSET"]
# [inline (always)]
# [must_use]
pub fn pendset2_3 (& mut self) -> PENDSET2_3_W < IPSR1_SPEC > { PENDSET2_3_W :: new (self , 2) } # [doc = "Bits 12:31 - PENDSET"]
# [inline (always)]
# [must_use]
pub fn pendset12_31 (& mut self) -> PENDSET12_31_W < IPSR1_SPEC > { PENDSET12_31_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ipsr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ipsr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IPSR1_SPEC ; impl crate :: RegisterSpec for IPSR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ipsr1::R`](R) reader structure"]
impl crate :: Readable for IPSR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`ipsr1::W`](W) writer structure"]
impl crate :: Writable for IPSR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPSR1 to value 0"]
impl crate :: Resettable for IPSR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPSR2 (rw) register accessor: Interrupt Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ipsr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ipsr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ipsr2`]
module"]
pub type IPSR2 = crate :: Reg < ipsr2 :: IPSR2_SPEC > ; # [doc = "Interrupt Pending Register"]
pub mod ipsr2 { # [doc = "Register `IPSR2` reader"]
pub type R = crate :: R < IPSR2_SPEC > ; # [doc = "Register `IPSR2` writer"]
pub type W = crate :: W < IPSR2_SPEC > ; # [doc = "Field `PENDSET` reader - PENDSET"]
pub type PENDSET_R = crate :: FieldReader < u32 > ; # [doc = "Field `PENDSET` writer - PENDSET"]
pub type PENDSET_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:27 - PENDSET"]
# [inline (always)]
pub fn pendset (& self) -> PENDSET_R { PENDSET_R :: new (self . bits & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:27 - PENDSET"]
# [inline (always)]
# [must_use]
pub fn pendset (& mut self) -> PENDSET_W < IPSR2_SPEC > { PENDSET_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ipsr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ipsr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IPSR2_SPEC ; impl crate :: RegisterSpec for IPSR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ipsr2::R`](R) reader structure"]
impl crate :: Readable for IPSR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`ipsr2::W`](W) writer structure"]
impl crate :: Writable for IPSR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPSR2 to value 0"]
impl crate :: Resettable for IPSR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPRR1 (rw) register accessor: Interrupt Pending Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iprr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iprr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iprr1`]
module"]
pub type IPRR1 = crate :: Reg < iprr1 :: IPRR1_SPEC > ; # [doc = "Interrupt Pending Clear Register"]
pub mod iprr1 { # [doc = "Register `IPRR1` reader"]
pub type R = crate :: R < IPRR1_SPEC > ; # [doc = "Register `IPRR1` writer"]
pub type W = crate :: W < IPRR1_SPEC > ; # [doc = "Field `PENDRESET2_3` reader - PENDRESET"]
pub type PENDRESET2_3_R = crate :: FieldReader ; # [doc = "Field `PENDRESET2_3` writer - PENDRESET"]
pub type PENDRESET2_3_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `PENDRESET12_31` reader - PENDRESET"]
pub type PENDRESET12_31_R = crate :: FieldReader < u32 > ; # [doc = "Field `PENDRESET12_31` writer - PENDRESET"]
pub type PENDRESET12_31_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 2:3 - PENDRESET"]
# [inline (always)]
pub fn pendreset2_3 (& self) -> PENDRESET2_3_R { PENDRESET2_3_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 12:31 - PENDRESET"]
# [inline (always)]
pub fn pendreset12_31 (& self) -> PENDRESET12_31_R { PENDRESET12_31_R :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 2:3 - PENDRESET"]
# [inline (always)]
# [must_use]
pub fn pendreset2_3 (& mut self) -> PENDRESET2_3_W < IPRR1_SPEC > { PENDRESET2_3_W :: new (self , 2) } # [doc = "Bits 12:31 - PENDRESET"]
# [inline (always)]
# [must_use]
pub fn pendreset12_31 (& mut self) -> PENDRESET12_31_W < IPRR1_SPEC > { PENDRESET12_31_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Pending Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iprr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iprr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IPRR1_SPEC ; impl crate :: RegisterSpec for IPRR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iprr1::R`](R) reader structure"]
impl crate :: Readable for IPRR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`iprr1::W`](W) writer structure"]
impl crate :: Writable for IPRR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPRR1 to value 0"]
impl crate :: Resettable for IPRR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IPRR2 (rw) register accessor: Interrupt Pending Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iprr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iprr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iprr2`]
module"]
pub type IPRR2 = crate :: Reg < iprr2 :: IPRR2_SPEC > ; # [doc = "Interrupt Pending Clear Register"]
pub mod iprr2 { # [doc = "Register `IPRR2` reader"]
pub type R = crate :: R < IPRR2_SPEC > ; # [doc = "Register `IPRR2` writer"]
pub type W = crate :: W < IPRR2_SPEC > ; # [doc = "Field `PENDRESET` reader - PENDRESET"]
pub type PENDRESET_R = crate :: FieldReader < u32 > ; # [doc = "Field `PENDRESET` writer - PENDRESET"]
pub type PENDRESET_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:27 - PENDRESET"]
# [inline (always)]
pub fn pendreset (& self) -> PENDRESET_R { PENDRESET_R :: new (self . bits & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:27 - PENDRESET"]
# [inline (always)]
# [must_use]
pub fn pendreset (& mut self) -> PENDRESET_W < IPRR2_SPEC > { PENDRESET_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Pending Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iprr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iprr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IPRR2_SPEC ; impl crate :: RegisterSpec for IPRR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iprr2::R`](R) reader structure"]
impl crate :: Readable for IPRR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`iprr2::W`](W) writer structure"]
impl crate :: Writable for IPRR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IPRR2 to value 0"]
impl crate :: Resettable for IPRR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IACTR1 (rw) register accessor: Interrupt ACTIVE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iactr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iactr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iactr1`]
module"]
pub type IACTR1 = crate :: Reg < iactr1 :: IACTR1_SPEC > ; # [doc = "Interrupt ACTIVE Register"]
pub mod iactr1 { # [doc = "Register `IACTR1` reader"]
pub type R = crate :: R < IACTR1_SPEC > ; # [doc = "Register `IACTR1` writer"]
pub type W = crate :: W < IACTR1_SPEC > ; # [doc = "Field `IACTS` reader - IACTS"]
pub type IACTS_R = crate :: FieldReader < u32 > ; # [doc = "Field `IACTS` writer - IACTS"]
pub type IACTS_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 20 , u32 > ; impl R { # [doc = "Bits 12:31 - IACTS"]
# [inline (always)]
pub fn iacts (& self) -> IACTS_R { IACTS_R :: new ((self . bits >> 12) & 0x000f_ffff) } } impl W { # [doc = "Bits 12:31 - IACTS"]
# [inline (always)]
# [must_use]
pub fn iacts (& mut self) -> IACTS_W < IACTR1_SPEC > { IACTS_W :: new (self , 12) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt ACTIVE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iactr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iactr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IACTR1_SPEC ; impl crate :: RegisterSpec for IACTR1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iactr1::R`](R) reader structure"]
impl crate :: Readable for IACTR1_SPEC { } # [doc = "`write(|w| ..)` method takes [`iactr1::W`](W) writer structure"]
impl crate :: Writable for IACTR1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IACTR1 to value 0"]
impl crate :: Resettable for IACTR1_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "IACTR2 (rw) register accessor: Interrupt ACTIVE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iactr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iactr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iactr2`]
module"]
pub type IACTR2 = crate :: Reg < iactr2 :: IACTR2_SPEC > ; # [doc = "Interrupt ACTIVE Register"]
pub mod iactr2 { # [doc = "Register `IACTR2` reader"]
pub type R = crate :: R < IACTR2_SPEC > ; # [doc = "Register `IACTR2` writer"]
pub type W = crate :: W < IACTR2_SPEC > ; # [doc = "Field `IACTS` reader - IACTS"]
pub type IACTS_R = crate :: FieldReader < u32 > ; # [doc = "Field `IACTS` writer - IACTS"]
pub type IACTS_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:27 - IACTS"]
# [inline (always)]
pub fn iacts (& self) -> IACTS_R { IACTS_R :: new (self . bits & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:27 - IACTS"]
# [inline (always)]
# [must_use]
pub fn iacts (& mut self) -> IACTS_W < IACTR2_SPEC > { IACTS_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt ACTIVE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iactr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iactr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IACTR2_SPEC ; impl crate :: RegisterSpec for IACTR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iactr2::R`](R) reader structure"]
impl crate :: Readable for IACTR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`iactr2::W`](W) writer structure"]
impl crate :: Writable for IACTR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets IACTR2 to value 0"]
impl crate :: Resettable for IACTR2_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "SCTLR (rw) register accessor: System Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sctlr`]
module"]
pub type SCTLR = crate :: Reg < sctlr :: SCTLR_SPEC > ; # [doc = "System Control Register"]
pub mod sctlr { # [doc = "Register `SCTLR` reader"]
pub type R = crate :: R < SCTLR_SPEC > ; # [doc = "Register `SCTLR` writer"]
pub type W = crate :: W < SCTLR_SPEC > ; # [doc = "Field `SLEEPONEXIT` reader - SLEEPONEXIT"]
pub type SLEEPONEXIT_R = crate :: BitReader ; # [doc = "Field `SLEEPONEXIT` writer - SLEEPONEXIT"]
pub type SLEEPONEXIT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SLEEPDEEP` reader - SLEEPDEEP"]
pub type SLEEPDEEP_R = crate :: BitReader ; # [doc = "Field `SLEEPDEEP` writer - SLEEPDEEP"]
pub type SLEEPDEEP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WFITOWFE` reader - WFITOWFE"]
pub type WFITOWFE_R = crate :: BitReader ; # [doc = "Field `WFITOWFE` writer - WFITOWFE"]
pub type WFITOWFE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SEVONPEND` reader - SEVONPEND"]
pub type SEVONPEND_R = crate :: BitReader ; # [doc = "Field `SEVONPEND` writer - SEVONPEND"]
pub type SEVONPEND_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SETEVENT` reader - SETEVENT"]
pub type SETEVENT_R = crate :: BitReader ; # [doc = "Field `SETEVENT` writer - SETEVENT"]
pub type SETEVENT_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 1 - SLEEPONEXIT"]
# [inline (always)]
pub fn sleeponexit (& self) -> SLEEPONEXIT_R { SLEEPONEXIT_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - SLEEPDEEP"]
# [inline (always)]
pub fn sleepdeep (& self) -> SLEEPDEEP_R { SLEEPDEEP_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - WFITOWFE"]
# [inline (always)]
pub fn wfitowfe (& self) -> WFITOWFE_R { WFITOWFE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - SEVONPEND"]
# [inline (always)]
pub fn sevonpend (& self) -> SEVONPEND_R { SEVONPEND_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - SETEVENT"]
# [inline (always)]
pub fn setevent (& self) -> SETEVENT_R { SETEVENT_R :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bit 1 - SLEEPONEXIT"]
# [inline (always)]
# [must_use]
pub fn sleeponexit (& mut self) -> SLEEPONEXIT_W < SCTLR_SPEC > { SLEEPONEXIT_W :: new (self , 1) } # [doc = "Bit 2 - SLEEPDEEP"]
# [inline (always)]
# [must_use]
pub fn sleepdeep (& mut self) -> SLEEPDEEP_W < SCTLR_SPEC > { SLEEPDEEP_W :: new (self , 2) } # [doc = "Bit 3 - WFITOWFE"]
# [inline (always)]
# [must_use]
pub fn wfitowfe (& mut self) -> WFITOWFE_W < SCTLR_SPEC > { WFITOWFE_W :: new (self , 3) } # [doc = "Bit 4 - SEVONPEND"]
# [inline (always)]
# [must_use]
pub fn sevonpend (& mut self) -> SEVONPEND_W < SCTLR_SPEC > { SEVONPEND_W :: new (self , 4) } # [doc = "Bit 5 - SETEVENT"]
# [inline (always)]
# [must_use]
pub fn setevent (& mut self) -> SETEVENT_W < SCTLR_SPEC > { SETEVENT_W :: new (self , 5) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "System Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SCTLR_SPEC ; impl crate :: RegisterSpec for SCTLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctlr::R`](R) reader structure"]
impl crate :: Readable for SCTLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctlr::W`](W) writer structure"]
impl crate :: Writable for SCTLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets SCTLR to value 0"]
impl crate :: Resettable for SCTLR_SPEC { const RESET_VALUE : u32 = 0 ; } } # [doc = "STK_CTLR (rw) register accessor: STK_CTLR Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stk_ctlr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stk_ctlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stk_ctlr`]
module"]
pub type STK_CTLR = crate :: Reg < stk_ctlr :: STK_CTLR_SPEC > ; # [doc = "STK_CTLR Register"]
pub mod stk_ctlr { # [doc = "Register `STK_CTLR` reader"]
pub type R = crate :: R < STK_CTLR_SPEC > ; # [doc = "Register `STK_CTLR` writer"]
pub type W = crate :: W < STK_CTLR_SPEC > ; # [doc = "Field `STE` reader - STE"]
pub type STE_R = crate :: FieldReader < u32 > ; # [doc = "Field `STE` writer - STE"]
pub type STE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 28 , u32 > ; impl R { # [doc = "Bits 0:27 - STE"]
# [inline (always)]
pub fn ste (& self) -> STE_R { STE_R :: new (self . bits & 0x0fff_ffff) } } impl W { # [doc = "Bits 0:27 - STE"]
# [inline (always)]
# [must_use]
pub fn ste (& mut self) -> STE_W < STK_CTLR_SPEC > { STE_W :: new (self , 0) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "STK_CTLR Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stk_ctlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stk_ctlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STK_CTLR_SPEC ; impl crate :: RegisterSpec for STK_CTLR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stk_ctlr::R`](R) reader structure"]
impl crate :: Readable for STK_CTLR_SPEC { } # [doc = "`write(|w| ..)` method takes [`stk_ctlr::W`](W) writer structure"]
impl crate :: Writable for STK_CTLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u32 = 0 ; } # [doc = "`reset()` method sets STK_CTLR to value 0"]
impl crate :: Resettable for STK_CTLR_SPEC { const RESET_VALUE : u32 = 0 ; } } } # [doc = "Universal serial bus full-speed device interface"]
pub struct USBD { _marker : PhantomData < * const () > } unsafe impl Send for USBD { } impl USBD { # [doc = r"Pointer to the register block"]
pub const PTR : * const usbd :: RegisterBlock = 0x4000_5c00 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const usbd :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for USBD { type Target = usbd :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for USBD { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("USBD") . finish () } } # [doc = "Universal serial bus full-speed device interface"]
pub mod usbd { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { ep0r : EP0R , _reserved1 : [u8 ; 0x02]
, ep1r : EP1R , _reserved2 : [u8 ; 0x02]
, ep2r : EP2R , _reserved3 : [u8 ; 0x02]
, ep3r : EP3R , _reserved4 : [u8 ; 0x02]
, ep4r : EP4R , _reserved5 : [u8 ; 0x02]
, ep5r : EP5R , _reserved6 : [u8 ; 0x02]
, ep6r : EP6R , _reserved7 : [u8 ; 0x02]
, ep7r : EP7R , _reserved8 : [u8 ; 0x22]
, cntr : CNTR , _reserved9 : [u8 ; 0x02]
, istr : ISTR , _reserved10 : [u8 ; 0x02]
, fnr : FNR , _reserved11 : [u8 ; 0x02]
, daddr : DADDR , _reserved12 : [u8 ; 0x02]
, btable : BTABLE , } impl RegisterBlock { # [doc = "0x00 - endpoint 0 register"]
# [inline (always)]
pub const fn ep0r (& self) -> & EP0R { & self . ep0r } # [doc = "0x04 - endpoint 1 register"]
# [inline (always)]
pub const fn ep1r (& self) -> & EP1R { & self . ep1r } # [doc = "0x08 - endpoint 2 register"]
# [inline (always)]
pub const fn ep2r (& self) -> & EP2R { & self . ep2r } # [doc = "0x0c - endpoint 3 register"]
# [inline (always)]
pub const fn ep3r (& self) -> & EP3R { & self . ep3r } # [doc = "0x10 - endpoint 4 register"]
# [inline (always)]
pub const fn ep4r (& self) -> & EP4R { & self . ep4r } # [doc = "0x14 - endpoint 5 register"]
# [inline (always)]
pub const fn ep5r (& self) -> & EP5R { & self . ep5r } # [doc = "0x18 - endpoint 6 register"]
# [inline (always)]
pub const fn ep6r (& self) -> & EP6R { & self . ep6r } # [doc = "0x1c - endpoint 7 register"]
# [inline (always)]
pub const fn ep7r (& self) -> & EP7R { & self . ep7r } # [doc = "0x40 - control register"]
# [inline (always)]
pub const fn cntr (& self) -> & CNTR { & self . cntr } # [doc = "0x44 - interrupt status register"]
# [inline (always)]
pub const fn istr (& self) -> & ISTR { & self . istr } # [doc = "0x48 - frame number register"]
# [inline (always)]
pub const fn fnr (& self) -> & FNR { & self . fnr } # [doc = "0x4c - device address"]
# [inline (always)]
pub const fn daddr (& self) -> & DADDR { & self . daddr } # [doc = "0x50 - Buffer table address"]
# [inline (always)]
pub const fn btable (& self) -> & BTABLE { & self . btable } } # [doc = "EP0R (rw) register accessor: endpoint 0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep0r::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep0r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ep0r`]
module"]
pub type EP0R = crate :: Reg < ep0r :: EP0R_SPEC > ; # [doc = "endpoint 0 register"]
pub mod ep0r { # [doc = "Register `EP0R` reader"]
pub type R = crate :: R < EP0R_SPEC > ; # [doc = "Register `EP0R` writer"]
pub type W = crate :: W < EP0R_SPEC > ; # [doc = "Field `EA` reader - Endpoint address"]
pub type EA_R = crate :: FieldReader ; # [doc = "Field `EA` writer - Endpoint address"]
pub type EA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `STAT_TX` reader - Status bits, for transmission transfers"]
pub type STAT_TX_R = crate :: FieldReader ; # [doc = "Field `STAT_TX` writer - Status bits, for transmission transfers"]
pub type STAT_TX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_TX` reader - Data Toggle, for transmission transfers"]
pub type DTOG_TX_R = crate :: BitReader ; # [doc = "Field `DTOG_TX` writer - Data Toggle, for transmission transfers"]
pub type DTOG_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_TX` reader - Correct Transfer for transmission"]
pub type CTR_TX_R = crate :: BitReader ; # [doc = "Field `CTR_TX` writer - Correct Transfer for transmission"]
pub type CTR_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_KIND` reader - Endpoint kind"]
pub type EP_KIND_R = crate :: BitReader ; # [doc = "Field `EP_KIND` writer - Endpoint kind"]
pub type EP_KIND_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_TYPE` reader - Endpoint type"]
pub type EP_TYPE_R = crate :: FieldReader ; # [doc = "Field `EP_TYPE` writer - Endpoint type"]
pub type EP_TYPE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SETUP` reader - Setup transaction completed"]
pub type SETUP_R = crate :: BitReader ; # [doc = "Field `SETUP` writer - Setup transaction completed"]
pub type SETUP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STAT_RX` reader - Status bits, for reception transfers"]
pub type STAT_RX_R = crate :: FieldReader ; # [doc = "Field `STAT_RX` writer - Status bits, for reception transfers"]
pub type STAT_RX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_RX` reader - Data Toggle, for reception transfers"]
pub type DTOG_RX_R = crate :: BitReader ; # [doc = "Field `DTOG_RX` writer - Data Toggle, for reception transfers"]
pub type DTOG_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_RX` reader - Correct transfer for reception"]
pub type CTR_RX_R = crate :: BitReader ; # [doc = "Field `CTR_RX` writer - Correct transfer for reception"]
pub type CTR_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
pub fn ea (& self) -> EA_R { EA_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
pub fn stat_tx (& self) -> STAT_TX_R { STAT_TX_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
pub fn dtog_tx (& self) -> DTOG_TX_R { DTOG_TX_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
pub fn ctr_tx (& self) -> CTR_TX_R { CTR_TX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
pub fn ep_kind (& self) -> EP_KIND_R { EP_KIND_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
pub fn ep_type (& self) -> EP_TYPE_R { EP_TYPE_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
pub fn setup (& self) -> SETUP_R { SETUP_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
pub fn stat_rx (& self) -> STAT_RX_R { STAT_RX_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
pub fn dtog_rx (& self) -> DTOG_RX_R { DTOG_RX_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
pub fn ctr_rx (& self) -> CTR_RX_R { CTR_RX_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
# [must_use]
pub fn ea (& mut self) -> EA_W < EP0R_SPEC > { EA_W :: new (self , 0) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn stat_tx (& mut self) -> STAT_TX_W < EP0R_SPEC > { STAT_TX_W :: new (self , 4) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_tx (& mut self) -> DTOG_TX_W < EP0R_SPEC > { DTOG_TX_W :: new (self , 6) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
# [must_use]
pub fn ctr_tx (& mut self) -> CTR_TX_W < EP0R_SPEC > { CTR_TX_W :: new (self , 7) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
# [must_use]
pub fn ep_kind (& mut self) -> EP_KIND_W < EP0R_SPEC > { EP_KIND_W :: new (self , 8) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
# [must_use]
pub fn ep_type (& mut self) -> EP_TYPE_W < EP0R_SPEC > { EP_TYPE_W :: new (self , 9) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
# [must_use]
pub fn setup (& mut self) -> SETUP_W < EP0R_SPEC > { SETUP_W :: new (self , 11) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn stat_rx (& mut self) -> STAT_RX_W < EP0R_SPEC > { STAT_RX_W :: new (self , 12) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_rx (& mut self) -> DTOG_RX_W < EP0R_SPEC > { DTOG_RX_W :: new (self , 14) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
# [must_use]
pub fn ctr_rx (& mut self) -> CTR_RX_W < EP0R_SPEC > { CTR_RX_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep0r::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep0r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EP0R_SPEC ; impl crate :: RegisterSpec for EP0R_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`ep0r::R`](R) reader structure"]
impl crate :: Readable for EP0R_SPEC { } # [doc = "`write(|w| ..)` method takes [`ep0r::W`](W) writer structure"]
impl crate :: Writable for EP0R_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets EP0R to value 0"]
impl crate :: Resettable for EP0R_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "EP1R (rw) register accessor: endpoint 1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep1r::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep1r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ep1r`]
module"]
pub type EP1R = crate :: Reg < ep1r :: EP1R_SPEC > ; # [doc = "endpoint 1 register"]
pub mod ep1r { # [doc = "Register `EP1R` reader"]
pub type R = crate :: R < EP1R_SPEC > ; # [doc = "Register `EP1R` writer"]
pub type W = crate :: W < EP1R_SPEC > ; # [doc = "Field `EA` reader - Endpoint address"]
pub type EA_R = crate :: FieldReader ; # [doc = "Field `EA` writer - Endpoint address"]
pub type EA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `STAT_TX` reader - Status bits, for transmission transfers"]
pub type STAT_TX_R = crate :: FieldReader ; # [doc = "Field `STAT_TX` writer - Status bits, for transmission transfers"]
pub type STAT_TX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_TX` reader - Data Toggle, for transmission transfers"]
pub type DTOG_TX_R = crate :: BitReader ; # [doc = "Field `DTOG_TX` writer - Data Toggle, for transmission transfers"]
pub type DTOG_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_TX` reader - Correct Transfer for transmission"]
pub type CTR_TX_R = crate :: BitReader ; # [doc = "Field `CTR_TX` writer - Correct Transfer for transmission"]
pub type CTR_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_KIND` reader - Endpoint kind"]
pub type EP_KIND_R = crate :: BitReader ; # [doc = "Field `EP_KIND` writer - Endpoint kind"]
pub type EP_KIND_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_TYPE` reader - Endpoint type"]
pub type EP_TYPE_R = crate :: FieldReader ; # [doc = "Field `EP_TYPE` writer - Endpoint type"]
pub type EP_TYPE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SETUP` reader - Setup transaction completed"]
pub type SETUP_R = crate :: BitReader ; # [doc = "Field `SETUP` writer - Setup transaction completed"]
pub type SETUP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STAT_RX` reader - Status bits, for reception transfers"]
pub type STAT_RX_R = crate :: FieldReader ; # [doc = "Field `STAT_RX` writer - Status bits, for reception transfers"]
pub type STAT_RX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_RX` reader - Data Toggle, for reception transfers"]
pub type DTOG_RX_R = crate :: BitReader ; # [doc = "Field `DTOG_RX` writer - Data Toggle, for reception transfers"]
pub type DTOG_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_RX` reader - Correct transfer for reception"]
pub type CTR_RX_R = crate :: BitReader ; # [doc = "Field `CTR_RX` writer - Correct transfer for reception"]
pub type CTR_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
pub fn ea (& self) -> EA_R { EA_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
pub fn stat_tx (& self) -> STAT_TX_R { STAT_TX_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
pub fn dtog_tx (& self) -> DTOG_TX_R { DTOG_TX_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
pub fn ctr_tx (& self) -> CTR_TX_R { CTR_TX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
pub fn ep_kind (& self) -> EP_KIND_R { EP_KIND_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
pub fn ep_type (& self) -> EP_TYPE_R { EP_TYPE_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
pub fn setup (& self) -> SETUP_R { SETUP_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
pub fn stat_rx (& self) -> STAT_RX_R { STAT_RX_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
pub fn dtog_rx (& self) -> DTOG_RX_R { DTOG_RX_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
pub fn ctr_rx (& self) -> CTR_RX_R { CTR_RX_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
# [must_use]
pub fn ea (& mut self) -> EA_W < EP1R_SPEC > { EA_W :: new (self , 0) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn stat_tx (& mut self) -> STAT_TX_W < EP1R_SPEC > { STAT_TX_W :: new (self , 4) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_tx (& mut self) -> DTOG_TX_W < EP1R_SPEC > { DTOG_TX_W :: new (self , 6) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
# [must_use]
pub fn ctr_tx (& mut self) -> CTR_TX_W < EP1R_SPEC > { CTR_TX_W :: new (self , 7) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
# [must_use]
pub fn ep_kind (& mut self) -> EP_KIND_W < EP1R_SPEC > { EP_KIND_W :: new (self , 8) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
# [must_use]
pub fn ep_type (& mut self) -> EP_TYPE_W < EP1R_SPEC > { EP_TYPE_W :: new (self , 9) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
# [must_use]
pub fn setup (& mut self) -> SETUP_W < EP1R_SPEC > { SETUP_W :: new (self , 11) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn stat_rx (& mut self) -> STAT_RX_W < EP1R_SPEC > { STAT_RX_W :: new (self , 12) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_rx (& mut self) -> DTOG_RX_W < EP1R_SPEC > { DTOG_RX_W :: new (self , 14) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
# [must_use]
pub fn ctr_rx (& mut self) -> CTR_RX_W < EP1R_SPEC > { CTR_RX_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep1r::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep1r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EP1R_SPEC ; impl crate :: RegisterSpec for EP1R_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`ep1r::R`](R) reader structure"]
impl crate :: Readable for EP1R_SPEC { } # [doc = "`write(|w| ..)` method takes [`ep1r::W`](W) writer structure"]
impl crate :: Writable for EP1R_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets EP1R to value 0"]
impl crate :: Resettable for EP1R_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "EP2R (rw) register accessor: endpoint 2 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep2r::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep2r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ep2r`]
module"]
pub type EP2R = crate :: Reg < ep2r :: EP2R_SPEC > ; # [doc = "endpoint 2 register"]
pub mod ep2r { # [doc = "Register `EP2R` reader"]
pub type R = crate :: R < EP2R_SPEC > ; # [doc = "Register `EP2R` writer"]
pub type W = crate :: W < EP2R_SPEC > ; # [doc = "Field `EA` reader - Endpoint address"]
pub type EA_R = crate :: FieldReader ; # [doc = "Field `EA` writer - Endpoint address"]
pub type EA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `STAT_TX` reader - Status bits, for transmission transfers"]
pub type STAT_TX_R = crate :: FieldReader ; # [doc = "Field `STAT_TX` writer - Status bits, for transmission transfers"]
pub type STAT_TX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_TX` reader - Data Toggle, for transmission transfers"]
pub type DTOG_TX_R = crate :: BitReader ; # [doc = "Field `DTOG_TX` writer - Data Toggle, for transmission transfers"]
pub type DTOG_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_TX` reader - Correct Transfer for transmission"]
pub type CTR_TX_R = crate :: BitReader ; # [doc = "Field `CTR_TX` writer - Correct Transfer for transmission"]
pub type CTR_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_KIND` reader - Endpoint kind"]
pub type EP_KIND_R = crate :: BitReader ; # [doc = "Field `EP_KIND` writer - Endpoint kind"]
pub type EP_KIND_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_TYPE` reader - Endpoint type"]
pub type EP_TYPE_R = crate :: FieldReader ; # [doc = "Field `EP_TYPE` writer - Endpoint type"]
pub type EP_TYPE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SETUP` reader - Setup transaction completed"]
pub type SETUP_R = crate :: BitReader ; # [doc = "Field `SETUP` writer - Setup transaction completed"]
pub type SETUP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STAT_RX` reader - Status bits, for reception transfers"]
pub type STAT_RX_R = crate :: FieldReader ; # [doc = "Field `STAT_RX` writer - Status bits, for reception transfers"]
pub type STAT_RX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_RX` reader - Data Toggle, for reception transfers"]
pub type DTOG_RX_R = crate :: BitReader ; # [doc = "Field `DTOG_RX` writer - Data Toggle, for reception transfers"]
pub type DTOG_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_RX` reader - Correct transfer for reception"]
pub type CTR_RX_R = crate :: BitReader ; # [doc = "Field `CTR_RX` writer - Correct transfer for reception"]
pub type CTR_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
pub fn ea (& self) -> EA_R { EA_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
pub fn stat_tx (& self) -> STAT_TX_R { STAT_TX_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
pub fn dtog_tx (& self) -> DTOG_TX_R { DTOG_TX_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
pub fn ctr_tx (& self) -> CTR_TX_R { CTR_TX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
pub fn ep_kind (& self) -> EP_KIND_R { EP_KIND_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
pub fn ep_type (& self) -> EP_TYPE_R { EP_TYPE_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
pub fn setup (& self) -> SETUP_R { SETUP_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
pub fn stat_rx (& self) -> STAT_RX_R { STAT_RX_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
pub fn dtog_rx (& self) -> DTOG_RX_R { DTOG_RX_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
pub fn ctr_rx (& self) -> CTR_RX_R { CTR_RX_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
# [must_use]
pub fn ea (& mut self) -> EA_W < EP2R_SPEC > { EA_W :: new (self , 0) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn stat_tx (& mut self) -> STAT_TX_W < EP2R_SPEC > { STAT_TX_W :: new (self , 4) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_tx (& mut self) -> DTOG_TX_W < EP2R_SPEC > { DTOG_TX_W :: new (self , 6) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
# [must_use]
pub fn ctr_tx (& mut self) -> CTR_TX_W < EP2R_SPEC > { CTR_TX_W :: new (self , 7) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
# [must_use]
pub fn ep_kind (& mut self) -> EP_KIND_W < EP2R_SPEC > { EP_KIND_W :: new (self , 8) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
# [must_use]
pub fn ep_type (& mut self) -> EP_TYPE_W < EP2R_SPEC > { EP_TYPE_W :: new (self , 9) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
# [must_use]
pub fn setup (& mut self) -> SETUP_W < EP2R_SPEC > { SETUP_W :: new (self , 11) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn stat_rx (& mut self) -> STAT_RX_W < EP2R_SPEC > { STAT_RX_W :: new (self , 12) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_rx (& mut self) -> DTOG_RX_W < EP2R_SPEC > { DTOG_RX_W :: new (self , 14) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
# [must_use]
pub fn ctr_rx (& mut self) -> CTR_RX_W < EP2R_SPEC > { CTR_RX_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 2 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep2r::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep2r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EP2R_SPEC ; impl crate :: RegisterSpec for EP2R_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`ep2r::R`](R) reader structure"]
impl crate :: Readable for EP2R_SPEC { } # [doc = "`write(|w| ..)` method takes [`ep2r::W`](W) writer structure"]
impl crate :: Writable for EP2R_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets EP2R to value 0"]
impl crate :: Resettable for EP2R_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "EP3R (rw) register accessor: endpoint 3 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep3r::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep3r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ep3r`]
module"]
pub type EP3R = crate :: Reg < ep3r :: EP3R_SPEC > ; # [doc = "endpoint 3 register"]
pub mod ep3r { # [doc = "Register `EP3R` reader"]
pub type R = crate :: R < EP3R_SPEC > ; # [doc = "Register `EP3R` writer"]
pub type W = crate :: W < EP3R_SPEC > ; # [doc = "Field `EA` reader - Endpoint address"]
pub type EA_R = crate :: FieldReader ; # [doc = "Field `EA` writer - Endpoint address"]
pub type EA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `STAT_TX` reader - Status bits, for transmission transfers"]
pub type STAT_TX_R = crate :: FieldReader ; # [doc = "Field `STAT_TX` writer - Status bits, for transmission transfers"]
pub type STAT_TX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_TX` reader - Data Toggle, for transmission transfers"]
pub type DTOG_TX_R = crate :: BitReader ; # [doc = "Field `DTOG_TX` writer - Data Toggle, for transmission transfers"]
pub type DTOG_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_TX` reader - Correct Transfer for transmission"]
pub type CTR_TX_R = crate :: BitReader ; # [doc = "Field `CTR_TX` writer - Correct Transfer for transmission"]
pub type CTR_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_KIND` reader - Endpoint kind"]
pub type EP_KIND_R = crate :: BitReader ; # [doc = "Field `EP_KIND` writer - Endpoint kind"]
pub type EP_KIND_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_TYPE` reader - Endpoint type"]
pub type EP_TYPE_R = crate :: FieldReader ; # [doc = "Field `EP_TYPE` writer - Endpoint type"]
pub type EP_TYPE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SETUP` reader - Setup transaction completed"]
pub type SETUP_R = crate :: BitReader ; # [doc = "Field `SETUP` writer - Setup transaction completed"]
pub type SETUP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STAT_RX` reader - Status bits, for reception transfers"]
pub type STAT_RX_R = crate :: FieldReader ; # [doc = "Field `STAT_RX` writer - Status bits, for reception transfers"]
pub type STAT_RX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_RX` reader - Data Toggle, for reception transfers"]
pub type DTOG_RX_R = crate :: BitReader ; # [doc = "Field `DTOG_RX` writer - Data Toggle, for reception transfers"]
pub type DTOG_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_RX` reader - Correct transfer for reception"]
pub type CTR_RX_R = crate :: BitReader ; # [doc = "Field `CTR_RX` writer - Correct transfer for reception"]
pub type CTR_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
pub fn ea (& self) -> EA_R { EA_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
pub fn stat_tx (& self) -> STAT_TX_R { STAT_TX_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
pub fn dtog_tx (& self) -> DTOG_TX_R { DTOG_TX_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
pub fn ctr_tx (& self) -> CTR_TX_R { CTR_TX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
pub fn ep_kind (& self) -> EP_KIND_R { EP_KIND_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
pub fn ep_type (& self) -> EP_TYPE_R { EP_TYPE_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
pub fn setup (& self) -> SETUP_R { SETUP_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
pub fn stat_rx (& self) -> STAT_RX_R { STAT_RX_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
pub fn dtog_rx (& self) -> DTOG_RX_R { DTOG_RX_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
pub fn ctr_rx (& self) -> CTR_RX_R { CTR_RX_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
# [must_use]
pub fn ea (& mut self) -> EA_W < EP3R_SPEC > { EA_W :: new (self , 0) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn stat_tx (& mut self) -> STAT_TX_W < EP3R_SPEC > { STAT_TX_W :: new (self , 4) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_tx (& mut self) -> DTOG_TX_W < EP3R_SPEC > { DTOG_TX_W :: new (self , 6) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
# [must_use]
pub fn ctr_tx (& mut self) -> CTR_TX_W < EP3R_SPEC > { CTR_TX_W :: new (self , 7) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
# [must_use]
pub fn ep_kind (& mut self) -> EP_KIND_W < EP3R_SPEC > { EP_KIND_W :: new (self , 8) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
# [must_use]
pub fn ep_type (& mut self) -> EP_TYPE_W < EP3R_SPEC > { EP_TYPE_W :: new (self , 9) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
# [must_use]
pub fn setup (& mut self) -> SETUP_W < EP3R_SPEC > { SETUP_W :: new (self , 11) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn stat_rx (& mut self) -> STAT_RX_W < EP3R_SPEC > { STAT_RX_W :: new (self , 12) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_rx (& mut self) -> DTOG_RX_W < EP3R_SPEC > { DTOG_RX_W :: new (self , 14) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
# [must_use]
pub fn ctr_rx (& mut self) -> CTR_RX_W < EP3R_SPEC > { CTR_RX_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 3 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep3r::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep3r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EP3R_SPEC ; impl crate :: RegisterSpec for EP3R_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`ep3r::R`](R) reader structure"]
impl crate :: Readable for EP3R_SPEC { } # [doc = "`write(|w| ..)` method takes [`ep3r::W`](W) writer structure"]
impl crate :: Writable for EP3R_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets EP3R to value 0"]
impl crate :: Resettable for EP3R_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "EP4R (rw) register accessor: endpoint 4 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep4r::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep4r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ep4r`]
module"]
pub type EP4R = crate :: Reg < ep4r :: EP4R_SPEC > ; # [doc = "endpoint 4 register"]
pub mod ep4r { # [doc = "Register `EP4R` reader"]
pub type R = crate :: R < EP4R_SPEC > ; # [doc = "Register `EP4R` writer"]
pub type W = crate :: W < EP4R_SPEC > ; # [doc = "Field `EA` reader - Endpoint address"]
pub type EA_R = crate :: FieldReader ; # [doc = "Field `EA` writer - Endpoint address"]
pub type EA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `STAT_TX` reader - Status bits, for transmission transfers"]
pub type STAT_TX_R = crate :: FieldReader ; # [doc = "Field `STAT_TX` writer - Status bits, for transmission transfers"]
pub type STAT_TX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_TX` reader - Data Toggle, for transmission transfers"]
pub type DTOG_TX_R = crate :: BitReader ; # [doc = "Field `DTOG_TX` writer - Data Toggle, for transmission transfers"]
pub type DTOG_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_TX` reader - Correct Transfer for transmission"]
pub type CTR_TX_R = crate :: BitReader ; # [doc = "Field `CTR_TX` writer - Correct Transfer for transmission"]
pub type CTR_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_KIND` reader - Endpoint kind"]
pub type EP_KIND_R = crate :: BitReader ; # [doc = "Field `EP_KIND` writer - Endpoint kind"]
pub type EP_KIND_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_TYPE` reader - Endpoint type"]
pub type EP_TYPE_R = crate :: FieldReader ; # [doc = "Field `EP_TYPE` writer - Endpoint type"]
pub type EP_TYPE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SETUP` reader - Setup transaction completed"]
pub type SETUP_R = crate :: BitReader ; # [doc = "Field `SETUP` writer - Setup transaction completed"]
pub type SETUP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STAT_RX` reader - Status bits, for reception transfers"]
pub type STAT_RX_R = crate :: FieldReader ; # [doc = "Field `STAT_RX` writer - Status bits, for reception transfers"]
pub type STAT_RX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_RX` reader - Data Toggle, for reception transfers"]
pub type DTOG_RX_R = crate :: BitReader ; # [doc = "Field `DTOG_RX` writer - Data Toggle, for reception transfers"]
pub type DTOG_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_RX` reader - Correct transfer for reception"]
pub type CTR_RX_R = crate :: BitReader ; # [doc = "Field `CTR_RX` writer - Correct transfer for reception"]
pub type CTR_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
pub fn ea (& self) -> EA_R { EA_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
pub fn stat_tx (& self) -> STAT_TX_R { STAT_TX_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
pub fn dtog_tx (& self) -> DTOG_TX_R { DTOG_TX_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
pub fn ctr_tx (& self) -> CTR_TX_R { CTR_TX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
pub fn ep_kind (& self) -> EP_KIND_R { EP_KIND_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
pub fn ep_type (& self) -> EP_TYPE_R { EP_TYPE_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
pub fn setup (& self) -> SETUP_R { SETUP_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
pub fn stat_rx (& self) -> STAT_RX_R { STAT_RX_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
pub fn dtog_rx (& self) -> DTOG_RX_R { DTOG_RX_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
pub fn ctr_rx (& self) -> CTR_RX_R { CTR_RX_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
# [must_use]
pub fn ea (& mut self) -> EA_W < EP4R_SPEC > { EA_W :: new (self , 0) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn stat_tx (& mut self) -> STAT_TX_W < EP4R_SPEC > { STAT_TX_W :: new (self , 4) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_tx (& mut self) -> DTOG_TX_W < EP4R_SPEC > { DTOG_TX_W :: new (self , 6) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
# [must_use]
pub fn ctr_tx (& mut self) -> CTR_TX_W < EP4R_SPEC > { CTR_TX_W :: new (self , 7) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
# [must_use]
pub fn ep_kind (& mut self) -> EP_KIND_W < EP4R_SPEC > { EP_KIND_W :: new (self , 8) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
# [must_use]
pub fn ep_type (& mut self) -> EP_TYPE_W < EP4R_SPEC > { EP_TYPE_W :: new (self , 9) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
# [must_use]
pub fn setup (& mut self) -> SETUP_W < EP4R_SPEC > { SETUP_W :: new (self , 11) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn stat_rx (& mut self) -> STAT_RX_W < EP4R_SPEC > { STAT_RX_W :: new (self , 12) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_rx (& mut self) -> DTOG_RX_W < EP4R_SPEC > { DTOG_RX_W :: new (self , 14) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
# [must_use]
pub fn ctr_rx (& mut self) -> CTR_RX_W < EP4R_SPEC > { CTR_RX_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 4 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep4r::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep4r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EP4R_SPEC ; impl crate :: RegisterSpec for EP4R_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`ep4r::R`](R) reader structure"]
impl crate :: Readable for EP4R_SPEC { } # [doc = "`write(|w| ..)` method takes [`ep4r::W`](W) writer structure"]
impl crate :: Writable for EP4R_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets EP4R to value 0"]
impl crate :: Resettable for EP4R_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "EP5R (rw) register accessor: endpoint 5 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep5r::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep5r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ep5r`]
module"]
pub type EP5R = crate :: Reg < ep5r :: EP5R_SPEC > ; # [doc = "endpoint 5 register"]
pub mod ep5r { # [doc = "Register `EP5R` reader"]
pub type R = crate :: R < EP5R_SPEC > ; # [doc = "Register `EP5R` writer"]
pub type W = crate :: W < EP5R_SPEC > ; # [doc = "Field `EA` reader - Endpoint address"]
pub type EA_R = crate :: FieldReader ; # [doc = "Field `EA` writer - Endpoint address"]
pub type EA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `STAT_TX` reader - Status bits, for transmission transfers"]
pub type STAT_TX_R = crate :: FieldReader ; # [doc = "Field `STAT_TX` writer - Status bits, for transmission transfers"]
pub type STAT_TX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_TX` reader - Data Toggle, for transmission transfers"]
pub type DTOG_TX_R = crate :: BitReader ; # [doc = "Field `DTOG_TX` writer - Data Toggle, for transmission transfers"]
pub type DTOG_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_TX` reader - Correct Transfer for transmission"]
pub type CTR_TX_R = crate :: BitReader ; # [doc = "Field `CTR_TX` writer - Correct Transfer for transmission"]
pub type CTR_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_KIND` reader - Endpoint kind"]
pub type EP_KIND_R = crate :: BitReader ; # [doc = "Field `EP_KIND` writer - Endpoint kind"]
pub type EP_KIND_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_TYPE` reader - Endpoint type"]
pub type EP_TYPE_R = crate :: FieldReader ; # [doc = "Field `EP_TYPE` writer - Endpoint type"]
pub type EP_TYPE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SETUP` reader - Setup transaction completed"]
pub type SETUP_R = crate :: BitReader ; # [doc = "Field `SETUP` writer - Setup transaction completed"]
pub type SETUP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STAT_RX` reader - Status bits, for reception transfers"]
pub type STAT_RX_R = crate :: FieldReader ; # [doc = "Field `STAT_RX` writer - Status bits, for reception transfers"]
pub type STAT_RX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_RX` reader - Data Toggle, for reception transfers"]
pub type DTOG_RX_R = crate :: BitReader ; # [doc = "Field `DTOG_RX` writer - Data Toggle, for reception transfers"]
pub type DTOG_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_RX` reader - Correct transfer for reception"]
pub type CTR_RX_R = crate :: BitReader ; # [doc = "Field `CTR_RX` writer - Correct transfer for reception"]
pub type CTR_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
pub fn ea (& self) -> EA_R { EA_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
pub fn stat_tx (& self) -> STAT_TX_R { STAT_TX_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
pub fn dtog_tx (& self) -> DTOG_TX_R { DTOG_TX_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
pub fn ctr_tx (& self) -> CTR_TX_R { CTR_TX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
pub fn ep_kind (& self) -> EP_KIND_R { EP_KIND_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
pub fn ep_type (& self) -> EP_TYPE_R { EP_TYPE_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
pub fn setup (& self) -> SETUP_R { SETUP_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
pub fn stat_rx (& self) -> STAT_RX_R { STAT_RX_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
pub fn dtog_rx (& self) -> DTOG_RX_R { DTOG_RX_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
pub fn ctr_rx (& self) -> CTR_RX_R { CTR_RX_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
# [must_use]
pub fn ea (& mut self) -> EA_W < EP5R_SPEC > { EA_W :: new (self , 0) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn stat_tx (& mut self) -> STAT_TX_W < EP5R_SPEC > { STAT_TX_W :: new (self , 4) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_tx (& mut self) -> DTOG_TX_W < EP5R_SPEC > { DTOG_TX_W :: new (self , 6) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
# [must_use]
pub fn ctr_tx (& mut self) -> CTR_TX_W < EP5R_SPEC > { CTR_TX_W :: new (self , 7) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
# [must_use]
pub fn ep_kind (& mut self) -> EP_KIND_W < EP5R_SPEC > { EP_KIND_W :: new (self , 8) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
# [must_use]
pub fn ep_type (& mut self) -> EP_TYPE_W < EP5R_SPEC > { EP_TYPE_W :: new (self , 9) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
# [must_use]
pub fn setup (& mut self) -> SETUP_W < EP5R_SPEC > { SETUP_W :: new (self , 11) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn stat_rx (& mut self) -> STAT_RX_W < EP5R_SPEC > { STAT_RX_W :: new (self , 12) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_rx (& mut self) -> DTOG_RX_W < EP5R_SPEC > { DTOG_RX_W :: new (self , 14) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
# [must_use]
pub fn ctr_rx (& mut self) -> CTR_RX_W < EP5R_SPEC > { CTR_RX_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 5 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep5r::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep5r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EP5R_SPEC ; impl crate :: RegisterSpec for EP5R_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`ep5r::R`](R) reader structure"]
impl crate :: Readable for EP5R_SPEC { } # [doc = "`write(|w| ..)` method takes [`ep5r::W`](W) writer structure"]
impl crate :: Writable for EP5R_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets EP5R to value 0"]
impl crate :: Resettable for EP5R_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "EP6R (rw) register accessor: endpoint 6 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep6r::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep6r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ep6r`]
module"]
pub type EP6R = crate :: Reg < ep6r :: EP6R_SPEC > ; # [doc = "endpoint 6 register"]
pub mod ep6r { # [doc = "Register `EP6R` reader"]
pub type R = crate :: R < EP6R_SPEC > ; # [doc = "Register `EP6R` writer"]
pub type W = crate :: W < EP6R_SPEC > ; # [doc = "Field `EA` reader - Endpoint address"]
pub type EA_R = crate :: FieldReader ; # [doc = "Field `EA` writer - Endpoint address"]
pub type EA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `STAT_TX` reader - Status bits, for transmission transfers"]
pub type STAT_TX_R = crate :: FieldReader ; # [doc = "Field `STAT_TX` writer - Status bits, for transmission transfers"]
pub type STAT_TX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_TX` reader - Data Toggle, for transmission transfers"]
pub type DTOG_TX_R = crate :: BitReader ; # [doc = "Field `DTOG_TX` writer - Data Toggle, for transmission transfers"]
pub type DTOG_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_TX` reader - Correct Transfer for transmission"]
pub type CTR_TX_R = crate :: BitReader ; # [doc = "Field `CTR_TX` writer - Correct Transfer for transmission"]
pub type CTR_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_KIND` reader - Endpoint kind"]
pub type EP_KIND_R = crate :: BitReader ; # [doc = "Field `EP_KIND` writer - Endpoint kind"]
pub type EP_KIND_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_TYPE` reader - Endpoint type"]
pub type EP_TYPE_R = crate :: FieldReader ; # [doc = "Field `EP_TYPE` writer - Endpoint type"]
pub type EP_TYPE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SETUP` reader - Setup transaction completed"]
pub type SETUP_R = crate :: BitReader ; # [doc = "Field `SETUP` writer - Setup transaction completed"]
pub type SETUP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STAT_RX` reader - Status bits, for reception transfers"]
pub type STAT_RX_R = crate :: FieldReader ; # [doc = "Field `STAT_RX` writer - Status bits, for reception transfers"]
pub type STAT_RX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_RX` reader - Data Toggle, for reception transfers"]
pub type DTOG_RX_R = crate :: BitReader ; # [doc = "Field `DTOG_RX` writer - Data Toggle, for reception transfers"]
pub type DTOG_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_RX` reader - Correct transfer for reception"]
pub type CTR_RX_R = crate :: BitReader ; # [doc = "Field `CTR_RX` writer - Correct transfer for reception"]
pub type CTR_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
pub fn ea (& self) -> EA_R { EA_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
pub fn stat_tx (& self) -> STAT_TX_R { STAT_TX_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
pub fn dtog_tx (& self) -> DTOG_TX_R { DTOG_TX_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
pub fn ctr_tx (& self) -> CTR_TX_R { CTR_TX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
pub fn ep_kind (& self) -> EP_KIND_R { EP_KIND_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
pub fn ep_type (& self) -> EP_TYPE_R { EP_TYPE_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
pub fn setup (& self) -> SETUP_R { SETUP_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
pub fn stat_rx (& self) -> STAT_RX_R { STAT_RX_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
pub fn dtog_rx (& self) -> DTOG_RX_R { DTOG_RX_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
pub fn ctr_rx (& self) -> CTR_RX_R { CTR_RX_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
# [must_use]
pub fn ea (& mut self) -> EA_W < EP6R_SPEC > { EA_W :: new (self , 0) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn stat_tx (& mut self) -> STAT_TX_W < EP6R_SPEC > { STAT_TX_W :: new (self , 4) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_tx (& mut self) -> DTOG_TX_W < EP6R_SPEC > { DTOG_TX_W :: new (self , 6) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
# [must_use]
pub fn ctr_tx (& mut self) -> CTR_TX_W < EP6R_SPEC > { CTR_TX_W :: new (self , 7) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
# [must_use]
pub fn ep_kind (& mut self) -> EP_KIND_W < EP6R_SPEC > { EP_KIND_W :: new (self , 8) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
# [must_use]
pub fn ep_type (& mut self) -> EP_TYPE_W < EP6R_SPEC > { EP_TYPE_W :: new (self , 9) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
# [must_use]
pub fn setup (& mut self) -> SETUP_W < EP6R_SPEC > { SETUP_W :: new (self , 11) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn stat_rx (& mut self) -> STAT_RX_W < EP6R_SPEC > { STAT_RX_W :: new (self , 12) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_rx (& mut self) -> DTOG_RX_W < EP6R_SPEC > { DTOG_RX_W :: new (self , 14) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
# [must_use]
pub fn ctr_rx (& mut self) -> CTR_RX_W < EP6R_SPEC > { CTR_RX_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 6 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep6r::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep6r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EP6R_SPEC ; impl crate :: RegisterSpec for EP6R_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`ep6r::R`](R) reader structure"]
impl crate :: Readable for EP6R_SPEC { } # [doc = "`write(|w| ..)` method takes [`ep6r::W`](W) writer structure"]
impl crate :: Writable for EP6R_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets EP6R to value 0"]
impl crate :: Resettable for EP6R_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "EP7R (rw) register accessor: endpoint 7 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep7r::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep7r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ep7r`]
module"]
pub type EP7R = crate :: Reg < ep7r :: EP7R_SPEC > ; # [doc = "endpoint 7 register"]
pub mod ep7r { # [doc = "Register `EP7R` reader"]
pub type R = crate :: R < EP7R_SPEC > ; # [doc = "Register `EP7R` writer"]
pub type W = crate :: W < EP7R_SPEC > ; # [doc = "Field `EA` reader - Endpoint address"]
pub type EA_R = crate :: FieldReader ; # [doc = "Field `EA` writer - Endpoint address"]
pub type EA_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `STAT_TX` reader - Status bits, for transmission transfers"]
pub type STAT_TX_R = crate :: FieldReader ; # [doc = "Field `STAT_TX` writer - Status bits, for transmission transfers"]
pub type STAT_TX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_TX` reader - Data Toggle, for transmission transfers"]
pub type DTOG_TX_R = crate :: BitReader ; # [doc = "Field `DTOG_TX` writer - Data Toggle, for transmission transfers"]
pub type DTOG_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_TX` reader - Correct Transfer for transmission"]
pub type CTR_TX_R = crate :: BitReader ; # [doc = "Field `CTR_TX` writer - Correct Transfer for transmission"]
pub type CTR_TX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_KIND` reader - Endpoint kind"]
pub type EP_KIND_R = crate :: BitReader ; # [doc = "Field `EP_KIND` writer - Endpoint kind"]
pub type EP_KIND_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `EP_TYPE` reader - Endpoint type"]
pub type EP_TYPE_R = crate :: FieldReader ; # [doc = "Field `EP_TYPE` writer - Endpoint type"]
pub type EP_TYPE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `SETUP` reader - Setup transaction completed"]
pub type SETUP_R = crate :: BitReader ; # [doc = "Field `SETUP` writer - Setup transaction completed"]
pub type SETUP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `STAT_RX` reader - Status bits, for reception transfers"]
pub type STAT_RX_R = crate :: FieldReader ; # [doc = "Field `STAT_RX` writer - Status bits, for reception transfers"]
pub type STAT_RX_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 2 > ; # [doc = "Field `DTOG_RX` reader - Data Toggle, for reception transfers"]
pub type DTOG_RX_R = crate :: BitReader ; # [doc = "Field `DTOG_RX` writer - Data Toggle, for reception transfers"]
pub type DTOG_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR_RX` reader - Correct transfer for reception"]
pub type CTR_RX_R = crate :: BitReader ; # [doc = "Field `CTR_RX` writer - Correct transfer for reception"]
pub type CTR_RX_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
pub fn ea (& self) -> EA_R { EA_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
pub fn stat_tx (& self) -> STAT_TX_R { STAT_TX_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
pub fn dtog_tx (& self) -> DTOG_TX_R { DTOG_TX_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
pub fn ctr_tx (& self) -> CTR_TX_R { CTR_TX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
pub fn ep_kind (& self) -> EP_KIND_R { EP_KIND_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
pub fn ep_type (& self) -> EP_TYPE_R { EP_TYPE_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
pub fn setup (& self) -> SETUP_R { SETUP_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
pub fn stat_rx (& self) -> STAT_RX_R { STAT_RX_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
pub fn dtog_rx (& self) -> DTOG_RX_R { DTOG_RX_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
pub fn ctr_rx (& self) -> CTR_RX_R { CTR_RX_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Endpoint address"]
# [inline (always)]
# [must_use]
pub fn ea (& mut self) -> EA_W < EP7R_SPEC > { EA_W :: new (self , 0) } # [doc = "Bits 4:5 - Status bits, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn stat_tx (& mut self) -> STAT_TX_W < EP7R_SPEC > { STAT_TX_W :: new (self , 4) } # [doc = "Bit 6 - Data Toggle, for transmission transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_tx (& mut self) -> DTOG_TX_W < EP7R_SPEC > { DTOG_TX_W :: new (self , 6) } # [doc = "Bit 7 - Correct Transfer for transmission"]
# [inline (always)]
# [must_use]
pub fn ctr_tx (& mut self) -> CTR_TX_W < EP7R_SPEC > { CTR_TX_W :: new (self , 7) } # [doc = "Bit 8 - Endpoint kind"]
# [inline (always)]
# [must_use]
pub fn ep_kind (& mut self) -> EP_KIND_W < EP7R_SPEC > { EP_KIND_W :: new (self , 8) } # [doc = "Bits 9:10 - Endpoint type"]
# [inline (always)]
# [must_use]
pub fn ep_type (& mut self) -> EP_TYPE_W < EP7R_SPEC > { EP_TYPE_W :: new (self , 9) } # [doc = "Bit 11 - Setup transaction completed"]
# [inline (always)]
# [must_use]
pub fn setup (& mut self) -> SETUP_W < EP7R_SPEC > { SETUP_W :: new (self , 11) } # [doc = "Bits 12:13 - Status bits, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn stat_rx (& mut self) -> STAT_RX_W < EP7R_SPEC > { STAT_RX_W :: new (self , 12) } # [doc = "Bit 14 - Data Toggle, for reception transfers"]
# [inline (always)]
# [must_use]
pub fn dtog_rx (& mut self) -> DTOG_RX_W < EP7R_SPEC > { DTOG_RX_W :: new (self , 14) } # [doc = "Bit 15 - Correct transfer for reception"]
# [inline (always)]
# [must_use]
pub fn ctr_rx (& mut self) -> CTR_RX_W < EP7R_SPEC > { CTR_RX_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "endpoint 7 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep7r::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep7r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EP7R_SPEC ; impl crate :: RegisterSpec for EP7R_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`ep7r::R`](R) reader structure"]
impl crate :: Readable for EP7R_SPEC { } # [doc = "`write(|w| ..)` method takes [`ep7r::W`](W) writer structure"]
impl crate :: Writable for EP7R_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets EP7R to value 0"]
impl crate :: Resettable for EP7R_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "CNTR (rw) register accessor: control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntr`]
module"]
pub type CNTR = crate :: Reg < cntr :: CNTR_SPEC > ; # [doc = "control register"]
pub mod cntr { # [doc = "Register `CNTR` reader"]
pub type R = crate :: R < CNTR_SPEC > ; # [doc = "Register `CNTR` writer"]
pub type W = crate :: W < CNTR_SPEC > ; # [doc = "Field `FRES` reader - Force USB Reset"]
pub type FRES_R = crate :: BitReader ; # [doc = "Field `FRES` writer - Force USB Reset"]
pub type FRES_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PDWN` reader - Power down"]
pub type PDWN_R = crate :: BitReader ; # [doc = "Field `PDWN` writer - Power down"]
pub type PDWN_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `LPMODE` reader - Low-power mode"]
pub type LPMODE_R = crate :: BitReader ; # [doc = "Field `LPMODE` writer - Low-power mode"]
pub type LPMODE_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `FSUSP` reader - Force suspend"]
pub type FSUSP_R = crate :: BitReader ; # [doc = "Field `FSUSP` writer - Force suspend"]
pub type FSUSP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESUME` reader - Resume request"]
pub type RESUME_R = crate :: BitReader ; # [doc = "Field `RESUME` writer - Resume request"]
pub type RESUME_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESOFM` reader - Expected start of frame interrupt mask"]
pub type ESOFM_R = crate :: BitReader ; # [doc = "Field `ESOFM` writer - Expected start of frame interrupt mask"]
pub type ESOFM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SOFM` reader - Start of frame interrupt mask"]
pub type SOFM_R = crate :: BitReader ; # [doc = "Field `SOFM` writer - Start of frame interrupt mask"]
pub type SOFM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESETM` reader - USB reset interrupt mask"]
pub type RESETM_R = crate :: BitReader ; # [doc = "Field `RESETM` writer - USB reset interrupt mask"]
pub type RESETM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SUSPM` reader - Suspend mode interrupt mask"]
pub type SUSPM_R = crate :: BitReader ; # [doc = "Field `SUSPM` writer - Suspend mode interrupt mask"]
pub type SUSPM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WKUPM` reader - Wakeup interrupt mask"]
pub type WKUPM_R = crate :: BitReader ; # [doc = "Field `WKUPM` writer - Wakeup interrupt mask"]
pub type WKUPM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERRM` reader - Error interrupt mask"]
pub type ERRM_R = crate :: BitReader ; # [doc = "Field `ERRM` writer - Error interrupt mask"]
pub type ERRM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PMAOVRM` reader - Packet memory area over / underrun interrupt mask"]
pub type PMAOVRM_R = crate :: BitReader ; # [doc = "Field `PMAOVRM` writer - Packet memory area over / underrun interrupt mask"]
pub type PMAOVRM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTRM` reader - Correct transfer interrupt mask"]
pub type CTRM_R = crate :: BitReader ; # [doc = "Field `CTRM` writer - Correct transfer interrupt mask"]
pub type CTRM_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bit 0 - Force USB Reset"]
# [inline (always)]
pub fn fres (& self) -> FRES_R { FRES_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Power down"]
# [inline (always)]
pub fn pdwn (& self) -> PDWN_R { PDWN_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Low-power mode"]
# [inline (always)]
pub fn lpmode (& self) -> LPMODE_R { LPMODE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Force suspend"]
# [inline (always)]
pub fn fsusp (& self) -> FSUSP_R { FSUSP_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Resume request"]
# [inline (always)]
pub fn resume (& self) -> RESUME_R { RESUME_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 8 - Expected start of frame interrupt mask"]
# [inline (always)]
pub fn esofm (& self) -> ESOFM_R { ESOFM_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Start of frame interrupt mask"]
# [inline (always)]
pub fn sofm (& self) -> SOFM_R { SOFM_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - USB reset interrupt mask"]
# [inline (always)]
pub fn resetm (& self) -> RESETM_R { RESETM_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Suspend mode interrupt mask"]
# [inline (always)]
pub fn suspm (& self) -> SUSPM_R { SUSPM_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Wakeup interrupt mask"]
# [inline (always)]
pub fn wkupm (& self) -> WKUPM_R { WKUPM_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Error interrupt mask"]
# [inline (always)]
pub fn errm (& self) -> ERRM_R { ERRM_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Packet memory area over / underrun interrupt mask"]
# [inline (always)]
pub fn pmaovrm (& self) -> PMAOVRM_R { PMAOVRM_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Correct transfer interrupt mask"]
# [inline (always)]
pub fn ctrm (& self) -> CTRM_R { CTRM_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bit 0 - Force USB Reset"]
# [inline (always)]
# [must_use]
pub fn fres (& mut self) -> FRES_W < CNTR_SPEC > { FRES_W :: new (self , 0) } # [doc = "Bit 1 - Power down"]
# [inline (always)]
# [must_use]
pub fn pdwn (& mut self) -> PDWN_W < CNTR_SPEC > { PDWN_W :: new (self , 1) } # [doc = "Bit 2 - Low-power mode"]
# [inline (always)]
# [must_use]
pub fn lpmode (& mut self) -> LPMODE_W < CNTR_SPEC > { LPMODE_W :: new (self , 2) } # [doc = "Bit 3 - Force suspend"]
# [inline (always)]
# [must_use]
pub fn fsusp (& mut self) -> FSUSP_W < CNTR_SPEC > { FSUSP_W :: new (self , 3) } # [doc = "Bit 4 - Resume request"]
# [inline (always)]
# [must_use]
pub fn resume (& mut self) -> RESUME_W < CNTR_SPEC > { RESUME_W :: new (self , 4) } # [doc = "Bit 8 - Expected start of frame interrupt mask"]
# [inline (always)]
# [must_use]
pub fn esofm (& mut self) -> ESOFM_W < CNTR_SPEC > { ESOFM_W :: new (self , 8) } # [doc = "Bit 9 - Start of frame interrupt mask"]
# [inline (always)]
# [must_use]
pub fn sofm (& mut self) -> SOFM_W < CNTR_SPEC > { SOFM_W :: new (self , 9) } # [doc = "Bit 10 - USB reset interrupt mask"]
# [inline (always)]
# [must_use]
pub fn resetm (& mut self) -> RESETM_W < CNTR_SPEC > { RESETM_W :: new (self , 10) } # [doc = "Bit 11 - Suspend mode interrupt mask"]
# [inline (always)]
# [must_use]
pub fn suspm (& mut self) -> SUSPM_W < CNTR_SPEC > { SUSPM_W :: new (self , 11) } # [doc = "Bit 12 - Wakeup interrupt mask"]
# [inline (always)]
# [must_use]
pub fn wkupm (& mut self) -> WKUPM_W < CNTR_SPEC > { WKUPM_W :: new (self , 12) } # [doc = "Bit 13 - Error interrupt mask"]
# [inline (always)]
# [must_use]
pub fn errm (& mut self) -> ERRM_W < CNTR_SPEC > { ERRM_W :: new (self , 13) } # [doc = "Bit 14 - Packet memory area over / underrun interrupt mask"]
# [inline (always)]
# [must_use]
pub fn pmaovrm (& mut self) -> PMAOVRM_W < CNTR_SPEC > { PMAOVRM_W :: new (self , 14) } # [doc = "Bit 15 - Correct transfer interrupt mask"]
# [inline (always)]
# [must_use]
pub fn ctrm (& mut self) -> CTRM_W < CNTR_SPEC > { CTRM_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CNTR_SPEC ; impl crate :: RegisterSpec for CNTR_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`cntr::R`](R) reader structure"]
impl crate :: Readable for CNTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`cntr::W`](W) writer structure"]
impl crate :: Writable for CNTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets CNTR to value 0x03"]
impl crate :: Resettable for CNTR_SPEC { const RESET_VALUE : u16 = 0x03 ; } } # [doc = "ISTR (rw) register accessor: interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`istr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`istr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@istr`]
module"]
pub type ISTR = crate :: Reg < istr :: ISTR_SPEC > ; # [doc = "interrupt status register"]
pub mod istr { # [doc = "Register `ISTR` reader"]
pub type R = crate :: R < ISTR_SPEC > ; # [doc = "Register `ISTR` writer"]
pub type W = crate :: W < ISTR_SPEC > ; # [doc = "Field `EP_ID` reader - Endpoint Identifier"]
pub type EP_ID_R = crate :: FieldReader ; # [doc = "Field `EP_ID` writer - Endpoint Identifier"]
pub type EP_ID_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 4 > ; # [doc = "Field `DIR` reader - Direction of transaction"]
pub type DIR_R = crate :: BitReader ; # [doc = "Field `DIR` writer - Direction of transaction"]
pub type DIR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ESOF` reader - Expected start frame"]
pub type ESOF_R = crate :: BitReader ; # [doc = "Field `ESOF` writer - Expected start frame"]
pub type ESOF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SOF` reader - start of frame"]
pub type SOF_R = crate :: BitReader ; # [doc = "Field `SOF` writer - start of frame"]
pub type SOF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `RESET` reader - reset request"]
pub type RESET_R = crate :: BitReader ; # [doc = "Field `RESET` writer - reset request"]
pub type RESET_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `SUSP` reader - Suspend mode request"]
pub type SUSP_R = crate :: BitReader ; # [doc = "Field `SUSP` writer - Suspend mode request"]
pub type SUSP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `WKUP` reader - Wakeup"]
pub type WKUP_R = crate :: BitReader ; # [doc = "Field `WKUP` writer - Wakeup"]
pub type WKUP_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `ERR` reader - Error"]
pub type ERR_R = crate :: BitReader ; # [doc = "Field `ERR` writer - Error"]
pub type ERR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `PMAOVR` reader - Packet memory area over / underrun"]
pub type PMAOVR_R = crate :: BitReader ; # [doc = "Field `PMAOVR` writer - Packet memory area over / underrun"]
pub type PMAOVR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; # [doc = "Field `CTR` reader - Correct transfer"]
pub type CTR_R = crate :: BitReader ; # [doc = "Field `CTR` writer - Correct transfer"]
pub type CTR_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:3 - Endpoint Identifier"]
# [inline (always)]
pub fn ep_id (& self) -> EP_ID_R { EP_ID_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - Direction of transaction"]
# [inline (always)]
pub fn dir (& self) -> DIR_R { DIR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 8 - Expected start frame"]
# [inline (always)]
pub fn esof (& self) -> ESOF_R { ESOF_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - start of frame"]
# [inline (always)]
pub fn sof (& self) -> SOF_R { SOF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - reset request"]
# [inline (always)]
pub fn reset (& self) -> RESET_R { RESET_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Suspend mode request"]
# [inline (always)]
pub fn susp (& self) -> SUSP_R { SUSP_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Wakeup"]
# [inline (always)]
pub fn wkup (& self) -> WKUP_R { WKUP_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Error"]
# [inline (always)]
pub fn err (& self) -> ERR_R { ERR_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Packet memory area over / underrun"]
# [inline (always)]
pub fn pmaovr (& self) -> PMAOVR_R { PMAOVR_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Correct transfer"]
# [inline (always)]
pub fn ctr (& self) -> CTR_R { CTR_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Endpoint Identifier"]
# [inline (always)]
# [must_use]
pub fn ep_id (& mut self) -> EP_ID_W < ISTR_SPEC > { EP_ID_W :: new (self , 0) } # [doc = "Bit 4 - Direction of transaction"]
# [inline (always)]
# [must_use]
pub fn dir (& mut self) -> DIR_W < ISTR_SPEC > { DIR_W :: new (self , 4) } # [doc = "Bit 8 - Expected start frame"]
# [inline (always)]
# [must_use]
pub fn esof (& mut self) -> ESOF_W < ISTR_SPEC > { ESOF_W :: new (self , 8) } # [doc = "Bit 9 - start of frame"]
# [inline (always)]
# [must_use]
pub fn sof (& mut self) -> SOF_W < ISTR_SPEC > { SOF_W :: new (self , 9) } # [doc = "Bit 10 - reset request"]
# [inline (always)]
# [must_use]
pub fn reset (& mut self) -> RESET_W < ISTR_SPEC > { RESET_W :: new (self , 10) } # [doc = "Bit 11 - Suspend mode request"]
# [inline (always)]
# [must_use]
pub fn susp (& mut self) -> SUSP_W < ISTR_SPEC > { SUSP_W :: new (self , 11) } # [doc = "Bit 12 - Wakeup"]
# [inline (always)]
# [must_use]
pub fn wkup (& mut self) -> WKUP_W < ISTR_SPEC > { WKUP_W :: new (self , 12) } # [doc = "Bit 13 - Error"]
# [inline (always)]
# [must_use]
pub fn err (& mut self) -> ERR_W < ISTR_SPEC > { ERR_W :: new (self , 13) } # [doc = "Bit 14 - Packet memory area over / underrun"]
# [inline (always)]
# [must_use]
pub fn pmaovr (& mut self) -> PMAOVR_W < ISTR_SPEC > { PMAOVR_W :: new (self , 14) } # [doc = "Bit 15 - Correct transfer"]
# [inline (always)]
# [must_use]
pub fn ctr (& mut self) -> CTR_W < ISTR_SPEC > { CTR_W :: new (self , 15) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`istr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`istr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISTR_SPEC ; impl crate :: RegisterSpec for ISTR_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`istr::R`](R) reader structure"]
impl crate :: Readable for ISTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`istr::W`](W) writer structure"]
impl crate :: Writable for ISTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets ISTR to value 0"]
impl crate :: Resettable for ISTR_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "FNR (r) register accessor: frame number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fnr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fnr`]
module"]
pub type FNR = crate :: Reg < fnr :: FNR_SPEC > ; # [doc = "frame number register"]
pub mod fnr { # [doc = "Register `FNR` reader"]
pub type R = crate :: R < FNR_SPEC > ; # [doc = "Field `FN` reader - Frame number"]
pub type FN_R = crate :: FieldReader < u16 > ; # [doc = "Field `LSOF` reader - Lost SOF"]
pub type LSOF_R = crate :: FieldReader ; # [doc = "Field `LCK` reader - Locked"]
pub type LCK_R = crate :: BitReader ; # [doc = "Field `RXDM` reader - Receive data - line status"]
pub type RXDM_R = crate :: BitReader ; # [doc = "Field `RXDP` reader - Receive data + line status"]
pub type RXDP_R = crate :: BitReader ; impl R { # [doc = "Bits 0:10 - Frame number"]
# [inline (always)]
pub fn fn_ (& self) -> FN_R { FN_R :: new (self . bits & 0x07ff) } # [doc = "Bits 11:12 - Lost SOF"]
# [inline (always)]
pub fn lsof (& self) -> LSOF_R { LSOF_R :: new (((self . bits >> 11) & 3) as u8) } # [doc = "Bit 13 - Locked"]
# [inline (always)]
pub fn lck (& self) -> LCK_R { LCK_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Receive data - line status"]
# [inline (always)]
pub fn rxdm (& self) -> RXDM_R { RXDM_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Receive data + line status"]
# [inline (always)]
pub fn rxdp (& self) -> RXDP_R { RXDP_R :: new (((self . bits >> 15) & 1) != 0) } } # [doc = "frame number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fnr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FNR_SPEC ; impl crate :: RegisterSpec for FNR_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`fnr::R`](R) reader structure"]
impl crate :: Readable for FNR_SPEC { } # [doc = "`reset()` method sets FNR to value 0"]
impl crate :: Resettable for FNR_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "DADDR (rw) register accessor: device address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daddr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`daddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daddr`]
module"]
pub type DADDR = crate :: Reg < daddr :: DADDR_SPEC > ; # [doc = "device address"]
pub mod daddr { # [doc = "Register `DADDR` reader"]
pub type R = crate :: R < DADDR_SPEC > ; # [doc = "Register `DADDR` writer"]
pub type W = crate :: W < DADDR_SPEC > ; # [doc = "Field `ADD` reader - Device address"]
pub type ADD_R = crate :: FieldReader ; # [doc = "Field `ADD` writer - Device address"]
pub type ADD_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 7 > ; # [doc = "Field `EF` reader - Enable function"]
pub type EF_R = crate :: BitReader ; # [doc = "Field `EF` writer - Enable function"]
pub type EF_W < 'a , REG > = crate :: BitWriter < 'a , REG > ; impl R { # [doc = "Bits 0:6 - Device address"]
# [inline (always)]
pub fn add (& self) -> ADD_R { ADD_R :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - Enable function"]
# [inline (always)]
pub fn ef (& self) -> EF_R { EF_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:6 - Device address"]
# [inline (always)]
# [must_use]
pub fn add (& mut self) -> ADD_W < DADDR_SPEC > { ADD_W :: new (self , 0) } # [doc = "Bit 7 - Enable function"]
# [inline (always)]
# [must_use]
pub fn ef (& mut self) -> EF_W < DADDR_SPEC > { EF_W :: new (self , 7) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "device address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daddr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`daddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DADDR_SPEC ; impl crate :: RegisterSpec for DADDR_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`daddr::R`](R) reader structure"]
impl crate :: Readable for DADDR_SPEC { } # [doc = "`write(|w| ..)` method takes [`daddr::W`](W) writer structure"]
impl crate :: Writable for DADDR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets DADDR to value 0"]
impl crate :: Resettable for DADDR_SPEC { const RESET_VALUE : u16 = 0 ; } } # [doc = "BTABLE (rw) register accessor: Buffer table address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`btable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`btable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@btable`]
module"]
pub type BTABLE = crate :: Reg < btable :: BTABLE_SPEC > ; # [doc = "Buffer table address"]
pub mod btable { # [doc = "Register `BTABLE` reader"]
pub type R = crate :: R < BTABLE_SPEC > ; # [doc = "Register `BTABLE` writer"]
pub type W = crate :: W < BTABLE_SPEC > ; # [doc = "Field `BTABLE` reader - Buffer table"]
pub type BTABLE_R = crate :: FieldReader < u16 > ; # [doc = "Field `BTABLE` writer - Buffer table"]
pub type BTABLE_W < 'a , REG > = crate :: FieldWriter < 'a , REG , 13 , u16 > ; impl R { # [doc = "Bits 3:15 - Buffer table"]
# [inline (always)]
pub fn btable (& self) -> BTABLE_R { BTABLE_R :: new ((self . bits >> 3) & 0x1fff) } } impl W { # [doc = "Bits 3:15 - Buffer table"]
# [inline (always)]
# [must_use]
pub fn btable (& mut self) -> BTABLE_W < BTABLE_SPEC > { BTABLE_W :: new (self , 3) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u16) -> & mut Self { self . bits = bits ; self } } # [doc = "Buffer table address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`btable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`btable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BTABLE_SPEC ; impl crate :: RegisterSpec for BTABLE_SPEC { type Ux = u16 ; } # [doc = "`read()` method returns [`btable::R`](R) reader structure"]
impl crate :: Readable for BTABLE_SPEC { } # [doc = "`write(|w| ..)` method takes [`btable::W`](W) writer structure"]
impl crate :: Writable for BTABLE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : u16 = 0 ; } # [doc = "`reset()` method sets BTABLE to value 0"]
impl crate :: Resettable for BTABLE_SPEC { const RESET_VALUE : u16 = 0 ; } } } # [no_mangle]
static mut DEVICE_PERIPHERALS : bool = false ; # [doc = r" All the peripherals."]
# [allow (non_snake_case)]
pub struct Peripherals { # [doc = "PWR"]
pub PWR : PWR , # [doc = "RCC"]
pub RCC : RCC , # [doc = "EXTEND"]
pub EXTEND : EXTEND , # [doc = "GPIOA"]
pub GPIOA : GPIOA , # [doc = "GPIOB"]
pub GPIOB : GPIOB , # [doc = "GPIOC"]
pub GPIOC : GPIOC , # [doc = "GPIOD"]
pub GPIOD : GPIOD , # [doc = "AFIO"]
pub AFIO : AFIO , # [doc = "EXTI"]
pub EXTI : EXTI , # [doc = "DMA"]
pub DMA : DMA , # [doc = "RTC"]
pub RTC : RTC , # [doc = "BKP"]
pub BKP : BKP , # [doc = "IWDG"]
pub IWDG : IWDG , # [doc = "WWDG"]
pub WWDG : WWDG , # [doc = "TIM1"]
pub TIM1 : TIM1 , # [doc = "TIM2"]
pub TIM2 : TIM2 , # [doc = "TIM3"]
pub TIM3 : TIM3 , # [doc = "TIM4"]
pub TIM4 : TIM4 , # [doc = "I2C1"]
pub I2C1 : I2C1 , # [doc = "I2C2"]
pub I2C2 : I2C2 , # [doc = "SPI1"]
pub SPI1 : SPI1 , # [doc = "SPI2"]
pub SPI2 : SPI2 , # [doc = "USART1"]
pub USART1 : USART1 , # [doc = "USART2"]
pub USART2 : USART2 , # [doc = "USART3"]
pub USART3 : USART3 , # [doc = "ADC"]
pub ADC : ADC , # [doc = "DAC1"]
pub DAC1 : DAC1 , # [doc = "DBG"]
pub DBG : DBG , # [doc = "USBHD"]
pub USBHD : USBHD , # [doc = "CRC"]
pub CRC : CRC , # [doc = "FLASH"]
pub FLASH : FLASH , # [doc = "PFIC"]
pub PFIC : PFIC , # [doc = "USBD"]
pub USBD : USBD , } impl Peripherals { # [doc = r" Returns all the peripherals *once*."]
# [cfg (feature = "critical-section")]
# [inline]
pub fn take () -> Option < Self > { critical_section :: with (| _ | { if unsafe { DEVICE_PERIPHERALS } { return None } Some (unsafe { Peripherals :: steal () }) }) } # [doc = r" Unchecked version of `Peripherals::take`."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Each of the returned peripherals must be used at most once."]
# [inline]
pub unsafe fn steal () -> Self { DEVICE_PERIPHERALS = true ; Peripherals { PWR : PWR { _marker : PhantomData } , RCC : RCC { _marker : PhantomData } , EXTEND : EXTEND { _marker : PhantomData } , GPIOA : GPIOA { _marker : PhantomData } , GPIOB : GPIOB { _marker : PhantomData } , GPIOC : GPIOC { _marker : PhantomData } , GPIOD : GPIOD { _marker : PhantomData } , AFIO : AFIO { _marker : PhantomData } , EXTI : EXTI { _marker : PhantomData } , DMA : DMA { _marker : PhantomData } , RTC : RTC { _marker : PhantomData } , BKP : BKP { _marker : PhantomData } , IWDG : IWDG { _marker : PhantomData } , WWDG : WWDG { _marker : PhantomData } , TIM1 : TIM1 { _marker : PhantomData } , TIM2 : TIM2 { _marker : PhantomData } , TIM3 : TIM3 { _marker : PhantomData } , TIM4 : TIM4 { _marker : PhantomData } , I2C1 : I2C1 { _marker : PhantomData } , I2C2 : I2C2 { _marker : PhantomData } , SPI1 : SPI1 { _marker : PhantomData } , SPI2 : SPI2 { _marker : PhantomData } , USART1 : USART1 { _marker : PhantomData } , USART2 : USART2 { _marker : PhantomData } , USART3 : USART3 { _marker : PhantomData } , ADC : ADC { _marker : PhantomData } , DAC1 : DAC1 { _marker : PhantomData } , DBG : DBG { _marker : PhantomData } , USBHD : USBHD { _marker : PhantomData } , CRC : CRC { _marker : PhantomData } , FLASH : FLASH { _marker : PhantomData } , PFIC : PFIC { _marker : PhantomData } , USBD : USBD { _marker : PhantomData } , } } }