NXP Semiconductors S32K144W 1.2 S32K144W_M4 NXP Microcontroller Copyright 2016-2020 NXP NXP Confidential. This software is owned or controlled by NXP and may only be used strictly in accordance with the applicable license terms. By expressly accepting such terms or by downloading, installing, activating and/or otherwise using the software, you are agreeing that you have read, and that you agree to comply with and are bound by, such license terms. If you do not agree to be bound by the applicable license terms, then you may not retain, install, activate or otherwise use the software. The production use license in Section 2.3 is expressly granted for this software. CM4 r0p1 little true true true 4 false 8 32 AIPS AIPS AIPS 0x40000000 0 0x70 registers MPRA Master Privilege Register A 0 32 read-write 0x4A19BA0 0xFFFFFFFF MPL2 Master 2 Privilege Level 20 1 read-write MPL2_0 Accesses from this master are forced to user-mode. 0 MPL2_1 Accesses from this master are not forced to user-mode. 0x1 MTW2 Master 2 Trusted For Writes 21 1 read-write MTW2_0 This master is not trusted for write accesses. 0 MTW2_1 This master is trusted for write accesses. 0x1 MTR2 Master 2 Trusted For Read 22 1 read-write MTR2_0 This master is not trusted for read accesses. 0 MTR2_1 This master is trusted for read accesses. 0x1 MPL1 Master 1 Privilege Level 24 1 read-write MPL1_0 Accesses from this master are forced to user-mode. 0 MPL1_1 Accesses from this master are not forced to user-mode. 0x1 MTW1 Master 1 Trusted for Writes 25 1 read-write MTW1_0 This master is not trusted for write accesses. 0 MTW1_1 This master is trusted for write accesses. 0x1 MTR1 Master 1 Trusted for Read 26 1 read-write MTR1_0 This master is not trusted for read accesses. 0 MTR1_1 This master is trusted for read accesses. 0x1 MPL0 Master 0 Privilege Level 28 1 read-write MPL0_0 Accesses from this master are forced to user-mode. 0 MPL0_1 Accesses from this master are not forced to user-mode. 0x1 MTW0 Master 0 Trusted For Writes 29 1 read-write MTW0_0 This master is not trusted for write accesses. 0 MTW0_1 This master is trusted for write accesses. 0x1 MTR0 Master 0 Trusted For Read 30 1 read-write MTR0_0 This master is not trusted for read accesses. 0 MTR0_1 This master is trusted for read accesses. 0x1 PACRA Peripheral Access Control Register 0x20 32 read-write 0x54000000 0xFFFFFFFF TP1 Trusted Protect 24 1 read-write TP1_0 Accesses from an untrusted master are allowed. 0 TP1_1 Accesses from an untrusted master are not allowed. 0x1 WP1 Write Protect 25 1 read-write WP1_0 This peripheral allows write accesses. 0 WP1_1 This peripheral is write protected. 0x1 SP1 Supervisor Protect 26 1 read-write SP1_0 This peripheral does not require supervisor privilege level for accesses. 0 SP1_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP0 Trusted Protect 28 1 read-write TP0_0 Accesses from an untrusted master are allowed. 0 TP0_1 Accesses from an untrusted master are not allowed. 0x1 WP0 Write Protect 29 1 read-write WP0_0 This peripheral allows write accesses. 0 WP0_1 This peripheral is write protected. 0x1 SP0 Supervisor Protect 30 1 read-write SP0_0 This peripheral does not require supervisor privilege level for accesses. 0 SP0_1 This peripheral requires supervisor privilege level for accesses. 0x1 PACRB Peripheral Access Control Register 0x24 32 read-write 0x44000400 0xFFFFFFFF TP5 Trusted Protect 8 1 read-write TP5_0 Accesses from an untrusted master are allowed. 0 TP5_1 Accesses from an untrusted master are not allowed. 0x1 WP5 Write Protect 9 1 read-write WP5_0 This peripheral allows write accesses. 0 WP5_1 This peripheral is write protected. 0x1 SP5 Supervisor Protect 10 1 read-write SP5_0 This peripheral does not require supervisor privilege level for accesses. 0 SP5_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP1 Trusted Protect 24 1 read-write TP1_0 Accesses from an untrusted master are allowed. 0 TP1_1 Accesses from an untrusted master are not allowed. 0x1 WP1 Write Protect 25 1 read-write WP1_0 This peripheral allows write accesses. 0 WP1_1 This peripheral is write protected. 0x1 SP1 Supervisor Protect 26 1 read-write SP1_0 This peripheral does not require supervisor privilege level for accesses. 0 SP1_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP0 Trusted Protect 28 1 read-write TP0_0 Accesses from an untrusted master are allowed. 0 TP0_1 Accesses from an untrusted master are not allowed. 0x1 WP0 Write Protect 29 1 read-write WP0_0 This peripheral allows write accesses. 0 WP0_1 This peripheral is write protected. 0x1 SP0 Supervisor Protect 30 1 read-write SP0_0 This peripheral does not require supervisor privilege level for accesses. 0 SP0_1 This peripheral requires supervisor privilege level for accesses. 0x1 PACRD Peripheral Access Control Register 0x2C 32 read-write 0x44000000 0xFFFFFFFF TP1 Trusted Protect 24 1 read-write TP1_0 Accesses from an untrusted master are allowed. 0 TP1_1 Accesses from an untrusted master are not allowed. 0x1 WP1 Write Protect 25 1 read-write WP1_0 This peripheral allows write accesses. 0 WP1_1 This peripheral is write protected. 0x1 SP1 Supervisor Protect 26 1 read-write SP1_0 This peripheral does not require supervisor privilege level for accesses. 0 SP1_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP0 Trusted Protect 28 1 read-write TP0_0 Accesses from an untrusted master are allowed. 0 TP0_1 Accesses from an untrusted master are not allowed. 0x1 WP0 Write Protect 29 1 read-write WP0_0 This peripheral allows write accesses. 0 WP0_1 This peripheral is write protected. 0x1 SP0 Supervisor Protect 30 1 read-write SP0_0 This peripheral does not require supervisor privilege level for accesses. 0 SP0_1 This peripheral requires supervisor privilege level for accesses. 0x1 OPACRA Off-Platform Peripheral Access Control Register 0x40 32 read-write 0x44004444 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write TP7_0 Accesses from an untrusted master are allowed. 0 TP7_1 Accesses from an untrusted master are not allowed. 0x1 WP7 Write Protect 1 1 read-write WP7_0 This peripheral allows write accesses. 0 WP7_1 This peripheral is write protected. 0x1 SP7 Supervisor Protect 2 1 read-write SP7_0 This peripheral does not require supervisor privilege level for accesses. 0 SP7_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP6 Trusted Protect 4 1 read-write TP6_0 Accesses from an untrusted master are allowed. 0 TP6_1 Accesses from an untrusted master are not allowed. 0x1 WP6 Write Protect 5 1 read-write WP6_0 This peripheral allows write accesses. 0 WP6_1 This peripheral is write protected. 0x1 SP6 Supervisor Protect 6 1 read-write SP6_0 This peripheral does not require supervisor privilege level for accesses. 0 SP6_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP5 Trusted Protect 8 1 read-write TP5_0 Accesses from an untrusted master are allowed. 0 TP5_1 Accesses from an untrusted master are not allowed. 0x1 WP5 Write Protect 9 1 read-write WP5_0 This peripheral allows write accesses. 0 WP5_1 This peripheral is write protected. 0x1 SP5 Supervisor Protect 10 1 read-write SP5_0 This peripheral does not require supervisor privilege level for accesses. 0 SP5_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP4 Trusted Protect 12 1 read-write TP4_0 Accesses from an untrusted master are allowed. 0 TP4_1 Accesses from an untrusted master are not allowed. 0x1 WP4 Write Protect 13 1 read-write WP4_0 This peripheral allows write accesses. 0 WP4_1 This peripheral is write protected. 0x1 SP4 Supervisor Protect 14 1 read-write SP4_0 This peripheral does not require supervisor privilege level for accesses. 0 SP4_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP1 Trusted Protect 24 1 read-write TP1_0 Accesses from an untrusted master are allowed. 0 TP1_1 Accesses from an untrusted master are not allowed. 0x1 WP1 Write Protect 25 1 read-write WP1_0 This peripheral allows write accesses. 0 WP1_1 This peripheral is write protected. 0x1 SP1 Supervisor Protect 26 1 read-write SP1_0 This peripheral does not require supervisor privilege level for accesses. 0 SP1_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP0 Trusted Protect 28 1 read-write TP0_0 Accesses from an untrusted master are allowed. 0 TP0_1 Accesses from an untrusted master are not allowed. 0x1 WP0 Write Protect 29 1 read-write WP0_0 This peripheral allows write accesses. 0 WP0_1 This peripheral is write protected. 0x1 SP0 Supervisor Protect 30 1 read-write SP0_0 This peripheral does not require supervisor privilege level for accesses. 0 SP0_1 This peripheral requires supervisor privilege level for accesses. 0x1 OPACRB Off-Platform Peripheral Access Control Register 0x44 32 read-write 0x4440 0xFFFFFFFF TP6 Trusted Protect 4 1 read-write TP6_0 Accesses from an untrusted master are allowed. 0 TP6_1 Accesses from an untrusted master are not allowed. 0x1 WP6 Write Protect 5 1 read-write WP6_0 This peripheral allows write accesses. 0 WP6_1 This peripheral is write protected. 0x1 SP6 Supervisor Protect 6 1 read-write SP6_0 This peripheral does not require supervisor privilege level for accesses. 0 SP6_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP5 Trusted Protect 8 1 read-write TP5_0 Accesses from an untrusted master are allowed. 0 TP5_1 Accesses from an untrusted master are not allowed. 0x1 WP5 Write Protect 9 1 read-write WP5_0 This peripheral allows write accesses. 0 WP5_1 This peripheral is write protected. 0x1 SP5 Supervisor Protect 10 1 read-write SP5_0 This peripheral does not require supervisor privilege level for accesses. 0 SP5_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP4 Trusted Protect 12 1 read-write TP4_0 Accesses from an untrusted master are allowed. 0 TP4_1 Accesses from an untrusted master are not allowed. 0x1 WP4 Write Protect 13 1 read-write WP4_0 This peripheral allows write accesses. 0 WP4_1 This peripheral is write protected. 0x1 SP4 Supervisor Protect 14 1 read-write SP4_0 This peripheral does not require supervisor privilege level for accesses. 0 SP4_1 This peripheral requires supervisor privilege level for accesses. 0x1 OPACRC Off-Platform Peripheral Access Control Register 0x48 32 read-write 0x4400044 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write TP7_0 Accesses from an untrusted master are allowed. 0 TP7_1 Accesses from an untrusted master are not allowed. 0x1 WP7 Write Protect 1 1 read-write WP7_0 This peripheral allows write accesses. 0 WP7_1 This peripheral is write protected. 0x1 SP7 Supervisor Protect 2 1 read-write SP7_0 This peripheral does not require supervisor privilege level for accesses. 0 SP7_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP6 Trusted Protect 4 1 read-write TP6_0 Accesses from an untrusted master are allowed. 0 TP6_1 Accesses from an untrusted master are not allowed. 0x1 WP6 Write Protect 5 1 read-write WP6_0 This peripheral allows write accesses. 0 WP6_1 This peripheral is write protected. 0x1 SP6 Supervisor Protect 6 1 read-write SP6_0 This peripheral does not require supervisor privilege level for accesses. 0 SP6_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP2 Trusted Protect 20 1 read-write TP2_0 Accesses from an untrusted master are allowed. 0 TP2_1 Accesses from an untrusted master are not allowed. 0x1 WP2 Write Protect 21 1 read-write WP2_0 This peripheral allows write accesses. 0 WP2_1 This peripheral is write protected. 0x1 SP2 Supervisor Protect 22 1 read-write SP2_0 This peripheral does not require supervisor privilege level for accesses. 0 SP2_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP1 Trusted Protect 24 1 read-write TP1_0 Accesses from an untrusted master are allowed. 0 TP1_1 Accesses from an untrusted master are not allowed. 0x1 WP1 Write Protect 25 1 read-write WP1_0 This peripheral allows write accesses. 0 WP1_1 This peripheral is write protected. 0x1 SP1 Supervisor Protect 26 1 read-write SP1_0 This peripheral does not require supervisor privilege level for accesses. 0 SP1_1 This peripheral requires supervisor privilege level for accesses. 0x1 OPACRD Off-Platform Peripheral Access Control Register 0x4C 32 read-write 0x44440400 0xFFFFFFFF TP5 Trusted Protect 8 1 read-write TP5_0 Accesses from an untrusted master are allowed. 0 TP5_1 Accesses from an untrusted master are not allowed. 0x1 WP5 Write Protect 9 1 read-write WP5_0 This peripheral allows write accesses. 0 WP5_1 This peripheral is write protected. 0x1 SP5 Supervisor Protect 10 1 read-write SP5_0 This peripheral does not require supervisor privilege level for accesses. 0 SP5_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP3 Trusted Protect 16 1 read-write TP3_0 Accesses from an untrusted master are allowed. 0 TP3_1 Accesses from an untrusted master are not allowed. 0x1 WP3 Write Protect 17 1 read-write WP3_0 This peripheral allows write accesses. 0 WP3_1 This peripheral is write protected. 0x1 SP3 Supervisor Protect 18 1 read-write SP3_0 This peripheral does not require supervisor privilege level for accesses. 0 SP3_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP2 Trusted Protect 20 1 read-write TP2_0 Accesses from an untrusted master are allowed. 0 TP2_1 Accesses from an untrusted master are not allowed. 0x1 WP2 Write Protect 21 1 read-write WP2_0 This peripheral allows write accesses. 0 WP2_1 This peripheral is write protected. 0x1 SP2 Supervisor Protect 22 1 read-write SP2_0 This peripheral does not require supervisor privilege level for accesses. 0 SP2_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP1 Trusted Protect 24 1 read-write TP1_0 Accesses from an untrusted master are allowed. 0 TP1_1 Accesses from an untrusted master are not allowed. 0x1 WP1 Write Protect 25 1 read-write WP1_0 This peripheral allows write accesses. 0 WP1_1 This peripheral is write protected. 0x1 SP1 Supervisor Protect 26 1 read-write SP1_0 This peripheral does not require supervisor privilege level for accesses. 0 SP1_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP0 Trusted Protect 28 1 read-write TP0_0 Accesses from an untrusted master are allowed. 0 TP0_1 Accesses from an untrusted master are not allowed. 0x1 WP0 Write Protect 29 1 read-write WP0_0 This peripheral allows write accesses. 0 WP0_1 This peripheral is write protected. 0x1 SP0 Supervisor Protect 30 1 read-write SP0_0 This peripheral does not require supervisor privilege level for accesses. 0 SP0_1 This peripheral requires supervisor privilege level for accesses. 0x1 OPACRE Off-Platform Peripheral Access Control Register 0x50 32 read-write 0x40000040 0xFFFFFFFF TP6 Trusted Protect 4 1 read-write TP6_0 Accesses from an untrusted master are allowed. 0 TP6_1 Accesses from an untrusted master are not allowed. 0x1 WP6 Write Protect 5 1 read-write WP6_0 This peripheral allows write accesses. 0 WP6_1 This peripheral is write protected. 0x1 SP6 Supervisor Protect 6 1 read-write SP6_0 This peripheral does not require supervisor privilege level for accesses. 0 SP6_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP0 Trusted Protect 28 1 read-write TP0_0 Accesses from an untrusted master are allowed. 0 TP0_1 Accesses from an untrusted master are not allowed. 0x1 WP0 Write Protect 29 1 read-write WP0_0 This peripheral allows write accesses. 0 WP0_1 This peripheral is write protected. 0x1 SP0 Supervisor Protect 30 1 read-write SP0_0 This peripheral does not require supervisor privilege level for accesses. 0 SP0_1 This peripheral requires supervisor privilege level for accesses. 0x1 OPACRF Off-Platform Peripheral Access Control Register 0x54 32 read-write 0x44444400 0xFFFFFFFF TP5 Trusted Protect 8 1 read-write TP5_0 Accesses from an untrusted master are allowed. 0 TP5_1 Accesses from an untrusted master are not allowed. 0x1 WP5 Write Protect 9 1 read-write WP5_0 This peripheral allows write accesses. 0 WP5_1 This peripheral is write protected. 0x1 SP5 Supervisor Protect 10 1 read-write SP5_0 This peripheral does not require supervisor privilege level for accesses. 0 SP5_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP4 Trusted Protect 12 1 read-write TP4_0 Accesses from an untrusted master are allowed. 0 TP4_1 Accesses from an untrusted master are not allowed. 0x1 WP4 Write Protect 13 1 read-write WP4_0 This peripheral allows write accesses. 0 WP4_1 This peripheral is write protected. 0x1 SP4 Supervisor Protect 14 1 read-write SP4_0 This peripheral does not require supervisor privilege level for accesses. 0 SP4_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP3 Trusted Protect 16 1 read-write TP3_0 Accesses from an untrusted master are allowed. 0 TP3_1 Accesses from an untrusted master are not allowed. 0x1 WP3 Write Protect 17 1 read-write WP3_0 This peripheral allows write accesses. 0 WP3_1 This peripheral is write protected. 0x1 SP3 Supervisor Protect 18 1 read-write SP3_0 This peripheral does not require supervisor privilege level for accesses. 0 SP3_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP2 Trusted Protect 20 1 read-write TP2_0 Accesses from an untrusted master are allowed. 0 TP2_1 Accesses from an untrusted master are not allowed. 0x1 WP2 Write Protect 21 1 read-write WP2_0 This peripheral allows write accesses. 0 WP2_1 This peripheral is write protected. 0x1 SP2 Supervisor Protect 22 1 read-write SP2_0 This peripheral does not require supervisor privilege level for accesses. 0 SP2_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP1 Trusted Protect 24 1 read-write TP1_0 Accesses from an untrusted master are allowed. 0 TP1_1 Accesses from an untrusted master are not allowed. 0x1 WP1 Write Protect 25 1 read-write WP1_0 This peripheral allows write accesses. 0 WP1_1 This peripheral is write protected. 0x1 SP1 Supervisor Protect 26 1 read-write SP1_0 This peripheral does not require supervisor privilege level for accesses. 0 SP1_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP0 Trusted Protect 28 1 read-write TP0_0 Accesses from an untrusted master are allowed. 0 TP0_1 Accesses from an untrusted master are not allowed. 0x1 WP0 Write Protect 29 1 read-write WP0_0 This peripheral allows write accesses. 0 WP0_1 This peripheral is write protected. 0x1 SP0 Supervisor Protect 30 1 read-write SP0_0 This peripheral does not require supervisor privilege level for accesses. 0 SP0_1 This peripheral requires supervisor privilege level for accesses. 0x1 OPACRG Off-Platform Peripheral Access Control Register 0x58 32 read-write 0x400000 0xFFFFFFFF TP2 Trusted Protect 20 1 read-write TP2_0 Accesses from an untrusted master are allowed. 0 TP2_1 Accesses from an untrusted master are not allowed. 0x1 WP2 Write Protect 21 1 read-write WP2_0 This peripheral allows write accesses. 0 WP2_1 This peripheral is write protected. 0x1 SP2 Supervisor Protect 22 1 read-write SP2_0 This peripheral does not require supervisor privilege level for accesses. 0 SP2_1 This peripheral requires supervisor privilege level for accesses. 0x1 OPACRH Off-Platform Peripheral Access Control Register 0x5C 32 read-write 0x400000 0xFFFFFFFF TP2 Trusted Protect 20 1 read-write TP2_0 Accesses from an untrusted master are allowed. 0 TP2_1 Accesses from an untrusted master are not allowed. 0x1 WP2 Write Protect 21 1 read-write WP2_0 This peripheral allows write accesses. 0 WP2_1 This peripheral is write protected. 0x1 SP2 Supervisor Protect 22 1 read-write SP2_0 This peripheral does not require supervisor privilege level for accesses. 0 SP2_1 This peripheral requires supervisor privilege level for accesses. 0x1 OPACRI Off-Platform Peripheral Access Control Register 0x60 32 read-write 0x4044440 0xFFFFFFFF TP6 Trusted Protect 4 1 read-write TP6_0 Accesses from an untrusted master are allowed. 0 TP6_1 Accesses from an untrusted master are not allowed. 0x1 WP6 Write Protect 5 1 read-write WP6_0 This peripheral allows write accesses. 0 WP6_1 This peripheral is write protected. 0x1 SP6 Supervisor Protect 6 1 read-write SP6_0 This peripheral does not require supervisor privilege level for accesses. 0 SP6_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP5 Trusted Protect 8 1 read-write TP5_0 Accesses from an untrusted master are allowed. 0 TP5_1 Accesses from an untrusted master are not allowed. 0x1 WP5 Write Protect 9 1 read-write WP5_0 This peripheral allows write accesses. 0 WP5_1 This peripheral is write protected. 0x1 SP5 Supervisor Protect 10 1 read-write SP5_0 This peripheral does not require supervisor privilege level for accesses. 0 SP5_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP4 Trusted Protect 12 1 read-write TP4_0 Accesses from an untrusted master are allowed. 0 TP4_1 Accesses from an untrusted master are not allowed. 0x1 WP4 Write Protect 13 1 read-write WP4_0 This peripheral allows write accesses. 0 WP4_1 This peripheral is write protected. 0x1 SP4 Supervisor Protect 14 1 read-write SP4_0 This peripheral does not require supervisor privilege level for accesses. 0 SP4_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP3 Trusted Protect 16 1 read-write TP3_0 Accesses from an untrusted master are allowed. 0 TP3_1 Accesses from an untrusted master are not allowed. 0x1 WP3 Write Protect 17 1 read-write WP3_0 This peripheral allows write accesses. 0 WP3_1 This peripheral is write protected. 0x1 SP3 Supervisor Protect 18 1 read-write SP3_0 This peripheral does not require supervisor privilege level for accesses. 0 SP3_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP1 Trusted Protect 24 1 read-write TP1_0 Accesses from an untrusted master are allowed. 0 TP1_1 Accesses from an untrusted master are not allowed. 0x1 WP1 Write Protect 25 1 read-write WP1_0 This peripheral allows write accesses. 0 WP1_1 This peripheral is write protected. 0x1 SP1 Supervisor Protect 26 1 read-write SP1_0 This peripheral does not require supervisor privilege level for accesses. 0 SP1_1 This peripheral requires supervisor privilege level for accesses. 0x1 OPACRJ Off-Platform Peripheral Access Control Register 0x64 32 read-write 0x444000 0xFFFFFFFF TP4 Trusted Protect 12 1 read-write TP4_0 Accesses from an untrusted master are allowed. 0 TP4_1 Accesses from an untrusted master are not allowed. 0x1 WP4 Write Protect 13 1 read-write WP4_0 This peripheral allows write accesses. 0 WP4_1 This peripheral is write protected. 0x1 SP4 Supervisor Protect 14 1 read-write SP4_0 This peripheral does not require supervisor privilege level for accesses. 0 SP4_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP3 Trusted Protect 16 1 read-write TP3_0 Accesses from an untrusted master are allowed. 0 TP3_1 Accesses from an untrusted master are not allowed. 0x1 WP3 Write Protect 17 1 read-write WP3_0 This peripheral allows write accesses. 0 WP3_1 This peripheral is write protected. 0x1 SP3 Supervisor Protect 18 1 read-write SP3_0 This peripheral does not require supervisor privilege level for accesses. 0 SP3_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP2 Trusted Protect 20 1 read-write TP2_0 Accesses from an untrusted master are allowed. 0 TP2_1 Accesses from an untrusted master are not allowed. 0x1 WP2 Write Protect 21 1 read-write WP2_0 This peripheral allows write accesses. 0 WP2_1 This peripheral is write protected. 0x1 SP2 Supervisor Protect 22 1 read-write SP2_0 This peripheral does not require supervisor privilege level for accesses. 0 SP2_1 This peripheral requires supervisor privilege level for accesses. 0x1 OPACRK Off-Platform Peripheral Access Control Register 0x68 32 read-write 0x40000 0xFFFFFFFF TP3 Trusted Protect 16 1 read-write TP3_0 Accesses from an untrusted master are allowed. 0 TP3_1 Accesses from an untrusted master are not allowed. 0x1 WP3 Write Protect 17 1 read-write WP3_0 This peripheral allows write accesses. 0 WP3_1 This peripheral is write protected. 0x1 SP3 Supervisor Protect 18 1 read-write SP3_0 This peripheral does not require supervisor privilege level for accesses. 0 SP3_1 This peripheral requires supervisor privilege level for accesses. 0x1 OPACRL Off-Platform Peripheral Access Control Register 0x6C 32 read-write 0x444 0xFFFFFFFF TP7 Trusted Protect 0 1 read-write TP7_0 Accesses from an untrusted master are allowed. 0 TP7_1 Accesses from an untrusted master are not allowed. 0x1 WP7 Write Protect 1 1 read-write WP7_0 This peripheral allows write accesses. 0 WP7_1 This peripheral is write protected. 0x1 SP7 Supervisor Protect 2 1 read-write SP7_0 This peripheral does not require supervisor privilege level for accesses. 0 SP7_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP6 Trusted Protect 4 1 read-write TP6_0 Accesses from an untrusted master are allowed. 0 TP6_1 Accesses from an untrusted master are not allowed. 0x1 WP6 Write Protect 5 1 read-write WP6_0 This peripheral allows write accesses. 0 WP6_1 This peripheral is write protected. 0x1 SP6 Supervisor Protect 6 1 read-write SP6_0 This peripheral does not require supervisor privilege level for accesses. 0 SP6_1 This peripheral requires supervisor privilege level for accesses. 0x1 TP5 Trusted Protect 8 1 read-write TP5_0 Accesses from an untrusted master are allowed. 0 TP5_1 Accesses from an untrusted master are not allowed. 0x1 WP5 Write Protect 9 1 read-write WP5_0 This peripheral allows write accesses. 0 WP5_1 This peripheral is write protected. 0x1 SP5 Supervisor Protect 10 1 read-write SP5_0 This peripheral does not require supervisor privilege level for accesses. 0 SP5_1 This peripheral requires supervisor privilege level for accesses. 0x1 MSCM MSCM MSCM 0x40001000 0 0x40C registers CPxTYPE Processor X Type Register 0 32 read-only 0 0 RYPZ Processor x Revision 0 8 read-only PERSONALITY Processor x Personality 8 24 read-only CPxNUM Processor X Number Register 0x4 32 read-only 0 0xFFFFFFFE CPN Processor x Number 0 1 read-only CPxMASTER Processor X Master Register 0x8 32 read-only 0 0xFFFFFFC0 PPMN Processor x Physical Master Number 0 6 read-only CPxCOUNT Processor X Count Register 0xC 32 read-only 0 0xFFFFFFFF PCNT Processor Count 0 2 read-only CPxCFG0 Processor X Configuration Register 0 0x10 32 read-only 0 0 DCWY Level 1 Data Cache Ways 0 8 read-only DCSZ Level 1 Data Cache Size 8 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only CPxCFG1 Processor X Configuration Register 1 0x14 32 read-only 0 0xFFFF L2WY Level 2 Instruction Cache Ways 16 8 read-only L2SZ Level 2 Instruction Cache Size 24 8 read-only CPxCFG2 Processor X Configuration Register 2 0x18 32 read-only 0x10001 0xFF00FF TMUSZ Tightly-coupled Memory Upper Size 8 8 read-only TMLSZ Tightly-coupled Memory Lower Size 24 8 read-only CPxCFG3 Processor X Configuration Register 3 0x1C 32 read-only 0 0xFFFFFC80 FPU Floating Point Unit 0 1 read-only FPU_0 FPU support is not included. 0 FPU_1 FPU support is included. 0x1 SIMD SIMD/NEON instruction support 1 1 read-only SIMD_0 SIMD/NEON support is not included. 0 SIMD_1 SIMD/NEON support is included. 0x1 JAZ Jazelle support 2 1 read-only JAZ_0 Jazelle support is not included. 0 JAZ_1 Jazelle support is included. 0x1 MMU Memory Management Unit 3 1 read-only MMU_0 MMU support is not included. 0 MMU_1 MMU support is included. 0x1 TZ Trust Zone 4 1 read-only TZ_0 Trust Zone support is not included. 0 TZ_1 Trust Zone support is included. 0x1 CMP Core Memory Protection unit 5 1 read-only CMP_0 Core Memory Protection is not included. 0 CMP_1 Core Memory Protection is included. 0x1 BB Bit Banding 6 1 read-only BB_0 Bit Banding is not supported. 0 BB_1 Bit Banding is supported. 0x1 SBP System Bus Ports 8 2 read-only CP0TYPE Processor 0 Type Register 0x20 32 read-only 0x434D3401 0xFFFFFFFF RYPZ Processor 0 Revision 0 8 read-only PERSONALITY Processor 0 Personality 8 24 read-only CP0NUM Processor 0 Number Register 0x24 32 read-only 0 0xFFFFFFFF CPN Processor 0 Number 0 1 read-only CP0MASTER Processor 0 Master Register 0x28 32 read-only 0 0xFFFFFFFF PPMN Processor 0 Physical Master Number 0 6 read-only CP0COUNT Processor 0 Count Register 0x2C 32 read-only 0 0xFFFFFFFF PCNT Processor Count 0 2 read-only CP0CFG0 Processor 0 Configuration Register 0 0x30 32 read-only 0x4000000 0xFFFFFFFF DCWY Level 1 Data Cache Ways 0 8 read-only DCSZ Level 1 Data Cache Size 8 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only CP0CFG1 Processor 0 Configuration Register 1 0x34 32 read-only 0 0xFFFFFFFF L2WY Level 2 Instruction Cache Ways 16 8 read-only L2SZ Level 2 Instruction Cache Size 24 8 read-only CP0CFG2 Processor 0 Configuration Register 2 0x38 32 read-only 0x7010701 0xFFFFFFFF TMUSZ Tightly-coupled Memory Upper Size 8 8 read-only TMLSZ Tightly-coupled Memory Lower Size 24 8 read-only CP0CFG3 Processor 0 Configuration Register 3 0x3C 32 read-only 0x101 0xFFFFFFFF FPU Floating Point Unit 0 1 read-only FPU_0 FPU support is not included. 0 FPU_1 FPU support is included. 0x1 SIMD SIMD/NEON instruction support 1 1 read-only SIMD_0 SIMD/NEON support is not included. 0 SIMD_1 SIMD/NEON support is included. 0x1 JAZ Jazelle support 2 1 read-only JAZ_0 Jazelle support is not included. 0 JAZ_1 Jazelle support is included. 0x1 MMU Memory Management Unit 3 1 read-only MMU_0 MMU support is not included. 0 MMU_1 MMU support is included. 0x1 TZ Trust Zone 4 1 read-only TZ_0 Trust Zone support is not included. 0 TZ_1 Trust Zone support is included. 0x1 CMP Core Memory Protection unit 5 1 read-only CMP_0 Core Memory Protection is not included. 0 CMP_1 Core Memory Protection is included. 0x1 BB Bit Banding 6 1 read-only BB_0 Bit Banding is not supported. 0 BB_1 Bit Banding is supported. 0x1 SBP System Bus Ports 8 2 read-only OCMDR0 On-Chip Memory Descriptor Register 0x400 32 read-write 0xCA089000 0xFFFFFFFF OCM1 OCMEM Control Field 1 4 2 read-write OCMPU OCMPU 12 1 read-only OCMT OCMT 13 3 read-only OCMT_4 OCMEMn is a Program Flash. 0x4 OCMT_5 OCMEMn is a Data Flash. 0x5 OCMT_6 OCMEMn is an EEE. 0x6 RO RO 16 1 read-write RO_0 Writes to the OCMDRn[11:0] are allowed 0 RO_1 Writes to the OCMDRn[11:0] are ignored 0x1 OCMW OCMW 17 3 read-only OCMW_2 OCMEMn 32-bits wide 0x2 OCMW_3 OCMEMn 64-bits wide 0x3 OCMW_4 OCMEMn 128-bits wide 0x4 OCMW_5 OCMEMn 256-bits wide 0x5 OCMSZ OCMSZ 24 4 read-only OCMSZ_0 no OCMEMn 0 OCMSZ_1 1KB OCMEMn 0x1 OCMSZ_2 2KB OCMEMn 0x2 OCMSZ_3 4KB OCMEMn 0x3 OCMSZ_4 8KB OCMEMn 0x4 OCMSZ_5 16KB OCMEMn 0x5 OCMSZ_6 32KB OCMEMn 0x6 OCMSZ_7 64KB OCMEMn 0x7 OCMSZ_8 128KB OCMEMn 0x8 OCMSZ_9 256KB OCMEMn 0x9 OCMSZ_10 512KB OCMEMn 0xA OCMSZ_11 1MB OCMEMn 0xB OCMSZ_12 2MB OCMEMn 0xC OCMSZ_13 4MB OCMEMn 0xD OCMSZ_14 8MB OCMEMn 0xE OCMSZ_15 16MB OCMEMn 0xF OCMSZH OCMSZH 28 1 read-only OCMSZH_0 OCMEMn is a power-of-2 capacity. 0 OCMSZH_1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. 0x1 V V 31 1 read-only V_0 OCMEMn is not present. 0 V_1 OCMEMn is present. 0x1 OCMDR1 On-Chip Memory Descriptor Register 0x404 32 read-write 0xC706B000 0xFFFFFFFF OCM1 OCMEM Control Field 1 4 2 read-write OCMPU OCMPU 12 1 read-only OCMT OCMT 13 3 read-only OCMT_4 OCMEMn is a Program Flash. 0x4 OCMT_5 OCMEMn is a Data Flash. 0x5 OCMT_6 OCMEMn is an EEE. 0x6 RO RO 16 1 read-write RO_0 Writes to the OCMDRn[11:0] are allowed 0 RO_1 Writes to the OCMDRn[11:0] are ignored 0x1 OCMW OCMW 17 3 read-only OCMW_2 OCMEMn 32-bits wide 0x2 OCMW_3 OCMEMn 64-bits wide 0x3 OCMW_4 OCMEMn 128-bits wide 0x4 OCMW_5 OCMEMn 256-bits wide 0x5 OCMSZ OCMSZ 24 4 read-only OCMSZ_0 no OCMEMn 0 OCMSZ_1 1KB OCMEMn 0x1 OCMSZ_2 2KB OCMEMn 0x2 OCMSZ_3 4KB OCMEMn 0x3 OCMSZ_4 8KB OCMEMn 0x4 OCMSZ_5 16KB OCMEMn 0x5 OCMSZ_6 32KB OCMEMn 0x6 OCMSZ_7 64KB OCMEMn 0x7 OCMSZ_8 128KB OCMEMn 0x8 OCMSZ_9 256KB OCMEMn 0x9 OCMSZ_10 512KB OCMEMn 0xA OCMSZ_11 1MB OCMEMn 0xB OCMSZ_12 2MB OCMEMn 0xC OCMSZ_13 4MB OCMEMn 0xD OCMSZ_14 8MB OCMEMn 0xE OCMSZ_15 16MB OCMEMn 0xF OCMSZH OCMSZH 28 1 read-only OCMSZH_0 OCMEMn is a power-of-2 capacity. 0 OCMSZH_1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. 0x1 V V 31 1 read-only V_0 OCMEMn is not present. 0 V_1 OCMEMn is present. 0x1 OCMDR2 On-Chip Memory Descriptor Register 0x408 32 read-write 0xC304D000 0xFFFFFFFF OCMPU OCMPU 12 1 read-only OCMT OCMT 13 3 read-only OCMT_4 OCMEMn is a Program Flash. 0x4 OCMT_5 OCMEMn is a Data Flash. 0x5 OCMT_6 OCMEMn is an EEE. 0x6 RO RO 16 1 read-write RO_0 Writes to the OCMDRn[11:0] are allowed 0 RO_1 Writes to the OCMDRn[11:0] are ignored 0x1 OCMW OCMW 17 3 read-only OCMW_2 OCMEMn 32-bits wide 0x2 OCMW_3 OCMEMn 64-bits wide 0x3 OCMW_4 OCMEMn 128-bits wide 0x4 OCMW_5 OCMEMn 256-bits wide 0x5 OCMSZ OCMSZ 24 4 read-only OCMSZ_0 no OCMEMn 0 OCMSZ_1 1KB OCMEMn 0x1 OCMSZ_2 2KB OCMEMn 0x2 OCMSZ_3 4KB OCMEMn 0x3 OCMSZ_4 8KB OCMEMn 0x4 OCMSZ_5 16KB OCMEMn 0x5 OCMSZ_6 32KB OCMEMn 0x6 OCMSZ_7 64KB OCMEMn 0x7 OCMSZ_8 128KB OCMEMn 0x8 OCMSZ_9 256KB OCMEMn 0x9 OCMSZ_10 512KB OCMEMn 0xA OCMSZ_11 1MB OCMEMn 0xB OCMSZ_12 2MB OCMEMn 0xC OCMSZ_13 4MB OCMEMn 0xD OCMSZ_14 8MB OCMEMn 0xE OCMSZ_15 16MB OCMEMn 0xF OCMSZH OCMSZH 28 1 read-only OCMSZH_0 OCMEMn is a power-of-2 capacity. 0 OCMSZH_1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. 0x1 V V 31 1 read-only V_0 OCMEMn is not present. 0 V_1 OCMEMn is present. 0x1 DMA DMA DMA 0x40008000 0 0x1200 registers CR Control Register 0 32 read-write 0 0x80FFFFFF EDBG Enable Debug 1 1 read-write EDBG_0 When in debug mode, the DMA continues to operate. 0 EDBG_1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. 0x1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write ERCA_0 Fixed priority arbitration is used for channel selection . 0 ERCA_1 Round robin arbitration is used for channel selection . 0x1 HOE Halt On Error 4 1 read-write HOE_0 Normal operation 0 HOE_1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. 0x1 HALT Halt DMA Operations 5 1 read-write HALT_0 Normal operation 0 HALT_1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. 0x1 CLM Continuous Link Mode 6 1 read-write CLM_0 A minor loop channel link made to itself goes through channel arbitration before being activated again. 0 CLM_1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. 0x1 EMLM Enable Minor Loop Mapping 7 1 read-write EMLM_0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 0 EMLM_1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. 0x1 ECX Error Cancel Transfer 16 1 read-write ECX_0 Normal operation 0 ECX_1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. 0x1 CX Cancel Transfer 17 1 read-write CX_0 Normal operation 0 CX_1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. 0x1 ACTIVE DMA Active Status 31 1 read-only ACTIVE_0 eDMA is idle. 0 ACTIVE_1 eDMA is executing a channel. 0x1 ES Error Status Register 0x4 32 read-only 0 0xFFFFFFFF DBE Destination Bus Error 0 1 read-only DBE_0 No destination bus error 0 DBE_1 The last recorded error was a bus error on a destination write 0x1 SBE Source Bus Error 1 1 read-only SBE_0 No source bus error 0 SBE_1 The last recorded error was a bus error on a source read 0x1 SGE Scatter/Gather Configuration Error 2 1 read-only SGE_0 No scatter/gather configuration error 0 SGE_1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. 0x1 NCE NBYTES/CITER Configuration Error 3 1 read-only NCE_0 No NBYTES/CITER configuration error 0 NCE_1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] 0x1 DOE Destination Offset Error 4 1 read-only DOE_0 No destination offset configuration error 0 DOE_1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. 0x1 DAE Destination Address Error 5 1 read-only DAE_0 No destination address configuration error 0 DAE_1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. 0x1 SOE Source Offset Error 6 1 read-only SOE_0 No source offset configuration error 0 SOE_1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. 0x1 SAE Source Address Error 7 1 read-only SAE_0 No source address configuration error. 0 SAE_1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. 0x1 ERRCHN Error Channel Number or Canceled Channel Number 8 4 read-only CPE Channel Priority Error 14 1 read-only CPE_0 No channel priority error 0 CPE_1 The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. 0x1 ECX Transfer Canceled 16 1 read-only ECX_0 No canceled transfers 0 ECX_1 The last recorded entry was a canceled transfer by the error cancel transfer input 0x1 VLD VLD 31 1 read-only VLD_0 No ERR bits are set. 0 VLD_1 At least one ERR bit is set indicating a valid error exists that has not been cleared. 0x1 ERQ Enable Request Register 0xC 32 read-write 0 0xFFFFFFFF ERQ0 Enable DMA Request 0 0 1 read-write ERQ0_0 The DMA request signal for the corresponding channel is disabled 0 ERQ0_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ1 Enable DMA Request 1 1 1 read-write ERQ1_0 The DMA request signal for the corresponding channel is disabled 0 ERQ1_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ2 Enable DMA Request 2 2 1 read-write ERQ2_0 The DMA request signal for the corresponding channel is disabled 0 ERQ2_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ3 Enable DMA Request 3 3 1 read-write ERQ3_0 The DMA request signal for the corresponding channel is disabled 0 ERQ3_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ4 Enable DMA Request 4 4 1 read-write ERQ4_0 The DMA request signal for the corresponding channel is disabled 0 ERQ4_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ5 Enable DMA Request 5 5 1 read-write ERQ5_0 The DMA request signal for the corresponding channel is disabled 0 ERQ5_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ6 Enable DMA Request 6 6 1 read-write ERQ6_0 The DMA request signal for the corresponding channel is disabled 0 ERQ6_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ7 Enable DMA Request 7 7 1 read-write ERQ7_0 The DMA request signal for the corresponding channel is disabled 0 ERQ7_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ8 Enable DMA Request 8 8 1 read-write ERQ8_0 The DMA request signal for the corresponding channel is disabled 0 ERQ8_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ9 Enable DMA Request 9 9 1 read-write ERQ9_0 The DMA request signal for the corresponding channel is disabled 0 ERQ9_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ10 Enable DMA Request 10 10 1 read-write ERQ10_0 The DMA request signal for the corresponding channel is disabled 0 ERQ10_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ11 Enable DMA Request 11 11 1 read-write ERQ11_0 The DMA request signal for the corresponding channel is disabled 0 ERQ11_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ12 Enable DMA Request 12 12 1 read-write ERQ12_0 The DMA request signal for the corresponding channel is disabled 0 ERQ12_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ13 Enable DMA Request 13 13 1 read-write ERQ13_0 The DMA request signal for the corresponding channel is disabled 0 ERQ13_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ14 Enable DMA Request 14 14 1 read-write ERQ14_0 The DMA request signal for the corresponding channel is disabled 0 ERQ14_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ15 Enable DMA Request 15 15 1 read-write ERQ15_0 The DMA request signal for the corresponding channel is disabled 0 ERQ15_1 The DMA request signal for the corresponding channel is enabled 0x1 EEI Enable Error Interrupt Register 0x14 32 read-write 0 0xFFFFFFFF EEI0 Enable Error Interrupt 0 0 1 read-write EEI0_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI0_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI1 Enable Error Interrupt 1 1 1 read-write EEI1_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI1_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI2 Enable Error Interrupt 2 2 1 read-write EEI2_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI2_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI3 Enable Error Interrupt 3 3 1 read-write EEI3_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI3_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI4 Enable Error Interrupt 4 4 1 read-write EEI4_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI4_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI5 Enable Error Interrupt 5 5 1 read-write EEI5_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI5_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI6 Enable Error Interrupt 6 6 1 read-write EEI6_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI6_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI7 Enable Error Interrupt 7 7 1 read-write EEI7_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI7_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI8 Enable Error Interrupt 8 8 1 read-write EEI8_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI8_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI9 Enable Error Interrupt 9 9 1 read-write EEI9_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI9_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI10 Enable Error Interrupt 10 10 1 read-write EEI10_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI10_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI11 Enable Error Interrupt 11 11 1 read-write EEI11_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI11_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI12 Enable Error Interrupt 12 12 1 read-write EEI12_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI12_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI13 Enable Error Interrupt 13 13 1 read-write EEI13_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI13_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI14 Enable Error Interrupt 14 14 1 read-write EEI14_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI14_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI15 Enable Error Interrupt 15 15 1 read-write EEI15_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI15_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 CEEI Clear Enable Error Interrupt Register 0x18 8 read-write 0 0xFF CEEI Clear Enable Error Interrupt 0 4 read-write CAEE Clear All Enable Error Interrupts 6 1 read-write CAEE_0 Clear only the EEI bit specified in the CEEI field 0 CAEE_1 Clear all bits in EEI 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 SEEI Set Enable Error Interrupt Register 0x19 8 read-write 0 0xFF SEEI Set Enable Error Interrupt 0 4 read-write SAEE Sets All Enable Error Interrupts 6 1 read-write SAEE_0 Set only the EEI bit specified in the SEEI field. 0 SAEE_1 Sets all bits in EEI 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 CERQ Clear Enable Request Register 0x1A 8 read-write 0 0xFF CERQ Clear Enable Request 0 4 read-write CAER Clear All Enable Requests 6 1 read-write CAER_0 Clear only the ERQ bit specified in the CERQ field 0 CAER_1 Clear all bits in ERQ 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 SERQ Set Enable Request Register 0x1B 8 read-write 0 0xFF SERQ Set Enable Request 0 4 read-write SAER Set All Enable Requests 6 1 read-write SAER_0 Set only the ERQ bit specified in the SERQ field 0 SAER_1 Set all bits in ERQ 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 CDNE Clear DONE Status Bit Register 0x1C 8 read-write 0 0xFF CDNE Clear DONE Bit 0 4 read-write CADN Clears All DONE Bits 6 1 read-write CADN_0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field 0 CADN_1 Clears all bits in TCDn_CSR[DONE] 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 SSRT Set START Bit Register 0x1D 8 read-write 0 0xFF SSRT Set START Bit 0 4 read-write SAST Set All START Bits (activates all channels) 6 1 read-write SAST_0 Set only the TCDn_CSR[START] bit specified in the SSRT field 0 SAST_1 Set all bits in TCDn_CSR[START] 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 CERR Clear Error Register 0x1E 8 read-write 0 0xFF CERR Clear Error Indicator 0 4 read-write CAEI Clear All Error Indicators 6 1 read-write CAEI_0 Clear only the ERR bit specified in the CERR field 0 CAEI_1 Clear all bits in ERR 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 CINT Clear Interrupt Request Register 0x1F 8 read-write 0 0xFF CINT Clear Interrupt Request 0 4 read-write CAIR Clear All Interrupt Requests 6 1 read-write CAIR_0 Clear only the INT bit specified in the CINT field 0 CAIR_1 Clear all bits in INT 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 INT Interrupt Request Register 0x24 32 read-write 0 0xFFFFFFFF INT0 Interrupt Request 0 0 1 read-write oneToClear INT0_0 The interrupt request for corresponding channel is cleared 0 INT0_1 The interrupt request for corresponding channel is active 0x1 INT1 Interrupt Request 1 1 1 read-write oneToClear INT1_0 The interrupt request for corresponding channel is cleared 0 INT1_1 The interrupt request for corresponding channel is active 0x1 INT2 Interrupt Request 2 2 1 read-write oneToClear INT2_0 The interrupt request for corresponding channel is cleared 0 INT2_1 The interrupt request for corresponding channel is active 0x1 INT3 Interrupt Request 3 3 1 read-write oneToClear INT3_0 The interrupt request for corresponding channel is cleared 0 INT3_1 The interrupt request for corresponding channel is active 0x1 INT4 Interrupt Request 4 4 1 read-write oneToClear INT4_0 The interrupt request for corresponding channel is cleared 0 INT4_1 The interrupt request for corresponding channel is active 0x1 INT5 Interrupt Request 5 5 1 read-write oneToClear INT5_0 The interrupt request for corresponding channel is cleared 0 INT5_1 The interrupt request for corresponding channel is active 0x1 INT6 Interrupt Request 6 6 1 read-write oneToClear INT6_0 The interrupt request for corresponding channel is cleared 0 INT6_1 The interrupt request for corresponding channel is active 0x1 INT7 Interrupt Request 7 7 1 read-write oneToClear INT7_0 The interrupt request for corresponding channel is cleared 0 INT7_1 The interrupt request for corresponding channel is active 0x1 INT8 Interrupt Request 8 8 1 read-write oneToClear INT8_0 The interrupt request for corresponding channel is cleared 0 INT8_1 The interrupt request for corresponding channel is active 0x1 INT9 Interrupt Request 9 9 1 read-write oneToClear INT9_0 The interrupt request for corresponding channel is cleared 0 INT9_1 The interrupt request for corresponding channel is active 0x1 INT10 Interrupt Request 10 10 1 read-write oneToClear INT10_0 The interrupt request for corresponding channel is cleared 0 INT10_1 The interrupt request for corresponding channel is active 0x1 INT11 Interrupt Request 11 11 1 read-write oneToClear INT11_0 The interrupt request for corresponding channel is cleared 0 INT11_1 The interrupt request for corresponding channel is active 0x1 INT12 Interrupt Request 12 12 1 read-write oneToClear INT12_0 The interrupt request for corresponding channel is cleared 0 INT12_1 The interrupt request for corresponding channel is active 0x1 INT13 Interrupt Request 13 13 1 read-write oneToClear INT13_0 The interrupt request for corresponding channel is cleared 0 INT13_1 The interrupt request for corresponding channel is active 0x1 INT14 Interrupt Request 14 14 1 read-write oneToClear INT14_0 The interrupt request for corresponding channel is cleared 0 INT14_1 The interrupt request for corresponding channel is active 0x1 INT15 Interrupt Request 15 15 1 read-write oneToClear INT15_0 The interrupt request for corresponding channel is cleared 0 INT15_1 The interrupt request for corresponding channel is active 0x1 ERR Error Register 0x2C 32 read-write 0 0xFFFFFFFF ERR0 Error In Channel 0 0 1 read-write oneToClear ERR0_0 An error in this channel has not occurred 0 ERR0_1 An error in this channel has occurred 0x1 ERR1 Error In Channel 1 1 1 read-write oneToClear ERR1_0 An error in this channel has not occurred 0 ERR1_1 An error in this channel has occurred 0x1 ERR2 Error In Channel 2 2 1 read-write oneToClear ERR2_0 An error in this channel has not occurred 0 ERR2_1 An error in this channel has occurred 0x1 ERR3 Error In Channel 3 3 1 read-write oneToClear ERR3_0 An error in this channel has not occurred 0 ERR3_1 An error in this channel has occurred 0x1 ERR4 Error In Channel 4 4 1 read-write oneToClear ERR4_0 An error in this channel has not occurred 0 ERR4_1 An error in this channel has occurred 0x1 ERR5 Error In Channel 5 5 1 read-write oneToClear ERR5_0 An error in this channel has not occurred 0 ERR5_1 An error in this channel has occurred 0x1 ERR6 Error In Channel 6 6 1 read-write oneToClear ERR6_0 An error in this channel has not occurred 0 ERR6_1 An error in this channel has occurred 0x1 ERR7 Error In Channel 7 7 1 read-write oneToClear ERR7_0 An error in this channel has not occurred 0 ERR7_1 An error in this channel has occurred 0x1 ERR8 Error In Channel 8 8 1 read-write oneToClear ERR8_0 An error in this channel has not occurred 0 ERR8_1 An error in this channel has occurred 0x1 ERR9 Error In Channel 9 9 1 read-write oneToClear ERR9_0 An error in this channel has not occurred 0 ERR9_1 An error in this channel has occurred 0x1 ERR10 Error In Channel 10 10 1 read-write oneToClear ERR10_0 An error in this channel has not occurred 0 ERR10_1 An error in this channel has occurred 0x1 ERR11 Error In Channel 11 11 1 read-write oneToClear ERR11_0 An error in this channel has not occurred 0 ERR11_1 An error in this channel has occurred 0x1 ERR12 Error In Channel 12 12 1 read-write oneToClear ERR12_0 An error in this channel has not occurred 0 ERR12_1 An error in this channel has occurred 0x1 ERR13 Error In Channel 13 13 1 read-write oneToClear ERR13_0 An error in this channel has not occurred 0 ERR13_1 An error in this channel has occurred 0x1 ERR14 Error In Channel 14 14 1 read-write oneToClear ERR14_0 An error in this channel has not occurred 0 ERR14_1 An error in this channel has occurred 0x1 ERR15 Error In Channel 15 15 1 read-write oneToClear ERR15_0 An error in this channel has not occurred 0 ERR15_1 An error in this channel has occurred 0x1 HRS Hardware Request Status Register 0x34 32 read-only 0 0xFFFFFFFF HRS0 Hardware Request Status Channel 0 0 1 read-only HRS0_0 A hardware service request for channel 0 is not present 0 HRS0_1 A hardware service request for channel 0 is present 0x1 HRS1 Hardware Request Status Channel 1 1 1 read-only HRS1_0 A hardware service request for channel 1 is not present 0 HRS1_1 A hardware service request for channel 1 is present 0x1 HRS2 Hardware Request Status Channel 2 2 1 read-only HRS2_0 A hardware service request for channel 2 is not present 0 HRS2_1 A hardware service request for channel 2 is present 0x1 HRS3 Hardware Request Status Channel 3 3 1 read-only HRS3_0 A hardware service request for channel 3 is not present 0 HRS3_1 A hardware service request for channel 3 is present 0x1 HRS4 Hardware Request Status Channel 4 4 1 read-only HRS4_0 A hardware service request for channel 4 is not present 0 HRS4_1 A hardware service request for channel 4 is present 0x1 HRS5 Hardware Request Status Channel 5 5 1 read-only HRS5_0 A hardware service request for channel 5 is not present 0 HRS5_1 A hardware service request for channel 5 is present 0x1 HRS6 Hardware Request Status Channel 6 6 1 read-only HRS6_0 A hardware service request for channel 6 is not present 0 HRS6_1 A hardware service request for channel 6 is present 0x1 HRS7 Hardware Request Status Channel 7 7 1 read-only HRS7_0 A hardware service request for channel 7 is not present 0 HRS7_1 A hardware service request for channel 7 is present 0x1 HRS8 Hardware Request Status Channel 8 8 1 read-only HRS8_0 A hardware service request for channel 8 is not present 0 HRS8_1 A hardware service request for channel 8 is present 0x1 HRS9 Hardware Request Status Channel 9 9 1 read-only HRS9_0 A hardware service request for channel 9 is not present 0 HRS9_1 A hardware service request for channel 9 is present 0x1 HRS10 Hardware Request Status Channel 10 10 1 read-only HRS10_0 A hardware service request for channel 10 is not present 0 HRS10_1 A hardware service request for channel 10 is present 0x1 HRS11 Hardware Request Status Channel 11 11 1 read-only HRS11_0 A hardware service request for channel 11 is not present 0 HRS11_1 A hardware service request for channel 11 is present 0x1 HRS12 Hardware Request Status Channel 12 12 1 read-only HRS12_0 A hardware service request for channel 12 is not present 0 HRS12_1 A hardware service request for channel 12 is present 0x1 HRS13 Hardware Request Status Channel 13 13 1 read-only HRS13_0 A hardware service request for channel 13 is not present 0 HRS13_1 A hardware service request for channel 13 is present 0x1 HRS14 Hardware Request Status Channel 14 14 1 read-only HRS14_0 A hardware service request for channel 14 is not present 0 HRS14_1 A hardware service request for channel 14 is present 0x1 HRS15 Hardware Request Status Channel 15 15 1 read-only HRS15_0 A hardware service request for channel 15 is not present 0 HRS15_1 A hardware service request for channel 15 is present 0x1 EARS Enable Asynchronous Request in Stop Register 0x44 32 read-write 0 0xFFFFFFFF EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 read-write EDREQ_0_0 Disable asynchronous DMA request for channel 0. 0 EDREQ_0_1 Enable asynchronous DMA request for channel 0. 0x1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 1 1 read-write EDREQ_1_0 Disable asynchronous DMA request for channel 1 0 EDREQ_1_1 Enable asynchronous DMA request for channel 1. 0x1 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 2 1 read-write EDREQ_2_0 Disable asynchronous DMA request for channel 2. 0 EDREQ_2_1 Enable asynchronous DMA request for channel 2. 0x1 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 3 1 read-write EDREQ_3_0 Disable asynchronous DMA request for channel 3. 0 EDREQ_3_1 Enable asynchronous DMA request for channel 3. 0x1 EDREQ_4 Enable asynchronous DMA request in stop mode for channel 4 4 1 read-write EDREQ_4_0 Disable asynchronous DMA request for channel 4. 0 EDREQ_4_1 Enable asynchronous DMA request for channel 4. 0x1 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5 5 1 read-write EDREQ_5_0 Disable asynchronous DMA request for channel 5. 0 EDREQ_5_1 Enable asynchronous DMA request for channel 5. 0x1 EDREQ_6 Enable asynchronous DMA request in stop mode for channel 6 6 1 read-write EDREQ_6_0 Disable asynchronous DMA request for channel 6. 0 EDREQ_6_1 Enable asynchronous DMA request for channel 6. 0x1 EDREQ_7 Enable asynchronous DMA request in stop mode for channel 7 7 1 read-write EDREQ_7_0 Disable asynchronous DMA request for channel 7. 0 EDREQ_7_1 Enable asynchronous DMA request for channel 7. 0x1 EDREQ_8 Enable asynchronous DMA request in stop mode for channel 8 8 1 read-write EDREQ_8_0 Disable asynchronous DMA request for channel 8. 0 EDREQ_8_1 Enable asynchronous DMA request for channel 8. 0x1 EDREQ_9 Enable asynchronous DMA request in stop mode for channel 9 9 1 read-write EDREQ_9_0 Disable asynchronous DMA request for channel 9. 0 EDREQ_9_1 Enable asynchronous DMA request for channel 9. 0x1 EDREQ_10 Enable asynchronous DMA request in stop mode for channel 10 10 1 read-write EDREQ_10_0 Disable asynchronous DMA request for channel 10. 0 EDREQ_10_1 Enable asynchronous DMA request for channel 10. 0x1 EDREQ_11 Enable asynchronous DMA request in stop mode for channel 11 11 1 read-write EDREQ_11_0 Disable asynchronous DMA request for channel 11. 0 EDREQ_11_1 Enable asynchronous DMA request for channel 11. 0x1 EDREQ_12 Enable asynchronous DMA request in stop mode for channel 12 12 1 read-write EDREQ_12_0 Disable asynchronous DMA request for channel 12. 0 EDREQ_12_1 Enable asynchronous DMA request for channel 12. 0x1 EDREQ_13 Enable asynchronous DMA request in stop mode for channel 13 13 1 read-write EDREQ_13_0 Disable asynchronous DMA request for channel 13. 0 EDREQ_13_1 Enable asynchronous DMA request for channel 13. 0x1 EDREQ_14 Enable asynchronous DMA request in stop mode for channel 14 14 1 read-write EDREQ_14_0 Disable asynchronous DMA request for channel 14. 0 EDREQ_14_1 Enable asynchronous DMA request for channel 14. 0x1 EDREQ_15 Enable asynchronous DMA request in stop mode for channel 15 15 1 read-write EDREQ_15_0 Disable asynchronous DMA request for channel 15. 0 EDREQ_15_1 Enable asynchronous DMA request for channel 15. 0x1 DCHPRI3 Channel Priority Register 0x100 8 read-write 0x3 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI2 Channel Priority Register 0x101 8 read-write 0x2 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI1 Channel Priority Register 0x102 8 read-write 0x1 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI0 Channel Priority Register 0x103 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI7 Channel Priority Register 0x104 8 read-write 0x7 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI6 Channel Priority Register 0x105 8 read-write 0x6 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI5 Channel Priority Register 0x106 8 read-write 0x5 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI4 Channel Priority Register 0x107 8 read-write 0x4 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI11 Channel Priority Register 0x108 8 read-write 0xB 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI10 Channel Priority Register 0x109 8 read-write 0xA 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI9 Channel Priority Register 0x10A 8 read-write 0x9 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI8 Channel Priority Register 0x10B 8 read-write 0x8 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI15 Channel Priority Register 0x10C 8 read-write 0xF 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI14 Channel Priority Register 0x10D 8 read-write 0xE 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI13 Channel Priority Register 0x10E 8 read-write 0xD 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI12 Channel Priority Register 0x10F 8 read-write 0xC 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 TCD0_SADDR TCD Source Address 0x1000 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD0_SOFF TCD Signed Source Address Offset 0x1004 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD0_ATTR TCD Transfer Attributes 0x1006 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD0_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD0_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD0_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD0_SLAST TCD Last Source Address Adjustment 0x100C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD0_DADDR TCD Destination Address 0x1010 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD0_DOFF TCD Signed Destination Address Offset 0x1014 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD0_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD0_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD0_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1018 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD0_CSR TCD Control and Status 0x101C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD0_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x101E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD0_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x101E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD1_SADDR TCD Source Address 0x1020 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD1_SOFF TCD Signed Source Address Offset 0x1024 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD1_ATTR TCD Transfer Attributes 0x1026 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD1_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x1028 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD1_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x1028 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD1_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x1028 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD1_SLAST TCD Last Source Address Adjustment 0x102C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD1_DADDR TCD Destination Address 0x1030 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD1_DOFF TCD Signed Destination Address Offset 0x1034 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD1_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x1036 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD1_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x1036 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD1_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1038 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD1_CSR TCD Control and Status 0x103C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD1_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x103E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD1_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x103E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD2_SADDR TCD Source Address 0x1040 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD2_SOFF TCD Signed Source Address Offset 0x1044 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD2_ATTR TCD Transfer Attributes 0x1046 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD2_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x1048 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD2_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x1048 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD2_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x1048 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD2_SLAST TCD Last Source Address Adjustment 0x104C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD2_DADDR TCD Destination Address 0x1050 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD2_DOFF TCD Signed Destination Address Offset 0x1054 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD2_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x1056 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD2_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x1056 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD2_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1058 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD2_CSR TCD Control and Status 0x105C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD2_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x105E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD2_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x105E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD3_SADDR TCD Source Address 0x1060 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD3_SOFF TCD Signed Source Address Offset 0x1064 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD3_ATTR TCD Transfer Attributes 0x1066 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD3_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x1068 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD3_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x1068 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD3_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x1068 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD3_SLAST TCD Last Source Address Adjustment 0x106C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD3_DADDR TCD Destination Address 0x1070 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD3_DOFF TCD Signed Destination Address Offset 0x1074 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD3_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x1076 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD3_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x1076 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD3_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1078 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD3_CSR TCD Control and Status 0x107C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD3_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x107E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD3_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x107E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD4_SADDR TCD Source Address 0x1080 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD4_SOFF TCD Signed Source Address Offset 0x1084 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD4_ATTR TCD Transfer Attributes 0x1086 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD4_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x1088 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD4_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x1088 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD4_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x1088 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD4_SLAST TCD Last Source Address Adjustment 0x108C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD4_DADDR TCD Destination Address 0x1090 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD4_DOFF TCD Signed Destination Address Offset 0x1094 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD4_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x1096 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD4_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x1096 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD4_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1098 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD4_CSR TCD Control and Status 0x109C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD4_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x109E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD4_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x109E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD5_SADDR TCD Source Address 0x10A0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD5_SOFF TCD Signed Source Address Offset 0x10A4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD5_ATTR TCD Transfer Attributes 0x10A6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD5_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x10A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD5_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x10A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD5_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x10A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD5_SLAST TCD Last Source Address Adjustment 0x10AC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD5_DADDR TCD Destination Address 0x10B0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD5_DOFF TCD Signed Destination Address Offset 0x10B4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD5_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x10B6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD5_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x10B6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD5_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10B8 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD5_CSR TCD Control and Status 0x10BC 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD5_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x10BE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD5_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x10BE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD6_SADDR TCD Source Address 0x10C0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD6_SOFF TCD Signed Source Address Offset 0x10C4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD6_ATTR TCD Transfer Attributes 0x10C6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD6_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x10C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD6_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x10C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD6_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x10C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD6_SLAST TCD Last Source Address Adjustment 0x10CC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD6_DADDR TCD Destination Address 0x10D0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD6_DOFF TCD Signed Destination Address Offset 0x10D4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD6_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x10D6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD6_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x10D6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD6_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10D8 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD6_CSR TCD Control and Status 0x10DC 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD6_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x10DE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD6_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x10DE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD7_SADDR TCD Source Address 0x10E0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD7_SOFF TCD Signed Source Address Offset 0x10E4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD7_ATTR TCD Transfer Attributes 0x10E6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD7_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x10E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD7_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x10E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD7_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x10E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD7_SLAST TCD Last Source Address Adjustment 0x10EC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD7_DADDR TCD Destination Address 0x10F0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD7_DOFF TCD Signed Destination Address Offset 0x10F4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD7_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x10F6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD7_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x10F6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD7_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10F8 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD7_CSR TCD Control and Status 0x10FC 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD7_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x10FE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD7_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x10FE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD8_SADDR TCD Source Address 0x1100 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD8_SOFF TCD Signed Source Address Offset 0x1104 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD8_ATTR TCD Transfer Attributes 0x1106 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD8_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x1108 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD8_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x1108 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD8_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x1108 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD8_SLAST TCD Last Source Address Adjustment 0x110C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD8_DADDR TCD Destination Address 0x1110 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD8_DOFF TCD Signed Destination Address Offset 0x1114 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD8_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x1116 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD8_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x1116 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD8_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1118 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD8_CSR TCD Control and Status 0x111C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD8_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x111E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD8_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x111E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD9_SADDR TCD Source Address 0x1120 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD9_SOFF TCD Signed Source Address Offset 0x1124 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD9_ATTR TCD Transfer Attributes 0x1126 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD9_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x1128 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD9_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x1128 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD9_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x1128 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD9_SLAST TCD Last Source Address Adjustment 0x112C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD9_DADDR TCD Destination Address 0x1130 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD9_DOFF TCD Signed Destination Address Offset 0x1134 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD9_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x1136 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD9_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x1136 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD9_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1138 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD9_CSR TCD Control and Status 0x113C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD9_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x113E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD9_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x113E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD10_SADDR TCD Source Address 0x1140 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD10_SOFF TCD Signed Source Address Offset 0x1144 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD10_ATTR TCD Transfer Attributes 0x1146 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD10_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x1148 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD10_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x1148 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD10_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x1148 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD10_SLAST TCD Last Source Address Adjustment 0x114C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD10_DADDR TCD Destination Address 0x1150 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD10_DOFF TCD Signed Destination Address Offset 0x1154 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD10_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x1156 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD10_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x1156 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD10_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1158 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD10_CSR TCD Control and Status 0x115C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD10_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x115E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD10_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x115E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD11_SADDR TCD Source Address 0x1160 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD11_SOFF TCD Signed Source Address Offset 0x1164 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD11_ATTR TCD Transfer Attributes 0x1166 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD11_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x1168 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD11_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x1168 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD11_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x1168 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD11_SLAST TCD Last Source Address Adjustment 0x116C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD11_DADDR TCD Destination Address 0x1170 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD11_DOFF TCD Signed Destination Address Offset 0x1174 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD11_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x1176 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD11_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x1176 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD11_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1178 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD11_CSR TCD Control and Status 0x117C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD11_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x117E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD11_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x117E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD12_SADDR TCD Source Address 0x1180 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD12_SOFF TCD Signed Source Address Offset 0x1184 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD12_ATTR TCD Transfer Attributes 0x1186 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD12_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x1188 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD12_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x1188 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD12_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x1188 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD12_SLAST TCD Last Source Address Adjustment 0x118C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD12_DADDR TCD Destination Address 0x1190 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD12_DOFF TCD Signed Destination Address Offset 0x1194 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD12_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x1196 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD12_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x1196 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD12_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1198 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD12_CSR TCD Control and Status 0x119C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD12_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x119E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD12_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x119E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD13_SADDR TCD Source Address 0x11A0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD13_SOFF TCD Signed Source Address Offset 0x11A4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD13_ATTR TCD Transfer Attributes 0x11A6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD13_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x11A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD13_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x11A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD13_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x11A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD13_SLAST TCD Last Source Address Adjustment 0x11AC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD13_DADDR TCD Destination Address 0x11B0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD13_DOFF TCD Signed Destination Address Offset 0x11B4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD13_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x11B6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD13_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x11B6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD13_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x11B8 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD13_CSR TCD Control and Status 0x11BC 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD13_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x11BE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD13_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x11BE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD14_SADDR TCD Source Address 0x11C0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD14_SOFF TCD Signed Source Address Offset 0x11C4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD14_ATTR TCD Transfer Attributes 0x11C6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD14_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x11C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD14_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x11C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD14_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x11C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD14_SLAST TCD Last Source Address Adjustment 0x11CC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD14_DADDR TCD Destination Address 0x11D0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD14_DOFF TCD Signed Destination Address Offset 0x11D4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD14_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x11D6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD14_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x11D6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD14_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x11D8 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD14_CSR TCD Control and Status 0x11DC 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD14_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x11DE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD14_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x11DE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD15_SADDR TCD Source Address 0x11E0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD15_SOFF TCD Signed Source Address Offset 0x11E4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD15_ATTR TCD Transfer Attributes 0x11E6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 16-byte burst 0x4 SSIZE_5 32-byte burst 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD15_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) NBYTES 0x11E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD15_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) NBYTES 0x11E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD15_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) NBYTES 0x11E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD15_SLAST TCD Last Source Address Adjustment 0x11EC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD15_DADDR TCD Destination Address 0x11F0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD15_DOFF TCD Signed Destination Address Offset 0x11F4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD15_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) CITER 0x11F6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD15_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) CITER 0x11F6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD15_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x11F8 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD15_CSR TCD Control and Status 0x11FC 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD15_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) BITER 0x11FE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD15_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) BITER 0x11FE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 MPU MPU MPU 0x4000D000 0 0x820 registers CESR Control/Error Status Register 0 32 read-write 0x814001 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 MPU is disabled. All accesses from all bus masters are allowed. 0 VLD_1 MPU is enabled 0x1 NRGD Number Of Region Descriptors 8 4 read-only NRGD_0 8 region descriptors 0 NRGD_1 12 region descriptors 0x1 NRGD_2 16 region descriptors 0x2 NSP Number Of Slave Ports 12 4 read-only HRL Hardware Revision Level 16 4 read-only SPERR3 Slave Port 3 Error 28 1 read-write oneToClear SPERR3_0 No error has occurred for slave port 3. 0 SPERR3_1 An error has occurred for slave port 3. 0x1 SPERR2 Slave Port 2 Error 29 1 read-write oneToClear SPERR2_0 No error has occurred for slave port 2. 0 SPERR2_1 An error has occurred for slave port 2. 0x1 SPERR1 Slave Port 1 Error 30 1 read-write oneToClear SPERR1_0 No error has occurred for slave port 1. 0 SPERR1_1 An error has occurred for slave port 1. 0x1 SPERR0 Slave Port 0 Error 31 1 read-write oneToClear SPERR0_0 No error has occurred for slave port 0. 0 SPERR0_1 An error has occurred for slave port 0. 0x1 EAR0 Error Address Register, slave port 0 0x10 32 read-only 0 0xFFFFFFFF EADDR Error Address 0 32 read-only EDR0 Error Detail Register, slave port 0 0x14 32 read-only 0 0xFFFFFFFF ERW Error Read/Write 0 1 read-only ERW_0 Read 0 ERW_1 Write 0x1 EATTR Error Attributes 1 3 read-only EATTR_0 User mode, instruction access 0 EATTR_1 User mode, data access 0x1 EATTR_2 Supervisor mode, instruction access 0x2 EATTR_3 Supervisor mode, data access 0x3 EMN Error Master Number 4 4 read-only EPID Error Process Identification 8 8 read-only EACD Error Access Control Detail 16 16 read-only EAR1 Error Address Register, slave port 1 0x18 32 read-only 0 0xFFFFFFFF EADDR Error Address 0 32 read-only EDR1 Error Detail Register, slave port 1 0x1C 32 read-only 0 0xFFFFFFFF ERW Error Read/Write 0 1 read-only ERW_0 Read 0 ERW_1 Write 0x1 EATTR Error Attributes 1 3 read-only EATTR_0 User mode, instruction access 0 EATTR_1 User mode, data access 0x1 EATTR_2 Supervisor mode, instruction access 0x2 EATTR_3 Supervisor mode, data access 0x3 EMN Error Master Number 4 4 read-only EPID Error Process Identification 8 8 read-only EACD Error Access Control Detail 16 16 read-only EAR2 Error Address Register, slave port 2 0x20 32 read-only 0 0xFFFFFFFF EADDR Error Address 0 32 read-only EDR2 Error Detail Register, slave port 2 0x24 32 read-only 0 0xFFFFFFFF ERW Error Read/Write 0 1 read-only ERW_0 Read 0 ERW_1 Write 0x1 EATTR Error Attributes 1 3 read-only EATTR_0 User mode, instruction access 0 EATTR_1 User mode, data access 0x1 EATTR_2 Supervisor mode, instruction access 0x2 EATTR_3 Supervisor mode, data access 0x3 EMN Error Master Number 4 4 read-only EPID Error Process Identification 8 8 read-only EACD Error Access Control Detail 16 16 read-only EAR3 Error Address Register, slave port 3 0x28 32 read-only 0 0xFFFFFFFF EADDR Error Address 0 32 read-only EDR3 Error Detail Register, slave port 3 0x2C 32 read-only 0 0xFFFFFFFF ERW Error Read/Write 0 1 read-only ERW_0 Read 0 ERW_1 Write 0x1 EATTR Error Attributes 1 3 read-only EATTR_0 User mode, instruction access 0 EATTR_1 User mode, data access 0x1 EATTR_2 Supervisor mode, instruction access 0x2 EATTR_3 Supervisor mode, data access 0x3 EMN Error Master Number 4 4 read-only EPID Error Process Identification 8 8 read-only EACD Error Access Control Detail 16 16 read-only RGD0_WORD0 Region Descriptor 0, Word 0 0x400 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD0_WORD1 Region Descriptor 0, Word 1 0x404 32 read-write 0xFFFFFFFF 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD0_WORD2 Region Descriptor 0, Word 2 0x408 32 read-write 0x61F7DF 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGD0_WORD3 Region Descriptor 0, Word 3 0x40C 32 read-write 0x1 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 Region descriptor is invalid 0 VLD_1 Region descriptor is valid 0x1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD1_WORD0 Region Descriptor 1, Word 0 0x410 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD1_WORD1 Region Descriptor 1, Word 1 0x414 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD1_WORD2 Region Descriptor 1, Word 2 0x418 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGD1_WORD3 Region Descriptor 1, Word 3 0x41C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 Region descriptor is invalid 0 VLD_1 Region descriptor is valid 0x1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD2_WORD0 Region Descriptor 2, Word 0 0x420 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD2_WORD1 Region Descriptor 2, Word 1 0x424 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD2_WORD2 Region Descriptor 2, Word 2 0x428 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGD2_WORD3 Region Descriptor 2, Word 3 0x42C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 Region descriptor is invalid 0 VLD_1 Region descriptor is valid 0x1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD3_WORD0 Region Descriptor 3, Word 0 0x430 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD3_WORD1 Region Descriptor 3, Word 1 0x434 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD3_WORD2 Region Descriptor 3, Word 2 0x438 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGD3_WORD3 Region Descriptor 3, Word 3 0x43C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 Region descriptor is invalid 0 VLD_1 Region descriptor is valid 0x1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD4_WORD0 Region Descriptor 4, Word 0 0x440 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD4_WORD1 Region Descriptor 4, Word 1 0x444 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD4_WORD2 Region Descriptor 4, Word 2 0x448 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGD4_WORD3 Region Descriptor 4, Word 3 0x44C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 Region descriptor is invalid 0 VLD_1 Region descriptor is valid 0x1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD5_WORD0 Region Descriptor 5, Word 0 0x450 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD5_WORD1 Region Descriptor 5, Word 1 0x454 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD5_WORD2 Region Descriptor 5, Word 2 0x458 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGD5_WORD3 Region Descriptor 5, Word 3 0x45C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 Region descriptor is invalid 0 VLD_1 Region descriptor is valid 0x1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD6_WORD0 Region Descriptor 6, Word 0 0x460 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD6_WORD1 Region Descriptor 6, Word 1 0x464 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD6_WORD2 Region Descriptor 6, Word 2 0x468 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGD6_WORD3 Region Descriptor 6, Word 3 0x46C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 Region descriptor is invalid 0 VLD_1 Region descriptor is valid 0x1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGD7_WORD0 Region Descriptor 7, Word 0 0x470 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 5 27 read-write RGD7_WORD1 Region Descriptor 7, Word 1 0x474 32 read-write 0x1F 0xFFFFFFFF ENDADDR End Address 5 27 read-write RGD7_WORD2 Region Descriptor 7, Word 2 0x478 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGD7_WORD3 Region Descriptor 7, Word 3 0x47C 32 read-write 0 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 Region descriptor is invalid 0 VLD_1 Region descriptor is valid 0x1 PIDMASK Process Identifier Mask 16 8 read-write PID Process Identifier 24 8 read-write RGDAAC0 Region Descriptor Alternate Access Control 0 0x800 32 read-write 0x61F7DF 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGDAAC1 Region Descriptor Alternate Access Control 1 0x804 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGDAAC2 Region Descriptor Alternate Access Control 2 0x808 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGDAAC3 Region Descriptor Alternate Access Control 3 0x80C 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGDAAC4 Region Descriptor Alternate Access Control 4 0x810 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGDAAC5 Region Descriptor Alternate Access Control 5 0x814 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGDAAC6 Region Descriptor Alternate Access Control 6 0x818 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 RGDAAC7 Region Descriptor Alternate Access Control 7 0x81C 32 read-write 0 0xFFFFFFFF M0UM Bus Master 0 User Mode Access Control 0 3 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0SM_0 r/w/x; read, write and execute allowed 0 M0SM_1 r/x; read and execute allowed, but no write 0x1 M0SM_2 r/w; read and write allowed, but no execute 0x2 M0SM_3 Same as User mode defined in M0UM 0x3 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0PE_0 Do not include the process identifier in the evaluation 0 M0PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M1UM Bus Master 1 User Mode Access Control 6 3 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1SM_0 r/w/x; read, write and execute allowed 0 M1SM_1 r/x; read and execute allowed, but no write 0x1 M1SM_2 r/w; read and write allowed, but no execute 0x2 M1SM_3 Same as User mode defined in M1UM 0x3 M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1PE_0 Do not include the process identifier in the evaluation 0 M1PE_1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 0x1 M2UM Bus Master 2 User Mode Access Control 12 3 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2SM_0 r/w/x; read, write and execute allowed 0 M2SM_1 r/x; read and execute allowed, but no write 0x1 M2SM_2 r/w; read and write allowed, but no execute 0x2 M2SM_3 Same as User mode defined in M2UM 0x3 M3UM Bus Master 3 User Mode Access Control 18 3 read-write M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write M3SM_0 r/w/x; read, write and execute allowed 0 M3SM_1 r/x; read and execute allowed, but no write 0x1 M3SM_2 r/w; read and write allowed, but no execute 0x2 M3SM_3 Same as User mode defined in M3UM 0x3 M4WE Bus Master 4 Write Enable 24 1 read-write M4WE_0 Bus master 4 writes terminate with an access error and the write is not performed 0 M4WE_1 Bus master 4 writes allowed 0x1 M4RE Bus Master 4 Read Enable 25 1 read-write M4RE_0 Bus master 4 reads terminate with an access error and the read is not performed 0 M4RE_1 Bus master 4 reads allowed 0x1 M5WE Bus Master 5 Write Enable 26 1 read-write M5WE_0 Bus master 5 writes terminate with an access error and the write is not performed 0 M5WE_1 Bus master 5 writes allowed 0x1 M5RE Bus Master 5 Read Enable 27 1 read-write M5RE_0 Bus master 5 reads terminate with an access error and the read is not performed 0 M5RE_1 Bus master 5 reads allowed 0x1 M6WE Bus Master 6 Write Enable 28 1 read-write M6WE_0 Bus master 6 writes terminate with an access error and the write is not performed 0 M6WE_1 Bus master 6 writes allowed 0x1 M6RE Bus Master 6 Read Enable 29 1 read-write M6RE_0 Bus master 6 reads terminate with an access error and the read is not performed 0 M6RE_1 Bus master 6 reads allowed 0x1 M7WE Bus Master 7 Write Enable 30 1 read-write M7WE_0 Bus master 7 writes terminate with an access error and the write is not performed 0 M7WE_1 Bus master 7 writes allowed 0x1 M7RE Bus Master 7 Read Enable 31 1 read-write M7RE_0 Bus master 7 reads terminate with an access error and the read is not performed 0 M7RE_1 Bus master 7 reads allowed 0x1 ERM ERM ERM 0x40018000 0 0x114 registers CR0 ERM Configuration Register 0 0 32 read-write 0 0xFFFFFFFF ENCIE1 ENCIE1 26 1 read-write ENCIE1_0 Interrupt notification of Memory 1 non-correctable error events is disabled. 0 ENCIE1_1 Interrupt notification of Memory 1 non-correctable error events is enabled. 0x1 ESCIE1 ESCIE1 27 1 read-write ESCIE1_0 Interrupt notification of Memory 1 single-bit correction events is disabled. 0 ESCIE1_1 Interrupt notification of Memory 1 single-bit correction events is enabled. 0x1 ENCIE0 ENCIE0 30 1 read-write ENCIE0_0 Interrupt notification of Memory 0 non-correctable error events is disabled. 0 ENCIE0_1 Interrupt notification of Memory 0 non-correctable error events is enabled. 0x1 ESCIE0 ESCIE0 31 1 read-write ESCIE0_0 Interrupt notification of Memory 0 single-bit correction events is disabled. 0 ESCIE0_1 Interrupt notification of Memory 0 single-bit correction events is enabled. 0x1 SR0 ERM Status Register 0 0x10 32 read-write 0 0xFFFFFFFF NCE1 NCE1 26 1 read-write oneToClear NCE1_0 No non-correctable error event on Memory 1 detected. 0 NCE1_1 Non-correctable error event on Memory 1 detected. 0x1 SBC1 SBC1 27 1 read-write oneToClear SBC1_0 No single-bit correction event on Memory 1 detected. 0 SBC1_1 Single-bit correction event on Memory 1 detected. 0x1 NCE0 NCE0 30 1 read-write oneToClear NCE0_0 No non-correctable error event on Memory 0 detected. 0 NCE0_1 Non-correctable error event on Memory 0 detected. 0x1 SBC0 SBC0 31 1 read-write oneToClear SBC0_0 No single-bit correction event on Memory 0 detected. 0 SBC0_1 Single-bit correction event on Memory 0 detected. 0x1 EAR0 ERM Memory n Error Address Register 0x100 32 read-only 0 0xFFFFFFFF EAR EAR 0 32 read-only EAR1 ERM Memory n Error Address Register 0x110 32 read-only 0 0xFFFFFFFF EAR EAR 0 32 read-only EIM EIM EIM 0x40019000 0 0x208 registers EIMCR Error Injection Module Configuration Register 0 32 read-write 0 0xFFFFFFFF GEIEN Global Error Injection Enable 0 1 read-write GEIEN_0 Disabled 0 GEIEN_1 Enabled 0x1 EICHEN Error Injection Channel Enable register 0x4 32 read-write 0 0xFFFFFFFF EICH1EN Error Injection Channel 1 Enable 30 1 read-write EICH1EN_0 Error injection is disabled on Error Injection Channel 1 0 EICH1EN_1 Error injection is enabled on Error Injection Channel 1 0x1 EICH0EN Error Injection Channel 0 Enable 31 1 read-write EICH0EN_0 Error injection is disabled on Error Injection Channel 0 0 EICH0EN_1 Error injection is enabled on Error Injection Channel 0 0x1 2 0x100 EICHDn[%s] no description available 0x100 EICHD_WORD0 Error Injection Channel Descriptor n, Word0 0 32 read-write 0 0xFFFFFFFF CHKBIT_MASK Checkbit Mask 25 7 read-write EICHD_WORD1 Error Injection Channel Descriptor n, Word1 0x4 32 read-write 0 0xFFFFFFFF B0_3DATA_MASK Data Mask Bytes 0-3 0 32 read-write FTFM FTFM FTFM 0x40020000 0 0x30 registers FSTAT Flash Status Register 0 8 read-write 0x80 0xF0 MGSTAT0 Memory Controller Status Flag 0 0 1 read-only MGSTAT1 Memory Controller Status Flag 1 1 1 read-only MGSTAT2 Memory Controller Status Flag 2 2 1 read-only MGSTAT3 Memory Controller Status Flag 3 3 1 read-only FPVIOL Flash Protection Violation Flag 4 1 read-write oneToClear FPVIOL_0 No protection violation detected 0 FPVIOL_1 Protection violation detected 0x1 ACCERR Flash Access Error Flag 5 1 read-write oneToClear ACCERR_0 No access error detected 0 ACCERR_1 Access error detected 0x1 RDCOLERR FTFM Read Collision Error Flag 6 1 read-write oneToClear RDCOLERR_0 No collision error detected 0 RDCOLERR_1 Collision error detected 0x1 CCIF Command Complete Interrupt Flag 7 1 read-write oneToClear CCIF_0 FTFM command or emulated EEPROM file system operation in progress 0 CCIF_1 FTFM command or emulated EEPROM file system operation has completed 0x1 FCNFG Flash Configuration Register 0x1 8 read-write 0 0xFC EEERDY EEE Ready 0 1 read-only EEERDY_0 FlexRAM is not available for emulated EEPROM operation 0 EEERDY_1 The FlexRAM is available for EEPROM operations where: (1) reads from the FlexRAM return data previously written to the FlexRAM in emulated EEPROM mode and (2) writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup data memory. 0x1 RAMRDY RAM Ready 1 1 read-only RAMRDY_0 FlexRAM is not available for traditional RAM access 0 RAMRDY_1 FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations 0x1 ERSSUSP Erase Suspend 4 1 read-write ERSSUSP_0 No suspend requested 0 ERSSUSP_1 Suspend the current Erase Flash Sector command execution 0x1 ERSAREQ Erase All Request 5 1 read-only ERSAREQ_0 No request or request complete 0 ERSAREQ_1 Request to run the Erase All Blocks Unsecure command. 0x1 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write RDCOLLIE_0 Read collision error interrupt disabled 0 RDCOLLIE_1 Read collision error interrupt enabled. An interrupt request is generated whenever an FTFM read collision error is detected (see the description of FSTAT[RDCOLERR]). 0x1 CCIE Command Complete Interrupt Enable 7 1 read-write CCIE_0 Command complete interrupt disabled 0 CCIE_1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. 0x1 FSEC Flash Security Register 0x2 8 read-only 0 0 SEC Flash Security 0 2 read-only SEC_0 MCU security status is secure 0 SEC_1 MCU security status is secure 0x1 SEC_2 MCU security status is unsecure (The standard shipping condition of the FTFM is unsecure.) 0x2 SEC_3 MCU security status is secure 0x3 FSLACC Factory Failure Analysis Access Code 2 2 read-only FSLACC_0 Factory access granted 0 FSLACC_1 Factory access denied 0x1 FSLACC_2 Factory access denied 0x2 FSLACC_3 Factory access granted 0x3 MEEN Mass Erase Enable Bits 4 2 read-only MEEN_0 Mass erase is enabled 0 MEEN_1 Mass erase is enabled 0x1 MEEN_2 Mass erase is disabled 0x2 MEEN_3 Mass erase is enabled 0x3 KEYEN Backdoor Key Security Enable 6 2 read-only KEYEN_0 Backdoor key access disabled 0 KEYEN_1 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) 0x1 KEYEN_2 Backdoor key access enabled 0x2 KEYEN_3 Backdoor key access disabled 0x3 FOPT Flash Option Register 0x3 8 read-only 0 0 OPT Nonvolatile Option 0 8 read-only 12 0x1 3,2,1,0,7,6,5,4,B,A,9,8 FCCOB%s Flash Common Command Object Registers 0x4 8 read-write 0 0xFF CCOBn CCOBn 0 8 read-write 4 0x1 3,2,1,0 FPROT%s Program Flash Protection Registers 0x10 8 read-write 0 0 PROT Program Flash Region Protect 0 8 read-write FEPROT EEPROM Protection Register 0x16 8 read-write 0 0 EPROT EEPROM Region Protect 0 8 read-write FDPROT Data Flash Protection Register 0x17 8 read-write 0 0 DPROT Data Flash Region Protect 0 8 read-write FCSESTAT1 Flash CSEc Status Register 1 0x2C 8 read-only 0 0xFF BSY Busy 0 1 read-only BSY_0 CSEc command processing has completed 0 BSY_1 CSEc command processing is in progress 0x1 SB Secure Boot 1 1 read-only SB_0 Secure boot not activated 0 SB_1 Secure boot is activated 0x1 BIN Secure Boot Initialization 2 1 read-only BIN_0 Secure boot personalization not completed 0 BIN_1 Secure boot personalization has completed 0x1 BFN Secure Boot Finished 3 1 read-only BFN_0 Secure Boot is not finished 0 BFN_1 Secure Boot has finished 0x1 BOK Secure Boot OK 4 1 read-only BOK_0 Secure boot is not complete, or secure boot failure 0 BOK_1 Secure boot was successful 0x1 RIN Random Number Generator Initialized 5 1 read-only RIN_0 Random number generator is not initialized 0 RIN_1 Random number generator is initialized 0x1 EDB External Debug 6 1 read-only EDB_0 External debugger not attached 0 EDB_1 External debugger is attached 0x1 IDB Internal Debug 7 1 read-only IDB_0 Internal debug functions are disabled 0 IDB_1 Internal debugger functions are enabled 0x1 FCSESTAT0 Flash CSEc Status Register 0 0x2D 8 read-only 0 0xFF CMDTYPE Command Type 1 1 read-only CMDTYPE_0 Flash command or no command 0 CMDTYPE_1 CSEc command 0x1 MEMERR Memory Error 2 1 read-only MEMERR_0 Uncorrectable ECC fault not detected, CSE_PRAM access not blocked 0 MEMERR_1 Uncorrectable ECC fault detected, CSE_PRAM access blocked 0x1 FERSTAT Flash Error Status Register 0x2E 8 read-write 0 0xF3 PDFDIF Platform FlexRAM Double Bit Fault Detect Interrupt Flag 0 1 read-write oneToClear PDFDIF_0 Fault not detected during a valid FlexRAM or CSE_PRAM read access from the platform flash controller 0 PDFDIF_1 Fault detected (or FERCNFG[PFDFD] is set) during a valid FlexRAM or CSE_PRAM read access from the platform flash controller 0x1 DFDIF Platform Flash Double Bit Fault Detect Interrupt Flag 1 1 read-write oneToClear DFDIF_0 Fault not detected during a valid flash read access from the platform flash controller 0 DFDIF_1 Fault detected (or FERCNFG[FDFD] is set) during a valid flash read access from the platform flash controller 0x1 EDFDIF Controller FlexRAM Double Bit Fault Detect Interrupt Flag 2 1 read-write oneToClear EDFDIF_0 Fault not detected during a valid FlexRAM or CSE_PRAM read access from the flash memory controller 0 EDFDIF_1 Fault detected (or FERCNFG[EFDFD] is set) during a valid FlexRAM or CSE_PRAM read access from the flash memory controller 0x1 CDFDIF Controller Flash Double Bit Fault Detect Interrupt Flag 3 1 read-write oneToClear CDFDIF_0 Fault not detected during a valid internal RAM or flash read access from the flash memory controller 0 CDFDIF_1 Fault detected (or FERCNFG[CFDFD] is set) during a valid internal RAM or flash read access from the flash memory controller 0x1 FERCNFG Flash Error Configuration Register 0x2F 8 read-write 0xD 0xFF PDFDIE Platform FlexRAM Double Bit Fault Detect Interrupt Enable 0 1 read-write PDFDIE_0 Fault detect interrupt disabled 0 PDFDIE_1 Fault detect interrupt enabled. An interrupt request is generated whenever the FERSTAT[PDFDIF] flag is set. 0x1 DFDIE Platform Flash Double Bit Fault Detect Interrupt Enable 1 1 read-write DFDIE_0 Fault detect interrupt disabled 0 DFDIE_1 Fault detect interrupt enabled. An interrupt request is generated whenever the FERSTAT[DFDIF] flag is set. 0x1 EDFDIE Controller FlexRAM Double Bit Fault Detect Interrupt Enable 2 1 read-write EDFDIE_0 Fault detect interrupt disabled 0 EDFDIE_1 Fault detect interrupt enabled. An interrupt request is generated whenever the FERSTAT[EDFDIF] flag is set. 0x1 CDFDIE Controller Flash Double Bit Fault Detect Interrupt Enable 3 1 read-write CDFDIE_0 Fault detect interrupt disabled 0 CDFDIE_1 Fault detect interrupt enabled. An interrupt request is generated whenever the FERSTAT[CDFDIF] flag is set. 0x1 PFDFD Platform FlexRAM Force Double Bit Fault Detect 4 1 read-write PFDFD_0 FERSTAT[PDFDIF] sets only if a fault is detected during a valid FlexRAM or CSE_PRAM read access from the platform flash controller 0 PFDFD_1 FERSTAT[PDFDIF] sets during any valid FlexRAM or CSE_PRAM read access from the platform flash controller. An interrupt request is generated if the PDFDIE bit is set. 0x1 FDFD Force Double Bit Fault Detect 5 1 read-write FDFD_0 FERSTAT[DFDIF] sets only if a fault is detected during a valid flash read access from the platform flash controller 0 FDFD_1 FERSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set. 0x1 EFDFD Controller FlexRAM Force Double Bit Fault Detect 6 1 read-write EFDFD_0 FERSTAT[EDFDIF] sets only if a fault is detected during a valid FlexRAM or CSE_PRAM read access from the flash memory controller 0 EFDFD_1 FERSTAT[EDFDIF] sets during the next FlexRAM or CSE_PRAM read access from the flash memory controller. An interrupt request is generated if the EDFDIE bit is set. 0x1 CFDFD Controller Flash Force Double Bit Fault Detect 7 1 read-write CFDFD_0 FERSTAT[CDFDIF] sets only if a fault is detected during a valid internal RAM or flash read access from the flash memory controller 0 CFDFD_1 FERSTAT[CDFDIF] sets during the next internal RAM or flash read access from the flash memory controller. An interrupt request is generated if the CDFDIE bit is set. 0x1 DMAMUX DMAMUX DMAMUX 0x40021000 0 0x10 registers 16 0x1 CHCFG[%s] Channel Configuration register 0 8 read-write 0 0xFF SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. 0x1 ENBL DMA Channel Enable 7 1 read-write ENBL_0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 0 ENBL_1 DMA channel is enabled 0x1 CAN0 CAN CAN 0x40024000 0 0xC0C registers MCR Module Configuration register 0 32 read-write 0xD890000F 0xFFFFFFFF MAXMB Number Of The Last Message Buffer 0 7 read-write IDAM ID Acceptance Mode 8 2 read-write one_full_ID Format A: One full ID (standard and extended) per ID filter table element. 0 two_full_ID Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. 0x1 four_partial_ID Format C: Four partial 8-bit standard IDs per ID filter table element. 0x2 all_frames_rejected Format D: All frames rejected. 0x3 FDEN CAN FD operation enable 11 1 read-write CAN_FD_disabled CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format. 0 CAN_FD_enabled CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. 0x1 AEN Abort Enable 12 1 read-write abort_disabled Abort disabled. 0 abort_enabled Abort enabled. 0x1 LPRIOEN Local Priority Enable 13 1 read-write local_priority_disabled Local Priority disabled. 0 local_priority_enabled Local Priority enabled. 0x1 PNET_EN Pretended Networking Enable 14 1 read-write PN_disabled Pretended Networking mode is disabled. 0 PN_enabled Pretended Networking mode is enabled. 0x1 DMA DMA Enable 15 1 read-write id2 DMA feature for RX FIFO disabled. 0 id4 DMA feature for RX FIFO enabled. 0x1 IRMQ Individual Rx Masking And Queue Enable 16 1 read-write individual_rx_masking_disabled Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. 0 individual_rx_masking_enabled Individual Rx masking and queue feature are enabled. 0x1 SRXDIS Self Reception Disable 17 1 read-write self_reception_enabled Self-reception enabled. 0 self_reception_disabled Self-reception disabled. 0x1 LPMACK Low-Power Mode Acknowledge 20 1 read-only low_power_no FlexCAN is not in a low-power mode. 0 low_power_yes FlexCAN is in a low-power mode. 0x1 WRNEN Warning Interrupt Enable 21 1 read-write TWRNINT_RWRNINT_inactive TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. 0 TWRNINT_RWRNINT_active TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. 0x1 SUPV Supervisor Mode 23 1 read-write id2 FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. 0 id4 FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. 0x1 FRZACK Freeze Mode Acknowledge 24 1 read-only freeze_mode_no FlexCAN not in Freeze mode, prescaler running. 0 freeze_mode_yes FlexCAN in Freeze mode, prescaler stopped. 0x1 SOFTRST Soft Reset 25 1 read-write SOFTRST_no_reset_request No reset request. 0 SOFTRST_reset_registers Resets the registers affected by soft reset. 0x1 NOTRDY FlexCAN Not Ready 27 1 read-only id1 FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode. 0 id4 FlexCAN module is either in Disable mode, Stop mode, or Freeze mode. 0x1 HALT Halt FlexCAN 28 1 read-write HALT_disable No Freeze mode request. 0 HALT_enable Enters Freeze mode if the FRZ bit is asserted. 0x1 RFEN Rx FIFO Enable 29 1 read-write id2 Rx FIFO not enabled. 0 id4 Rx FIFO enabled. 0x1 FRZ Freeze Enable 30 1 read-write freeze_mode_disabled Not enabled to enter Freeze mode. 0 freeze_mode_enabled Enabled to enter Freeze mode. 0x1 MDIS Module Disable 31 1 read-write flexcan_enabled Enable the FlexCAN module. 0 flexcan_disabled Disable the FlexCAN module. 0x1 CTRL1 Control 1 register 0x4 32 read-write 0 0xFFFFFFFF PROPSEG Propagation Segment 0 3 read-write LOM Listen-Only Mode 3 1 read-write listen_only_mode_disabled Listen-Only mode is deactivated. 0 listen_only_mode_enabled FlexCAN module operates in Listen-Only mode. 0x1 LBUF Lowest Buffer Transmitted First 4 1 read-write highest_buffer_first Buffer with highest priority is transmitted first. 0 lowest_buffer_first Lowest number buffer is transmitted first. 0x1 TSYN Timer Sync 5 1 read-write timer_sync_disabled Timer sync feature disabled 0 timer_sync_enabled Timer sync feature enabled 0x1 BOFFREC Bus Off Recovery 6 1 read-write auto_recover_enabled Automatic recovering from Bus Off state enabled. 0 auto_recover_disabled Automatic recovering from Bus Off state disabled. 0x1 SMP CAN Bit Sampling 7 1 read-write one_sample Just one sample is used to determine the bit value. 0 three_sample Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples; a majority rule is used. 0x1 RWRNMSK Rx Warning Interrupt Mask 10 1 read-write rx_warning_int_disabled Rx Warning interrupt disabled. 0 rx_warning_int_enabled Rx Warning interrupt enabled. 0x1 TWRNMSK Tx Warning Interrupt Mask 11 1 read-write tx_warning_int_disabled Tx Warning interrupt disabled. 0 tx_warning_int_enabled Tx Warning interrupt enabled. 0x1 LPB Loop Back Mode 12 1 read-write loopback_disabled Loop Back disabled. 0 loopback_enabled Loop Back enabled. 0x1 CLKSRC CAN Engine Clock Source 13 1 read-write oscillator_clock The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. 0 peripheral_clock The CAN engine clock source is the peripheral clock. 0x1 ERRMSK Error Interrupt Mask 14 1 read-write error_int_disabled Error interrupt disabled. 0 error_int_enabled Error interrupt enabled. 0x1 BOFFMSK Bus Off Interrupt Mask 15 1 read-write bus_off_int_disabled Bus Off interrupt disabled. 0 bus_off_int_enabled Bus Off interrupt enabled. 0x1 PSEG2 Phase Segment 2 16 3 read-write PSEG1 Phase Segment 1 19 3 read-write RJW Resync Jump Width 22 2 read-write PRESDIV Prescaler Division Factor 24 8 read-write TIMER Free Running Timer 0x8 32 read-write 0 0xFFFFFFFF TIMER Timer Value 0 16 read-write RXMGMASK Rx Mailboxes Global Mask register 0x10 32 read-write 0 0 MG Rx Mailboxes Global Mask Bits 0 32 read-write RX14MASK Rx 14 Mask register 0x14 32 read-write 0 0 RX14M Rx Buffer 14 Mask Bits 0 32 read-write RX15MASK Rx 15 Mask register 0x18 32 read-write 0 0 RX15M Rx Buffer 15 Mask Bits 0 32 read-write ECR Error Counter 0x1C 32 read-write 0 0xFFFFFFFF TXERRCNT Transmit Error Counter 0 8 read-write RXERRCNT Receive Error Counter 8 8 read-write TXERRCNT_FAST Transmit Error Counter for fast bits 16 8 read-write RXERRCNT_FAST Receive Error Counter for fast bits 24 8 read-write ESR1 Error and Status 1 register 0x20 32 read-write 0 0xFFFFFFFF ERRINT Error Interrupt 1 1 read-write oneToClear DISABLE No such occurrence. 0 ENABLE Indicates setting of any error bit in the Error and Status register. 0x1 BOFFINT Bus Off Interrupt 2 1 read-write oneToClear DISABLE No such occurrence. 0 ENABLE FlexCAN module entered Bus Off state. 0x1 RX FlexCAN In Reception 3 1 read-only DISABLE FlexCAN is not receiving a message. 0 ENABLE FlexCAN is receiving a message. 0x1 FLTCONF Fault Confinement State 4 2 read-only error_active Error Active 0 error_passive Error Passive 0x1 bus_off Bus Off #1x TX FlexCAN In Transmission 6 1 read-only transmit_message_no FlexCAN is not transmitting a message. 0 transmit_message_yes FlexCAN is transmitting a message. 0x1 IDLE IDLE 7 1 read-only can_bus_not_idle No such occurrence. 0 can_bus_idle CAN bus is now IDLE. 0x1 RXWRN Rx Error Warning 8 1 read-only RXERRCNT_LT_96 No such occurrence. 0 RXERRCNT_GTE_96 RXERRCNT is greater than or equal to 96. 0x1 TXWRN TX Error Warning 9 1 read-only TXERRCNT_LT_96 No such occurrence. 0 TXERRCNT_GTE_96 TXERRCNT is greater than or equal to 96. 0x1 STFERR Stuffing Error 10 1 read-only stuffing_error_no No such occurrence. 0 stuffing_error_yes A stuffing error occurred since last read of this register. 0x1 FRMERR Form Error 11 1 read-only form_error_no No such occurrence. 0 form_error_yes A Form Error occurred since last read of this register. 0x1 CRCERR Cyclic Redundancy Check Error 12 1 read-only CRC_error_no No such occurrence. 0 CRC_error_yes A CRC error occurred since last read of this register. 0x1 ACKERR Acknowledge Error 13 1 read-only ACK_error_no No such occurrence. 0 ACK_error_yes An ACK error occurred since last read of this register. 0x1 BIT0ERR Bit0 Error 14 1 read-only bit0_error_no No such occurrence. 0 bit0_error_yes At least one bit sent as dominant is received as recessive. 0x1 BIT1ERR Bit1 Error 15 1 read-only bit1_error_no No such occurrence. 0 bit1_error_yes At least one bit sent as recessive is received as dominant. 0x1 RWRNINT Rx Warning Interrupt Flag 16 1 read-write oneToClear Rx_warning_int_no No such occurrence. 0 Rx_warning_int_yes The Rx error counter transitioned from less than 96 to greater than or equal to 96. 0x1 TWRNINT Tx Warning Interrupt Flag 17 1 read-write oneToClear Tx_warning_int_no No such occurrence. 0 Tx_warning_int_yes The Tx error counter transitioned from less than 96 to greater than or equal to 96. 0x1 SYNCH CAN Synchronization Status 18 1 read-only CAN_bus_sync_no FlexCAN is not synchronized to the CAN bus. 0 CAN_bus_sync_yes FlexCAN is synchronized to the CAN bus. 0x1 BOFFDONEINT Bus Off Done Interrupt 19 1 read-write oneToClear bus_off_not_done No such occurrence. 0 bus_off_done FlexCAN module has completed Bus Off process. 0x1 ERRINT_FAST Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set 20 1 read-write oneToClear errors_data_phase_no No such occurrence. 0 errors_data_phase_yes Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set. 0x1 ERROVR Error Overrun 21 1 read-write oneToClear overrun_not_occurred Overrun has not occurred. 0 overrun_occurred Overrun has occurred. 0x1 STFERR_FAST Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set 26 1 read-only stuffing_error_no No such occurrence. 0 stuffing_error_yes A stuffing error occurred since last read of this register. 0x1 FRMERR_FAST Form Error in the Data Phase of CAN FD frames with the BRS bit set 27 1 read-only form_error_no No such occurrence. 0 form_error_yes A form error occurred since last read of this register. 0x1 CRCERR_FAST Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set 28 1 read-only CRC_error_no No such occurrence. 0 CRC_error_yes A CRC error occurred since last read of this register. 0x1 BIT0ERR_FAST Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set 30 1 read-only bit0_error_no No such occurrence. 0 bit0_error_yes At least one bit sent as dominant is received as recessive. 0x1 BIT1ERR_FAST Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set 31 1 read-only bit1_error_no No such occurrence. 0 bit1_error_yes At least one bit sent as recessive is received as dominant. 0x1 IMASK2 Interrupt Masks 2 register 0x24 32 read-write 0 0xFFFFFFFF BUF63TO32M Buffer MB i Mask 0 32 read-write IMASK1 Interrupt Masks 1 register 0x28 32 read-write 0 0xFFFFFFFF BUF31TO0M Buffer MB i Mask 0 32 read-write IFLAG2 Interrupt Flags 2 register 0x2C 32 read-write 0 0xFFFFFFFF BUF63TO32I Buffer MB i Interrupt 0 32 read-write oneToClear IFLAG1 Interrupt Flags 1 register 0x30 32 read-write 0 0xFFFFFFFF BUF0I Buffer MB0 Interrupt Or Clear FIFO bit 0 1 read-write oneToClear buffer_Tx_Rx_not_complete The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0 buffer_Tx_Rx_complete The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. 0x1 BUF4TO1I Buffer MB i Interrupt Or Reserved 1 4 read-write oneToClear BUF5I Buffer MB5 Interrupt Or Frames available in Rx FIFO 5 1 read-write oneToClear id2 No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0 id4 MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. 0x1 BUF6I Buffer MB6 Interrupt Or Rx FIFO Warning 6 1 read-write oneToClear id2 No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 0 id4 MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 0x1 BUF7I Buffer MB7 Interrupt Or Rx FIFO Overflow 7 1 read-write oneToClear id2 No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 0 id4 MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 0x1 BUF31TO8I Buffer MBi Interrupt 8 24 read-write oneToClear CTRL2 Control 2 register 0x34 32 read-write 0x800000 0xFFFFFFFF EDFLTDIS Edge Filter Disable 11 1 read-write ENABLE Edge filter is enabled 0 DISABLE Edge filter is disabled 0x1 ISOCANFDEN ISO CAN FD Enable 12 1 read-write non_ISO FlexCAN operates using the non-ISO CAN FD protocol. 0 ISO FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1). 0x1 PREXCEN Protocol Exception Enable 14 1 read-write DISABLE Protocol exception is disabled. 0 ENABLE Protocol exception is enabled. 0x1 TIMER_SRC Timer Source 15 1 read-write CAN_bit_clock The free running timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus. 0 external_clock The free running timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus, or a different value as required. See the device-specific section for details about the external time tick. 0x1 EACEN Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 16 1 read-write RTR_compare_no Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. 0 RTR_compare_yes Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. 0x1 RRS Remote Request Storing 17 1 read-write remote_response_frame_not_generated Remote response frame is generated. 0 remote_response_frame_generated Remote request frame is stored. 0x1 MRP Mailboxes Reception Priority 18 1 read-write id2 Matching starts from Rx FIFO or Enhanced Rx FIFO and continues on mailboxes. 0 id4 Matching starts from mailboxes and continues on Rx FIFO. 0x1 TASD Tx Arbitration Start Delay 19 5 read-write RFFN Number Of Rx FIFO Filters 24 4 read-write BOFFDONEMSK Bus Off Done Interrupt Mask 30 1 read-write DISABLE Bus off done interrupt disabled. 0 ENABLE Bus off done interrupt enabled. 0x1 ERRMSK_FAST Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames 31 1 read-write DISABLE ERRINT_FAST error interrupt disabled. 0 ENABLE ERRINT_FAST error interrupt enabled. 0x1 ESR2 Error and Status 2 register 0x38 32 read-only 0 0xFFFFFFFF IMB Inactive Mailbox 13 1 read-only inactive_mailbox_no If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox. 0 inactive_mailbox_yes If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one. 0x1 VPS Valid Priority Status 14 1 read-only invalid Contents of IMB and LPTM are invalid. 0 valid Contents of IMB and LPTM are valid. 0x1 LPTM Lowest Priority Tx Mailbox 16 7 read-only CRCR CRC register 0x44 32 read-only 0 0xFFFFFFFF TXCRC Transmitted CRC value 0 15 read-only MBCRC CRC Mailbox 16 7 read-only RXFGMASK Rx FIFO Global Mask register 0x48 32 read-write 0 0 FGM Rx FIFO Global Mask Bits 0 32 read-write RXFIR Rx FIFO Information register 0x4C 32 read-only 0 0 IDHIT Identifier Acceptance Filter Hit Indicator 0 9 read-only CBT CAN Bit Timing register 0x50 32 read-write 0 0xFFFFFFFF EPSEG2 Extended Phase Segment 2 0 5 read-write EPSEG1 Extended Phase Segment 1 5 5 read-write EPROPSEG Extended Propagation Segment 10 6 read-write ERJW Extended Resync Jump Width 16 5 read-write EPRESDIV Extended Prescaler Division Factor 21 10 read-write BTF Bit Timing Format Enable 31 1 read-write DISABLE Extended bit time definitions disabled. 0 ENABLE Extended bit time definitions enabled. 0x1 256 0x4 RAMn[%s] Embedded RAM 0x80 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write 64 0x4 RXIMR[%s] Rx Individual Mask registers 0x880 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write CTRL1_PN Pretended Networking Control 1 register 0xB00 32 read-write 0x100 0xFFFFFFFF FCS Filtering Combination Selection 0 2 read-write ID_filtering Message ID filtering only 0 ID_payload_filtering Message ID filtering and payload filtering 0x1 ID_filtering_number Message ID filtering occurring a specified number of times 0x2 ID_payload_filtering_number Message ID filtering and payload filtering a specified number of times 0x3 IDFS ID Filtering Selection 2 2 read-write match_exact Match upon ID contents against an exact target value 0 match_GTE Match upon an ID value greater than or equal to a specified target value 0x1 match_LTE Match upon an ID value smaller than or equal to a specified target value 0x2 match_range Match upon an ID value inside a range, greater than or equal to a specified lower limit, and smaller than or equal to a specified upper limit 0x3 PLFS Payload Filtering Selection 4 2 read-write match_exact Match upon a payload contents against an exact target value 0 match_GTE Match upon a payload value greater than or equal to a specified target value 0x1 match_LTE Match upon a payload value smaller than or equal to a specified target value 0x2 match_range Match upon a payload value inside a range, greater than or equal to a specified lower limit, and smaller than or equal to a specified upper limit 0x3 NMATCH Number of Messages Matching the Same Filtering Criteria 8 8 read-write match_1 Received message must match the predefined filtering criteria for ID and/or PL once before generating a wakeup event. 0x1 match_2 Received message must match the predefined filtering criteria for ID and/or PL twice before generating a wakeup event. 0x2 match_255 Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wakeup event. 0xFF WUMF_MSK Wake Up by Match Flag Mask Bit 16 1 read-write DISABLE Wakeup match event is disabled 0 ENABLE Wakeup match event is enabled 0x1 WTOF_MSK Wake Up by Timeout Flag Mask Bit 17 1 read-write DISABLE Timeout wakeup event is disabled 0 ENABLE Timeout wakeup event is enabled 0x1 CTRL2_PN Pretended Networking Control 2 register 0xB04 32 read-write 0 0xFFFFFFFF MATCHTO Timeout for No Message Matching the Filtering Criteria 0 16 read-write WU_MTC Pretended Networking Wake Up Match register 0xB08 32 read-write 0 0xFFFFFFFF MCOUNTER Number of Matches when in Pretended Networking 8 8 read-only WUMF Wake Up by Match Flag Bit 16 1 read-write oneToClear no_match No wakeup by match event detected 0 match Wakeup by match event detected 0x1 WTOF Wake Up by Timeout Flag Bit 17 1 read-write oneToClear no_wakeup No wakeup by timeout event detected 0 wakeup Wakeup by timeout event detected 0x1 FLT_ID1 Pretended Networking ID Filter 1 register 0xB0C 32 read-write 0 0xFFFFFFFF FLT_ID1 ID Filter 1 for Pretended Networking filtering 0 29 read-write FLT_RTR Remote Transmission Request Filter 29 1 read-write reject Reject remote frame (accept data frame) 0 accept Accept remote frame 0x1 FLT_IDE ID Extended Filter 30 1 read-write standard Accept standard frame format 0 extended Accept extended frame format 0x1 FLT_DLC Pretended Networking DLC Filter register 0xB10 32 read-write 0x8 0xFFFFFFFF FLT_DLC_HI Upper Limit for Length of Data Bytes Filter 0 4 read-write FLT_DLC_LO Lower Limit for Length of Data Bytes Filter 16 4 read-write PL1_LO Pretended Networking Payload Low Filter 1 register 0xB14 32 read-write 0 0xFFFFFFFF Data_byte_3 Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 3. 0 8 read-write Data_byte_2 Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 2. 8 8 read-write Data_byte_1 Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 1. 16 8 read-write Data_byte_0 Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 0. 24 8 read-write PL1_HI Pretended Networking Payload High Filter 1 register 0xB18 32 read-write 0 0xFFFFFFFF Data_byte_7 Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 7. 0 8 read-write Data_byte_6 Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 6. 8 8 read-write Data_byte_5 Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 5. 16 8 read-write Data_byte_4 Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 4. 24 8 read-write FLT_ID2_IDMASK Pretended Networking ID Filter 2 Register / ID Mask register 0xB1C 32 read-write 0 0xFFFFFFFF FLT_ID2_IDMASK ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering 0 29 read-write RTR_MSK Remote Transmission Request Mask Bit 29 1 read-write frame_type_no The corresponding bit in the filter is "don't care" 0 frame_type_yes The corresponding bit in the filter is checked 0x1 IDE_MSK ID Extended Mask Bit 30 1 read-write frame_format_no The corresponding bit in the filter is "don't care" 0 frame_format_yes The corresponding bit in the filter is checked 0x1 PL2_PLMASK_LO Pretended Networking Payload Low Filter 2 Register / Payload Low Mask register 0xB20 32 read-write 0 0xFFFFFFFF Data_byte_3 Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 3. 0 8 read-write Data_byte_2 Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 2. 8 8 read-write Data_byte_1 Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 1. 16 8 read-write Data_byte_0 Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 0. 24 8 read-write PL2_PLMASK_HI Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register 0xB24 32 read-write 0 0xFFFFFFFF Data_byte_7 Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 7. 0 8 read-write Data_byte_6 Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 6. 8 8 read-write Data_byte_5 Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 5. 16 8 read-write Data_byte_4 Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 4. 24 8 read-write 4 0x10 WMB[%s] no description available 0xB40 WMBn_CS Wake Up Message Buffer register for C/S 0 32 read-only 0 0xFFFFFFFF DLC Length of Data in Bytes 16 4 read-only RTR Remote Transmission Request Bit 20 1 read-only not_remote Frame is data one (not remote) 0 remote Frame is a remote one 0x1 IDE ID Extended Bit 21 1 read-only standard Frame format is standard 0 extended Frame format is extended 0x1 SRR Substitute Remote Request 22 1 read-only WMBn_ID Wake Up Message Buffer Register for ID 0x4 32 read-only 0 0xFFFFFFFF ID Received ID under Pretended Networking mode 0 29 read-only WMBn_D03 Wake Up Message Buffer Register for Data 0-3 0x8 32 read-only 0 0xFFFFFFFF Data_byte_3 Received payload corresponding to the data byte 3 under Pretended Networking mode 0 8 read-only Data_byte_2 Received payload corresponding to the data byte 2 under Pretended Networking mode 8 8 read-only Data_byte_1 Received payload corresponding to the data byte 1 under Pretended Networking mode 16 8 read-only Data_byte_0 Received payload corresponding to the data byte 0 under Pretended Networking mode 24 8 read-only WMBn_D47 Wake Up Message Buffer Register Data 4-7 0xC 32 read-only 0 0xFFFFFFFF Data_byte_7 Received payload corresponding to the data byte 7 under Pretended Networking mode 0 8 read-only Data_byte_6 Received payload corresponding to the data byte 6 under Pretended Networking mode 8 8 read-only Data_byte_5 Received payload corresponding to the data byte 5 under Pretended Networking mode 16 8 read-only Data_byte_4 Received payload corresponding to the data byte 4 under Pretended Networking mode 24 8 read-only FDCTRL CAN FD Control register 0xC00 32 read-write 0x80000100 0xFFFFFFFF TDCVAL Transceiver Delay Compensation Value 0 6 read-only TDCOFF Transceiver Delay Compensation Offset 8 5 read-write TDCFAIL Transceiver Delay Compensation Fail 14 1 read-write oneToClear in_range Measured loop delay is in range. 0 out_of_range Measured loop delay is out of range. 0x1 TDCEN Transceiver Delay Compensation Enable 15 1 read-write DISABLE TDC is disabled 0 ENABLE TDC is enabled 0x1 MBDSR0 Message Buffer Data Size for Region 0 16 2 read-write R0_8_bytes Selects 8 bytes per message buffer. 0 R0_16_bytes Selects 16 bytes per message buffer. 0x1 R0_32_bytes Selects 32 bytes per message buffer. 0x2 R0_64_bytes Selects 64 bytes per message buffer. 0x3 MBDSR1 Message Buffer Data Size for Region 1 19 2 read-write R1_8_bytes Selects 8 bytes per message buffer. 0 R1_16_bytes Selects 16 bytes per message buffer. 0x1 R1_32_bytes Selects 32 bytes per message buffer. 0x2 R1_64_bytes Selects 64 bytes per message buffer. 0x3 FDRATE Bit Rate Switch Enable 31 1 read-write nominal Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. 0 bit_rate_switching Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. 0x1 FDCBT CAN FD Bit Timing register 0xC04 32 read-write 0 0xFFFFFFFF FPSEG2 Fast Phase Segment 2 0 3 read-write FPSEG1 Fast Phase Segment 1 5 3 read-write FPROPSEG Fast Propagation Segment 10 5 read-write FRJW Fast Resync Jump Width 16 3 read-write FPRESDIV Fast Prescaler Division Factor 20 10 read-write FDCRC CAN FD CRC register 0xC08 32 read-only 0 0xFFFFFFFF FD_TXCRC Extended Transmitted CRC value 0 21 read-only FD_MBCRC CRC Mailbox Number for FD_TXCRC 24 7 read-only CAN1 CAN CAN 0x40025000 0 0xC0C registers MCR Module Configuration register 0 32 read-write 0xD890000F 0xFFFFFFFF MAXMB Number Of The Last Message Buffer 0 7 read-write IDAM ID Acceptance Mode 8 2 read-write one_full_ID Format A: One full ID (standard and extended) per ID filter table element. 0 two_full_ID Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. 0x1 four_partial_ID Format C: Four partial 8-bit standard IDs per ID filter table element. 0x2 all_frames_rejected Format D: All frames rejected. 0x3 FDEN CAN FD operation enable 11 1 read-write CAN_FD_disabled CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format. 0 CAN_FD_enabled CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. 0x1 AEN Abort Enable 12 1 read-write abort_disabled Abort disabled. 0 abort_enabled Abort enabled. 0x1 LPRIOEN Local Priority Enable 13 1 read-write local_priority_disabled Local Priority disabled. 0 local_priority_enabled Local Priority enabled. 0x1 DMA DMA Enable 15 1 read-write id2 DMA feature for RX FIFO disabled. 0 id4 DMA feature for RX FIFO enabled. 0x1 IRMQ Individual Rx Masking And Queue Enable 16 1 read-write individual_rx_masking_disabled Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. 0 individual_rx_masking_enabled Individual Rx masking and queue feature are enabled. 0x1 SRXDIS Self Reception Disable 17 1 read-write self_reception_enabled Self-reception enabled. 0 self_reception_disabled Self-reception disabled. 0x1 LPMACK Low-Power Mode Acknowledge 20 1 read-only low_power_no FlexCAN is not in a low-power mode. 0 low_power_yes FlexCAN is in a low-power mode. 0x1 WRNEN Warning Interrupt Enable 21 1 read-write TWRNINT_RWRNINT_inactive TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. 0 TWRNINT_RWRNINT_active TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. 0x1 SUPV Supervisor Mode 23 1 read-write id2 FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. 0 id4 FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. 0x1 FRZACK Freeze Mode Acknowledge 24 1 read-only freeze_mode_no FlexCAN not in Freeze mode, prescaler running. 0 freeze_mode_yes FlexCAN in Freeze mode, prescaler stopped. 0x1 SOFTRST Soft Reset 25 1 read-write SOFTRST_no_reset_request No reset request. 0 SOFTRST_reset_registers Resets the registers affected by soft reset. 0x1 NOTRDY FlexCAN Not Ready 27 1 read-only id1 FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode. 0 id4 FlexCAN module is either in Disable mode, Stop mode, or Freeze mode. 0x1 HALT Halt FlexCAN 28 1 read-write HALT_disable No Freeze mode request. 0 HALT_enable Enters Freeze mode if the FRZ bit is asserted. 0x1 RFEN Rx FIFO Enable 29 1 read-write id2 Rx FIFO not enabled. 0 id4 Rx FIFO enabled. 0x1 FRZ Freeze Enable 30 1 read-write freeze_mode_disabled Not enabled to enter Freeze mode. 0 freeze_mode_enabled Enabled to enter Freeze mode. 0x1 MDIS Module Disable 31 1 read-write flexcan_enabled Enable the FlexCAN module. 0 flexcan_disabled Disable the FlexCAN module. 0x1 CTRL1 Control 1 register 0x4 32 read-write 0 0xFFFFFFFF PROPSEG Propagation Segment 0 3 read-write LOM Listen-Only Mode 3 1 read-write listen_only_mode_disabled Listen-Only mode is deactivated. 0 listen_only_mode_enabled FlexCAN module operates in Listen-Only mode. 0x1 LBUF Lowest Buffer Transmitted First 4 1 read-write highest_buffer_first Buffer with highest priority is transmitted first. 0 lowest_buffer_first Lowest number buffer is transmitted first. 0x1 TSYN Timer Sync 5 1 read-write timer_sync_disabled Timer sync feature disabled 0 timer_sync_enabled Timer sync feature enabled 0x1 BOFFREC Bus Off Recovery 6 1 read-write auto_recover_enabled Automatic recovering from Bus Off state enabled. 0 auto_recover_disabled Automatic recovering from Bus Off state disabled. 0x1 SMP CAN Bit Sampling 7 1 read-write one_sample Just one sample is used to determine the bit value. 0 three_sample Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples; a majority rule is used. 0x1 RWRNMSK Rx Warning Interrupt Mask 10 1 read-write rx_warning_int_disabled Rx Warning interrupt disabled. 0 rx_warning_int_enabled Rx Warning interrupt enabled. 0x1 TWRNMSK Tx Warning Interrupt Mask 11 1 read-write tx_warning_int_disabled Tx Warning interrupt disabled. 0 tx_warning_int_enabled Tx Warning interrupt enabled. 0x1 LPB Loop Back Mode 12 1 read-write loopback_disabled Loop Back disabled. 0 loopback_enabled Loop Back enabled. 0x1 CLKSRC CAN Engine Clock Source 13 1 read-write oscillator_clock The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. 0 peripheral_clock The CAN engine clock source is the peripheral clock. 0x1 ERRMSK Error Interrupt Mask 14 1 read-write error_int_disabled Error interrupt disabled. 0 error_int_enabled Error interrupt enabled. 0x1 BOFFMSK Bus Off Interrupt Mask 15 1 read-write bus_off_int_disabled Bus Off interrupt disabled. 0 bus_off_int_enabled Bus Off interrupt enabled. 0x1 PSEG2 Phase Segment 2 16 3 read-write PSEG1 Phase Segment 1 19 3 read-write RJW Resync Jump Width 22 2 read-write PRESDIV Prescaler Division Factor 24 8 read-write TIMER Free Running Timer 0x8 32 read-write 0 0xFFFFFFFF TIMER Timer Value 0 16 read-write RXMGMASK Rx Mailboxes Global Mask register 0x10 32 read-write 0 0 MG Rx Mailboxes Global Mask Bits 0 32 read-write RX14MASK Rx 14 Mask register 0x14 32 read-write 0 0 RX14M Rx Buffer 14 Mask Bits 0 32 read-write RX15MASK Rx 15 Mask register 0x18 32 read-write 0 0 RX15M Rx Buffer 15 Mask Bits 0 32 read-write ECR Error Counter 0x1C 32 read-write 0 0xFFFFFFFF TXERRCNT Transmit Error Counter 0 8 read-write RXERRCNT Receive Error Counter 8 8 read-write TXERRCNT_FAST Transmit Error Counter for fast bits 16 8 read-write RXERRCNT_FAST Receive Error Counter for fast bits 24 8 read-write ESR1 Error and Status 1 register 0x20 32 read-write 0 0xFFFFFFFF ERRINT Error Interrupt 1 1 read-write oneToClear DISABLE No such occurrence. 0 ENABLE Indicates setting of any error bit in the Error and Status register. 0x1 BOFFINT Bus Off Interrupt 2 1 read-write oneToClear DISABLE No such occurrence. 0 ENABLE FlexCAN module entered Bus Off state. 0x1 RX FlexCAN In Reception 3 1 read-only DISABLE FlexCAN is not receiving a message. 0 ENABLE FlexCAN is receiving a message. 0x1 FLTCONF Fault Confinement State 4 2 read-only error_active Error Active 0 error_passive Error Passive 0x1 bus_off Bus Off #1x TX FlexCAN In Transmission 6 1 read-only transmit_message_no FlexCAN is not transmitting a message. 0 transmit_message_yes FlexCAN is transmitting a message. 0x1 IDLE IDLE 7 1 read-only can_bus_not_idle No such occurrence. 0 can_bus_idle CAN bus is now IDLE. 0x1 RXWRN Rx Error Warning 8 1 read-only RXERRCNT_LT_96 No such occurrence. 0 RXERRCNT_GTE_96 RXERRCNT is greater than or equal to 96. 0x1 TXWRN TX Error Warning 9 1 read-only TXERRCNT_LT_96 No such occurrence. 0 TXERRCNT_GTE_96 TXERRCNT is greater than or equal to 96. 0x1 STFERR Stuffing Error 10 1 read-only stuffing_error_no No such occurrence. 0 stuffing_error_yes A stuffing error occurred since last read of this register. 0x1 FRMERR Form Error 11 1 read-only form_error_no No such occurrence. 0 form_error_yes A Form Error occurred since last read of this register. 0x1 CRCERR Cyclic Redundancy Check Error 12 1 read-only CRC_error_no No such occurrence. 0 CRC_error_yes A CRC error occurred since last read of this register. 0x1 ACKERR Acknowledge Error 13 1 read-only ACK_error_no No such occurrence. 0 ACK_error_yes An ACK error occurred since last read of this register. 0x1 BIT0ERR Bit0 Error 14 1 read-only bit0_error_no No such occurrence. 0 bit0_error_yes At least one bit sent as dominant is received as recessive. 0x1 BIT1ERR Bit1 Error 15 1 read-only bit1_error_no No such occurrence. 0 bit1_error_yes At least one bit sent as recessive is received as dominant. 0x1 RWRNINT Rx Warning Interrupt Flag 16 1 read-write oneToClear Rx_warning_int_no No such occurrence. 0 Rx_warning_int_yes The Rx error counter transitioned from less than 96 to greater than or equal to 96. 0x1 TWRNINT Tx Warning Interrupt Flag 17 1 read-write oneToClear Tx_warning_int_no No such occurrence. 0 Tx_warning_int_yes The Tx error counter transitioned from less than 96 to greater than or equal to 96. 0x1 SYNCH CAN Synchronization Status 18 1 read-only CAN_bus_sync_no FlexCAN is not synchronized to the CAN bus. 0 CAN_bus_sync_yes FlexCAN is synchronized to the CAN bus. 0x1 BOFFDONEINT Bus Off Done Interrupt 19 1 read-write oneToClear bus_off_not_done No such occurrence. 0 bus_off_done FlexCAN module has completed Bus Off process. 0x1 ERRINT_FAST Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set 20 1 read-write oneToClear errors_data_phase_no No such occurrence. 0 errors_data_phase_yes Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set. 0x1 ERROVR Error Overrun 21 1 read-write oneToClear overrun_not_occurred Overrun has not occurred. 0 overrun_occurred Overrun has occurred. 0x1 STFERR_FAST Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set 26 1 read-only stuffing_error_no No such occurrence. 0 stuffing_error_yes A stuffing error occurred since last read of this register. 0x1 FRMERR_FAST Form Error in the Data Phase of CAN FD frames with the BRS bit set 27 1 read-only form_error_no No such occurrence. 0 form_error_yes A form error occurred since last read of this register. 0x1 CRCERR_FAST Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set 28 1 read-only CRC_error_no No such occurrence. 0 CRC_error_yes A CRC error occurred since last read of this register. 0x1 BIT0ERR_FAST Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set 30 1 read-only bit0_error_no No such occurrence. 0 bit0_error_yes At least one bit sent as dominant is received as recessive. 0x1 BIT1ERR_FAST Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set 31 1 read-only bit1_error_no No such occurrence. 0 bit1_error_yes At least one bit sent as recessive is received as dominant. 0x1 IMASK2 Interrupt Masks 2 register 0x24 32 read-write 0 0xFFFFFFFF BUF63TO32M Buffer MB i Mask 0 32 read-write IMASK1 Interrupt Masks 1 register 0x28 32 read-write 0 0xFFFFFFFF BUF31TO0M Buffer MB i Mask 0 32 read-write IFLAG2 Interrupt Flags 2 register 0x2C 32 read-write 0 0xFFFFFFFF BUF63TO32I Buffer MB i Interrupt 0 32 read-write oneToClear IFLAG1 Interrupt Flags 1 register 0x30 32 read-write 0 0xFFFFFFFF BUF0I Buffer MB0 Interrupt Or Clear FIFO bit 0 1 read-write oneToClear buffer_Tx_Rx_not_complete The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0 buffer_Tx_Rx_complete The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. 0x1 BUF4TO1I Buffer MB i Interrupt Or Reserved 1 4 read-write oneToClear BUF5I Buffer MB5 Interrupt Or Frames available in Rx FIFO 5 1 read-write oneToClear id2 No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0 id4 MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. 0x1 BUF6I Buffer MB6 Interrupt Or Rx FIFO Warning 6 1 read-write oneToClear id2 No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 0 id4 MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 0x1 BUF7I Buffer MB7 Interrupt Or Rx FIFO Overflow 7 1 read-write oneToClear id2 No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 0 id4 MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 0x1 BUF31TO8I Buffer MBi Interrupt 8 24 read-write oneToClear CTRL2 Control 2 register 0x34 32 read-write 0x800000 0xFFFFFFFF EDFLTDIS Edge Filter Disable 11 1 read-write ENABLE Edge filter is enabled 0 DISABLE Edge filter is disabled 0x1 ISOCANFDEN ISO CAN FD Enable 12 1 read-write non_ISO FlexCAN operates using the non-ISO CAN FD protocol. 0 ISO FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1). 0x1 PREXCEN Protocol Exception Enable 14 1 read-write DISABLE Protocol exception is disabled. 0 ENABLE Protocol exception is enabled. 0x1 EACEN Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 16 1 read-write RTR_compare_no Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. 0 RTR_compare_yes Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. 0x1 RRS Remote Request Storing 17 1 read-write remote_response_frame_not_generated Remote response frame is generated. 0 remote_response_frame_generated Remote request frame is stored. 0x1 MRP Mailboxes Reception Priority 18 1 read-write id2 Matching starts from Rx FIFO or Enhanced Rx FIFO and continues on mailboxes. 0 id4 Matching starts from mailboxes and continues on Rx FIFO. 0x1 TASD Tx Arbitration Start Delay 19 5 read-write RFFN Number Of Rx FIFO Filters 24 4 read-write BOFFDONEMSK Bus Off Done Interrupt Mask 30 1 read-write DISABLE Bus off done interrupt disabled. 0 ENABLE Bus off done interrupt enabled. 0x1 ERRMSK_FAST Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames 31 1 read-write DISABLE ERRINT_FAST error interrupt disabled. 0 ENABLE ERRINT_FAST error interrupt enabled. 0x1 ESR2 Error and Status 2 register 0x38 32 read-only 0 0xFFFFFFFF IMB Inactive Mailbox 13 1 read-only inactive_mailbox_no If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox. 0 inactive_mailbox_yes If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one. 0x1 VPS Valid Priority Status 14 1 read-only invalid Contents of IMB and LPTM are invalid. 0 valid Contents of IMB and LPTM are valid. 0x1 LPTM Lowest Priority Tx Mailbox 16 7 read-only CRCR CRC register 0x44 32 read-only 0 0xFFFFFFFF TXCRC Transmitted CRC value 0 15 read-only MBCRC CRC Mailbox 16 7 read-only RXFGMASK Rx FIFO Global Mask register 0x48 32 read-write 0 0 FGM Rx FIFO Global Mask Bits 0 32 read-write RXFIR Rx FIFO Information register 0x4C 32 read-only 0 0 IDHIT Identifier Acceptance Filter Hit Indicator 0 9 read-only CBT CAN Bit Timing register 0x50 32 read-write 0 0xFFFFFFFF EPSEG2 Extended Phase Segment 2 0 5 read-write EPSEG1 Extended Phase Segment 1 5 5 read-write EPROPSEG Extended Propagation Segment 10 6 read-write ERJW Extended Resync Jump Width 16 5 read-write EPRESDIV Extended Prescaler Division Factor 21 10 read-write BTF Bit Timing Format Enable 31 1 read-write DISABLE Extended bit time definitions disabled. 0 ENABLE Extended bit time definitions enabled. 0x1 256 0x4 RAMn[%s] Embedded RAM 0x80 32 read-write 0 0xFFFFFFFF DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write 64 0x4 RXIMR[%s] Rx Individual Mask registers 0x880 32 read-write 0 0 MI Individual Mask Bits 0 32 read-write FDCTRL CAN FD Control register 0xC00 32 read-write 0x80000100 0xFFFFFFFF TDCVAL Transceiver Delay Compensation Value 0 6 read-only TDCOFF Transceiver Delay Compensation Offset 8 5 read-write TDCFAIL Transceiver Delay Compensation Fail 14 1 read-write oneToClear in_range Measured loop delay is in range. 0 out_of_range Measured loop delay is out of range. 0x1 TDCEN Transceiver Delay Compensation Enable 15 1 read-write DISABLE TDC is disabled 0 ENABLE TDC is enabled 0x1 MBDSR0 Message Buffer Data Size for Region 0 16 2 read-write R0_8_bytes Selects 8 bytes per message buffer. 0 R0_16_bytes Selects 16 bytes per message buffer. 0x1 R0_32_bytes Selects 32 bytes per message buffer. 0x2 R0_64_bytes Selects 64 bytes per message buffer. 0x3 MBDSR1 Message Buffer Data Size for Region 1 19 2 read-write R1_8_bytes Selects 8 bytes per message buffer. 0 R1_16_bytes Selects 16 bytes per message buffer. 0x1 R1_32_bytes Selects 32 bytes per message buffer. 0x2 R1_64_bytes Selects 64 bytes per message buffer. 0x3 FDRATE Bit Rate Switch Enable 31 1 read-write nominal Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. 0 bit_rate_switching Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. 0x1 FDCBT CAN FD Bit Timing register 0xC04 32 read-write 0 0xFFFFFFFF FPSEG2 Fast Phase Segment 2 0 3 read-write FPSEG1 Fast Phase Segment 1 5 3 read-write FPROPSEG Fast Propagation Segment 10 5 read-write FRJW Fast Resync Jump Width 16 3 read-write FPRESDIV Fast Prescaler Division Factor 20 10 read-write FDCRC CAN FD CRC register 0xC08 32 read-only 0 0xFFFFFFFF FD_TXCRC Extended Transmitted CRC value 0 21 read-only FD_MBCRC CRC Mailbox Number for FD_TXCRC 24 7 read-only LPSPI0 LPSPI LPSPI LPSPI 0x4002C000 0 0x78 registers VERID Version ID Register 0 32 read-only 0x1000004 0xFFFFFFFF FEATURE Module Identification Number 0 16 read-only STANDARD Standard feature set supporting a 32-bit shift register. 0x4 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x202 0xFFFFFFFF TXFIFO Transmit FIFO Size 0 8 read-only RXFIFO Receive FIFO Size 8 8 read-only CR Control Register 0x10 32 read-write 0 0xFFFFFFFF MEN Module Enable 0 1 read-write DISABLED Module is disabled 0 ENABLED Module is enabled 0x1 RST Software Reset 1 1 read-write NOT_RESET Module is not reset 0 RESET Module is reset 0x1 DOZEN Doze Mode Enable 2 1 read-write ENABLED LPSPI module is enabled in Doze mode 0 DISABLED LPSPI module is disabled in Doze mode 0x1 DBGEN Debug Enable 3 1 read-write DISABLED LPSPI module is disabled in debug mode 0 ENABLED LPSPI module is enabled in debug mode 0x1 RTF Reset Transmit FIFO 8 1 write-only NO_EFFECT No effect 0 TXFIFO_RST Transmit FIFO is reset 0x1 RRF Reset Receive FIFO 9 1 write-only NO_EFFECT No effect 0 RXFIFO_RST Receive FIFO is reset 0x1 SR Status Register 0x14 32 read-write 0x1 0xFFFFFFFF TDF Transmit Data Flag 0 1 read-only TXDATA_NOT_REQST Transmit data not requested 0 TXDATA_REQST Transmit data is requested 0x1 RDF Receive Data Flag 1 1 read-only NOTREADY Receive Data is not ready 0 READY Receive data is ready 0x1 WCF Word Complete Flag 8 1 read-write oneToClear NOT_COMPLETED Transfer of a received word has not yet completed 0 COMPLETED Transfer of a received word has completed 0x1 FCF Frame Complete Flag 9 1 read-write oneToClear NOT_COMPLETED Frame transfer has not completed 0 COMPLETED Frame transfer has completed 0x1 TCF Transfer Complete Flag 10 1 read-write oneToClear NOT_COMPLETED All transfers have not completed 0 COMPLETED All transfers have completed 0x1 TEF Transmit Error Flag 11 1 read-write oneToClear NO_UNDERRUN Transmit FIFO underrun has not occurred 0 UNDERRUN Transmit FIFO underrun has occurred 0x1 REF Receive Error Flag 12 1 read-write oneToClear NOT_OVERFLOWED Receive FIFO has not overflowed 0 OVERFLOWED Receive FIFO has overflowed 0x1 DMF Data Match Flag 13 1 read-write oneToClear NO_MATCH Have not received matching data 0 MATCH Have received matching data 0x1 MBF Module Busy Flag 24 1 read-only IDLE LPSPI is idle 0 BUSY LPSPI is busy 0x1 IER Interrupt Enable Register 0x18 32 read-write 0 0xFFFFFFFF TDIE Transmit Data Interrupt Enable 0 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 WCIE Word Complete Interrupt Enable 8 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 FCIE Frame Complete Interrupt Enable 9 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 TCIE Transfer Complete Interrupt Enable 10 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 TEIE Transmit Error Interrupt Enable 11 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 REIE Receive Error Interrupt Enable 12 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 DMIE Data Match Interrupt Enable 13 1 read-write DISABLED Disabled 0 ENABLED Enabled 0x1 DER DMA Enable Register 0x1C 32 read-write 0 0xFFFFFFFF TDDE Transmit Data DMA Enable 0 1 read-write DISABLED DMA request is disabled 0 ENABLED DMA request is enabled 0x1 RDDE Receive Data DMA Enable 1 1 read-write DISABLED DMA request is disabled 0 ENABLED DMA request is enabled 0x1 CFGR0 Configuration Register 0 0x20 32 read-write 0 0xFFFFFFFF HREN Host Request Enable 0 1 read-write DISABLED Host request is disabled 0 ENABLED Host request is enabled 0x1 HRPOL Host Request Polarity 1 1 read-write DISABLED LPSPI_HREQ pin is active low 0 ENABLED LPSPI_HREQ pin is active high 0x1 HRSEL Host Request Select 2 1 read-write HREQPIN Host request input is the LPSPI_HREQ pin 0 INPUT_TRIGGER Host request input is the input trigger 0x1 CIRFIFO Circular FIFO Enable 8 1 read-write DISABLED Circular FIFO is disabled 0 ENABLED Circular FIFO is enabled 0x1 RDMO Receive Data Match Only 9 1 read-write STORED Received data is stored in the receive FIFO as in normal operations 0 DISCARDED Received data is discarded unless the Data Match Flag (DMF) is set 0x1 CFGR1 Configuration Register 1 0x24 32 read-write 0 0xFFFFFFFF MASTER Master Mode 0 1 read-write SLAVE_MODE Slave mode 0 MASTER_MODE Master mode 0x1 SAMPLE Sample Point 1 1 read-write ON_SCK_EDGE Input data is sampled on SCK edge 0 ON_DELAYED_SCK_EDGE Input data is sampled on delayed SCK edge 0x1 AUTOPCS Automatic PCS 2 1 read-write DISABLED Automatic PCS generation is disabled 0 ENABLED Automatic PCS generation is enabled 0x1 NOSTALL No Stall 3 1 read-write DISABLED Transfers will stall when the transmit FIFO is empty 0 ENABLED Transfers will not stall, allowing transmit FIFO underruns to occur 0x1 PCSPOL Peripheral Chip Select Polarity 8 4 read-write MATCFG Match Configuration 16 3 read-write DISABLED Match is disabled 0 ENABLED_FIRSTDATAMATCH 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) 0x2 ENABLED_ANYDATAMATCH 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) 0x3 ENABLED_DATAMATCH_100 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] 0x4 ENABLED_DATAMATCH_101 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] 0x5 ENABLED_DATAMATCH_110 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] 0x6 ENABLED_DATAMATCH_111 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] 0x7 PINCFG Pin Configuration 24 2 read-write SIN_IN_SOUT_OUT SIN is used for input data and SOUT is used for output data 0 SIN_BOTH_IN_OUT SIN is used for both input and output data, only half-duplex serial transfers are supported 0x1 SOUT_BOTH_IN_OUT SOUT is used for both input and output data, only half-duplex serial transfers are supported 0x2 SOUT_IN_SIN_OUT SOUT is used for input data and SIN is used for output data 0x3 OUTCFG Output Configuration 26 1 read-write RETAIN_LASTVALUE Output data retains last value when chip select is negated 0 TRISTATED Output data is tristated when chip select is negated 0x1 PCSCFG Peripheral Chip Select Configuration 27 1 read-write CHIP_SELECT PCS[3:2] are configured for chip select function 0 HALFDUPLEX4BIT PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) 0x1 DMR0 Data Match Register 0 0x30 32 read-write 0 0xFFFFFFFF MATCH0 Match 0 Value 0 32 read-write DMR1 Data Match Register 1 0x34 32 read-write 0 0xFFFFFFFF MATCH1 Match 1 Value 0 32 read-write CCR Clock Configuration Register 0x40 32 read-write 0 0xFFFFFFFF SCKDIV SCK Divider 0 8 read-write DBT Delay Between Transfers 8 8 read-write PCSSCK PCS-to-SCK Delay 16 8 read-write SCKPCS SCK-to-PCS Delay 24 8 read-write FCR FIFO Control Register 0x58 32 read-write 0 0xFFFFFFFF TXWATER Transmit FIFO Watermark 0 2 read-write RXWATER Receive FIFO Watermark 16 2 read-write FSR FIFO Status Register 0x5C 32 read-only 0 0xFFFFFFFF TXCOUNT Transmit FIFO Count 0 3 read-only RXCOUNT Receive FIFO Count 16 3 read-only TCR Transmit Command Register 0x60 32 read-write 0x1F 0xFFFFFFFF FRAMESZ Frame Size 0 12 read-write WIDTH Transfer Width 16 2 read-write ONEBIT 1 bit transfer 0 TWOBIT 2 bit transfer 0x1 FOURBIT 4 bit transfer 0x2 TXMSK Transmit Data Mask 18 1 read-write NORMAL Normal transfer 0 MASK Mask transmit data 0x1 RXMSK Receive Data Mask 19 1 read-write NORMAL Normal transfer 0 MASK Receive data is masked 0x1 CONTC Continuing Command 20 1 read-write START Command word for start of new transfer 0 CONTINUE Command word for continuing transfer 0x1 CONT Continuous Transfer 21 1 read-write DISABLED Continuous transfer is disabled 0 ENABLED Continuous transfer is enabled 0x1 BYSW Byte Swap 22 1 read-write DISABLED Byte swap is disabled 0 ENABLED Byte swap is enabled 0x1 LSBF LSB First 23 1 read-write MSB_FIRST Data is transferred MSB first 0 LSB_FIRST Data is transferred LSB first 0x1 PCS Peripheral Chip Select 24 2 read-write TX_PCS0 Transfer using LPSPI_PCS[0] 0 TX_PCS1 Transfer using LPSPI_PCS[1] 0x1 TX_PCS2 Transfer using LPSPI_PCS[2] 0x2 TX_PCS3 Transfer using LPSPI_PCS[3] 0x3 PRESCALE Prescaler Value 27 3 read-write DIVIDEBY1 Divide by 1 0 DIVIDEBY2 Divide by 2 0x1 DIVIDEBY4 Divide by 4 0x2 DIVIDEBY8 Divide by 8 0x3 DIVIDEBY16 Divide by 16 0x4 DIVIDEBY32 Divide by 32 0x5 DIVIDEBY64 Divide by 64 0x6 DIVIDEBY128 Divide by 128 0x7 CPHA Clock Phase 30 1 read-write CAPTURED Data is captured on the leading edge of SCK and changed on the following edge of SCK 0 CHANGED Data is changed on the leading edge of SCK and captured on the following edge of SCK 0x1 CPOL Clock Polarity 31 1 read-write INACTIVE_LOW The inactive state value of SCK is low 0 INACTIVE_HIGH The inactive state value of SCK is high 0x1 TDR Transmit Data Register 0x64 32 write-only 0 0xFFFFFFFF DATA Transmit Data 0 32 write-only RSR Receive Status Register 0x70 32 read-only 0x2 0xFFFFFFFF SOF Start Of Frame 0 1 read-only NEXT_DATAWORD Subsequent data word received after LPSPI_PCS assertion 0 FIRST_DATAWORD First data word received after LPSPI_PCS assertion 0x1 RXEMPTY RX FIFO Empty 1 1 read-only NOT_EMPTY RX FIFO is not empty 0 EMPTY RX FIFO is empty 0x1 RDR Receive Data Register 0x74 32 read-only 0 0xFFFFFFFF DATA Receive Data 0 32 read-only LPSPI1 LPSPI LPSPI 0x4002D000 0 0x78 registers LPSPI2 LPSPI LPSPI 0x4002E000 0 0x78 registers CRC CRC CRC 0x40032000 0 0xC registers DATA CRC Data register 0 32 read-write 0xFFFFFFFF 0xFFFFFFFF LL CRC Low Lower Byte 0 8 read-write LU CRC Low Upper Byte 8 8 read-write HL CRC High Lower Byte 16 8 read-write HU CRC High Upper Byte 24 8 read-write GPOLY CRC Polynomial register 0x4 32 read-write 0x1021 0xFFFFFFFF LOW Low Polynominal Half-word 0 16 read-write HIGH High Polynominal Half-word 16 16 read-write CTRL CRC Control register 0x8 32 read-write 0 0xFFFFFFFF TCRC TCRC 24 1 read-write TCRC_0 16-bit CRC protocol. 0 TCRC_1 32-bit CRC protocol. 0x1 WAS Write CRC Data Register As Seed 25 1 read-write WAS_0 Writes to the CRC data register are data values. 0 WAS_1 Writes to the CRC data register are seed values. 0x1 FXOR Complement Read Of CRC Data Register 26 1 read-write FXOR_0 No XOR on reading. 0 FXOR_1 Invert or complement the read value of the CRC Data register. 0x1 TOTR Type Of Transpose For Read 28 2 read-write TOTR_0 No transposition. 0 TOTR_1 Bits in bytes are transposed; bytes are not transposed. 0x1 TOTR_2 Both bits in bytes and bytes are transposed. 0x2 TOTR_3 Only bytes are transposed; no bits in a byte are transposed. 0x3 TOT Type Of Transpose For Writes 30 2 read-write TOT_0 No transposition. 0 TOT_1 Bits in bytes are transposed; bytes are not transposed. 0x1 TOT_2 Both bits in bytes and bytes are transposed. 0x2 TOT_3 Only bytes are transposed; no bits in a byte are transposed. 0x3 PDB0 Programmable Delay Block PDB PDB0_ PDB 0x40036000 0 0x198 registers SC Status and Control register 0 32 read-write 0 0xFFFFFFFF LDOK Load OK 0 1 read-write CONT Continuous Mode Enable 1 1 read-write CONT_0 PDB operation in One-Shot mode 0 CONT_1 PDB operation in Continuous mode 0x1 MULT Multiplication Factor Select for Prescaler 2 2 read-write MULT_0 Multiplication factor is 1. 0 MULT_1 Multiplication factor is 10. 0x1 MULT_2 Multiplication factor is 20. 0x2 MULT_3 Multiplication factor is 40. 0x3 PDBIE PDB Interrupt Enable 5 1 read-write PDBIE_0 PDB interrupt disabled. 0 PDBIE_1 PDB interrupt enabled. 0x1 PDBIF PDB Interrupt Flag 6 1 read-write PDBEN PDB Enable 7 1 read-write PDBEN_0 PDB disabled. Counter is off. 0 PDBEN_1 PDB enabled. 0x1 TRGSEL Trigger Input Source Select 8 4 read-write TRGSEL_0 Trigger-In 0 is selected. 0 TRGSEL_1 Trigger-In 1 is selected. 0x1 TRGSEL_2 Trigger-In 2 is selected. 0x2 TRGSEL_3 Trigger-In 3 is selected. 0x3 TRGSEL_4 Trigger-In 4 is selected. 0x4 TRGSEL_5 Trigger-In 5 is selected. 0x5 TRGSEL_6 Trigger-In 6 is selected. 0x6 TRGSEL_7 Trigger-In 7 is selected. 0x7 TRGSEL_8 Trigger-In 8 is selected. 0x8 TRGSEL_9 Trigger-In 9 is selected. 0x9 TRGSEL_10 Trigger-In 10 is selected. 0xA TRGSEL_11 Trigger-In 11 is selected. 0xB TRGSEL_12 Trigger-In 12 is selected. 0xC TRGSEL_13 Trigger-In 13 is selected. 0xD TRGSEL_14 Trigger-In 14 is selected. 0xE TRGSEL_15 Software trigger is selected. 0xF PRESCALER Prescaler Divider Select 12 3 read-write PRESCALER_0 Counting uses the peripheral clock divided by MULT (the multiplication factor). 0 PRESCALER_1 Counting uses the peripheral clock divided by 2 x MULT (the multiplication factor). 0x1 PRESCALER_2 Counting uses the peripheral clock divided by 4 x MULT (the multiplication factor). 0x2 PRESCALER_3 Counting uses the peripheral clock divided by 8 x MULT (the multiplication factor). 0x3 PRESCALER_4 Counting uses the peripheral clock divided by 16 x MULT (the multiplication factor). 0x4 PRESCALER_5 Counting uses the peripheral clock divided by 32 x MULT (the multiplication factor). 0x5 PRESCALER_6 Counting uses the peripheral clock divided by 64 x MULT (the multiplication factor). 0x6 PRESCALER_7 Counting uses the peripheral clock divided by 128 x MULT (the multiplication factor). 0x7 DMAEN DMA Enable 15 1 read-write DMAEN_0 DMA disabled. 0 DMAEN_1 DMA enabled. 0x1 SWTRIG Software Trigger 16 1 read-write PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write PDBEIE_0 PDB sequence error interrupt disabled. 0 PDBEIE_1 PDB sequence error interrupt enabled. 0x1 LDMOD Load Mode Select 18 2 read-write LDMOD_0 The internal registers are loaded with the values from their buffers, immediately after 1 is written to LDOK. 0 LDMOD_1 The internal registers are loaded with the values from their buffers when the PDB counter (CNT) = MOD + 1 CNT delay elapsed, after 1 is written to LDOK. 0x1 LDMOD_2 The internal registers are loaded with the values from their buffers when a trigger input event is detected, after 1 is written to LDOK. 0x2 LDMOD_3 The internal registers are loaded with the values from their buffers when either the PDB counter (CNT) = MOD + 1 CNT delay elapsed, or a trigger input event is detected, after 1 is written to LDOK. 0x3 MOD Modulus register 0x4 32 read-write 0xFFFF 0xFFFFFFFF MOD PDB Modulus 0 16 read-write CNT Counter register 0x8 32 read-only 0 0xFFFFFFFF CNT PDB Counter 0 16 read-only IDLY Interrupt Delay register 0xC 32 read-write 0xFFFF 0xFFFFFFFF IDLY PDB Interrupt Delay 0 16 read-write 2 0x28 0,1 CH%sC1 Channel n Control register 1 0x10 32 read-write 0 0xFFFFFFFF EN PDB Channel Pre-Trigger Enable 0 8 read-write EN_0 PDB channel's corresponding pre-trigger disabled. 0 EN_1 PDB channel's corresponding pre-trigger enabled. 0x1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write TOS_0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. 0 TOS_1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. 0x1 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write BB_0 PDB channel's corresponding pre-trigger back-to-back operation disabled. 0 BB_1 PDB channel's corresponding pre-trigger back-to-back operation enabled. 0x1 2 0x28 0,1 CH%sS Channel n Status register 0x14 32 read-write 0 0xFFFFFFFF ERR PDB Channel Sequence Error Flags 0 8 read-write ERR_0 Sequence error not detected on PDB channel's corresponding pre-trigger. 0 ERR_1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. 0x1 CF PDB Channel Flags 16 8 read-write 2 0x28 0,1 CH%sDLY0 Channel n Delay 0 register 0x18 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY1 Channel n Delay 1 register 0x1C 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY2 Channel n Delay 2 register 0x20 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY3 Channel n Delay 3 register 0x24 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY4 Channel n Delay 4 register 0x28 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY5 Channel n Delay 5 register 0x2C 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY6 Channel n Delay 6 register 0x30 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write 2 0x28 0,1 CH%sDLY7 Channel n Delay 7 register 0x34 32 read-write 0 0xFFFFFFFF DLY PDB Channel Delay 0 16 read-write POEN Pulse-Out n Enable register 0x190 32 read-write 0 0xFFFFFFFF POEN PDB Pulse-Out Enable 0 8 read-write POEN_0 PDB Pulse-Out disabled 0 POEN_1 PDB Pulse-Out enabled 0x1 PODLY Pulse-Out n Delay register 0x194 32 read-write 0 0xFFFFFFFF DLY2 PDB Pulse-Out Delay 2 0 16 read-write DLY1 PDB Pulse-Out Delay 1 16 16 read-write PDB1 Programmable Delay Block PDB PDB1_ 0x40031000 0 0x198 registers LPIT0 LPIT LPIT 0x40037000 0 0x5C registers VERID Version ID Register 0 32 read-only 0x1000000 0xFFFFFFFF FEATURE Feature Number 0 16 read-only MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x404 0xFFFFFFFF CHANNEL Number of Timer Channels 0 8 read-only EXT_TRIG Number of External Trigger Inputs 8 8 read-only MCR Module Control Register 0x8 32 read-write 0 0xFFFFFFFF M_CEN Module Clock Enable 0 1 read-write M_CEN_0 Disable peripheral clock to timers 0 M_CEN_1 Enable peripheral clock to timers 0x1 SW_RST Software Reset Bit 1 1 read-write SW_RST_0 Timer channels and registers are not reset 0 SW_RST_1 Reset timer channels and registers 0x1 DOZE_EN DOZE Mode Enable Bit 2 1 read-write DOZE_EN_0 Stop timer channels in DOZE mode 0 DOZE_EN_1 Allow timer channels to continue to run in DOZE mode 0x1 DBG_EN Debug Enable Bit 3 1 read-write DBG_EN_0 Stop timer channels in Debug mode 0 DBG_EN_1 Allow timer channels to continue to run in Debug mode 0x1 MSR Module Status Register 0xC 32 read-write 0 0xFFFFFFFF TIF0 Channel 0 Timer Interrupt Flag 0 1 read-write oneToClear TIF0_0 Timer has not timed out 0 TIF0_1 Timeout has occurred (timer has timed out) 0x1 TIF1 Channel 1 Timer Interrupt Flag 1 1 read-write oneToClear TIF1_0 Timer has not timed out 0 TIF1_1 Timeout has occurred (timer has timed out) 0x1 TIF2 Channel 2 Timer Interrupt Flag 2 1 read-write oneToClear TIF2_0 Timer has not timed out 0 TIF2_1 Timeout has occurred (timer has timed out) 0x1 TIF3 Channel 3 Timer Interrupt Flag 3 1 read-write oneToClear TIF3_0 Timer has not timed out 0 TIF3_1 Timeout has occurred (timer has timed out) 0x1 MIER Module Interrupt Enable Register 0x10 32 read-write 0 0xFFFFFFFF TIE0 Channel 0 Timer Interrupt Enable 0 1 read-write TIE0_0 Disabled 0 TIE0_1 Enabled 0x1 TIE1 Channel 1 Timer Interrupt Enable 1 1 read-write TIE1_0 Disabled 0 TIE1_1 Enabled 0x1 TIE2 Channel 2 Timer Interrupt Enable 2 1 read-write TIE2_0 Disabled 0 TIE2_1 Enabled 0x1 TIE3 Channel 3 Timer Interrupt Enable 3 1 read-write TIE3_0 Disabled 0 TIE3_1 Enabled 0x1 SETTEN Set Timer Enable Register 0x14 32 read-write 0 0xFFFFFFFF SET_T_EN_0 Set Timer 0 Enable 0 1 read-write SET_T_EN_0_0 No effect 0 SET_T_EN_0_1 Enables Timer Channel 0 0x1 SET_T_EN_1 Set Timer 1 Enable 1 1 read-write SET_T_EN_1_0 No Effect 0 SET_T_EN_1_1 Enables Timer Channel 1 0x1 SET_T_EN_2 Set Timer 2 Enable 2 1 read-write SET_T_EN_2_0 No Effect 0 SET_T_EN_2_1 Enables Timer Channel 2 0x1 SET_T_EN_3 Set Timer 3 Enable 3 1 read-write SET_T_EN_3_0 No effect 0 SET_T_EN_3_1 Enables Timer Channel 3 0x1 CLRTEN Clear Timer Enable Register 0x18 32 read-write 0 0xFFFFFFFF CLR_T_EN_0 Clear Timer 0 Enable 0 1 read-write CLR_T_EN_0_0 No action 0 CLR_T_EN_0_1 Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0 0x1 CLR_T_EN_1 Clear Timer 1 Enable 1 1 read-write CLR_T_EN_1_0 No Action 0 CLR_T_EN_1_1 Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1 0x1 CLR_T_EN_2 Clear Timer 2 Enable 2 1 read-write CLR_T_EN_2_0 No Action 0 CLR_T_EN_2_1 Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2 0x1 CLR_T_EN_3 Clear Timer 3 Enable 3 1 read-write CLR_T_EN_3_0 No Action 0 CLR_T_EN_3_1 Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3 0x1 4 0x10 TMR[%s] no description available 0x20 TVAL Timer Value Register 0 32 read-write 0 0xFFFFFFFF TMR_VAL Timer Value 0 32 read-write TMR_VAL_0 Invalid load value in compare mode 0 TMR_VAL_1 Invalid load value in compare mode 0x1 TMR_VAL_2 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x2 TMR_VAL_3 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x3 TMR_VAL_4 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x4 TMR_VAL_5 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x5 TMR_VAL_6 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x6 TMR_VAL_7 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x7 TMR_VAL_8 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x8 TMR_VAL_9 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x9 CVAL Current Timer Value 0x4 32 read-only 0xFFFFFFFF 0xFFFFFFFF TMR_CUR_VAL Current Timer Value 0 32 read-only TCTRL Timer Control Register 0x8 32 read-write 0 0xFFFFFFFF T_EN Timer Enable 0 1 read-write T_EN_0 Timer Channel is disabled 0 T_EN_1 Timer Channel is enabled 0x1 CHAIN Chain Channel 1 1 read-write CHAIN_0 Channel Chaining is disabled. The channel timer runs independently. 0 CHAIN_1 Channel Chaining is enabled. The timer decrements on the previous channel's timeout. 0x1 MODE Timer Operation Mode 2 2 read-write MODE_0 32-bit Periodic Counter 0 MODE_1 Dual 16-bit Periodic Counter 0x1 MODE_2 32-bit Trigger Accumulator 0x2 MODE_3 32-bit Trigger Input Capture 0x3 TSOT Timer Start On Trigger 16 1 read-write TSOT_0 Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) 0 TSOT_1 Timer starts to decrement when a rising edge on a selected trigger is detected 0x1 TSOI Timer Stop On Interrupt 17 1 read-write TSOI_0 The channel timer does not stop after timeout 0 TSOI_1 The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. 0x1 TROT Timer Reload On Trigger 18 1 read-write TROT_0 Timer will not reload on the selected trigger 0 TROT_1 Timer will reload on the selected trigger 0x1 TRG_SRC Trigger Source 23 1 read-write TRG_SRC_0 Selects external triggers 0 TRG_SRC_1 Selects internal triggers 0x1 TRG_SEL Trigger Select 24 4 read-write TRG_SEL_0 Timer channel 0 - 3 trigger source is selected 0 TRG_SEL_1 Timer channel 0 - 3 trigger source is selected 0x1 TRG_SEL_2 Timer channel 0 - 3 trigger source is selected 0x2 TRG_SEL_3 Timer channel 0 - 3 trigger source is selected 0x3 FTM0 FTM FTM FTM0 0x40038000 0 0xBC registers SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write PS_0 Divide by 1 0 PS_1 Divide by 2 0x1 PS_2 Divide by 4 0x2 PS_3 Divide by 8 0x3 PS_4 Divide by 16 0x4 PS_5 Divide by 32 0x5 PS_6 Divide by 64 0x6 PS_7 Divide by 128 0x7 CLKS Clock Source Selection 3 2 read-write CLKS_0 No clock selected. This in effect disables the FTM counter. 0 CLKS_1 FTM input clock 0x1 CLKS_2 Fixed frequency clock 0x2 CLKS_3 External clock 0x3 CPWMS Center-Aligned PWM Select 5 1 read-write CPWMS_0 FTM counter operates in Up Counting mode. 0 CPWMS_1 FTM counter operates in Up-Down Counting mode. 0x1 RIE Reload Point Interrupt Enable 6 1 read-write RIE_0 Reload point interrupt is disabled. 0 RIE_1 Reload point interrupt is enabled. 0x1 RF Reload Flag 7 1 read-write RF_0 A selected reload point did not happen. 0 RF_1 A selected reload point happened. 0x1 TOIE Timer Overflow Interrupt Enable 8 1 read-write TOIE_0 Disable TOF interrupts. Use software polling. 0 TOIE_1 Enable TOF interrupts. An interrupt is generated when TOF equals one. 0x1 TOF Timer Overflow Flag 9 1 read-write TOF_0 FTM counter has not overflowed. 0 TOF_1 FTM counter has overflowed. 0x1 PWMEN0 Channel 0 PWM enable bit 16 1 read-write PWMEN0_0 Channel output port is disabled. 0 PWMEN0_1 Channel output port is enabled. 0x1 PWMEN1 Channel 1 PWM enable bit 17 1 read-write PWMEN1_0 Channel output port is disabled. 0 PWMEN1_1 Channel output port is enabled. 0x1 PWMEN2 Channel 2 PWM enable bit 18 1 read-write PWMEN2_0 Channel output port is disabled. 0 PWMEN2_1 Channel output port is enabled. 0x1 PWMEN3 Channel 3 PWM enable bit 19 1 read-write PWMEN3_0 Channel output port is disabled. 0 PWMEN3_1 Channel output port is enabled. 0x1 PWMEN4 Channel 4 PWM enable bit 20 1 read-write PWMEN4_0 Channel output port is disabled. 0 PWMEN4_1 Channel output port is enabled. 0x1 PWMEN5 Channel 5 PWM enable bit 21 1 read-write PWMEN5_0 Channel output port is disabled. 0 PWMEN5_1 Channel output port is enabled. 0x1 PWMEN6 Channel 6 PWM enable bit 22 1 read-write PWMEN6_0 Channel output port is disabled. 0 PWMEN6_1 Channel output port is enabled. 0x1 PWMEN7 Channel 7 PWM enable bit 23 1 read-write PWMEN7_0 Channel output port is disabled. 0 PWMEN7_1 Channel output port is enabled. 0x1 FLTPS Filter Prescaler 24 4 read-write FLTPS_0 Divide by 1 0 FLTPS_1 Divide by 2 0x1 FLTPS_2 Divide by 3 0x2 FLTPS_3 Divide by 4 0x3 FLTPS_4 Divide by 5 0x4 FLTPS_5 Divide by 6 0x5 FLTPS_6 Divide by 7 0x6 FLTPS_7 Divide by 8 0x7 FLTPS_8 Divide by 9 0x8 FLTPS_9 Divide by 10 0x9 FLTPS_10 Divide by 11 0xA FLTPS_11 Divide by 12 0xB FLTPS_12 Divide by 13 0xC FLTPS_13 Divide by 14 0xD FLTPS_14 Divide by 15 0xE FLTPS_15 Divide by 16 0xF CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD MOD 0 16 read-write 8 0x8 CONTROLS[%s] no description available 0xC CSC Channel (n) Status And Control 0 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write ICRST_0 FTM counter is not reset when the selected channel (n) input event is detected. 0 ICRST_1 FTM counter is reset when the selected channel (n) input event is detected. 0x1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write CHIE_0 Disable channel (n) interrupt. Use software polling. 0 CHIE_1 Enable channel (n) interrupt. 0x1 CHF Channel (n) Flag 7 1 read-write CHF_0 No channel (n) event has occurred. 0 CHF_1 A channel (n) event has occurred. 0x1 TRIGMODE Trigger mode control 8 1 read-write TRIGMODE_0 Channel outputs will generate the normal PWM outputs without generating a pulse. 0 TRIGMODE_1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. 0x1 CHIS Channel (n) Input State 9 1 read-only CHIS_0 The channel (n) input is zero. 0 CHIS_1 The channel (n) input is one. 0x1 CHOV Channel (n) Output Value 10 1 read-only CHOV_0 The channel (n) output is zero. 0 CHOV_1 The channel (n) output is one. 0x1 CV Channel (n) Value 0x4 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT INIT 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write CH0F_0 No channel event has occurred. 0 CH0F_1 A channel event has occurred. 0x1 CH1F Channel 1 Flag 1 1 read-write CH1F_0 No channel event has occurred. 0 CH1F_1 A channel event has occurred. 0x1 CH2F Channel 2 Flag 2 1 read-write CH2F_0 No channel event has occurred. 0 CH2F_1 A channel event has occurred. 0x1 CH3F Channel 3 Flag 3 1 read-write CH3F_0 No channel event has occurred. 0 CH3F_1 A channel event has occurred. 0x1 CH4F Channel 4 Flag 4 1 read-write CH4F_0 No channel event has occurred. 0 CH4F_1 A channel event has occurred. 0x1 CH5F Channel 5 Flag 5 1 read-write CH5F_0 No channel event has occurred. 0 CH5F_1 A channel event has occurred. 0x1 CH6F Channel 6 Flag 6 1 read-write CH6F_0 No channel event has occurred. 0 CH6F_1 A channel event has occurred. 0x1 CH7F Channel 7 Flag 7 1 read-write CH7F_0 No channel event has occurred. 0 CH7F_1 A channel event has occurred. 0x1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write FTMEN_0 TPM compatibility. Free running counter and synchronization compatible with TPM. 0 FTMEN_1 Free running counter and synchronization are different from TPM behavior. 0x1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write WPDIS_0 Write protection is enabled. 0 WPDIS_1 Write protection is disabled. 0x1 PWMSYNC PWM Synchronization Mode 3 1 read-write PWMSYNC_0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. 0 PWMSYNC_1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. 0x1 CAPTEST Capture Test Mode Enable 4 1 read-write CAPTEST_0 Capture test mode is disabled. 0 CAPTEST_1 Capture test mode is enabled. 0x1 FAULTM Fault Control Mode 5 2 read-write FAULTM_0 Fault control is disabled for all channels. 0 FAULTM_1 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. 0x1 FAULTM_2 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. 0x2 FAULTM_3 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. 0x3 FAULTIE Fault Interrupt Enable 7 1 read-write FAULTIE_0 Fault control interrupt is disabled. 0 FAULTIE_1 Fault control interrupt is enabled. 0x1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write CNTMIN_0 The minimum loading point is disabled. 0 CNTMIN_1 The minimum loading point is enabled. 0x1 CNTMAX Maximum Loading Point Enable 1 1 read-write CNTMAX_0 The maximum loading point is disabled. 0 CNTMAX_1 The maximum loading point is enabled. 0x1 REINIT FTM Counter Reinitialization by Synchronization 2 1 read-write REINIT_0 FTM counter continues to count normally. 0 REINIT_1 FTM counter is updated with its initial value when the selected trigger is detected. 0x1 SYNCHOM Output Mask Synchronization 3 1 read-write SYNCHOM_0 OUTMASK register is updated with the value of its buffer in all rising edges of the FTM input clock. 0 SYNCHOM_1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. 0x1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write TRIG0_0 Trigger is disabled. 0 TRIG0_1 Trigger is enabled. 0x1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write TRIG1_0 Trigger is disabled. 0 TRIG1_1 Trigger is enabled. 0x1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write TRIG2_0 Trigger is disabled. 0 TRIG2_1 Trigger is enabled. 0x1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write SWSYNC_0 Software trigger is not selected. 0 SWSYNC_1 Software trigger is selected. 0x1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write CH0OI_0 The initialization value is 0. 0 CH0OI_1 The initialization value is 1. 0x1 CH1OI Channel 1 Output Initialization Value 1 1 read-write CH1OI_0 The initialization value is 0. 0 CH1OI_1 The initialization value is 1. 0x1 CH2OI Channel 2 Output Initialization Value 2 1 read-write CH2OI_0 The initialization value is 0. 0 CH2OI_1 The initialization value is 1. 0x1 CH3OI Channel 3 Output Initialization Value 3 1 read-write CH3OI_0 The initialization value is 0. 0 CH3OI_1 The initialization value is 1. 0x1 CH4OI Channel 4 Output Initialization Value 4 1 read-write CH4OI_0 The initialization value is 0. 0 CH4OI_1 The initialization value is 1. 0x1 CH5OI Channel 5 Output Initialization Value 5 1 read-write CH5OI_0 The initialization value is 0. 0 CH5OI_1 The initialization value is 1. 0x1 CH6OI Channel 6 Output Initialization Value 6 1 read-write CH6OI_0 The initialization value is 0. 0 CH6OI_1 The initialization value is 1. 0x1 CH7OI Channel 7 Output Initialization Value 7 1 read-write CH7OI_0 The initialization value is 0. 0 CH7OI_1 The initialization value is 1. 0x1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write CH0OM_0 Channel output is not masked. It continues to operate normally. 0 CH0OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH1OM Channel 1 Output Mask 1 1 read-write CH1OM_0 Channel output is not masked. It continues to operate normally. 0 CH1OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH2OM Channel 2 Output Mask 2 1 read-write CH2OM_0 Channel output is not masked. It continues to operate normally. 0 CH2OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH3OM Channel 3 Output Mask 3 1 read-write CH3OM_0 Channel output is not masked. It continues to operate normally. 0 CH3OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH4OM Channel 4 Output Mask 4 1 read-write CH4OM_0 Channel output is not masked. It continues to operate normally. 0 CH4OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH5OM Channel 5 Output Mask 5 1 read-write CH5OM_0 Channel output is not masked. It continues to operate normally. 0 CH5OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH6OM Channel 6 Output Mask 6 1 read-write CH6OM_0 Channel output is not masked. It continues to operate normally. 0 CH6OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH7OM Channel 7 Output Mask 7 1 read-write CH7OM_0 Channel output is not masked. It continues to operate normally. 0 CH7OM_1 Channel output is masked. It is forced to its inactive state. 0x1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write COMP0 Complement Of Channel (n) For n = 0 1 1 read-write COMP0_0 If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the channel (n+1) output is independent from channel (n) output. 0 COMP0_1 The channel (n+1) output is the complement of the channel (n) output. 0x1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write DECAP0_0 The dual edge captures are inactive. 0 DECAP0_1 The dual edge captures are active. 0x1 DTEN0 Deadtime Enable For n = 0 4 1 read-write DTEN0_0 The deadtime insertion in this pair of channels is disabled. 0 DTEN0_1 The deadtime insertion in this pair of channels is enabled. 0x1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write SYNCEN0_0 The PWM synchronization in this pair of channels is disabled. 0 SYNCEN0_1 The PWM synchronization in this pair of channels is enabled. 0x1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write FAULTEN0_0 The fault control in this pair of channels is disabled. 0 FAULTEN0_1 The fault control in this pair of channels is enabled. 0x1 MCOMBINE0 Modified Combine Mode For n = 0 7 1 read-write COMBINE1 Combine Channels For n = 2 8 1 read-write COMP1 Complement Of Channel (n) For n = 2 9 1 read-write COMP1_0 If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the channel (n+1) output is independent from channel (n) output. 0 COMP1_1 The channel (n+1) output is the complement of the channel (n) output. 0x1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write DECAP1_0 The dual edge captures are inactive. 0 DECAP1_1 The dual edge captures are active. 0x1 DTEN1 Deadtime Enable For n = 2 12 1 read-write DTEN1_0 The deadtime insertion in this pair of channels is disabled. 0 DTEN1_1 The deadtime insertion in this pair of channels is enabled. 0x1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write SYNCEN1_0 The PWM synchronization in this pair of channels is disabled. 0 SYNCEN1_1 The PWM synchronization in this pair of channels is enabled. 0x1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write FAULTEN1_0 The fault control in this pair of channels is disabled. 0 FAULTEN1_1 The fault control in this pair of channels is enabled. 0x1 MCOMBINE1 Modified Combine Mode For n = 2 15 1 read-write COMBINE2 Combine Channels For n = 4 16 1 read-write COMP2 Complement Of Channel (n) For n = 4 17 1 read-write COMP2_0 If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the channel (n+1) output is independent from channel (n) output. 0 COMP2_1 The channel (n+1) output is the complement of the channel (n) output. 0x1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write DECAP2_0 The dual edge captures are inactive. 0 DECAP2_1 The dual edge captures are active. 0x1 DTEN2 Deadtime Enable For n = 4 20 1 read-write DTEN2_0 The deadtime insertion in this pair of channels is disabled. 0 DTEN2_1 The deadtime insertion in this pair of channels is enabled. 0x1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write SYNCEN2_0 The PWM synchronization in this pair of channels is disabled. 0 SYNCEN2_1 The PWM synchronization in this pair of channels is enabled. 0x1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write FAULTEN2_0 The fault control in this pair of channels is disabled. 0 FAULTEN2_1 The fault control in this pair of channels is enabled. 0x1 MCOMBINE2 Modified Combine Mode For n = 4 23 1 read-write COMBINE3 Combine Channels For n = 6 24 1 read-write COMP3 Complement Of Channel (n) for n = 6 25 1 read-write COMP3_0 If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the channel (n+1) output is independent from channel (n) output. 0 COMP3_1 The channel (n+1) output is the complement of the channel (n) output. 0x1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write DECAP3_0 The dual edge captures are inactive. 0 DECAP3_1 The dual edge captures are active. 0x1 DTEN3 Deadtime Enable For n = 6 28 1 read-write DTEN3_0 The deadtime insertion in this pair of channels is disabled. 0 DTEN3_1 The deadtime insertion in this pair of channels is enabled. 0x1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write SYNCEN3_0 The PWM synchronization in this pair of channels is disabled. 0 SYNCEN3_1 The PWM synchronization in this pair of channels is enabled. 0x1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write FAULTEN3_0 The fault control in this pair of channels is disabled. 0 FAULTEN3_1 The fault control in this pair of channels is enabled. 0x1 MCOMBINE3 Modified Combine Mode For n = 6 31 1 read-write DEADTIME Deadtime Configuration 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write DTPS_0 Divide the FTM input clock by 1. #0x DTPS_2 Divide the FTM input clock by 4. 0x2 DTPS_3 Divide the FTM input clock by 16. 0x3 DTVALEX Extended Deadtime Value 16 4 read-write EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 External Trigger Enable 0 1 read-write CH2TRIG_0 The generation of this external trigger is disabled. 0 CH2TRIG_1 The generation of this external trigger is enabled. 0x1 CH3TRIG Channel 3 External Trigger Enable 1 1 read-write CH3TRIG_0 The generation of this external trigger is disabled. 0 CH3TRIG_1 The generation of this external trigger is enabled. 0x1 CH4TRIG Channel 4 External Trigger Enable 2 1 read-write CH4TRIG_0 The generation of this external trigger is disabled. 0 CH4TRIG_1 The generation of this external trigger is enabled. 0x1 CH5TRIG Channel 5 External Trigger Enable 3 1 read-write CH5TRIG_0 The generation of this external trigger is disabled. 0 CH5TRIG_1 The generation of this external trigger is enabled. 0x1 CH0TRIG Channel 0 External Trigger Enable 4 1 read-write CH0TRIG_0 The generation of this external trigger is disabled. 0 CH0TRIG_1 The generation of this external trigger is enabled. 0x1 CH1TRIG Channel 1 External Trigger Enable 5 1 read-write CH1TRIG_0 The generation of this external trigger is disabled. 0 CH1TRIG_1 The generation of this external trigger is enabled. 0x1 INITTRIGEN Initialization Trigger Enable 6 1 read-write INITTRIGEN_0 The generation of initialization trigger is disabled. 0 INITTRIGEN_1 The generation of initialization trigger is enabled. 0x1 TRIGF Channel Trigger Flag 7 1 read-write TRIGF_0 No channel trigger was generated. 0 TRIGF_1 A channel trigger was generated. 0x1 CH6TRIG Channel 6 External Trigger Enable 8 1 read-write CH6TRIG_0 The generation of this external trigger is disabled. 0 CH6TRIG_1 The generation of this external trigger is enabled. 0x1 CH7TRIG Channel 7 External Trigger Enable 9 1 read-write CH7TRIG_0 The generation of this external trigger is disabled. 0 CH7TRIG_1 The generation of this external trigger is enabled. 0x1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write POL0_0 The channel polarity is active high. 0 POL0_1 The channel polarity is active low. 0x1 POL1 Channel 1 Polarity 1 1 read-write POL1_0 The channel polarity is active high. 0 POL1_1 The channel polarity is active low. 0x1 POL2 Channel 2 Polarity 2 1 read-write POL2_0 The channel polarity is active high. 0 POL2_1 The channel polarity is active low. 0x1 POL3 Channel 3 Polarity 3 1 read-write POL3_0 The channel polarity is active high. 0 POL3_1 The channel polarity is active low. 0x1 POL4 Channel 4 Polarity 4 1 read-write POL4_0 The channel polarity is active high. 0 POL4_1 The channel polarity is active low. 0x1 POL5 Channel 5 Polarity 5 1 read-write POL5_0 The channel polarity is active high. 0 POL5_1 The channel polarity is active low. 0x1 POL6 Channel 6 Polarity 6 1 read-write POL6_0 The channel polarity is active high. 0 POL6_1 The channel polarity is active low. 0x1 POL7 Channel 7 Polarity 7 1 read-write POL7_0 The channel polarity is active high. 0 POL7_1 The channel polarity is active low. 0x1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-write FAULTF0_0 No fault condition was detected at the fault input. 0 FAULTF0_1 A fault condition was detected at the fault input. 0x1 FAULTF1 Fault Detection Flag 1 1 1 read-write FAULTF1_0 No fault condition was detected at the fault input. 0 FAULTF1_1 A fault condition was detected at the fault input. 0x1 FAULTF2 Fault Detection Flag 2 2 1 read-write FAULTF2_0 No fault condition was detected at the fault input. 0 FAULTF2_1 A fault condition was detected at the fault input. 0x1 FAULTF3 Fault Detection Flag 3 3 1 read-write FAULTF3_0 No fault condition was detected at the fault input. 0 FAULTF3_1 A fault condition was detected at the fault input. 0x1 FAULTIN Fault Inputs 5 1 read-only FAULTIN_0 The logic OR of the enabled fault inputs is 0. 0 FAULTIN_1 The logic OR of the enabled fault inputs is 1. 0x1 WPEN Write Protection Enable 6 1 read-write WPEN_0 Write protection is disabled. Write protected bits can be written. 0 WPEN_1 Write protection is enabled. Write protected bits cannot be written. 0x1 FAULTF Fault Detection Flag 7 1 read-write FAULTF_0 No fault condition was detected. 0 FAULTF_1 A fault condition was detected. 0x1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write FAULT0EN_0 Fault input is disabled. 0 FAULT0EN_1 Fault input is enabled. 0x1 FAULT1EN Fault Input 1 Enable 1 1 read-write FAULT1EN_0 Fault input is disabled. 0 FAULT1EN_1 Fault input is enabled. 0x1 FAULT2EN Fault Input 2 Enable 2 1 read-write FAULT2EN_0 Fault input is disabled. 0 FAULT2EN_1 Fault input is enabled. 0x1 FAULT3EN Fault Input 3 Enable 3 1 read-write FAULT3EN_0 Fault input is disabled. 0 FAULT3EN_1 Fault input is enabled. 0x1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write FFLTR0EN_0 Fault input filter is disabled. 0 FFLTR0EN_1 Fault input filter is enabled. 0x1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write FFLTR1EN_0 Fault input filter is disabled. 0 FFLTR1EN_1 Fault input filter is enabled. 0x1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write FFLTR2EN_0 Fault input filter is disabled. 0 FFLTR2EN_1 Fault input filter is enabled. 0x1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write FFLTR3EN_0 Fault input filter is disabled. 0 FFLTR3EN_1 Fault input filter is enabled. 0x1 FFVAL Fault Input Filter 8 4 read-write FSTATE Fault output state 15 1 read-write FSTATE_0 FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits). 0 FSTATE_1 FTM outputs will be tri-stated when fault event is ongoing 0x1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF LDFQ Frequency of the Reload Opportunities 0 5 read-write BDMMODE Debug Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write GTBEEN_0 Use of an external global time base is disabled. 0 GTBEEN_1 Use of an external global time base is enabled. 0x1 GTBEOUT Global Time Base Output 10 1 read-write GTBEOUT_0 A global time base signal generation is disabled. 0 GTBEOUT_1 A global time base signal generation is enabled. 0x1 ITRIGR Initialization trigger on Reload Point 11 1 read-write ITRIGR_0 Initialization trigger is generated on counter wrap events. 0 ITRIGR_1 Initialization trigger is generated when a reload point is reached. 0x1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write FLT0POL_0 The fault input polarity is active high. A 1 at the fault input indicates a fault. 0 FLT0POL_1 The fault input polarity is active low. A 0 at the fault input indicates a fault. 0x1 FLT1POL Fault Input 1 Polarity 1 1 read-write FLT1POL_0 The fault input polarity is active high. A 1 at the fault input indicates a fault. 0 FLT1POL_1 The fault input polarity is active low. A 0 at the fault input indicates a fault. 0x1 FLT2POL Fault Input 2 Polarity 2 1 read-write FLT2POL_0 The fault input polarity is active high. A 1 at the fault input indicates a fault. 0 FLT2POL_1 The fault input polarity is active low. A 0 at the fault input indicates a fault. 0x1 FLT3POL Fault Input 3 Polarity 3 1 read-write FLT3POL_0 The fault input polarity is active high. A 1 at the fault input indicates a fault. 0 FLT3POL_1 The fault input polarity is active low. A 0 at the fault input indicates a fault. 0x1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write HWTRIGMODE_0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 0 HWTRIGMODE_1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 0x1 CNTINC CNTIN Register Synchronization 2 1 read-write CNTINC_0 CNTIN register is updated with its buffer value at all rising edges of FTM input clock. 0 CNTINC_1 CNTIN register is updated with its buffer value by the PWM synchronization. 0x1 INVC INVCTRL Register Synchronization 4 1 read-write INVC_0 INVCTRL register is updated with its buffer value at all rising edges of FTM input clock. 0 INVC_1 INVCTRL register is updated with its buffer value by the PWM synchronization. 0x1 SWOC SWOCTRL Register Synchronization 5 1 read-write SWOC_0 SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock. 0 SWOC_1 SWOCTRL register is updated with its buffer value by the PWM synchronization. 0x1 SYNCMODE Synchronization Mode 7 1 read-write SYNCMODE_0 Legacy PWM synchronization is selected. 0 SYNCMODE_1 Enhanced PWM synchronization is selected. 0x1 SWRSTCNT FTM counter synchronization is activated by the software trigger 8 1 read-write SWRSTCNT_0 The software trigger does not activate the FTM counter synchronization. 0 SWRSTCNT_1 The software trigger activates the FTM counter synchronization. 0x1 SWWRBUF MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger 9 1 read-write SWWRBUF_0 The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. 0 SWWRBUF_1 The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization. 0x1 SWOM Output mask synchronization is activated by the software trigger 10 1 read-write SWOM_0 The software trigger does not activate the OUTMASK register synchronization. 0 SWOM_1 The software trigger activates the OUTMASK register synchronization. 0x1 SWINVC Inverting control synchronization is activated by the software trigger 11 1 read-write SWINVC_0 The software trigger does not activate the INVCTRL register synchronization. 0 SWINVC_1 The software trigger activates the INVCTRL register synchronization. 0x1 SWSOC Software output control synchronization is activated by the software trigger 12 1 read-write SWSOC_0 The software trigger does not activate the SWOCTRL register synchronization. 0 SWSOC_1 The software trigger activates the SWOCTRL register synchronization. 0x1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger 16 1 read-write HWRSTCNT_0 A hardware trigger does not activate the FTM counter synchronization. 0 HWRSTCNT_1 A hardware trigger activates the FTM counter synchronization. 0x1 HWWRBUF MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger 17 1 read-write HWWRBUF_0 A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. 0 HWWRBUF_1 A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization. 0x1 HWOM Output mask synchronization is activated by a hardware trigger 18 1 read-write HWOM_0 A hardware trigger does not activate the OUTMASK register synchronization. 0 HWOM_1 A hardware trigger activates the OUTMASK register synchronization. 0x1 HWINVC Inverting control synchronization is activated by a hardware trigger 19 1 read-write HWINVC_0 A hardware trigger does not activate the INVCTRL register synchronization. 0 HWINVC_1 A hardware trigger activates the INVCTRL register synchronization. 0x1 HWSOC Software output control synchronization is activated by a hardware trigger 20 1 read-write HWSOC_0 A hardware trigger does not activate the SWOCTRL register synchronization. 0 HWSOC_1 A hardware trigger activates the SWOCTRL register synchronization. 0x1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write INV0EN_0 Inverting is disabled. 0 INV0EN_1 Inverting is enabled. 0x1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write INV1EN_0 Inverting is disabled. 0 INV1EN_1 Inverting is enabled. 0x1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write INV2EN_0 Inverting is disabled. 0 INV2EN_1 Inverting is enabled. 0x1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write INV3EN_0 Inverting is disabled. 0 INV3EN_1 Inverting is enabled. 0x1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write CH0OC_0 The channel output is not affected by software output control. 0 CH0OC_1 The channel output is affected by software output control. 0x1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write CH1OC_0 The channel output is not affected by software output control. 0 CH1OC_1 The channel output is affected by software output control. 0x1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write CH2OC_0 The channel output is not affected by software output control. 0 CH2OC_1 The channel output is affected by software output control. 0x1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write CH3OC_0 The channel output is not affected by software output control. 0 CH3OC_1 The channel output is affected by software output control. 0x1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write CH4OC_0 The channel output is not affected by software output control. 0 CH4OC_1 The channel output is affected by software output control. 0x1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write CH5OC_0 The channel output is not affected by software output control. 0 CH5OC_1 The channel output is affected by software output control. 0x1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write CH6OC_0 The channel output is not affected by software output control. 0 CH6OC_1 The channel output is affected by software output control. 0x1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write CH7OC_0 The channel output is not affected by software output control. 0 CH7OC_1 The channel output is affected by software output control. 0x1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write CH0OCV_0 The software output control forces 0 to the channel output. 0 CH0OCV_1 The software output control forces 1 to the channel output. 0x1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write CH1OCV_0 The software output control forces 0 to the channel output. 0 CH1OCV_1 The software output control forces 1 to the channel output. 0x1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write CH2OCV_0 The software output control forces 0 to the channel output. 0 CH2OCV_1 The software output control forces 1 to the channel output. 0x1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write CH3OCV_0 The software output control forces 0 to the channel output. 0 CH3OCV_1 The software output control forces 1 to the channel output. 0x1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write CH4OCV_0 The software output control forces 0 to the channel output. 0 CH4OCV_1 The software output control forces 1 to the channel output. 0x1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write CH5OCV_0 The software output control forces 0 to the channel output. 0 CH5OCV_1 The software output control forces 1 to the channel output. 0x1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write CH6OCV_0 The software output control forces 0 to the channel output. 0 CH6OCV_1 The software output control forces 1 to the channel output. 0x1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write CH7OCV_0 The software output control forces 0 to the channel output. 0 CH7OCV_1 The software output control forces 1 to the channel output. 0x1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write CH0SEL_0 Channel match is not included as a reload opportunity. 0 CH0SEL_1 Channel match is included as a reload opportunity. 0x1 CH1SEL Channel 1 Select 1 1 read-write CH1SEL_0 Channel match is not included as a reload opportunity. 0 CH1SEL_1 Channel match is included as a reload opportunity. 0x1 CH2SEL Channel 2 Select 2 1 read-write CH2SEL_0 Channel match is not included as a reload opportunity. 0 CH2SEL_1 Channel match is included as a reload opportunity. 0x1 CH3SEL Channel 3 Select 3 1 read-write CH3SEL_0 Channel match is not included as a reload opportunity. 0 CH3SEL_1 Channel match is included as a reload opportunity. 0x1 CH4SEL Channel 4 Select 4 1 read-write CH4SEL_0 Channel match is not included as a reload opportunity. 0 CH4SEL_1 Channel match is included as a reload opportunity. 0x1 CH5SEL Channel 5 Select 5 1 read-write CH5SEL_0 Channel match is not included as a reload opportunity. 0 CH5SEL_1 Channel match is included as a reload opportunity. 0x1 CH6SEL Channel 6 Select 6 1 read-write CH6SEL_0 Channel match is not included as a reload opportunity. 0 CH6SEL_1 Channel match is included as a reload opportunity. 0x1 CH7SEL Channel 7 Select 7 1 read-write CH7SEL_0 Channel match is not included as a reload opportunity. 0 CH7SEL_1 Channel match is included as a reload opportunity. 0x1 HCSEL Half Cycle Select 8 1 read-write HCSEL_0 Half cycle reload is disabled and it is not considered as a reload opportunity. 0 HCSEL_1 Half cycle reload is enabled and it is considered as a reload opportunity. 0x1 LDOK Load Enable 9 1 read-write LDOK_0 Loading updated values is disabled. 0 LDOK_1 Loading updated values is enabled. 0x1 GLEN Global Load Enable 10 1 read-write GLEN_0 Global Load Ok disabled. 0 GLEN_1 Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit. 0x1 GLDOK Global Load OK 11 1 read-write GLDOK_0 No action. 0 GLDOK_1 LDOK bit is set. 0x1 HCR Half Cycle Register 0x9C 32 read-write 0 0xFFFFFFFF HCVAL Half Cycle Value 0 16 read-write PAIR0DEADTIME Pair 0 Deadtime Configuration 0xA0 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write DTPS_0 Divide the FTM input clock by 1. #0x DTPS_2 Divide the FTM input clock by 4. 0x2 DTPS_3 Divide the FTM input clock by 16. 0x3 DTVALEX Extended Deadtime Value 16 4 read-write PAIR1DEADTIME Pair 1 Deadtime Configuration 0xA8 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write DTPS_0 Divide the FTM input clock by 1. #0x DTPS_2 Divide the FTM input clock by 4. 0x2 DTPS_3 Divide the FTM input clock by 16. 0x3 DTVALEX Extended Deadtime Value 16 4 read-write PAIR2DEADTIME Pair 2 Deadtime Configuration 0xB0 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write DTPS_0 Divide the FTM input clock by 1. #0x DTPS_2 Divide the FTM input clock by 4. 0x2 DTPS_3 Divide the FTM input clock by 16. 0x3 DTVALEX Extended Deadtime Value 16 4 read-write PAIR3DEADTIME Pair 3 Deadtime Configuration 0xB8 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write DTPS_0 Divide the FTM input clock by 1. #0x DTPS_2 Divide the FTM input clock by 4. 0x2 DTPS_3 Divide the FTM input clock by 16. 0x3 DTVALEX Extended Deadtime Value 16 4 read-write FTM3 FTM FTM 0x40026000 0 0xBC registers FTM1 FTM FTM FTM1 0x40039000 0 0x224 registers SC Status And Control 0 32 read-write 0 0xFFFFFFFF PS Prescale Factor Selection 0 3 read-write PS_0 Divide by 1 0 PS_1 Divide by 2 0x1 PS_2 Divide by 4 0x2 PS_3 Divide by 8 0x3 PS_4 Divide by 16 0x4 PS_5 Divide by 32 0x5 PS_6 Divide by 64 0x6 PS_7 Divide by 128 0x7 CLKS Clock Source Selection 3 2 read-write CLKS_0 No clock selected. This in effect disables the FTM counter. 0 CLKS_1 FTM input clock 0x1 CLKS_2 Fixed frequency clock 0x2 CLKS_3 External clock 0x3 CPWMS Center-Aligned PWM Select 5 1 read-write CPWMS_0 FTM counter operates in Up Counting mode. 0 CPWMS_1 FTM counter operates in Up-Down Counting mode. 0x1 RIE Reload Point Interrupt Enable 6 1 read-write RIE_0 Reload point interrupt is disabled. 0 RIE_1 Reload point interrupt is enabled. 0x1 RF Reload Flag 7 1 read-write RF_0 A selected reload point did not happen. 0 RF_1 A selected reload point happened. 0x1 TOIE Timer Overflow Interrupt Enable 8 1 read-write TOIE_0 Disable TOF interrupts. Use software polling. 0 TOIE_1 Enable TOF interrupts. An interrupt is generated when TOF equals one. 0x1 TOF Timer Overflow Flag 9 1 read-write TOF_0 FTM counter has not overflowed. 0 TOF_1 FTM counter has overflowed. 0x1 PWMEN0 Channel 0 PWM enable bit 16 1 read-write PWMEN0_0 Channel output port is disabled. 0 PWMEN0_1 Channel output port is enabled. 0x1 PWMEN1 Channel 1 PWM enable bit 17 1 read-write PWMEN1_0 Channel output port is disabled. 0 PWMEN1_1 Channel output port is enabled. 0x1 PWMEN2 Channel 2 PWM enable bit 18 1 read-write PWMEN2_0 Channel output port is disabled. 0 PWMEN2_1 Channel output port is enabled. 0x1 PWMEN3 Channel 3 PWM enable bit 19 1 read-write PWMEN3_0 Channel output port is disabled. 0 PWMEN3_1 Channel output port is enabled. 0x1 PWMEN4 Channel 4 PWM enable bit 20 1 read-write PWMEN4_0 Channel output port is disabled. 0 PWMEN4_1 Channel output port is enabled. 0x1 PWMEN5 Channel 5 PWM enable bit 21 1 read-write PWMEN5_0 Channel output port is disabled. 0 PWMEN5_1 Channel output port is enabled. 0x1 PWMEN6 Channel 6 PWM enable bit 22 1 read-write PWMEN6_0 Channel output port is disabled. 0 PWMEN6_1 Channel output port is enabled. 0x1 PWMEN7 Channel 7 PWM enable bit 23 1 read-write PWMEN7_0 Channel output port is disabled. 0 PWMEN7_1 Channel output port is enabled. 0x1 FLTPS Filter Prescaler 24 4 read-write FLTPS_0 Divide by 1 0 FLTPS_1 Divide by 2 0x1 FLTPS_2 Divide by 3 0x2 FLTPS_3 Divide by 4 0x3 FLTPS_4 Divide by 5 0x4 FLTPS_5 Divide by 6 0x5 FLTPS_6 Divide by 7 0x6 FLTPS_7 Divide by 8 0x7 FLTPS_8 Divide by 9 0x8 FLTPS_9 Divide by 10 0x9 FLTPS_10 Divide by 11 0xA FLTPS_11 Divide by 12 0xB FLTPS_12 Divide by 13 0xC FLTPS_13 Divide by 14 0xD FLTPS_14 Divide by 15 0xE FLTPS_15 Divide by 16 0xF CNT Counter 0x4 32 read-write 0 0xFFFFFFFF COUNT Counter Value 0 16 read-write MOD Modulo 0x8 32 read-write 0 0xFFFFFFFF MOD MOD 0 16 read-write 8 0x8 CONTROLS[%s] no description available 0xC CSC Channel (n) Status And Control 0 32 read-write 0 0xFFFFFFFF DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ICRST FTM counter reset by the selected input capture event. 1 1 read-write ICRST_0 FTM counter is not reset when the selected channel (n) input event is detected. 0 ICRST_1 FTM counter is reset when the selected channel (n) input event is detected. 0x1 ELSA Channel (n) Edge or Level Select 2 1 read-write ELSB Channel (n) Edge or Level Select 3 1 read-write MSA Channel (n) Mode Select 4 1 read-write MSB Channel (n) Mode Select 5 1 read-write CHIE Channel (n) Interrupt Enable 6 1 read-write CHIE_0 Disable channel (n) interrupt. Use software polling. 0 CHIE_1 Enable channel (n) interrupt. 0x1 CHF Channel (n) Flag 7 1 read-write CHF_0 No channel (n) event has occurred. 0 CHF_1 A channel (n) event has occurred. 0x1 TRIGMODE Trigger mode control 8 1 read-write TRIGMODE_0 Channel outputs will generate the normal PWM outputs without generating a pulse. 0 TRIGMODE_1 If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. 0x1 CHIS Channel (n) Input State 9 1 read-only CHIS_0 The channel (n) input is zero. 0 CHIS_1 The channel (n) input is one. 0x1 CHOV Channel (n) Output Value 10 1 read-only CHOV_0 The channel (n) output is zero. 0 CHOV_1 The channel (n) output is one. 0x1 CV Channel (n) Value 0x4 32 read-write 0 0xFFFFFFFF VAL Channel Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write 0 0xFFFFFFFF INIT INIT 0 16 read-write STATUS Capture And Compare Status 0x50 32 read-write 0 0xFFFFFFFF CH0F Channel 0 Flag 0 1 read-write CH0F_0 No channel event has occurred. 0 CH0F_1 A channel event has occurred. 0x1 CH1F Channel 1 Flag 1 1 read-write CH1F_0 No channel event has occurred. 0 CH1F_1 A channel event has occurred. 0x1 CH2F Channel 2 Flag 2 1 read-write CH2F_0 No channel event has occurred. 0 CH2F_1 A channel event has occurred. 0x1 CH3F Channel 3 Flag 3 1 read-write CH3F_0 No channel event has occurred. 0 CH3F_1 A channel event has occurred. 0x1 CH4F Channel 4 Flag 4 1 read-write CH4F_0 No channel event has occurred. 0 CH4F_1 A channel event has occurred. 0x1 CH5F Channel 5 Flag 5 1 read-write CH5F_0 No channel event has occurred. 0 CH5F_1 A channel event has occurred. 0x1 CH6F Channel 6 Flag 6 1 read-write CH6F_0 No channel event has occurred. 0 CH6F_1 A channel event has occurred. 0x1 CH7F Channel 7 Flag 7 1 read-write CH7F_0 No channel event has occurred. 0 CH7F_1 A channel event has occurred. 0x1 MODE Features Mode Selection 0x54 32 read-write 0x4 0xFFFFFFFF FTMEN FTM Enable 0 1 read-write FTMEN_0 TPM compatibility. Free running counter and synchronization compatible with TPM. 0 FTMEN_1 Free running counter and synchronization are different from TPM behavior. 0x1 INIT Initialize The Channels Output 1 1 read-write WPDIS Write Protection Disable 2 1 read-write WPDIS_0 Write protection is enabled. 0 WPDIS_1 Write protection is disabled. 0x1 PWMSYNC PWM Synchronization Mode 3 1 read-write PWMSYNC_0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. 0 PWMSYNC_1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. 0x1 CAPTEST Capture Test Mode Enable 4 1 read-write CAPTEST_0 Capture test mode is disabled. 0 CAPTEST_1 Capture test mode is enabled. 0x1 FAULTM Fault Control Mode 5 2 read-write FAULTM_0 Fault control is disabled for all channels. 0 FAULTM_1 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. 0x1 FAULTM_2 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. 0x2 FAULTM_3 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. 0x3 FAULTIE Fault Interrupt Enable 7 1 read-write FAULTIE_0 Fault control interrupt is disabled. 0 FAULTIE_1 Fault control interrupt is enabled. 0x1 SYNC Synchronization 0x58 32 read-write 0 0xFFFFFFFF CNTMIN Minimum Loading Point Enable 0 1 read-write CNTMIN_0 The minimum loading point is disabled. 0 CNTMIN_1 The minimum loading point is enabled. 0x1 CNTMAX Maximum Loading Point Enable 1 1 read-write CNTMAX_0 The maximum loading point is disabled. 0 CNTMAX_1 The maximum loading point is enabled. 0x1 REINIT FTM Counter Reinitialization by Synchronization 2 1 read-write REINIT_0 FTM counter continues to count normally. 0 REINIT_1 FTM counter is updated with its initial value when the selected trigger is detected. 0x1 SYNCHOM Output Mask Synchronization 3 1 read-write SYNCHOM_0 OUTMASK register is updated with the value of its buffer in all rising edges of the FTM input clock. 0 SYNCHOM_1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. 0x1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write TRIG0_0 Trigger is disabled. 0 TRIG0_1 Trigger is enabled. 0x1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write TRIG1_0 Trigger is disabled. 0 TRIG1_1 Trigger is enabled. 0x1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write TRIG2_0 Trigger is disabled. 0 TRIG2_1 Trigger is enabled. 0x1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write SWSYNC_0 Software trigger is not selected. 0 SWSYNC_1 Software trigger is selected. 0x1 OUTINIT Initial State For Channels Output 0x5C 32 read-write 0 0xFFFFFFFF CH0OI Channel 0 Output Initialization Value 0 1 read-write CH0OI_0 The initialization value is 0. 0 CH0OI_1 The initialization value is 1. 0x1 CH1OI Channel 1 Output Initialization Value 1 1 read-write CH1OI_0 The initialization value is 0. 0 CH1OI_1 The initialization value is 1. 0x1 CH2OI Channel 2 Output Initialization Value 2 1 read-write CH2OI_0 The initialization value is 0. 0 CH2OI_1 The initialization value is 1. 0x1 CH3OI Channel 3 Output Initialization Value 3 1 read-write CH3OI_0 The initialization value is 0. 0 CH3OI_1 The initialization value is 1. 0x1 CH4OI Channel 4 Output Initialization Value 4 1 read-write CH4OI_0 The initialization value is 0. 0 CH4OI_1 The initialization value is 1. 0x1 CH5OI Channel 5 Output Initialization Value 5 1 read-write CH5OI_0 The initialization value is 0. 0 CH5OI_1 The initialization value is 1. 0x1 CH6OI Channel 6 Output Initialization Value 6 1 read-write CH6OI_0 The initialization value is 0. 0 CH6OI_1 The initialization value is 1. 0x1 CH7OI Channel 7 Output Initialization Value 7 1 read-write CH7OI_0 The initialization value is 0. 0 CH7OI_1 The initialization value is 1. 0x1 OUTMASK Output Mask 0x60 32 read-write 0 0xFFFFFFFF CH0OM Channel 0 Output Mask 0 1 read-write CH0OM_0 Channel output is not masked. It continues to operate normally. 0 CH0OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH1OM Channel 1 Output Mask 1 1 read-write CH1OM_0 Channel output is not masked. It continues to operate normally. 0 CH1OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH2OM Channel 2 Output Mask 2 1 read-write CH2OM_0 Channel output is not masked. It continues to operate normally. 0 CH2OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH3OM Channel 3 Output Mask 3 1 read-write CH3OM_0 Channel output is not masked. It continues to operate normally. 0 CH3OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH4OM Channel 4 Output Mask 4 1 read-write CH4OM_0 Channel output is not masked. It continues to operate normally. 0 CH4OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH5OM Channel 5 Output Mask 5 1 read-write CH5OM_0 Channel output is not masked. It continues to operate normally. 0 CH5OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH6OM Channel 6 Output Mask 6 1 read-write CH6OM_0 Channel output is not masked. It continues to operate normally. 0 CH6OM_1 Channel output is masked. It is forced to its inactive state. 0x1 CH7OM Channel 7 Output Mask 7 1 read-write CH7OM_0 Channel output is not masked. It continues to operate normally. 0 CH7OM_1 Channel output is masked. It is forced to its inactive state. 0x1 COMBINE Function For Linked Channels 0x64 32 read-write 0 0xFFFFFFFF COMBINE0 Combine Channels For n = 0 0 1 read-write COMP0 Complement Of Channel (n) For n = 0 1 1 read-write COMP0_0 If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the channel (n+1) output is independent from channel (n) output. 0 COMP0_1 The channel (n+1) output is the complement of the channel (n) output. 0x1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write DECAP0_0 The dual edge captures are inactive. 0 DECAP0_1 The dual edge captures are active. 0x1 DTEN0 Deadtime Enable For n = 0 4 1 read-write DTEN0_0 The deadtime insertion in this pair of channels is disabled. 0 DTEN0_1 The deadtime insertion in this pair of channels is enabled. 0x1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write SYNCEN0_0 The PWM synchronization in this pair of channels is disabled. 0 SYNCEN0_1 The PWM synchronization in this pair of channels is enabled. 0x1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write FAULTEN0_0 The fault control in this pair of channels is disabled. 0 FAULTEN0_1 The fault control in this pair of channels is enabled. 0x1 MCOMBINE0 Modified Combine Mode For n = 0 7 1 read-write COMBINE1 Combine Channels For n = 2 8 1 read-write COMP1 Complement Of Channel (n) For n = 2 9 1 read-write COMP1_0 If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the channel (n+1) output is independent from channel (n) output. 0 COMP1_1 The channel (n+1) output is the complement of the channel (n) output. 0x1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write DECAP1_0 The dual edge captures are inactive. 0 DECAP1_1 The dual edge captures are active. 0x1 DTEN1 Deadtime Enable For n = 2 12 1 read-write DTEN1_0 The deadtime insertion in this pair of channels is disabled. 0 DTEN1_1 The deadtime insertion in this pair of channels is enabled. 0x1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write SYNCEN1_0 The PWM synchronization in this pair of channels is disabled. 0 SYNCEN1_1 The PWM synchronization in this pair of channels is enabled. 0x1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write FAULTEN1_0 The fault control in this pair of channels is disabled. 0 FAULTEN1_1 The fault control in this pair of channels is enabled. 0x1 MCOMBINE1 Modified Combine Mode For n = 2 15 1 read-write COMBINE2 Combine Channels For n = 4 16 1 read-write COMP2 Complement Of Channel (n) For n = 4 17 1 read-write COMP2_0 If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the channel (n+1) output is independent from channel (n) output. 0 COMP2_1 The channel (n+1) output is the complement of the channel (n) output. 0x1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write DECAP2_0 The dual edge captures are inactive. 0 DECAP2_1 The dual edge captures are active. 0x1 DTEN2 Deadtime Enable For n = 4 20 1 read-write DTEN2_0 The deadtime insertion in this pair of channels is disabled. 0 DTEN2_1 The deadtime insertion in this pair of channels is enabled. 0x1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write SYNCEN2_0 The PWM synchronization in this pair of channels is disabled. 0 SYNCEN2_1 The PWM synchronization in this pair of channels is enabled. 0x1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write FAULTEN2_0 The fault control in this pair of channels is disabled. 0 FAULTEN2_1 The fault control in this pair of channels is enabled. 0x1 MCOMBINE2 Modified Combine Mode For n = 4 23 1 read-write COMBINE3 Combine Channels For n = 6 24 1 read-write COMP3 Complement Of Channel (n) for n = 6 25 1 read-write COMP3_0 If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the channel (n+1) output is independent from channel (n) output. 0 COMP3_1 The channel (n+1) output is the complement of the channel (n) output. 0x1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write DECAP3_0 The dual edge captures are inactive. 0 DECAP3_1 The dual edge captures are active. 0x1 DTEN3 Deadtime Enable For n = 6 28 1 read-write DTEN3_0 The deadtime insertion in this pair of channels is disabled. 0 DTEN3_1 The deadtime insertion in this pair of channels is enabled. 0x1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write SYNCEN3_0 The PWM synchronization in this pair of channels is disabled. 0 SYNCEN3_1 The PWM synchronization in this pair of channels is enabled. 0x1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write FAULTEN3_0 The fault control in this pair of channels is disabled. 0 FAULTEN3_1 The fault control in this pair of channels is enabled. 0x1 MCOMBINE3 Modified Combine Mode For n = 6 31 1 read-write DEADTIME Deadtime Configuration 0x68 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write DTPS_0 Divide the FTM input clock by 1. #0x DTPS_2 Divide the FTM input clock by 4. 0x2 DTPS_3 Divide the FTM input clock by 16. 0x3 DTVALEX Extended Deadtime Value 16 4 read-write EXTTRIG FTM External Trigger 0x6C 32 read-write 0 0xFFFFFFFF CH2TRIG Channel 2 External Trigger Enable 0 1 read-write CH2TRIG_0 The generation of this external trigger is disabled. 0 CH2TRIG_1 The generation of this external trigger is enabled. 0x1 CH3TRIG Channel 3 External Trigger Enable 1 1 read-write CH3TRIG_0 The generation of this external trigger is disabled. 0 CH3TRIG_1 The generation of this external trigger is enabled. 0x1 CH4TRIG Channel 4 External Trigger Enable 2 1 read-write CH4TRIG_0 The generation of this external trigger is disabled. 0 CH4TRIG_1 The generation of this external trigger is enabled. 0x1 CH5TRIG Channel 5 External Trigger Enable 3 1 read-write CH5TRIG_0 The generation of this external trigger is disabled. 0 CH5TRIG_1 The generation of this external trigger is enabled. 0x1 CH0TRIG Channel 0 External Trigger Enable 4 1 read-write CH0TRIG_0 The generation of this external trigger is disabled. 0 CH0TRIG_1 The generation of this external trigger is enabled. 0x1 CH1TRIG Channel 1 External Trigger Enable 5 1 read-write CH1TRIG_0 The generation of this external trigger is disabled. 0 CH1TRIG_1 The generation of this external trigger is enabled. 0x1 INITTRIGEN Initialization Trigger Enable 6 1 read-write INITTRIGEN_0 The generation of initialization trigger is disabled. 0 INITTRIGEN_1 The generation of initialization trigger is enabled. 0x1 TRIGF Channel Trigger Flag 7 1 read-write TRIGF_0 No channel trigger was generated. 0 TRIGF_1 A channel trigger was generated. 0x1 CH6TRIG Channel 6 External Trigger Enable 8 1 read-write CH6TRIG_0 The generation of this external trigger is disabled. 0 CH6TRIG_1 The generation of this external trigger is enabled. 0x1 CH7TRIG Channel 7 External Trigger Enable 9 1 read-write CH7TRIG_0 The generation of this external trigger is disabled. 0 CH7TRIG_1 The generation of this external trigger is enabled. 0x1 POL Channels Polarity 0x70 32 read-write 0 0xFFFFFFFF POL0 Channel 0 Polarity 0 1 read-write POL0_0 The channel polarity is active high. 0 POL0_1 The channel polarity is active low. 0x1 POL1 Channel 1 Polarity 1 1 read-write POL1_0 The channel polarity is active high. 0 POL1_1 The channel polarity is active low. 0x1 POL2 Channel 2 Polarity 2 1 read-write POL2_0 The channel polarity is active high. 0 POL2_1 The channel polarity is active low. 0x1 POL3 Channel 3 Polarity 3 1 read-write POL3_0 The channel polarity is active high. 0 POL3_1 The channel polarity is active low. 0x1 POL4 Channel 4 Polarity 4 1 read-write POL4_0 The channel polarity is active high. 0 POL4_1 The channel polarity is active low. 0x1 POL5 Channel 5 Polarity 5 1 read-write POL5_0 The channel polarity is active high. 0 POL5_1 The channel polarity is active low. 0x1 POL6 Channel 6 Polarity 6 1 read-write POL6_0 The channel polarity is active high. 0 POL6_1 The channel polarity is active low. 0x1 POL7 Channel 7 Polarity 7 1 read-write POL7_0 The channel polarity is active high. 0 POL7_1 The channel polarity is active low. 0x1 FMS Fault Mode Status 0x74 32 read-write 0 0xFFFFFFFF FAULTF0 Fault Detection Flag 0 0 1 read-write FAULTF0_0 No fault condition was detected at the fault input. 0 FAULTF0_1 A fault condition was detected at the fault input. 0x1 FAULTF1 Fault Detection Flag 1 1 1 read-write FAULTF1_0 No fault condition was detected at the fault input. 0 FAULTF1_1 A fault condition was detected at the fault input. 0x1 FAULTF2 Fault Detection Flag 2 2 1 read-write FAULTF2_0 No fault condition was detected at the fault input. 0 FAULTF2_1 A fault condition was detected at the fault input. 0x1 FAULTF3 Fault Detection Flag 3 3 1 read-write FAULTF3_0 No fault condition was detected at the fault input. 0 FAULTF3_1 A fault condition was detected at the fault input. 0x1 FAULTIN Fault Inputs 5 1 read-only FAULTIN_0 The logic OR of the enabled fault inputs is 0. 0 FAULTIN_1 The logic OR of the enabled fault inputs is 1. 0x1 WPEN Write Protection Enable 6 1 read-write WPEN_0 Write protection is disabled. Write protected bits can be written. 0 WPEN_1 Write protection is enabled. Write protected bits cannot be written. 0x1 FAULTF Fault Detection Flag 7 1 read-write FAULTF_0 No fault condition was detected. 0 FAULTF_1 A fault condition was detected. 0x1 FILTER Input Capture Filter Control 0x78 32 read-write 0 0xFFFFFFFF CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write 0 0xFFFFFFFF FAULT0EN Fault Input 0 Enable 0 1 read-write FAULT0EN_0 Fault input is disabled. 0 FAULT0EN_1 Fault input is enabled. 0x1 FAULT1EN Fault Input 1 Enable 1 1 read-write FAULT1EN_0 Fault input is disabled. 0 FAULT1EN_1 Fault input is enabled. 0x1 FAULT2EN Fault Input 2 Enable 2 1 read-write FAULT2EN_0 Fault input is disabled. 0 FAULT2EN_1 Fault input is enabled. 0x1 FAULT3EN Fault Input 3 Enable 3 1 read-write FAULT3EN_0 Fault input is disabled. 0 FAULT3EN_1 Fault input is enabled. 0x1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write FFLTR0EN_0 Fault input filter is disabled. 0 FFLTR0EN_1 Fault input filter is enabled. 0x1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write FFLTR1EN_0 Fault input filter is disabled. 0 FFLTR1EN_1 Fault input filter is enabled. 0x1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write FFLTR2EN_0 Fault input filter is disabled. 0 FFLTR2EN_1 Fault input filter is enabled. 0x1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write FFLTR3EN_0 Fault input filter is disabled. 0 FFLTR3EN_1 Fault input filter is enabled. 0x1 FFVAL Fault Input Filter 8 4 read-write FSTATE Fault output state 15 1 read-write FSTATE_0 FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits). 0 FSTATE_1 FTM outputs will be tri-stated when fault event is ongoing 0x1 QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write 0 0xFFFFFFFF QUADEN Quadrature Decoder Mode Enable 0 1 read-write QUADEN_0 Quadrature Decoder mode is disabled. 0 QUADEN_1 Quadrature Decoder mode is enabled. 0x1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only TOFDIR_0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). 0 TOFDIR_1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). 0x1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only QUADIR_0 Counting direction is decreasing (FTM counter decrement). 0 QUADIR_1 Counting direction is increasing (FTM counter increment). 0x1 QUADMODE Quadrature Decoder Mode 3 1 read-write QUADMODE_0 Phase A and phase B encoding mode. 0 QUADMODE_1 Count and direction encoding mode. 0x1 PHBPOL Phase B Input Polarity 4 1 read-write PHBPOL_0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. 0 PHBPOL_1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. 0x1 PHAPOL Phase A Input Polarity 5 1 read-write PHAPOL_0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. 0 PHAPOL_1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. 0x1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write PHBFLTREN_0 Phase B input filter is disabled. 0 PHBFLTREN_1 Phase B input filter is enabled. 0x1 PHAFLTREN Phase A Input Filter Enable 7 1 read-write PHAFLTREN_0 Phase A input filter is disabled. 0 PHAFLTREN_1 Phase A input filter is enabled. 0x1 CONF Configuration 0x84 32 read-write 0 0xFFFFFFFF LDFQ Frequency of the Reload Opportunities 0 5 read-write BDMMODE Debug Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write GTBEEN_0 Use of an external global time base is disabled. 0 GTBEEN_1 Use of an external global time base is enabled. 0x1 GTBEOUT Global Time Base Output 10 1 read-write GTBEOUT_0 A global time base signal generation is disabled. 0 GTBEOUT_1 A global time base signal generation is enabled. 0x1 ITRIGR Initialization trigger on Reload Point 11 1 read-write ITRIGR_0 Initialization trigger is generated on counter wrap events. 0 ITRIGR_1 Initialization trigger is generated when a reload point is reached. 0x1 FLTPOL FTM Fault Input Polarity 0x88 32 read-write 0 0xFFFFFFFF FLT0POL Fault Input 0 Polarity 0 1 read-write FLT0POL_0 The fault input polarity is active high. A 1 at the fault input indicates a fault. 0 FLT0POL_1 The fault input polarity is active low. A 0 at the fault input indicates a fault. 0x1 FLT1POL Fault Input 1 Polarity 1 1 read-write FLT1POL_0 The fault input polarity is active high. A 1 at the fault input indicates a fault. 0 FLT1POL_1 The fault input polarity is active low. A 0 at the fault input indicates a fault. 0x1 FLT2POL Fault Input 2 Polarity 2 1 read-write FLT2POL_0 The fault input polarity is active high. A 1 at the fault input indicates a fault. 0 FLT2POL_1 The fault input polarity is active low. A 0 at the fault input indicates a fault. 0x1 FLT3POL Fault Input 3 Polarity 3 1 read-write FLT3POL_0 The fault input polarity is active high. A 1 at the fault input indicates a fault. 0 FLT3POL_1 The fault input polarity is active low. A 0 at the fault input indicates a fault. 0x1 SYNCONF Synchronization Configuration 0x8C 32 read-write 0 0xFFFFFFFF HWTRIGMODE Hardware Trigger Mode 0 1 read-write HWTRIGMODE_0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 0 HWTRIGMODE_1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 0x1 CNTINC CNTIN Register Synchronization 2 1 read-write CNTINC_0 CNTIN register is updated with its buffer value at all rising edges of FTM input clock. 0 CNTINC_1 CNTIN register is updated with its buffer value by the PWM synchronization. 0x1 INVC INVCTRL Register Synchronization 4 1 read-write INVC_0 INVCTRL register is updated with its buffer value at all rising edges of FTM input clock. 0 INVC_1 INVCTRL register is updated with its buffer value by the PWM synchronization. 0x1 SWOC SWOCTRL Register Synchronization 5 1 read-write SWOC_0 SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock. 0 SWOC_1 SWOCTRL register is updated with its buffer value by the PWM synchronization. 0x1 SYNCMODE Synchronization Mode 7 1 read-write SYNCMODE_0 Legacy PWM synchronization is selected. 0 SYNCMODE_1 Enhanced PWM synchronization is selected. 0x1 SWRSTCNT FTM counter synchronization is activated by the software trigger 8 1 read-write SWRSTCNT_0 The software trigger does not activate the FTM counter synchronization. 0 SWRSTCNT_1 The software trigger activates the FTM counter synchronization. 0x1 SWWRBUF MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger 9 1 read-write SWWRBUF_0 The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. 0 SWWRBUF_1 The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization. 0x1 SWOM Output mask synchronization is activated by the software trigger 10 1 read-write SWOM_0 The software trigger does not activate the OUTMASK register synchronization. 0 SWOM_1 The software trigger activates the OUTMASK register synchronization. 0x1 SWINVC Inverting control synchronization is activated by the software trigger 11 1 read-write SWINVC_0 The software trigger does not activate the INVCTRL register synchronization. 0 SWINVC_1 The software trigger activates the INVCTRL register synchronization. 0x1 SWSOC Software output control synchronization is activated by the software trigger 12 1 read-write SWSOC_0 The software trigger does not activate the SWOCTRL register synchronization. 0 SWSOC_1 The software trigger activates the SWOCTRL register synchronization. 0x1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger 16 1 read-write HWRSTCNT_0 A hardware trigger does not activate the FTM counter synchronization. 0 HWRSTCNT_1 A hardware trigger activates the FTM counter synchronization. 0x1 HWWRBUF MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger 17 1 read-write HWWRBUF_0 A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. 0 HWWRBUF_1 A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization. 0x1 HWOM Output mask synchronization is activated by a hardware trigger 18 1 read-write HWOM_0 A hardware trigger does not activate the OUTMASK register synchronization. 0 HWOM_1 A hardware trigger activates the OUTMASK register synchronization. 0x1 HWINVC Inverting control synchronization is activated by a hardware trigger 19 1 read-write HWINVC_0 A hardware trigger does not activate the INVCTRL register synchronization. 0 HWINVC_1 A hardware trigger activates the INVCTRL register synchronization. 0x1 HWSOC Software output control synchronization is activated by a hardware trigger 20 1 read-write HWSOC_0 A hardware trigger does not activate the SWOCTRL register synchronization. 0 HWSOC_1 A hardware trigger activates the SWOCTRL register synchronization. 0x1 INVCTRL FTM Inverting Control 0x90 32 read-write 0 0xFFFFFFFF INV0EN Pair Channels 0 Inverting Enable 0 1 read-write INV0EN_0 Inverting is disabled. 0 INV0EN_1 Inverting is enabled. 0x1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write INV1EN_0 Inverting is disabled. 0 INV1EN_1 Inverting is enabled. 0x1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write INV2EN_0 Inverting is disabled. 0 INV2EN_1 Inverting is enabled. 0x1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write INV3EN_0 Inverting is disabled. 0 INV3EN_1 Inverting is enabled. 0x1 SWOCTRL FTM Software Output Control 0x94 32 read-write 0 0xFFFFFFFF CH0OC Channel 0 Software Output Control Enable 0 1 read-write CH0OC_0 The channel output is not affected by software output control. 0 CH0OC_1 The channel output is affected by software output control. 0x1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write CH1OC_0 The channel output is not affected by software output control. 0 CH1OC_1 The channel output is affected by software output control. 0x1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write CH2OC_0 The channel output is not affected by software output control. 0 CH2OC_1 The channel output is affected by software output control. 0x1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write CH3OC_0 The channel output is not affected by software output control. 0 CH3OC_1 The channel output is affected by software output control. 0x1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write CH4OC_0 The channel output is not affected by software output control. 0 CH4OC_1 The channel output is affected by software output control. 0x1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write CH5OC_0 The channel output is not affected by software output control. 0 CH5OC_1 The channel output is affected by software output control. 0x1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write CH6OC_0 The channel output is not affected by software output control. 0 CH6OC_1 The channel output is affected by software output control. 0x1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write CH7OC_0 The channel output is not affected by software output control. 0 CH7OC_1 The channel output is affected by software output control. 0x1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write CH0OCV_0 The software output control forces 0 to the channel output. 0 CH0OCV_1 The software output control forces 1 to the channel output. 0x1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write CH1OCV_0 The software output control forces 0 to the channel output. 0 CH1OCV_1 The software output control forces 1 to the channel output. 0x1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write CH2OCV_0 The software output control forces 0 to the channel output. 0 CH2OCV_1 The software output control forces 1 to the channel output. 0x1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write CH3OCV_0 The software output control forces 0 to the channel output. 0 CH3OCV_1 The software output control forces 1 to the channel output. 0x1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write CH4OCV_0 The software output control forces 0 to the channel output. 0 CH4OCV_1 The software output control forces 1 to the channel output. 0x1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write CH5OCV_0 The software output control forces 0 to the channel output. 0 CH5OCV_1 The software output control forces 1 to the channel output. 0x1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write CH6OCV_0 The software output control forces 0 to the channel output. 0 CH6OCV_1 The software output control forces 1 to the channel output. 0x1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write CH7OCV_0 The software output control forces 0 to the channel output. 0 CH7OCV_1 The software output control forces 1 to the channel output. 0x1 PWMLOAD FTM PWM Load 0x98 32 read-write 0 0xFFFFFFFF CH0SEL Channel 0 Select 0 1 read-write CH0SEL_0 Channel match is not included as a reload opportunity. 0 CH0SEL_1 Channel match is included as a reload opportunity. 0x1 CH1SEL Channel 1 Select 1 1 read-write CH1SEL_0 Channel match is not included as a reload opportunity. 0 CH1SEL_1 Channel match is included as a reload opportunity. 0x1 CH2SEL Channel 2 Select 2 1 read-write CH2SEL_0 Channel match is not included as a reload opportunity. 0 CH2SEL_1 Channel match is included as a reload opportunity. 0x1 CH3SEL Channel 3 Select 3 1 read-write CH3SEL_0 Channel match is not included as a reload opportunity. 0 CH3SEL_1 Channel match is included as a reload opportunity. 0x1 CH4SEL Channel 4 Select 4 1 read-write CH4SEL_0 Channel match is not included as a reload opportunity. 0 CH4SEL_1 Channel match is included as a reload opportunity. 0x1 CH5SEL Channel 5 Select 5 1 read-write CH5SEL_0 Channel match is not included as a reload opportunity. 0 CH5SEL_1 Channel match is included as a reload opportunity. 0x1 CH6SEL Channel 6 Select 6 1 read-write CH6SEL_0 Channel match is not included as a reload opportunity. 0 CH6SEL_1 Channel match is included as a reload opportunity. 0x1 CH7SEL Channel 7 Select 7 1 read-write CH7SEL_0 Channel match is not included as a reload opportunity. 0 CH7SEL_1 Channel match is included as a reload opportunity. 0x1 HCSEL Half Cycle Select 8 1 read-write HCSEL_0 Half cycle reload is disabled and it is not considered as a reload opportunity. 0 HCSEL_1 Half cycle reload is enabled and it is considered as a reload opportunity. 0x1 LDOK Load Enable 9 1 read-write LDOK_0 Loading updated values is disabled. 0 LDOK_1 Loading updated values is enabled. 0x1 GLEN Global Load Enable 10 1 read-write GLEN_0 Global Load Ok disabled. 0 GLEN_1 Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit. 0x1 GLDOK Global Load OK 11 1 read-write GLDOK_0 No action. 0 GLDOK_1 LDOK bit is set. 0x1 HCR Half Cycle Register 0x9C 32 read-write 0 0xFFFFFFFF HCVAL Half Cycle Value 0 16 read-write PAIR0DEADTIME Pair 0 Deadtime Configuration 0xA0 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write DTPS_0 Divide the FTM input clock by 1. #0x DTPS_2 Divide the FTM input clock by 4. 0x2 DTPS_3 Divide the FTM input clock by 16. 0x3 DTVALEX Extended Deadtime Value 16 4 read-write PAIR1DEADTIME Pair 1 Deadtime Configuration 0xA8 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write DTPS_0 Divide the FTM input clock by 1. #0x DTPS_2 Divide the FTM input clock by 4. 0x2 DTPS_3 Divide the FTM input clock by 16. 0x3 DTVALEX Extended Deadtime Value 16 4 read-write PAIR2DEADTIME Pair 2 Deadtime Configuration 0xB0 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write DTPS_0 Divide the FTM input clock by 1. #0x DTPS_2 Divide the FTM input clock by 4. 0x2 DTPS_3 Divide the FTM input clock by 16. 0x3 DTVALEX Extended Deadtime Value 16 4 read-write PAIR3DEADTIME Pair 3 Deadtime Configuration 0xB8 32 read-write 0 0xFFFFFFFF DTVAL Deadtime Value 0 6 read-write DTPS Deadtime Prescaler Value 6 2 read-write DTPS_0 Divide the FTM input clock by 1. #0x DTPS_2 Divide the FTM input clock by 4. 0x2 DTPS_3 Divide the FTM input clock by 16. 0x3 DTVALEX Extended Deadtime Value 16 4 read-write MOD_MIRROR Mirror of Modulo Value 0x200 32 read-write 0 0xFFFFFFFF FRACMOD Modulo Fractional Value 11 5 read-write MOD Mirror of the Modulo Integer Value 16 16 read-write 8 0x4 CV_MIRROR[%s] Mirror of Channel (n) Match Value 0x204 32 read-write 0 0xFFFFFFFF FRACVAL Channel (n) Match Fractional Value 11 5 read-write VAL Mirror of the Channel (n) Match Integer Value 16 16 read-write FTM2 FTM FTM 0x4003A000 0 0x224 registers ADC0 ADC ADC ADC 0x4003B000 0 0xEC registers 16 0x4 A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P SC1%s ADC Status and Control Register 1 0 32 read-write 0x1F 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 External channel 0 is selected as input. 0 ADCH_1 External channel 1 is selected as input. 0x1 ADCH_2 External channel 2 is selected as input. 0x2 ADCH_3 External channel 3 is selected as input. 0x3 ADCH_4 External channel 4 is selected as input. 0x4 ADCH_5 External channel 5 is selected as input. 0x5 ADCH_6 External channel 6 is selected as input. 0x6 ADCH_7 External channel 7 is selected as input. 0x7 ADCH_8 External channel 8 is selected as input. 0x8 ADCH_9 External channel 9 is selected as input. 0x9 ADCH_10 External channel 10 is selected as input. 0xA ADCH_11 External channel 11 is selected as input. 0xB ADCH_12 External channel 12 is selected as input. 0xC ADCH_13 External channel 13 is selected as input. 0xD ADCH_14 External channel 14 is selected as input. 0xE ADCH_15 External channel 15 is selected as input. 0xF ADCH_18 External channel 18 is selected as input. 0x12 ADCH_19 External channel 19 is selected as input. 0x13 ADCH_21 Internal channel 0 is selected as input. 0x15 ADCH_22 Internal channel 1 is selected as input. 0x16 ADCH_23 Internal channel 2 is selected as input. 0x17 ADCH_27 Band Gap 0x1B ADCH_28 Internal channel 3 is selected as input. 0x1C ADCH_29 VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 0x1D ADCH_30 VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 0x1E ADCH_31 Module is disabled 0x1F AIEN Interrupt Enable 6 1 read-write AIEN_0 Conversion complete interrupt is disabled. 0 AIEN_1 Conversion complete interrupt is enabled. 0x1 COCO Conversion Complete Flag 7 1 read-only COCO_0 Conversion is not complete. 0 COCO_1 Conversion is complete. 0x1 CFG1 ADC Configuration Register 1 0x40 32 read-write 0 0xFFFFFFFF ADICLK Input Clock Select 0 2 read-write ADICLK_0 Alternate clock 1 (ALTCLK1) 0 ADICLK_1 Alternate clock 2 (ALTCLK2) 0x1 ADICLK_2 Alternate clock 3 (ALTCLK3) 0x2 ADICLK_3 Alternate clock 4 (ALTCLK4) 0x3 MODE Conversion mode selection 2 2 read-write MODE_0 8-bit conversion. 0 MODE_1 12-bit conversion. 0x1 MODE_2 10-bit conversion. 0x2 ADIV Clock Divide Select 5 2 read-write ADIV_0 The divide ratio is 1 and the clock rate is input clock. 0 ADIV_1 The divide ratio is 2 and the clock rate is (input clock)/2. 0x1 ADIV_2 The divide ratio is 4 and the clock rate is (input clock)/4. 0x2 ADIV_3 The divide ratio is 8 and the clock rate is (input clock)/8. 0x3 CFG2 ADC Configuration Register 2 0x44 32 read-write 0xC 0xFFFFFFFF SMPLTS Sample Time Select 0 8 read-write 16 0x4 A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P R%s ADC Data Result Registers 0x48 32 read-only 0 0xFFFFFFFF D Data result 0 12 read-only 2 0x4 1,2 CV%s Compare Value Registers 0x88 32 read-write 0 0xFFFFFFFF CV Compare Value. 0 16 read-write SC2 Status and Control Register 2 0x90 32 read-write 0 0xFFFFFFFF REFSEL Voltage Reference Selection 0 2 read-write REFSEL_0 Default voltage reference pin pair, that is, external pins VREFH and VREFL 0 REFSEL_1 Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU. 0x1 DMAEN DMA Enable 2 1 read-write DMAEN_0 DMA is disabled. 0 DMAEN_1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted. 0x1 ACREN Compare Function Range Enable 3 1 read-write ACFGT Compare Function Greater Than Enable 4 1 read-write ACFE Compare Function Enable 5 1 read-write ACFE_0 Compare function disabled. 0 ACFE_1 Compare function enabled. 0x1 ADTRG Conversion Trigger Select 6 1 read-write ADTRG_0 Software trigger selected. 0 ADTRG_1 Hardware trigger selected. 0x1 ADACT Conversion Active 7 1 read-only ADACT_0 Conversion not in progress. 0 ADACT_1 Conversion in progress. 0x1 SC3 Status and Control Register 3 0x94 32 read-write 0 0xFFFFFFFF AVGS Hardware Average Select 0 2 read-write AVGS_0 4 samples averaged. 0 AVGS_1 8 samples averaged. 0x1 AVGS_2 16 samples averaged. 0x2 AVGS_3 32 samples averaged. 0x3 AVGE Hardware Average Enable 2 1 read-write AVGE_0 Hardware average function disabled. 0 AVGE_1 Hardware average function enabled. 0x1 ADCO Continuous Conversion Enable 3 1 read-write ADCO_0 One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated. 0 ADCO_1 Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated. 0x1 CAL Calibration 7 1 read-write BASE_OFS BASE Offset Register 0x98 32 read-write 0x40 0xFFFFFFFF BA_OFS Base Offset Error Correction Value 0 8 read-write OFS ADC Offset Correction Register 0x9C 32 read-write 0 0xFFFF0000 OFS Offset Error Correction Value 0 16 read-write USR_OFS USER Offset Correction Register 0xA0 32 read-write 0 0xFFFFFFFF USR_OFS USER Offset Error Correction Value 0 8 read-write XOFS ADC X Offset Correction Register 0xA4 32 read-write 0x30 0xFFFFFFFF XOFS X offset error correction value 0 6 read-write YOFS ADC Y Offset Correction Register 0xA8 32 read-write 0x37 0xFFFFFFFF YOFS Y offset error correction value 0 8 read-write G ADC Gain Register 0xAC 32 read-write 0 0xFFFFF800 G G 0 11 read-write UG ADC User Gain Register 0xB0 32 read-write 0x4 0xFFFFFFFF UG UG 0 10 read-write CLPS ADC General Calibration Value Register S 0xB4 32 read-write 0 0xFFFFFF80 CLPS CLPS 0 7 read-write CLP3 ADC Plus-Side General Calibration Value Register 3 0xB8 32 read-write 0 0xFFFFFC00 CLP3 CLP3 0 10 read-write CLP2 ADC Plus-Side General Calibration Value Register 2 0xBC 32 read-write 0 0xFFFFFC00 CLP2 CLP2 0 10 read-write CLP1 ADC Plus-Side General Calibration Value Register 1 0xC0 32 read-write 0 0xFFFFFE00 CLP1 CLP1 0 9 read-write CLP0 ADC Plus-Side General Calibration Value Register 0 0xC4 32 read-write 0 0xFFFFFF00 CLP0 CLP0 0 8 read-write CLPX ADC Plus-Side General Calibration Value Register X 0xC8 32 read-write 0 0xFFFFFF80 CLPX CLPX 0 7 read-write CLP9 ADC Plus-Side General Calibration Value Register 9 0xCC 32 read-write 0 0xFFFFFF80 CLP9 CLP9 0 7 read-write CLPS_OFS ADC General Calibration Offset Value Register S 0xD0 32 read-write 0 0xFFFFFFFF CLPS_OFS CLPS Offset 0 4 read-write CLP3_OFS ADC Plus-Side General Calibration Offset Value Register 3 0xD4 32 read-write 0 0xFFFFFFFF CLP3_OFS CLP3 Offset 0 4 read-write CLP2_OFS ADC Plus-Side General Calibration Offset Value Register 2 0xD8 32 read-write 0 0xFFFFFFFF CLP2_OFS CLP2 Offset 0 4 read-write CLP1_OFS ADC Plus-Side General Calibration Offset Value Register 1 0xDC 32 read-write 0 0xFFFFFFFF CLP1_OFS CLP1 Offset 0 4 read-write CLP0_OFS ADC Plus-Side General Calibration Offset Value Register 0 0xE0 32 read-write 0 0xFFFFFFFF CLP0_OFS CLP0 Offset 0 4 read-write CLPX_OFS ADC Plus-Side General Calibration Offset Value Register X 0xE4 32 read-write 0x440 0xFFFFFFFF CLPX_OFS CLPX Offset 0 12 read-write CLP9_OFS ADC Plus-Side General Calibration Offset Value Register 9 0xE8 32 read-write 0x240 0xFFFFFFFF CLP9_OFS CLP9 Offset 0 12 read-write ADC1 ADC ADC 0x40027000 0 0xEC registers RTC RTC RTC 0x4003D000 0 0x20 registers TSR RTC Time Seconds Register 0 32 read-write 0 0xFFFFFFFF TSR Time Seconds Register 0 32 read-write TPR RTC Time Prescaler Register 0x4 32 read-write 0 0xFFFFFFFF TPR Time Prescaler Register 0 16 read-write TAR RTC Time Alarm Register 0x8 32 read-write 0 0xFFFFFFFF TAR Time Alarm Register 0 32 read-write TCR RTC Time Compensation Register 0xC 32 read-write 0 0xFFFFFFFF TCR Time Compensation Register 0 8 read-write TCR_0 Time Prescaler Register overflows every 32768 clock cycles. 0 TCR_1 Time Prescaler Register overflows every 32767 clock cycles. 0x1 TCR_126 Time Prescaler Register overflows every 32642 clock cycles. 0x7E TCR_127 Time Prescaler Register overflows every 32641 clock cycles. 0x7F TCR_128 Time Prescaler Register overflows every 32896 clock cycles. 0x80 TCR_129 Time Prescaler Register overflows every 32895 clock cycles. 0x81 TCR_255 Time Prescaler Register overflows every 32769 clock cycles. 0xFF CIR Compensation Interval Register 8 8 read-write TCV Time Compensation Value 16 8 read-only CIC Compensation Interval Counter 24 8 read-only CR RTC Control Register 0x10 32 read-write 0 0xFFFFFFFF SWR Software Reset 0 1 read-write SWR_0 No effect. 0 SWR_1 Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. 0x1 SUP Supervisor Access 2 1 read-write SUP_0 Non-supervisor mode write accesses are not supported and generate a bus error. 0 SUP_1 Non-supervisor mode write accesses are supported. 0x1 UM Update Mode 3 1 read-write UM_0 Registers cannot be written when locked. 0 UM_1 Registers can be written when locked under limited conditions. 0x1 CPS Clock Pin Select 5 1 read-write CPS_0 The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT. 0 CPS_1 The RTC 32.768 kHz clock is output on RTC_CLKOUT, provided it is output to other peripherals. 0x1 LPOS LPO Select 7 1 read-write LPOS_0 RTC prescaler increments using 32.768 kHz clock. 0 LPOS_1 RTC prescaler increments using 1 kHz LPO, bits [4:0] of the prescaler are ignored. 0x1 CLKO Clock Output 9 1 read-write CLKO_0 The 32 kHz clock is output to other peripherals. 0 CLKO_1 The 32 kHz clock is not output to other peripherals. 0x1 CPE Clock Pin Enable 24 1 read-write CPE_0 The RTC_CLKOUT function is disabled. 0 CPE_1 Enable RTC_CLKOUT function. 0x1 SR RTC Status Register 0x14 32 read-write 0x1 0xFFFFFFFF TIF Time Invalid Flag 0 1 read-only TIF_0 Time is valid. 0 TIF_1 Time is invalid and time counter is read as zero. 0x1 TOF Time Overflow Flag 1 1 read-only TOF_0 Time overflow has not occurred. 0 TOF_1 Time overflow has occurred and time counter is read as zero. 0x1 TAF Time Alarm Flag 2 1 read-only TAF_0 Time alarm has not occurred. 0 TAF_1 Time alarm has occurred. 0x1 TCE Time Counter Enable 4 1 read-write TCE_0 Time counter is disabled. 0 TCE_1 Time counter is enabled. 0x1 LR RTC Lock Register 0x18 32 read-write 0xFF 0xFFFFFFFF TCL Time Compensation Lock 3 1 read-write TCL_0 Time Compensation Register is locked and writes are ignored. 0 TCL_1 Time Compensation Register is not locked and writes complete as normal. 0x1 CRL Control Register Lock 4 1 read-write CRL_0 Control Register is locked and writes are ignored. 0 CRL_1 Control Register is not locked and writes complete as normal. 0x1 SRL Status Register Lock 5 1 read-write SRL_0 Status Register is locked and writes are ignored. 0 SRL_1 Status Register is not locked and writes complete as normal. 0x1 LRL Lock Register Lock 6 1 read-write LRL_0 Lock Register is locked and writes are ignored. 0 LRL_1 Lock Register is not locked and writes complete as normal. 0x1 IER RTC Interrupt Enable Register 0x1C 32 read-write 0x7 0xFFFFFFFF TIIE Time Invalid Interrupt Enable 0 1 read-write TIIE_0 Time invalid flag does not generate an interrupt. 0 TIIE_1 Time invalid flag does generate an interrupt. 0x1 TOIE Time Overflow Interrupt Enable 1 1 read-write TOIE_0 Time overflow flag does not generate an interrupt. 0 TOIE_1 Time overflow flag does generate an interrupt. 0x1 TAIE Time Alarm Interrupt Enable 2 1 read-write TAIE_0 Time alarm flag does not generate an interrupt. 0 TAIE_1 Time alarm flag does generate an interrupt. 0x1 TSIE Time Seconds Interrupt Enable 4 1 read-write TSIE_0 Seconds interrupt is disabled. 0 TSIE_1 Seconds interrupt is enabled. 0x1 TSIC Timer Seconds Interrupt Configuration 16 3 read-write TSIC_0 1 Hz. 0 TSIC_1 2 Hz. 0x1 TSIC_2 4 Hz. 0x2 TSIC_3 8 Hz. 0x3 TSIC_4 16 Hz. 0x4 TSIC_5 32 Hz. 0x5 TSIC_6 64 Hz. 0x6 TSIC_7 128 Hz. 0x7 LPTMR0 LPTMR LPTMR 0x40040000 0 0x10 registers CSR Low Power Timer Control Status Register 0 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write TEN_0 LPTMR is disabled and internal logic is reset. 0 TEN_1 LPTMR is enabled. 0x1 TMS Timer Mode Select 1 1 read-write TMS_0 Time Counter mode. 0 TMS_1 Pulse Counter mode. 0x1 TFC Timer Free-Running Counter 2 1 read-write TFC_0 CNR is reset whenever TCF is set. 0 TFC_1 CNR is reset on overflow. 0x1 TPP Timer Pin Polarity 3 1 read-write TPP_0 Pulse Counter input source is active-high, and the CNR increments on the rising-edge. 0 TPP_1 Pulse Counter input source is active-low, and the CNR increments on the falling-edge. 0x1 TPS Timer Pin Select 4 2 read-write TPS_0 Pulse counter input 0 is selected. 0 TPS_1 Pulse counter input 1 is selected. 0x1 TPS_2 Pulse counter input 2 is selected. 0x2 TPS_3 Pulse counter input 3 is selected. 0x3 TIE Timer Interrupt Enable 6 1 read-write TIE_0 Timer interrupt disabled. 0 TIE_1 Timer interrupt enabled. 0x1 TCF Timer Compare Flag 7 1 read-write oneToClear TCF_0 The value of CNR is not equal to CMR and increments. 0 TCF_1 The value of CNR is equal to CMR and increments. 0x1 TDRE Timer DMA Request Enable 8 1 read-write TDRE_0 Timer DMA Request disabled. 0 TDRE_1 Timer DMA Request enabled. 0x1 PSR Low Power Timer Prescale Register 0x4 32 read-write 0 0xFFFFFFFF PCS Prescaler Clock Select 0 2 read-write PCS_0 Prescaler/glitch filter clock 0 selected. 0 PCS_1 Prescaler/glitch filter clock 1 selected. 0x1 PCS_2 Prescaler/glitch filter clock 2 selected. 0x2 PCS_3 Prescaler/glitch filter clock 3 selected. 0x3 PBYP Prescaler Bypass 2 1 read-write PBYP_0 Prescaler/glitch filter is enabled. 0 PBYP_1 Prescaler/glitch filter is bypassed. 0x1 PRESCALE Prescale Value 3 4 read-write PRESCALE_0 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. 0 PRESCALE_1 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. 0x1 PRESCALE_2 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. 0x2 PRESCALE_3 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. 0x3 PRESCALE_4 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. 0x4 PRESCALE_5 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. 0x5 PRESCALE_6 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. 0x6 PRESCALE_7 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. 0x7 PRESCALE_8 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. 0x8 PRESCALE_9 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. 0x9 PRESCALE_10 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. 0xA PRESCALE_11 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. 0xB PRESCALE_12 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. 0xC PRESCALE_13 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. 0xD PRESCALE_14 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. 0xE PRESCALE_15 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. 0xF CMR Low Power Timer Compare Register 0x8 32 read-write 0 0xFFFFFFFF COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write 0 0xFFFFFFFF COUNTER Counter Value 0 16 read-write SIM SIM SIM 0x40048000 0 0x70 registers CHIPCTL Chip Control register 0x4 32 read-write 0x300000 0xFFFFFFFF ADC_INTERLEAVE_EN ADC interleave channel enable 0 4 read-write ADC_INTERLEAVE_EN_0 Interleaving disabled. No channel pair interleaved. Interleaved channels are individually connected to pins. PTC0 is connected to ADC0_SE8. PTC1 is connected to ADC0_SE9. PTB15 is connected to ADC1_SE14. PTB16 is connected to ADC1_SE15. PTB0 is connected to ADC0_SE4. PTB1 is connected to ADC0_SE5. PTB13 is connected to ADC1_SE8. PTB14 is connected to ADC1_SE9. 0 ADC_INTERLEAVE_EN_8 PTB14 to ADC1_SE9 and ADC0_SE9 #1xxx CLKOUTSEL CLKOUT Select 4 4 read-write CLKOUTSEL_0 SCG CLKOUT 0 CLKOUTSEL_2 SOSC DIV2 CLK 0x2 CLKOUTSEL_4 SIRC DIV2 CLK 0x4 CLKOUTSEL_5 For S32K148: QSPI_SFIF_CLK_HYP_PREMUX: Divide by 2 clock (configured through SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI; For others: Reserved 0x5 CLKOUTSEL_6 FIRC DIV2 CLK 0x6 CLKOUTSEL_7 HCLK 0x7 CLKOUTSEL_8 For S32K14x: SPLL DIV2 CLK For S32K11x: Reserved 0x8 CLKOUTSEL_9 BUS_CLK 0x9 CLKOUTSEL_10 LPO128K_CLK 0xA CLKOUTSEL_11 For S32K148: QSPI_Module clock; For others: Reserved 0xB CLKOUTSEL_12 LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL] 0xC CLKOUTSEL_13 For S32K148: QSPI_SFIF_CLK; For others: Reserved 0xD CLKOUTSEL_14 RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL] 0xE CLKOUTSEL_15 For S32K148: QSPI_2xSFIF_CLK; For others: Reserved 0xF CLKOUTDIV CLKOUT Divide Ratio 8 3 read-write CLKOUTDIV_0 Divide by 1 0 CLKOUTDIV_1 Divide by 2 0x1 CLKOUTDIV_2 Divide by 3 0x2 CLKOUTDIV_3 Divide by 4 0x3 CLKOUTDIV_4 Divide by 5 0x4 CLKOUTDIV_5 Divide by 6 0x5 CLKOUTDIV_6 Divide by 7 0x6 CLKOUTDIV_7 Divide by 8 0x7 CLKOUTEN CLKOUT enable 11 1 read-write CLKOUTEN_0 Clockout disable 0 CLKOUTEN_1 Clockout enable 0x1 TRACECLK_SEL Debug trace clock select 12 1 read-write TRACECLK_SEL_0 Core clock 0 PDB_BB_SEL PDB back-to-back select 13 1 read-write PDB_BB_SEL_0 PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-back operation with ADC1 COCO[7:0] 0 PDB_BB_SEL_1 Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1. 0x1 ADC_SUPPLY ADC_SUPPLY 16 3 read-write ADC_SUPPLY_0 5 V input VDD supply (VDD) 0 ADC_SUPPLY_1 5 V input analog supply (VDDA) 0x1 ADC_SUPPLY_2 ADC Reference Supply (VREFH) 0x2 ADC_SUPPLY_3 3.3 V Oscillator Regulator Output (VDD_3V) 0x3 ADC_SUPPLY_4 3.3 V flash regulator output (VDD_flash_3V) 0x4 ADC_SUPPLY_5 1.2 V core regulator output (VDD_LV) 0x5 ADC_SUPPLYEN ADC_SUPPLYEN 19 1 read-write ADC_SUPPLYEN_0 Disable internal supply monitoring 0 ADC_SUPPLYEN_1 Enable internal supply monitoring 0x1 SRAMU_RETEN SRAMU_RETEN 20 1 read-write SRAMU_RETEN_0 SRAMU contents are retained across resets 0 SRAMU_RETEN_1 No SRAMU retention 0x1 SRAML_RETEN SRAML_RETEN 21 1 read-write SRAML_RETEN_0 SRAML contents are retained across resets 0 SRAML_RETEN_1 No SRAML retention 0x1 PDB_BB_SEL_1 PDB back-to-back select 1 22 1 read-write PDB_BB_SEL_2 PDB back-to-back select 2 23 1 read-write FTMOPT0 FTM Option Register 0 0xC 32 read-write 0 0xFFFFFFFF FTM0FLTxSEL FTM0 Fault X Select 0 3 read-write FTM0FLTxSEL_0 FTM0_FLTx pin 0 FTM0FLTxSEL_1 TRGMUX_FTM0 out 0x1 FTM1FLTxSEL FTM1 Fault X Select 4 3 read-write FTM1FLTxSEL_0 FTM1_FLTx pin 0 FTM1FLTxSEL_1 TRGMUX_FTM1 out 0x1 FTM2FLTxSEL FTM2 Fault X Select 8 3 read-write FTM2FLTxSEL_0 FTM2_FLTx pin 0 FTM2FLTxSEL_1 TRGMUX_FTM2 out 0x1 FTM3FLTxSEL FTM3 Fault X Select 12 3 read-write FTM3FLTxSEL_0 FTM3_FLTx pin 0 FTM3FLTxSEL_1 TRGMUX_FTM3 out 0x1 FTM0CLKSEL FTM0 External Clock Pin Select 24 2 read-write FTM0CLKSEL_0 FTM0 external clock driven by TCLK0 pin. 0 FTM0CLKSEL_1 FTM0 external clock driven by TCLK1 pin. 0x1 FTM0CLKSEL_2 FTM0 external clock driven by TCLK2 pin. 0x2 FTM0CLKSEL_3 No clock input 0x3 FTM1CLKSEL FTM1 External Clock Pin Select 26 2 read-write FTM1CLKSEL_0 FTM1 external clock driven by TCLK0 pin. 0 FTM1CLKSEL_1 FTM1 external clock driven by TCLK1 pin. 0x1 FTM1CLKSEL_2 FTM1 external clock driven by TCLK2 pin. 0x2 FTM1CLKSEL_3 No clock input 0x3 FTM2CLKSEL FTM2 External Clock Pin Select 28 2 read-write FTM2CLKSEL_0 FTM2 external clock driven by TCLK0 pin. 0 FTM2CLKSEL_1 FTM2 external clock driven by TCLK1 pin. 0x1 FTM2CLKSEL_2 FTM2 external clock driven by TCLK2 pin. 0x2 FTM2CLKSEL_3 No clock input 0x3 FTM3CLKSEL FTM3 External Clock Pin Select 30 2 read-write FTM3CLKSEL_0 FTM3 external clock driven by TCLK0 pin. 0 FTM3CLKSEL_1 FTM3 external clock driven by TCLK1 pin. 0x1 FTM3CLKSEL_2 FTM3 external clock driven by TCLK2 pin. 0x2 FTM3CLKSEL_3 No clock input 0x3 LPOCLKS LPO Clock Select Register 0x10 32 read-write 0x3 0xFFFFFFFF LPO1KCLKEN 1 kHz LPO_CLK enable 0 1 read-write LPO1KCLKEN_0 Disable 1 kHz LPO_CLK output 0 LPO1KCLKEN_1 Enable 1 kHz LPO_CLK output 0x1 LPO32KCLKEN 32 kHz LPO_CLK enable 1 1 read-write LPO32KCLKEN_0 Disable 32 kHz LPO_CLK output 0 LPO32KCLKEN_1 Enable 32 kHz LPO_CLK output 0x1 LPOCLKSEL LPO clock source select 2 2 read-write LPOCLKSEL_0 128 kHz LPO_CLK 0 LPOCLKSEL_1 No clock 0x1 LPOCLKSEL_2 32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK 0x2 LPOCLKSEL_3 1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK 0x3 RTCCLKSEL 32 kHz clock source select 4 2 read-write RTCCLKSEL_0 SOSCDIV1_CLK 0 RTCCLKSEL_1 32 kHz LPO_CLK 0x1 RTCCLKSEL_2 32 kHz RTC_CLKIN clock 0x2 RTCCLKSEL_3 FIRCDIV1_CLK 0x3 ADCOPT ADC Options Register 0x18 32 read-write 0 0xFFFFFFFF ADC0TRGSEL ADC0 trigger source select 0 1 read-write ADC0TRGSEL_0 PDB output 0 ADC0TRGSEL_1 TRGMUX output 0x1 ADC0SWPRETRG ADC0 software pretrigger sources 1 3 read-write ADC0SWPRETRG_0 Software pretrigger disabled 0 ADC0SWPRETRG_4 Software pretrigger 0 0x4 ADC0SWPRETRG_5 Software pretrigger 1 0x5 ADC0SWPRETRG_6 Software pretrigger 2 0x6 ADC0SWPRETRG_7 Software pretrigger 3 0x7 ADC0PRETRGSEL ADC0 pretrigger source select 4 2 read-write ADC0PRETRGSEL_0 PDB pretrigger (default) 0 ADC0PRETRGSEL_1 TRGMUX pretrigger 0x1 ADC0PRETRGSEL_2 Software pretrigger 0x2 ADC1TRGSEL ADC1 trigger source select 8 1 read-write ADC1TRGSEL_0 PDB output 0 ADC1TRGSEL_1 TRGMUX output 0x1 ADC1SWPRETRG ADC1 software pretrigger sources 9 3 read-write ADC1SWPRETRG_0 Software pretrigger disabled 0 ADC1SWPRETRG_4 Software pretrigger 0 0x4 ADC1SWPRETRG_5 Software pretrigger 1 0x5 ADC1SWPRETRG_6 Software pretrigger 2 0x6 ADC1SWPRETRG_7 Software pretrigger 3 0x7 ADC1PRETRGSEL ADC1 pretrigger source select 12 2 read-write ADC1PRETRGSEL_0 PDB pretrigger (default) 0 ADC1PRETRGSEL_1 TRGMUX pretrigger 0x1 ADC1PRETRGSEL_2 Software pretrigger 0x2 FTMOPT1 FTM Option Register 1 0x1C 32 read-write 0 0xFFFFFFFF FTM0SYNCBIT FTM0 Sync Bit 0 1 read-write FTM1SYNCBIT FTM1 Sync Bit 1 1 read-write FTM2SYNCBIT FTM2 Sync Bit 2 1 read-write FTM3SYNCBIT FTM3 Sync Bit 3 1 read-write FTM1CH0SEL FTM1 CH0 Select 4 2 read-write FTM1CH0SEL_0 FTM1_CH0 input 0 FTM1CH0SEL_1 CMP0 output 0x1 FTM2CH0SEL FTM2 CH0 Select 6 2 read-write FTM2CH0SEL_0 FTM2_CH0 input 0 FTM2CH0SEL_1 CMP0 output 0x1 FTM2CH1SEL FTM2 CH1 Select 8 1 read-write FTM2CH1SEL_0 FTM2_CH1 input 0 FTM2CH1SEL_1 exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1 0x1 FTMGLDOK FTM global load enable 15 1 read-write FTMGLDOK_0 FTM Global load mechanism disabled. 0 FTMGLDOK_1 FTM Global load mechanism enabled 0x1 FTM0_OUTSEL FTM0 channel modulation select with FTM1_CH1 16 8 read-write FTM0_OUTSEL_0 No modulation with FTM1_CH1 0 FTM0_OUTSEL_1 Modulation with FTM1_CH1 0x1 FTM3_OUTSEL FTM3 channel modulation select with FTM2_CH1 24 8 read-write FTM3_OUTSEL_0 No modulation with FTM2_CH1 0 FTM3_OUTSEL_1 Modulation with FTM2_CH1 0x1 MISCTRL0 Miscellaneous control register 0 0x20 32 read-write 0 0xFFFFFFFF STOP1_MONITOR STOP1 monitor bit 9 1 read-write oneToClear STOP1_MONITOR_0 Bus clock enabled or STOP1 entry aborted 0 STOP1_MONITOR_1 STOP1 entry successful 0x1 STOP2_MONITOR STOP2 monitor bit 10 1 read-write oneToClear STOP2_MONITOR_0 System clock enabled or STOP2 entry aborted 0 STOP2_MONITOR_1 STOP2 entry successful 0x1 ECC_EEERAM_STAT ECC double-bit fault detected during MGATE access to FlexRAM or PRAM 11 1 read-write oneToClear ECC_MGRAM_STAT ECC double-bit fault detected during MGATE access to Flash firmware or MGRAM 12 1 read-write oneToClear FTM0_OBE_CTRL FTM0 OBE CTRL bit 16 1 read-write FTM0_OBE_CTRL_0 The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated. 0 FTM0_OBE_CTRL_1 The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]. 0x1 FTM1_OBE_CTRL FTM1 OBE CTRL bit 17 1 read-write FTM1_OBE_CTRL_0 The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated. 0 FTM1_OBE_CTRL_1 The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]. 0x1 FTM2_OBE_CTRL FTM2 OBE CTRL bit 18 1 read-write FTM2_OBE_CTRL_0 The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated. 0 FTM2_OBE_CTRL_1 The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]. 0x1 FTM3_OBE_CTRL FTM3 OBE CTRL bit 19 1 read-write FTM3_OBE_CTRL_0 The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated. 0 FTM3_OBE_CTRL_1 The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]. 0x1 SDID System Device Identification Register 0x24 32 read-only 0 0 FEATURES Features 0 8 read-only PACKAGE Package 8 4 read-only PACKAGE_2 48 LQFP 0x2 PACKAGE_3 64 LQFP 0x3 PACKAGE_4 100 LQFP 0x4 PACKAGE_6 144 LQFP 0x6 PACKAGE_7 176 LQFP 0x7 PACKAGE_8 100 MAP BGA 0x8 REVID Device revision number 12 4 read-only RAMSIZE RAM size 16 4 read-only RAMSIZE_11 192 KB (S32K148), 96 KB (S32K146), Reserved (others) 0xB RAMSIZE_13 48 KB (S32K144), Reserved (others) 0xD RAMSIZE_15 256 KB (S32K148), 128 KB (S32K146), 64 KB (S32K144), 32 KB (S32K142), 25 KB (S32K118), 17 KB (S32K116) 0xF DERIVATE Derivate 20 4 read-only SUBSERIES Subseries 24 4 read-only GENERATION S32K product series generation 28 4 read-only PLATCGC Platform Clock Gating Control Register 0x40 32 read-write 0x1F 0xFFFFFFFF CGCMSCM MSCM Clock Gating Control 0 1 read-write CGCMSCM_0 Clock disabled 0 CGCMSCM_1 Clock enabled 0x1 CGCMPU MPU Clock Gating Control 1 1 read-write CGCMPU_0 Clock disabled 0 CGCMPU_1 Clock enabled 0x1 CGCDMA DMA Clock Gating Control 2 1 read-write CGCDMA_0 Clock disabled 0 CGCDMA_1 Clock enabled 0x1 CGCERM ERM Clock Gating Control 3 1 read-write CGCERM_0 Clock disabled 0 CGCERM_1 Clock enabled 0x1 CGCEIM EIM Clock Gating Control 4 1 read-write CGCEIM_0 Clock disabled 0 CGCEIM_1 Clock enabled 0x1 FCFG1 Flash Configuration Register 1 0x4C 32 read-write 0 0 DEPART FlexNVM partition 12 4 read-only EEERAMSIZE EEE SRAM SIZE 16 4 read-only EEERAMSIZE_2 4 KB 0x2 EEERAMSIZE_3 2 KB 0x3 EEERAMSIZE_4 1 KB 0x4 EEERAMSIZE_5 512 Bytes 0x5 EEERAMSIZE_6 256 Bytes 0x6 EEERAMSIZE_7 128 Bytes 0x7 EEERAMSIZE_8 64 Bytes 0x8 EEERAMSIZE_9 32 Bytes 0x9 EEERAMSIZE_15 0 Bytes 0xF UIDH Unique Identification Register High 0x54 32 read-only 0 0 UID127_96 Unique Identification 0 32 read-only UIDMH Unique Identification Register Mid-High 0x58 32 read-only 0 0 UID95_64 Unique Identification 0 32 read-only UIDML Unique Identification Register Mid Low 0x5C 32 read-only 0 0 UID63_32 Unique Identification 0 32 read-only UIDL Unique Identification Register Low 0x60 32 read-only 0 0 UID31_0 Unique Identification 0 32 read-only CLKDIV4 System Clock Divider Register 4 0x68 32 read-write 0x10000000 0xFFFFFFFF TRACEFRAC Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear TRACEDIVEN to disable the trace clock divide function. 0 1 read-write TRACEDIV Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it after setting TRACEDIV. 1 3 read-write TRACEDIVEN Debug Trace Divider control 28 1 read-write TRACEDIVEN_0 Debug trace divider disabled 0 TRACEDIVEN_1 Debug trace divider enabled 0x1 MISCTRL1 Miscellaneous Control register 1 0x6C 32 read-write 0 0xFFFFFFFF SW_TRG Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity). 0 1 read-write PORTA Pin Control and Interrupts PORT PORTA_ PORT 0x40049000 0 0xCC registers 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 PCR%s Pin Control Register n 0 32 read-write 0 0xFFFFFFFF PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 PE Pull Enable 1 1 read-write PE_0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. 0 PE_1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. 0x1 PFE Passive Filter Enable 4 1 read-write PFE_0 Passive input filter is disabled on the corresponding pin. 0 PFE_1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. 0x1 DSE Drive Strength Enable 6 1 read-write DSE_0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0 DSE_1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 LK Lock Register 15 1 read-write LK_0 Pin Control Register fields [15:0] are not locked. 0 LK_1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. 0x1 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. 0x1 GPCLR Global Pin Control Low Register 0x80 32 read-write 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 read-write GPWE Global Pin Write Enable 16 16 read-write GPWE_0 Corresponding Pin Control Register is not updated with the value in GPWD. 0 GPWE_1 Corresponding Pin Control Register is updated with the value in GPWD. 0x1 GPCHR Global Pin Control High Register 0x84 32 read-write 0 0xFFFFFFFF GPWD Global Pin Write Data 0 16 read-write GPWE Global Pin Write Enable 16 16 read-write GPWE_0 Corresponding Pin Control Register is not updated with the value in GPWD. 0 GPWE_1 Corresponding Pin Control Register is updated with the value in GPWD. 0x1 GICLR Global Interrupt Control Low Register 0x88 32 read-write 0 0xFFFFFFFF GIWE Global Interrupt Write Enable 0 16 read-write GIWE_0 Corresponding Pin Control Register is not updated with the value in GPWD. 0 GIWE_1 Corresponding Pin Control Register is updated with the value in GPWD. 0x1 GIWD Global Interrupt Write Data 16 16 read-write GICHR Global Interrupt Control High Register 0x8C 32 read-write 0 0xFFFFFFFF GIWE Global Interrupt Write Enable 0 16 read-write GIWE_0 Corresponding Pin Control Register is not updated with the value in GPWD. 0 GIWE_1 Corresponding Pin Control Register is updated with the value in GPWD. 0x1 GIWD Global Interrupt Write Data 16 16 read-write ISFR Interrupt Status Flag Register 0xA0 32 read-write 0 0xFFFFFFFF ISF Interrupt Status Flag 0 32 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. 0x1 DFER Digital Filter Enable Register 0xC0 32 read-write 0 0xFFFFFFFF DFE Digital Filter Enable 0 32 read-write DFE_0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. 0 DFE_1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. 0x1 DFCR Digital Filter Clock Register 0xC4 32 read-write 0 0xFFFFFFFF CS Clock Source 0 1 read-write CS_0 Digital filters are clocked by the bus clock. 0 CS_1 Digital filters are clocked by the LPO clock. 0x1 DFWR Digital Filter Width Register 0xC8 32 read-write 0 0xFFFFFFFF FILT Filter Length 0 5 read-write PORTB Pin Control and Interrupts PORT PORTB_ 0x4004A000 0 0xCC registers PORTC Pin Control and Interrupts PORT PORTC_ 0x4004B000 0 0xCC registers PORTD Pin Control and Interrupts PORT PORTD_ 0x4004C000 0 0xCC registers PORTE Pin Control and Interrupts PORT PORTE_ 0x4004D000 0 0xCC registers WDOG WDOG WDOG 0x40052000 0 0x10 registers CS Watchdog Control and Status Register 0 32 read-write 0x2980 0xFFFFFFFF STOP Stop Enable 0 1 read-write STOP_0 Watchdog disabled in chip stop mode. 0 STOP_1 Watchdog enabled in chip stop mode. 0x1 WAIT Wait Enable 1 1 read-write WAIT_0 Watchdog disabled in chip wait mode. 0 WAIT_1 Watchdog enabled in chip wait mode. 0x1 DBG Debug Enable 2 1 read-write DBG_0 Watchdog disabled in chip debug mode. 0 DBG_1 Watchdog enabled in chip debug mode. 0x1 TST Watchdog Test 3 2 read-write TST_0 Watchdog test mode disabled. 0 TST_1 Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. 0x1 TST_2 Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. 0x2 TST_3 Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. 0x3 UPDATE Allow updates 5 1 read-write UPDATE_0 Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. 0 UPDATE_1 Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. 0x1 INT Watchdog Interrupt 6 1 read-write INT_0 Watchdog interrupts are disabled. Watchdog resets are not delayed. 0 INT_1 Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. 0x1 EN Watchdog Enable 7 1 read-write EN_0 Watchdog disabled. 0 EN_1 Watchdog enabled. 0x1 CLK Watchdog Clock 8 2 read-write RCS Reconfiguration Success 10 1 read-only RCS_0 Reconfiguring WDOG. 0 RCS_1 Reconfiguration is successful. 0x1 ULK Unlock status 11 1 read-only ULK_0 WDOG is locked. 0 ULK_1 WDOG is unlocked. 0x1 PRES Watchdog prescaler 12 1 read-write PRES_0 256 prescaler disabled. 0 PRES_1 256 prescaler enabled. 0x1 CMD32EN Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words 13 1 read-write CMD32EN_0 Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. 0 CMD32EN_1 Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. 0x1 FLG Watchdog Interrupt Flag 14 1 read-write oneToClear FLG_0 No interrupt occurred. 0 FLG_1 An interrupt occurred. 0x1 WIN Watchdog Window 15 1 read-write WIN_0 Window mode disabled. 0 WIN_1 Window mode enabled. 0x1 CNT Watchdog Counter Register 0x4 32 read-write 0 0xFFFFFFFF CNTLOW Low byte of the Watchdog Counter 0 8 read-write CNTHIGH High byte of the Watchdog Counter 8 8 read-write TOVAL Watchdog Timeout Value Register 0x8 32 read-write 0x400 0xFFFFFFFF TOVALLOW Low byte of the timeout value 0 8 read-write TOVALHIGH High byte of the timeout value 8 8 read-write WIN Watchdog Window Register 0xC 32 read-write 0 0xFFFFFFFF WINLOW Low byte of Watchdog Window 0 8 read-write WINHIGH High byte of Watchdog Window 8 8 read-write FLEXIO FLEXIO FLEXIO 0x4005A000 0 0x510 registers VERID Version ID Register 0 32 read-only 0x1010000 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only FEATURE_0 Standard features implemented. 0 FEATURE_1 Supports state, logic and parallel modes. 0x1 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x4080404 0xFFFFFFFF SHIFTER Shifter Number 0 8 read-only TIMER Timer Number 8 8 read-only PIN Pin Number 16 8 read-only TRIGGER Trigger Number 24 8 read-only CTRL FlexIO Control Register 0x8 32 read-write 0 0xFFFFFFFF FLEXEN FlexIO Enable 0 1 read-write FLEXEN_0 FlexIO module is disabled. 0 FLEXEN_1 FlexIO module is enabled. 0x1 SWRST Software Reset 1 1 read-write SWRST_0 Software reset is disabled 0 SWRST_1 Software reset is enabled, all FlexIO registers except the Control Register are reset. 0x1 FASTACC Fast Access 2 1 read-write FASTACC_0 Configures for normal register accesses to FlexIO 0 FASTACC_1 Configures for fast register accesses to FlexIO 0x1 DBGE Debug Enable 30 1 read-write DBGE_0 FlexIO is disabled in debug modes. 0 DBGE_1 FlexIO is enabled in debug modes 0x1 DOZEN Doze Enable 31 1 read-write DOZEN_0 FlexIO enabled in Doze modes. 0 DOZEN_1 FlexIO disabled in Doze modes. 0x1 PIN Pin State Register 0xC 32 read-only 0 0xFFFFFFFF PDI Pin Data Input 0 8 read-only SHIFTSTAT Shifter Status Register 0x10 32 read-write 0 0xFFFFFFFF SSF Shifter Status Flag 0 4 read-write oneToClear SHIFTERR Shifter Error Register 0x14 32 read-write 0 0xFFFFFFFF SEF Shifter Error Flags 0 4 read-write oneToClear TIMSTAT Timer Status Register 0x18 32 read-write 0 0xFFFFFFFF TSF Timer Status Flags 0 4 read-write oneToClear SHIFTSIEN Shifter Status Interrupt Enable 0x20 32 read-write 0 0xFFFFFFFF SSIE Shifter Status Interrupt Enable 0 4 read-write SHIFTEIEN Shifter Error Interrupt Enable 0x24 32 read-write 0 0xFFFFFFFF SEIE Shifter Error Interrupt Enable 0 4 read-write TIMIEN Timer Interrupt Enable Register 0x28 32 read-write 0 0xFFFFFFFF TEIE Timer Status Interrupt Enable 0 4 read-write SHIFTSDEN Shifter Status DMA Enable 0x30 32 read-write 0 0xFFFFFFFF SSDE Shifter Status DMA Enable 0 4 read-write 4 0x4 SHIFTCTL[%s] Shifter Control N Register 0x80 32 read-write 0 0xFFFFFFFF SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 3 read-write PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 2 read-write 4 0x4 SHIFTCFG[%s] Shifter Configuration N Register 0x100 32 read-write 0 0xFFFFFFFF SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 4 0x4 SHIFTBUF[%s] Shifter Buffer N Register 0x200 32 read-write 0 0xFFFFFFFF SHIFTBUF Shift Buffer 0 32 read-write 4 0x4 SHIFTBUFBIS[%s] Shifter Buffer N Bit Swapped Register 0x280 32 read-write 0 0xFFFFFFFF SHIFTBUFBIS Shift Buffer 0 32 read-write 4 0x4 SHIFTBUFBYS[%s] Shifter Buffer N Byte Swapped Register 0x300 32 read-write 0 0xFFFFFFFF SHIFTBUFBYS Shift Buffer 0 32 read-write 4 0x4 SHIFTBUFBBS[%s] Shifter Buffer N Bit Byte Swapped Register 0x380 32 read-write 0 0xFFFFFFFF SHIFTBUFBBS Shift Buffer 0 32 read-write 4 0x4 TIMCTL[%s] Timer Control N Register 0x400 32 read-write 0 0xFFFFFFFF TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 3 read-write PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 4 read-write 4 0x4 TIMCFG[%s] Timer Configuration N Register 0x480 32 read-write 0 0xFFFFFFFF TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 4 0x4 TIMCMP[%s] Timer Compare N Register 0x500 32 read-write 0 0xFFFFFFFF CMP Timer Compare Value 0 16 read-write EWM EWM EWM 0x40061000 0 0x6 registers CTRL Control Register 0 8 read-write 0 0xFF EWMEN EWM enable. 0 1 read-writeOnce ASSIN EWM_in's Assertion State Select. 1 1 read-writeOnce INEN Input Enable. 2 1 read-writeOnce INTEN Interrupt Enable. 3 1 read-write SERV Service Register 0x1 8 read-write 0 0xFF SERVICE SERVICE 0 8 read-write CMPL Compare Low Register 0x2 8 read-writeOnce 0 0xFF COMPAREL COMPAREL 0 8 read-writeOnce CMPH Compare High Register 0x3 8 read-writeOnce 0xFF 0xFF COMPAREH COMPAREH 0 8 read-writeOnce CLKPRESCALER Clock Prescaler Register 0x5 8 read-writeOnce 0 0xFF CLK_DIV CLK_DIV 0 8 read-writeOnce TRGMUX TRGMUX TRGMUX 0x40063000 0 0x68 registers DMAMUX0 TRGMUX DMAMUX0 Register 0 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 EXTOUT0 TRGMUX EXTOUT0 Register 0x4 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 EXTOUT1 TRGMUX EXTOUT1 Register 0x8 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 ADC0 TRGMUX ADC0 Register 0xC 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 ADC1 TRGMUX ADC1 Register 0x10 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 CMP0 TRGMUX CMP0 Register 0x1C 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 FTM0 TRGMUX FTM0 Register 0x28 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 FTM1 TRGMUX FTM1 Register 0x2C 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 FTM2 TRGMUX FTM2 Register 0x30 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 FTM3 TRGMUX FTM3 Register 0x34 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 PDB0 TRGMUX PDB0 Register 0x38 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 PDB1 TRGMUX PDB1 Register 0x3C 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 FLEXIO TRGMUX FLEXIO Register 0x44 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 LPIT0 TRGMUX LPIT0 Register 0x48 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 LPUART0 TRGMUX LPUART0 Register 0x4C 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 LPUART1 TRGMUX LPUART1 Register 0x50 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 LPI2C0 TRGMUX LPI2C0 Register 0x54 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 LPSPI0 TRGMUX LPSPI0 Register 0x5C 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 LPSPI1 TRGMUX LPSPI1 Register 0x60 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 LPTMR0 TRGMUX LPTMR0 Register 0x64 32 read-write 0 0xFFFFFFFF SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SCG System Clock Generator SCG SCG_ 0x40064000 0 0x60C registers VERID Version ID Register 0 32 read-only 0x1000000 0xFFFFFFFF VERSION SCG Version Number 0 32 read-only PARAM Parameter Register 0x4 32 read-only 0xF80000FE 0xFFFFFFFF CLKPRES Clock Present 0 8 read-only DIVPRES Divider Present 27 5 read-only CSR Clock Status Register 0x10 32 read-only 0x3000001 0xFFFFFFFF DIVSLOW Slow Clock Divide Ratio 0 4 read-only DIVSLOW_0 Divide-by-1 0 DIVSLOW_1 Divide-by-2 0x1 DIVSLOW_2 Divide-by-3 0x2 DIVSLOW_3 Divide-by-4 0x3 DIVSLOW_4 Divide-by-5 0x4 DIVSLOW_5 Divide-by-6 0x5 DIVSLOW_6 Divide-by-7 0x6 DIVSLOW_7 Divide-by-8 0x7 DIVBUS Bus Clock Divide Ratio 4 4 read-only DIVBUS_0 Divide-by-1 0 DIVBUS_1 Divide-by-2 0x1 DIVBUS_2 Divide-by-3 0x2 DIVBUS_3 Divide-by-4 0x3 DIVBUS_4 Divide-by-5 0x4 DIVBUS_5 Divide-by-6 0x5 DIVBUS_6 Divide-by-7 0x6 DIVBUS_7 Divide-by-8 0x7 DIVBUS_8 Divide-by-9 0x8 DIVBUS_9 Divide-by-10 0x9 DIVBUS_10 Divide-by-11 0xA DIVBUS_11 Divide-by-12 0xB DIVBUS_12 Divide-by-13 0xC DIVBUS_13 Divide-by-14 0xD DIVBUS_14 Divide-by-15 0xE DIVBUS_15 Divide-by-16 0xF DIVCORE Core Clock Divide Ratio 16 4 read-only DIVCORE_0 Divide-by-1 0 DIVCORE_1 Divide-by-2 0x1 DIVCORE_2 Divide-by-3 0x2 DIVCORE_3 Divide-by-4 0x3 DIVCORE_4 Divide-by-5 0x4 DIVCORE_5 Divide-by-6 0x5 DIVCORE_6 Divide-by-7 0x6 DIVCORE_7 Divide-by-8 0x7 DIVCORE_8 Divide-by-9 0x8 DIVCORE_9 Divide-by-10 0x9 DIVCORE_10 Divide-by-11 0xA DIVCORE_11 Divide-by-12 0xB DIVCORE_12 Divide-by-13 0xC DIVCORE_13 Divide-by-14 0xD DIVCORE_14 Divide-by-15 0xE DIVCORE_15 Divide-by-16 0xF SCS System Clock Source 24 4 read-only SCS_1 System OSC (SOSC_CLK) 0x1 SCS_2 Slow IRC (SIRC_CLK) 0x2 SCS_3 Fast IRC (FIRC_CLK) 0x3 SCS_6 System PLL (SPLL_CLK) 0x6 RCCR Run Clock Control Register 0x14 32 read-write 0x3000001 0xFFFFFFFF DIVSLOW Slow Clock Divide Ratio 0 4 read-write DIVSLOW_0 Divide-by-1 0 DIVSLOW_1 Divide-by-2 0x1 DIVSLOW_2 Divide-by-3 0x2 DIVSLOW_3 Divide-by-4 0x3 DIVSLOW_4 Divide-by-5 0x4 DIVSLOW_5 Divide-by-6 0x5 DIVSLOW_6 Divide-by-7 0x6 DIVSLOW_7 Divide-by-8 0x7 DIVBUS Bus Clock Divide Ratio 4 4 read-write DIVBUS_0 Divide-by-1 0 DIVBUS_1 Divide-by-2 0x1 DIVBUS_2 Divide-by-3 0x2 DIVBUS_3 Divide-by-4 0x3 DIVBUS_4 Divide-by-5 0x4 DIVBUS_5 Divide-by-6 0x5 DIVBUS_6 Divide-by-7 0x6 DIVBUS_7 Divide-by-8 0x7 DIVBUS_8 Divide-by-9 0x8 DIVBUS_9 Divide-by-10 0x9 DIVBUS_10 Divide-by-11 0xA DIVBUS_11 Divide-by-12 0xB DIVBUS_12 Divide-by-13 0xC DIVBUS_13 Divide-by-14 0xD DIVBUS_14 Divide-by-15 0xE DIVBUS_15 Divide-by-16 0xF DIVCORE Core Clock Divide Ratio 16 4 read-write DIVCORE_0 Divide-by-1 0 DIVCORE_1 Divide-by-2 0x1 DIVCORE_2 Divide-by-3 0x2 DIVCORE_3 Divide-by-4 0x3 DIVCORE_4 Divide-by-5 0x4 DIVCORE_5 Divide-by-6 0x5 DIVCORE_6 Divide-by-7 0x6 DIVCORE_7 Divide-by-8 0x7 DIVCORE_8 Divide-by-9 0x8 DIVCORE_9 Divide-by-10 0x9 DIVCORE_10 Divide-by-11 0xA DIVCORE_11 Divide-by-12 0xB DIVCORE_12 Divide-by-13 0xC DIVCORE_13 Divide-by-14 0xD DIVCORE_14 Divide-by-15 0xE DIVCORE_15 Divide-by-16 0xF SCS System Clock Source 24 4 read-write SCS_1 System OSC (SOSC_CLK) 0x1 SCS_2 Slow IRC (SIRC_CLK) 0x2 SCS_3 Fast IRC (FIRC_CLK) 0x3 SCS_6 System PLL (SPLL_CLK) 0x6 VCCR VLPR Clock Control Register 0x18 32 read-write 0x2000001 0xFFFFFFFF DIVSLOW Slow Clock Divide Ratio 0 4 read-write DIVSLOW_0 Divide-by-1 0 DIVSLOW_1 Divide-by-2 0x1 DIVSLOW_2 Divide-by-3 0x2 DIVSLOW_3 Divide-by-4 0x3 DIVSLOW_4 Divide-by-5 0x4 DIVSLOW_5 Divide-by-6 0x5 DIVSLOW_6 Divide-by-7 0x6 DIVSLOW_7 Divide-by-8 0x7 DIVBUS Bus Clock Divide Ratio 4 4 read-write DIVBUS_0 Divide-by-1 0 DIVBUS_1 Divide-by-2 0x1 DIVBUS_2 Divide-by-3 0x2 DIVBUS_3 Divide-by-4 0x3 DIVBUS_4 Divide-by-5 0x4 DIVBUS_5 Divide-by-6 0x5 DIVBUS_6 Divide-by-7 0x6 DIVBUS_7 Divide-by-8 0x7 DIVBUS_8 Divide-by-9 0x8 DIVBUS_9 Divide-by-10 0x9 DIVBUS_10 Divide-by-11 0xA DIVBUS_11 Divide-by-12 0xB DIVBUS_12 Divide-by-13 0xC DIVBUS_13 Divide-by-14 0xD DIVBUS_14 Divide-by-15 0xE DIVBUS_15 Divide-by-16 0xF DIVCORE Core Clock Divide Ratio 16 4 read-write DIVCORE_0 Divide-by-1 0 DIVCORE_1 Divide-by-2 0x1 DIVCORE_2 Divide-by-3 0x2 DIVCORE_3 Divide-by-4 0x3 DIVCORE_4 Divide-by-5 0x4 DIVCORE_5 Divide-by-6 0x5 DIVCORE_6 Divide-by-7 0x6 DIVCORE_7 Divide-by-8 0x7 DIVCORE_8 Divide-by-9 0x8 DIVCORE_9 Divide-by-10 0x9 DIVCORE_10 Divide-by-11 0xA DIVCORE_11 Divide-by-12 0xB DIVCORE_12 Divide-by-13 0xC DIVCORE_13 Divide-by-14 0xD DIVCORE_14 Divide-by-15 0xE DIVCORE_15 Divide-by-16 0xF SCS System Clock Source 24 4 read-write SCS_2 Slow IRC (SIRC_CLK) 0x2 CLKOUTCNFG SCG CLKOUT Configuration Register 0x20 32 read-write 0x3000000 0xFFFFFFFF CLKOUTSEL SCG Clkout Select 24 4 read-write CLKOUTSEL_0 SCG SLOW Clock 0 CLKOUTSEL_1 System OSC (SOSC_CLK) 0x1 CLKOUTSEL_2 Slow IRC (SIRC_CLK) 0x2 CLKOUTSEL_3 Fast IRC (FIRC_CLK) 0x3 CLKOUTSEL_6 System PLL (SPLL_CLK) 0x6 SOSCCSR System OSC Control Status Register 0x100 32 read-write 0 0xFFFFFFFF SOSCEN System OSC Enable 0 1 read-write SOSCEN_0 System OSC is disabled 0 SOSCEN_1 System OSC is enabled 0x1 SOSCCM System OSC Clock Monitor 16 1 read-write SOSCCM_0 System OSC Clock Monitor is disabled 0 SOSCCM_1 System OSC Clock Monitor is enabled 0x1 SOSCCMRE System OSC Clock Monitor Reset Enable 17 1 read-write SOSCCMRE_0 Clock Monitor generates interrupt when error detected 0 SOSCCMRE_1 Clock Monitor generates reset when error detected 0x1 LK Lock Register 23 1 read-write LK_0 This Control Status Register can be written. 0 LK_1 This Control Status Register cannot be written. 0x1 SOSCVLD System OSC Valid 24 1 read-only SOSCVLD_0 System OSC is not enabled or clock is not valid 0 SOSCVLD_1 System OSC is enabled and output clock is valid 0x1 SOSCSEL System OSC Selected 25 1 read-only SOSCSEL_0 System OSC is not the system clock source 0 SOSCSEL_1 System OSC is the system clock source 0x1 SOSCERR System OSC Clock Error 26 1 read-write oneToClear SOSCERR_0 System OSC Clock Monitor is disabled or has not detected an error 0 SOSCERR_1 System OSC Clock Monitor is enabled and detected an error 0x1 SOSCDIV System OSC Divide Register 0x104 32 read-write 0 0xFFFFFFFF SOSCDIV1 System OSC Clock Divide 1 0 3 read-write SOSCDIV1_0 Output disabled 0 SOSCDIV1_1 Divide by 1 0x1 SOSCDIV1_2 Divide by 2 0x2 SOSCDIV1_3 Divide by 4 0x3 SOSCDIV1_4 Divide by 8 0x4 SOSCDIV1_5 Divide by 16 0x5 SOSCDIV1_6 Divide by 32 0x6 SOSCDIV1_7 Divide by 64 0x7 SOSCDIV2 System OSC Clock Divide 2 8 3 read-write SOSCDIV2_0 Output disabled 0 SOSCDIV2_1 Divide by 1 0x1 SOSCDIV2_2 Divide by 2 0x2 SOSCDIV2_3 Divide by 4 0x3 SOSCDIV2_4 Divide by 8 0x4 SOSCDIV2_5 Divide by 16 0x5 SOSCDIV2_6 Divide by 32 0x6 SOSCDIV2_7 Divide by 64 0x7 SOSCCFG System Oscillator Configuration Register 0x108 32 read-write 0x10 0xFFFFFFFF EREFS External Reference Select 2 1 read-write EREFS_0 External reference clock selected 0 EREFS_1 Internal crystal oscillator of OSC selected. 0x1 HGO High Gain Oscillator Select 3 1 read-write HGO_0 Configure crystal oscillator for low-gain operation 0 HGO_1 Configure crystal oscillator for high-gain operation 0x1 RANGE System OSC Range Select 4 2 read-write RANGE_1 Low frequency range selected for the crystal oscillator 0x1 RANGE_2 Medium frequency range selected for the crytstal oscillator 0x2 RANGE_3 High frequency range selected for the crystal oscillator 0x3 SIRCCSR Slow IRC Control Status Register 0x200 32 read-write 0x1000005 0xFFFFFFFF SIRCEN Slow IRC Enable 0 1 read-write SIRCEN_0 Slow IRC is disabled 0 SIRCEN_1 Slow IRC is enabled 0x1 SIRCSTEN Slow IRC Stop Enable 1 1 read-write SIRCSTEN_0 Slow IRC is disabled in supported Stop modes 0 SIRCSTEN_1 Slow IRC is enabled in supported Stop modes 0x1 SIRCLPEN Slow IRC Low Power Enable 2 1 read-write SIRCLPEN_0 Slow IRC is disabled in VLP modes 0 SIRCLPEN_1 Slow IRC is enabled in VLP modes 0x1 LK Lock Register 23 1 read-write LK_0 Control Status Register can be written. 0 LK_1 Control Status Register cannot be written. 0x1 SIRCVLD Slow IRC Valid 24 1 read-only SIRCVLD_0 Slow IRC is not enabled or clock is not valid 0 SIRCVLD_1 Slow IRC is enabled and output clock is valid 0x1 SIRCSEL Slow IRC Selected 25 1 read-only SIRCSEL_0 Slow IRC is not the system clock source 0 SIRCSEL_1 Slow IRC is the system clock source 0x1 SIRCDIV Slow IRC Divide Register 0x204 32 read-write 0 0xFFFFFFFF SIRCDIV1 Slow IRC Clock Divide 1 0 3 read-write SIRCDIV1_0 Output disabled 0 SIRCDIV1_1 Divide by 1 0x1 SIRCDIV1_2 Divide by 2 0x2 SIRCDIV1_3 Divide by 4 0x3 SIRCDIV1_4 Divide by 8 0x4 SIRCDIV1_5 Divide by 16 0x5 SIRCDIV1_6 Divide by 32 0x6 SIRCDIV1_7 Divide by 64 0x7 SIRCDIV2 Slow IRC Clock Divide 2 8 3 read-write SIRCDIV2_0 Output disabled 0 SIRCDIV2_1 Divide by 1 0x1 SIRCDIV2_2 Divide by 2 0x2 SIRCDIV2_3 Divide by 4 0x3 SIRCDIV2_4 Divide by 8 0x4 SIRCDIV2_5 Divide by 16 0x5 SIRCDIV2_6 Divide by 32 0x6 SIRCDIV2_7 Divide by 64 0x7 SIRCCFG Slow IRC Configuration Register 0x208 32 read-write 0x1 0xFFFFFFFF RANGE Frequency Range 0 1 read-write RANGE_0 Slow IRC low range clock (2 MHz) 0 RANGE_1 Slow IRC high range clock (8 MHz ) 0x1 FIRCCSR Fast IRC Control Status Register 0x300 32 read-write 0x3000001 0xFFFFFFFF FIRCEN Fast IRC Enable 0 1 read-write FIRCEN_0 Fast IRC is disabled 0 FIRCEN_1 Fast IRC is enabled 0x1 FIRCREGOFF Fast IRC Regulator Enable 3 1 read-write FIRCREGOFF_0 Fast IRC Regulator is enabled. 0 FIRCREGOFF_1 Fast IRC Regulator is disabled. 0x1 LK Lock Register 23 1 read-write LK_0 Control Status Register can be written. 0 LK_1 Control Status Register cannot be written. 0x1 FIRCVLD Fast IRC Valid status 24 1 read-only FIRCVLD_0 Fast IRC is not enabled or clock is not valid. 0 FIRCVLD_1 Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog. 0x1 FIRCSEL Fast IRC Selected status 25 1 read-only FIRCSEL_0 Fast IRC is not the system clock source 0 FIRCSEL_1 Fast IRC is the system clock source 0x1 FIRCERR Fast IRC Clock Error 26 1 read-write oneToClear FIRCERR_0 Error not detected with the Fast IRC trimming. 0 FIRCERR_1 Error detected with the Fast IRC trimming. 0x1 FIRCDIV Fast IRC Divide Register 0x304 32 read-write 0 0xFFFFFFFF FIRCDIV1 Fast IRC Clock Divide 1 0 3 read-write FIRCDIV1_0 Output disabled 0 FIRCDIV1_1 Divide by 1 0x1 FIRCDIV1_2 Divide by 2 0x2 FIRCDIV1_3 Divide by 4 0x3 FIRCDIV1_4 Divide by 8 0x4 FIRCDIV1_5 Divide by 16 0x5 FIRCDIV1_6 Divide by 32 0x6 FIRCDIV1_7 Divide by 64 0x7 FIRCDIV2 Fast IRC Clock Divide 2 8 3 read-write FIRCDIV2_0 Output disabled 0 FIRCDIV2_1 Divide by 1 0x1 FIRCDIV2_2 Divide by 2 0x2 FIRCDIV2_3 Divide by 4 0x3 FIRCDIV2_4 Divide by 8 0x4 FIRCDIV2_5 Divide by 16 0x5 FIRCDIV2_6 Divide by 32 0x6 FIRCDIV2_7 Divide by 64 0x7 FIRCCFG Fast IRC Configuration Register 0x308 32 read-write 0 0xFFFFFFFF RANGE Frequency Range 0 2 read-write RANGE_0 Fast IRC is trimmed to 48 MHz 0 SPLLCSR System PLL Control Status Register 0x600 32 read-write 0 0xFFFFFFFF SPLLEN System PLL Enable 0 1 read-write SPLLEN_0 System PLL is disabled 0 SPLLEN_1 System PLL is enabled 0x1 SPLLCM System PLL Clock Monitor 16 1 read-write SPLLCM_0 System PLL Clock Monitor is disabled 0 SPLLCM_1 System PLL Clock Monitor is enabled 0x1 SPLLCMRE System PLL Clock Monitor Reset Enable 17 1 read-write SPLLCMRE_0 Clock Monitor generates interrupt when error detected 0 SPLLCMRE_1 Clock Monitor generates reset when error detected 0x1 LK Lock Register 23 1 read-write LK_0 Control Status Register can be written. 0 LK_1 Control Status Register cannot be written. 0x1 SPLLVLD System PLL Valid 24 1 read-only SPLLVLD_0 System PLL is not enabled or clock is not valid 0 SPLLVLD_1 System PLL is enabled and output clock is valid 0x1 SPLLSEL System PLL Selected 25 1 read-only SPLLSEL_0 System PLL is not the system clock source 0 SPLLSEL_1 System PLL is the system clock source 0x1 SPLLERR System PLL Clock Error 26 1 read-write oneToClear SPLLERR_0 System PLL Clock Monitor is disabled or has not detected an error 0 SPLLERR_1 System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set. 0x1 SPLLDIV System PLL Divide Register 0x604 32 read-write 0 0xFFFFFFFF SPLLDIV1 System PLL Clock Divide 1 0 3 read-write SPLLDIV1_0 Clock disabled 0 SPLLDIV1_1 Divide by 1 0x1 SPLLDIV1_2 Divide by 2 0x2 SPLLDIV1_3 Divide by 4 0x3 SPLLDIV1_4 Divide by 8 0x4 SPLLDIV1_5 Divide by 16 0x5 SPLLDIV1_6 Divide by 32 0x6 SPLLDIV1_7 Divide by 64 0x7 SPLLDIV2 System PLL Clock Divide 2 8 3 read-write SPLLDIV2_0 Clock disabled 0 SPLLDIV2_1 Divide by 1 0x1 SPLLDIV2_2 Divide by 2 0x2 SPLLDIV2_3 Divide by 4 0x3 SPLLDIV2_4 Divide by 8 0x4 SPLLDIV2_5 Divide by 16 0x5 SPLLDIV2_6 Divide by 32 0x6 SPLLDIV2_7 Divide by 64 0x7 SPLLCFG System PLL Configuration Register 0x608 32 read-write 0 0xFFFFFFFF SOURCE Clock Source 0 1 read-write SOURCE_0 System OSC (SOSC) 0 SOURCE_1 Fast IRC (FIRC) 0x1 PREDIV PLL Reference Clock Divider 8 3 read-write MULT System PLL Multiplier 16 5 read-write PCC PCC PCC 0x40065000 0 0x1D0 registers PCC_FTFM PCC FTFM Register 0x80 32 read-write 0xC0000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_DMAMUX PCC DMAMUX Register 0x84 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_FlexCAN0 PCC FlexCAN0 Register 0x90 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_FlexCAN1 PCC FlexCAN1 Register 0x94 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_FTM3 PCC FTM3 Register 0x98 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_ADC1 PCC ADC1 Register 0x9C 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_LPSPI0 PCC LPSPI0 Register 0xB0 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_LPSPI1 PCC LPSPI1 Register 0xB4 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_LPSPI2 PCC LPSPI2 Register 0xB8 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_PDB1 PCC PDB1 Register 0xC4 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_CRC PCC CRC Register 0xC8 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_PDB0 PCC PDB0 Register 0xD8 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_LPIT PCC LPIT Register 0xDC 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_FTM0 PCC FTM0 Register 0xE0 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_FTM1 PCC FTM1 Register 0xE4 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_FTM2 PCC FTM2 Register 0xE8 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_ADC0 PCC ADC0 Register 0xEC 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_RTC PCC RTC Register 0xF4 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_LPTMR0 PCC LPTMR0 Register 0x100 32 read-write 0x80000000 0xFFFFFFFF PCD Peripheral Clock Divider Select 0 3 read-write DIV_1 Divide by 1. 0 DIV_2 Divide by 2. 0x1 DIV_3 Divide by 3. 0x2 DIV_4 Divide by 4. 0x3 DIV_5 Divide by 5. 0x4 DIV_6 Divide by 6. 0x5 DIV_7 Divide by 7. 0x6 DIV_8 Divide by 8. 0x7 FRAC Peripheral Clock Divider Fraction 3 1 read-write FRAC_0 Fractional value is 0. 0 FRAC_1 Fractional value is 1. 0x1 PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_PORTA PCC PORTA Register 0x124 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_PORTB PCC PORTB Register 0x128 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_PORTC PCC PORTC Register 0x12C 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_PORTD PCC PORTD Register 0x130 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_PORTE PCC PORTE Register 0x134 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_FlexIO PCC FlexIO Register 0x168 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_EWM PCC EWM Register 0x184 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_LPI2C0 PCC LPI2C0 Register 0x198 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_LPUART0 PCC LPUART0 Register 0x1A8 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_LPUART1 PCC LPUART1 Register 0x1AC 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_LPUART2 PCC LPUART2 Register 0x1B0 32 read-write 0x80000000 0xFFFFFFFF PCS Peripheral Clock Source Select 24 3 read-write CLOCK_OFF Clock is off. 0 CLOCK_OPT1 Clock option 1 0x1 CLOCK_OPT2 Clock option 2 0x2 CLOCK_OPT3 Clock option 3 0x3 CLOCK_OPT4 Clock option 4 0x4 CLOCK_OPT5 Clock option 5 0x5 CLOCK_OPT6 Clock option 6 0x6 CLOCK_OPT7 Clock option 7 0x7 CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 PCC_CMP0 PCC CMP0 Register 0x1CC 32 read-write 0x80000000 0xFFFFFFFF CGC Clock Gate Control 30 1 read-write DISABLED Clock disabled. The current clock selection and divider options are not locked and can be modified. 0 ENABLED Clock enabled. The current clock selection and divider options are locked and cannot be modified. 0x1 PR Present 31 1 read-only NOT_PRESENT Peripheral is not present. 0 PRESENT Peripheral is present. 0x1 LPI2C0 LPI2C LPI2C 0x40066000 0 0x174 registers VERID Version ID Register 0 32 read-only 0x1000003 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only FEATURE_2 Master only, with standard feature set 0x2 FEATURE_3 Master and slave, with standard feature set 0x3 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x202 0xFFFFFFFF MTXFIFO Master Transmit FIFO Size 0 4 read-only MRXFIFO Master Receive FIFO Size 8 4 read-only MCR Master Control Register 0x10 32 read-write 0 0xFFFFFFFF MEN Master Enable 0 1 read-write MEN_0 Master logic is disabled 0 MEN_1 Master logic is enabled 0x1 RST Software Reset 1 1 read-write RST_0 Master logic is not reset 0 RST_1 Master logic is reset 0x1 DOZEN Doze mode enable 2 1 read-write DOZEN_0 Master is enabled in Doze mode 0 DOZEN_1 Master is disabled in Doze mode 0x1 DBGEN Debug Enable 3 1 read-write DBGEN_0 Master is disabled in debug mode 0 DBGEN_1 Master is enabled in debug mode 0x1 RTF Reset Transmit FIFO 8 1 read-write RTF_0 No effect 0 RTF_1 Transmit FIFO is reset 0x1 RRF Reset Receive FIFO 9 1 read-write RRF_0 No effect 0 RRF_1 Receive FIFO is reset 0x1 MSR Master Status Register 0x14 32 read-write 0x1 0xFFFFFFFF TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data is not requested 0 TDF_1 Transmit data is requested 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive Data is not ready 0 RDF_1 Receive data is ready 0x1 EPF End Packet Flag 8 1 read-write oneToClear EPF_0 Master has not generated a STOP or Repeated START condition 0 EPF_1 Master has generated a STOP or Repeated START condition 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear SDF_0 Master has not generated a STOP condition 0 SDF_1 Master has generated a STOP condition 0x1 NDF NACK Detect Flag 10 1 read-write oneToClear NDF_0 Unexpected NACK was not detected 0 NDF_1 Unexpected NACK was detected 0x1 ALF Arbitration Lost Flag 11 1 read-write oneToClear ALF_0 Master has not lost arbitration 0 ALF_1 Master has lost arbitration 0x1 FEF FIFO Error Flag 12 1 read-write oneToClear FEF_0 No error 0 FEF_1 Master sending or receiving data without a START condition 0x1 PLTF Pin Low Timeout Flag 13 1 read-write oneToClear PLTF_0 Pin low timeout has not occurred or is disabled 0 PLTF_1 Pin low timeout has occurred 0x1 DMF Data Match Flag 14 1 read-write oneToClear DMF_0 Have not received matching data 0 DMF_1 Have received matching data 0x1 MBF Master Busy Flag 24 1 read-only MBF_0 I2C Master is idle 0 MBF_1 I2C Master is busy 0x1 BBF Bus Busy Flag 25 1 read-only BBF_0 I2C Bus is idle 0 BBF_1 I2C Bus is busy 0x1 MIER Master Interrupt Enable Register 0x18 32 read-write 0 0xFFFFFFFF TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 EPIE End Packet Interrupt Enable 8 1 read-write EPIE_0 Disabled 0 EPIE_1 Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write SDIE_0 Disabled 0 SDIE_1 Enabled 0x1 NDIE NACK Detect Interrupt Enable 10 1 read-write NDIE_0 Disabled 0 NDIE_1 Enabled 0x1 ALIE Arbitration Lost Interrupt Enable 11 1 read-write ALIE_0 Disabled 0 ALIE_1 Enabled 0x1 FEIE FIFO Error Interrupt Enable 12 1 read-write FEIE_0 Enabled 0 FEIE_1 Disabled 0x1 PLTIE Pin Low Timeout Interrupt Enable 13 1 read-write PLTIE_0 Disabled 0 PLTIE_1 Enabled 0x1 DMIE Data Match Interrupt Enable 14 1 read-write DMIE_0 Disabled 0 DMIE_1 Enabled 0x1 MDER Master DMA Enable Register 0x1C 32 read-write 0 0xFFFFFFFF TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 MCFGR0 Master Configuration Register 0 0x20 32 read-write 0 0xFFFFFFFF HREN Host Request Enable 0 1 read-write HREN_0 Host request input is disabled 0 HREN_1 Host request input is enabled 0x1 HRPOL Host Request Polarity 1 1 read-write HRPOL_0 Active low 0 HRPOL_1 Active high 0x1 HRSEL Host Request Select 2 1 read-write HRSEL_0 Host request input is pin HREQ 0 HRSEL_1 Host request input is input trigger 0x1 CIRFIFO Circular FIFO Enable 8 1 read-write CIRFIFO_0 Circular FIFO is disabled 0 CIRFIFO_1 Circular FIFO is enabled 0x1 RDMO Receive Data Match Only 9 1 read-write RDMO_0 Received data is stored in the receive FIFO 0 RDMO_1 Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set 0x1 MCFGR1 Master Configuration Register 1 0x24 32 read-write 0 0xFFFFFFFF PRESCALE Prescaler 0 3 read-write PRESCALE_0 Divide by 1 0 PRESCALE_1 Divide by 2 0x1 PRESCALE_2 Divide by 4 0x2 PRESCALE_3 Divide by 8 0x3 PRESCALE_4 Divide by 16 0x4 PRESCALE_5 Divide by 32 0x5 PRESCALE_6 Divide by 64 0x6 PRESCALE_7 Divide by 128 0x7 AUTOSTOP Automatic STOP Generation 8 1 read-write AUTOSTOP_0 No effect 0 AUTOSTOP_1 STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy 0x1 IGNACK IGNACK 9 1 read-write IGNACK_0 LPI2C Master will receive ACK and NACK normally 0 IGNACK_1 LPI2C Master will treat a received NACK as if it (NACK) was an ACK 0x1 TIMECFG Timeout Configuration 10 1 read-write TIMECFG_0 Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout 0 TIMECFG_1 Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout 0x1 MATCFG Match Configuration 16 3 read-write MATCFG_0 Match is disabled 0 MATCFG_2 Match is enabled (1st data word equals MATCH0 OR MATCH1) 0x2 MATCFG_3 Match is enabled (any data word equals MATCH0 OR MATCH1) 0x3 MATCFG_4 Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) 0x4 MATCFG_5 Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) 0x5 MATCFG_6 Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) 0x6 MATCFG_7 Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) 0x7 PINCFG Pin Configuration 24 3 read-write PINCFG_0 2-pin open drain mode 0 PINCFG_1 2-pin output only mode (ultra-fast mode) 0x1 PINCFG_2 2-pin push-pull mode 0x2 PINCFG_3 4-pin push-pull mode 0x3 PINCFG_4 2-pin open drain mode with separate LPI2C slave 0x4 PINCFG_5 2-pin output only mode (ultra-fast mode) with separate LPI2C slave 0x5 PINCFG_6 2-pin push-pull mode with separate LPI2C slave 0x6 PINCFG_7 4-pin push-pull mode (inverted outputs) 0x7 MCFGR2 Master Configuration Register 2 0x28 32 read-write 0 0xFFFFFFFF BUSIDLE Bus Idle Timeout 0 12 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write MCFGR3 Master Configuration Register 3 0x2C 32 read-write 0 0xFFFFFFFF PINLOW Pin Low Timeout 8 12 read-write MDMR Master Data Match Register 0x40 32 read-write 0 0xFFFFFFFF MATCH0 Match 0 Value 0 8 read-write MATCH1 Match 1 Value 16 8 read-write MCCR0 Master Clock Configuration Register 0 0x48 32 read-write 0 0xFFFFFFFF CLKLO Clock Low Period 0 6 read-write CLKHI Clock High Period 8 6 read-write SETHOLD Setup Hold Delay 16 6 read-write DATAVD Data Valid Delay 24 6 read-write MCCR1 Master Clock Configuration Register 1 0x50 32 read-write 0 0xFFFFFFFF CLKLO Clock Low Period 0 6 read-write CLKHI Clock High Period 8 6 read-write SETHOLD Setup Hold Delay 16 6 read-write DATAVD Data Valid Delay 24 6 read-write MFCR Master FIFO Control Register 0x58 32 read-write 0 0xFFFFFFFF TXWATER Transmit FIFO Watermark 0 2 read-write RXWATER Receive FIFO Watermark 16 2 read-write MFSR Master FIFO Status Register 0x5C 32 read-only 0 0xFFFFFFFF TXCOUNT Transmit FIFO Count 0 3 read-only RXCOUNT Receive FIFO Count 16 3 read-only MTDR Master Transmit Data Register 0x60 32 write-only 0 0xFFFFFFFF DATA Transmit Data 0 8 write-only CMD Command Data 8 3 write-only CMD_0 Transmit DATA[7:0] 0 CMD_1 Receive (DATA[7:0] + 1) bytes 0x1 CMD_2 Generate STOP condition 0x2 CMD_3 Receive and discard (DATA[7:0] + 1) bytes 0x3 CMD_4 Generate (repeated) START and transmit address in DATA[7:0] 0x4 CMD_5 Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. 0x5 CMD_6 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode 0x6 CMD_7 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. 0x7 MRDR Master Receive Data Register 0x70 32 read-only 0x4000 0xFFFFFFFF DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only RXEMPTY_0 Receive FIFO is not empty 0 RXEMPTY_1 Receive FIFO is empty 0x1 SCR Slave Control Register 0x110 32 read-write 0 0xFFFFFFFF SEN Slave Enable 0 1 read-write SEN_0 I2C Slave mode is disabled 0 SEN_1 I2C Slave mode is enabled 0x1 RST Software Reset 1 1 read-write RST_0 Slave mode logic is not reset 0 RST_1 Slave mode logic is reset 0x1 FILTEN Filter Enable 4 1 read-write FILTEN_0 Disable digital filter and output delay counter for slave mode 0 FILTEN_1 Enable digital filter and output delay counter for slave mode 0x1 FILTDZ Filter Doze Enable 5 1 read-write FILTDZ_0 Filter remains enabled in Doze mode 0 FILTDZ_1 Filter is disabled in Doze mode 0x1 RTF Reset Transmit FIFO 8 1 read-write RTF_0 No effect 0 RTF_1 Transmit Data Register is now empty 0x1 RRF Reset Receive FIFO 9 1 read-write RRF_0 No effect 0 RRF_1 Receive Data Register is now empty 0x1 SSR Slave Status Register 0x114 32 read-write 0 0xFFFFFFFF TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data not requested 0 TDF_1 Transmit data is requested 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive data is not ready 0 RDF_1 Receive data is ready 0x1 AVF Address Valid Flag 2 1 read-only AVF_0 Address Status Register is not valid 0 AVF_1 Address Status Register is valid 0x1 TAF Transmit ACK Flag 3 1 read-only TAF_0 Transmit ACK/NACK is not required 0 TAF_1 Transmit ACK/NACK is required 0x1 RSF Repeated Start Flag 8 1 read-write oneToClear RSF_0 Slave has not detected a Repeated START condition 0 RSF_1 Slave has detected a Repeated START condition 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear SDF_0 Slave has not detected a STOP condition 0 SDF_1 Slave has detected a STOP condition 0x1 BEF Bit Error Flag 10 1 read-write oneToClear BEF_0 Slave has not detected a bit error 0 BEF_1 Slave has detected a bit error 0x1 FEF FIFO Error Flag 11 1 read-write oneToClear FEF_0 FIFO underflow or overflow was not detected 0 FEF_1 FIFO underflow or overflow was detected 0x1 AM0F Address Match 0 Flag 12 1 read-only AM0F_0 Have not received an ADDR0 matching address 0 AM0F_1 Have received an ADDR0 matching address 0x1 AM1F Address Match 1 Flag 13 1 read-only AM1F_0 Have not received an ADDR1 or ADDR0/ADDR1 range matching address 0 AM1F_1 Have received an ADDR1 or ADDR0/ADDR1 range matching address 0x1 GCF General Call Flag 14 1 read-only GCF_0 Slave has not detected the General Call Address or the General Call Address is disabled 0 GCF_1 Slave has detected the General Call Address 0x1 SARF SMBus Alert Response Flag 15 1 read-only SARF_0 SMBus Alert Response is disabled or not detected 0 SARF_1 SMBus Alert Response is enabled and detected 0x1 SBF Slave Busy Flag 24 1 read-only SBF_0 I2C Slave is idle 0 SBF_1 I2C Slave is busy 0x1 BBF Bus Busy Flag 25 1 read-only BBF_0 I2C Bus is idle 0 BBF_1 I2C Bus is busy 0x1 SIER Slave Interrupt Enable Register 0x118 32 read-write 0 0xFFFFFFFF TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 AVIE Address Valid Interrupt Enable 2 1 read-write AVIE_0 Disabled 0 AVIE_1 Enabled 0x1 TAIE Transmit ACK Interrupt Enable 3 1 read-write TAIE_0 Disabled 0 TAIE_1 Enabled 0x1 RSIE Repeated Start Interrupt Enable 8 1 read-write RSIE_0 Disabled 0 RSIE_1 Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write SDIE_0 Disabled 0 SDIE_1 Enabled 0x1 BEIE Bit Error Interrupt Enable 10 1 read-write BEIE_0 Disabled 0 BEIE_1 Enabled 0x1 FEIE FIFO Error Interrupt Enable 11 1 read-write FEIE_0 Disabled 0 FEIE_1 Enabled 0x1 AM0IE Address Match 0 Interrupt Enable 12 1 read-write AM0IE_0 Enabled 0 AM0IE_1 Disabled 0x1 AM1F Address Match 1 Interrupt Enable 13 1 read-write AM1F_0 Disabled 0 AM1F_1 Enabled 0x1 GCIE General Call Interrupt Enable 14 1 read-write GCIE_0 Disabled 0 GCIE_1 Enabled 0x1 SARIE SMBus Alert Response Interrupt Enable 15 1 read-write SARIE_0 Disabled 0 SARIE_1 Enabled 0x1 SDER Slave DMA Enable Register 0x11C 32 read-write 0 0xFFFFFFFF TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 AVDE Address Valid DMA Enable 2 1 read-write AVDE_0 DMA request is disabled 0 AVDE_1 DMA request is enabled 0x1 SCFGR1 Slave Configuration Register 1 0x124 32 read-write 0 0xFFFFFFFF ADRSTALL Address SCL Stall 0 1 read-write ADRSTALL_0 Clock stretching is disabled 0 ADRSTALL_1 Clock stretching is enabled 0x1 RXSTALL RX SCL Stall 1 1 read-write RXSTALL_0 Clock stretching is disabled 0 RXSTALL_1 Clock stretching is enabled 0x1 TXDSTALL TX Data SCL Stall 2 1 read-write TXDSTALL_0 Clock stretching is disabled 0 TXDSTALL_1 Clock stretching is enabled 0x1 ACKSTALL ACK SCL Stall 3 1 read-write ACKSTALL_0 Clock stretching is disabled 0 ACKSTALL_1 Clock stretching is enabled 0x1 GCEN General Call Enable 8 1 read-write GCEN_0 General Call address is disabled 0 GCEN_1 General Call address is enabled 0x1 SAEN SMBus Alert Enable 9 1 read-write SAEN_0 Disables match on SMBus Alert 0 SAEN_1 Enables match on SMBus Alert 0x1 TXCFG Transmit Flag Configuration 10 1 read-write TXCFG_0 Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty 0 TXCFG_1 Transmit Data Flag will assert whenever the Transmit Data register is empty 0x1 RXCFG Receive Data Configuration 11 1 read-write RXCFG_0 Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). 0 RXCFG_1 Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). 0x1 IGNACK Ignore NACK 12 1 read-write IGNACK_0 Slave will end transfer when NACK is detected 0 IGNACK_1 Slave will not end transfer when NACK detected 0x1 HSMEN High Speed Mode Enable 13 1 read-write HSMEN_0 Disables detection of HS-mode master code 0 HSMEN_1 Enables detection of HS-mode master code 0x1 ADDRCFG Address Configuration 16 3 read-write ADDRCFG_0 Address match 0 (7-bit) 0 ADDRCFG_1 Address match 0 (10-bit) 0x1 ADDRCFG_2 Address match 0 (7-bit) or Address match 1 (7-bit) 0x2 ADDRCFG_3 Address match 0 (10-bit) or Address match 1 (10-bit) 0x3 ADDRCFG_4 Address match 0 (7-bit) or Address match 1 (10-bit) 0x4 ADDRCFG_5 Address match 0 (10-bit) or Address match 1 (7-bit) 0x5 ADDRCFG_6 From Address match 0 (7-bit) to Address match 1 (7-bit) 0x6 ADDRCFG_7 From Address match 0 (10-bit) to Address match 1 (10-bit) 0x7 SCFGR2 Slave Configuration Register 2 0x128 32 read-write 0 0xFFFFFFFF CLKHOLD Clock Hold Time 0 4 read-write DATAVD Data Valid Delay 8 6 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write SAMR Slave Address Match Register 0x140 32 read-write 0 0xFFFFFFFF ADDR0 Address 0 Value 1 10 read-write ADDR1 Address 1 Value 17 10 read-write SASR Slave Address Status Register 0x150 32 read-only 0x4000 0xFFFFFFFF RADDR Received Address 0 11 read-only ANV Address Not Valid 14 1 read-only ANV_0 Received Address (RADDR) is valid 0 ANV_1 Received Address (RADDR) is not valid 0x1 STAR Slave Transmit ACK Register 0x154 32 read-write 0 0xFFFFFFFF TXNACK Transmit NACK 0 1 read-write TXNACK_0 Write a Transmit ACK for each received word 0 TXNACK_1 Write a Transmit NACK for each received word 0x1 STDR Slave Transmit Data Register 0x160 32 write-only 0 0xFFFFFFFF DATA Transmit Data 0 8 write-only SRDR Slave Receive Data Register 0x170 32 read-only 0x4000 0xFFFFFFFF DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only RXEMPTY_0 The Receive Data Register is not empty 0 RXEMPTY_1 The Receive Data Register is empty 0x1 SOF Start Of Frame 15 1 read-only SOF_0 Indicates this is not the first data word since a (repeated) START or STOP condition 0 SOF_1 Indicates this is the first data word since a (repeated) START or STOP condition 0x1 LPUART0 LPUART LPUART LPUART 0x4006A000 0 0x30 registers VERID Version ID Register 0 32 read-only 0x4010003 0xFFFFFFFF FEATURE Feature Identification Number 0 16 read-only FEATURE_1 Standard feature set. 0x1 FEATURE_3 Standard feature set with MODEM/IrDA support. 0x3 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x202 0xFFFFFFFF TXFIFO Transmit FIFO Size 0 8 read-only RXFIFO Receive FIFO Size 8 8 read-only GLOBAL LPUART Global Register 0x8 32 read-write 0 0xFFFFFFFF RST Software Reset 1 1 read-write RST_0 Module is not reset. 0 RST_1 Module is reset. 0x1 PINCFG LPUART Pin Configuration Register 0xC 32 read-write 0 0xFFFFFFFF TRGSEL Trigger Select 0 2 read-write TRGSEL_0 Input trigger is disabled. 0 TRGSEL_1 Input trigger is used instead of RXD pin input. 0x1 TRGSEL_2 Input trigger is used instead of CTS_B pin input. 0x2 TRGSEL_3 Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. 0x3 BAUD LPUART Baud Rate Register 0x10 32 read-write 0xF000004 0xFFFFFFFF SBR Baud Rate Modulo Divisor. 0 13 read-write SBNS Stop Bit Number Select 13 1 read-write SBNS_0 One stop bit. 0 SBNS_1 Two stop bits. 0x1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write RXEDGIE_0 Hardware interrupts from STAT[RXEDGIF] are disabled. 0 RXEDGIE_1 Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. 0x1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write LBKDIE_0 Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). 0 LBKDIE_1 Hardware interrupt requested when STAT[LBKDIF] flag is 1. 0x1 RESYNCDIS Resynchronization Disable 16 1 read-write RESYNCDIS_0 Resynchronization during received data word is supported 0 RESYNCDIS_1 Resynchronization during received data word is disabled 0x1 BOTHEDGE Both Edge Sampling 17 1 read-write BOTHEDGE_0 Receiver samples input data using the rising edge of the baud rate clock. 0 BOTHEDGE_1 Receiver samples input data using the rising and falling edge of the baud rate clock. 0x1 MATCFG Match Configuration 18 2 read-write MATCFG_0 Address Match Wakeup 0 MATCFG_1 Idle Match Wakeup 0x1 MATCFG_2 Match On and Match Off 0x2 MATCFG_3 Enables RWU on Data Match and Match On/Off for transmitter CTS input 0x3 RIDMAE Receiver Idle DMA Enable 20 1 read-write RIDMAE_0 DMA request disabled. 0 RIDMAE_1 DMA request enabled. 0x1 RDMAE Receiver Full DMA Enable 21 1 read-write RDMAE_0 DMA request disabled. 0 RDMAE_1 DMA request enabled. 0x1 TDMAE Transmitter DMA Enable 23 1 read-write TDMAE_0 DMA request disabled. 0 TDMAE_1 DMA request enabled. 0x1 OSR Oversampling Ratio 24 5 read-write OSR_0 Writing 0 to this field results in an oversampling ratio of 16 0 OSR_3 Oversampling ratio of 4, requires BOTHEDGE to be set. 0x3 OSR_4 Oversampling ratio of 5, requires BOTHEDGE to be set. 0x4 OSR_5 Oversampling ratio of 6, requires BOTHEDGE to be set. 0x5 OSR_6 Oversampling ratio of 7, requires BOTHEDGE to be set. 0x6 OSR_7 Oversampling ratio of 8. 0x7 OSR_8 Oversampling ratio of 9. 0x8 OSR_9 Oversampling ratio of 10. 0x9 OSR_10 Oversampling ratio of 11. 0xA OSR_11 Oversampling ratio of 12. 0xB OSR_12 Oversampling ratio of 13. 0xC OSR_13 Oversampling ratio of 14. 0xD OSR_14 Oversampling ratio of 15. 0xE OSR_15 Oversampling ratio of 16. 0xF OSR_16 Oversampling ratio of 17. 0x10 OSR_17 Oversampling ratio of 18. 0x11 OSR_18 Oversampling ratio of 19. 0x12 OSR_19 Oversampling ratio of 20. 0x13 OSR_20 Oversampling ratio of 21. 0x14 OSR_21 Oversampling ratio of 22. 0x15 OSR_22 Oversampling ratio of 23. 0x16 OSR_23 Oversampling ratio of 24. 0x17 OSR_24 Oversampling ratio of 25. 0x18 OSR_25 Oversampling ratio of 26. 0x19 OSR_26 Oversampling ratio of 27. 0x1A OSR_27 Oversampling ratio of 28. 0x1B OSR_28 Oversampling ratio of 29. 0x1C OSR_29 Oversampling ratio of 30. 0x1D OSR_30 Oversampling ratio of 31. 0x1E OSR_31 Oversampling ratio of 32. 0x1F M10 10-bit Mode select 29 1 read-write M10_0 Receiver and transmitter use 7-bit to 9-bit data characters. 0 M10_1 Receiver and transmitter use 10-bit data characters. 0x1 MAEN2 Match Address Mode Enable 2 30 1 read-write MAEN2_0 Normal operation. 0 MAEN2_1 Enables automatic address matching or data matching mode for MATCH[MA2]. 0x1 MAEN1 Match Address Mode Enable 1 31 1 read-write MAEN1_0 Normal operation. 0 MAEN1_1 Enables automatic address matching or data matching mode for MATCH[MA1]. 0x1 STAT LPUART Status Register 0x14 32 read-write 0xC00000 0xFFFFFFFF MA2F Match 2 Flag 14 1 read-write oneToClear MA2F_0 Received data is not equal to MA2 0 MA2F_1 Received data is equal to MA2 0x1 MA1F Match 1 Flag 15 1 read-write oneToClear MA1F_0 Received data is not equal to MA1 0 MA1F_1 Received data is equal to MA1 0x1 PF Parity Error Flag 16 1 read-write oneToClear PF_0 No parity error. 0 PF_1 Parity error. 0x1 FE Framing Error Flag 17 1 read-write oneToClear FE_0 No framing error detected. This does not guarantee the framing is correct. 0 FE_1 Framing error. 0x1 NF Noise Flag 18 1 read-write oneToClear NF_0 No noise detected. 0 NF_1 Noise detected in the received character in the DATA register. 0x1 OR Receiver Overrun Flag 19 1 read-write oneToClear OR_0 No overrun. 0 OR_1 Receive overrun (new LPUART data lost). 0x1 IDLE Idle Line Flag 20 1 read-write oneToClear IDLE_0 No idle line detected. 0 IDLE_1 Idle line was detected. 0x1 RDRF Receive Data Register Full Flag 21 1 read-only RDRF_0 Receive data buffer empty. 0 RDRF_1 Receive data buffer full. 0x1 TC Transmission Complete Flag 22 1 read-only TC_0 Transmitter active (sending data, a preamble, or a break). 0 TC_1 Transmitter idle (transmission activity complete). 0x1 TDRE Transmit Data Register Empty Flag 23 1 read-only TDRE_0 Transmit data buffer full. 0 TDRE_1 Transmit data buffer empty. 0x1 RAF Receiver Active Flag 24 1 read-only RAF_0 LPUART receiver idle waiting for a start bit. 0 RAF_1 LPUART receiver active (RXD input not idle). 0x1 LBKDE LIN Break Detection Enable 25 1 read-write LBKDE_0 LIN break detect is disabled, normal break character can be detected. 0 LBKDE_1 LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). 0x1 BRK13 Break Character Generation Length 26 1 read-write BRK13_0 Break character is transmitted with length of 9 to 13 bit times. 0 BRK13_1 Break character is transmitted with length of 12 to 15 bit times. 0x1 RWUID Receive Wake Up Idle Detect 27 1 read-write RWUID_0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. 0 RWUID_1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. 0x1 RXINV Receive Data Inversion 28 1 read-write RXINV_0 Receive data not inverted. 0 RXINV_1 Receive data inverted. 0x1 MSBF MSB First 29 1 read-write MSBF_0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. 0 MSBF_1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. 0x1 RXEDGIF RXD Pin Active Edge Interrupt Flag 30 1 read-write oneToClear RXEDGIF_0 No active edge on the receive pin has occurred. 0 RXEDGIF_1 An active edge on the receive pin has occurred. 0x1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write oneToClear LBKDIF_0 No LIN break character has been detected. 0 LBKDIF_1 LIN break character has been detected. 0x1 CTRL LPUART Control Register 0x18 32 read-write 0 0xFFFFFFFF PT Parity Type 0 1 read-write PT_0 Even parity. 0 PT_1 Odd parity. 0x1 PE Parity Enable 1 1 read-write PE_0 No hardware parity generation or checking. 0 PE_1 Parity enabled. 0x1 ILT Idle Line Type Select 2 1 read-write ILT_0 Idle character bit count starts after start bit. 0 ILT_1 Idle character bit count starts after stop bit. 0x1 WAKE Receiver Wakeup Method Select 3 1 read-write WAKE_0 Configures RWU for idle-line wakeup. 0 WAKE_1 Configures RWU with address-mark wakeup. 0x1 M 9-Bit or 8-Bit Mode Select 4 1 read-write M_0 Receiver and transmitter use 8-bit data characters. 0 M_1 Receiver and transmitter use 9-bit data characters. 0x1 RSRC Receiver Source Select 5 1 read-write RSRC_0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. 0 RSRC_1 Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. 0x1 DOZEEN Doze Enable 6 1 read-write DOZEEN_0 LPUART is enabled in Doze mode. 0 DOZEEN_1 LPUART is disabled in Doze mode. 0x1 LOOPS Loop Mode Select 7 1 read-write LOOPS_0 Normal operation - RXD and TXD use separate pins. 0 LOOPS_1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). 0x1 IDLECFG Idle Configuration 8 3 read-write IDLECFG_0 1 idle character 0 IDLECFG_1 2 idle characters 0x1 IDLECFG_2 4 idle characters 0x2 IDLECFG_3 8 idle characters 0x3 IDLECFG_4 16 idle characters 0x4 IDLECFG_5 32 idle characters 0x5 IDLECFG_6 64 idle characters 0x6 IDLECFG_7 128 idle characters 0x7 M7 7-Bit Mode Select 11 1 read-write M7_0 Receiver and transmitter use 8-bit to 10-bit data characters. 0 M7_1 Receiver and transmitter use 7-bit data characters. 0x1 MA2IE Match 2 Interrupt Enable 14 1 read-write MA2IE_0 MA2F interrupt disabled 0 MA2IE_1 MA2F interrupt enabled 0x1 MA1IE Match 1 Interrupt Enable 15 1 read-write MA1IE_0 MA1F interrupt disabled 0 MA1IE_1 MA1F interrupt enabled 0x1 SBK Send Break 16 1 read-write SBK_0 Normal transmitter operation. 0 SBK_1 Queue break character(s) to be sent. 0x1 RWU Receiver Wakeup Control 17 1 read-write RWU_0 Normal receiver operation. 0 RWU_1 LPUART receiver in standby waiting for wakeup condition. 0x1 RE Receiver Enable 18 1 read-write RE_0 Receiver disabled. 0 RE_1 Receiver enabled. 0x1 TE Transmitter Enable 19 1 read-write TE_0 Transmitter disabled. 0 TE_1 Transmitter enabled. 0x1 ILIE Idle Line Interrupt Enable 20 1 read-write ILIE_0 Hardware interrupts from IDLE disabled; use polling. 0 ILIE_1 Hardware interrupt requested when IDLE flag is 1. 0x1 RIE Receiver Interrupt Enable 21 1 read-write RIE_0 Hardware interrupts from RDRF disabled; use polling. 0 RIE_1 Hardware interrupt requested when RDRF flag is 1. 0x1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write TCIE_0 Hardware interrupts from TC disabled; use polling. 0 TCIE_1 Hardware interrupt requested when TC flag is 1. 0x1 TIE Transmit Interrupt Enable 23 1 read-write TIE_0 Hardware interrupts from TDRE disabled; use polling. 0 TIE_1 Hardware interrupt requested when TDRE flag is 1. 0x1 PEIE Parity Error Interrupt Enable 24 1 read-write PEIE_0 PF interrupts disabled; use polling). 0 PEIE_1 Hardware interrupt requested when PF is set. 0x1 FEIE Framing Error Interrupt Enable 25 1 read-write FEIE_0 FE interrupts disabled; use polling. 0 FEIE_1 Hardware interrupt requested when FE is set. 0x1 NEIE Noise Error Interrupt Enable 26 1 read-write NEIE_0 NF interrupts disabled; use polling. 0 NEIE_1 Hardware interrupt requested when NF is set. 0x1 ORIE Overrun Interrupt Enable 27 1 read-write ORIE_0 OR interrupts disabled; use polling. 0 ORIE_1 Hardware interrupt requested when OR is set. 0x1 TXINV Transmit Data Inversion 28 1 read-write TXINV_0 Transmit data not inverted. 0 TXINV_1 Transmit data inverted. 0x1 TXDIR TXD Pin Direction in Single-Wire Mode 29 1 read-write TXDIR_0 TXD pin is an input in single-wire mode. 0 TXDIR_1 TXD pin is an output in single-wire mode. 0x1 R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write DATA LPUART Data Register 0x1C 32 read-write 0x1000 0xFFFFFFFF R0T0 R0T0 0 1 read-write R1T1 R1T1 1 1 read-write R2T2 R2T2 2 1 read-write R3T3 R3T3 3 1 read-write R4T4 R4T4 4 1 read-write R5T5 R5T5 5 1 read-write R6T6 R6T6 6 1 read-write R7T7 R7T7 7 1 read-write R8T8 R8T8 8 1 read-write R9T9 R9T9 9 1 read-write IDLINE Idle Line 11 1 read-only IDLINE_0 Receiver was not idle before receiving this character. 0 IDLINE_1 Receiver was idle before receiving this character. 0x1 RXEMPT Receive Buffer Empty 12 1 read-only RXEMPT_0 Receive buffer contains valid data. 0 RXEMPT_1 Receive buffer is empty, data returned on read is not valid. 0x1 FRETSC Frame Error / Transmit Special Character 13 1 read-write FRETSC_0 The dataword was received without a frame error on read, or transmit a normal character on write. 0 FRETSC_1 The dataword was received with a frame error, or transmit an idle or break character on transmit. 0x1 PARITYE PARITYE 14 1 read-only PARITYE_0 The dataword was received without a parity error. 0 PARITYE_1 The dataword was received with a parity error. 0x1 NOISY NOISY 15 1 read-only NOISY_0 The dataword was received without noise. 0 NOISY_1 The data was received with noise. 0x1 MATCH LPUART Match Address Register 0x20 32 read-write 0 0xFFFFFFFF MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x24 32 read-write 0 0xFFFFFFFF TXCTSE Transmitter clear-to-send enable 0 1 read-write TXCTSE_0 CTS has no effect on the transmitter. 0 TXCTSE_1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. 0x1 TXRTSE Transmitter request-to-send enable 1 1 read-write TXRTSE_0 The transmitter has no effect on RTS. 0 TXRTSE_1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. 0x1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write TXRTSPOL_0 Transmitter RTS is active low. 0 TXRTSPOL_1 Transmitter RTS is active high. 0x1 RXRTSE Receiver request-to-send enable 3 1 read-write RXRTSE_0 The receiver has no effect on RTS. 0 RXRTSE_1 RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. 0x1 TXCTSC Transmit CTS Configuration 4 1 read-write TXCTSC_0 CTS input is sampled at the start of each character. 0 TXCTSC_1 CTS input is sampled when the transmitter is idle. 0x1 TXCTSSRC Transmit CTS Source 5 1 read-write TXCTSSRC_0 CTS input is the CTS_B pin. 0 TXCTSSRC_1 CTS input is the inverted Receiver Match result. 0x1 RTSWATER Receive RTS Configuration 8 2 read-write TNP Transmitter narrow pulse 16 2 read-write TNP_0 1/OSR. 0 TNP_1 2/OSR. 0x1 TNP_2 3/OSR. 0x2 TNP_3 4/OSR. 0x3 IREN Infrared enable 18 1 read-write IREN_0 IR disabled. 0 IREN_1 IR enabled. 0x1 FIFO LPUART FIFO Register 0x28 32 read-write 0xC00011 0xFFFFFFFF RXFIFOSIZE Receive FIFO Buffer Depth 0 3 read-only RXFIFOSIZE_0 Receive FIFO/Buffer depth = 1 dataword. 0 RXFIFOSIZE_1 Receive FIFO/Buffer depth = 4 datawords. 0x1 RXFIFOSIZE_2 Receive FIFO/Buffer depth = 8 datawords. 0x2 RXFIFOSIZE_3 Receive FIFO/Buffer depth = 16 datawords. 0x3 RXFIFOSIZE_4 Receive FIFO/Buffer depth = 32 datawords. 0x4 RXFIFOSIZE_5 Receive FIFO/Buffer depth = 64 datawords. 0x5 RXFIFOSIZE_6 Receive FIFO/Buffer depth = 128 datawords. 0x6 RXFIFOSIZE_7 Receive FIFO/Buffer depth = 256 datawords. 0x7 RXFE Receive FIFO Enable 3 1 read-write RXFE_0 Receive FIFO is not enabled. Buffer is depth 1. 0 RXFE_1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. 0x1 TXFIFOSIZE Transmit FIFO Buffer Depth 4 3 read-only TXFIFOSIZE_0 Transmit FIFO/Buffer depth = 1 dataword. 0 TXFIFOSIZE_1 Transmit FIFO/Buffer depth = 4 datawords. 0x1 TXFIFOSIZE_2 Transmit FIFO/Buffer depth = 8 datawords. 0x2 TXFIFOSIZE_3 Transmit FIFO/Buffer depth = 16 datawords. 0x3 TXFIFOSIZE_4 Transmit FIFO/Buffer depth = 32 datawords. 0x4 TXFIFOSIZE_5 Transmit FIFO/Buffer depth = 64 datawords. 0x5 TXFIFOSIZE_6 Transmit FIFO/Buffer depth = 128 datawords. 0x6 TXFIFOSIZE_7 Transmit FIFO/Buffer depth = 256 datawords 0x7 TXFE Transmit FIFO Enable 7 1 read-write TXFE_0 Transmit FIFO is not enabled. Buffer is depth 1. 0 TXFE_1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. 0x1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write RXUFE_0 RXUF flag does not generate an interrupt to the host. 0 RXUFE_1 RXUF flag generates an interrupt to the host. 0x1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write TXOFE_0 TXOF flag does not generate an interrupt to the host. 0 TXOFE_1 TXOF flag generates an interrupt to the host. 0x1 RXIDEN Receiver Idle Empty Enable 10 3 read-write RXIDEN_0 Disable RDRF assertion due to partially filled FIFO when receiver is idle. 0 RXIDEN_1 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. 0x1 RXIDEN_2 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. 0x2 RXIDEN_3 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. 0x3 RXIDEN_4 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. 0x4 RXIDEN_5 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. 0x5 RXIDEN_6 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. 0x6 RXIDEN_7 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. 0x7 RXFLUSH Receive FIFO/Buffer Flush 14 1 read-write RXFLUSH_0 No flush operation occurs. 0 RXFLUSH_1 All data in the receive FIFO/buffer is cleared out. 0x1 TXFLUSH Transmit FIFO/Buffer Flush 15 1 read-write TXFLUSH_0 No flush operation occurs. 0 TXFLUSH_1 All data in the transmit FIFO/Buffer is cleared out. 0x1 RXUF Receiver Buffer Underflow Flag 16 1 read-write oneToClear RXUF_0 No receive buffer underflow has occurred since the last time the flag was cleared. 0 RXUF_1 At least one receive buffer underflow has occurred since the last time the flag was cleared. 0x1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write oneToClear TXOF_0 No transmit buffer overflow has occurred since the last time the flag was cleared. 0 TXOF_1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. 0x1 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only RXEMPT_0 Receive buffer is not empty. 0 RXEMPT_1 Receive buffer is empty. 0x1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only TXEMPT_0 Transmit buffer is not empty. 0 TXEMPT_1 Transmit buffer is empty. 0x1 WATER LPUART Watermark Register 0x2C 32 read-write 0 0xFFFFFFFF TXWATER Transmit Watermark 0 2 read-write TXCOUNT Transmit Counter 8 3 read-only RXWATER Receive Watermark 16 2 read-write RXCOUNT Receive Counter 24 3 read-only LPUART1 LPUART LPUART 0x4006B000 0 0x30 registers LPUART2 LPUART LPUART 0x4006C000 0 0x30 registers CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP CMP0_ 0x40073000 0 0xC registers C0 CMP Control Register 0 0 32 read-write 0 0xFFFFFFFF HYSTCTR Comparator hard block hysteresis control. See chip data sheet to get the actual hysteresis value with each level 0 2 read-write HYSTCTR_0 The hard block output has level 0 hysteresis internally. 0 HYSTCTR_1 The hard block output has level 1 hysteresis internally. 0x1 HYSTCTR_2 The hard block output has level 2 hysteresis internally. 0x2 HYSTCTR_3 The hard block output has level 3 hysteresis internally. 0x3 OFFSET Comparator hard block offset control. See chip data sheet to get the actual offset value with each level 2 1 read-write OFFSET_0 The comparator hard block output has level 0 offset internally. 0 OFFSET_1 The comparator hard block output has level 1 offset internally. 0x1 FILTER_CNT Filter Sample Count 4 3 read-write FILTER_CNT_0 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. 0 FILTER_CNT_1 1 consecutive sample must agree (comparator output is simply sampled). 0x1 FILTER_CNT_2 2 consecutive samples must agree. 0x2 FILTER_CNT_3 3 consecutive samples must agree. 0x3 FILTER_CNT_4 4 consecutive samples must agree. 0x4 FILTER_CNT_5 5 consecutive samples must agree. 0x5 FILTER_CNT_6 6 consecutive samples must agree. 0x6 FILTER_CNT_7 7 consecutive samples must agree. 0x7 EN Comparator Module Enable 8 1 read-write EN_0 Analog Comparator is disabled. 0 EN_1 Analog Comparator is enabled. 0x1 OPE Comparator Output Pin Enable 9 1 read-write OPE_0 When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin. 0 OPE_1 When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin. 0x1 COS Comparator Output Select 10 1 read-write COS_0 Set CMPO to equal COUT (filtered comparator output). 0 COS_1 Set CMPO to equal COUTA (unfiltered comparator output). 0x1 INVT Comparator invert 11 1 read-write INVT_0 Does not invert the comparator output. 0 INVT_1 Inverts the comparator output. 0x1 PMODE Power Mode Select 12 1 read-write PMODE_0 Low Speed (LS) comparison mode is selected. 0 PMODE_1 High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode. 0x1 WE Windowing Enable 14 1 read-write WE_0 Windowing mode is not selected. 0 WE_1 Windowing mode is selected. 0x1 SE Sample Enable 15 1 read-write SE_0 Sampling mode is not selected. 0 SE_1 Sampling mode is selected. 0x1 FPR Filter Sample Period 16 8 read-write COUT Analog Comparator Output 24 1 read-only CFF Analog Comparator Flag Falling 25 1 read-write oneToClear CFF_0 A falling edge has not been detected on COUT. 0 CFF_1 A falling edge on COUT has occurred. 0x1 CFR Analog Comparator Flag Rising 26 1 read-write oneToClear CFR_0 A rising edge has not been detected on COUT. 0 CFR_1 A rising edge on COUT has occurred. 0x1 IEF Comparator Interrupt Enable Falling 27 1 read-write IEF_0 Interrupt is disabled. 0 IEF_1 Interrupt is enabled. 0x1 IER Comparator Interrupt Enable Rising 28 1 read-write IER_0 Interrupt is disabled. 0 IER_1 Interrupt is enabled. 0x1 DMAEN DMA Enable 30 1 read-write DMAEN_0 DMA is disabled. 0 DMAEN_1 DMA is enabled. 0x1 C1 CMP Control Register 1 0x4 32 read-write 0 0xFFFFFFFF VOSEL DAC Output Voltage Select 0 8 read-write MSEL Minus Input MUX Control 8 3 read-write MSEL_0 IN0 0 MSEL_1 IN1 0x1 MSEL_2 IN2 0x2 MSEL_3 IN3 0x3 MSEL_4 IN4 0x4 MSEL_5 IN5 0x5 MSEL_6 IN6 0x6 MSEL_7 IN7 0x7 PSEL Plus Input MUX Control 11 3 read-write PSEL_0 IN0 0 PSEL_1 IN1 0x1 PSEL_2 IN2 0x2 PSEL_3 IN3 0x3 PSEL_4 IN4 0x4 PSEL_5 IN5 0x5 PSEL_6 IN6 0x6 PSEL_7 IN7 0x7 VRSEL Supply Voltage Reference Source Select 14 1 read-write VRSEL_0 Vin1 is selected as resistor ladder network supply reference Vin. 0 VRSEL_1 Vin2 is selected as resistor ladder network supply reference Vin. 0x1 DACEN DAC Enable 15 1 read-write DACEN_0 DAC is disabled. 0 DACEN_1 DAC is enabled. 0x1 CHN0 Channel 0 input enable 16 1 read-write CHN1 Channel 1 input enable 17 1 read-write CHN2 Channel 2 input enable 18 1 read-write CHN3 Channel 3 input enable 19 1 read-write CHN4 Channel 4 input enable 20 1 read-write CHN5 Channel 5 input enable 21 1 read-write CHN6 Channel 6 input enable 22 1 read-write CHN7 Channel 7 input enable 23 1 read-write INNSEL Selection of the input to the negative port of the comparator 24 2 read-write INNSEL_0 IN0, from the 8-bit DAC output 0 INNSEL_1 IN1, from the analog 8-1 mux 0x1 INPSEL Selection of the input to the positive port of the comparator 27 2 read-write INPSEL_0 IN0, from the 8-bit DAC output 0 INPSEL_1 IN1, from the analog 8-1 mux 0x1 C2 CMP Control Register 2 0x8 32 read-write 0 0xFFFFFFFF ACOn The result of the input comparison for channel n 0 8 read-write INITMOD Comparator and DAC initialization delay modulus. 8 6 read-write INITMOD_0 The modulus is set to 64 (same with 111111). 0 NSAM Number of sample clocks 14 2 read-write NSAM_0 The comparison result is sampled as soon as the active channel is scanned in one round-robin clock. 0 NSAM_1 The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock. 0x1 NSAM_2 The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock. 0x2 NSAM_3 The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock. 0x3 CH0F Channel 0 input changed flag 16 1 read-write oneToClear CH1F Channel 1 input changed flag 17 1 read-write oneToClear CH2F Channel 2 input changed flag 18 1 read-write oneToClear CH3F Channel 3 input changed flag 19 1 read-write oneToClear CH4F Channel 4 input changed flag 20 1 read-write oneToClear CH5F Channel 5 input changed flag 21 1 read-write oneToClear CH6F Channel 6 input changed flag 22 1 read-write oneToClear CH7F Channel 7 input changed flag 23 1 read-write oneToClear FXMXCH Fixed channel selection 25 3 read-write FXMXCH_0 Channel 0 is selected as the fixed reference input for the fixed mux port. 0 FXMXCH_1 Channel 1 is selected as the fixed reference input for the fixed mux port. 0x1 FXMXCH_2 Channel 2 is selected as the fixed reference input for the fixed mux port. 0x2 FXMXCH_3 Channel 3 is selected as the fixed reference input for the fixed mux port. 0x3 FXMXCH_4 Channel 4 is selected as the fixed reference input for the fixed mux port. 0x4 FXMXCH_5 Channel 5 is selected as the fixed reference input for the fixed mux port. 0x5 FXMXCH_6 Channel 6 is selected as the fixed reference input for the fixed mux port. 0x6 FXMXCH_7 Channel 7 is selected as the fixed reference input for the fixed mux port. 0x7 FXMP Fixed MUX Port 29 1 read-write FXMP_0 The Plus port is fixed. Only the inputs to the Minus port are swept in each round. 0 FXMP_1 The Minus port is fixed. Only the inputs to the Plus port are swept in each round. 0x1 RRIE Round-Robin interrupt enable 30 1 read-write RRIE_0 The round-robin interrupt is disabled. 0 RRIE_1 The round-robin interrupt is enabled when a comparison result changes from the last sample. 0x1 RRE Round-Robin Enable 31 1 read-write RRE_0 Round-robin operation is disabled. 0 RRE_1 Round-robin operation is enabled. 0x1 PMC PMC PMC 0x4007D000 0 0x5 registers LVDSC2 Low Voltage Detect Status and Control 2 Register 0x1 8 read-write 0 0xFF LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write LVWIE_0 Hardware interrupt disabled (use polling) 0 LVWIE_1 Request a hardware interrupt when LVWF=1 0x1 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only LVWF_0 Low-voltage warning event not detected 0 LVWF_1 Low-voltage warning event detected 0x1 REGSC Regulator Status and Control Register 0x2 8 read-write 0x4 0xBF BIASEN Bias Enable Bit 0 1 read-write BIASEN_0 Biasing disabled, core logic can run in full performance 0 BIASEN_1 Biasing enabled, core logic is slower and there are restrictions in allowed system clock speed (see Data Sheet for details) 0x1 CLKBIASDIS Clock Bias Disable Bit 1 1 read-write CLKBIASDIS_0 No effect 0 CLKBIASDIS_1 In VLPS mode, the bias currents and reference voltages for the following clock modules are disabled: SIRC, FIRC, PLL. (if available on device) 0x1 REGFPM Regulator in Full Performance Mode Status Bit 2 1 read-only REGFPM_0 Regulator is in low power mode or transition to/from 0 REGFPM_1 Regulator is in full performance mode 0x1 LPOSTAT LPO Status Bit 6 1 read-only LPOSTAT_0 Low power oscillator in low phase 0 LPOSTAT_1 Low power oscillator in high phase 0x1 LPODIS LPO Disable Bit 7 1 read-write LPODIS_0 Low power oscillator enabled 0 LPODIS_1 Low power oscillator disabled 0x1 LVRFLG Low Voltage Reset Flags Register 0x3 8 read-write 0 0x40 LVRF LVR Core Flag 0 1 read-write oneToClear LVRLPF LVR in low power mode core Flag 1 1 read-write oneToClear LVRXF LVR External Flag 2 1 read-write oneToClear LVRXLPF LVR external in low power mode flag 3 1 read-write oneToClear LVR3F LVR 3V Flag 4 1 read-write oneToClear LVR3FLSF LVR 3V Flash memory Flag 5 1 read-write oneToClear PORF POR Flag 7 1 read-write oneToClear LPOTRIM Low Power Oscillator Trim Register 0x4 8 read-write 0 0xE0 LPOTRIM LPO trimming bits 0 5 read-write SMC System Mode Controller SMC SMC_ 0x4007E000 0 0x18 registers VERID SMC Version ID Register 0 32 read-only 0x1000000 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only FEATURE_0 Standard features implemented 0 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM SMC Parameter Register 0x4 32 read-only 0 0xFFFFFFFF EHSRUN Existence of HSRUN feature 0 1 read-only EHSRUN_0 The feature is not available. 0 EHSRUN_1 The feature is available. 0x1 ELLS Existence of LLS feature 3 1 read-only ELLS_0 The feature is not available. 0 ELLS_1 The feature is available. 0x1 ELLS2 Existence of LLS2 feature 5 1 read-only ELLS2_0 The feature is not available. 0 ELLS2_1 The feature is available. 0x1 EVLLS0 Existence of VLLS0 feature 6 1 read-only EVLLS0_0 The feature is not available. 0 EVLLS0_1 The feature is available. 0x1 PMPROT Power Mode Protection register 0x8 32 read-write 0 0xFFFFFFFF AVLP Allow Very-Low-Power Modes 5 1 read-write AVLP_0 VLPR and VLPS are not allowed. 0 AVLP_1 VLPR and VLPS are allowed. 0x1 PMCTRL Power Mode Control register 0xC 32 read-write 0 0xFFFFFFFF STOPM Stop Mode Control 0 3 read-write STOPM_0 Normal Stop (STOP) 0 STOPM_2 Very-Low-Power Stop (VLPS) 0x2 STOPM_6 Reseved 0x6 VLPSA Very Low Power Stop Aborted 3 1 read-only VLPSA_0 The previous stop mode entry was successful. 0 VLPSA_1 The previous stop mode entry was aborted. 0x1 RUNM Run Mode Control 5 2 read-write RUNM_0 Normal Run mode (RUN) 0 RUNM_2 Very-Low-Power Run mode (VLPR) 0x2 STOPCTRL Stop Control Register 0x10 32 read-write 0x3 0xFFFFFFFF STOPO Stop Option 6 2 read-write STOPO_1 STOP1 - Stop with both system and bus clocks disabled 0x1 STOPO_2 STOP2 - Stop with system clock disabled and bus clock enabled 0x2 PMSTAT Power Mode Status register 0x14 32 read-only 0x1 0xFFFFFFFF PMSTAT Power Mode Status 0 8 read-only RCM Reset Control Module RCM RCM_ 0x4007F000 0 0x20 registers VERID Version ID Register 0 32 read-only 0x3000003 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only FEATURE_3 Standard feature set. 0x3 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x2FEE 0xFFFFFFFF EWAKEUP Existence of SRS[WAKEUP] status indication feature 0 1 read-only EWAKEUP_0 The feature is not available. 0 EWAKEUP_1 The feature is available. 0x1 ELVD Existence of SRS[LVD] status indication feature 1 1 read-only ELVD_0 The feature is not available. 0 ELVD_1 The feature is available. 0x1 ELOC Existence of SRS[LOC] status indication feature 2 1 read-only ELOC_0 The feature is not available. 0 ELOC_1 The feature is available. 0x1 ELOL Existence of SRS[LOL] status indication feature 3 1 read-only ELOL_0 The feature is not available. 0 ELOL_1 The feature is available. 0x1 ECMU_LOC Existence of SRS[CMU_LOC] status indication feature 4 1 read-only ECMU_LOC_0 The feature is not available. 0 ECMU_LOC_1 The feature is available. 0x1 EWDOG Existence of SRS[WDOG] status indication feature 5 1 read-only EWDOG_0 The feature is not available. 0 EWDOG_1 The feature is available. 0x1 EPIN Existence of SRS[PIN] status indication feature 6 1 read-only EPIN_0 The feature is not available. 0 EPIN_1 The feature is available. 0x1 EPOR Existence of SRS[POR] status indication feature 7 1 read-only EPOR_0 The feature is not available. 0 EPOR_1 The feature is available. 0x1 EJTAG Existence of SRS[JTAG] status indication feature 8 1 read-only EJTAG_0 The feature is not available. 0 EJTAG_1 The feature is available. 0x1 ELOCKUP Existence of SRS[LOCKUP] status indication feature 9 1 read-only ELOCKUP_0 The feature is not available. 0 ELOCKUP_1 The feature is available. 0x1 ESW Existence of SRS[SW] status indication feature 10 1 read-only ESW_0 The feature is not available. 0 ESW_1 The feature is available. 0x1 EMDM_AP Existence of SRS[MDM_AP] status indication feature 11 1 read-only EMDM_AP_0 The feature is not available. 0 EMDM_AP_1 The feature is available. 0x1 ESACKERR Existence of SRS[SACKERR] status indication feature 13 1 read-only ESACKERR_0 The feature is not available. 0 ESACKERR_1 The feature is available. 0x1 ETAMPER Existence of SRS[TAMPER] status indication feature 15 1 read-only ETAMPER_0 The feature is not available. 0 ETAMPER_1 The feature is available. 0x1 ECORE1 Existence of SRS[CORE1] status indication feature 16 1 read-only ECORE1_0 The feature is not available. 0 ECORE1_1 The feature is available. 0x1 SRS System Reset Status Register 0x8 32 read-only 0x82 0xFFFFFFFF LVD Low-Voltage Detect Reset or High-Voltage Detect Reset 1 1 read-only LVD_0 Reset not caused by LVD trip, HVD trip or POR 0 LVD_1 Reset caused by LVD trip, HVD trip or POR 0x1 LOC Loss-of-Clock Reset 2 1 read-only LOC_0 Reset not caused by a loss of external clock. 0 LOC_1 Reset caused by a loss of external clock. 0x1 LOL Loss-of-Lock Reset 3 1 read-only LOL_0 Reset not caused by a loss of lock in the PLL/FLL 0 LOL_1 Reset caused by a loss of lock in the PLL/FLL 0x1 WDOG Watchdog 5 1 read-only WDOG_0 Reset not caused by watchdog timeout 0 WDOG_1 Reset caused by watchdog timeout 0x1 PIN External Reset Pin 6 1 read-only PIN_0 Reset not caused by external reset pin 0 PIN_1 Reset caused by external reset pin 0x1 POR Power-On Reset 7 1 read-only POR_0 Reset not caused by POR 0 POR_1 Reset caused by POR 0x1 JTAG JTAG generated reset 8 1 read-only JTAG_0 Reset not caused by JTAG 0 JTAG_1 Reset caused by JTAG 0x1 LOCKUP Core Lockup 9 1 read-only LOCKUP_0 Reset not caused by core LOCKUP event 0 LOCKUP_1 Reset caused by core LOCKUP event 0x1 SW Software 10 1 read-only SW_0 Reset not caused by software setting of SYSRESETREQ bit 0 SW_1 Reset caused by software setting of SYSRESETREQ bit 0x1 MDM_AP MDM-AP System Reset Request 11 1 read-only MDM_AP_0 Reset was not caused by host debugger system setting of the System Reset Request bit 0 MDM_AP_1 Reset was caused by host debugger system setting of the System Reset Request bit 0x1 SACKERR Stop Acknowledge Error 13 1 read-only SACKERR_0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode 0 SACKERR_1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode 0x1 RPC Reset Pin Control register 0xC 32 read-write 0 0xFFFFFFFF RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes 0 2 read-write RSTFLTSRW_0 All filtering disabled 0 RSTFLTSRW_1 Bus clock filter enabled for normal operation 0x1 RSTFLTSRW_2 LPO clock filter enabled for normal operation 0x2 RSTFLTSS Reset Pin Filter Select in Stop Mode 2 1 read-write RSTFLTSS_0 All filtering disabled 0 RSTFLTSS_1 LPO clock filter enabled 0x1 RSTFLTSEL Reset Pin Filter Bus Clock Select 8 5 read-write SSRS Sticky System Reset Status Register 0x18 32 read-write 0x82 0xFFFFFFFF SLVD Sticky Low-Voltage Detect Reset 1 1 read-write oneToClear SLVD_0 Reset not caused by LVD trip or POR 0 SLVD_1 Reset caused by LVD trip or POR 0x1 SLOC Sticky Loss-of-Clock Reset 2 1 read-write oneToClear SLOC_0 Reset not caused by a loss of external clock. 0 SLOC_1 Reset caused by a loss of external clock. 0x1 SLOL Sticky Loss-of-Lock Reset 3 1 read-write oneToClear SLOL_0 Reset not caused by a loss of lock in the PLL/FLL 0 SLOL_1 Reset caused by a loss of lock in the PLL/FLL 0x1 SWDOG Sticky Watchdog 5 1 read-write oneToClear SWDOG_0 Reset not caused by watchdog timeout 0 SWDOG_1 Reset caused by watchdog timeout 0x1 SPIN Sticky External Reset Pin 6 1 read-write oneToClear SPIN_0 Reset not caused by external reset pin 0 SPIN_1 Reset caused by external reset pin 0x1 SPOR Sticky Power-On Reset 7 1 read-write oneToClear SPOR_0 Reset not caused by POR 0 SPOR_1 Reset caused by POR 0x1 SJTAG Sticky JTAG generated reset 8 1 read-write oneToClear SJTAG_0 Reset not caused by JTAG 0 SJTAG_1 Reset caused by JTAG 0x1 SLOCKUP Sticky Core Lockup 9 1 read-write oneToClear SLOCKUP_0 Reset not caused by core LOCKUP event 0 SLOCKUP_1 Reset caused by core LOCKUP event 0x1 SSW Sticky Software 10 1 read-write oneToClear SSW_0 Reset not caused by software setting of SYSRESETREQ bit 0 SSW_1 Reset caused by software setting of SYSRESETREQ bit 0x1 SMDM_AP Sticky MDM-AP System Reset Request 11 1 read-write oneToClear SMDM_AP_0 Reset was not caused by host debugger system setting of the System Reset Request bit 0 SMDM_AP_1 Reset was caused by host debugger system setting of the System Reset Request bit 0x1 SSACKERR Sticky Stop Acknowledge Error 13 1 read-write oneToClear SSACKERR_0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode 0 SSACKERR_1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode 0x1 SRIE System Reset Interrupt Enable Register 0x1C 32 read-write 0 0xFFFFFFFF DELAY Reset Delay Time 0 2 read-write DELAY_0 10 LPO cycles 0 DELAY_1 34 LPO cycles 0x1 DELAY_2 130 LPO cycles 0x2 DELAY_3 514 LPO cycles 0x3 LOC Loss-of-Clock Interrupt 2 1 read-write LOC_0 Interrupt disabled. 0 LOC_1 Interrupt enabled. 0x1 LOL Loss-of-Lock Interrupt 3 1 read-write LOL_0 Interrupt disabled. 0 LOL_1 Interrupt enabled. 0x1 WDOG Watchdog Interrupt 5 1 read-write WDOG_0 Interrupt disabled. 0 WDOG_1 Interrupt enabled. 0x1 PIN External Reset Pin Interrupt 6 1 read-write PIN_0 Reset not caused by external reset pin 0 PIN_1 Reset caused by external reset pin 0x1 GIE Global Interrupt Enable 7 1 read-write GIE_0 All interrupt sources disabled. 0 GIE_1 All interrupt sources enabled. Note that the individual interrupt-enable bits still need to be set to generate interrupts. 0x1 JTAG JTAG generated reset 8 1 read-write JTAG_0 Interrupt disabled. 0 JTAG_1 Interrupt enabled. 0x1 LOCKUP Core Lockup Interrupt 9 1 read-write LOCKUP_0 Interrupt disabled. 0 LOCKUP_1 Interrupt enabled. 0x1 SW Software Interrupt 10 1 read-write SW_0 Interrupt disabled. 0 SW_1 Interrupt enabled. 0x1 MDM_AP MDM-AP System Reset Request 11 1 read-write MDM_AP_0 Interrupt disabled. 0 MDM_AP_1 Interrupt enabled. 0x1 SACKERR Stop Acknowledge Error Interrupt 13 1 read-write SACKERR_0 Interrupt disabled. 0 SACKERR_1 Interrupt enabled. 0x1 PTA GPIO GPIO GPIO 0x400FF000 0 0x1C registers PDOR Port Data Output Register 0 32 read-write 0 0xFFFFFFFF PDO Port Data Output 0 32 read-write PSOR Port Set Output Register 0x4 32 read-write 0 0xFFFFFFFF PTSO Port Set Output 0 32 read-write PCOR Port Clear Output Register 0x8 32 read-write 0 0xFFFFFFFF PTCO Port Clear Output 0 32 read-write PTOR Port Toggle Output Register 0xC 32 read-write 0 0xFFFFFFFF PTTO Port Toggle Output 0 32 read-write PDIR Port Data Input Register 0x10 32 read-only 0 0xFFFFFFFF PDI Port Data Input 0 32 read-only PDDR Port Data Direction Register 0x14 32 read-write 0 0xFFFFFFFF PDD Port Data Direction 0 32 read-write PIDR Port Input Disable Register 0x18 32 read-write 0 0xFFFFFFFF PID Port Input Disable 0 32 read-write PTB GPIO GPIO 0x400FF040 0 0x1C registers PTC GPIO GPIO 0x400FF080 0 0x1C registers PTD GPIO GPIO 0x400FF0C0 0 0x1C registers PTE GPIO GPIO 0x400FF100 0 0x1C registers MCM Core Platform Miscellaneous Control Module MCM MCM_ 0xE0080000 0 0x4A8 registers PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only 0x7 0xFFFF ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only ASC_0 A bus slave connection to AXBS input port n is absent 0 ASC_1 A bus slave connection to AXBS input port n is present 0x1 PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only 0x7 0xFFFF AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only AMC_0 A bus master connection to AXBS input port n is absent 0 AMC_1 A bus master connection to AXBS input port n is present 0x1 CPCR Core Platform Control Register 0xC 32 read-write 0 0xFFFFFFAF HLT_FSM_ST AXBS Halt State Machine Status 0 2 read-only HLT_FSM_ST_0 Waiting for request 0 HLT_FSM_ST_1 Waiting for platform idle 0x1 HLT_FSM_ST_2 Unused state 0x2 HLT_FSM_ST_3 Platform stalled 0x3 AXBS_HLT_REQ AXBS Halt Request 2 1 read-only AXBS_HLT_REQ_0 AXBS is not receiving halt request 0 AXBS_HLT_REQ_1 AXBS is receiving halt request 0x1 AXBS_HLTD AXBS Halted 3 1 read-only AXBS_HLTD_0 AXBS is not currently halted 0 AXBS_HLTD_1 AXBS is currently halted 0x1 FMC_PF_IDLE Flash Memory Controller Program Flash Idle 4 1 read-only FMC_PF_IDLE_0 FMC program flash is not idle 0 FMC_PF_IDLE_1 FMC program flash is currently idle 0x1 PBRIDGE_IDLE Peripheral Bridge Idle 6 1 read-only PBRIDGE_IDLE_0 PBRIDGE is not idle 0 PBRIDGE_IDLE_1 PBRIDGE is currently idle 0x1 CBRR Crossbar Round-robin Arbitration Enable 9 1 read-write CBRR_0 Fixed-priority arbitration 0 CBRR_1 Round-robin arbitration 0x1 SRAMUAP SRAM_U Arbitration Priority 24 2 read-write SRAMUAP_0 Round robin 0 SRAMUAP_1 Special round robin (favors SRAM backdoor accesses over the processor) 0x1 SRAMUAP_2 Fixed priority. Processor has highest, backdoor has lowest 0x2 SRAMUAP_3 Fixed priority. Backdoor has highest, processor has lowest 0x3 SRAMUWP SRAM_U Write Protect 26 1 read-write SRAMLAP SRAM_L Arbitration Priority 28 2 read-write SRAMLAP_0 Round robin 0 SRAMLAP_1 Special round robin (favors SRAM backdoor accesses over the processor) 0x1 SRAMLAP_2 Fixed priority. Processor has highest, backdoor has lowest 0x2 SRAMLAP_3 Fixed priority. Backdoor has highest, processor has lowest 0x3 SRAMLWP SRAM_L Write Protect 30 1 read-write ISCR Interrupt Status and Control Register 0x10 32 read-write 0x20000 0xFFFFFFFF FIOC FPU Invalid Operation Interrupt Status 8 1 read-only FIOC_0 No interrupt 0 FIOC_1 Interrupt occurred 0x1 FDZC FPU Divide-by-Zero Interrupt Status 9 1 read-only FDZC_0 No interrupt 0 FDZC_1 Interrupt occurred 0x1 FOFC FPU Overflow Interrupt Status 10 1 read-only FOFC_0 No interrupt 0 FOFC_1 Interrupt occurred 0x1 FUFC FPU Underflow Interrupt Status 11 1 read-only FUFC_0 No interrupt 0 FUFC_1 Interrupt occurred 0x1 FIXC FPU Inexact Interrupt Status 12 1 read-only FIXC_0 No interrupt 0 FIXC_1 Interrupt occurred 0x1 FIDC FPU Input Denormal Interrupt Status 15 1 read-only FIDC_0 No interrupt 0 FIDC_1 Interrupt occurred 0x1 FIOCE FPU Invalid Operation Interrupt Enable 24 1 read-write FIOCE_0 Disable interrupt 0 FIOCE_1 Enable interrupt 0x1 FDZCE FPU Divide-by-Zero Interrupt Enable 25 1 read-write FDZCE_0 Disable interrupt 0 FDZCE_1 Enable interrupt 0x1 FOFCE FPU Overflow Interrupt Enable 26 1 read-write FOFCE_0 Disable interrupt 0 FOFCE_1 Enable interrupt 0x1 FUFCE FPU Underflow Interrupt Enable 27 1 read-write FUFCE_0 Disable interrupt 0 FUFCE_1 Enable interrupt 0x1 FIXCE FPU Inexact Interrupt Enable 28 1 read-write FIXCE_0 Disable interrupt 0 FIXCE_1 Enable interrupt 0x1 FIDCE FPU Input Denormal Interrupt Enable 31 1 read-write FIDCE_0 Disable interrupt 0 FIDCE_1 Enable interrupt 0x1 PID Process ID Register 0x30 32 read-write 0 0xFFFFFFFF PID M0_PID and M1_PID for MPU 0 8 read-write CPO Compute Operation Control Register 0x40 32 read-write 0 0xFFFFFFFF CPOREQ Compute Operation Request 0 1 read-write CPOREQ_0 Request is cleared. 0 CPOREQ_1 Request Compute Operation. 0x1 CPOACK Compute Operation Acknowledge 1 1 read-only CPOACK_0 Compute operation entry has not completed or compute operation exit has completed. 0 CPOACK_1 Compute operation entry has completed or compute operation exit has not completed. 0x1 CPOWOI Compute Operation Wakeup On Interrupt 2 1 read-write CPOWOI_0 No effect. 0 CPOWOI_1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch. 0x1 2 0x4 0,1 LMDR%s Local Memory Descriptor Register 0x400 32 read-write 0 0 CF0 Control Field 0 LMDR0[CF0] bit field is Reserved and Read-Only 0 for S32K11x variants. 0 4 read-write MT Memory Type 13 3 read-only MT_0 SRAM_L 0 MT_1 SRAM_U 0x1 LOCK LOCK 16 1 read-write LOCK_0 Writes to the LMDRn[7:0] are allowed. 0 LOCK_1 Writes to the LMDRn[7:0] are ignored. 0x1 DPW LMEM Data Path Width. This field defines the width of the local memory. 17 3 read-only DPW_2 LMEMn 32-bits wide 0x2 DPW_3 LMEMn 64-bits wide 0x3 WY Level 1 Cache Ways 20 4 read-only WY_0 No Cache 0 WY_2 2-Way Set Associative 0x2 WY_4 4-Way Set Associative 0x4 LMSZ LMEM Size 24 4 read-only LMSZ_0 no LMEMn (0 KB) 0 LMSZ_1 1 KB LMEMn 0x1 LMSZ_2 2 KB LMEMn 0x2 LMSZ_3 4 KB LMEMn 0x3 LMSZ_4 8 KB LMEMn 0x4 LMSZ_5 16 KB LMEMn 0x5 LMSZ_6 32 KB LMEMn 0x6 LMSZ_7 64 KB LMEMn 0x7 LMSZ_8 128 KB LMEMn 0x8 LMSZ_9 256 KB LMEMn 0x9 LMSZ_10 512 KB LMEMn 0xA LMSZ_11 1024 KB LMEMn 0xB LMSZ_12 2048 KB LMEMn 0xC LMSZ_13 4096 KB LMEMn 0xD LMSZ_14 8192 KB LMEMn 0xE LMSZ_15 16384 KB LMEMn 0xF LMSZH LMEM Size Hole 28 1 read-only LMSZH_0 LMEMn is a power-of-2 capacity. 0 LMSZH_1 LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ. 0x1 V Local Memory Valid 31 1 read-only V_0 LMEMn is not present. 0 V_1 LMEMn is present. 0x1 LMDR2 Local Memory Descriptor Register2 0x408 32 read-write 0x842440A0 0xFFFFFFFF CF1 Control Field 1 4 4 read-write MT Memory Type 13 3 read-only MT_2 PC Cache 0x2 LOCK LOCK 16 1 read-write LOCK_0 Writes to the LMDRn[7:0] are allowed. 0 LOCK_1 Writes to the LMDRn[7:0] are ignored. 0x1 DPW LMEM Data Path Width. This field defines the width of the local memory. 17 3 read-only DPW_2 LMEMn 32-bits wide 0x2 DPW_3 LMEMn 64-bits wide 0x3 WY Level 1 Cache Ways 20 4 read-only WY_0 No Cache 0 WY_2 2-Way Set Associative 0x2 WY_4 4-Way Set Associative 0x4 LMSZ LMEM Size 24 4 read-only LMSZ_4 4 KB LMEMn 0x4 LMSZH LMEM Size Hole 28 1 read-only LMSZH_0 LMEMn is a power-of-2 capacity. 0 LMSZH_1 LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ. 0x1 V Local Memory Valid 31 1 read-only V_0 LMEMn is not present. 0 V_1 LMEMn is present. 0x1 LMPECR LMEM Parity and ECC Control Register 0x480 32 read-write 0 0xFFFFFFFF ERNCR Enable RAM ECC Noncorrectable Reporting This bit field is Reserved and Read-Only 0 for S32K11x variants. This bit field cannot mask ECC reporting, as a result the ECC would always be reported. 0 1 read-write ERNCR_0 Reporting disabled 0 ERNCR_1 Reporting enabled 0x1 ER1BR Enable RAM ECC 1 Bit Reporting This bit field is Reserved and Read-Only 0 for S32K11x variants. This bit field cannot mask ECC reporting, as a result the ECC would always be reported. 8 1 read-write ER1BR_0 Reporting disabled 0 ER1BR_1 Reporting enabled 0x1 ECPR Enable Cache Parity Reporting 20 1 read-write ECPR_0 Reporting disabled 0 ECPR_1 Reporting enabled 0x1 LMPEIR LMEM Parity and ECC Interrupt Register 0x488 32 read-write 0 0xFFFFFFFF ENC ENCn = ECC Noncorrectable Error n 0 8 read-write oneToClear E1B E1Bn = ECC 1-bit Error n 8 8 read-write oneToClear PE Cache Parity Error 16 8 read-write oneToClear PEELOC Parity or ECC Error Location 24 5 read-only PEELOC_0 Non-correctable ECC event from SRAM_L 0 PEELOC_1 Non-correctable ECC event from SRAM_U 0x1 PEELOC_8 1-bit correctable ECC event from SRAM_L 0x8 PEELOC_9 1-bit correctable ECC event from SRAM_U 0x9 PEELOC_14 PC tag parity error 0xE PEELOC_15 PC data parity error 0xF V Valid Bit 31 1 read-only LMFAR LMEM Fault Address Register 0x490 32 read-only 0 0xFFFFFFFF EFADD ECC Fault Address 0 32 read-only LMFATR LMEM Fault Attribute Register 0x494 32 read-only 0 0xFFFFFFFF PEFPRT Parity/ECC Fault Protection 0 4 read-only PEFSIZE Parity/ECC Fault Master Size 4 3 read-only PEFSIZE_0 8-bit access 0 PEFSIZE_1 16-bit access 0x1 PEFSIZE_2 32-bit access 0x2 PEFSIZE_3 64-bit access 0x3 PEFW Parity/ECC Fault Write 7 1 read-only PEFMST Parity/ECC Fault Master Number 8 8 read-only OVR Overrun 31 1 read-only LMFDHR LMEM Fault Data High Register 0x4A0 32 read-only 0 0xFFFFFFFF PEFDH Parity or ECC Fault Data High 0 32 read-only LMFDLR LMEM Fault Data Low Register 0x4A4 32 read-only 0 0xFFFFFFFF PEFDL Parity or ECC Fault Data Low 0 32 read-only LMEM LMEM LMEM 0xE0082000 0 0x24 registers PCCCR Cache control register 0 32 read-write 0 0xFFFFFFFF ENCACHE Cache enable 0 1 read-write ENCACHE_0 Cache disabled 0 ENCACHE_1 Cache enabled 0x1 PCCR2 Forces all cacheable spaces to write through 2 1 read-write PCCR3 Forces no allocation on cache misses (must also have PCCR2 asserted) 3 1 read-write INVW0 Invalidate Way 0 24 1 read-write INVW0_0 No operation 0 INVW0_1 When setting the GO bit, invalidate all lines in way 0. 0x1 PUSHW0 Push Way 0 25 1 read-write PUSHW0_0 No operation 0 PUSHW0_1 When setting the GO bit, push all modified lines in way 0 0x1 INVW1 Invalidate Way 1 26 1 read-write INVW1_0 No operation 0 INVW1_1 When setting the GO bit, invalidate all lines in way 1 0x1 PUSHW1 Push Way 1 27 1 read-write PUSHW1_0 No operation 0 PUSHW1_1 When setting the GO bit, push all modified lines in way 1 0x1 GO Initiate Cache Command 31 1 read-write GO_0 Write: no effect. Read: no cache command active. 0 GO_1 Write: initiate command indicated by bits 27-24. Read: cache command active. 0x1 PCCLCR Cache line control register 0x4 32 read-write 0 0xFFFFFFFF LGO Initiate Cache Line Command 0 1 read-write LGO_0 Write: no effect. Read: no line command active. 0 LGO_1 Write: initiate line command indicated by bits 27-24. Read: line command active. 0x1 CACHEADDR Cache address 2 12 read-write WSEL Way select 14 1 read-write WSEL_0 Way 0 0 WSEL_1 Way 1 0x1 TDSEL Tag/Data Select 16 1 read-write TDSEL_0 Data 0 TDSEL_1 Tag 0x1 LCIVB Line Command Initial Valid Bit 20 1 read-write LCIMB Line Command Initial Modified Bit 21 1 read-write LCWAY Line Command Way 22 1 read-write LCMD Line Command 24 2 read-write LCMD_0 Search and read or write 0 LCMD_1 Invalidate 0x1 LCMD_2 Push 0x2 LCMD_3 Clear 0x3 LADSEL Line Address Select 26 1 read-write LADSEL_0 Cache address 0 LADSEL_1 Physical address 0x1 LACC Line access type 27 1 read-write LACC_0 Read 0 LACC_1 Write 0x1 PCCSAR Cache search address register 0x8 32 read-write 0 0xFFFFFFFF LGO Initiate Cache Line Command 0 1 read-write LGO_0 Write: no effect. Read: no line command active. 0 LGO_1 Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. 0x1 PHYADDR Physical Address 2 30 read-write PCCCVR Cache read/write value register 0xC 32 read-write 0 0xFFFFFFFF DATA Cache read/write Data 0 32 read-write PCCRMR Cache regions mode register 0x20 32 read-write 0xAA0FA000 0xFFFFFFFF R15 Region 15 mode 0 2 read-write R15_0 Non-cacheable 0 R15_1 Non-cacheable 0x1 R15_2 Write-through 0x2 R15_3 Write-back 0x3 R14 Region 14 mode 2 2 read-write R14_0 Non-cacheable 0 R14_1 Non-cacheable 0x1 R14_2 Write-through 0x2 R14_3 Write-back 0x3 R13 Region 13 mode 4 2 read-write R13_0 Non-cacheable 0 R13_1 Non-cacheable 0x1 R13_2 Write-through 0x2 R13_3 Write-back 0x3 R12 Region 12 mode 6 2 read-write R12_0 Non-cacheable 0 R12_1 Non-cacheable 0x1 R12_2 Write-through 0x2 R12_3 Write-back 0x3 R11 Region 11 mode 8 2 read-write R11_0 Non-cacheable 0 R11_1 Non-cacheable 0x1 R11_2 Write-through 0x2 R11_3 Write-back 0x3 R10 Region 10 mode 10 2 read-write R10_0 Non-cacheable 0 R10_1 Non-cacheable 0x1 R10_2 Write-through 0x2 R10_3 Write-back 0x3 R9 Region 9 mode 12 2 read-write R9_0 Non-cacheable 0 R9_1 Non-cacheable 0x1 R9_2 Write-through 0x2 R9_3 Write-back 0x3 R8 Region 8 mode 14 2 read-write R8_0 Non-cacheable 0 R8_1 Non-cacheable 0x1 R8_2 Write-through 0x2 R8_3 Write-back 0x3 R7 Region 7 mode 16 2 read-write R7_0 Non-cacheable 0 R7_1 Non-cacheable 0x1 R7_2 Write-through 0x2 R7_3 Write-back 0x3 R6 Region 6 mode 18 2 read-write R6_0 Non-cacheable 0 R6_1 Non-cacheable 0x1 R6_2 Write-through 0x2 R6_3 Write-back 0x3 R5 Region 5 mode 20 2 read-write R5_0 Non-cacheable 0 R5_1 Non-cacheable 0x1 R5_2 Write-through 0x2 R5_3 Write-back 0x3 R4 Region 4 mode 22 2 read-write R4_0 Non-cacheable 0 R4_1 Non-cacheable 0x1 R4_2 Write-through 0x2 R4_3 Write-back 0x3 R3 Region 3 mode 24 2 read-write R3_0 Non-cacheable 0 R3_1 Non-cacheable 0x1 R3_2 Write-through 0x2 R3_3 Write-back 0x3 R2 Region 2 mode 26 2 read-write R2_0 Non-cacheable 0 R2_1 Non-cacheable 0x1 R2_2 Write-through 0x2 R2_3 Write-back 0x3 R1 Region 1 mode 28 2 read-write R1_0 Non-cacheable 0 R1_1 Non-cacheable 0x1 R1_2 Write-through 0x2 R1_3 Write-back 0x3 R0 Region 0 mode 30 2 read-write R0_0 Non-cacheable 0 R0_1 Non-cacheable 0x1 R0_2 Write-through 0x2 R0_3 Write-back 0x3