Atmel ATSAM3X8E SAM3X 0 Atmel ATSAM3X8E Microcontroller CM3 r2p0 selectable true false 4 false 8 32 HSMCI 6449O High Speed MultiMedia Card Interface HSMCI_ 0x40000000 0 0x4000 registers HSMCI 21 CR Control Register 0x00000000 32 write-only MCIEN Multi-Media Interface Enable 0 1 write-only MCIDIS Multi-Media Interface Disable 1 1 write-only PWSEN Power Save Mode Enable 2 1 write-only PWSDIS Power Save Mode Disable 3 1 write-only SWRST Software Reset 7 1 write-only MR Mode Register 0x00000004 32 read-write 0x00000000 CLKDIV Clock Divider 0 8 read-write PWSDIV Power Saving Divider 8 3 read-write RDPROOF Read Proof Enable 11 1 read-write WRPROOF Write Proof Enable 12 1 read-write FBYTE Force Byte Transfer 13 1 read-write PADV Padding Value 14 1 read-write DTOR Data Timeout Register 0x00000008 32 read-write 0x00000000 DTOCYC Data Timeout Cycle Number 0 4 read-write DTOMUL Data Timeout Multiplier 4 3 read-write 1 DTOCYC 0x0 16 DTOCYC x 16 0x1 128 DTOCYC x 128 0x2 256 DTOCYC x 256 0x3 1024 DTOCYC x 1024 0x4 4096 DTOCYC x 4096 0x5 65536 DTOCYC x 65536 0x6 1048576 DTOCYC x 1048576 0x7 SDCR SD/SDIO Card Register 0x0000000C 32 read-write 0x00000000 SDCSEL SDCard/SDIO Slot 0 2 read-write SLOTA Slot A is selected. 0x0 SLOTB SDCARD/SDIO Slot B selected 0x1 SLOTC - 0x2 SLOTD - 0x3 SDCBUS SDCard/SDIO Bus Width 6 2 read-write 1 1 bit 0x0 4 4 bits 0x2 8 8 bits 0x3 ARGR Argument Register 0x00000010 32 read-write 0x00000000 ARG Command Argument 0 32 read-write CMDR Command Register 0x00000014 32 write-only CMDNB Command Number 0 6 write-only RSPTYP Response Type 6 2 write-only NORESP No response 0x0 48_BIT 48-bit response 0x1 136_BIT 136-bit response 0x2 R1B R1b response type 0x3 SPCMD Special Command 8 3 write-only STD Not a special CMD. 0x0 INIT Initialization CMD: 74 clock cycles for initialization sequence. 0x1 SYNC Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. 0x2 CE_ATA CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. 0x3 IT_CMD Interrupt command: Corresponds to the Interrupt Mode (CMD40). 0x4 IT_RESP Interrupt response: Corresponds to the Interrupt Mode (CMD40). 0x5 BOR Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. 0x6 EBO End Boot Operation. This command allows the host processor to terminate the boot operation mode. 0x7 OPDCMD Open Drain Command 11 1 write-only PUSHPULL Push pull command. 0 OPENDRAIN Open drain command. 1 MAXLAT Max Latency for Command to Response 12 1 write-only 5 5-cycle max latency. 0 64 64-cycle max latency. 1 TRCMD Transfer Command 16 2 write-only NO_DATA No data transfer 0x0 START_DATA Start data transfer 0x1 STOP_DATA Stop data transfer 0x2 TRDIR Transfer Direction 18 1 write-only WRITE Write. 0 READ Read. 1 TRTYP Transfer Type 19 3 write-only SINGLE MMC/SD Card Single Block 0x0 MULTIPLE MMC/SD Card Multiple Block 0x1 STREAM MMC Stream 0x2 BYTE SDIO Byte 0x4 BLOCK SDIO Block 0x5 IOSPCMD SDIO Special Command 24 2 write-only STD Not an SDIO Special Command 0x0 SUSPEND SDIO Suspend Command 0x1 RESUME SDIO Resume Command 0x2 ATACS ATA with Command Completion Signal 26 1 write-only NORMAL Normal operation mode. 0 COMPLETION This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). 1 BOOT_ACK Boot Operation Acknowledge 27 1 write-only BLKR Block Register 0x00000018 32 read-write 0x00000000 BCNT MMC/SDIO Block Count - SDIO Byte Count 0 16 read-write BLKLEN Data Block Length 16 16 read-write CSTOR Completion Signal Timeout Register 0x0000001C 32 read-write 0x00000000 CSTOCYC Completion Signal Timeout Cycle Number 0 4 read-write CSTOMUL Completion Signal Timeout Multiplier 4 3 read-write 1 CSTOCYC x 1 0x0 16 CSTOCYC x 16 0x1 128 CSTOCYC x 128 0x2 256 CSTOCYC x 256 0x3 1024 CSTOCYC x 1024 0x4 4096 CSTOCYC x 4096 0x5 65536 CSTOCYC x 65536 0x6 1048576 CSTOCYC x 1048576 0x7 4 4 0-3 RSPR[%s] Response Register 0x00000020 32 read-only RSP Response 0 32 read-only RDR Receive Data Register 0x00000030 32 read-only 0x00000000 DATA Data to Read 0 32 read-only TDR Transmit Data Register 0x00000034 32 write-only DATA Data to Write 0 32 write-only SR Status Register 0x00000040 32 read-only 0x0000C0E5 CMDRDY Command Ready 0 1 read-only RXRDY Receiver Ready 1 1 read-only TXRDY Transmit Ready 2 1 read-only BLKE Data Block Ended 3 1 read-only DTIP Data Transfer in Progress 4 1 read-only NOTBUSY HSMCI Not Busy 5 1 read-only SDIOIRQforSlotA 8 1 read-only SDIOIRQforSlotB 9 1 read-only SDIOWAIT SDIO Read Wait Operation Status 12 1 read-only CSRCV CE-ATA Completion Signal Received 13 1 read-only RINDE Response Index Error 16 1 read-only RDIRE Response Direction Error 17 1 read-only RCRCE Response CRC Error 18 1 read-only RENDE Response End Bit Error 19 1 read-only RTOE Response Time-out Error 20 1 read-only DCRCE Data CRC Error 21 1 read-only DTOE Data Time-out Error 22 1 read-only CSTOE Completion Signal Time-out Error 23 1 read-only BLKOVRE DMA Block Overrun Error 24 1 read-only DMADONE DMA Transfer done 25 1 read-only FIFOEMPTY FIFO empty flag 26 1 read-only XFRDONE Transfer Done flag 27 1 read-only ACKRCV Boot Operation Acknowledge Received 28 1 read-only ACKRCVE Boot Operation Acknowledge Error 29 1 read-only OVRE Overrun 30 1 read-only UNRE Underrun 31 1 read-only IER Interrupt Enable Register 0x00000044 32 write-only CMDRDY Command Ready Interrupt Enable 0 1 write-only RXRDY Receiver Ready Interrupt Enable 1 1 write-only TXRDY Transmit Ready Interrupt Enable 2 1 write-only BLKE Data Block Ended Interrupt Enable 3 1 write-only DTIP Data Transfer in Progress Interrupt Enable 4 1 write-only NOTBUSY Data Not Busy Interrupt Enable 5 1 write-only SDIOIRQforSlotA 8 1 write-only SDIOIRQforSlotB 9 1 write-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Enable 12 1 write-only CSRCV Completion Signal Received Interrupt Enable 13 1 write-only RINDE Response Index Error Interrupt Enable 16 1 write-only RDIRE Response Direction Error Interrupt Enable 17 1 write-only RCRCE Response CRC Error Interrupt Enable 18 1 write-only RENDE Response End Bit Error Interrupt Enable 19 1 write-only RTOE Response Time-out Error Interrupt Enable 20 1 write-only DCRCE Data CRC Error Interrupt Enable 21 1 write-only DTOE Data Time-out Error Interrupt Enable 22 1 write-only CSTOE Completion Signal Timeout Error Interrupt Enable 23 1 write-only BLKOVRE DMA Block Overrun Error Interrupt Enable 24 1 write-only DMADONE DMA Transfer completed Interrupt Enable 25 1 write-only FIFOEMPTY FIFO empty Interrupt enable 26 1 write-only XFRDONE Transfer Done Interrupt enable 27 1 write-only ACKRCV Boot Acknowledge Interrupt Enable 28 1 write-only ACKRCVE Boot Acknowledge Error Interrupt Enable 29 1 write-only OVRE Overrun Interrupt Enable 30 1 write-only UNRE Underrun Interrupt Enable 31 1 write-only IDR Interrupt Disable Register 0x00000048 32 write-only CMDRDY Command Ready Interrupt Disable 0 1 write-only RXRDY Receiver Ready Interrupt Disable 1 1 write-only TXRDY Transmit Ready Interrupt Disable 2 1 write-only BLKE Data Block Ended Interrupt Disable 3 1 write-only DTIP Data Transfer in Progress Interrupt Disable 4 1 write-only NOTBUSY Data Not Busy Interrupt Disable 5 1 write-only SDIOIRQforSlotA 8 1 write-only SDIOIRQforSlotB 9 1 write-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Disable 12 1 write-only CSRCV Completion Signal received interrupt Disable 13 1 write-only RINDE Response Index Error Interrupt Disable 16 1 write-only RDIRE Response Direction Error Interrupt Disable 17 1 write-only RCRCE Response CRC Error Interrupt Disable 18 1 write-only RENDE Response End Bit Error Interrupt Disable 19 1 write-only RTOE Response Time-out Error Interrupt Disable 20 1 write-only DCRCE Data CRC Error Interrupt Disable 21 1 write-only DTOE Data Time-out Error Interrupt Disable 22 1 write-only CSTOE Completion Signal Time out Error Interrupt Disable 23 1 write-only BLKOVRE DMA Block Overrun Error Interrupt Disable 24 1 write-only DMADONE DMA Transfer completed Interrupt Disable 25 1 write-only FIFOEMPTY FIFO empty Interrupt Disable 26 1 write-only XFRDONE Transfer Done Interrupt Disable 27 1 write-only ACKRCV Boot Acknowledge Interrupt Disable 28 1 write-only ACKRCVE Boot Acknowledge Error Interrupt Disable 29 1 write-only OVRE Overrun Interrupt Disable 30 1 write-only UNRE Underrun Interrupt Disable 31 1 write-only IMR Interrupt Mask Register 0x0000004C 32 read-only 0x00000000 CMDRDY Command Ready Interrupt Mask 0 1 read-only RXRDY Receiver Ready Interrupt Mask 1 1 read-only TXRDY Transmit Ready Interrupt Mask 2 1 read-only BLKE Data Block Ended Interrupt Mask 3 1 read-only DTIP Data Transfer in Progress Interrupt Mask 4 1 read-only NOTBUSY Data Not Busy Interrupt Mask 5 1 read-only SDIOIRQforSlotA 8 1 read-only SDIOIRQforSlotB 9 1 read-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Mask 12 1 read-only CSRCV Completion Signal Received Interrupt Mask 13 1 read-only RINDE Response Index Error Interrupt Mask 16 1 read-only RDIRE Response Direction Error Interrupt Mask 17 1 read-only RCRCE Response CRC Error Interrupt Mask 18 1 read-only RENDE Response End Bit Error Interrupt Mask 19 1 read-only RTOE Response Time-out Error Interrupt Mask 20 1 read-only DCRCE Data CRC Error Interrupt Mask 21 1 read-only DTOE Data Time-out Error Interrupt Mask 22 1 read-only CSTOE Completion Signal Time-out Error Interrupt Mask 23 1 read-only BLKOVRE DMA Block Overrun Error Interrupt Mask 24 1 read-only DMADONE DMA Transfer Completed Interrupt Mask 25 1 read-only FIFOEMPTY FIFO Empty Interrupt Mask 26 1 read-only XFRDONE Transfer Done Interrupt Mask 27 1 read-only ACKRCV Boot Operation Acknowledge Received Interrupt Mask 28 1 read-only ACKRCVE Boot Operation Acknowledge Error Interrupt Mask 29 1 read-only OVRE Overrun Interrupt Mask 30 1 read-only UNRE Underrun Interrupt Mask 31 1 read-only DMA DMA Configuration Register 0x00000050 32 read-write 0x00000000 OFFSET DMA Write Buffer Offset 0 2 read-write CHKSIZE DMA Channel Read and Write Chunk Size 4 1 read-write 1 1 data available 0 4 4 data available 1 DMAEN DMA Hardware Handshaking Enable 8 1 read-write ROPT Read Optimization with padding 12 1 read-write CFG Configuration Register 0x00000054 32 read-write 0x00000000 FIFOMODE HSMCI Internal FIFO control mode 0 1 read-write FERRCTRL Flow Error flag reset control mode 4 1 read-write HSMODE High Speed Mode 8 1 read-write LSYNC Synchronize on the last block 12 1 read-write WPMR Write Protection Mode Register 0x000000E4 32 read-write WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x4D4349 WPSR Write Protection Status Register 0x000000E8 32 read-only WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only 256 4 0-255 FIFO[%s] FIFO Memory Aperture0 0x00000200 32 read-write DATA Data to Read or Data to Write 0 32 read-write SSC 6078M Synchronous Serial Controller SSC_ 0x40004000 0 0x4000 registers SSC 26 CR Control Register 0x00000000 32 write-only RXEN Receive Enable 0 1 write-only RXDIS Receive Disable 1 1 write-only TXEN Transmit Enable 8 1 write-only TXDIS Transmit Disable 9 1 write-only SWRST Software Reset 15 1 write-only CMR Clock Mode Register 0x00000004 32 read-write 0x00000000 DIV Clock Divider 0 12 read-write RCMR Receive Clock Mode Register 0x00000010 32 read-write 0x00000000 CKS Receive Clock Selection 0 2 read-write MCK Divided Clock 0x0 TK TK Clock signal 0x1 RK RK pin 0x2 CKO Receive Clock Output Mode Selection 2 3 read-write NONE None, RK pin is an input 0x0 CONTINUOUS Continuous Receive Clock, RK pin is an output 0x1 TRANSFER Receive Clock only during data transfers, RK pin is an output 0x2 CKI Receive Clock Inversion 5 1 read-write CKG Receive Clock Gating Selection 6 2 read-write CONTINUOUS None 0x0 EN_RF_LOW Receive Clock enabled only if RF Low 0x1 EN_RF_HIGH Receive Clock enabled only if RF High 0x2 START Receive Start Selection 8 4 read-write CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x0 TRANSMIT Transmit start 0x1 RF_LOW Detection of a low level on RF signal 0x2 RF_HIGH Detection of a high level on RF signal 0x3 RF_FALLING Detection of a falling edge on RF signal 0x4 RF_RISING Detection of a rising edge on RF signal 0x5 RF_LEVEL Detection of any level change on RF signal 0x6 RF_EDGE Detection of any edge on RF signal 0x7 CMP_0 Compare 0 0x8 STOP Receive Stop Selection 12 1 read-write STTDLY Receive Start Delay 16 8 read-write PERIOD Receive Period Divider Selection 24 8 read-write RFMR Receive Frame Mode Register 0x00000014 32 read-write 0x00000000 DATLEN Data Length 0 5 read-write LOOP Loop Mode 5 1 read-write MSBF Most Significant Bit First 7 1 read-write DATNB Data Number per Frame 8 4 read-write FSLEN Receive Frame Sync Length 16 4 read-write FSOS Receive Frame Sync Output Selection 20 3 read-write NONE None, RF pin is an input 0x0 NEGATIVE Negative Pulse, RF pin is an output 0x1 POSITIVE Positive Pulse, RF pin is an output 0x2 LOW Driven Low during data transfer, RF pin is an output 0x3 HIGH Driven High during data transfer, RF pin is an output 0x4 TOGGLING Toggling at each start of data transfer, RF pin is an output 0x5 FSEDGE Frame Sync Edge Detection 24 1 read-write POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN_EXT FSLEN Field Extension 28 4 read-write TCMR Transmit Clock Mode Register 0x00000018 32 read-write 0x00000000 CKS Transmit Clock Selection 0 2 read-write MCK Divided Clock 0x0 RK RK Clock signal 0x1 TK TK pin 0x2 CKO Transmit Clock Output Mode Selection 2 3 read-write NONE None, TK pin is an input 0x0 CONTINUOUS Continuous Transmit Clock, TK pin is an output 0x1 TRANSFER Transmit Clock only during data transfers, TK pin is an output 0x2 CKI Transmit Clock Inversion 5 1 read-write CKG Transmit Clock Gating Selection 6 2 read-write CONTINUOUS None 0x0 EN_TF_LOW Transmit Clock enabled only if TF Low 0x1 EN_TF_HIGH Transmit Clock enabled only if TF High 0x2 START Transmit Start Selection 8 4 read-write CONTINUOUS Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data 0x0 RECEIVE Receive start 0x1 TF_LOW Detection of a low level on TF signal 0x2 TF_HIGH Detection of a high level on TF signal 0x3 TF_FALLING Detection of a falling edge on TF signal 0x4 TF_RISING Detection of a rising edge on TF signal 0x5 TF_LEVEL Detection of any level change on TF signal 0x6 TF_EDGE Detection of any edge on TF signal 0x7 STTDLY Transmit Start Delay 16 8 read-write PERIOD Transmit Period Divider Selection 24 8 read-write TFMR Transmit Frame Mode Register 0x0000001C 32 read-write 0x00000000 DATLEN Data Length 0 5 read-write DATDEF Data Default Value 5 1 read-write MSBF Most Significant Bit First 7 1 read-write DATNB Data Number per frame 8 4 read-write FSLEN Transmit Frame Sync Length 16 4 read-write FSOS Transmit Frame Sync Output Selection 20 3 read-write NONE None, RF pin is an input 0x0 NEGATIVE Negative Pulse, RF pin is an output 0x1 POSITIVE Positive Pulse, RF pin is an output 0x2 LOW Driven Low during data transfer 0x3 HIGH Driven High during data transfer 0x4 TOGGLING Toggling at each start of data transfer 0x5 FSDEN Frame Sync Data Enable 23 1 read-write FSEDGE Frame Sync Edge Detection 24 1 read-write POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN_EXT FSLEN Field Extension 28 4 read-write RHR Receive Holding Register 0x00000020 32 read-only 0x00000000 RDAT Receive Data 0 32 read-only THR Transmit Holding Register 0x00000024 32 write-only TDAT Transmit Data 0 32 write-only RSHR Receive Sync. Holding Register 0x00000030 32 read-only 0x00000000 RSDAT Receive Synchronization Data 0 16 read-only TSHR Transmit Sync. Holding Register 0x00000034 32 read-write 0x00000000 TSDAT Transmit Synchronization Data 0 16 read-write RC0R Receive Compare 0 Register 0x00000038 32 read-write 0x00000000 CP0 Receive Compare Data 0 0 16 read-write RC1R Receive Compare 1 Register 0x0000003C 32 read-write 0x00000000 CP1 Receive Compare Data 1 0 16 read-write SR Status Register 0x00000040 32 read-only 0x000000CC TXRDY Transmit Ready 0 1 read-only TXEMPTY Transmit Empty 1 1 read-only RXRDY Receive Ready 4 1 read-only OVRUN Receive Overrun 5 1 read-only CP0 Compare 0 8 1 read-only CP1 Compare 1 9 1 read-only TXSYN Transmit Sync 10 1 read-only RXSYN Receive Sync 11 1 read-only TXEN Transmit Enable 16 1 read-only RXEN Receive Enable 17 1 read-only IER Interrupt Enable Register 0x00000044 32 write-only TXRDY Transmit Ready Interrupt Enable 0 1 write-only TXEMPTY Transmit Empty Interrupt Enable 1 1 write-only RXRDY Receive Ready Interrupt Enable 4 1 write-only OVRUN Receive Overrun Interrupt Enable 5 1 write-only CP0 Compare 0 Interrupt Enable 8 1 write-only CP1 Compare 1 Interrupt Enable 9 1 write-only TXSYN Tx Sync Interrupt Enable 10 1 write-only RXSYN Rx Sync Interrupt Enable 11 1 write-only IDR Interrupt Disable Register 0x00000048 32 write-only TXRDY Transmit Ready Interrupt Disable 0 1 write-only TXEMPTY Transmit Empty Interrupt Disable 1 1 write-only RXRDY Receive Ready Interrupt Disable 4 1 write-only OVRUN Receive Overrun Interrupt Disable 5 1 write-only CP0 Compare 0 Interrupt Disable 8 1 write-only CP1 Compare 1 Interrupt Disable 9 1 write-only TXSYN Tx Sync Interrupt Enable 10 1 write-only RXSYN Rx Sync Interrupt Enable 11 1 write-only IMR Interrupt Mask Register 0x0000004C 32 read-only 0x00000000 TXRDY Transmit Ready Interrupt Mask 0 1 read-only TXEMPTY Transmit Empty Interrupt Mask 1 1 read-only RXRDY Receive Ready Interrupt Mask 4 1 read-only OVRUN Receive Overrun Interrupt Mask 5 1 read-only CP0 Compare 0 Interrupt Mask 8 1 read-only CP1 Compare 1 Interrupt Mask 9 1 read-only TXSYN Tx Sync Interrupt Mask 10 1 read-only RXSYN Rx Sync Interrupt Mask 11 1 read-only WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x535343 WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 SPI0 6088W Serial Peripheral Interface 0 SPI SPI0_ 0x40008000 0 0x4000 registers SPI0 24 CR Control Register 0x00000000 32 write-only SPIEN SPI Enable 0 1 write-only SPIDIS SPI Disable 1 1 write-only SWRST SPI Software Reset 7 1 write-only LASTXFER Last Transfer 24 1 write-only MR Mode Register 0x00000004 32 read-write 0x00000000 MSTR Master/Slave Mode 0 1 read-write PS Peripheral Select 1 1 read-write PCSDEC Chip Select Decode 2 1 read-write MODFDIS Mode Fault Detection 4 1 read-write WDRBT Wait Data Read Before Transfer 5 1 read-write LLB Local Loopback Enable 7 1 read-write PCS Peripheral Chip Select 16 4 read-write DLYBCS Delay Between Chip Selects 24 8 read-write RDR Receive Data Register 0x00000008 32 read-only 0x00000000 RD Receive Data 0 16 read-only PCS Peripheral Chip Select 16 4 read-only TDR Transmit Data Register 0x0000000C 32 write-only TD Transmit Data 0 16 write-only PCS Peripheral Chip Select 16 4 write-only LASTXFER Last Transfer 24 1 write-only SR Status Register 0x00000010 32 read-only 0x000000F0 RDRF Receive Data Register Full 0 1 read-only TDRE Transmit Data Register Empty 1 1 read-only MODF Mode Fault Error 2 1 read-only OVRES Overrun Error Status 3 1 read-only NSSR NSS Rising 8 1 read-only TXEMPTY Transmission Registers Empty 9 1 read-only UNDES Underrun Error Status (Slave Mode Only) 10 1 read-only SPIENS SPI Enable Status 16 1 read-only IER Interrupt Enable Register 0x00000014 32 write-only RDRF Receive Data Register Full Interrupt Enable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Enable 1 1 write-only MODF Mode Fault Error Interrupt Enable 2 1 write-only OVRES Overrun Error Interrupt Enable 3 1 write-only NSSR NSS Rising Interrupt Enable 8 1 write-only TXEMPTY Transmission Registers Empty Enable 9 1 write-only UNDES Underrun Error Interrupt Enable 10 1 write-only IDR Interrupt Disable Register 0x00000018 32 write-only RDRF Receive Data Register Full Interrupt Disable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Disable 1 1 write-only MODF Mode Fault Error Interrupt Disable 2 1 write-only OVRES Overrun Error Interrupt Disable 3 1 write-only NSSR NSS Rising Interrupt Disable 8 1 write-only TXEMPTY Transmission Registers Empty Disable 9 1 write-only UNDES Underrun Error Interrupt Disable 10 1 write-only IMR Interrupt Mask Register 0x0000001C 32 read-only 0x00000000 RDRF Receive Data Register Full Interrupt Mask 0 1 read-only TDRE SPI Transmit Data Register Empty Interrupt Mask 1 1 read-only MODF Mode Fault Error Interrupt Mask 2 1 read-only OVRES Overrun Error Interrupt Mask 3 1 read-only NSSR NSS Rising Interrupt Mask 8 1 read-only TXEMPTY Transmission Registers Empty Mask 9 1 read-only UNDES Underrun Error Interrupt Mask 10 1 read-only 4 4 0-3 CSR[%s] Chip Select Register 0x00000030 32 read-write CPOL Clock Polarity 0 1 read-write NCPHA Clock Phase 1 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 SCBR Serial Clock Baud Rate 8 8 read-write DLYBS Delay Before SPCK 16 8 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write WPMR Write Protection Control Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x535049 WPSR Write Protection Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 8 read-only TC0 6082R Timer Counter 0 TC TC0_ 0x40080000 0 0x4000 registers TC0 27 TC1 28 TC2 29 CCR0 Channel Control Register (channel = 0) 0x00000000 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x00000004 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE Waveform Mode 15 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR0_WAVE_EQ_1 Channel Mode Register (channel = 0) WAVE_EQ_1 0x00000004 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE Waveform Mode 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 SMMR0 Stepper Motor Mode Register (channel = 0) 0x00000008 32 read-write 0x00000000 GCEN Gray Count Enable 0 1 read-write DOWN DOWN Count 1 1 read-write CV0 Counter Value (channel = 0) 0x00000010 32 read-only 0x00000000 CV Counter Value 0 32 read-only RA0 Register A (channel = 0) 0x00000014 32 read-write 0x00000000 RA Register A 0 32 read-write RB0 Register B (channel = 0) 0x00000018 32 read-write 0x00000000 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x0000001C 32 read-write 0x00000000 RC Register C 0 32 read-write SR0 Status Register (channel = 0) 0x00000020 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER0 Interrupt Enable Register (channel = 0) 0x00000024 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR0 Interrupt Disable Register (channel = 0) 0x00000028 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x0000002C 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only CCR1 Channel Control Register (channel = 1) 0x00000040 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR1 Channel Mode Register (channel = 1) 0x00000044 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE Waveform Mode 15 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR1_WAVE_EQ_1 Channel Mode Register (channel = 1) WAVE_EQ_1 0x00000044 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE Waveform Mode 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 SMMR1 Stepper Motor Mode Register (channel = 1) 0x00000048 32 read-write 0x00000000 GCEN Gray Count Enable 0 1 read-write DOWN DOWN Count 1 1 read-write CV1 Counter Value (channel = 1) 0x00000050 32 read-only 0x00000000 CV Counter Value 0 32 read-only RA1 Register A (channel = 1) 0x00000054 32 read-write 0x00000000 RA Register A 0 32 read-write RB1 Register B (channel = 1) 0x00000058 32 read-write 0x00000000 RB Register B 0 32 read-write RC1 Register C (channel = 1) 0x0000005C 32 read-write 0x00000000 RC Register C 0 32 read-write SR1 Status Register (channel = 1) 0x00000060 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER1 Interrupt Enable Register (channel = 1) 0x00000064 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x00000068 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR1 Interrupt Mask Register (channel = 1) 0x0000006C 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only CCR2 Channel Control Register (channel = 2) 0x00000080 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR2 Channel Mode Register (channel = 2) 0x00000084 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE Waveform Mode 15 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR2_WAVE_EQ_1 Channel Mode Register (channel = 2) WAVE_EQ_1 0x00000084 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE Waveform Mode 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 SMMR2 Stepper Motor Mode Register (channel = 2) 0x00000088 32 read-write 0x00000000 GCEN Gray Count Enable 0 1 read-write DOWN DOWN Count 1 1 read-write CV2 Counter Value (channel = 2) 0x00000090 32 read-only 0x00000000 CV Counter Value 0 32 read-only RA2 Register A (channel = 2) 0x00000094 32 read-write 0x00000000 RA Register A 0 32 read-write RB2 Register B (channel = 2) 0x00000098 32 read-write 0x00000000 RB Register B 0 32 read-write RC2 Register C (channel = 2) 0x0000009C 32 read-write 0x00000000 RC Register C 0 32 read-write SR2 Status Register (channel = 2) 0x000000A0 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER2 Interrupt Enable Register (channel = 2) 0x000000A4 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0x000000A8 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR2 Interrupt Mask Register (channel = 2) 0x000000AC 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only BCR Block Control Register 0x000000C0 32 write-only SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0x000000C4 32 read-write 0x00000000 TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA1 Signal connected to XC2: TIOA1 0x2 TIOA2 Signal connected to XC2: TIOA2 0x3 QDEN Quadrature Decoder ENabled 8 1 read-write POSEN POSition ENabled 9 1 read-write SPEEDEN SPEED ENabled 10 1 read-write QDTRANS Quadrature Decoding TRANSparent 11 1 read-write EDGPHA EDGe on PHA count mode 12 1 read-write INVA INVerted phA 13 1 read-write INVB INVerted phB 14 1 read-write INVIDX INVerted InDeX 15 1 read-write SWAP SWAP PHA and PHB 16 1 read-write IDXPHB InDeX pin is PHB pin 17 1 read-write FILTER 19 1 read-write MAXFILT MAXimum FILTer 20 6 read-write QIER QDEC Interrupt Enable Register 0x000000C8 32 write-only IDX InDeX 0 1 write-only DIRCHG DIRection CHanGe 1 1 write-only QERR Quadrature ERRor 2 1 write-only QIDR QDEC Interrupt Disable Register 0x000000CC 32 write-only IDX InDeX 0 1 write-only DIRCHG DIRection CHanGe 1 1 write-only QERR Quadrature ERRor 2 1 write-only QIMR QDEC Interrupt Mask Register 0x000000D0 32 read-only 0x00000000 IDX InDeX 0 1 read-only DIRCHG DIRection CHanGe 1 1 read-only QERR Quadrature ERRor 2 1 read-only QISR QDEC Interrupt Status Register 0x000000D4 32 read-only 0x00000000 IDX InDeX 0 1 read-only DIRCHG DIRection CHanGe 1 1 read-only QERR Quadrature ERRor 2 1 read-only DIR DIRection 8 1 read-only FMR Fault Mode Register 0x000000D8 32 read-write 0x00000000 ENCF0 ENable Compare Fault Channel 0 0 1 read-write ENCF1 ENable Compare Fault Channel 1 1 1 read-write WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TC1 6082R Timer Counter 1 TC TC1_ 0x40084000 0 0x4000 registers TC3 30 TC4 31 TC5 32 CCR0 Channel Control Register (channel = 0) 0x00000000 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x00000004 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE Waveform Mode 15 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR0_WAVE_EQ_1 Channel Mode Register (channel = 0) WAVE_EQ_1 0x00000004 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE Waveform Mode 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 SMMR0 Stepper Motor Mode Register (channel = 0) 0x00000008 32 read-write 0x00000000 GCEN Gray Count Enable 0 1 read-write DOWN DOWN Count 1 1 read-write CV0 Counter Value (channel = 0) 0x00000010 32 read-only 0x00000000 CV Counter Value 0 32 read-only RA0 Register A (channel = 0) 0x00000014 32 read-write 0x00000000 RA Register A 0 32 read-write RB0 Register B (channel = 0) 0x00000018 32 read-write 0x00000000 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x0000001C 32 read-write 0x00000000 RC Register C 0 32 read-write SR0 Status Register (channel = 0) 0x00000020 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER0 Interrupt Enable Register (channel = 0) 0x00000024 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR0 Interrupt Disable Register (channel = 0) 0x00000028 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x0000002C 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only CCR1 Channel Control Register (channel = 1) 0x00000040 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR1 Channel Mode Register (channel = 1) 0x00000044 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE Waveform Mode 15 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR1_WAVE_EQ_1 Channel Mode Register (channel = 1) WAVE_EQ_1 0x00000044 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE Waveform Mode 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 SMMR1 Stepper Motor Mode Register (channel = 1) 0x00000048 32 read-write 0x00000000 GCEN Gray Count Enable 0 1 read-write DOWN DOWN Count 1 1 read-write CV1 Counter Value (channel = 1) 0x00000050 32 read-only 0x00000000 CV Counter Value 0 32 read-only RA1 Register A (channel = 1) 0x00000054 32 read-write 0x00000000 RA Register A 0 32 read-write RB1 Register B (channel = 1) 0x00000058 32 read-write 0x00000000 RB Register B 0 32 read-write RC1 Register C (channel = 1) 0x0000005C 32 read-write 0x00000000 RC Register C 0 32 read-write SR1 Status Register (channel = 1) 0x00000060 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER1 Interrupt Enable Register (channel = 1) 0x00000064 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x00000068 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR1 Interrupt Mask Register (channel = 1) 0x0000006C 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only CCR2 Channel Control Register (channel = 2) 0x00000080 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR2 Channel Mode Register (channel = 2) 0x00000084 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE Waveform Mode 15 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR2_WAVE_EQ_1 Channel Mode Register (channel = 2) WAVE_EQ_1 0x00000084 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE Waveform Mode 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 SMMR2 Stepper Motor Mode Register (channel = 2) 0x00000088 32 read-write 0x00000000 GCEN Gray Count Enable 0 1 read-write DOWN DOWN Count 1 1 read-write CV2 Counter Value (channel = 2) 0x00000090 32 read-only 0x00000000 CV Counter Value 0 32 read-only RA2 Register A (channel = 2) 0x00000094 32 read-write 0x00000000 RA Register A 0 32 read-write RB2 Register B (channel = 2) 0x00000098 32 read-write 0x00000000 RB Register B 0 32 read-write RC2 Register C (channel = 2) 0x0000009C 32 read-write 0x00000000 RC Register C 0 32 read-write SR2 Status Register (channel = 2) 0x000000A0 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER2 Interrupt Enable Register (channel = 2) 0x000000A4 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0x000000A8 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR2 Interrupt Mask Register (channel = 2) 0x000000AC 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only BCR Block Control Register 0x000000C0 32 write-only SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0x000000C4 32 read-write 0x00000000 TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA1 Signal connected to XC2: TIOA1 0x2 TIOA2 Signal connected to XC2: TIOA2 0x3 QDEN Quadrature Decoder ENabled 8 1 read-write POSEN POSition ENabled 9 1 read-write SPEEDEN SPEED ENabled 10 1 read-write QDTRANS Quadrature Decoding TRANSparent 11 1 read-write EDGPHA EDGe on PHA count mode 12 1 read-write INVA INVerted phA 13 1 read-write INVB INVerted phB 14 1 read-write INVIDX INVerted InDeX 15 1 read-write SWAP SWAP PHA and PHB 16 1 read-write IDXPHB InDeX pin is PHB pin 17 1 read-write FILTER 19 1 read-write MAXFILT MAXimum FILTer 20 6 read-write QIER QDEC Interrupt Enable Register 0x000000C8 32 write-only IDX InDeX 0 1 write-only DIRCHG DIRection CHanGe 1 1 write-only QERR Quadrature ERRor 2 1 write-only QIDR QDEC Interrupt Disable Register 0x000000CC 32 write-only IDX InDeX 0 1 write-only DIRCHG DIRection CHanGe 1 1 write-only QERR Quadrature ERRor 2 1 write-only QIMR QDEC Interrupt Mask Register 0x000000D0 32 read-only 0x00000000 IDX InDeX 0 1 read-only DIRCHG DIRection CHanGe 1 1 read-only QERR Quadrature ERRor 2 1 read-only QISR QDEC Interrupt Status Register 0x000000D4 32 read-only 0x00000000 IDX InDeX 0 1 read-only DIRCHG DIRection CHanGe 1 1 read-only QERR Quadrature ERRor 2 1 read-only DIR DIRection 8 1 read-only FMR Fault Mode Register 0x000000D8 32 read-write 0x00000000 ENCF0 ENable Compare Fault Channel 0 0 1 read-write ENCF1 ENable Compare Fault Channel 1 1 1 read-write WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TC2 6082R Timer Counter 2 TC TC2_ 0x40088000 0 0x4000 registers TC6 33 TC7 34 TC8 35 CCR0 Channel Control Register (channel = 0) 0x00000000 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x00000004 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE Waveform Mode 15 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR0_WAVE_EQ_1 Channel Mode Register (channel = 0) WAVE_EQ_1 0x00000004 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE Waveform Mode 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 SMMR0 Stepper Motor Mode Register (channel = 0) 0x00000008 32 read-write 0x00000000 GCEN Gray Count Enable 0 1 read-write DOWN DOWN Count 1 1 read-write CV0 Counter Value (channel = 0) 0x00000010 32 read-only 0x00000000 CV Counter Value 0 32 read-only RA0 Register A (channel = 0) 0x00000014 32 read-write 0x00000000 RA Register A 0 32 read-write RB0 Register B (channel = 0) 0x00000018 32 read-write 0x00000000 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x0000001C 32 read-write 0x00000000 RC Register C 0 32 read-write SR0 Status Register (channel = 0) 0x00000020 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER0 Interrupt Enable Register (channel = 0) 0x00000024 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR0 Interrupt Disable Register (channel = 0) 0x00000028 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x0000002C 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only CCR1 Channel Control Register (channel = 1) 0x00000040 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR1 Channel Mode Register (channel = 1) 0x00000044 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE Waveform Mode 15 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR1_WAVE_EQ_1 Channel Mode Register (channel = 1) WAVE_EQ_1 0x00000044 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE Waveform Mode 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 SMMR1 Stepper Motor Mode Register (channel = 1) 0x00000048 32 read-write 0x00000000 GCEN Gray Count Enable 0 1 read-write DOWN DOWN Count 1 1 read-write CV1 Counter Value (channel = 1) 0x00000050 32 read-only 0x00000000 CV Counter Value 0 32 read-only RA1 Register A (channel = 1) 0x00000054 32 read-write 0x00000000 RA Register A 0 32 read-write RB1 Register B (channel = 1) 0x00000058 32 read-write 0x00000000 RB Register B 0 32 read-write RC1 Register C (channel = 1) 0x0000005C 32 read-write 0x00000000 RC Register C 0 32 read-write SR1 Status Register (channel = 1) 0x00000060 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER1 Interrupt Enable Register (channel = 1) 0x00000064 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x00000068 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR1 Interrupt Mask Register (channel = 1) 0x0000006C 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only CCR2 Channel Control Register (channel = 2) 0x00000080 32 write-only CLKEN Counter Clock Enable Command 0 1 write-only CLKDIS Counter Clock Disable Command 1 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR2 Channel Mode Register (channel = 2) 0x00000084 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDBDIS Counter Clock Disable with RB Loading 7 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write WAVE Waveform Mode 15 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 CMR2_WAVE_EQ_1 Channel Mode Register (channel = 2) WAVE_EQ_1 0x00000084 32 read-write 0x00000000 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: TCLK1 0x0 TIMER_CLOCK2 Clock selected: TCLK2 0x1 TIMER_CLOCK3 Clock selected: TCLK3 0x2 TIMER_CLOCK4 Clock selected: TCLK4 0x3 TIMER_CLOCK5 Clock selected: TCLK5 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 CLKI Clock Invert 3 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 ENETRG External Event Trigger Enable 12 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 WAVE Waveform Mode 15 1 read-write ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 SMMR2 Stepper Motor Mode Register (channel = 2) 0x00000088 32 read-write 0x00000000 GCEN Gray Count Enable 0 1 read-write DOWN DOWN Count 1 1 read-write CV2 Counter Value (channel = 2) 0x00000090 32 read-only 0x00000000 CV Counter Value 0 32 read-only RA2 Register A (channel = 2) 0x00000094 32 read-write 0x00000000 RA Register A 0 32 read-write RB2 Register B (channel = 2) 0x00000098 32 read-write 0x00000000 RB Register B 0 32 read-write RC2 Register C (channel = 2) 0x0000009C 32 read-write 0x00000000 RC Register C 0 32 read-write SR2 Status Register (channel = 2) 0x000000A0 32 read-only 0x00000000 COVFS Counter Overflow Status 0 1 read-only LOVRS Load Overrun Status 1 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only ETRGS External Trigger Status 7 1 read-only CLKSTA Clock Enabling Status 16 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only IER2 Interrupt Enable Register (channel = 2) 0x000000A4 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0x000000A8 32 write-only COVFS Counter Overflow 0 1 write-only LOVRS Load Overrun 1 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only ETRGS External Trigger 7 1 write-only IMR2 Interrupt Mask Register (channel = 2) 0x000000AC 32 read-only 0x00000000 COVFS Counter Overflow 0 1 read-only LOVRS Load Overrun 1 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only ETRGS External Trigger 7 1 read-only BCR Block Control Register 0x000000C0 32 write-only SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0x000000C4 32 read-write 0x00000000 TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA1 Signal connected to XC2: TIOA1 0x2 TIOA2 Signal connected to XC2: TIOA2 0x3 QDEN Quadrature Decoder ENabled 8 1 read-write POSEN POSition ENabled 9 1 read-write SPEEDEN SPEED ENabled 10 1 read-write QDTRANS Quadrature Decoding TRANSparent 11 1 read-write EDGPHA EDGe on PHA count mode 12 1 read-write INVA INVerted phA 13 1 read-write INVB INVerted phB 14 1 read-write INVIDX INVerted InDeX 15 1 read-write SWAP SWAP PHA and PHB 16 1 read-write IDXPHB InDeX pin is PHB pin 17 1 read-write FILTER 19 1 read-write MAXFILT MAXimum FILTer 20 6 read-write QIER QDEC Interrupt Enable Register 0x000000C8 32 write-only IDX InDeX 0 1 write-only DIRCHG DIRection CHanGe 1 1 write-only QERR Quadrature ERRor 2 1 write-only QIDR QDEC Interrupt Disable Register 0x000000CC 32 write-only IDX InDeX 0 1 write-only DIRCHG DIRection CHanGe 1 1 write-only QERR Quadrature ERRor 2 1 write-only QIMR QDEC Interrupt Mask Register 0x000000D0 32 read-only 0x00000000 IDX InDeX 0 1 read-only DIRCHG DIRection CHanGe 1 1 read-only QERR Quadrature ERRor 2 1 read-only QISR QDEC Interrupt Status Register 0x000000D4 32 read-only 0x00000000 IDX InDeX 0 1 read-only DIRCHG DIRection CHanGe 1 1 read-only QERR Quadrature ERRor 2 1 read-only DIR DIRection 8 1 read-only FMR Fault Mode Register 0x000000D8 32 read-write 0x00000000 ENCF0 ENable Compare Fault Channel 0 0 1 read-write ENCF1 ENable Compare Fault Channel 1 1 1 read-write WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TWI0 6212O Two-wire Interface 0 TWI TWI0_ 0x4008C000 0 0x4000 registers TWI0 22 CR Control Register 0x00000000 32 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only MSEN TWI Master Mode Enabled 2 1 write-only MSDIS TWI Master Mode Disabled 3 1 write-only SVEN TWI Slave Mode Enabled 4 1 write-only SVDIS TWI Slave Mode Disabled 5 1 write-only QUICK SMBUS Quick Command 6 1 write-only SWRST Software Reset 7 1 write-only MMR Master Mode Register 0x00000004 32 read-write 0x00000000 IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write DADR Device Address 16 7 read-write SMR Slave Mode Register 0x00000008 32 read-write 0x00000000 SADR Slave Address 16 7 read-write IADR Internal Address Register 0x0000000C 32 read-write 0x00000000 IADR Internal Address 0 24 read-write CWGR Clock Waveform Generator Register 0x00000010 32 read-write 0x00000000 CLDIV Clock Low Divider 0 8 read-write CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write SR Status Register 0x00000020 32 read-only 0x0000F009 TXCOMP Transmission Completed (automatically set / reset) 0 1 read-only RXRDY Receive Holding Register Ready (automatically set / reset) 1 1 read-only TXRDY Transmit Holding Register Ready (automatically set / reset) 2 1 read-only SVREAD Slave Read (automatically set / reset) 3 1 read-only SVACC Slave Access (automatically set / reset) 4 1 read-only GACC General Call Access (clear on read) 5 1 read-only OVRE Overrun Error (clear on read) 6 1 read-only NACK Not Acknowledged (clear on read) 8 1 read-only ARBLST Arbitration Lost (clear on read) 9 1 read-only SCLWS Clock Wait State (automatically set / reset) 10 1 read-only EOSACC End Of Slave Access (clear on read) 11 1 read-only ENDRX End of RX buffer 12 1 read-only ENDTX End of TX buffer 13 1 read-only RXBUFF RX Buffer Full 14 1 read-only TXBUFE TX Buffer Empty 15 1 read-only IER Interrupt Enable Register 0x00000024 32 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only ARBLST Arbitration Lost Interrupt Enable 9 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only ENDRX End of Receive Buffer Interrupt Enable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Enable 13 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 14 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 15 1 write-only IDR Interrupt Disable Register 0x00000028 32 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only ARBLST Arbitration Lost Interrupt Disable 9 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only ENDRX End of Receive Buffer Interrupt Disable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Disable 13 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 14 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 15 1 write-only IMR Interrupt Mask Register 0x0000002C 32 read-only 0x00000000 TXCOMP Transmission Completed Interrupt Mask 0 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only ARBLST Arbitration Lost Interrupt Mask 9 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only ENDRX End of Receive Buffer Interrupt Mask 12 1 read-only ENDTX End of Transmit Buffer Interrupt Mask 13 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 14 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 15 1 read-only RHR Receive Holding Register 0x00000030 32 read-only 0x00000000 RXDATA Master or Slave Receive Holding Data 0 8 read-only THR Transmit Holding Register 0x00000034 32 write-only 0x00000000 TXDATA Master or Slave Transmit Holding Data 0 8 write-only RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only TWI1 6212O Two-wire Interface 1 TWI TWI1_ 0x40090000 0 0x4000 registers TWI1 23 CR Control Register 0x00000000 32 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only MSEN TWI Master Mode Enabled 2 1 write-only MSDIS TWI Master Mode Disabled 3 1 write-only SVEN TWI Slave Mode Enabled 4 1 write-only SVDIS TWI Slave Mode Disabled 5 1 write-only QUICK SMBUS Quick Command 6 1 write-only SWRST Software Reset 7 1 write-only MMR Master Mode Register 0x00000004 32 read-write 0x00000000 IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write DADR Device Address 16 7 read-write SMR Slave Mode Register 0x00000008 32 read-write 0x00000000 SADR Slave Address 16 7 read-write IADR Internal Address Register 0x0000000C 32 read-write 0x00000000 IADR Internal Address 0 24 read-write CWGR Clock Waveform Generator Register 0x00000010 32 read-write 0x00000000 CLDIV Clock Low Divider 0 8 read-write CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write SR Status Register 0x00000020 32 read-only 0x0000F009 TXCOMP Transmission Completed (automatically set / reset) 0 1 read-only RXRDY Receive Holding Register Ready (automatically set / reset) 1 1 read-only TXRDY Transmit Holding Register Ready (automatically set / reset) 2 1 read-only SVREAD Slave Read (automatically set / reset) 3 1 read-only SVACC Slave Access (automatically set / reset) 4 1 read-only GACC General Call Access (clear on read) 5 1 read-only OVRE Overrun Error (clear on read) 6 1 read-only NACK Not Acknowledged (clear on read) 8 1 read-only ARBLST Arbitration Lost (clear on read) 9 1 read-only SCLWS Clock Wait State (automatically set / reset) 10 1 read-only EOSACC End Of Slave Access (clear on read) 11 1 read-only ENDRX End of RX buffer 12 1 read-only ENDTX End of TX buffer 13 1 read-only RXBUFF RX Buffer Full 14 1 read-only TXBUFE TX Buffer Empty 15 1 read-only IER Interrupt Enable Register 0x00000024 32 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only ARBLST Arbitration Lost Interrupt Enable 9 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only ENDRX End of Receive Buffer Interrupt Enable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Enable 13 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 14 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 15 1 write-only IDR Interrupt Disable Register 0x00000028 32 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only ARBLST Arbitration Lost Interrupt Disable 9 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only ENDRX End of Receive Buffer Interrupt Disable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Disable 13 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 14 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 15 1 write-only IMR Interrupt Mask Register 0x0000002C 32 read-only 0x00000000 TXCOMP Transmission Completed Interrupt Mask 0 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only ARBLST Arbitration Lost Interrupt Mask 9 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only ENDRX End of Receive Buffer Interrupt Mask 12 1 read-only ENDTX End of Transmit Buffer Interrupt Mask 13 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 14 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 15 1 read-only RHR Receive Holding Register 0x00000030 32 read-only 0x00000000 RXDATA Master or Slave Receive Holding Data 0 8 read-only THR Transmit Holding Register 0x00000034 32 write-only 0x00000000 TXDATA Master or Slave Transmit Holding Data 0 8 write-only RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only PWM 6343J Pulse Width Modulation Controller PWM_ 0x40094000 0 0x4000 registers PWM 36 CLK PWM Clock Register 0x00000000 32 read-write 0x00000000 DIVA CLKA, CLKB Divide Factor 0 8 read-write PREA CLKA, CLKB Source Clock Selection 8 4 read-write DIVB CLKA, CLKB Divide Factor 16 8 read-write PREB CLKA, CLKB Source Clock Selection 24 4 read-write ENA PWM Enable Register 0x00000004 32 write-only CHID0 Channel ID 0 1 write-only CHID1 Channel ID 1 1 write-only CHID2 Channel ID 2 1 write-only CHID3 Channel ID 3 1 write-only CHID4 Channel ID 4 1 write-only CHID5 Channel ID 5 1 write-only CHID6 Channel ID 6 1 write-only CHID7 Channel ID 7 1 write-only DIS PWM Disable Register 0x00000008 32 write-only CHID0 Channel ID 0 1 write-only CHID1 Channel ID 1 1 write-only CHID2 Channel ID 2 1 write-only CHID3 Channel ID 3 1 write-only CHID4 Channel ID 4 1 write-only CHID5 Channel ID 5 1 write-only CHID6 Channel ID 6 1 write-only CHID7 Channel ID 7 1 write-only SR PWM Status Register 0x0000000C 32 read-only 0x00000000 CHID0 Channel ID 0 1 read-only CHID1 Channel ID 1 1 read-only CHID2 Channel ID 2 1 read-only CHID3 Channel ID 3 1 read-only CHID4 Channel ID 4 1 read-only CHID5 Channel ID 5 1 read-only CHID6 Channel ID 6 1 read-only CHID7 Channel ID 7 1 read-only IER1 PWM Interrupt Enable Register 1 0x00000010 32 write-only CHID0 Counter Event on Channel 0 Interrupt Enable 0 1 write-only CHID1 Counter Event on Channel 1 Interrupt Enable 1 1 write-only CHID2 Counter Event on Channel 2 Interrupt Enable 2 1 write-only CHID3 Counter Event on Channel 3 Interrupt Enable 3 1 write-only CHID4 Counter Event on Channel 4 Interrupt Enable 4 1 write-only CHID5 Counter Event on Channel 5 Interrupt Enable 5 1 write-only CHID6 Counter Event on Channel 6 Interrupt Enable 6 1 write-only CHID7 Counter Event on Channel 7 Interrupt Enable 7 1 write-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Enable 16 1 write-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Enable 17 1 write-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Enable 18 1 write-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Enable 19 1 write-only FCHID4 Fault Protection Trigger on Channel 4 Interrupt Enable 20 1 write-only FCHID5 Fault Protection Trigger on Channel 5 Interrupt Enable 21 1 write-only FCHID6 Fault Protection Trigger on Channel 6 Interrupt Enable 22 1 write-only FCHID7 Fault Protection Trigger on Channel 7 Interrupt Enable 23 1 write-only IDR1 PWM Interrupt Disable Register 1 0x00000014 32 write-only CHID0 Counter Event on Channel 0 Interrupt Disable 0 1 write-only CHID1 Counter Event on Channel 1 Interrupt Disable 1 1 write-only CHID2 Counter Event on Channel 2 Interrupt Disable 2 1 write-only CHID3 Counter Event on Channel 3 Interrupt Disable 3 1 write-only CHID4 Counter Event on Channel 4 Interrupt Disable 4 1 write-only CHID5 Counter Event on Channel 5 Interrupt Disable 5 1 write-only CHID6 Counter Event on Channel 6 Interrupt Disable 6 1 write-only CHID7 Counter Event on Channel 7 Interrupt Disable 7 1 write-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Disable 16 1 write-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Disable 17 1 write-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Disable 18 1 write-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Disable 19 1 write-only FCHID4 Fault Protection Trigger on Channel 4 Interrupt Disable 20 1 write-only FCHID5 Fault Protection Trigger on Channel 5 Interrupt Disable 21 1 write-only FCHID6 Fault Protection Trigger on Channel 6 Interrupt Disable 22 1 write-only FCHID7 Fault Protection Trigger on Channel 7 Interrupt Disable 23 1 write-only IMR1 PWM Interrupt Mask Register 1 0x00000018 32 read-only 0x00000000 CHID0 Counter Event on Channel 0 Interrupt Mask 0 1 read-only CHID1 Counter Event on Channel 1 Interrupt Mask 1 1 read-only CHID2 Counter Event on Channel 2 Interrupt Mask 2 1 read-only CHID3 Counter Event on Channel 3 Interrupt Mask 3 1 read-only CHID4 Counter Event on Channel 4 Interrupt Mask 4 1 read-only CHID5 Counter Event on Channel 5 Interrupt Mask 5 1 read-only CHID6 Counter Event on Channel 6 Interrupt Mask 6 1 read-only CHID7 Counter Event on Channel 7 Interrupt Mask 7 1 read-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Mask 16 1 read-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Mask 17 1 read-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Mask 18 1 read-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Mask 19 1 read-only FCHID4 Fault Protection Trigger on Channel 4 Interrupt Mask 20 1 read-only FCHID5 Fault Protection Trigger on Channel 5 Interrupt Mask 21 1 read-only FCHID6 Fault Protection Trigger on Channel 6 Interrupt Mask 22 1 read-only FCHID7 Fault Protection Trigger on Channel 7 Interrupt Mask 23 1 read-only ISR1 PWM Interrupt Status Register 1 0x0000001C 32 read-only 0x00000000 CHID0 Counter Event on Channel 0 0 1 read-only CHID1 Counter Event on Channel 1 1 1 read-only CHID2 Counter Event on Channel 2 2 1 read-only CHID3 Counter Event on Channel 3 3 1 read-only CHID4 Counter Event on Channel 4 4 1 read-only CHID5 Counter Event on Channel 5 5 1 read-only CHID6 Counter Event on Channel 6 6 1 read-only CHID7 Counter Event on Channel 7 7 1 read-only FCHID0 Fault Protection Trigger on Channel 0 16 1 read-only FCHID1 Fault Protection Trigger on Channel 1 17 1 read-only FCHID2 Fault Protection Trigger on Channel 2 18 1 read-only FCHID3 Fault Protection Trigger on Channel 3 19 1 read-only FCHID4 Fault Protection Trigger on Channel 4 20 1 read-only FCHID5 Fault Protection Trigger on Channel 5 21 1 read-only FCHID6 Fault Protection Trigger on Channel 6 22 1 read-only FCHID7 Fault Protection Trigger on Channel 7 23 1 read-only SCM PWM Sync Channels Mode Register 0x00000020 32 read-write 0x00000000 SYNC0 Synchronous Channel 0 0 1 read-write SYNC1 Synchronous Channel 1 1 1 read-write SYNC2 Synchronous Channel 2 2 1 read-write SYNC3 Synchronous Channel 3 3 1 read-write SYNC4 Synchronous Channel 4 4 1 read-write SYNC5 Synchronous Channel 5 5 1 read-write SYNC6 Synchronous Channel 6 6 1 read-write SYNC7 Synchronous Channel 7 7 1 read-write UPDM Synchronous Channels Update Mode 16 2 read-write MODE0 Manual write of double buffer registers and manual update of synchronous channels 0x0 MODE1 Manual write of double buffer registers and automatic update of synchronous channels 0x1 MODE2 Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels 0x2 PTRM PDC Transfer Request Mode 20 1 read-write PTRCS PDC Transfer Request Comparison Selection 21 3 read-write SCUC PWM Sync Channels Update Control Register 0x00000028 32 read-write 0x00000000 UPDULOCK Synchronous Channels Update Unlock 0 1 read-write SCUP PWM Sync Channels Update Period Register 0x0000002C 32 read-write 0x00000000 UPR Update Period 0 4 read-write UPRCNT Update Period Counter 4 4 read-write SCUPUPD PWM Sync Channels Update Period Update Register 0x00000030 32 write-only 0x00000000 UPRUPD Update Period Update 0 4 write-only IER2 PWM Interrupt Enable Register 2 0x00000034 32 write-only WRDY Write Ready for Synchronous Channels Update Interrupt Enable 0 1 write-only ENDTX PDC End of TX Buffer Interrupt Enable 1 1 write-only TXBUFE PDC TX Buffer Empty Interrupt Enable 2 1 write-only UNRE Synchronous Channels Update Underrun Error Interrupt Enable 3 1 write-only CMPM0 Comparison 0 Match Interrupt Enable 8 1 write-only CMPM1 Comparison 1 Match Interrupt Enable 9 1 write-only CMPM2 Comparison 2 Match Interrupt Enable 10 1 write-only CMPM3 Comparison 3 Match Interrupt Enable 11 1 write-only CMPM4 Comparison 4 Match Interrupt Enable 12 1 write-only CMPM5 Comparison 5 Match Interrupt Enable 13 1 write-only CMPM6 Comparison 6 Match Interrupt Enable 14 1 write-only CMPM7 Comparison 7 Match Interrupt Enable 15 1 write-only CMPU0 Comparison 0 Update Interrupt Enable 16 1 write-only CMPU1 Comparison 1 Update Interrupt Enable 17 1 write-only CMPU2 Comparison 2 Update Interrupt Enable 18 1 write-only CMPU3 Comparison 3 Update Interrupt Enable 19 1 write-only CMPU4 Comparison 4 Update Interrupt Enable 20 1 write-only CMPU5 Comparison 5 Update Interrupt Enable 21 1 write-only CMPU6 Comparison 6 Update Interrupt Enable 22 1 write-only CMPU7 Comparison 7 Update Interrupt Enable 23 1 write-only IDR2 PWM Interrupt Disable Register 2 0x00000038 32 write-only WRDY Write Ready for Synchronous Channels Update Interrupt Disable 0 1 write-only ENDTX PDC End of TX Buffer Interrupt Disable 1 1 write-only TXBUFE PDC TX Buffer Empty Interrupt Disable 2 1 write-only UNRE Synchronous Channels Update Underrun Error Interrupt Disable 3 1 write-only CMPM0 Comparison 0 Match Interrupt Disable 8 1 write-only CMPM1 Comparison 1 Match Interrupt Disable 9 1 write-only CMPM2 Comparison 2 Match Interrupt Disable 10 1 write-only CMPM3 Comparison 3 Match Interrupt Disable 11 1 write-only CMPM4 Comparison 4 Match Interrupt Disable 12 1 write-only CMPM5 Comparison 5 Match Interrupt Disable 13 1 write-only CMPM6 Comparison 6 Match Interrupt Disable 14 1 write-only CMPM7 Comparison 7 Match Interrupt Disable 15 1 write-only CMPU0 Comparison 0 Update Interrupt Disable 16 1 write-only CMPU1 Comparison 1 Update Interrupt Disable 17 1 write-only CMPU2 Comparison 2 Update Interrupt Disable 18 1 write-only CMPU3 Comparison 3 Update Interrupt Disable 19 1 write-only CMPU4 Comparison 4 Update Interrupt Disable 20 1 write-only CMPU5 Comparison 5 Update Interrupt Disable 21 1 write-only CMPU6 Comparison 6 Update Interrupt Disable 22 1 write-only CMPU7 Comparison 7 Update Interrupt Disable 23 1 write-only IMR2 PWM Interrupt Mask Register 2 0x0000003C 32 read-only 0x00000000 WRDY Write Ready for Synchronous Channels Update Interrupt Mask 0 1 read-only ENDTX PDC End of TX Buffer Interrupt Mask 1 1 read-only TXBUFE PDC TX Buffer Empty Interrupt Mask 2 1 read-only UNRE Synchronous Channels Update Underrun Error Interrupt Mask 3 1 read-only CMPM0 Comparison 0 Match Interrupt Mask 8 1 read-only CMPM1 Comparison 1 Match Interrupt Mask 9 1 read-only CMPM2 Comparison 2 Match Interrupt Mask 10 1 read-only CMPM3 Comparison 3 Match Interrupt Mask 11 1 read-only CMPM4 Comparison 4 Match Interrupt Mask 12 1 read-only CMPM5 Comparison 5 Match Interrupt Mask 13 1 read-only CMPM6 Comparison 6 Match Interrupt Mask 14 1 read-only CMPM7 Comparison 7 Match Interrupt Mask 15 1 read-only CMPU0 Comparison 0 Update Interrupt Mask 16 1 read-only CMPU1 Comparison 1 Update Interrupt Mask 17 1 read-only CMPU2 Comparison 2 Update Interrupt Mask 18 1 read-only CMPU3 Comparison 3 Update Interrupt Mask 19 1 read-only CMPU4 Comparison 4 Update Interrupt Mask 20 1 read-only CMPU5 Comparison 5 Update Interrupt Mask 21 1 read-only CMPU6 Comparison 6 Update Interrupt Mask 22 1 read-only CMPU7 Comparison 7 Update Interrupt Mask 23 1 read-only ISR2 PWM Interrupt Status Register 2 0x00000040 32 read-only 0x00000000 WRDY Write Ready for Synchronous Channels Update 0 1 read-only ENDTX PDC End of TX Buffer 1 1 read-only TXBUFE PDC TX Buffer Empty 2 1 read-only UNRE Synchronous Channels Update Underrun Error 3 1 read-only CMPM0 Comparison 0 Match 8 1 read-only CMPM1 Comparison 1 Match 9 1 read-only CMPM2 Comparison 2 Match 10 1 read-only CMPM3 Comparison 3 Match 11 1 read-only CMPM4 Comparison 4 Match 12 1 read-only CMPM5 Comparison 5 Match 13 1 read-only CMPM6 Comparison 6 Match 14 1 read-only CMPM7 Comparison 7 Match 15 1 read-only CMPU0 Comparison 0 Update 16 1 read-only CMPU1 Comparison 1 Update 17 1 read-only CMPU2 Comparison 2 Update 18 1 read-only CMPU3 Comparison 3 Update 19 1 read-only CMPU4 Comparison 4 Update 20 1 read-only CMPU5 Comparison 5 Update 21 1 read-only CMPU6 Comparison 6 Update 22 1 read-only CMPU7 Comparison 7 Update 23 1 read-only OOV PWM Output Override Value Register 0x00000044 32 read-write 0x00000000 OOVH0 Output Override Value for PWMH output of the channel 0 0 1 read-write OOVH1 Output Override Value for PWMH output of the channel 1 1 1 read-write OOVH2 Output Override Value for PWMH output of the channel 2 2 1 read-write OOVH3 Output Override Value for PWMH output of the channel 3 3 1 read-write OOVH4 Output Override Value for PWMH output of the channel 4 4 1 read-write OOVH5 Output Override Value for PWMH output of the channel 5 5 1 read-write OOVH6 Output Override Value for PWMH output of the channel 6 6 1 read-write OOVH7 Output Override Value for PWMH output of the channel 7 7 1 read-write OOVL0 Output Override Value for PWML output of the channel 0 16 1 read-write OOVL1 Output Override Value for PWML output of the channel 1 17 1 read-write OOVL2 Output Override Value for PWML output of the channel 2 18 1 read-write OOVL3 Output Override Value for PWML output of the channel 3 19 1 read-write OOVL4 Output Override Value for PWML output of the channel 4 20 1 read-write OOVL5 Output Override Value for PWML output of the channel 5 21 1 read-write OOVL6 Output Override Value for PWML output of the channel 6 22 1 read-write OOVL7 Output Override Value for PWML output of the channel 7 23 1 read-write OS PWM Output Selection Register 0x00000048 32 read-write 0x00000000 OSH0 Output Selection for PWMH output of the channel 0 0 1 read-write OSH1 Output Selection for PWMH output of the channel 1 1 1 read-write OSH2 Output Selection for PWMH output of the channel 2 2 1 read-write OSH3 Output Selection for PWMH output of the channel 3 3 1 read-write OSH4 Output Selection for PWMH output of the channel 4 4 1 read-write OSH5 Output Selection for PWMH output of the channel 5 5 1 read-write OSH6 Output Selection for PWMH output of the channel 6 6 1 read-write OSH7 Output Selection for PWMH output of the channel 7 7 1 read-write OSL0 Output Selection for PWML output of the channel 0 16 1 read-write OSL1 Output Selection for PWML output of the channel 1 17 1 read-write OSL2 Output Selection for PWML output of the channel 2 18 1 read-write OSL3 Output Selection for PWML output of the channel 3 19 1 read-write OSL4 Output Selection for PWML output of the channel 4 20 1 read-write OSL5 Output Selection for PWML output of the channel 5 21 1 read-write OSL6 Output Selection for PWML output of the channel 6 22 1 read-write OSL7 Output Selection for PWML output of the channel 7 23 1 read-write OSS PWM Output Selection Set Register 0x0000004C 32 write-only OSSH0 Output Selection Set for PWMH output of the channel 0 0 1 write-only OSSH1 Output Selection Set for PWMH output of the channel 1 1 1 write-only OSSH2 Output Selection Set for PWMH output of the channel 2 2 1 write-only OSSH3 Output Selection Set for PWMH output of the channel 3 3 1 write-only OSSH4 Output Selection Set for PWMH output of the channel 4 4 1 write-only OSSH5 Output Selection Set for PWMH output of the channel 5 5 1 write-only OSSH6 Output Selection Set for PWMH output of the channel 6 6 1 write-only OSSH7 Output Selection Set for PWMH output of the channel 7 7 1 write-only OSSL0 Output Selection Set for PWML output of the channel 0 16 1 write-only OSSL1 Output Selection Set for PWML output of the channel 1 17 1 write-only OSSL2 Output Selection Set for PWML output of the channel 2 18 1 write-only OSSL3 Output Selection Set for PWML output of the channel 3 19 1 write-only OSSL4 Output Selection Set for PWML output of the channel 4 20 1 write-only OSSL5 Output Selection Set for PWML output of the channel 5 21 1 write-only OSSL6 Output Selection Set for PWML output of the channel 6 22 1 write-only OSSL7 Output Selection Set for PWML output of the channel 7 23 1 write-only OSC PWM Output Selection Clear Register 0x00000050 32 write-only OSCH0 Output Selection Clear for PWMH output of the channel 0 0 1 write-only OSCH1 Output Selection Clear for PWMH output of the channel 1 1 1 write-only OSCH2 Output Selection Clear for PWMH output of the channel 2 2 1 write-only OSCH3 Output Selection Clear for PWMH output of the channel 3 3 1 write-only OSCH4 Output Selection Clear for PWMH output of the channel 4 4 1 write-only OSCH5 Output Selection Clear for PWMH output of the channel 5 5 1 write-only OSCH6 Output Selection Clear for PWMH output of the channel 6 6 1 write-only OSCH7 Output Selection Clear for PWMH output of the channel 7 7 1 write-only OSCL0 Output Selection Clear for PWML output of the channel 0 16 1 write-only OSCL1 Output Selection Clear for PWML output of the channel 1 17 1 write-only OSCL2 Output Selection Clear for PWML output of the channel 2 18 1 write-only OSCL3 Output Selection Clear for PWML output of the channel 3 19 1 write-only OSCL4 Output Selection Clear for PWML output of the channel 4 20 1 write-only OSCL5 Output Selection Clear for PWML output of the channel 5 21 1 write-only OSCL6 Output Selection Clear for PWML output of the channel 6 22 1 write-only OSCL7 Output Selection Clear for PWML output of the channel 7 23 1 write-only OSSUPD PWM Output Selection Set Update Register 0x00000054 32 write-only OSSUPH0 Output Selection Set for PWMH output of the channel 0 0 1 write-only OSSUPH1 Output Selection Set for PWMH output of the channel 1 1 1 write-only OSSUPH2 Output Selection Set for PWMH output of the channel 2 2 1 write-only OSSUPH3 Output Selection Set for PWMH output of the channel 3 3 1 write-only OSSUPH4 Output Selection Set for PWMH output of the channel 4 4 1 write-only OSSUPH5 Output Selection Set for PWMH output of the channel 5 5 1 write-only OSSUPH6 Output Selection Set for PWMH output of the channel 6 6 1 write-only OSSUPH7 Output Selection Set for PWMH output of the channel 7 7 1 write-only OSSUPL0 Output Selection Set for PWML output of the channel 0 16 1 write-only OSSUPL1 Output Selection Set for PWML output of the channel 1 17 1 write-only OSSUPL2 Output Selection Set for PWML output of the channel 2 18 1 write-only OSSUPL3 Output Selection Set for PWML output of the channel 3 19 1 write-only OSSUPL4 Output Selection Set for PWML output of the channel 4 20 1 write-only OSSUPL5 Output Selection Set for PWML output of the channel 5 21 1 write-only OSSUPL6 Output Selection Set for PWML output of the channel 6 22 1 write-only OSSUPL7 Output Selection Set for PWML output of the channel 7 23 1 write-only OSCUPD PWM Output Selection Clear Update Register 0x00000058 32 write-only OSCUPH0 Output Selection Clear for PWMH output of the channel 0 0 1 write-only OSCUPH1 Output Selection Clear for PWMH output of the channel 1 1 1 write-only OSCUPH2 Output Selection Clear for PWMH output of the channel 2 2 1 write-only OSCUPH3 Output Selection Clear for PWMH output of the channel 3 3 1 write-only OSCUPH4 Output Selection Clear for PWMH output of the channel 4 4 1 write-only OSCUPH5 Output Selection Clear for PWMH output of the channel 5 5 1 write-only OSCUPH6 Output Selection Clear for PWMH output of the channel 6 6 1 write-only OSCUPH7 Output Selection Clear for PWMH output of the channel 7 7 1 write-only OSCUPL0 Output Selection Clear for PWML output of the channel 0 16 1 write-only OSCUPL1 Output Selection Clear for PWML output of the channel 1 17 1 write-only OSCUPL2 Output Selection Clear for PWML output of the channel 2 18 1 write-only OSCUPL3 Output Selection Clear for PWML output of the channel 3 19 1 write-only OSCUPL4 Output Selection Clear for PWML output of the channel 4 20 1 write-only OSCUPL5 Output Selection Clear for PWML output of the channel 5 21 1 write-only OSCUPL6 Output Selection Clear for PWML output of the channel 6 22 1 write-only OSCUPL7 Output Selection Clear for PWML output of the channel 7 23 1 write-only FMR PWM Fault Mode Register 0x0000005C 32 read-write 0x00000000 FPOL Fault Polarity (fault input bit varies from 0 to 5) 0 8 read-write FMOD Fault Activation Mode (fault input bit varies from 0 to 5) 8 8 read-write FFIL Fault Filtering (fault input bit varies from 0 to 5) 16 8 read-write FSR PWM Fault Status Register 0x00000060 32 read-only 0x00000000 FIV Fault Input Value (fault input bit varies from 0 to 5) 0 8 read-only FS Fault Status (fault input bit varies from 0 to 5) 8 8 read-only FCR PWM Fault Clear Register 0x00000064 32 write-only FCLR Fault Clear (fault input bit varies from 0 to 5) 0 8 write-only FPV PWM Fault Protection Value Register 0x00000068 32 read-write 0x00000000 FPVH0 Fault Protection Value for PWMH output on channel 0 0 1 read-write FPVH1 Fault Protection Value for PWMH output on channel 1 1 1 read-write FPVH2 Fault Protection Value for PWMH output on channel 2 2 1 read-write FPVH3 Fault Protection Value for PWMH output on channel 3 3 1 read-write FPVH4 Fault Protection Value for PWMH output on channel 4 4 1 read-write FPVH5 Fault Protection Value for PWMH output on channel 5 5 1 read-write FPVH6 Fault Protection Value for PWMH output on channel 6 6 1 read-write FPVH7 Fault Protection Value for PWMH output on channel 7 7 1 read-write FPVL0 Fault Protection Value for PWML output on channel 0 16 1 read-write FPVL1 Fault Protection Value for PWML output on channel 1 17 1 read-write FPVL2 Fault Protection Value for PWML output on channel 2 18 1 read-write FPVL3 Fault Protection Value for PWML output on channel 3 19 1 read-write FPVL4 Fault Protection Value for PWML output on channel 4 20 1 read-write FPVL5 Fault Protection Value for PWML output on channel 5 21 1 read-write FPVL6 Fault Protection Value for PWML output on channel 6 22 1 read-write FPVL7 Fault Protection Value for PWML output on channel 7 23 1 read-write FPE1 PWM Fault Protection Enable Register 1 0x0000006C 32 read-write 0x00000000 FPE0 Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) 0 8 read-write FPE1 Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) 8 8 read-write FPE2 Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) 16 8 read-write FPE3 Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) 24 8 read-write FPE2 PWM Fault Protection Enable Register 2 0x00000070 32 read-write 0x00000000 FPE4 Fault Protection Enable for channel 4 (fault input bit varies from 0 to 5) 0 8 read-write FPE5 Fault Protection Enable for channel 5 (fault input bit varies from 0 to 5) 8 8 read-write FPE6 Fault Protection Enable for channel 6 (fault input bit varies from 0 to 5) 16 8 read-write FPE7 Fault Protection Enable for channel 7 (fault input bit varies from 0 to 5) 24 8 read-write 2 4 0-1 ELMR[%s] PWM Event Line 0 Mode Register 0x0000007C 32 read-write CSEL0 Comparison 0 Selection 0 1 read-write CSEL1 Comparison 1 Selection 1 1 read-write CSEL2 Comparison 2 Selection 2 1 read-write CSEL3 Comparison 3 Selection 3 1 read-write CSEL4 Comparison 4 Selection 4 1 read-write CSEL5 Comparison 5 Selection 5 1 read-write CSEL6 Comparison 6 Selection 6 1 read-write CSEL7 Comparison 7 Selection 7 1 read-write SMMR PWM Stepper Motor Mode Register 0x000000B0 32 read-write 0x00000000 GCEN0 Gray Count ENable 0 1 read-write GCEN1 Gray Count ENable 1 1 read-write GCEN2 Gray Count ENable 2 1 read-write GCEN3 Gray Count ENable 3 1 read-write DOWN0 DOWN Count 16 1 read-write DOWN1 DOWN Count 17 1 read-write DOWN2 DOWN Count 18 1 read-write DOWN3 DOWN Count 19 1 read-write WPCR PWM Write Protect Control Register 0x000000E4 32 write-only WPCMD Write Protect Command 0 2 write-only WPRG0 Write Protect Register Group 0 2 1 write-only WPRG1 Write Protect Register Group 1 3 1 write-only WPRG2 Write Protect Register Group 2 4 1 write-only WPRG3 Write Protect Register Group 3 5 1 write-only WPRG4 Write Protect Register Group 4 6 1 write-only WPRG5 Write Protect Register Group 5 7 1 write-only WPKEY Write Protect Key 8 24 write-only WPSR PWM Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPSWS0 Write Protect SW Status 0 1 read-only WPSWS1 Write Protect SW Status 1 1 read-only WPSWS2 Write Protect SW Status 2 1 read-only WPSWS3 Write Protect SW Status 3 1 read-only WPSWS4 Write Protect SW Status 4 1 read-only WPSWS5 Write Protect SW Status 5 1 read-only WPVS Write Protect Violation Status 7 1 read-only WPHWS0 Write Protect HW Status 8 1 read-only WPHWS1 Write Protect HW Status 9 1 read-only WPHWS2 Write Protect HW Status 10 1 read-only WPHWS3 Write Protect HW Status 11 1 read-only WPHWS4 Write Protect HW Status 12 1 read-only WPHWS5 Write Protect HW Status 13 1 read-only WPVSRC Write Protect Violation Source 16 16 read-only CMPV0 PWM Comparison 0 Value Register 0x00000130 32 read-write 0x00000000 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPVUPD0 PWM Comparison 0 Value Update Register 0x00000134 32 write-only CVUPD Comparison x Value Update 0 24 write-only CVMUPD Comparison x Value Mode Update 24 1 write-only CMPM0 PWM Comparison 0 Mode Register 0x00000138 32 read-write 0x00000000 CEN Comparison x Enable 0 1 read-write CTR Comparison x Trigger 4 4 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPMUPD0 PWM Comparison 0 Mode Update Register 0x0000013C 32 write-only CENUPD Comparison x Enable Update 0 1 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CPRUPD Comparison x Period Update 8 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPV1 PWM Comparison 1 Value Register 0x00000140 32 read-write 0x00000000 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPVUPD1 PWM Comparison 1 Value Update Register 0x00000144 32 write-only CVUPD Comparison x Value Update 0 24 write-only CVMUPD Comparison x Value Mode Update 24 1 write-only CMPM1 PWM Comparison 1 Mode Register 0x00000148 32 read-write 0x00000000 CEN Comparison x Enable 0 1 read-write CTR Comparison x Trigger 4 4 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPMUPD1 PWM Comparison 1 Mode Update Register 0x0000014C 32 write-only CENUPD Comparison x Enable Update 0 1 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CPRUPD Comparison x Period Update 8 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPV2 PWM Comparison 2 Value Register 0x00000150 32 read-write 0x00000000 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPVUPD2 PWM Comparison 2 Value Update Register 0x00000154 32 write-only CVUPD Comparison x Value Update 0 24 write-only CVMUPD Comparison x Value Mode Update 24 1 write-only CMPM2 PWM Comparison 2 Mode Register 0x00000158 32 read-write 0x00000000 CEN Comparison x Enable 0 1 read-write CTR Comparison x Trigger 4 4 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPMUPD2 PWM Comparison 2 Mode Update Register 0x0000015C 32 write-only CENUPD Comparison x Enable Update 0 1 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CPRUPD Comparison x Period Update 8 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPV3 PWM Comparison 3 Value Register 0x00000160 32 read-write 0x00000000 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPVUPD3 PWM Comparison 3 Value Update Register 0x00000164 32 write-only CVUPD Comparison x Value Update 0 24 write-only CVMUPD Comparison x Value Mode Update 24 1 write-only CMPM3 PWM Comparison 3 Mode Register 0x00000168 32 read-write 0x00000000 CEN Comparison x Enable 0 1 read-write CTR Comparison x Trigger 4 4 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPMUPD3 PWM Comparison 3 Mode Update Register 0x0000016C 32 write-only CENUPD Comparison x Enable Update 0 1 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CPRUPD Comparison x Period Update 8 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPV4 PWM Comparison 4 Value Register 0x00000170 32 read-write 0x00000000 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPVUPD4 PWM Comparison 4 Value Update Register 0x00000174 32 write-only CVUPD Comparison x Value Update 0 24 write-only CVMUPD Comparison x Value Mode Update 24 1 write-only CMPM4 PWM Comparison 4 Mode Register 0x00000178 32 read-write 0x00000000 CEN Comparison x Enable 0 1 read-write CTR Comparison x Trigger 4 4 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPMUPD4 PWM Comparison 4 Mode Update Register 0x0000017C 32 write-only CENUPD Comparison x Enable Update 0 1 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CPRUPD Comparison x Period Update 8 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPV5 PWM Comparison 5 Value Register 0x00000180 32 read-write 0x00000000 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPVUPD5 PWM Comparison 5 Value Update Register 0x00000184 32 write-only CVUPD Comparison x Value Update 0 24 write-only CVMUPD Comparison x Value Mode Update 24 1 write-only CMPM5 PWM Comparison 5 Mode Register 0x00000188 32 read-write 0x00000000 CEN Comparison x Enable 0 1 read-write CTR Comparison x Trigger 4 4 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPMUPD5 PWM Comparison 5 Mode Update Register 0x0000018C 32 write-only CENUPD Comparison x Enable Update 0 1 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CPRUPD Comparison x Period Update 8 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPV6 PWM Comparison 6 Value Register 0x00000190 32 read-write 0x00000000 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPVUPD6 PWM Comparison 6 Value Update Register 0x00000194 32 write-only CVUPD Comparison x Value Update 0 24 write-only CVMUPD Comparison x Value Mode Update 24 1 write-only CMPM6 PWM Comparison 6 Mode Register 0x00000198 32 read-write 0x00000000 CEN Comparison x Enable 0 1 read-write CTR Comparison x Trigger 4 4 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPMUPD6 PWM Comparison 6 Mode Update Register 0x0000019C 32 write-only CENUPD Comparison x Enable Update 0 1 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CPRUPD Comparison x Period Update 8 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPV7 PWM Comparison 7 Value Register 0x000001A0 32 read-write 0x00000000 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPVUPD7 PWM Comparison 7 Value Update Register 0x000001A4 32 write-only CVUPD Comparison x Value Update 0 24 write-only CVMUPD Comparison x Value Mode Update 24 1 write-only CMPM7 PWM Comparison 7 Mode Register 0x000001A8 32 read-write 0x00000000 CEN Comparison x Enable 0 1 read-write CTR Comparison x Trigger 4 4 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPMUPD7 PWM Comparison 7 Mode Update Register 0x000001AC 32 write-only CENUPD Comparison x Enable Update 0 1 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CPRUPD Comparison x Period Update 8 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMR0 PWM Channel Mode Register (ch_num = 0) 0x00000200 32 read-write 0x00000000 CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC CALG Channel Alignment 8 1 read-write CPOL Channel Polarity 9 1 read-write CES Counter Event Selection 10 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CDTY0 PWM Channel Duty Cycle Register (ch_num = 0) 0x00000204 32 read-write 0x00000000 CDTY Channel Duty-Cycle 0 24 read-write CDTYUPD0 PWM Channel Duty Cycle Update Register (ch_num = 0) 0x00000208 32 write-only CDTYUPD Channel Duty-Cycle Update 0 24 write-only CPRD0 PWM Channel Period Register (ch_num = 0) 0x0000020C 32 read-write 0x00000000 CPRD Channel Period 0 24 read-write CPRDUPD0 PWM Channel Period Update Register (ch_num = 0) 0x00000210 32 write-only CPRDUPD Channel Period Update 0 24 write-only CCNT0 PWM Channel Counter Register (ch_num = 0) 0x00000214 32 read-only 0x00000000 CNT Channel Counter Register 0 24 read-only DT0 PWM Channel Dead Time Register (ch_num = 0) 0x00000218 32 read-write 0x00000000 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DTUPD0 PWM Channel Dead Time Update Register (ch_num = 0) 0x0000021C 32 write-only DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only CMR1 PWM Channel Mode Register (ch_num = 1) 0x00000220 32 read-write 0x00000000 CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC CALG Channel Alignment 8 1 read-write CPOL Channel Polarity 9 1 read-write CES Counter Event Selection 10 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CDTY1 PWM Channel Duty Cycle Register (ch_num = 1) 0x00000224 32 read-write 0x00000000 CDTY Channel Duty-Cycle 0 24 read-write CDTYUPD1 PWM Channel Duty Cycle Update Register (ch_num = 1) 0x00000228 32 write-only CDTYUPD Channel Duty-Cycle Update 0 24 write-only CPRD1 PWM Channel Period Register (ch_num = 1) 0x0000022C 32 read-write 0x00000000 CPRD Channel Period 0 24 read-write CPRDUPD1 PWM Channel Period Update Register (ch_num = 1) 0x00000230 32 write-only CPRDUPD Channel Period Update 0 24 write-only CCNT1 PWM Channel Counter Register (ch_num = 1) 0x00000234 32 read-only 0x00000000 CNT Channel Counter Register 0 24 read-only DT1 PWM Channel Dead Time Register (ch_num = 1) 0x00000238 32 read-write 0x00000000 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DTUPD1 PWM Channel Dead Time Update Register (ch_num = 1) 0x0000023C 32 write-only DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only CMR2 PWM Channel Mode Register (ch_num = 2) 0x00000240 32 read-write 0x00000000 CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC CALG Channel Alignment 8 1 read-write CPOL Channel Polarity 9 1 read-write CES Counter Event Selection 10 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CDTY2 PWM Channel Duty Cycle Register (ch_num = 2) 0x00000244 32 read-write 0x00000000 CDTY Channel Duty-Cycle 0 24 read-write CDTYUPD2 PWM Channel Duty Cycle Update Register (ch_num = 2) 0x00000248 32 write-only CDTYUPD Channel Duty-Cycle Update 0 24 write-only CPRD2 PWM Channel Period Register (ch_num = 2) 0x0000024C 32 read-write 0x00000000 CPRD Channel Period 0 24 read-write CPRDUPD2 PWM Channel Period Update Register (ch_num = 2) 0x00000250 32 write-only CPRDUPD Channel Period Update 0 24 write-only CCNT2 PWM Channel Counter Register (ch_num = 2) 0x00000254 32 read-only 0x00000000 CNT Channel Counter Register 0 24 read-only DT2 PWM Channel Dead Time Register (ch_num = 2) 0x00000258 32 read-write 0x00000000 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DTUPD2 PWM Channel Dead Time Update Register (ch_num = 2) 0x0000025C 32 write-only DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only CMR3 PWM Channel Mode Register (ch_num = 3) 0x00000260 32 read-write 0x00000000 CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC CALG Channel Alignment 8 1 read-write CPOL Channel Polarity 9 1 read-write CES Counter Event Selection 10 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CDTY3 PWM Channel Duty Cycle Register (ch_num = 3) 0x00000264 32 read-write 0x00000000 CDTY Channel Duty-Cycle 0 24 read-write CDTYUPD3 PWM Channel Duty Cycle Update Register (ch_num = 3) 0x00000268 32 write-only CDTYUPD Channel Duty-Cycle Update 0 24 write-only CPRD3 PWM Channel Period Register (ch_num = 3) 0x0000026C 32 read-write 0x00000000 CPRD Channel Period 0 24 read-write CPRDUPD3 PWM Channel Period Update Register (ch_num = 3) 0x00000270 32 write-only CPRDUPD Channel Period Update 0 24 write-only CCNT3 PWM Channel Counter Register (ch_num = 3) 0x00000274 32 read-only 0x00000000 CNT Channel Counter Register 0 24 read-only DT3 PWM Channel Dead Time Register (ch_num = 3) 0x00000278 32 read-write 0x00000000 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DTUPD3 PWM Channel Dead Time Update Register (ch_num = 3) 0x0000027C 32 write-only DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only CMR4 PWM Channel Mode Register (ch_num = 4) 0x00000280 32 read-write 0x00000000 CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC CALG Channel Alignment 8 1 read-write CPOL Channel Polarity 9 1 read-write CES Counter Event Selection 10 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CDTY4 PWM Channel Duty Cycle Register (ch_num = 4) 0x00000284 32 read-write 0x00000000 CDTY Channel Duty-Cycle 0 24 read-write CDTYUPD4 PWM Channel Duty Cycle Update Register (ch_num = 4) 0x00000288 32 write-only CDTYUPD Channel Duty-Cycle Update 0 24 write-only CPRD4 PWM Channel Period Register (ch_num = 4) 0x0000028C 32 read-write 0x00000000 CPRD Channel Period 0 24 read-write CPRDUPD4 PWM Channel Period Update Register (ch_num = 4) 0x00000290 32 write-only CPRDUPD Channel Period Update 0 24 write-only CCNT4 PWM Channel Counter Register (ch_num = 4) 0x00000294 32 read-only 0x00000000 CNT Channel Counter Register 0 24 read-only DT4 PWM Channel Dead Time Register (ch_num = 4) 0x00000298 32 read-write 0x00000000 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DTUPD4 PWM Channel Dead Time Update Register (ch_num = 4) 0x0000029C 32 write-only DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only CMR5 PWM Channel Mode Register (ch_num = 5) 0x000002A0 32 read-write 0x00000000 CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC CALG Channel Alignment 8 1 read-write CPOL Channel Polarity 9 1 read-write CES Counter Event Selection 10 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CDTY5 PWM Channel Duty Cycle Register (ch_num = 5) 0x000002A4 32 read-write 0x00000000 CDTY Channel Duty-Cycle 0 24 read-write CDTYUPD5 PWM Channel Duty Cycle Update Register (ch_num = 5) 0x000002A8 32 write-only CDTYUPD Channel Duty-Cycle Update 0 24 write-only CPRD5 PWM Channel Period Register (ch_num = 5) 0x000002AC 32 read-write 0x00000000 CPRD Channel Period 0 24 read-write CPRDUPD5 PWM Channel Period Update Register (ch_num = 5) 0x000002B0 32 write-only CPRDUPD Channel Period Update 0 24 write-only CCNT5 PWM Channel Counter Register (ch_num = 5) 0x000002B4 32 read-only 0x00000000 CNT Channel Counter Register 0 24 read-only DT5 PWM Channel Dead Time Register (ch_num = 5) 0x000002B8 32 read-write 0x00000000 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DTUPD5 PWM Channel Dead Time Update Register (ch_num = 5) 0x000002BC 32 write-only DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only CMR6 PWM Channel Mode Register (ch_num = 6) 0x000002C0 32 read-write 0x00000000 CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC CALG Channel Alignment 8 1 read-write CPOL Channel Polarity 9 1 read-write CES Counter Event Selection 10 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CDTY6 PWM Channel Duty Cycle Register (ch_num = 6) 0x000002C4 32 read-write 0x00000000 CDTY Channel Duty-Cycle 0 24 read-write CDTYUPD6 PWM Channel Duty Cycle Update Register (ch_num = 6) 0x000002C8 32 write-only CDTYUPD Channel Duty-Cycle Update 0 24 write-only CPRD6 PWM Channel Period Register (ch_num = 6) 0x000002CC 32 read-write 0x00000000 CPRD Channel Period 0 24 read-write CPRDUPD6 PWM Channel Period Update Register (ch_num = 6) 0x000002D0 32 write-only CPRDUPD Channel Period Update 0 24 write-only CCNT6 PWM Channel Counter Register (ch_num = 6) 0x000002D4 32 read-only 0x00000000 CNT Channel Counter Register 0 24 read-only DT6 PWM Channel Dead Time Register (ch_num = 6) 0x000002D8 32 read-write 0x00000000 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DTUPD6 PWM Channel Dead Time Update Register (ch_num = 6) 0x000002DC 32 write-only DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only CMR7 PWM Channel Mode Register (ch_num = 7) 0x000002E0 32 read-write 0x00000000 CPRE Channel Pre-scaler 0 4 read-write MCK Master clock 0x0 MCK_DIV_2 Master clock/2 0x1 MCK_DIV_4 Master clock/4 0x2 MCK_DIV_8 Master clock/8 0x3 MCK_DIV_16 Master clock/16 0x4 MCK_DIV_32 Master clock/32 0x5 MCK_DIV_64 Master clock/64 0x6 MCK_DIV_128 Master clock/128 0x7 MCK_DIV_256 Master clock/256 0x8 MCK_DIV_512 Master clock/512 0x9 MCK_DIV_1024 Master clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC CALG Channel Alignment 8 1 read-write CPOL Channel Polarity 9 1 read-write CES Counter Event Selection 10 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write CDTY7 PWM Channel Duty Cycle Register (ch_num = 7) 0x000002E4 32 read-write 0x00000000 CDTY Channel Duty-Cycle 0 24 read-write CDTYUPD7 PWM Channel Duty Cycle Update Register (ch_num = 7) 0x000002E8 32 write-only CDTYUPD Channel Duty-Cycle Update 0 24 write-only CPRD7 PWM Channel Period Register (ch_num = 7) 0x000002EC 32 read-write 0x00000000 CPRD Channel Period 0 24 read-write CPRDUPD7 PWM Channel Period Update Register (ch_num = 7) 0x000002F0 32 write-only CPRDUPD Channel Period Update 0 24 write-only CCNT7 PWM Channel Counter Register (ch_num = 7) 0x000002F4 32 read-only 0x00000000 CNT Channel Counter Register 0 24 read-only DT7 PWM Channel Dead Time Register (ch_num = 7) 0x000002F8 32 read-write 0x00000000 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DTUPD7 PWM Channel Dead Time Update Register (ch_num = 7) 0x000002FC 32 write-only DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only USART0 6089ZF Universal Synchronous Asynchronous Receiver Transmitter 0 USART USART0_ 0x40098000 0 0x4000 registers USART0 17 CR Control Register 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only STTBRK Start Break 9 1 write-only STPBRK Stop Break 10 1 write-only STTTO Start Time-out 11 1 write-only SENDA Send Address 12 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RETTO Rearm Time-out 15 1 write-only RTSEN Request to Send Enable 18 1 write-only RTSDIS Request to Send Disable 19 1 write-only LINABT Abort LIN Transmission 20 1 write-only LINWKUP Send LIN Wakeup Signal 21 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only MR Mode Register 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_MASTER LIN master 0xA LIN_SLAVE LIN Slave 0xB SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 SYNC Synchronous Mode Select 8 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 MSBF Bit Order 16 1 read-write MODE9 9-bit Character Length 17 1 read-write CLKO Clock Output Select 18 1 read-write OVER Oversampling Mode 19 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write DSNACK Disable Successive NACK 21 1 read-write VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write INVDATA Inverted Data 23 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write FILTER Infrared Receive Line Filter 28 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write ONEBIT Start Frame Delimiter Selector 31 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write WRDBT Wait Read Data Before Transfer 20 1 read-write IER Interrupt Enable Register 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only ENDRX End of Receive Transfer Interrupt Enable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Enable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only TXBUFE Buffer Empty Interrupt Enable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Enable (available in all USART modes of operation) 12 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only IER_LIN_MODE Interrupt Enable Register LIN_MODE 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Enable 13 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 write-only LINTC LIN Transfer Completed Interrupt Enable 15 1 write-only LINBE LIN Bus Error Interrupt Enable 25 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 write-only LINIPE LIN Identifier Parity Interrupt Enable 27 1 write-only LINCE LIN Checksum Error Interrupt Enable 28 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 write-only IDR Interrupt Disable Register 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation) 12 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only IDR_LIN_MODE Interrupt Disable Register LIN_MODE 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Disable 13 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 write-only LINTC LIN Transfer Completed Interrupt Disable 15 1 write-only LINBE LIN Bus Error Interrupt Disable 25 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 write-only LINIPE LIN Identifier Parity Interrupt Disable 27 1 write-only LINCE LIN Checksum Error Interrupt Disable 28 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 write-only IMR Interrupt Mask Register 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only ENDRX End of Receive Transfer Interrupt Mask (available in all USART modes of operation) 3 1 read-only ENDTX End of Transmit Interrupt Mask (available in all USART modes of operation) 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only TXBUFE Buffer Empty Interrupt Mask (available in all USART modes of operation) 11 1 read-only RXBUFF Buffer Full Interrupt Mask (available in all USART modes of operation) 12 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only IMR_LIN_MODE Interrupt Mask Register LIN_MODE 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only LINBK LIN Break Sent or LIN Break Received Interrupt Mask 13 1 read-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask 14 1 read-only LINTC LIN Transfer Completed Interrupt Mask 15 1 read-only LINBE LIN Bus Error Interrupt Mask 25 1 read-only LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 read-only LINIPE LIN Identifier Parity Interrupt Mask 27 1 read-only LINCE LIN Checksum Error Interrupt Mask 28 1 read-only LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 read-only CSR Channel Status Register 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only RXBRK Break Received/End of Break 2 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXEMPTY Transmitter Empty 9 1 read-only ITER Max Number of Repetitions Reached 10 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only RXBUFF Reception Buffer Full 12 1 read-only NACK Non Acknowledge Interrupt 13 1 read-only CTSIC Clear to Send Input Change Flag 19 1 read-only CTS Image of CTS Input 23 1 read-only MANERR Manchester Error 24 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error 5 1 read-only TXEMPTY Transmitter Empty 9 1 read-only UNRE Underrun Error 10 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only CSR_LIN_MODE Channel Status Register LIN_MODE 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only LINBK LIN Break Sent or LIN Break Received 13 1 read-only LINID LIN Identifier Sent or LIN Identifier Received 14 1 read-only LINTC LIN Transfer Completed 15 1 read-only LINBLS LIN Bus Line Status 23 1 read-only LINBE LIN Bit Error 25 1 read-only LINISFE LIN Inconsistent Synch Field Error 26 1 read-only LINIPE LIN Identifier Parity Error 27 1 read-only LINCE LIN Checksum Error 28 1 read-only LINSNRE LIN Slave Not Responding Error 29 1 read-only RHR Receive Holding Register 0x00000018 32 read-only 0x00000000 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only THR Transmit Holding Register 0x0000001C 32 write-only TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only BRGR Baud Rate Generator Register 0x00000020 32 read-write 0x00000000 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write RTOR Receiver Time-out Register 0x00000024 32 read-write 0x00000000 TO Time-out Value 0 17 read-write TTGR Transmitter Timeguard Register 0x00000028 32 read-write 0x00000000 TG Timeguard Value 0 8 read-write FIDI FI DI Ratio Register 0x00000040 32 read-write 0x00000174 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write NER Number of Errors Register 0x00000044 32 read-only NB_ERRORS Number of Errors 0 8 read-only IF IrDA Filter Register 0x0000004C 32 read-write 0x00000000 IRDA_FILTER IrDA Filter 0 8 read-write MAN Manchester Configuration Register 0x00000050 32 read-write 0xB0011004 TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 RX_MPOL Receiver Manchester Polarity 28 1 read-write ONE Must Be Set to 1 29 1 read-write DRIFT Drift Compensation 30 1 read-write LINMR LIN Mode Register 0x00000054 32 read-write 0x00000000 NACT LIN Node Action 0 2 read-write PUBLISH The USART transmits the response. 0x0 SUBSCRIBE The USART receives the response. 0x1 IGNORE The USART does not transmit and does not receive the response. 0x2 PARDIS Parity Disable 2 1 read-write CHKDIS Checksum Disable 3 1 read-write CHKTYP Checksum Type 4 1 read-write DLM Data Length Mode 5 1 read-write FSDIS Frame Slot Mode Disable 6 1 read-write WKUPTYP Wakeup Signal Type 7 1 read-write DLC Data Length Control 8 8 read-write PDCM PDC Mode 16 1 read-write LINIR LIN Identifier Register 0x00000058 32 read-write 0x00000000 IDCHR Identifier Character 0 8 read-write LINBRR LIN Baud Rate Register 0x0000005C 32 read-only 0x00000000 LINCD Clock Divider after Synchronization 0 16 read-only LINFP Fractional Part after Synchronization 16 3 read-only WPMR Write Protection Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only USART1 6089ZF Universal Synchronous Asynchronous Receiver Transmitter 1 USART USART1_ 0x4009C000 0 0x4000 registers USART1 18 CR Control Register 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only STTBRK Start Break 9 1 write-only STPBRK Stop Break 10 1 write-only STTTO Start Time-out 11 1 write-only SENDA Send Address 12 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RETTO Rearm Time-out 15 1 write-only RTSEN Request to Send Enable 18 1 write-only RTSDIS Request to Send Disable 19 1 write-only LINABT Abort LIN Transmission 20 1 write-only LINWKUP Send LIN Wakeup Signal 21 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only MR Mode Register 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_MASTER LIN master 0xA LIN_SLAVE LIN Slave 0xB SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 SYNC Synchronous Mode Select 8 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 MSBF Bit Order 16 1 read-write MODE9 9-bit Character Length 17 1 read-write CLKO Clock Output Select 18 1 read-write OVER Oversampling Mode 19 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write DSNACK Disable Successive NACK 21 1 read-write VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write INVDATA Inverted Data 23 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write FILTER Infrared Receive Line Filter 28 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write ONEBIT Start Frame Delimiter Selector 31 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write WRDBT Wait Read Data Before Transfer 20 1 read-write IER Interrupt Enable Register 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only ENDRX End of Receive Transfer Interrupt Enable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Enable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only TXBUFE Buffer Empty Interrupt Enable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Enable (available in all USART modes of operation) 12 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only IER_LIN_MODE Interrupt Enable Register LIN_MODE 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Enable 13 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 write-only LINTC LIN Transfer Completed Interrupt Enable 15 1 write-only LINBE LIN Bus Error Interrupt Enable 25 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 write-only LINIPE LIN Identifier Parity Interrupt Enable 27 1 write-only LINCE LIN Checksum Error Interrupt Enable 28 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 write-only IDR Interrupt Disable Register 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation) 12 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only IDR_LIN_MODE Interrupt Disable Register LIN_MODE 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Disable 13 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 write-only LINTC LIN Transfer Completed Interrupt Disable 15 1 write-only LINBE LIN Bus Error Interrupt Disable 25 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 write-only LINIPE LIN Identifier Parity Interrupt Disable 27 1 write-only LINCE LIN Checksum Error Interrupt Disable 28 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 write-only IMR Interrupt Mask Register 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only ENDRX End of Receive Transfer Interrupt Mask (available in all USART modes of operation) 3 1 read-only ENDTX End of Transmit Interrupt Mask (available in all USART modes of operation) 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only TXBUFE Buffer Empty Interrupt Mask (available in all USART modes of operation) 11 1 read-only RXBUFF Buffer Full Interrupt Mask (available in all USART modes of operation) 12 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only IMR_LIN_MODE Interrupt Mask Register LIN_MODE 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only LINBK LIN Break Sent or LIN Break Received Interrupt Mask 13 1 read-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask 14 1 read-only LINTC LIN Transfer Completed Interrupt Mask 15 1 read-only LINBE LIN Bus Error Interrupt Mask 25 1 read-only LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 read-only LINIPE LIN Identifier Parity Interrupt Mask 27 1 read-only LINCE LIN Checksum Error Interrupt Mask 28 1 read-only LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 read-only CSR Channel Status Register 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only RXBRK Break Received/End of Break 2 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXEMPTY Transmitter Empty 9 1 read-only ITER Max Number of Repetitions Reached 10 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only RXBUFF Reception Buffer Full 12 1 read-only NACK Non Acknowledge Interrupt 13 1 read-only CTSIC Clear to Send Input Change Flag 19 1 read-only CTS Image of CTS Input 23 1 read-only MANERR Manchester Error 24 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error 5 1 read-only TXEMPTY Transmitter Empty 9 1 read-only UNRE Underrun Error 10 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only CSR_LIN_MODE Channel Status Register LIN_MODE 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only LINBK LIN Break Sent or LIN Break Received 13 1 read-only LINID LIN Identifier Sent or LIN Identifier Received 14 1 read-only LINTC LIN Transfer Completed 15 1 read-only LINBLS LIN Bus Line Status 23 1 read-only LINBE LIN Bit Error 25 1 read-only LINISFE LIN Inconsistent Synch Field Error 26 1 read-only LINIPE LIN Identifier Parity Error 27 1 read-only LINCE LIN Checksum Error 28 1 read-only LINSNRE LIN Slave Not Responding Error 29 1 read-only RHR Receive Holding Register 0x00000018 32 read-only 0x00000000 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only THR Transmit Holding Register 0x0000001C 32 write-only TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only BRGR Baud Rate Generator Register 0x00000020 32 read-write 0x00000000 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write RTOR Receiver Time-out Register 0x00000024 32 read-write 0x00000000 TO Time-out Value 0 17 read-write TTGR Transmitter Timeguard Register 0x00000028 32 read-write 0x00000000 TG Timeguard Value 0 8 read-write FIDI FI DI Ratio Register 0x00000040 32 read-write 0x00000174 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write NER Number of Errors Register 0x00000044 32 read-only NB_ERRORS Number of Errors 0 8 read-only IF IrDA Filter Register 0x0000004C 32 read-write 0x00000000 IRDA_FILTER IrDA Filter 0 8 read-write MAN Manchester Configuration Register 0x00000050 32 read-write 0xB0011004 TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 RX_MPOL Receiver Manchester Polarity 28 1 read-write ONE Must Be Set to 1 29 1 read-write DRIFT Drift Compensation 30 1 read-write LINMR LIN Mode Register 0x00000054 32 read-write 0x00000000 NACT LIN Node Action 0 2 read-write PUBLISH The USART transmits the response. 0x0 SUBSCRIBE The USART receives the response. 0x1 IGNORE The USART does not transmit and does not receive the response. 0x2 PARDIS Parity Disable 2 1 read-write CHKDIS Checksum Disable 3 1 read-write CHKTYP Checksum Type 4 1 read-write DLM Data Length Mode 5 1 read-write FSDIS Frame Slot Mode Disable 6 1 read-write WKUPTYP Wakeup Signal Type 7 1 read-write DLC Data Length Control 8 8 read-write PDCM PDC Mode 16 1 read-write LINIR LIN Identifier Register 0x00000058 32 read-write 0x00000000 IDCHR Identifier Character 0 8 read-write LINBRR LIN Baud Rate Register 0x0000005C 32 read-only 0x00000000 LINCD Clock Divider after Synchronization 0 16 read-only LINFP Fractional Part after Synchronization 16 3 read-only WPMR Write Protection Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only USART2 6089ZF Universal Synchronous Asynchronous Receiver Transmitter 2 USART USART2_ 0x400A0000 0 0x4000 registers USART2 19 CR Control Register 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only STTBRK Start Break 9 1 write-only STPBRK Stop Break 10 1 write-only STTTO Start Time-out 11 1 write-only SENDA Send Address 12 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RETTO Rearm Time-out 15 1 write-only RTSEN Request to Send Enable 18 1 write-only RTSDIS Request to Send Disable 19 1 write-only LINABT Abort LIN Transmission 20 1 write-only LINWKUP Send LIN Wakeup Signal 21 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only MR Mode Register 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_MASTER LIN master 0xA LIN_SLAVE LIN Slave 0xB SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 SYNC Synchronous Mode Select 8 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 MSBF Bit Order 16 1 read-write MODE9 9-bit Character Length 17 1 read-write CLKO Clock Output Select 18 1 read-write OVER Oversampling Mode 19 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write DSNACK Disable Successive NACK 21 1 read-write VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write INVDATA Inverted Data 23 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write FILTER Infrared Receive Line Filter 28 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write ONEBIT Start Frame Delimiter Selector 31 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write WRDBT Wait Read Data Before Transfer 20 1 read-write IER Interrupt Enable Register 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only ENDRX End of Receive Transfer Interrupt Enable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Enable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only TXBUFE Buffer Empty Interrupt Enable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Enable (available in all USART modes of operation) 12 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only IER_LIN_MODE Interrupt Enable Register LIN_MODE 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Enable 13 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 write-only LINTC LIN Transfer Completed Interrupt Enable 15 1 write-only LINBE LIN Bus Error Interrupt Enable 25 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 write-only LINIPE LIN Identifier Parity Interrupt Enable 27 1 write-only LINCE LIN Checksum Error Interrupt Enable 28 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 write-only IDR Interrupt Disable Register 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation) 12 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only IDR_LIN_MODE Interrupt Disable Register LIN_MODE 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Disable 13 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 write-only LINTC LIN Transfer Completed Interrupt Disable 15 1 write-only LINBE LIN Bus Error Interrupt Disable 25 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 write-only LINIPE LIN Identifier Parity Interrupt Disable 27 1 write-only LINCE LIN Checksum Error Interrupt Disable 28 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 write-only IMR Interrupt Mask Register 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only ENDRX End of Receive Transfer Interrupt Mask (available in all USART modes of operation) 3 1 read-only ENDTX End of Transmit Interrupt Mask (available in all USART modes of operation) 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only TXBUFE Buffer Empty Interrupt Mask (available in all USART modes of operation) 11 1 read-only RXBUFF Buffer Full Interrupt Mask (available in all USART modes of operation) 12 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only IMR_LIN_MODE Interrupt Mask Register LIN_MODE 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only LINBK LIN Break Sent or LIN Break Received Interrupt Mask 13 1 read-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask 14 1 read-only LINTC LIN Transfer Completed Interrupt Mask 15 1 read-only LINBE LIN Bus Error Interrupt Mask 25 1 read-only LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 read-only LINIPE LIN Identifier Parity Interrupt Mask 27 1 read-only LINCE LIN Checksum Error Interrupt Mask 28 1 read-only LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 read-only CSR Channel Status Register 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only RXBRK Break Received/End of Break 2 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXEMPTY Transmitter Empty 9 1 read-only ITER Max Number of Repetitions Reached 10 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only RXBUFF Reception Buffer Full 12 1 read-only NACK Non Acknowledge Interrupt 13 1 read-only CTSIC Clear to Send Input Change Flag 19 1 read-only CTS Image of CTS Input 23 1 read-only MANERR Manchester Error 24 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error 5 1 read-only TXEMPTY Transmitter Empty 9 1 read-only UNRE Underrun Error 10 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only CSR_LIN_MODE Channel Status Register LIN_MODE 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only LINBK LIN Break Sent or LIN Break Received 13 1 read-only LINID LIN Identifier Sent or LIN Identifier Received 14 1 read-only LINTC LIN Transfer Completed 15 1 read-only LINBLS LIN Bus Line Status 23 1 read-only LINBE LIN Bit Error 25 1 read-only LINISFE LIN Inconsistent Synch Field Error 26 1 read-only LINIPE LIN Identifier Parity Error 27 1 read-only LINCE LIN Checksum Error 28 1 read-only LINSNRE LIN Slave Not Responding Error 29 1 read-only RHR Receive Holding Register 0x00000018 32 read-only 0x00000000 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only THR Transmit Holding Register 0x0000001C 32 write-only TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only BRGR Baud Rate Generator Register 0x00000020 32 read-write 0x00000000 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write RTOR Receiver Time-out Register 0x00000024 32 read-write 0x00000000 TO Time-out Value 0 17 read-write TTGR Transmitter Timeguard Register 0x00000028 32 read-write 0x00000000 TG Timeguard Value 0 8 read-write FIDI FI DI Ratio Register 0x00000040 32 read-write 0x00000174 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write NER Number of Errors Register 0x00000044 32 read-only NB_ERRORS Number of Errors 0 8 read-only IF IrDA Filter Register 0x0000004C 32 read-write 0x00000000 IRDA_FILTER IrDA Filter 0 8 read-write MAN Manchester Configuration Register 0x00000050 32 read-write 0xB0011004 TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 RX_MPOL Receiver Manchester Polarity 28 1 read-write ONE Must Be Set to 1 29 1 read-write DRIFT Drift Compensation 30 1 read-write LINMR LIN Mode Register 0x00000054 32 read-write 0x00000000 NACT LIN Node Action 0 2 read-write PUBLISH The USART transmits the response. 0x0 SUBSCRIBE The USART receives the response. 0x1 IGNORE The USART does not transmit and does not receive the response. 0x2 PARDIS Parity Disable 2 1 read-write CHKDIS Checksum Disable 3 1 read-write CHKTYP Checksum Type 4 1 read-write DLM Data Length Mode 5 1 read-write FSDIS Frame Slot Mode Disable 6 1 read-write WKUPTYP Wakeup Signal Type 7 1 read-write DLC Data Length Control 8 8 read-write PDCM PDC Mode 16 1 read-write LINIR LIN Identifier Register 0x00000058 32 read-write 0x00000000 IDCHR Identifier Character 0 8 read-write LINBRR LIN Baud Rate Register 0x0000005C 32 read-only 0x00000000 LINCD Clock Divider after Synchronization 0 16 read-only LINFP Fractional Part after Synchronization 16 3 read-only WPMR Write Protection Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only USART3 6089ZF Universal Synchronous Asynchronous Receiver Transmitter 3 USART USART3_ 0x400A4000 0 0x4000 registers USART3 20 CR Control Register 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only STTBRK Start Break 9 1 write-only STPBRK Stop Break 10 1 write-only STTTO Start Time-out 11 1 write-only SENDA Send Address 12 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RETTO Rearm Time-out 15 1 write-only RTSEN Request to Send Enable 18 1 write-only RTSDIS Request to Send Disable 19 1 write-only LINABT Abort LIN Transmission 20 1 write-only LINWKUP Send LIN Wakeup Signal 21 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only MR Mode Register 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LIN_MASTER LIN master 0xA LIN_SLAVE LIN Slave 0xB SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 SYNC Synchronous Mode Select 8 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 MSBF Bit Order 16 1 read-write MODE9 9-bit Character Length 17 1 read-write CLKO Clock Output Select 18 1 read-write OVER Oversampling Mode 19 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write DSNACK Disable Successive NACK 21 1 read-write VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write INVDATA Inverted Data 23 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write FILTER Infrared Receive Line Filter 28 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write ONEBIT Start Frame Delimiter Selector 31 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x00000004 32 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write WRDBT Wait Read Data Before Transfer 20 1 read-write IER Interrupt Enable Register 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only ENDRX End of Receive Transfer Interrupt Enable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Enable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only TXBUFE Buffer Empty Interrupt Enable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Enable (available in all USART modes of operation) 12 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only IER_LIN_MODE Interrupt Enable Register LIN_MODE 0x00000008 32 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Enable 13 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 write-only LINTC LIN Transfer Completed Interrupt Enable 15 1 write-only LINBE LIN Bus Error Interrupt Enable 25 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 write-only LINIPE LIN Identifier Parity Interrupt Enable 27 1 write-only LINCE LIN Checksum Error Interrupt Enable 28 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 write-only IDR Interrupt Disable Register 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation) 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation) 11 1 write-only RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation) 12 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only IDR_LIN_MODE Interrupt Disable Register LIN_MODE 0x0000000C 32 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXBUFE 11 1 write-only RXBUFF 12 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Disable 13 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 write-only LINTC LIN Transfer Completed Interrupt Disable 15 1 write-only LINBE LIN Bus Error Interrupt Disable 25 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 write-only LINIPE LIN Identifier Parity Interrupt Disable 27 1 write-only LINCE LIN Checksum Error Interrupt Disable 28 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 write-only IMR Interrupt Mask Register 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only ENDRX End of Receive Transfer Interrupt Mask (available in all USART modes of operation) 3 1 read-only ENDTX End of Transmit Interrupt Mask (available in all USART modes of operation) 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only TXBUFE Buffer Empty Interrupt Mask (available in all USART modes of operation) 11 1 read-only RXBUFF Buffer Full Interrupt Mask (available in all USART modes of operation) 12 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only IMR_LIN_MODE Interrupt Mask Register LIN_MODE 0x00000010 32 read-only 0x00000000 RXRDY RXRDY Interrupt Mask 0 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only LINBK LIN Break Sent or LIN Break Received Interrupt Mask 13 1 read-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask 14 1 read-only LINTC LIN Transfer Completed Interrupt Mask 15 1 read-only LINBE LIN Bus Error Interrupt Mask 25 1 read-only LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 read-only LINIPE LIN Identifier Parity Interrupt Mask 27 1 read-only LINCE LIN Checksum Error Interrupt Mask 28 1 read-only LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 read-only CSR Channel Status Register 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only RXBRK Break Received/End of Break 2 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXEMPTY Transmitter Empty 9 1 read-only ITER Max Number of Repetitions Reached 10 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only RXBUFF Reception Buffer Full 12 1 read-only NACK Non Acknowledge Interrupt 13 1 read-only CTSIC Clear to Send Input Change Flag 19 1 read-only CTS Image of CTS Input 23 1 read-only MANERR Manchester Error 24 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error 5 1 read-only TXEMPTY Transmitter Empty 9 1 read-only UNRE Underrun Error 10 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only CSR_LIN_MODE Channel Status Register LIN_MODE 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXBUFE 11 1 read-only RXBUFF 12 1 read-only LINBK LIN Break Sent or LIN Break Received 13 1 read-only LINID LIN Identifier Sent or LIN Identifier Received 14 1 read-only LINTC LIN Transfer Completed 15 1 read-only LINBLS LIN Bus Line Status 23 1 read-only LINBE LIN Bit Error 25 1 read-only LINISFE LIN Inconsistent Synch Field Error 26 1 read-only LINIPE LIN Identifier Parity Error 27 1 read-only LINCE LIN Checksum Error 28 1 read-only LINSNRE LIN Slave Not Responding Error 29 1 read-only RHR Receive Holding Register 0x00000018 32 read-only 0x00000000 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only THR Transmit Holding Register 0x0000001C 32 write-only TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only BRGR Baud Rate Generator Register 0x00000020 32 read-write 0x00000000 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write RTOR Receiver Time-out Register 0x00000024 32 read-write 0x00000000 TO Time-out Value 0 17 read-write TTGR Transmitter Timeguard Register 0x00000028 32 read-write 0x00000000 TG Timeguard Value 0 8 read-write FIDI FI DI Ratio Register 0x00000040 32 read-write 0x00000174 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write NER Number of Errors Register 0x00000044 32 read-only NB_ERRORS Number of Errors 0 8 read-only IF IrDA Filter Register 0x0000004C 32 read-write 0x00000000 IRDA_FILTER IrDA Filter 0 8 read-write MAN Manchester Configuration Register 0x00000050 32 read-write 0xB0011004 TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 RX_MPOL Receiver Manchester Polarity 28 1 read-write ONE Must Be Set to 1 29 1 read-write DRIFT Drift Compensation 30 1 read-write LINMR LIN Mode Register 0x00000054 32 read-write 0x00000000 NACT LIN Node Action 0 2 read-write PUBLISH The USART transmits the response. 0x0 SUBSCRIBE The USART receives the response. 0x1 IGNORE The USART does not transmit and does not receive the response. 0x2 PARDIS Parity Disable 2 1 read-write CHKDIS Checksum Disable 3 1 read-write CHKTYP Checksum Type 4 1 read-write DLM Data Length Mode 5 1 read-write FSDIS Frame Slot Mode Disable 6 1 read-write WKUPTYP Wakeup Signal Type 7 1 read-write DLC Data Length Control 8 8 read-write PDCM PDC Mode 16 1 read-write LINIR LIN Identifier Register 0x00000058 32 read-write 0x00000000 IDCHR Identifier Character 0 8 read-write LINBRR LIN Baud Rate Register 0x0000005C 32 read-only 0x00000000 LINCD Clock Divider after Synchronization 0 16 read-only LINFP Fractional Part after Synchronization 16 3 read-only WPMR Write Protection Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only UOTGHS 11016C USB On-The-Go Interface UOTGHS_ 0x400AC000 0 0x4000 registers UOTGHS 40 DEVCTRL Device General Control Register 0x00000000 32 read-write 0x00000100 UADD USB Address 0 7 read-write ADDEN Address Enable 7 1 read-write DETACH Detach 8 1 read-write RMWKUP Remote Wake-Up 9 1 read-write SPDCONF Mode Configuration 10 2 read-write NORMAL The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. 0x0 LOW_POWER For a better consumption, if high-speed is not needed. 0x1 HIGH_SPEED Forced high speed. 0x2 FORCED_FS The peripheral remains in full-speed mode whatever the host speed capability. 0x3 LS Low-Speed Mode Force 12 1 read-write TSTJ Test mode J 13 1 read-write TSTK Test mode K 14 1 read-write TSTPCKT Test packet mode 15 1 read-write OPMODE2 Specific Operational mode 16 1 read-write DEVISR Device Global Interrupt Status Register 0x00000004 32 read-only 0x00000000 SUSP Suspend Interrupt 0 1 read-only MSOF Micro Start of Frame Interrupt 1 1 read-only SOF Start of Frame Interrupt 2 1 read-only EORST End of Reset Interrupt 3 1 read-only WAKEUP Wake-Up Interrupt 4 1 read-only EORSM End of Resume Interrupt 5 1 read-only UPRSM Upstream Resume Interrupt 6 1 read-only PEP_0 Endpoint 0 Interrupt 12 1 read-only PEP_1 Endpoint 1 Interrupt 13 1 read-only PEP_2 Endpoint 2 Interrupt 14 1 read-only PEP_3 Endpoint 3 Interrupt 15 1 read-only PEP_4 Endpoint 4 Interrupt 16 1 read-only PEP_5 Endpoint 5 Interrupt 17 1 read-only PEP_6 Endpoint 6 Interrupt 18 1 read-only PEP_7 Endpoint 7 Interrupt 19 1 read-only PEP_8 Endpoint 8 Interrupt 20 1 read-only PEP_9 Endpoint 9 Interrupt 21 1 read-only DMA_1 DMA Channel 1 Interrupt 25 1 read-only DMA_2 DMA Channel 2 Interrupt 26 1 read-only DMA_3 DMA Channel 3 Interrupt 27 1 read-only DMA_4 DMA Channel 4 Interrupt 28 1 read-only DMA_5 DMA Channel 5 Interrupt 29 1 read-only DMA_6 DMA Channel 6 Interrupt 30 1 read-only DEVICR Device Global Interrupt Clear Register 0x00000008 32 write-only SUSPC Suspend Interrupt Clear 0 1 write-only MSOFC Micro Start of Frame Interrupt Clear 1 1 write-only SOFC Start of Frame Interrupt Clear 2 1 write-only EORSTC End of Reset Interrupt Clear 3 1 write-only WAKEUPC Wake-Up Interrupt Clear 4 1 write-only EORSMC End of Resume Interrupt Clear 5 1 write-only UPRSMC Upstream Resume Interrupt Clear 6 1 write-only DEVIFR Device Global Interrupt Set Register 0x0000000C 32 write-only SUSPS Suspend Interrupt Set 0 1 write-only MSOFS Micro Start of Frame Interrupt Set 1 1 write-only SOFS Start of Frame Interrupt Set 2 1 write-only EORSTS End of Reset Interrupt Set 3 1 write-only WAKEUPS Wake-Up Interrupt Set 4 1 write-only EORSMS End of Resume Interrupt Set 5 1 write-only UPRSMS Upstream Resume Interrupt Set 6 1 write-only DMA_1 DMA Channel 1 Interrupt Set 25 1 write-only DMA_2 DMA Channel 2 Interrupt Set 26 1 write-only DMA_3 DMA Channel 3 Interrupt Set 27 1 write-only DMA_4 DMA Channel 4 Interrupt Set 28 1 write-only DMA_5 DMA Channel 5 Interrupt Set 29 1 write-only DMA_6 DMA Channel 6 Interrupt Set 30 1 write-only DEVIMR Device Global Interrupt Mask Register 0x00000010 32 read-only 0x00000000 SUSPE Suspend Interrupt Mask 0 1 read-only MSOFE Micro Start of Frame Interrupt Mask 1 1 read-only SOFE Start of Frame Interrupt Mask 2 1 read-only EORSTE End of Reset Interrupt Mask 3 1 read-only WAKEUPE Wake-Up Interrupt Mask 4 1 read-only EORSME End of Resume Interrupt Mask 5 1 read-only UPRSME Upstream Resume Interrupt Mask 6 1 read-only PEP_0 Endpoint 0 Interrupt Mask 12 1 read-only PEP_1 Endpoint 1 Interrupt Mask 13 1 read-only PEP_2 Endpoint 2 Interrupt Mask 14 1 read-only PEP_3 Endpoint 3 Interrupt Mask 15 1 read-only PEP_4 Endpoint 4 Interrupt Mask 16 1 read-only PEP_5 Endpoint 5 Interrupt Mask 17 1 read-only PEP_6 Endpoint 6 Interrupt Mask 18 1 read-only PEP_7 Endpoint 7 Interrupt Mask 19 1 read-only PEP_8 Endpoint 8 Interrupt Mask 20 1 read-only PEP_9 Endpoint 9 Interrupt Mask 21 1 read-only DMA_1 DMA Channel 1 Interrupt Mask 25 1 read-only DMA_2 DMA Channel 2 Interrupt Mask 26 1 read-only DMA_3 DMA Channel 3 Interrupt Mask 27 1 read-only DMA_4 DMA Channel 4 Interrupt Mask 28 1 read-only DMA_5 DMA Channel 5 Interrupt Mask 29 1 read-only DMA_6 DMA Channel 6 Interrupt Mask 30 1 read-only DEVIDR Device Global Interrupt Disable Register 0x00000014 32 write-only SUSPEC Suspend Interrupt Disable 0 1 write-only MSOFEC Micro Start of Frame Interrupt Disable 1 1 write-only SOFEC Start of Frame Interrupt Disable 2 1 write-only EORSTEC End of Reset Interrupt Disable 3 1 write-only WAKEUPEC Wake-Up Interrupt Disable 4 1 write-only EORSMEC End of Resume Interrupt Disable 5 1 write-only UPRSMEC Upstream Resume Interrupt Disable 6 1 write-only PEP_0 Endpoint 0 Interrupt Disable 12 1 write-only PEP_1 Endpoint 1 Interrupt Disable 13 1 write-only PEP_2 Endpoint 2 Interrupt Disable 14 1 write-only PEP_3 Endpoint 3 Interrupt Disable 15 1 write-only PEP_4 Endpoint 4 Interrupt Disable 16 1 write-only PEP_5 Endpoint 5 Interrupt Disable 17 1 write-only PEP_6 Endpoint 6 Interrupt Disable 18 1 write-only PEP_7 Endpoint 7 Interrupt Disable 19 1 write-only PEP_8 Endpoint 8 Interrupt Disable 20 1 write-only PEP_9 Endpoint 9 Interrupt Disable 21 1 write-only DMA_1 DMA Channel 1 Interrupt Disable 25 1 write-only DMA_2 DMA Channel 2 Interrupt Disable 26 1 write-only DMA_3 DMA Channel 3 Interrupt Disable 27 1 write-only DMA_4 DMA Channel 4 Interrupt Disable 28 1 write-only DMA_5 DMA Channel 5 Interrupt Disable 29 1 write-only DMA_6 DMA Channel 6 Interrupt Disable 30 1 write-only DEVIER Device Global Interrupt Enable Register 0x00000018 32 write-only SUSPES Suspend Interrupt Enable 0 1 write-only MSOFES Micro Start of Frame Interrupt Enable 1 1 write-only SOFES Start of Frame Interrupt Enable 2 1 write-only EORSTES End of Reset Interrupt Enable 3 1 write-only WAKEUPES Wake-Up Interrupt Enable 4 1 write-only EORSMES End of Resume Interrupt Enable 5 1 write-only UPRSMES Upstream Resume Interrupt Enable 6 1 write-only PEP_0 Endpoint 0 Interrupt Enable 12 1 write-only PEP_1 Endpoint 1 Interrupt Enable 13 1 write-only PEP_2 Endpoint 2 Interrupt Enable 14 1 write-only PEP_3 Endpoint 3 Interrupt Enable 15 1 write-only PEP_4 Endpoint 4 Interrupt Enable 16 1 write-only PEP_5 Endpoint 5 Interrupt Enable 17 1 write-only PEP_6 Endpoint 6 Interrupt Enable 18 1 write-only PEP_7 Endpoint 7 Interrupt Enable 19 1 write-only PEP_8 Endpoint 8 Interrupt Enable 20 1 write-only PEP_9 Endpoint 9 Interrupt Enable 21 1 write-only DMA_1 DMA Channel 1 Interrupt Enable 25 1 write-only DMA_2 DMA Channel 2 Interrupt Enable 26 1 write-only DMA_3 DMA Channel 3 Interrupt Enable 27 1 write-only DMA_4 DMA Channel 4 Interrupt Enable 28 1 write-only DMA_5 DMA Channel 5 Interrupt Enable 29 1 write-only DMA_6 DMA Channel 6 Interrupt Enable 30 1 write-only DEVEPT Device Endpoint Register 0x0000001C 32 read-write 0x00000000 EPEN0 Endpoint 0 Enable 0 1 read-write EPEN1 Endpoint 1 Enable 1 1 read-write EPEN2 Endpoint 2 Enable 2 1 read-write EPEN3 Endpoint 3 Enable 3 1 read-write EPEN4 Endpoint 4 Enable 4 1 read-write EPEN5 Endpoint 5 Enable 5 1 read-write EPEN6 Endpoint 6 Enable 6 1 read-write EPEN7 Endpoint 7 Enable 7 1 read-write EPEN8 Endpoint 8 Enable 8 1 read-write EPRST0 Endpoint 0 Reset 16 1 read-write EPRST1 Endpoint 1 Reset 17 1 read-write EPRST2 Endpoint 2 Reset 18 1 read-write EPRST3 Endpoint 3 Reset 19 1 read-write EPRST4 Endpoint 4 Reset 20 1 read-write EPRST5 Endpoint 5 Reset 21 1 read-write EPRST6 Endpoint 6 Reset 22 1 read-write EPRST7 Endpoint 7 Reset 23 1 read-write EPRST8 Endpoint 8 Reset 24 1 read-write DEVFNUM Device Frame Number Register 0x00000020 32 read-only 0x00000000 MFNUM Micro Frame Number 0 3 read-only FNUM Frame Number 3 11 read-only FNCERR Frame Number CRC Error 15 1 read-only 10 4 0-9 DEVEPTCFG[%s] Device Endpoint Configuration Register (n = 0) 0x00000100 32 read-write ALLOC Endpoint Memory Allocate 1 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 AUTOSW Automatic Switch 9 1 read-write EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transaction per microframe for isochronous endpoint 13 2 read-write 0_TRANS reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS default value: one transaction per micro-frame. 0x1 2_TRANS 2 transactions per micro-frame. This endpoint should be configured as double-bank. 0x2 3_TRANS 3 transactions per micro-frame. This endpoint should be configured as triple-bank. 0x3 10 4 0-9 DEVEPTISR[%s] Device Endpoint Status Register (n = 0) 0x00000130 32 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NAKINI NAKed IN Interrupt 4 1 read-only OVERFI Overflow Interrupt 5 1 read-only STALLEDI STALLed Interrupt 6 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 RWALL Read-write Allowed 16 1 read-only CTRLDIR Control Direction 17 1 read-only CFGOK Configuration OK Status 18 1 read-only BYCT Byte Count 20 11 read-only DEVEPTISR0_ISOENPT Device Endpoint Status Register (n = 0) ISOENPT 0x00000130 32 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only UNDERFI Underflow Interrupt 2 1 read-only HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 read-only HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt 4 1 read-only OVERFI Overflow Interrupt 5 1 read-only CRCERRI CRC Error Interrupt 6 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Data2 toggle sequence (for high-bandwidth isochronous endpoint) 0x2 MDATA MData toggle sequence (for high-bandwidth isochronous endpoint) 0x3 ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt 10 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 RWALL Read-write Allowed 16 1 read-only CFGOK Configuration OK Status 18 1 read-only BYCT Byte Count 20 11 read-only 10 4 0-9 DEVEPTICR[%s] Device Endpoint Clear Register (n = 0) 0x00000160 32 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only NAKINIC NAKed IN Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only DEVEPTICR0_ISOENPT Device Endpoint Clear Register (n = 0) ISOENPT 0x00000160 32 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only UNDERFIC Underflow Interrupt Clear 2 1 write-only HBISOINERRIC High bandwidth isochronous IN Underflow Error Interrupt Clear 3 1 write-only HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only CRCERRIC CRC Error Interrupt Clear 6 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only 10 4 0-9 DEVEPTIFR[%s] Device Endpoint Set Register (n = 0) 0x00000190 32 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NAKINIS NAKed IN Interrupt Set 4 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only DEVEPTIFR0_ISOENPT Device Endpoint Set Register (n = 0) ISOENPT 0x00000190 32 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only UNDERFIS Underflow Interrupt Set 2 1 write-only HBISOINERRIS High bandwidth isochronous IN Underflow Error Interrupt Set 3 1 write-only HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set 4 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only CRCERRIS CRC Error Interrupt Set 6 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only 10 4 0-9 DEVEPTIMR[%s] Device Endpoint Mask Register (n = 0) 0x000001C0 32 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only OVERFE Overflow Interrupt 5 1 read-only STALLEDE STALLed Interrupt 6 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only KILLBK Kill IN Bank 13 1 read-only FIFOCON FIFO Control 14 1 read-only EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only NYETDIS NYET Token Disable 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only STALLRQ STALL Request 19 1 read-only DEVEPTIMR0_ISOENPT Device Endpoint Mask Register (n = 0) ISOENPT 0x000001C0 32 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only UNDERFE Underflow Interrupt 2 1 read-only HBISOINERRE High Bandwidth Isochronous IN Error Interrupt 3 1 read-only HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt 4 1 read-only OVERFE Overflow Interrupt 5 1 read-only CRCERRE CRC Error Interrupt 6 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only MDATAE MData Interrupt 8 1 read-only DATAXE DataX Interrupt 9 1 read-only ERRORTRANSE Transaction Error Interrupt 10 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only KILLBK Kill IN Bank 13 1 read-only FIFOCON FIFO Control 14 1 read-only EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only RSTDT Reset Data Toggle 18 1 read-only 10 4 0-9 DEVEPTIER[%s] Device Endpoint Enable Register (n = 0) 0x000001F0 32 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only KILLBKS Kill IN Bank 13 1 write-only FIFOCONS FIFO Control 14 1 write-only EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only STALLRQS STALL Request Enable 19 1 write-only DEVEPTIER0_ISOENPT Device Endpoint Enable Register (n = 0) ISOENPT 0x000001F0 32 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only UNDERFES Underflow Interrupt Enable 2 1 write-only HBISOINERRES High Bandwidth Isochronous IN Error Interrupt Enable 3 1 write-only HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable 4 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only CRCERRES CRC Error Interrupt Enable 6 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only MDATAES MData Interrupt Enable 8 1 write-only DATAXES DataX Interrupt Enable 9 1 write-only ERRORTRANSES Transaction Error Interrupt Enable 10 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only KILLBKS Kill IN Bank 13 1 write-only FIFOCONS FIFO Control 14 1 write-only EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only STALLRQS STALL Request Enable 19 1 write-only 10 4 0-9 DEVEPTIDR[%s] Device Endpoint Disable Register (n = 0) 0x00000220 32 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only STALLRQC STALL Request Clear 19 1 write-only DEVEPTIDR0_ISOENPT Device Endpoint Disable Register (n = 0) ISOENPT 0x00000220 32 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only UNDERFEC Underflow Interrupt Clear 2 1 write-only HBISOINERREC High Bandwidth Isochronous IN Error Interrupt Clear 3 1 write-only HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only CRCERREC CRC Error Interrupt Clear 6 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only MDATEC MData Interrupt Clear 8 1 write-only DATAXEC DataX Interrupt Clear 9 1 write-only ERRORTRANSEC Transaction Error Interrupt Clear 10 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only DEVDMANXTDSC1 Device DMA Channel Next Descriptor Address Register (n = 1) 0x00000310 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMAADDRESS1 Device DMA Channel Address Register (n = 1) 0x00000314 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write DEVDMACONTROL1 Device DMA Channel Control Register (n = 1) 0x00000318 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write DEVDMASTATUS1 Device DMA Channel Status Register (n = 1) 0x0000031C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write DEVDMANXTDSC2 Device DMA Channel Next Descriptor Address Register (n = 2) 0x00000320 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMAADDRESS2 Device DMA Channel Address Register (n = 2) 0x00000324 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write DEVDMACONTROL2 Device DMA Channel Control Register (n = 2) 0x00000328 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write DEVDMASTATUS2 Device DMA Channel Status Register (n = 2) 0x0000032C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write DEVDMANXTDSC3 Device DMA Channel Next Descriptor Address Register (n = 3) 0x00000330 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMAADDRESS3 Device DMA Channel Address Register (n = 3) 0x00000334 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write DEVDMACONTROL3 Device DMA Channel Control Register (n = 3) 0x00000338 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write DEVDMASTATUS3 Device DMA Channel Status Register (n = 3) 0x0000033C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write DEVDMANXTDSC4 Device DMA Channel Next Descriptor Address Register (n = 4) 0x00000340 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMAADDRESS4 Device DMA Channel Address Register (n = 4) 0x00000344 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write DEVDMACONTROL4 Device DMA Channel Control Register (n = 4) 0x00000348 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write DEVDMASTATUS4 Device DMA Channel Status Register (n = 4) 0x0000034C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write DEVDMANXTDSC5 Device DMA Channel Next Descriptor Address Register (n = 5) 0x00000350 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMAADDRESS5 Device DMA Channel Address Register (n = 5) 0x00000354 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write DEVDMACONTROL5 Device DMA Channel Control Register (n = 5) 0x00000358 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write DEVDMASTATUS5 Device DMA Channel Status Register (n = 5) 0x0000035C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write DEVDMANXTDSC6 Device DMA Channel Next Descriptor Address Register (n = 6) 0x00000360 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMAADDRESS6 Device DMA Channel Address Register (n = 6) 0x00000364 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write DEVDMACONTROL6 Device DMA Channel Control Register (n = 6) 0x00000368 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write DEVDMASTATUS6 Device DMA Channel Status Register (n = 6) 0x0000036C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write DEVDMANXTDSC7 Device DMA Channel Next Descriptor Address Register (n = 7) 0x00000370 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMAADDRESS7 Device DMA Channel Address Register (n = 7) 0x00000374 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write DEVDMACONTROL7 Device DMA Channel Control Register (n = 7) 0x00000378 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable Control 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write DEVDMASTATUS7 Device DMA Channel Status Register (n = 7) 0x0000037C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write HSTCTRL Host General Control Register 0x00000400 32 read-write 0x00000000 SOFE Start of Frame Generation Enable 8 1 read-write RESET Send USB Reset 9 1 read-write RESUME Send USB Resume 10 1 read-write SPDCONF Mode Configuration 12 2 read-write NORMAL The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. 0x0 LOW_POWER For a better consumption, if high-speed is not needed. 0x1 HIGH_SPEED Forced high speed. 0x2 FORCED_FS The host remains to full-speed mode whatever the peripheral speed capability. 0x3 HSTISR Host Global Interrupt Status Register 0x00000404 32 read-only 0x00000000 DCONNI Device Connection Interrupt 0 1 read-only DDISCI Device Disconnection Interrupt 1 1 read-only RSTI USB Reset Sent Interrupt 2 1 read-only RSMEDI Downstream Resume Sent Interrupt 3 1 read-only RXRSMI Upstream Resume Received Interrupt 4 1 read-only HSOFI Host Start of Frame Interrupt 5 1 read-only HWUPI Host Wake-Up Interrupt 6 1 read-only PEP_0 Pipe 0 Interrupt 8 1 read-only PEP_1 Pipe 1 Interrupt 9 1 read-only PEP_2 Pipe 2 Interrupt 10 1 read-only PEP_3 Pipe 3 Interrupt 11 1 read-only PEP_4 Pipe 4 Interrupt 12 1 read-only PEP_5 Pipe 5 Interrupt 13 1 read-only PEP_6 Pipe 6 Interrupt 14 1 read-only PEP_7 Pipe 7 Interrupt 15 1 read-only PEP_8 Pipe 8 Interrupt 16 1 read-only PEP_9 Pipe 9 Interrupt 17 1 read-only DMA_1 DMA Channel 1 Interrupt 25 1 read-only DMA_2 DMA Channel 2 Interrupt 26 1 read-only DMA_3 DMA Channel 3 Interrupt 27 1 read-only DMA_4 DMA Channel 4 Interrupt 28 1 read-only DMA_5 DMA Channel 5 Interrupt 29 1 read-only DMA_6 DMA Channel 6 Interrupt 30 1 read-only HSTICR Host Global Interrupt Clear Register 0x00000408 32 write-only DCONNIC Device Connection Interrupt Clear 0 1 write-only DDISCIC Device Disconnection Interrupt Clear 1 1 write-only RSTIC USB Reset Sent Interrupt Clear 2 1 write-only RSMEDIC Downstream Resume Sent Interrupt Clear 3 1 write-only RXRSMIC Upstream Resume Received Interrupt Clear 4 1 write-only HSOFIC Host Start of Frame Interrupt Clear 5 1 write-only HWUPIC Host Wake-Up Interrupt Clear 6 1 write-only HSTIFR Host Global Interrupt Set Register 0x0000040C 32 write-only DCONNIS Device Connection Interrupt Set 0 1 write-only DDISCIS Device Disconnection Interrupt Set 1 1 write-only RSTIS USB Reset Sent Interrupt Set 2 1 write-only RSMEDIS Downstream Resume Sent Interrupt Set 3 1 write-only RXRSMIS Upstream Resume Received Interrupt Set 4 1 write-only HSOFIS Host Start of Frame Interrupt Set 5 1 write-only HWUPIS Host Wake-Up Interrupt Set 6 1 write-only DMA_1 DMA Channel 1 Interrupt Set 25 1 write-only DMA_2 DMA Channel 2 Interrupt Set 26 1 write-only DMA_3 DMA Channel 3 Interrupt Set 27 1 write-only DMA_4 DMA Channel 4 Interrupt Set 28 1 write-only DMA_5 DMA Channel 5 Interrupt Set 29 1 write-only DMA_6 DMA Channel 6 Interrupt Set 30 1 write-only HSTIMR Host Global Interrupt Mask Register 0x00000410 32 read-only 0x00000000 DCONNIE Device Connection Interrupt Enable 0 1 read-only DDISCIE Device Disconnection Interrupt Enable 1 1 read-only RSTIE USB Reset Sent Interrupt Enable 2 1 read-only RSMEDIE Downstream Resume Sent Interrupt Enable 3 1 read-only RXRSMIE Upstream Resume Received Interrupt Enable 4 1 read-only HSOFIE Host Start of Frame Interrupt Enable 5 1 read-only HWUPIE Host Wake-Up Interrupt Enable 6 1 read-only PEP_0 Pipe 0 Interrupt Enable 8 1 read-only PEP_1 Pipe 1 Interrupt Enable 9 1 read-only PEP_2 Pipe 2 Interrupt Enable 10 1 read-only PEP_3 Pipe 3 Interrupt Enable 11 1 read-only PEP_4 Pipe 4 Interrupt Enable 12 1 read-only PEP_5 Pipe 5 Interrupt Enable 13 1 read-only PEP_6 Pipe 6 Interrupt Enable 14 1 read-only PEP_7 Pipe 7 Interrupt Enable 15 1 read-only PEP_8 Pipe 8 Interrupt Enable 16 1 read-only PEP_9 Pipe 9 Interrupt Enable 17 1 read-only DMA_1 DMA Channel 1 Interrupt Enable 25 1 read-only DMA_2 DMA Channel 2 Interrupt Enable 26 1 read-only DMA_3 DMA Channel 3 Interrupt Enable 27 1 read-only DMA_4 DMA Channel 4 Interrupt Enable 28 1 read-only DMA_5 DMA Channel 5 Interrupt Enable 29 1 read-only DMA_6 DMA Channel 6 Interrupt Enable 30 1 read-only HSTIDR Host Global Interrupt Disable Register 0x00000414 32 write-only DCONNIEC Device Connection Interrupt Disable 0 1 write-only DDISCIEC Device Disconnection Interrupt Disable 1 1 write-only RSTIEC USB Reset Sent Interrupt Disable 2 1 write-only RSMEDIEC Downstream Resume Sent Interrupt Disable 3 1 write-only RXRSMIEC Upstream Resume Received Interrupt Disable 4 1 write-only HSOFIEC Host Start of Frame Interrupt Disable 5 1 write-only HWUPIEC Host Wake-Up Interrupt Disable 6 1 write-only PEP_0 Pipe 0 Interrupt Disable 8 1 write-only PEP_1 Pipe 1 Interrupt Disable 9 1 write-only PEP_2 Pipe 2 Interrupt Disable 10 1 write-only PEP_3 Pipe 3 Interrupt Disable 11 1 write-only PEP_4 Pipe 4 Interrupt Disable 12 1 write-only PEP_5 Pipe 5 Interrupt Disable 13 1 write-only PEP_6 Pipe 6 Interrupt Disable 14 1 write-only PEP_7 Pipe 7 Interrupt Disable 15 1 write-only PEP_8 Pipe 8 Interrupt Disable 16 1 write-only PEP_9 Pipe 9 Interrupt Disable 17 1 write-only DMA_1 DMA Channel 1 Interrupt Disable 25 1 write-only DMA_2 DMA Channel 2 Interrupt Disable 26 1 write-only DMA_3 DMA Channel 3 Interrupt Disable 27 1 write-only DMA_4 DMA Channel 4 Interrupt Disable 28 1 write-only DMA_5 DMA Channel 5 Interrupt Disable 29 1 write-only DMA_6 DMA Channel 6 Interrupt Disable 30 1 write-only HSTIER Host Global Interrupt Enable Register 0x00000418 32 write-only DCONNIES Device Connection Interrupt Enable 0 1 write-only DDISCIES Device Disconnection Interrupt Enable 1 1 write-only RSTIES USB Reset Sent Interrupt Enable 2 1 write-only RSMEDIES Downstream Resume Sent Interrupt Enable 3 1 write-only RXRSMIES Upstream Resume Received Interrupt Enable 4 1 write-only HSOFIES Host Start of Frame Interrupt Enable 5 1 write-only HWUPIES Host Wake-Up Interrupt Enable 6 1 write-only PEP_0 Pipe 0 Interrupt Enable 8 1 write-only PEP_1 Pipe 1 Interrupt Enable 9 1 write-only PEP_2 Pipe 2 Interrupt Enable 10 1 write-only PEP_3 Pipe 3 Interrupt Enable 11 1 write-only PEP_4 Pipe 4 Interrupt Enable 12 1 write-only PEP_5 Pipe 5 Interrupt Enable 13 1 write-only PEP_6 Pipe 6 Interrupt Enable 14 1 write-only PEP_7 Pipe 7 Interrupt Enable 15 1 write-only PEP_8 Pipe 8 Interrupt Enable 16 1 write-only PEP_9 Pipe 9 Interrupt Enable 17 1 write-only DMA_1 DMA Channel 1 Interrupt Enable 25 1 write-only DMA_2 DMA Channel 2 Interrupt Enable 26 1 write-only DMA_3 DMA Channel 3 Interrupt Enable 27 1 write-only DMA_4 DMA Channel 4 Interrupt Enable 28 1 write-only DMA_5 DMA Channel 5 Interrupt Enable 29 1 write-only DMA_6 DMA Channel 6 Interrupt Enable 30 1 write-only HSTPIP Host Pipe Register 0x0000041C 32 read-write 0x00000000 PEN0 Pipe 0 Enable 0 1 read-write PEN1 Pipe 1 Enable 1 1 read-write PEN2 Pipe 2 Enable 2 1 read-write PEN3 Pipe 3 Enable 3 1 read-write PEN4 Pipe 4 Enable 4 1 read-write PEN5 Pipe 5 Enable 5 1 read-write PEN6 Pipe 6 Enable 6 1 read-write PEN7 Pipe 7 Enable 7 1 read-write PEN8 Pipe 8 Enable 8 1 read-write PRST0 Pipe 0 Reset 16 1 read-write PRST1 Pipe 1 Reset 17 1 read-write PRST2 Pipe 2 Reset 18 1 read-write PRST3 Pipe 3 Reset 19 1 read-write PRST4 Pipe 4 Reset 20 1 read-write PRST5 Pipe 5 Reset 21 1 read-write PRST6 Pipe 6 Reset 22 1 read-write PRST7 Pipe 7 Reset 23 1 read-write PRST8 Pipe 8 Reset 24 1 read-write HSTFNUM Host Frame Number Register 0x00000420 32 read-write 0x00000000 MFNUM Micro Frame Number 0 3 read-write FNUM Frame Number 3 11 read-write FLENHIGH Frame Length 16 8 read-write HSTADDR1 Host Address 1 Register 0x00000424 32 read-write 0x00000000 HSTADDRP0 USB Host Address 0 7 read-write HSTADDRP1 USB Host Address 8 7 read-write HSTADDRP2 USB Host Address 16 7 read-write HSTADDRP3 USB Host Address 24 7 read-write HSTADDR2 Host Address 2 Register 0x00000428 32 read-write 0x00000000 HSTADDRP4 USB Host Address 0 7 read-write HSTADDRP5 USB Host Address 8 7 read-write HSTADDRP6 USB Host Address 16 7 read-write HSTADDRP7 USB Host Address 24 7 read-write HSTADDR3 Host Address 3 Register 0x0000042C 32 read-write 0x00000000 HSTADDRP8 USB Host Address 0 7 read-write HSTADDRP9 USB Host Address 8 7 read-write 10 4 0-9 HSTPIPCFG[%s] Host Pipe Configuration Register (n = 0) 0x00000500 32 read-write ALLOC Pipe Memory Allocate 1 1 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 AUTOSW Automatic Switch 10 1 read-write PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 PEPNUM Pipe Endpoint Number 16 4 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write HSTPIPCFG0_HSBOHSCP Host Pipe Configuration Register (n = 0) HSBOHSCP 0x00000500 32 read-write ALLOC Pipe Memory Allocate 1 1 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 AUTOSW Automatic Switch 10 1 read-write PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 BLK Bulk 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PINGEN Ping Enable 20 1 read-write BINTERVAL Binterval Parameter for the Bulk-Out/Ping Transaction 24 8 read-write 10 4 0-9 HSTPIPISR[%s] Host Pipe Status Register (n = 0) 0x00000530 32 read-only RXINI Received IN Data Interrupt 0 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only PERRI Pipe Error Interrupt 3 1 read-only NAKEDI NAKed Interrupt 4 1 read-only OVERFI Overflow Interrupt 5 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 RWALL Read-write Allowed 16 1 read-only CFGOK Configuration OK Status 18 1 read-only PBYCT Pipe Byte Count 20 11 read-only HSTPIPISR0_INTPIPES Host Pipe Status Register (n = 0) INTPIPES 0x00000530 32 read-only RXINI Received IN Data Interrupt 0 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only UNDERFI Underflow Interrupt 2 1 read-only PERRI Pipe Error Interrupt 3 1 read-only NAKEDI NAKed Interrupt 4 1 read-only OVERFI Overflow Interrupt 5 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 RWALL Read-write Allowed 16 1 read-only CFGOK Configuration OK Status 18 1 read-only PBYCT Pipe Byte Count 20 11 read-only HSTPIPISR0_ISOPIPES Host Pipe Status Register (n = 0) ISOPIPES 0x00000530 32 read-only RXINI Received IN Data Interrupt 0 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only UNDERFI Underflow Interrupt 2 1 read-only PERRI Pipe Error Interrupt 3 1 read-only NAKEDI NAKed Interrupt 4 1 read-only OVERFI Overflow Interrupt 5 1 read-only CRCERRI CRC Error Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 RWALL Read-write Allowed 16 1 read-only CFGOK Configuration OK Status 18 1 read-only PBYCT Pipe Byte Count 20 11 read-only 10 4 0-9 HSTPIPICR[%s] Host Pipe Clear Register (n = 0) 0x00000560 32 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only HSTPIPICR0_INTPIPES Host Pipe Clear Register (n = 0) INTPIPES 0x00000560 32 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only UNDERFIC Underflow Interrupt Clear 2 1 write-only NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only HSTPIPICR0_ISOPIPES Host Pipe Clear Register (n = 0) ISOPIPES 0x00000560 32 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only UNDERFIC Underflow Interrupt Clear 2 1 write-only NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only CRCERRIC CRC Error Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only 10 4 0-9 HSTPIPIFR[%s] Host Pipe Set Register (n = 0) 0x00000590 32 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only NAKEDIS NAKed Interrupt Set 4 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only HSTPIPIFR0_INTPIPES Host Pipe Set Register (n = 0) INTPIPES 0x00000590 32 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only UNDERFIS Underflow Interrupt Set 2 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only NAKEDIS NAKed Interrupt Set 4 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only HSTPIPIFR0_ISOPIPES Host Pipe Set Register (n = 0) ISOPIPES 0x00000590 32 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only UNDERFIS Underflow Interrupt Set 2 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only NAKEDIS NAKed Interrupt Set 4 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only CRCERRIS CRC Error Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only 10 4 0-9 HSTPIPIMR[%s] Host Pipe Mask Register (n = 0) 0x000005C0 32 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only FIFOCON FIFO Control 14 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only HSTPIPIMR0_INTPIPES Host Pipe Mask Register (n = 0) INTPIPES 0x000005C0 32 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only UNDERFIE Underflow Interrupt Enable 2 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only FIFOCON FIFO Control 14 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only HSTPIPIMR0_ISOPIPES Host Pipe Mask Register (n = 0) ISOPIPES 0x000005C0 32 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only UNDERFIE Underflow Interrupt Enable 2 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only CRCERRE CRC Error Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only FIFOCON FIFO Control 14 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only 10 4 0-9 HSTPIPIER[%s] Host Pipe Enable Register (n = 0) 0x000005F0 32 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only NAKEDES NAKed Interrupt Enable 4 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only HSTPIPIER0_INTPIPES Host Pipe Enable Register (n = 0) INTPIPES 0x000005F0 32 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only UNDERFIES Underflow Interrupt Enable 2 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only NAKEDES NAKed Interrupt Enable 4 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only HSTPIPIER0_ISOPIPES Host Pipe Enable Register (n = 0) ISOPIPES 0x000005F0 32 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only UNDERFIES Underflow Interrupt Enable 2 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only NAKEDES NAKed Interrupt Enable 4 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only CRCERRES CRC Error Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only 10 4 0-9 HSTPIPIDR[%s] Host Pipe Disable Register (n = 0) 0x00000620 32 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only FIFOCONC FIFO Control Disable 14 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only HSTPIPIDR0_INTPIPES Host Pipe Disable Register (n = 0) INTPIPES 0x00000620 32 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only UNDERFIEC Underflow Interrupt Disable 2 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only FIFOCONC FIFO Control Disable 14 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only HSTPIPIDR0_ISOPIPES Host Pipe Disable Register (n = 0) ISOPIPES 0x00000620 32 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only UNDERFIEC Underflow Interrupt Disable 2 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only CRCERREC CRC Error Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only FIFOCONC FIFO Control Disable 14 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only 10 4 0-9 HSTPIPINRQ[%s] Host Pipe IN Request Register (n = 0) 0x00000650 32 read-write INRQ IN Request Number before Freeze 0 8 read-write INMODE IN Request Mode 8 1 read-write 10 4 0-9 HSTPIPERR[%s] Host Pipe Error Register (n = 0) 0x00000680 32 read-write DATATGL Data Toggle Error 0 1 read-write DATAPID Data PID Error 1 1 read-write PID PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write CRC16 CRC16 Error 4 1 read-write COUNTER Error Counter 5 2 read-write HSTDMANXTDSC1 Host DMA Channel Next Descriptor Address Register (n = 1) 0x00000710 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMAADDRESS1 Host DMA Channel Address Register (n = 1) 0x00000714 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write HSTDMACONTROL1 Host DMA Channel Control Register (n = 1) 0x00000718 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write HSTDMASTATUS1 Host DMA Channel Status Register (n = 1) 0x0000071C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write HSTDMANXTDSC2 Host DMA Channel Next Descriptor Address Register (n = 2) 0x00000720 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMAADDRESS2 Host DMA Channel Address Register (n = 2) 0x00000724 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write HSTDMACONTROL2 Host DMA Channel Control Register (n = 2) 0x00000728 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write HSTDMASTATUS2 Host DMA Channel Status Register (n = 2) 0x0000072C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write HSTDMANXTDSC3 Host DMA Channel Next Descriptor Address Register (n = 3) 0x00000730 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMAADDRESS3 Host DMA Channel Address Register (n = 3) 0x00000734 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write HSTDMACONTROL3 Host DMA Channel Control Register (n = 3) 0x00000738 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write HSTDMASTATUS3 Host DMA Channel Status Register (n = 3) 0x0000073C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write HSTDMANXTDSC4 Host DMA Channel Next Descriptor Address Register (n = 4) 0x00000740 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMAADDRESS4 Host DMA Channel Address Register (n = 4) 0x00000744 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write HSTDMACONTROL4 Host DMA Channel Control Register (n = 4) 0x00000748 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write HSTDMASTATUS4 Host DMA Channel Status Register (n = 4) 0x0000074C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write HSTDMANXTDSC5 Host DMA Channel Next Descriptor Address Register (n = 5) 0x00000750 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMAADDRESS5 Host DMA Channel Address Register (n = 5) 0x00000754 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write HSTDMACONTROL5 Host DMA Channel Control Register (n = 5) 0x00000758 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write HSTDMASTATUS5 Host DMA Channel Status Register (n = 5) 0x0000075C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write HSTDMANXTDSC6 Host DMA Channel Next Descriptor Address Register (n = 6) 0x00000760 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMAADDRESS6 Host DMA Channel Address Register (n = 6) 0x00000764 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write HSTDMACONTROL6 Host DMA Channel Control Register (n = 6) 0x00000768 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write HSTDMASTATUS6 Host DMA Channel Status Register (n = 6) 0x0000076C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write HSTDMANXTDSC7 Host DMA Channel Next Descriptor Address Register (n = 7) 0x00000770 32 read-write 0x00000000 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMAADDRESS7 Host DMA Channel Address Register (n = 7) 0x00000774 32 read-write 0x00000000 BUFF_ADD Buffer Address 0 32 read-write HSTDMACONTROL7 Host DMA Channel Control Register (n = 7) 0x00000778 32 read-write 0x00000000 CHANN_ENB Channel Enable Command 0 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write BURST_LCK Burst Lock Enable 7 1 read-write BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write HSTDMASTATUS7 Host DMA Channel Status Register (n = 7) 0x0000077C 32 read-write 0x00000000 CHANN_ENB Channel Enable Status 0 1 read-write CHANN_ACT Channel Active Status 1 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write BUFF_COUNT Buffer Byte Count 16 16 read-write CTRL General Control Register 0x00000800 32 read-write 0x03004000 IDTE ID Transition Interrupt Enable 0 1 read-write VBUSTE VBus Transition Interrupt Enable 1 1 read-write SRPE SRP Interrupt Enable 2 1 read-write VBERRE VBus Error Interrupt Enable 3 1 read-write BCERRE B-Connection Error Interrupt Enable 4 1 read-write ROLEEXE Role Exchange Interrupt Enable 5 1 read-write HNPERRE HNP Error Interrupt Enable 6 1 read-write STOE Suspend Time-Out Interrupt Enable 7 1 read-write VBUSHWC VBus Hardware Control 8 1 read-write SRPSEL SRP Selection 9 1 read-write SRPREQ SRP Request 10 1 read-write HNPREQ HNP Request 11 1 read-write OTGPADE OTG Pad Enable 12 1 read-write VBUSPO VBus Polarity Off 13 1 read-write FRZCLK Freeze USB Clock 14 1 read-write USBE UOTGHS Enable 15 1 read-write TIMVALUE Timer Value 16 2 read-write TIMPAGE Timer Page 20 2 read-write UNLOCK Timer Access Unlock 22 1 read-write UIDE UOTGID Pin Enable 24 1 read-write UIMOD The USB mode (device/host) is selected from the UIMOD bit. 0 UOTGID The USB mode (device/host) is selected from the UOTGID input pin. 1 UIMOD UOTGHS Mode 25 1 read-write HOST The module is in USB host mode. 0 DEVICE The module is in USB device mode. 1 SR General Status Register 0x00000804 32 read-only 0x00000400 IDTI ID Transition Interrupt 0 1 read-only VBUSTI VBus Transition Interrupt 1 1 read-only SRPI SRP Interrupt 2 1 read-only VBERRI VBus Error Interrupt 3 1 read-only BCERRI B-Connection Error Interrupt 4 1 read-only ROLEEXI Role Exchange Interrupt 5 1 read-only HNPERRI HNP Error Interrupt 6 1 read-only STOI Suspend Time-Out Interrupt 7 1 read-only VBUSRQ VBus Request 9 1 read-only ID UOTGID Pin State 10 1 read-only VBUS VBus Level 11 1 read-only SPEED Speed Status 12 2 read-only FULL_SPEED Full-Speed mode 0x0 HIGH_SPEED High-Speed mode 0x1 LOW_SPEED Low-Speed mode 0x2 CLKUSABLE UTMI Clock Usable 14 1 read-only SCR General Status Clear Register 0x00000808 32 write-only IDTIC ID Transition Interrupt Clear 0 1 write-only VBUSTIC VBus Transition Interrupt Clear 1 1 write-only SRPIC SRP Interrupt Clear 2 1 write-only VBERRIC VBus Error Interrupt Clear 3 1 write-only BCERRIC B-Connection Error Interrupt Clear 4 1 write-only ROLEEXIC Role Exchange Interrupt Clear 5 1 write-only HNPERRIC HNP Error Interrupt Clear 6 1 write-only STOIC Suspend Time-Out Interrupt Clear 7 1 write-only VBUSRQC VBus Request Clear 9 1 write-only SFR General Status Set Register 0x0000080C 32 write-only IDTIS ID Transition Interrupt Set 0 1 write-only VBUSTIS VBus Transition Interrupt Set 1 1 write-only SRPIS SRP Interrupt Set 2 1 write-only VBERRIS VBus Error Interrupt Set 3 1 write-only BCERRIS B-Connection Error Interrupt Set 4 1 write-only ROLEEXIS Role Exchange Interrupt Set 5 1 write-only HNPERRIS HNP Error Interrupt Set 6 1 write-only STOIS Suspend Time-Out Interrupt Set 7 1 write-only VBUSRQS VBus Request Set 9 1 write-only FSM General Finite State Machine Register 0x0000082C 32 read-only 0x00000009 DRDSTATE Dual Role Device State 0 4 read-only A_IDLESTATE This is the start state for A-devices (when the ID pin is 0) 0x0 A_WAIT_VRISE In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). 0x1 A_WAIT_BCON In this state, the A-device waits for the B-device to signal a connection. 0x2 A_HOST In this state, the A-device that operates in Host mode is operational. 0x3 A_SUSPEND The A-device operating as a host is in the suspend mode. 0x4 A_PERIPHERAL The A-device operates as a peripheral. 0x5 A_WAIT_VFALL In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). 0x6 A_VBUS_ERR In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. 0x7 A_WAIT_DISCHARGE In this state, the A-device waits for the data USB line to discharge (100 us). 0x8 B_IDLE This is the start state for B-device (when the ID pin is 1). 0x9 B_PERIPHERAL In this state, the B-device acts as the peripheral. 0xA B_WAIT_BEGIN_HNP In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. 0xB B_WAIT_DISCHARGE In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host. 0xC B_WAIT_ACON In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. 0xD B_HOST In this state, the B-device acts as the Host. 0xE B_SRP_INIT In this state, the B-device attempts to start a session using the SRP protocol. 0xF EMAC 6119I Ethernet MAC 10/100 EMAC_ 0x400B0000 0 0x4000 registers EMAC 42 NCR Network Control Register 0x00000000 32 read-write 0x00000000 LB LoopBack 0 1 read-write LLB Loopback local 1 1 read-write RE Receive enable 2 1 read-write TE Transmit enable 3 1 read-write MPE Management port enable 4 1 read-write CLRSTAT Clear statistics registers 5 1 read-write INCSTAT Increment statistics registers 6 1 read-write WESTAT Write enable for statistics registers 7 1 read-write BP Back pressure 8 1 read-write TSTART Start transmission 9 1 read-write THALT Transmit halt 10 1 read-write NCFGR Network Configuration Register 0x00000004 32 read-write 0x00000800 SPD Speed 0 1 read-write FD Full Duplex 1 1 read-write JFRAME Jumbo Frames 3 1 read-write CAF Copy All Frames 4 1 read-write NBC No Broadcast 5 1 read-write MTI Multicast Hash Enable 6 1 read-write UNI Unicast Hash Enable 7 1 read-write BIG Receive 1536 bytes frames 8 1 read-write CLK MDC clock divider 10 2 read-write MCK_8 MCK divided by 8 (MCK up to 20 MHz). 0x0 MCK_16 MCK divided by 16 (MCK up to 40 MHz). 0x1 MCK_32 MCK divided by 32 (MCK up to 80 MHz). 0x2 MCK_64 MCK divided by 64 (MCK up to 160 MHz). 0x3 RTY Retry test 12 1 read-write PAE Pause Enable 13 1 read-write RBOF Receive Buffer Offset 14 2 read-write OFFSET_0 No offset from start of receive buffer. 0x0 OFFSET_1 One-byte offset from start of receive buffer. 0x1 OFFSET_2 Two-byte offset from start of receive buffer. 0x2 OFFSET_3 Three-byte offset from start of receive buffer. 0x3 RLCE Receive Length field Checking Enable 16 1 read-write DRFCS Discard Receive FCS 17 1 read-write EFRHD 18 1 read-write IRXFCS Ignore RX FCS 19 1 read-write NSR Network Status Register 0x00000008 32 read-only MDIO 1 1 read-only IDLE 2 1 read-only TSR Transmit Status Register 0x00000014 32 read-write 0x00000000 UBR Used Bit Read 0 1 read-write COL Collision Occurred 1 1 read-write RLES Retry Limit exceeded 2 1 read-write TGO Transmit Go 3 1 read-write BEX Buffers exhausted mid frame 4 1 read-write COMP Transmit Complete 5 1 read-write UND Transmit Underrun 6 1 read-write RBQP Receive Buffer Queue Pointer Register 0x00000018 32 read-write 0x00000000 ADDR Receive buffer queue pointer address 2 30 read-write TBQP Transmit Buffer Queue Pointer Register 0x0000001C 32 read-write 0x00000000 ADDR Transmit buffer queue pointer address 2 30 read-write RSR Receive Status Register 0x00000020 32 read-write 0x00000000 BNA Buffer Not Available 0 1 read-write REC Frame Received 1 1 read-write OVR Receive Overrun 2 1 read-write ISR Interrupt Status Register 0x00000024 32 read-write 0x00000000 MFD Management Frame Done 0 1 read-write RCOMP Receive Complete 1 1 read-write RXUBR Receive Used Bit Read 2 1 read-write TXUBR Transmit Used Bit Read 3 1 read-write TUND Ethernet Transmit Buffer Underrun 4 1 read-write RLEX Retry Limit Exceeded 5 1 read-write TXERR Transmit Error 6 1 read-write TCOMP Transmit Complete 7 1 read-write ROVR Receive Overrun 10 1 read-write HRESP Hresp not OK 11 1 read-write PFRE Pause Frame Received 12 1 read-write PTZ Pause Time Zero 13 1 read-write IER Interrupt Enable Register 0x00000028 32 write-only MFD Management Frame sent 0 1 write-only RCOMP Receive Complete 1 1 write-only RXUBR Receive Used Bit Read 2 1 write-only TXUBR Transmit Used Bit Read 3 1 write-only TUND Ethernet Transmit Buffer Underrun 4 1 write-only RLE Retry Limit Exceeded 5 1 write-only TXERR 6 1 write-only TCOMP Transmit Complete 7 1 write-only ROVR Receive Overrun 10 1 write-only HRESP Hresp not OK 11 1 write-only PFR Pause Frame Received 12 1 write-only PTZ Pause Time Zero 13 1 write-only IDR Interrupt Disable Register 0x0000002C 32 write-only MFD Management Frame sent 0 1 write-only RCOMP Receive Complete 1 1 write-only RXUBR Receive Used Bit Read 2 1 write-only TXUBR Transmit Used Bit Read 3 1 write-only TUND Ethernet Transmit Buffer Underrun 4 1 write-only RLE Retry Limit Exceeded 5 1 write-only TXERR 6 1 write-only TCOMP Transmit Complete 7 1 write-only ROVR Receive Overrun 10 1 write-only HRESP Hresp not OK 11 1 write-only PFR Pause Frame Received 12 1 write-only PTZ Pause Time Zero 13 1 write-only IMR Interrupt Mask Register 0x00000030 32 read-only 0x00003FFF MFD Management Frame sent 0 1 read-only RCOMP Receive Complete 1 1 read-only RXUBR Receive Used Bit Read 2 1 read-only TXUBR Transmit Used Bit Read 3 1 read-only TUND Ethernet Transmit Buffer Underrun 4 1 read-only RLE Retry Limit Exceeded 5 1 read-only TXERR 6 1 read-only TCOMP Transmit Complete 7 1 read-only ROVR Receive Overrun 10 1 read-only HRESP Hresp not OK 11 1 read-only PFR Pause Frame Received 12 1 read-only PTZ Pause Time Zero 13 1 read-only MAN Phy Maintenance Register 0x00000034 32 read-write 0x00000000 DATA 0 16 read-write CODE 16 2 read-write REGA Register Address 18 5 read-write PHYA PHY Address 23 5 read-write RW Read-write 28 2 read-write SOF Start of frame 30 2 read-write PTR Pause Time Register 0x00000038 32 read-write 0x00000000 PTIME Pause Time 0 16 read-write PFR Pause Frames Received Register 0x0000003C 32 read-write 0x00000000 FROK Pause Frames received OK 0 16 read-write FTO Frames Transmitted Ok Register 0x00000040 32 read-write 0x00000000 FTOK Frames Transmitted OK 0 24 read-write SCF Single Collision Frames Register 0x00000044 32 read-write 0x00000000 SCF Single Collision Frames 0 16 read-write MCF Multiple Collision Frames Register 0x00000048 32 read-write 0x00000000 MCF Multicollision Frames 0 16 read-write FRO Frames Received Ok Register 0x0000004C 32 read-write 0x00000000 FROK Frames Received OK 0 24 read-write FCSE Frame Check Sequence Errors Register 0x00000050 32 read-write 0x00000000 FCSE Frame Check Sequence Errors 0 8 read-write ALE Alignment Errors Register 0x00000054 32 read-write 0x00000000 ALE Alignment Errors 0 8 read-write DTF Deferred Transmission Frames Register 0x00000058 32 read-write 0x00000000 DTF Deferred Transmission Frames 0 16 read-write LCOL Late Collisions Register 0x0000005C 32 read-write 0x00000000 LCOL Late Collisions 0 8 read-write ECOL Excessive Collisions Register 0x00000060 32 read-write 0x00000000 EXCOL Excessive Collisions 0 8 read-write TUND Transmit Underrun Errors Register 0x00000064 32 read-write 0x00000000 TUND Transmit Underruns 0 8 read-write CSE Carrier Sense Errors Register 0x00000068 32 read-write 0x00000000 CSE Carrier Sense Errors 0 8 read-write RRE Receive Resource Errors Register 0x0000006C 32 read-write 0x00000000 RRE Receive Resource Errors 0 16 read-write ROV Receive Overrun Errors Register 0x00000070 32 read-write 0x00000000 ROVR Receive Overrun 0 8 read-write RSE Receive Symbol Errors Register 0x00000074 32 read-write 0x00000000 RSE Receive Symbol Errors 0 8 read-write ELE Excessive Length Errors Register 0x00000078 32 read-write 0x00000000 EXL Excessive Length Errors 0 8 read-write RJA Receive Jabbers Register 0x0000007C 32 read-write 0x00000000 RJB Receive Jabbers 0 8 read-write USF Undersize Frames Register 0x00000080 32 read-write 0x00000000 USF Undersize frames 0 8 read-write STE SQE Test Errors Register 0x00000084 32 read-write 0x00000000 SQER SQE test errors 0 8 read-write RLE Received Length Field Mismatch Register 0x00000088 32 read-write 0x00000000 RLFM Receive Length Field Mismatch 0 8 read-write HRB Hash Register Bottom [31:0] Register 0x00000090 32 read-write 0x00000000 ADDR 0 32 read-write HRT Hash Register Top [63:32] Register 0x00000094 32 read-write 0x00000000 ADDR 0 32 read-write SA1B Specific Address 1 Bottom Register 0x00000098 32 read-write 0x00000000 ADDR 0 32 read-write SA1T Specific Address 1 Top Register 0x0000009C 32 read-write 0x00000000 ADDR 0 16 read-write SA2B Specific Address 2 Bottom Register 0x000000A0 32 read-write 0x00000000 ADDR 0 32 read-write SA2T Specific Address 2 Top Register 0x000000A4 32 read-write 0x00000000 ADDR 0 16 read-write SA3B Specific Address 3 Bottom Register 0x000000A8 32 read-write 0x00000000 ADDR 0 32 read-write SA3T Specific Address 3 Top Register 0x000000AC 32 read-write 0x00000000 ADDR 0 16 read-write SA4B Specific Address 4 Bottom Register 0x000000B0 32 read-write 0x00000000 ADDR 0 32 read-write SA4T Specific Address 4 Top Register 0x000000B4 32 read-write 0x00000000 ADDR 0 16 read-write TID Type ID Checking Register 0x000000B8 32 read-write 0x00000000 TID Type ID checking 0 16 read-write USRIO User Input/Output Register 0x000000C0 32 read-write 0x00000000 RMII Reduce MII 0 1 read-write CLKEN Clock Enable 1 1 read-write CAN0 6019N Controller Area Network 0 CAN CAN0_ 0x400B4000 0 0x4000 registers CAN0 43 MR Mode Register 0x00000000 32 read-write 0x00000000 CANEN CAN Controller Enable 0 1 read-write LPM Disable/Enable Low Power Mode 1 1 read-write ABM Disable/Enable Autobaud/Listen mode 2 1 read-write OVL Disable/Enable Overload Frame 3 1 read-write TEOF Timestamp messages at each end of Frame 4 1 read-write TTM Disable/Enable Time Triggered Mode 5 1 read-write TIMFRZ Enable Timer Freeze 6 1 read-write DRPT Disable Repeat 7 1 read-write RXSYNC Reception Synchronization Stage (not readable) 24 3 read-write DOUBLE_PP Rx Signal with Double Synchro Stages (2 Positive Edges) 0x0 DOUBLE_PN Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge) 0x1 SINGLE_P Rx Signal with Single Synchro Stage (Positive Edge) 0x2 NONE Rx Signal with No Synchro Stage 0x3 IER Interrupt Enable Register 0x00000004 32 write-only MB0 Mailbox 0 Interrupt Enable 0 1 write-only MB1 Mailbox 1 Interrupt Enable 1 1 write-only MB2 Mailbox 2 Interrupt Enable 2 1 write-only MB3 Mailbox 3 Interrupt Enable 3 1 write-only MB4 Mailbox 4 Interrupt Enable 4 1 write-only MB5 Mailbox 5 Interrupt Enable 5 1 write-only MB6 Mailbox 6 Interrupt Enable 6 1 write-only MB7 Mailbox 7 Interrupt Enable 7 1 write-only ERRA Error Active Mode Interrupt Enable 16 1 write-only WARN Warning Limit Interrupt Enable 17 1 write-only ERRP Error Passive Mode Interrupt Enable 18 1 write-only BOFF Bus Off Mode Interrupt Enable 19 1 write-only SLEEP Sleep Interrupt Enable 20 1 write-only WAKEUP Wakeup Interrupt Enable 21 1 write-only TOVF Timer Overflow Interrupt Enable 22 1 write-only TSTP TimeStamp Interrupt Enable 23 1 write-only CERR CRC Error Interrupt Enable 24 1 write-only SERR Stuffing Error Interrupt Enable 25 1 write-only AERR Acknowledgment Error Interrupt Enable 26 1 write-only FERR Form Error Interrupt Enable 27 1 write-only BERR Bit Error Interrupt Enable 28 1 write-only IDR Interrupt Disable Register 0x00000008 32 write-only MB0 Mailbox 0 Interrupt Disable 0 1 write-only MB1 Mailbox 1 Interrupt Disable 1 1 write-only MB2 Mailbox 2 Interrupt Disable 2 1 write-only MB3 Mailbox 3 Interrupt Disable 3 1 write-only MB4 Mailbox 4 Interrupt Disable 4 1 write-only MB5 Mailbox 5 Interrupt Disable 5 1 write-only MB6 Mailbox 6 Interrupt Disable 6 1 write-only MB7 Mailbox 7 Interrupt Disable 7 1 write-only ERRA Error Active Mode Interrupt Disable 16 1 write-only WARN Warning Limit Interrupt Disable 17 1 write-only ERRP Error Passive Mode Interrupt Disable 18 1 write-only BOFF Bus Off Mode Interrupt Disable 19 1 write-only SLEEP Sleep Interrupt Disable 20 1 write-only WAKEUP Wakeup Interrupt Disable 21 1 write-only TOVF Timer Overflow Interrupt 22 1 write-only TSTP TimeStamp Interrupt Disable 23 1 write-only CERR CRC Error Interrupt Disable 24 1 write-only SERR Stuffing Error Interrupt Disable 25 1 write-only AERR Acknowledgment Error Interrupt Disable 26 1 write-only FERR Form Error Interrupt Disable 27 1 write-only BERR Bit Error Interrupt Disable 28 1 write-only IMR Interrupt Mask Register 0x0000000C 32 read-only 0x00000000 MB0 Mailbox 0 Interrupt Mask 0 1 read-only MB1 Mailbox 1 Interrupt Mask 1 1 read-only MB2 Mailbox 2 Interrupt Mask 2 1 read-only MB3 Mailbox 3 Interrupt Mask 3 1 read-only MB4 Mailbox 4 Interrupt Mask 4 1 read-only MB5 Mailbox 5 Interrupt Mask 5 1 read-only MB6 Mailbox 6 Interrupt Mask 6 1 read-only MB7 Mailbox 7 Interrupt Mask 7 1 read-only ERRA Error Active Mode Interrupt Mask 16 1 read-only WARN Warning Limit Interrupt Mask 17 1 read-only ERRP Error Passive Mode Interrupt Mask 18 1 read-only BOFF Bus Off Mode Interrupt Mask 19 1 read-only SLEEP Sleep Interrupt Mask 20 1 read-only WAKEUP Wakeup Interrupt Mask 21 1 read-only TOVF Timer Overflow Interrupt Mask 22 1 read-only TSTP Timestamp Interrupt Mask 23 1 read-only CERR CRC Error Interrupt Mask 24 1 read-only SERR Stuffing Error Interrupt Mask 25 1 read-only AERR Acknowledgment Error Interrupt Mask 26 1 read-only FERR Form Error Interrupt Mask 27 1 read-only BERR Bit Error Interrupt Mask 28 1 read-only SR Status Register 0x00000010 32 read-only 0x00000000 MB0 Mailbox 0 Event 0 1 read-only MB1 Mailbox 1 Event 1 1 read-only MB2 Mailbox 2 Event 2 1 read-only MB3 Mailbox 3 Event 3 1 read-only MB4 Mailbox 4 Event 4 1 read-only MB5 Mailbox 5 Event 5 1 read-only MB6 Mailbox 6 Event 6 1 read-only MB7 Mailbox 7 Event 7 1 read-only ERRA Error Active Mode 16 1 read-only WARN Warning Limit 17 1 read-only ERRP Error Passive Mode 18 1 read-only BOFF Bus Off Mode 19 1 read-only SLEEP CAN controller in Low power Mode 20 1 read-only WAKEUP CAN controller is not in Low power Mode 21 1 read-only TOVF Timer Overflow 22 1 read-only TSTP 23 1 read-only CERR Mailbox CRC Error 24 1 read-only SERR Mailbox Stuffing Error 25 1 read-only AERR Acknowledgment Error 26 1 read-only FERR Form Error 27 1 read-only BERR Bit Error 28 1 read-only RBSY Receiver busy 29 1 read-only TBSY Transmitter busy 30 1 read-only OVLSY Overload busy 31 1 read-only BR Baudrate Register 0x00000014 32 read-write 0x00000000 PHASE2 Phase 2 segment 0 3 read-write PHASE1 Phase 1 segment 4 3 read-write PROPAG Programming time segment 8 3 read-write SJW Re-synchronization jump width 12 2 read-write BRP Baudrate Prescaler. 16 7 read-write SMP Sampling Mode 24 1 read-write ONCE The incoming bit stream is sampled once at sample point. 0 THREE The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. 1 TIM Timer Register 0x00000018 32 read-only 0x00000000 TIMER Timer 0 16 read-only TIMESTP Timestamp Register 0x0000001C 32 read-only 0x00000000 MTIMESTAMP Timestamp 0 16 read-only ECR Error Counter Register 0x00000020 32 read-only 0x00000000 REC Receive Error Counter 0 8 read-only TEC Transmit Error Counter 16 8 read-only TCR Transfer Command Register 0x00000024 32 write-only MB0 Transfer Request for Mailbox 0 0 1 write-only MB1 Transfer Request for Mailbox 1 1 1 write-only MB2 Transfer Request for Mailbox 2 2 1 write-only MB3 Transfer Request for Mailbox 3 3 1 write-only MB4 Transfer Request for Mailbox 4 4 1 write-only MB5 Transfer Request for Mailbox 5 5 1 write-only MB6 Transfer Request for Mailbox 6 6 1 write-only MB7 Transfer Request for Mailbox 7 7 1 write-only TIMRST Timer Reset 31 1 write-only ACR Abort Command Register 0x00000028 32 write-only MB0 Abort Request for Mailbox 0 0 1 write-only MB1 Abort Request for Mailbox 1 1 1 write-only MB2 Abort Request for Mailbox 2 2 1 write-only MB3 Abort Request for Mailbox 3 3 1 write-only MB4 Abort Request for Mailbox 4 4 1 write-only MB5 Abort Request for Mailbox 5 5 1 write-only MB6 Abort Request for Mailbox 6 6 1 write-only MB7 Abort Request for Mailbox 7 7 1 write-only WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protection Enable 0 1 read-write WPKEY SPI Write Protection Key Password 8 24 read-write WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 8 read-only MMR0 Mailbox Mode Register (MB = 0) 0x00000200 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM0 Mailbox Acceptance Mask Register (MB = 0) 0x00000204 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID0 Mailbox ID Register (MB = 0) 0x00000208 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID0 Mailbox Family ID Register (MB = 0) 0x0000020C 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR0 Mailbox Status Register (MB = 0) 0x00000210 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL0 Mailbox Data Low Register (MB = 0) 0x00000214 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH0 Mailbox Data High Register (MB = 0) 0x00000218 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR0 Mailbox Control Register (MB = 0) 0x0000021C 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR1 Mailbox Mode Register (MB = 1) 0x00000220 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM1 Mailbox Acceptance Mask Register (MB = 1) 0x00000224 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID1 Mailbox ID Register (MB = 1) 0x00000228 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID1 Mailbox Family ID Register (MB = 1) 0x0000022C 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR1 Mailbox Status Register (MB = 1) 0x00000230 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL1 Mailbox Data Low Register (MB = 1) 0x00000234 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH1 Mailbox Data High Register (MB = 1) 0x00000238 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR1 Mailbox Control Register (MB = 1) 0x0000023C 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR2 Mailbox Mode Register (MB = 2) 0x00000240 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM2 Mailbox Acceptance Mask Register (MB = 2) 0x00000244 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID2 Mailbox ID Register (MB = 2) 0x00000248 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID2 Mailbox Family ID Register (MB = 2) 0x0000024C 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR2 Mailbox Status Register (MB = 2) 0x00000250 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL2 Mailbox Data Low Register (MB = 2) 0x00000254 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH2 Mailbox Data High Register (MB = 2) 0x00000258 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR2 Mailbox Control Register (MB = 2) 0x0000025C 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR3 Mailbox Mode Register (MB = 3) 0x00000260 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM3 Mailbox Acceptance Mask Register (MB = 3) 0x00000264 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID3 Mailbox ID Register (MB = 3) 0x00000268 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID3 Mailbox Family ID Register (MB = 3) 0x0000026C 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR3 Mailbox Status Register (MB = 3) 0x00000270 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL3 Mailbox Data Low Register (MB = 3) 0x00000274 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH3 Mailbox Data High Register (MB = 3) 0x00000278 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR3 Mailbox Control Register (MB = 3) 0x0000027C 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR4 Mailbox Mode Register (MB = 4) 0x00000280 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM4 Mailbox Acceptance Mask Register (MB = 4) 0x00000284 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID4 Mailbox ID Register (MB = 4) 0x00000288 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID4 Mailbox Family ID Register (MB = 4) 0x0000028C 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR4 Mailbox Status Register (MB = 4) 0x00000290 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL4 Mailbox Data Low Register (MB = 4) 0x00000294 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH4 Mailbox Data High Register (MB = 4) 0x00000298 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR4 Mailbox Control Register (MB = 4) 0x0000029C 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR5 Mailbox Mode Register (MB = 5) 0x000002A0 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM5 Mailbox Acceptance Mask Register (MB = 5) 0x000002A4 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID5 Mailbox ID Register (MB = 5) 0x000002A8 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID5 Mailbox Family ID Register (MB = 5) 0x000002AC 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR5 Mailbox Status Register (MB = 5) 0x000002B0 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL5 Mailbox Data Low Register (MB = 5) 0x000002B4 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH5 Mailbox Data High Register (MB = 5) 0x000002B8 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR5 Mailbox Control Register (MB = 5) 0x000002BC 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR6 Mailbox Mode Register (MB = 6) 0x000002C0 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM6 Mailbox Acceptance Mask Register (MB = 6) 0x000002C4 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID6 Mailbox ID Register (MB = 6) 0x000002C8 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID6 Mailbox Family ID Register (MB = 6) 0x000002CC 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR6 Mailbox Status Register (MB = 6) 0x000002D0 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL6 Mailbox Data Low Register (MB = 6) 0x000002D4 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH6 Mailbox Data High Register (MB = 6) 0x000002D8 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR6 Mailbox Control Register (MB = 6) 0x000002DC 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR7 Mailbox Mode Register (MB = 7) 0x000002E0 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM7 Mailbox Acceptance Mask Register (MB = 7) 0x000002E4 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID7 Mailbox ID Register (MB = 7) 0x000002E8 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID7 Mailbox Family ID Register (MB = 7) 0x000002EC 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR7 Mailbox Status Register (MB = 7) 0x000002F0 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL7 Mailbox Data Low Register (MB = 7) 0x000002F4 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH7 Mailbox Data High Register (MB = 7) 0x000002F8 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR7 Mailbox Control Register (MB = 7) 0x000002FC 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only CAN1 6019N Controller Area Network 1 CAN CAN1_ 0x400B8000 0 0x4000 registers CAN1 44 MR Mode Register 0x00000000 32 read-write 0x00000000 CANEN CAN Controller Enable 0 1 read-write LPM Disable/Enable Low Power Mode 1 1 read-write ABM Disable/Enable Autobaud/Listen mode 2 1 read-write OVL Disable/Enable Overload Frame 3 1 read-write TEOF Timestamp messages at each end of Frame 4 1 read-write TTM Disable/Enable Time Triggered Mode 5 1 read-write TIMFRZ Enable Timer Freeze 6 1 read-write DRPT Disable Repeat 7 1 read-write RXSYNC Reception Synchronization Stage (not readable) 24 3 read-write DOUBLE_PP Rx Signal with Double Synchro Stages (2 Positive Edges) 0x0 DOUBLE_PN Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge) 0x1 SINGLE_P Rx Signal with Single Synchro Stage (Positive Edge) 0x2 NONE Rx Signal with No Synchro Stage 0x3 IER Interrupt Enable Register 0x00000004 32 write-only MB0 Mailbox 0 Interrupt Enable 0 1 write-only MB1 Mailbox 1 Interrupt Enable 1 1 write-only MB2 Mailbox 2 Interrupt Enable 2 1 write-only MB3 Mailbox 3 Interrupt Enable 3 1 write-only MB4 Mailbox 4 Interrupt Enable 4 1 write-only MB5 Mailbox 5 Interrupt Enable 5 1 write-only MB6 Mailbox 6 Interrupt Enable 6 1 write-only MB7 Mailbox 7 Interrupt Enable 7 1 write-only ERRA Error Active Mode Interrupt Enable 16 1 write-only WARN Warning Limit Interrupt Enable 17 1 write-only ERRP Error Passive Mode Interrupt Enable 18 1 write-only BOFF Bus Off Mode Interrupt Enable 19 1 write-only SLEEP Sleep Interrupt Enable 20 1 write-only WAKEUP Wakeup Interrupt Enable 21 1 write-only TOVF Timer Overflow Interrupt Enable 22 1 write-only TSTP TimeStamp Interrupt Enable 23 1 write-only CERR CRC Error Interrupt Enable 24 1 write-only SERR Stuffing Error Interrupt Enable 25 1 write-only AERR Acknowledgment Error Interrupt Enable 26 1 write-only FERR Form Error Interrupt Enable 27 1 write-only BERR Bit Error Interrupt Enable 28 1 write-only IDR Interrupt Disable Register 0x00000008 32 write-only MB0 Mailbox 0 Interrupt Disable 0 1 write-only MB1 Mailbox 1 Interrupt Disable 1 1 write-only MB2 Mailbox 2 Interrupt Disable 2 1 write-only MB3 Mailbox 3 Interrupt Disable 3 1 write-only MB4 Mailbox 4 Interrupt Disable 4 1 write-only MB5 Mailbox 5 Interrupt Disable 5 1 write-only MB6 Mailbox 6 Interrupt Disable 6 1 write-only MB7 Mailbox 7 Interrupt Disable 7 1 write-only ERRA Error Active Mode Interrupt Disable 16 1 write-only WARN Warning Limit Interrupt Disable 17 1 write-only ERRP Error Passive Mode Interrupt Disable 18 1 write-only BOFF Bus Off Mode Interrupt Disable 19 1 write-only SLEEP Sleep Interrupt Disable 20 1 write-only WAKEUP Wakeup Interrupt Disable 21 1 write-only TOVF Timer Overflow Interrupt 22 1 write-only TSTP TimeStamp Interrupt Disable 23 1 write-only CERR CRC Error Interrupt Disable 24 1 write-only SERR Stuffing Error Interrupt Disable 25 1 write-only AERR Acknowledgment Error Interrupt Disable 26 1 write-only FERR Form Error Interrupt Disable 27 1 write-only BERR Bit Error Interrupt Disable 28 1 write-only IMR Interrupt Mask Register 0x0000000C 32 read-only 0x00000000 MB0 Mailbox 0 Interrupt Mask 0 1 read-only MB1 Mailbox 1 Interrupt Mask 1 1 read-only MB2 Mailbox 2 Interrupt Mask 2 1 read-only MB3 Mailbox 3 Interrupt Mask 3 1 read-only MB4 Mailbox 4 Interrupt Mask 4 1 read-only MB5 Mailbox 5 Interrupt Mask 5 1 read-only MB6 Mailbox 6 Interrupt Mask 6 1 read-only MB7 Mailbox 7 Interrupt Mask 7 1 read-only ERRA Error Active Mode Interrupt Mask 16 1 read-only WARN Warning Limit Interrupt Mask 17 1 read-only ERRP Error Passive Mode Interrupt Mask 18 1 read-only BOFF Bus Off Mode Interrupt Mask 19 1 read-only SLEEP Sleep Interrupt Mask 20 1 read-only WAKEUP Wakeup Interrupt Mask 21 1 read-only TOVF Timer Overflow Interrupt Mask 22 1 read-only TSTP Timestamp Interrupt Mask 23 1 read-only CERR CRC Error Interrupt Mask 24 1 read-only SERR Stuffing Error Interrupt Mask 25 1 read-only AERR Acknowledgment Error Interrupt Mask 26 1 read-only FERR Form Error Interrupt Mask 27 1 read-only BERR Bit Error Interrupt Mask 28 1 read-only SR Status Register 0x00000010 32 read-only 0x00000000 MB0 Mailbox 0 Event 0 1 read-only MB1 Mailbox 1 Event 1 1 read-only MB2 Mailbox 2 Event 2 1 read-only MB3 Mailbox 3 Event 3 1 read-only MB4 Mailbox 4 Event 4 1 read-only MB5 Mailbox 5 Event 5 1 read-only MB6 Mailbox 6 Event 6 1 read-only MB7 Mailbox 7 Event 7 1 read-only ERRA Error Active Mode 16 1 read-only WARN Warning Limit 17 1 read-only ERRP Error Passive Mode 18 1 read-only BOFF Bus Off Mode 19 1 read-only SLEEP CAN controller in Low power Mode 20 1 read-only WAKEUP CAN controller is not in Low power Mode 21 1 read-only TOVF Timer Overflow 22 1 read-only TSTP 23 1 read-only CERR Mailbox CRC Error 24 1 read-only SERR Mailbox Stuffing Error 25 1 read-only AERR Acknowledgment Error 26 1 read-only FERR Form Error 27 1 read-only BERR Bit Error 28 1 read-only RBSY Receiver busy 29 1 read-only TBSY Transmitter busy 30 1 read-only OVLSY Overload busy 31 1 read-only BR Baudrate Register 0x00000014 32 read-write 0x00000000 PHASE2 Phase 2 segment 0 3 read-write PHASE1 Phase 1 segment 4 3 read-write PROPAG Programming time segment 8 3 read-write SJW Re-synchronization jump width 12 2 read-write BRP Baudrate Prescaler. 16 7 read-write SMP Sampling Mode 24 1 read-write ONCE The incoming bit stream is sampled once at sample point. 0 THREE The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. 1 TIM Timer Register 0x00000018 32 read-only 0x00000000 TIMER Timer 0 16 read-only TIMESTP Timestamp Register 0x0000001C 32 read-only 0x00000000 MTIMESTAMP Timestamp 0 16 read-only ECR Error Counter Register 0x00000020 32 read-only 0x00000000 REC Receive Error Counter 0 8 read-only TEC Transmit Error Counter 16 8 read-only TCR Transfer Command Register 0x00000024 32 write-only MB0 Transfer Request for Mailbox 0 0 1 write-only MB1 Transfer Request for Mailbox 1 1 1 write-only MB2 Transfer Request for Mailbox 2 2 1 write-only MB3 Transfer Request for Mailbox 3 3 1 write-only MB4 Transfer Request for Mailbox 4 4 1 write-only MB5 Transfer Request for Mailbox 5 5 1 write-only MB6 Transfer Request for Mailbox 6 6 1 write-only MB7 Transfer Request for Mailbox 7 7 1 write-only TIMRST Timer Reset 31 1 write-only ACR Abort Command Register 0x00000028 32 write-only MB0 Abort Request for Mailbox 0 0 1 write-only MB1 Abort Request for Mailbox 1 1 1 write-only MB2 Abort Request for Mailbox 2 2 1 write-only MB3 Abort Request for Mailbox 3 3 1 write-only MB4 Abort Request for Mailbox 4 4 1 write-only MB5 Abort Request for Mailbox 5 5 1 write-only MB6 Abort Request for Mailbox 6 6 1 write-only MB7 Abort Request for Mailbox 7 7 1 write-only WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protection Enable 0 1 read-write WPKEY SPI Write Protection Key Password 8 24 read-write WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 8 read-only MMR0 Mailbox Mode Register (MB = 0) 0x00000200 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM0 Mailbox Acceptance Mask Register (MB = 0) 0x00000204 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID0 Mailbox ID Register (MB = 0) 0x00000208 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID0 Mailbox Family ID Register (MB = 0) 0x0000020C 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR0 Mailbox Status Register (MB = 0) 0x00000210 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL0 Mailbox Data Low Register (MB = 0) 0x00000214 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH0 Mailbox Data High Register (MB = 0) 0x00000218 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR0 Mailbox Control Register (MB = 0) 0x0000021C 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR1 Mailbox Mode Register (MB = 1) 0x00000220 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM1 Mailbox Acceptance Mask Register (MB = 1) 0x00000224 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID1 Mailbox ID Register (MB = 1) 0x00000228 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID1 Mailbox Family ID Register (MB = 1) 0x0000022C 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR1 Mailbox Status Register (MB = 1) 0x00000230 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL1 Mailbox Data Low Register (MB = 1) 0x00000234 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH1 Mailbox Data High Register (MB = 1) 0x00000238 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR1 Mailbox Control Register (MB = 1) 0x0000023C 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR2 Mailbox Mode Register (MB = 2) 0x00000240 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM2 Mailbox Acceptance Mask Register (MB = 2) 0x00000244 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID2 Mailbox ID Register (MB = 2) 0x00000248 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID2 Mailbox Family ID Register (MB = 2) 0x0000024C 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR2 Mailbox Status Register (MB = 2) 0x00000250 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL2 Mailbox Data Low Register (MB = 2) 0x00000254 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH2 Mailbox Data High Register (MB = 2) 0x00000258 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR2 Mailbox Control Register (MB = 2) 0x0000025C 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR3 Mailbox Mode Register (MB = 3) 0x00000260 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM3 Mailbox Acceptance Mask Register (MB = 3) 0x00000264 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID3 Mailbox ID Register (MB = 3) 0x00000268 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID3 Mailbox Family ID Register (MB = 3) 0x0000026C 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR3 Mailbox Status Register (MB = 3) 0x00000270 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL3 Mailbox Data Low Register (MB = 3) 0x00000274 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH3 Mailbox Data High Register (MB = 3) 0x00000278 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR3 Mailbox Control Register (MB = 3) 0x0000027C 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR4 Mailbox Mode Register (MB = 4) 0x00000280 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM4 Mailbox Acceptance Mask Register (MB = 4) 0x00000284 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID4 Mailbox ID Register (MB = 4) 0x00000288 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID4 Mailbox Family ID Register (MB = 4) 0x0000028C 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR4 Mailbox Status Register (MB = 4) 0x00000290 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL4 Mailbox Data Low Register (MB = 4) 0x00000294 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH4 Mailbox Data High Register (MB = 4) 0x00000298 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR4 Mailbox Control Register (MB = 4) 0x0000029C 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR5 Mailbox Mode Register (MB = 5) 0x000002A0 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM5 Mailbox Acceptance Mask Register (MB = 5) 0x000002A4 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID5 Mailbox ID Register (MB = 5) 0x000002A8 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID5 Mailbox Family ID Register (MB = 5) 0x000002AC 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR5 Mailbox Status Register (MB = 5) 0x000002B0 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL5 Mailbox Data Low Register (MB = 5) 0x000002B4 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH5 Mailbox Data High Register (MB = 5) 0x000002B8 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR5 Mailbox Control Register (MB = 5) 0x000002BC 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR6 Mailbox Mode Register (MB = 6) 0x000002C0 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM6 Mailbox Acceptance Mask Register (MB = 6) 0x000002C4 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID6 Mailbox ID Register (MB = 6) 0x000002C8 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID6 Mailbox Family ID Register (MB = 6) 0x000002CC 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR6 Mailbox Status Register (MB = 6) 0x000002D0 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL6 Mailbox Data Low Register (MB = 6) 0x000002D4 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH6 Mailbox Data High Register (MB = 6) 0x000002D8 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR6 Mailbox Control Register (MB = 6) 0x000002DC 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only MMR7 Mailbox Mode Register (MB = 7) 0x000002E0 32 read-write 0x00000000 MTIMEMARK Mailbox Timemark 0 16 read-write PRIOR Mailbox Priority 16 4 read-write MOT Mailbox Object Type 24 3 read-write MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 0x0 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 0x1 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 0x2 MB_TX Transmit mailbox. Mailbox is configured for transmission. 0x3 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 0x4 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 0x5 MAM7 Mailbox Acceptance Mask Register (MB = 7) 0x000002E4 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MID7 Mailbox ID Register (MB = 7) 0x000002E8 32 read-write 0x00000000 MIDvB Complementary bits for identifier in extended frame mode 0 18 read-write MIDvA Identifier for standard frame mode 18 11 read-write MIDE Identifier Version 29 1 read-write MFID7 Mailbox Family ID Register (MB = 7) 0x000002EC 32 read-only 0x00000000 MFID Family ID 0 29 read-only MSR7 Mailbox Status Register (MB = 7) 0x000002F0 32 read-only 0x00000000 MTIMESTAMP Timer value 0 16 read-only MDLC Mailbox Data Length Code 16 4 read-only MRTR Mailbox Remote Transmission Request 20 1 read-only MABT Mailbox Message Abort 22 1 read-only MRDY Mailbox Ready 23 1 read-only MMI Mailbox Message Ignored 24 1 read-only MDL7 Mailbox Data Low Register (MB = 7) 0x000002F4 32 read-write 0x00000000 MDL Message Data Low Value 0 32 read-write MDH7 Mailbox Data High Register (MB = 7) 0x000002F8 32 read-write 0x00000000 MDH Message Data High Value 0 32 read-write MCR7 Mailbox Control Register (MB = 7) 0x000002FC 32 write-only MDLC Mailbox Data Length Code 16 4 write-only MRTR Mailbox Remote Transmission Request 20 1 write-only MACR Abort Request for Mailbox x 22 1 write-only MTCR Mailbox Transfer Command 23 1 write-only TRNG 6334D True Random Number Generator TRNG_ 0x400BC000 0 0x4000 registers TRNG 41 CR Control Register 0x00000000 32 write-only ENABLE Enables the TRNG to provide random values 0 1 write-only KEY Security Key 8 24 write-only IER Interrupt Enable Register 0x00000010 32 write-only DATRDY Data Ready Interrupt Enable 0 1 write-only IDR Interrupt Disable Register 0x00000014 32 write-only DATRDY Data Ready Interrupt Disable 0 1 write-only IMR Interrupt Mask Register 0x00000018 32 read-only 0x00000000 DATRDY Data Ready Interrupt Mask 0 1 read-only ISR Interrupt Status Register 0x0000001C 32 read-only 0x00000000 DATRDY Data Ready 0 1 read-only ODATA Output Data Register 0x00000050 32 read-only 0x00000000 ODATA Output Data 0 32 read-only ADC 6489Q Analog-to-Digital Converter ADC_ 0x400C0000 0 0x4000 registers ADC 37 CR Control Register 0x00000000 32 write-only SWRST Software Reset 0 1 write-only START Start Conversion 1 1 write-only MR Mode Register 0x00000004 32 read-write 0x00000000 TRGEN Trigger Enable 0 1 read-write DIS Hardware triggers are disabled. Starting a conversion is only possible by software. 0 EN Hardware trigger selected by TRGSEL field is enabled. 1 TRGSEL Trigger Selection 1 3 read-write ADC_TRIG0 External : ADCTRG 0x0 ADC_TRIG1 TIOA Output of the Timer Counter Channel 0 0x1 ADC_TRIG2 TIOA Output of the Timer Counter Channel 1 0x2 ADC_TRIG3 TIOA Output of the Timer Counter Channel 2 0x3 ADC_TRIG4 PWM Event Line 0 0x4 ADC_TRIG5 PWM Event Line 0 0x5 SLEEP Sleep Mode 5 1 read-write NORMAL Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions 0 SLEEP Sleep Mode: The wake-up time can be modified by programming FWUP bit 1 FWUP Fast Wake Up 6 1 read-write OFF If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions 0 ON If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF 1 FREERUN Free Run Mode 7 1 read-write OFF Normal Mode 0 ON Free Run Mode: Never wait for any trigger. 1 PRESCAL Prescaler Rate Selection 8 8 read-write STARTUP Start Up Time 16 4 read-write SUT0 0 periods of ADCClock 0x0 SUT8 8 periods of ADCClock 0x1 SUT16 16 periods of ADCClock 0x2 SUT24 24 periods of ADCClock 0x3 SUT64 64 periods of ADCClock 0x4 SUT80 80 periods of ADCClock 0x5 SUT96 96 periods of ADCClock 0x6 SUT112 112 periods of ADCClock 0x7 SUT512 512 periods of ADCClock 0x8 SUT576 576 periods of ADCClock 0x9 SUT640 640 periods of ADCClock 0xA SUT704 704 periods of ADCClock 0xB SUT768 768 periods of ADCClock 0xC SUT832 832 periods of ADCClock 0xD SUT896 896 periods of ADCClock 0xE SUT960 960 periods of ADCClock 0xF SETTLING Analog Settling Time 20 2 read-write AST3 3 periods of ADCClock 0x0 AST5 5 periods of ADCClock 0x1 AST9 9 periods of ADCClock 0x2 AST17 17 periods of ADCClock 0x3 ANACH Analog Change 23 1 read-write NONE No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels 0 ALLOWED Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers 1 TRACKTIM Tracking Time 24 4 read-write TRANSFER Transfer Period 28 2 read-write USEQ Use Sequence Enable 31 1 read-write NUM_ORDER Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. 0 REG_ORDER User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. 1 SEQR1 Channel Sequence Register 1 0x00000008 32 read-write 0x00000000 USCH1 User Sequence Number 1 0 4 read-write USCH2 User Sequence Number 2 4 4 read-write USCH3 User Sequence Number 3 8 4 read-write USCH4 User Sequence Number 4 12 4 read-write USCH5 User Sequence Number 5 16 4 read-write USCH6 User Sequence Number 6 20 4 read-write USCH7 User Sequence Number 7 24 4 read-write USCH8 User Sequence Number 8 28 4 read-write SEQR2 Channel Sequence Register 2 0x0000000C 32 read-write 0x00000000 USCH9 User Sequence Number 9 0 4 read-write USCH10 User Sequence Number 10 4 4 read-write USCH11 User Sequence Number 11 8 4 read-write USCH12 User Sequence Number 12 12 4 read-write USCH13 User Sequence Number 13 16 4 read-write USCH14 User Sequence Number 14 20 4 read-write USCH15 User Sequence Number 15 24 4 read-write CHER Channel Enable Register 0x00000010 32 write-only CH0 Channel 0 Enable 0 1 write-only CH1 Channel 1 Enable 1 1 write-only CH2 Channel 2 Enable 2 1 write-only CH3 Channel 3 Enable 3 1 write-only CH4 Channel 4 Enable 4 1 write-only CH5 Channel 5 Enable 5 1 write-only CH6 Channel 6 Enable 6 1 write-only CH7 Channel 7 Enable 7 1 write-only CH8 Channel 8 Enable 8 1 write-only CH9 Channel 9 Enable 9 1 write-only CH10 Channel 10 Enable 10 1 write-only CH11 Channel 11 Enable 11 1 write-only CH12 Channel 12 Enable 12 1 write-only CH13 Channel 13 Enable 13 1 write-only CH14 Channel 14 Enable 14 1 write-only CH15 Channel 15 Enable 15 1 write-only CHDR Channel Disable Register 0x00000014 32 write-only CH0 Channel 0 Disable 0 1 write-only CH1 Channel 1 Disable 1 1 write-only CH2 Channel 2 Disable 2 1 write-only CH3 Channel 3 Disable 3 1 write-only CH4 Channel 4 Disable 4 1 write-only CH5 Channel 5 Disable 5 1 write-only CH6 Channel 6 Disable 6 1 write-only CH7 Channel 7 Disable 7 1 write-only CH8 Channel 8 Disable 8 1 write-only CH9 Channel 9 Disable 9 1 write-only CH10 Channel 10 Disable 10 1 write-only CH11 Channel 11 Disable 11 1 write-only CH12 Channel 12 Disable 12 1 write-only CH13 Channel 13 Disable 13 1 write-only CH14 Channel 14 Disable 14 1 write-only CH15 Channel 15 Disable 15 1 write-only CHSR Channel Status Register 0x00000018 32 read-only 0x00000000 CH0 Channel 0 Status 0 1 read-only CH1 Channel 1 Status 1 1 read-only CH2 Channel 2 Status 2 1 read-only CH3 Channel 3 Status 3 1 read-only CH4 Channel 4 Status 4 1 read-only CH5 Channel 5 Status 5 1 read-only CH6 Channel 6 Status 6 1 read-only CH7 Channel 7 Status 7 1 read-only CH8 Channel 8 Status 8 1 read-only CH9 Channel 9 Status 9 1 read-only CH10 Channel 10 Status 10 1 read-only CH11 Channel 11 Status 11 1 read-only CH12 Channel 12 Status 12 1 read-only CH13 Channel 13 Status 13 1 read-only CH14 Channel 14 Status 14 1 read-only CH15 Channel 15 Status 15 1 read-only LCDR Last Converted Data Register 0x00000020 32 read-only 0x00000000 LDATA Last Data Converted 0 12 read-only CHNB Channel Number 12 4 read-only IER Interrupt Enable Register 0x00000024 32 write-only EOC0 End of Conversion Interrupt Enable 0 0 1 write-only EOC1 End of Conversion Interrupt Enable 1 1 1 write-only EOC2 End of Conversion Interrupt Enable 2 2 1 write-only EOC3 End of Conversion Interrupt Enable 3 3 1 write-only EOC4 End of Conversion Interrupt Enable 4 4 1 write-only EOC5 End of Conversion Interrupt Enable 5 5 1 write-only EOC6 End of Conversion Interrupt Enable 6 6 1 write-only EOC7 End of Conversion Interrupt Enable 7 7 1 write-only EOC8 End of Conversion Interrupt Enable 8 8 1 write-only EOC9 End of Conversion Interrupt Enable 9 9 1 write-only EOC10 End of Conversion Interrupt Enable 10 10 1 write-only EOC11 End of Conversion Interrupt Enable 11 11 1 write-only EOC12 End of Conversion Interrupt Enable 12 12 1 write-only EOC13 End of Conversion Interrupt Enable 13 13 1 write-only EOC14 End of Conversion Interrupt Enable 14 14 1 write-only EOC15 End of Conversion Interrupt Enable 15 15 1 write-only DRDY Data Ready Interrupt Enable 24 1 write-only GOVRE General Overrun Error Interrupt Enable 25 1 write-only COMPE Comparison Event Interrupt Enable 26 1 write-only ENDRX End of Receive Buffer Interrupt Enable 27 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 28 1 write-only IDR Interrupt Disable Register 0x00000028 32 write-only EOC0 End of Conversion Interrupt Disable 0 0 1 write-only EOC1 End of Conversion Interrupt Disable 1 1 1 write-only EOC2 End of Conversion Interrupt Disable 2 2 1 write-only EOC3 End of Conversion Interrupt Disable 3 3 1 write-only EOC4 End of Conversion Interrupt Disable 4 4 1 write-only EOC5 End of Conversion Interrupt Disable 5 5 1 write-only EOC6 End of Conversion Interrupt Disable 6 6 1 write-only EOC7 End of Conversion Interrupt Disable 7 7 1 write-only EOC8 End of Conversion Interrupt Disable 8 8 1 write-only EOC9 End of Conversion Interrupt Disable 9 9 1 write-only EOC10 End of Conversion Interrupt Disable 10 10 1 write-only EOC11 End of Conversion Interrupt Disable 11 11 1 write-only EOC12 End of Conversion Interrupt Disable 12 12 1 write-only EOC13 End of Conversion Interrupt Disable 13 13 1 write-only EOC14 End of Conversion Interrupt Disable 14 14 1 write-only EOC15 End of Conversion Interrupt Disable 15 15 1 write-only DRDY Data Ready Interrupt Disable 24 1 write-only GOVRE General Overrun Error Interrupt Disable 25 1 write-only COMPE Comparison Event Interrupt Disable 26 1 write-only ENDRX End of Receive Buffer Interrupt Disable 27 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 28 1 write-only IMR Interrupt Mask Register 0x0000002C 32 read-only 0x00000000 EOC0 End of Conversion Interrupt Mask 0 0 1 read-only EOC1 End of Conversion Interrupt Mask 1 1 1 read-only EOC2 End of Conversion Interrupt Mask 2 2 1 read-only EOC3 End of Conversion Interrupt Mask 3 3 1 read-only EOC4 End of Conversion Interrupt Mask 4 4 1 read-only EOC5 End of Conversion Interrupt Mask 5 5 1 read-only EOC6 End of Conversion Interrupt Mask 6 6 1 read-only EOC7 End of Conversion Interrupt Mask 7 7 1 read-only EOC8 End of Conversion Interrupt Mask 8 8 1 read-only EOC9 End of Conversion Interrupt Mask 9 9 1 read-only EOC10 End of Conversion Interrupt Mask 10 10 1 read-only EOC11 End of Conversion Interrupt Mask 11 11 1 read-only EOC12 End of Conversion Interrupt Mask 12 12 1 read-only EOC13 End of Conversion Interrupt Mask 13 13 1 read-only EOC14 End of Conversion Interrupt Mask 14 14 1 read-only EOC15 End of Conversion Interrupt Mask 15 15 1 read-only DRDY Data Ready Interrupt Mask 24 1 read-only GOVRE General Overrun Error Interrupt Mask 25 1 read-only COMPE Comparison Event Interrupt Mask 26 1 read-only ENDRX End of Receive Buffer Interrupt Mask 27 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 28 1 read-only ISR Interrupt Status Register 0x00000030 32 read-only 0x00000000 EOC0 End of Conversion 0 0 1 read-only EOC1 End of Conversion 1 1 1 read-only EOC2 End of Conversion 2 2 1 read-only EOC3 End of Conversion 3 3 1 read-only EOC4 End of Conversion 4 4 1 read-only EOC5 End of Conversion 5 5 1 read-only EOC6 End of Conversion 6 6 1 read-only EOC7 End of Conversion 7 7 1 read-only EOC8 End of Conversion 8 8 1 read-only EOC9 End of Conversion 9 9 1 read-only EOC10 End of Conversion 10 10 1 read-only EOC11 End of Conversion 11 11 1 read-only EOC12 End of Conversion 12 12 1 read-only EOC13 End of Conversion 13 13 1 read-only EOC14 End of Conversion 14 14 1 read-only EOC15 End of Conversion 15 15 1 read-only DRDY Data Ready 24 1 read-only GOVRE General Overrun Error 25 1 read-only COMPE Comparison Error 26 1 read-only ENDRX End of RX Buffer 27 1 read-only RXBUFF RX Buffer Full 28 1 read-only OVER Overrun Status Register 0x0000003C 32 read-only 0x00000000 OVRE0 Overrun Error 0 0 1 read-only OVRE1 Overrun Error 1 1 1 read-only OVRE2 Overrun Error 2 2 1 read-only OVRE3 Overrun Error 3 3 1 read-only OVRE4 Overrun Error 4 4 1 read-only OVRE5 Overrun Error 5 5 1 read-only OVRE6 Overrun Error 6 6 1 read-only OVRE7 Overrun Error 7 7 1 read-only OVRE8 Overrun Error 8 8 1 read-only OVRE9 Overrun Error 9 9 1 read-only OVRE10 Overrun Error 10 10 1 read-only OVRE11 Overrun Error 11 11 1 read-only OVRE12 Overrun Error 12 12 1 read-only OVRE13 Overrun Error 13 13 1 read-only OVRE14 Overrun Error 14 14 1 read-only OVRE15 Overrun Error 15 15 1 read-only EMR Extended Mode Register 0x00000040 32 read-write 0x00000000 CMPMODE Comparison Mode 0 2 read-write LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 CMPSEL Comparison Selected Channel 4 4 read-write CMPALL Compare All Channels 9 1 read-write CMPFILTER Compare Event Filtering 12 2 read-write TAG TAG of the ADC_LDCR register 24 1 read-write CWR Compare Window Register 0x00000044 32 read-write 0x00000000 LOWTHRES Low Threshold 0 12 read-write HIGHTHRES High Threshold 16 12 read-write CGR Channel Gain Register 0x00000048 32 read-write 0x00000000 GAIN0 Gain for Channel 0 0 2 read-write GAIN1 Gain for Channel 1 2 2 read-write GAIN2 Gain for Channel 2 4 2 read-write GAIN3 Gain for Channel 3 6 2 read-write GAIN4 Gain for Channel 4 8 2 read-write GAIN5 Gain for Channel 5 10 2 read-write GAIN6 Gain for Channel 6 12 2 read-write GAIN7 Gain for Channel 7 14 2 read-write GAIN8 Gain for Channel 8 16 2 read-write GAIN9 Gain for Channel 9 18 2 read-write GAIN10 Gain for Channel 10 20 2 read-write GAIN11 Gain for Channel 11 22 2 read-write GAIN12 Gain for Channel 12 24 2 read-write GAIN13 Gain for Channel 13 26 2 read-write GAIN14 Gain for Channel 14 28 2 read-write GAIN15 Gain for Channel 15 30 2 read-write COR Channel Offset Register 0x0000004C 32 read-write 0x00000000 OFF0 Offset for channel 0 0 1 read-write OFF1 Offset for channel 1 1 1 read-write OFF2 Offset for channel 2 2 1 read-write OFF3 Offset for channel 3 3 1 read-write OFF4 Offset for channel 4 4 1 read-write OFF5 Offset for channel 5 5 1 read-write OFF6 Offset for channel 6 6 1 read-write OFF7 Offset for channel 7 7 1 read-write OFF8 Offset for channel 8 8 1 read-write OFF9 Offset for channel 9 9 1 read-write OFF10 Offset for channel 10 10 1 read-write OFF11 Offset for channel 11 11 1 read-write OFF12 Offset for channel 12 12 1 read-write OFF13 Offset for channel 13 13 1 read-write OFF14 Offset for channel 14 14 1 read-write OFF15 Offset for channel 15 15 1 read-write DIFF0 Differential inputs for channel 0 16 1 read-write DIFF1 Differential inputs for channel 1 17 1 read-write DIFF2 Differential inputs for channel 2 18 1 read-write DIFF3 Differential inputs for channel 3 19 1 read-write DIFF4 Differential inputs for channel 4 20 1 read-write DIFF5 Differential inputs for channel 5 21 1 read-write DIFF6 Differential inputs for channel 6 22 1 read-write DIFF7 Differential inputs for channel 7 23 1 read-write DIFF8 Differential inputs for channel 8 24 1 read-write DIFF9 Differential inputs for channel 9 25 1 read-write DIFF10 Differential inputs for channel 10 26 1 read-write DIFF11 Differential inputs for channel 11 27 1 read-write DIFF12 Differential inputs for channel 12 28 1 read-write DIFF13 Differential inputs for channel 13 29 1 read-write DIFF14 Differential inputs for channel 14 30 1 read-write DIFF15 Differential inputs for channel 15 31 1 read-write 16 4 0-15 CDR[%s] Channel Data Register 0x00000050 32 read-only DATA Converted Data 0 12 read-only ACR Analog Control Register 0x00000094 32 read-write 0x00000100 TSON Temperature Sensor On 4 1 read-write IBCTL ADC Bias Current Control 8 2 read-write WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x414443 WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only DMAC 6233P DMA Controller DMAC_ 0x400C4000 0 0x4000 registers DMAC 39 GCFG DMAC Global Configuration Register 0x00000000 32 read-write 0x00000010 ARB_CFG Arbiter Configuration 4 1 read-write FIXED Fixed priority arbiter (see "Basic Definitions" ) 0 ROUND_ROBIN Modified round robin arbiter. 1 EN DMAC Enable Register 0x00000004 32 read-write 0x00000000 ENABLE General Enable of DMA 0 1 read-write SREQ DMAC Software Single Request Register 0x00000008 32 read-write 0x00000000 SSREQ0 Source Request 0 1 read-write DSREQ0 Destination Request 1 1 read-write SSREQ1 Source Request 2 1 read-write DSREQ1 Destination Request 3 1 read-write SSREQ2 Source Request 4 1 read-write DSREQ2 Destination Request 5 1 read-write SSREQ3 Source Request 6 1 read-write DSREQ3 Destination Request 7 1 read-write SSREQ4 Source Request 8 1 read-write DSREQ4 Destination Request 9 1 read-write SSREQ5 Source Request 10 1 read-write DSREQ5 Destination Request 11 1 read-write CREQ DMAC Software Chunk Transfer Request Register 0x0000000C 32 read-write 0x00000000 SCREQ0 Source Chunk Request 0 1 read-write DCREQ0 Destination Chunk Request 1 1 read-write SCREQ1 Source Chunk Request 2 1 read-write DCREQ1 Destination Chunk Request 3 1 read-write SCREQ2 Source Chunk Request 4 1 read-write DCREQ2 Destination Chunk Request 5 1 read-write SCREQ3 Source Chunk Request 6 1 read-write DCREQ3 Destination Chunk Request 7 1 read-write SCREQ4 Source Chunk Request 8 1 read-write DCREQ4 Destination Chunk Request 9 1 read-write SCREQ5 Source Chunk Request 10 1 read-write DCREQ5 Destination Chunk Request 11 1 read-write LAST DMAC Software Last Transfer Flag Register 0x00000010 32 read-write 0x00000000 SLAST0 Source Last 0 1 read-write DLAST0 Destination Last 1 1 read-write SLAST1 Source Last 2 1 read-write DLAST1 Destination Last 3 1 read-write SLAST2 Source Last 4 1 read-write DLAST2 Destination Last 5 1 read-write SLAST3 Source Last 6 1 read-write DLAST3 Destination Last 7 1 read-write SLAST4 Source Last 8 1 read-write DLAST4 Destination Last 9 1 read-write SLAST5 Source Last 10 1 read-write DLAST5 Destination Last 11 1 read-write EBCIER DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. 0x00000018 32 write-only BTC0 Buffer Transfer Completed [5:0] 0 1 write-only BTC1 Buffer Transfer Completed [5:0] 1 1 write-only BTC2 Buffer Transfer Completed [5:0] 2 1 write-only BTC3 Buffer Transfer Completed [5:0] 3 1 write-only BTC4 Buffer Transfer Completed [5:0] 4 1 write-only BTC5 Buffer Transfer Completed [5:0] 5 1 write-only CBTC0 Chained Buffer Transfer Completed [5:0] 8 1 write-only CBTC1 Chained Buffer Transfer Completed [5:0] 9 1 write-only CBTC2 Chained Buffer Transfer Completed [5:0] 10 1 write-only CBTC3 Chained Buffer Transfer Completed [5:0] 11 1 write-only CBTC4 Chained Buffer Transfer Completed [5:0] 12 1 write-only CBTC5 Chained Buffer Transfer Completed [5:0] 13 1 write-only ERR0 Access Error [5:0] 16 1 write-only ERR1 Access Error [5:0] 17 1 write-only ERR2 Access Error [5:0] 18 1 write-only ERR3 Access Error [5:0] 19 1 write-only ERR4 Access Error [5:0] 20 1 write-only ERR5 Access Error [5:0] 21 1 write-only EBCIDR DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. 0x0000001C 32 write-only BTC0 Buffer Transfer Completed [5:0] 0 1 write-only BTC1 Buffer Transfer Completed [5:0] 1 1 write-only BTC2 Buffer Transfer Completed [5:0] 2 1 write-only BTC3 Buffer Transfer Completed [5:0] 3 1 write-only BTC4 Buffer Transfer Completed [5:0] 4 1 write-only BTC5 Buffer Transfer Completed [5:0] 5 1 write-only CBTC0 Chained Buffer Transfer Completed [5:0] 8 1 write-only CBTC1 Chained Buffer Transfer Completed [5:0] 9 1 write-only CBTC2 Chained Buffer Transfer Completed [5:0] 10 1 write-only CBTC3 Chained Buffer Transfer Completed [5:0] 11 1 write-only CBTC4 Chained Buffer Transfer Completed [5:0] 12 1 write-only CBTC5 Chained Buffer Transfer Completed [5:0] 13 1 write-only ERR0 Access Error [5:0] 16 1 write-only ERR1 Access Error [5:0] 17 1 write-only ERR2 Access Error [5:0] 18 1 write-only ERR3 Access Error [5:0] 19 1 write-only ERR4 Access Error [5:0] 20 1 write-only ERR5 Access Error [5:0] 21 1 write-only EBCIMR DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. 0x00000020 32 read-only 0x00000000 BTC0 Buffer Transfer Completed [5:0] 0 1 read-only BTC1 Buffer Transfer Completed [5:0] 1 1 read-only BTC2 Buffer Transfer Completed [5:0] 2 1 read-only BTC3 Buffer Transfer Completed [5:0] 3 1 read-only BTC4 Buffer Transfer Completed [5:0] 4 1 read-only BTC5 Buffer Transfer Completed [5:0] 5 1 read-only CBTC0 Chained Buffer Transfer Completed [5:0] 8 1 read-only CBTC1 Chained Buffer Transfer Completed [5:0] 9 1 read-only CBTC2 Chained Buffer Transfer Completed [5:0] 10 1 read-only CBTC3 Chained Buffer Transfer Completed [5:0] 11 1 read-only CBTC4 Chained Buffer Transfer Completed [5:0] 12 1 read-only CBTC5 Chained Buffer Transfer Completed [5:0] 13 1 read-only ERR0 Access Error [5:0] 16 1 read-only ERR1 Access Error [5:0] 17 1 read-only ERR2 Access Error [5:0] 18 1 read-only ERR3 Access Error [5:0] 19 1 read-only ERR4 Access Error [5:0] 20 1 read-only ERR5 Access Error [5:0] 21 1 read-only EBCISR DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. 0x00000024 32 read-only 0x00000000 BTC0 Buffer Transfer Completed [5:0] 0 1 read-only BTC1 Buffer Transfer Completed [5:0] 1 1 read-only BTC2 Buffer Transfer Completed [5:0] 2 1 read-only BTC3 Buffer Transfer Completed [5:0] 3 1 read-only BTC4 Buffer Transfer Completed [5:0] 4 1 read-only BTC5 Buffer Transfer Completed [5:0] 5 1 read-only CBTC0 Chained Buffer Transfer Completed [5:0] 8 1 read-only CBTC1 Chained Buffer Transfer Completed [5:0] 9 1 read-only CBTC2 Chained Buffer Transfer Completed [5:0] 10 1 read-only CBTC3 Chained Buffer Transfer Completed [5:0] 11 1 read-only CBTC4 Chained Buffer Transfer Completed [5:0] 12 1 read-only CBTC5 Chained Buffer Transfer Completed [5:0] 13 1 read-only ERR0 Access Error [5:0] 16 1 read-only ERR1 Access Error [5:0] 17 1 read-only ERR2 Access Error [5:0] 18 1 read-only ERR3 Access Error [5:0] 19 1 read-only ERR4 Access Error [5:0] 20 1 read-only ERR5 Access Error [5:0] 21 1 read-only CHER DMAC Channel Handler Enable Register 0x00000028 32 write-only ENA0 Enable [5:0] 0 1 write-only ENA1 Enable [5:0] 1 1 write-only ENA2 Enable [5:0] 2 1 write-only ENA3 Enable [5:0] 3 1 write-only ENA4 Enable [5:0] 4 1 write-only ENA5 Enable [5:0] 5 1 write-only SUSP0 Suspend [5:0] 8 1 write-only SUSP1 Suspend [5:0] 9 1 write-only SUSP2 Suspend [5:0] 10 1 write-only SUSP3 Suspend [5:0] 11 1 write-only SUSP4 Suspend [5:0] 12 1 write-only SUSP5 Suspend [5:0] 13 1 write-only KEEP0 Keep on [5:0] 24 1 write-only KEEP1 Keep on [5:0] 25 1 write-only KEEP2 Keep on [5:0] 26 1 write-only KEEP3 Keep on [5:0] 27 1 write-only KEEP4 Keep on [5:0] 28 1 write-only KEEP5 Keep on [5:0] 29 1 write-only CHDR DMAC Channel Handler Disable Register 0x0000002C 32 write-only DIS0 Disable [5:0] 0 1 write-only DIS1 Disable [5:0] 1 1 write-only DIS2 Disable [5:0] 2 1 write-only DIS3 Disable [5:0] 3 1 write-only DIS4 Disable [5:0] 4 1 write-only DIS5 Disable [5:0] 5 1 write-only RES0 Resume [5:0] 8 1 write-only RES1 Resume [5:0] 9 1 write-only RES2 Resume [5:0] 10 1 write-only RES3 Resume [5:0] 11 1 write-only RES4 Resume [5:0] 12 1 write-only RES5 Resume [5:0] 13 1 write-only CHSR DMAC Channel Handler Status Register 0x00000030 32 read-only 0x00FF0000 ENA0 Enable [5:0] 0 1 read-only ENA1 Enable [5:0] 1 1 read-only ENA2 Enable [5:0] 2 1 read-only ENA3 Enable [5:0] 3 1 read-only ENA4 Enable [5:0] 4 1 read-only ENA5 Enable [5:0] 5 1 read-only SUSP0 Suspend [5:0] 8 1 read-only SUSP1 Suspend [5:0] 9 1 read-only SUSP2 Suspend [5:0] 10 1 read-only SUSP3 Suspend [5:0] 11 1 read-only SUSP4 Suspend [5:0] 12 1 read-only SUSP5 Suspend [5:0] 13 1 read-only EMPT0 Empty [5:0] 16 1 read-only EMPT1 Empty [5:0] 17 1 read-only EMPT2 Empty [5:0] 18 1 read-only EMPT3 Empty [5:0] 19 1 read-only EMPT4 Empty [5:0] 20 1 read-only EMPT5 Empty [5:0] 21 1 read-only STAL0 Stalled [5:0] 24 1 read-only STAL1 Stalled [5:0] 25 1 read-only STAL2 Stalled [5:0] 26 1 read-only STAL3 Stalled [5:0] 27 1 read-only STAL4 Stalled [5:0] 28 1 read-only STAL5 Stalled [5:0] 29 1 read-only SADDR0 DMAC Channel Source Address Register (ch_num = 0) 0x0000003C 32 read-write 0x00000000 SADDR Channel x Source Address 0 32 read-write DADDR0 DMAC Channel Destination Address Register (ch_num = 0) 0x00000040 32 read-write 0x00000000 DADDR Channel x Destination Address 0 32 read-write DSCR0 DMAC Channel Descriptor Address Register (ch_num = 0) 0x00000044 32 read-write 0x00000000 DSCR Buffer Transfer Descriptor Address 2 30 read-write CTRLA0 DMAC Channel Control A Register (ch_num = 0) 0x00000048 32 read-write 0x00000000 BTSIZE Buffer Transfer Size 0 16 read-write SCSIZE Source Chunk Transfer Size. 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 DCSIZE Destination Chunk Transfer Size 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 SRC_WIDTH Transfer Width for the Source 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH Transfer Width for the Destination 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE Current Descriptor Stop Command and Transfer Completed Memory Indicator 31 1 read-write CTRLB0 DMAC Channel Control B Register (ch_num = 0) 0x0000004C 32 read-write 0x00000000 SRC_DSCR Source Address Descriptor 16 1 read-write FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. 1 DST_DSCR Destination Address Descriptor 20 1 read-write FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. 1 FC Flow Control 21 2 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 SRC_INCR Incrementing, Decrementing or Fixed Address for the Source 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR Incrementing, Decrementing or Fixed Address for the Destination 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN Interrupt Enable Not 30 1 read-write CFG0 DMAC Channel Configuration Register (ch_num = 0) 0x00000050 32 read-write 0x01000000 SRC_PER Source with Peripheral identifier 0 4 read-write DST_PER Destination with Peripheral identifier 4 4 read-write SRC_H2SEL Software or Hardware Selection for the Source 9 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 DST_H2SEL Software or Hardware Selection for the Destination 13 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 SOD Stop On Done 16 1 read-write DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 0 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 1 LOCK_IF Interface Lock 20 1 read-write DISABLE Interface Lock capability is disabled 0 ENABLE Interface Lock capability is enabled 1 LOCK_B Bus Lock 21 1 read-write DISABLE AHB Bus Locking capability is disabled. 0 LOCK_IF_L Master Interface Arbiter Lock 22 1 read-write CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 0 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. 1 AHB_PROT AHB Protection 24 3 read-write FIFOCFG FIFO Configuration 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 SADDR1 DMAC Channel Source Address Register (ch_num = 1) 0x00000064 32 read-write 0x00000000 SADDR Channel x Source Address 0 32 read-write DADDR1 DMAC Channel Destination Address Register (ch_num = 1) 0x00000068 32 read-write 0x00000000 DADDR Channel x Destination Address 0 32 read-write DSCR1 DMAC Channel Descriptor Address Register (ch_num = 1) 0x0000006C 32 read-write 0x00000000 DSCR Buffer Transfer Descriptor Address 2 30 read-write CTRLA1 DMAC Channel Control A Register (ch_num = 1) 0x00000070 32 read-write 0x00000000 BTSIZE Buffer Transfer Size 0 16 read-write SCSIZE Source Chunk Transfer Size. 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 DCSIZE Destination Chunk Transfer Size 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 SRC_WIDTH Transfer Width for the Source 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH Transfer Width for the Destination 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE Current Descriptor Stop Command and Transfer Completed Memory Indicator 31 1 read-write CTRLB1 DMAC Channel Control B Register (ch_num = 1) 0x00000074 32 read-write 0x00000000 SRC_DSCR Source Address Descriptor 16 1 read-write FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. 1 DST_DSCR Destination Address Descriptor 20 1 read-write FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. 1 FC Flow Control 21 2 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 SRC_INCR Incrementing, Decrementing or Fixed Address for the Source 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR Incrementing, Decrementing or Fixed Address for the Destination 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN Interrupt Enable Not 30 1 read-write CFG1 DMAC Channel Configuration Register (ch_num = 1) 0x00000078 32 read-write 0x01000000 SRC_PER Source with Peripheral identifier 0 4 read-write DST_PER Destination with Peripheral identifier 4 4 read-write SRC_H2SEL Software or Hardware Selection for the Source 9 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 DST_H2SEL Software or Hardware Selection for the Destination 13 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 SOD Stop On Done 16 1 read-write DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 0 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 1 LOCK_IF Interface Lock 20 1 read-write DISABLE Interface Lock capability is disabled 0 ENABLE Interface Lock capability is enabled 1 LOCK_B Bus Lock 21 1 read-write DISABLE AHB Bus Locking capability is disabled. 0 LOCK_IF_L Master Interface Arbiter Lock 22 1 read-write CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 0 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. 1 AHB_PROT AHB Protection 24 3 read-write FIFOCFG FIFO Configuration 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 SADDR2 DMAC Channel Source Address Register (ch_num = 2) 0x0000008C 32 read-write 0x00000000 SADDR Channel x Source Address 0 32 read-write DADDR2 DMAC Channel Destination Address Register (ch_num = 2) 0x00000090 32 read-write 0x00000000 DADDR Channel x Destination Address 0 32 read-write DSCR2 DMAC Channel Descriptor Address Register (ch_num = 2) 0x00000094 32 read-write 0x00000000 DSCR Buffer Transfer Descriptor Address 2 30 read-write CTRLA2 DMAC Channel Control A Register (ch_num = 2) 0x00000098 32 read-write 0x00000000 BTSIZE Buffer Transfer Size 0 16 read-write SCSIZE Source Chunk Transfer Size. 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 DCSIZE Destination Chunk Transfer Size 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 SRC_WIDTH Transfer Width for the Source 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH Transfer Width for the Destination 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE Current Descriptor Stop Command and Transfer Completed Memory Indicator 31 1 read-write CTRLB2 DMAC Channel Control B Register (ch_num = 2) 0x0000009C 32 read-write 0x00000000 SRC_DSCR Source Address Descriptor 16 1 read-write FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. 1 DST_DSCR Destination Address Descriptor 20 1 read-write FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. 1 FC Flow Control 21 2 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 SRC_INCR Incrementing, Decrementing or Fixed Address for the Source 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR Incrementing, Decrementing or Fixed Address for the Destination 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN Interrupt Enable Not 30 1 read-write CFG2 DMAC Channel Configuration Register (ch_num = 2) 0x000000A0 32 read-write 0x01000000 SRC_PER Source with Peripheral identifier 0 4 read-write DST_PER Destination with Peripheral identifier 4 4 read-write SRC_H2SEL Software or Hardware Selection for the Source 9 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 DST_H2SEL Software or Hardware Selection for the Destination 13 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 SOD Stop On Done 16 1 read-write DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 0 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 1 LOCK_IF Interface Lock 20 1 read-write DISABLE Interface Lock capability is disabled 0 ENABLE Interface Lock capability is enabled 1 LOCK_B Bus Lock 21 1 read-write DISABLE AHB Bus Locking capability is disabled. 0 LOCK_IF_L Master Interface Arbiter Lock 22 1 read-write CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 0 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. 1 AHB_PROT AHB Protection 24 3 read-write FIFOCFG FIFO Configuration 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 SADDR3 DMAC Channel Source Address Register (ch_num = 3) 0x000000B4 32 read-write 0x00000000 SADDR Channel x Source Address 0 32 read-write DADDR3 DMAC Channel Destination Address Register (ch_num = 3) 0x000000B8 32 read-write 0x00000000 DADDR Channel x Destination Address 0 32 read-write DSCR3 DMAC Channel Descriptor Address Register (ch_num = 3) 0x000000BC 32 read-write 0x00000000 DSCR Buffer Transfer Descriptor Address 2 30 read-write CTRLA3 DMAC Channel Control A Register (ch_num = 3) 0x000000C0 32 read-write 0x00000000 BTSIZE Buffer Transfer Size 0 16 read-write SCSIZE Source Chunk Transfer Size. 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 DCSIZE Destination Chunk Transfer Size 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 SRC_WIDTH Transfer Width for the Source 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH Transfer Width for the Destination 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE Current Descriptor Stop Command and Transfer Completed Memory Indicator 31 1 read-write CTRLB3 DMAC Channel Control B Register (ch_num = 3) 0x000000C4 32 read-write 0x00000000 SRC_DSCR Source Address Descriptor 16 1 read-write FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. 1 DST_DSCR Destination Address Descriptor 20 1 read-write FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. 1 FC Flow Control 21 2 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 SRC_INCR Incrementing, Decrementing or Fixed Address for the Source 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR Incrementing, Decrementing or Fixed Address for the Destination 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN Interrupt Enable Not 30 1 read-write CFG3 DMAC Channel Configuration Register (ch_num = 3) 0x000000C8 32 read-write 0x01000000 SRC_PER Source with Peripheral identifier 0 4 read-write DST_PER Destination with Peripheral identifier 4 4 read-write SRC_H2SEL Software or Hardware Selection for the Source 9 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 DST_H2SEL Software or Hardware Selection for the Destination 13 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 SOD Stop On Done 16 1 read-write DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 0 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 1 LOCK_IF Interface Lock 20 1 read-write DISABLE Interface Lock capability is disabled 0 ENABLE Interface Lock capability is enabled 1 LOCK_B Bus Lock 21 1 read-write DISABLE AHB Bus Locking capability is disabled. 0 LOCK_IF_L Master Interface Arbiter Lock 22 1 read-write CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 0 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. 1 AHB_PROT AHB Protection 24 3 read-write FIFOCFG FIFO Configuration 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 SADDR4 DMAC Channel Source Address Register (ch_num = 4) 0x000000DC 32 read-write 0x00000000 SADDR Channel x Source Address 0 32 read-write DADDR4 DMAC Channel Destination Address Register (ch_num = 4) 0x000000E0 32 read-write 0x00000000 DADDR Channel x Destination Address 0 32 read-write DSCR4 DMAC Channel Descriptor Address Register (ch_num = 4) 0x000000E4 32 read-write 0x00000000 DSCR Buffer Transfer Descriptor Address 2 30 read-write CTRLA4 DMAC Channel Control A Register (ch_num = 4) 0x000000E8 32 read-write 0x00000000 BTSIZE Buffer Transfer Size 0 16 read-write SCSIZE Source Chunk Transfer Size. 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 DCSIZE Destination Chunk Transfer Size 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 SRC_WIDTH Transfer Width for the Source 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH Transfer Width for the Destination 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE Current Descriptor Stop Command and Transfer Completed Memory Indicator 31 1 read-write CTRLB4 DMAC Channel Control B Register (ch_num = 4) 0x000000EC 32 read-write 0x00000000 SRC_DSCR Source Address Descriptor 16 1 read-write FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. 1 DST_DSCR Destination Address Descriptor 20 1 read-write FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. 1 FC Flow Control 21 2 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 SRC_INCR Incrementing, Decrementing or Fixed Address for the Source 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR Incrementing, Decrementing or Fixed Address for the Destination 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN Interrupt Enable Not 30 1 read-write CFG4 DMAC Channel Configuration Register (ch_num = 4) 0x000000F0 32 read-write 0x01000000 SRC_PER Source with Peripheral identifier 0 4 read-write DST_PER Destination with Peripheral identifier 4 4 read-write SRC_H2SEL Software or Hardware Selection for the Source 9 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 DST_H2SEL Software or Hardware Selection for the Destination 13 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 SOD Stop On Done 16 1 read-write DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 0 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 1 LOCK_IF Interface Lock 20 1 read-write DISABLE Interface Lock capability is disabled 0 ENABLE Interface Lock capability is enabled 1 LOCK_B Bus Lock 21 1 read-write DISABLE AHB Bus Locking capability is disabled. 0 LOCK_IF_L Master Interface Arbiter Lock 22 1 read-write CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 0 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. 1 AHB_PROT AHB Protection 24 3 read-write FIFOCFG FIFO Configuration 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 SADDR5 DMAC Channel Source Address Register (ch_num = 5) 0x00000104 32 read-write 0x00000000 SADDR Channel x Source Address 0 32 read-write DADDR5 DMAC Channel Destination Address Register (ch_num = 5) 0x00000108 32 read-write 0x00000000 DADDR Channel x Destination Address 0 32 read-write DSCR5 DMAC Channel Descriptor Address Register (ch_num = 5) 0x0000010C 32 read-write 0x00000000 DSCR Buffer Transfer Descriptor Address 2 30 read-write CTRLA5 DMAC Channel Control A Register (ch_num = 5) 0x00000110 32 read-write 0x00000000 BTSIZE Buffer Transfer Size 0 16 read-write SCSIZE Source Chunk Transfer Size. 16 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 DCSIZE Destination Chunk Transfer Size 20 3 read-write CHK_1 1 data transferred 0x0 CHK_4 4 data transferred 0x1 CHK_8 8 data transferred 0x2 CHK_16 16 data transferred 0x3 SRC_WIDTH Transfer Width for the Source 24 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DST_WIDTH Transfer Width for the Destination 28 2 read-write BYTE the transfer size is set to 8-bit width 0x0 HALF_WORD the transfer size is set to 16-bit width 0x1 WORD the transfer size is set to 32-bit width 0x2 DONE Current Descriptor Stop Command and Transfer Completed Memory Indicator 31 1 read-write CTRLB5 DMAC Channel Control B Register (ch_num = 5) 0x00000114 32 read-write 0x00000000 SRC_DSCR Source Address Descriptor 16 1 read-write FETCH_FROM_MEM Source address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the source. 1 DST_DSCR Destination Address Descriptor 20 1 read-write FETCH_FROM_MEM Destination address is updated when the descriptor is fetched from the memory. 0 FETCH_DISABLE Buffer Descriptor Fetch operation is disabled for the destination. 1 FC Flow Control 21 2 read-write MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller 0x0 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller 0x1 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller 0x2 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller 0x3 SRC_INCR Incrementing, Decrementing or Fixed Address for the Source 24 2 read-write INCREMENTING The source address is incremented 0x0 DECREMENTING The source address is decremented 0x1 FIXED The source address remains unchanged 0x2 DST_INCR Incrementing, Decrementing or Fixed Address for the Destination 28 2 read-write INCREMENTING The destination address is incremented 0x0 DECREMENTING The destination address is decremented 0x1 FIXED The destination address remains unchanged 0x2 IEN Interrupt Enable Not 30 1 read-write CFG5 DMAC Channel Configuration Register (ch_num = 5) 0x00000118 32 read-write 0x01000000 SRC_PER Source with Peripheral identifier 0 4 read-write DST_PER Destination with Peripheral identifier 4 4 read-write SRC_H2SEL Software or Hardware Selection for the Source 9 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 DST_H2SEL Software or Hardware Selection for the Destination 13 1 read-write SW Software handshaking interface is used to trigger a transfer request. 0 HW Hardware handshaking interface is used to trigger a transfer request. 1 SOD Stop On Done 16 1 read-write DISABLE STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 0 ENABLE STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 1 LOCK_IF Interface Lock 20 1 read-write DISABLE Interface Lock capability is disabled 0 ENABLE Interface Lock capability is enabled 1 LOCK_B Bus Lock 21 1 read-write DISABLE AHB Bus Locking capability is disabled. 0 LOCK_IF_L Master Interface Arbiter Lock 22 1 read-write CHUNK The Master Interface Arbiter is locked by the channel x for a chunk transfer. 0 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer. 1 AHB_PROT AHB Protection 24 3 read-write FIFOCFG FIFO Configuration 28 2 read-write ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 0x0 HALF_CFG When half FIFO size is available/filled, a source/destination request is serviced. 0x1 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the request is serviced. 0x2 WPMR DMAC Write Protect Mode Register 0x000001E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x444D41 WPSR DMAC Write Protect Status Register 0x000001E8 32 read-only 0x00000000 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only DACC 6461F Digital-to-Analog Converter Controller DACC_ 0x400C8000 0 0x4000 registers DACC 38 CR Control Register 0x00000000 32 write-only SWRST Software Reset 0 1 write-only MR Mode Register 0x00000004 32 read-write 0x00000000 TRGEN Trigger Enable 0 1 read-write DIS External trigger mode disabled. DACC in free running mode. 0 EN External trigger mode enabled. 1 TRGSEL Trigger Selection 1 3 read-write WORD Word Transfer 4 1 read-write HALF Half-Word transfer 0 WORD Word Transfer 1 SLEEP Sleep Mode 5 1 read-write FASTWKUP Fast Wake up Mode 6 1 read-write REFRESH Refresh Period 8 8 read-write USER_SEL User Channel Selection 16 2 read-write CHANNEL0 Channel 0 0 CHANNEL1 Channel 1 1 TAG Tag Selection Mode 20 1 read-write DIS Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. 0 EN Tag selection mode enabled 1 MAXS Max Speed Mode 21 1 read-write NORMAL Normal Mode 0 MAXIMUM Max Speed Mode enabled 1 STARTUP Startup Time Selection 24 6 read-write 0 0 periods of DACClock 0x0 8 8 periods of DACClock 0x1 16 16 periods of DACClock 0x2 24 24 periods of DACClock 0x3 64 64 periods of DACClock 0x4 80 80 periods of DACClock 0x5 96 96 periods of DACClock 0x6 112 112 periods of DACClock 0x7 512 512 periods of DACClock 0x8 576 576 periods of DACClock 0x9 640 640 periods of DACClock 0xA 704 704 periods of DACClock 0xB 768 768 periods of DACClock 0xC 832 832 periods of DACClock 0xD 896 896 periods of DACClock 0xE 960 960 periods of DACClock 0xF 1024 1024 periods of DACClock 0x10 1088 1088 periods of DACClock 0x11 1152 1152 periods of DACClock 0x12 1216 1216 periods of DACClock 0x13 1280 1280 periods of DACClock 0x14 1344 1344 periods of DACClock 0x15 1408 1408 periods of DACClock 0x16 1472 1472 periods of DACClock 0x17 1536 1536 periods of DACClock 0x18 1600 1600 periods of DACClock 0x19 1664 1664 periods of DACClock 0x1A 1728 1728 periods of DACClock 0x1B 1792 1792 periods of DACClock 0x1C 1856 1856 periods of DACClock 0x1D 1920 1920 periods of DACClock 0x1E 1984 1984 periods of DACClock 0x1F CHER Channel Enable Register 0x00000010 32 write-only CH0 Channel 0 Enable 0 1 write-only CH1 Channel 1 Enable 1 1 write-only CHDR Channel Disable Register 0x00000014 32 write-only CH0 Channel 0 Disable 0 1 write-only CH1 Channel 1 Disable 1 1 write-only CHSR Channel Status Register 0x00000018 32 read-only 0x00000000 CH0 Channel 0 Status 0 1 read-only CH1 Channel 1 Status 1 1 read-only CDR Conversion Data Register 0x00000020 32 write-only 0x00000000 DATA Data to Convert 0 32 write-only IER Interrupt Enable Register 0x00000024 32 write-only TXRDY Transmit Ready Interrupt Enable 0 1 write-only EOC End of Conversion Interrupt Enable 1 1 write-only ENDTX End of Transmit Buffer Interrupt Enable 2 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 3 1 write-only IDR Interrupt Disable Register 0x00000028 32 write-only TXRDY Transmit Ready Interrupt Disable. 0 1 write-only EOC End of Conversion Interrupt Disable 1 1 write-only ENDTX End of Transmit Buffer Interrupt Disable 2 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 3 1 write-only IMR Interrupt Mask Register 0x0000002C 32 read-only 0x00000000 TXRDY Transmit Ready Interrupt Mask 0 1 read-only EOC End of Conversion Interrupt Mask 1 1 read-only ENDTX End of Transmit Buffer Interrupt Mask 2 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 3 1 read-only ISR Interrupt Status Register 0x00000030 32 read-only 0x00000000 TXRDY Transmit Ready Interrupt Flag 0 1 read-only EOC End of Conversion Interrupt Flag 1 1 read-only ENDTX End of DMA Interrupt Flag 2 1 read-only TXBUFE Transmit Buffer Empty 3 1 read-only ACR Analog Current Register 0x00000094 32 read-write 0x00000000 IBCTLCH0 Analog Output Current Control 0 2 read-write IBCTLCH1 Analog Output Current Control 2 2 read-write IBCTLDACCORE Bias Current Control for DAC Core 8 2 read-write WPMR Write Protect Mode register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status register 0x000000E8 32 read-only 0x00000000 WPROTERR Write protection error 0 1 read-only WPROTADDR Write protection error address 8 8 read-only TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only SMC 6411F Static Memory Controller EBI SMC_ 0x400E0000 0 0x200 registers CFG SMC NFC Configuration Register 0x00000000 32 read-write 0x00000000 PAGESIZE Page Size of the NAND Flash Device 0 2 read-write PS512 Main area 512 Bytes 0x0 PS1024 Main area 1024 Bytes 0x1 PS2048 Main area 2048 Bytes 0x2 PS4096 Main area 4096 Bytes 0x3 WSPARE Write Spare Area 8 1 read-write RSPARE Read Spare Area 9 1 read-write EDGECTRL Rising/Falling Edge Detection Control 12 1 read-write RBEDGE Ready/Busy Signal Edge Detection 13 1 read-write DTOCYC Data Timeout Cycle Number 16 4 read-write DTOMUL Data Timeout Multiplier 20 3 read-write X1 DTOCYC 0x0 X16 DTOCYC x 16 0x1 X128 DTOCYC x 128 0x2 X256 DTOCYC x 256 0x3 X1024 DTOCYC x 1024 0x4 X4096 DTOCYC x 4096 0x5 X65536 DTOCYC x 65536 0x6 X1048576 DTOCYC x 1048576 0x7 CTRL SMC NFC Control Register 0x00000004 32 write-only 0x00000000 NFCEN NAND Flash Controller Enable 0 1 write-only NFCDIS NAND Flash Controller Disable 1 1 write-only SR SMC NFC Status Register 0x00000008 32 read-only 0x00000000 SMCSTS NAND Flash Controller status (this field cannot be reset) 0 1 read-only RB_RISE Selected Ready Busy Rising Edge Detected 4 1 read-only RB_FALL Selected Ready Busy Falling Edge Detected 5 1 read-only NFCBUSY NFC Busy (this field cannot be reset) 8 1 read-only NFCWR NFC Write/Read Operation (this field cannot be reset) 11 1 read-only NFCSID NFC Chip Select ID (this field cannot be reset) 12 3 read-only XFRDONE NFC Data Transfer Terminated 16 1 read-only CMDDONE Command Done 17 1 read-only DTOE Data Timeout Error 20 1 read-only UNDEF Undefined Area Error 21 1 read-only AWB Accessing While Busy 22 1 read-only NFCASE NFC Access Size Error 23 1 read-only RB_EDGE0 Ready/Busy Line 0 Edge Detected 24 1 read-only IER SMC NFC Interrupt Enable Register 0x0000000C 32 write-only 0x00000000 RB_RISE Ready Busy Rising Edge Detection Interrupt Enable 4 1 write-only RB_FALL Ready Busy Falling Edge Detection Interrupt Enable 5 1 write-only XFRDONE Transfer Done Interrupt Enable 16 1 write-only CMDDONE Command Done Interrupt Enable 17 1 write-only DTOE Data Timeout Error Interrupt Enable 20 1 write-only UNDEF Undefined Area Access Interrupt Enable 21 1 write-only AWB Accessing While Busy Interrupt Enable 22 1 write-only NFCASE NFC Access Size Error Interrupt Enable 23 1 write-only RB_EDGE0 Ready/Busy Line 0 Interrupt Enable 24 1 write-only IDR SMC NFC Interrupt Disable Register 0x00000010 32 write-only 0x00000000 RB_RISE Ready Busy Rising Edge Detection Interrupt Disable 4 1 write-only RB_FALL Ready Busy Falling Edge Detection Interrupt Disable 5 1 write-only XFRDONE Transfer Done Interrupt Disable 16 1 write-only CMDDONE Command Done Interrupt Disable 17 1 write-only DTOE Data Timeout Error Interrupt Disable 20 1 write-only UNDEF Undefined Area Access Interrupt Disable 21 1 write-only AWB Accessing While Busy Interrupt Disable 22 1 write-only NFCASE NFC Access Size Error Interrupt Disable 23 1 write-only RB_EDGE0 Ready/Busy Line 0 Interrupt Disable 24 1 write-only IMR SMC NFC Interrupt Mask Register 0x00000014 32 read-only 0x00000000 RB_RISE Ready Busy Rising Edge Detection Interrupt Mask 4 1 read-only RB_FALL Ready Busy Falling Edge Detection Interrupt Mask 5 1 read-only XFRDONE Transfer Done Interrupt Mask 16 1 read-only CMDDONE Command Done Interrupt Mask 17 1 read-only DTOE Data Timeout Error Interrupt Mask 20 1 read-only UNDEF Undefined Area Access Interrupt Mask5 21 1 read-only AWB Accessing While Busy Interrupt Mask 22 1 read-only NFCASE NFC Access Size Error Interrupt Mask 23 1 read-only RB_EDGE0 Ready/Busy Line 0 Interrupt Mask 24 1 read-only ADDR SMC NFC Address Cycle Zero Register 0x00000018 32 read-write 0x00000000 ADDR_CYCLE0 NAND Flash Array Address cycle 0 0 8 read-write BANK SMC Bank Address Register 0x0000001C 32 read-write 0x00000000 BANK Bank Identifier 0 3 read-write ECC_CTRL SMC ECC Control Register 0x00000020 32 write-only 0x00000000 RST Reset ECC 0 1 write-only SWRST Software Reset 1 1 write-only ECC_MD SMC ECC Mode Register 0x00000024 32 read-write 0x00000000 ECC_PAGESIZE ECC Page Size 0 2 read-write PS512 Main area 512 Words 0x0 PS1024 Main area 1024 Words 0x1 PS2048 Main area 2048 Words 0x2 PS4096 Main area 4096 Words 0x3 TYPCORREC Type of Correction 4 2 read-write CPAGE 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash) 0x0 C256B 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) 0x1 C512B 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) 0x2 ECC_SR1 SMC ECC Status 1 Register 0x00000028 32 read-only 0x00000000 RECERR0 Recoverable Error 0 1 read-only ECCERR0 ECC Error 1 1 read-only MULERR0 Multiple Error 2 1 read-only RECERR1 Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes 4 1 read-only ECCERR1 ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes 5 1 read-only MULERR1 Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes 6 1 read-only RECERR2 Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes 8 1 read-only ECCERR2 ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes 9 1 read-only MULERR2 Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes 10 1 read-only RECERR3 Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes 12 1 read-only ECCERR3 ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes 13 1 read-only MULERR3 Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes 14 1 read-only RECERR4 Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes 16 1 read-only ECCERR4 ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes 17 1 read-only MULERR4 Multiple Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes 18 1 read-only RECERR5 Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes 20 1 read-only ECCERR5 ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes 21 1 read-only MULERR5 Multiple Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes 22 1 read-only RECERR6 Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes 24 1 read-only ECCERR6 ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes 25 1 read-only MULERR6 Multiple Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes 26 1 read-only RECERR7 Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes 28 1 read-only ECCERR7 ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes 29 1 read-only MULERR7 Multiple Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes 30 1 read-only ECC_PR0 SMC ECC Parity 0 Register 0x0000002C 32 read-only 0x00000000 BITADDR Bit Address 0 4 read-only WORDADDR Word Address 4 12 read-only ECC_PR0_W9BIT SMC ECC Parity 0 Register W9BIT 0x0000002C 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only NPARITY Parity N 12 12 read-only ECC_PR0_W8BIT SMC ECC Parity 0 Register W8BIT 0x0000002C 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR1 SMC ECC parity 1 Register 0x00000030 32 read-only 0x00000000 NPARITY Parity N 0 16 read-only ECC_PR1_W9BIT SMC ECC parity 1 Register W9BIT 0x00000030 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only NPARITY Parity N 12 12 read-only ECC_PR1_W8BIT SMC ECC parity 1 Register W8BIT 0x00000030 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_SR2 SMC ECC status 2 Register 0x00000034 32 read-only 0x00000000 RECERR8 Recoverable Error in the page between the 2048th and the 2303rd bytes 0 1 read-only ECCERR8 ECC Error in the page between the 2048th and the 2303rd bytes 1 1 read-only MULERR8 Multiple Error in the page between the 2048th and the 2303rd bytes 2 1 read-only RECERR9 Recoverable Error in the page between the 2304th and the 2559th bytes 4 1 read-only ECCERR9 ECC Error in the page between the 2304th and the 2559th bytes 5 1 read-only MULERR9 Multiple Error in the page between the 2304th and the 2559th bytes 6 1 read-only RECERR10 Recoverable Error in the page between the 2560th and the 2815th bytes 8 1 read-only ECCERR10 ECC Error in the page between the 2560th and the 2815th bytes 9 1 read-only MULERR10 Multiple Error in the page between the 2560th and the 2815th bytes 10 1 read-only RECERR11 Recoverable Error in the page between the 2816th and the 3071st bytes 12 1 read-only ECCERR11 ECC Error in the page between the 2816th and the 3071st bytes 13 1 read-only MULERR11 Multiple Error in the page between the 2816th and the 3071st bytes 14 1 read-only RECERR12 Recoverable Error in the page between the 3072nd and the 3327th bytes 16 1 read-only ECCERR12 ECC Error in the page between the 3072nd and the 3327th bytes 17 1 read-only MULERR12 Multiple Error in the page between the 3072nd and the 3327th bytes 18 1 read-only RECERR13 Recoverable Error in the page between the 3328th and the 3583rd bytes 20 1 read-only ECCERR13 ECC Error in the page between the 3328th and the 3583rd bytes 21 1 read-only MULERR13 Multiple Error in the page between the 3328th and the 3583rd bytes 22 1 read-only RECERR14 Recoverable Error in the page between the 3584th and the 3839th bytes 24 1 read-only ECCERR14 ECC Error in the page between the 3584th and the 3839th bytes 25 1 read-only MULERR14 Multiple Error in the page between the 3584th and the 3839th bytes 26 1 read-only RECERR15 Recoverable Error in the page between the 3840th and the 4095th bytes 28 1 read-only ECCERR15 ECC Error in the page between the 3840th and the 4095th bytes 29 1 read-only MULERR15 Multiple Error in the page between the 3840th and the 4095th bytes 30 1 read-only ECC_PR2 SMC ECC parity 2 Register 0x00000038 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only NPARITY Parity N 12 12 read-only ECC_PR2_W8BIT SMC ECC parity 2 Register W8BIT 0x00000038 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR3 SMC ECC parity 3 Register 0x0000003C 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only NPARITY Parity N 12 12 read-only ECC_PR3_W8BIT SMC ECC parity 3 Register W8BIT 0x0000003C 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR4 SMC ECC parity 4 Register 0x00000040 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only NPARITY Parity N 12 12 read-only ECC_PR4_W8BIT SMC ECC parity 4 Register W8BIT 0x00000040 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR5 SMC ECC parity 5 Register 0x00000044 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only NPARITY Parity N 12 12 read-only ECC_PR5_W8BIT SMC ECC parity 5 Register W8BIT 0x00000044 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR6 SMC ECC parity 6 Register 0x00000048 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only NPARITY Parity N 12 12 read-only ECC_PR6_W8BIT SMC ECC parity 6 Register W8BIT 0x00000048 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR7 SMC ECC parity 7 Register 0x0000004C 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes 3 9 read-only NPARITY Parity N 12 12 read-only ECC_PR7_W8BIT SMC ECC parity 7 Register W8BIT 0x0000004C 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR8 SMC ECC parity 8 Register 0x00000050 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR9 SMC ECC parity 9 Register 0x00000054 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR10 SMC ECC parity 10 Register 0x00000058 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR11 SMC ECC parity 11 Register 0x0000005C 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR12 SMC ECC parity 12 Register 0x00000060 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR13 SMC ECC parity 13 Register 0x00000064 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR14 SMC ECC parity 14 Register 0x00000068 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only ECC_PR15 SMC ECC parity 15 Register 0x0000006C 32 read-only 0x00000000 BITADDR Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 0 3 read-only WORDADDR Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes 3 8 read-only NPARITY Parity N 12 11 read-only SETUP0 SMC Setup Register (CS_number = 0) 0x00000070 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write PULSE0 SMC Pulse Register (CS_number = 0) 0x00000074 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE0 SMC Cycle Register (CS_number = 0) 0x00000078 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write TIMINGS0 SMC Timings Register (CS_number = 0) 0x0000007C 32 read-write 0x00000000 TCLR CLE to REN Low Delay 0 4 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write NFSEL NAND Flash Selection 31 1 read-write MODE0 SMC Mode Register (CS_number = 0) 0x00000080 32 read-write 0x10000003 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write SETUP1 SMC Setup Register (CS_number = 1) 0x00000084 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write PULSE1 SMC Pulse Register (CS_number = 1) 0x00000088 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE1 SMC Cycle Register (CS_number = 1) 0x0000008C 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write TIMINGS1 SMC Timings Register (CS_number = 1) 0x00000090 32 read-write 0x00000000 TCLR CLE to REN Low Delay 0 4 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write NFSEL NAND Flash Selection 31 1 read-write MODE1 SMC Mode Register (CS_number = 1) 0x00000094 32 read-write 0x10000003 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write SETUP2 SMC Setup Register (CS_number = 2) 0x00000098 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write PULSE2 SMC Pulse Register (CS_number = 2) 0x0000009C 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE2 SMC Cycle Register (CS_number = 2) 0x000000A0 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write TIMINGS2 SMC Timings Register (CS_number = 2) 0x000000A4 32 read-write 0x00000000 TCLR CLE to REN Low Delay 0 4 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write NFSEL NAND Flash Selection 31 1 read-write MODE2 SMC Mode Register (CS_number = 2) 0x000000A8 32 read-write 0x10000003 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write SETUP3 SMC Setup Register (CS_number = 3) 0x000000AC 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write PULSE3 SMC Pulse Register (CS_number = 3) 0x000000B0 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE3 SMC Cycle Register (CS_number = 3) 0x000000B4 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write TIMINGS3 SMC Timings Register (CS_number = 3) 0x000000B8 32 read-write 0x00000000 TCLR CLE to REN Low Delay 0 4 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write NFSEL NAND Flash Selection 31 1 read-write MODE3 SMC Mode Register (CS_number = 3) 0x000000BC 32 read-write 0x10000003 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write SETUP4 SMC Setup Register (CS_number = 4) 0x000000C0 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write PULSE4 SMC Pulse Register (CS_number = 4) 0x000000C4 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE4 SMC Cycle Register (CS_number = 4) 0x000000C8 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write TIMINGS4 SMC Timings Register (CS_number = 4) 0x000000CC 32 read-write 0x00000000 TCLR CLE to REN Low Delay 0 4 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write NFSEL NAND Flash Selection 31 1 read-write MODE4 SMC Mode Register (CS_number = 4) 0x000000D0 32 read-write 0x10000003 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write SETUP5 SMC Setup Register (CS_number = 5) 0x000000D4 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write PULSE5 SMC Pulse Register (CS_number = 5) 0x000000D8 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE5 SMC Cycle Register (CS_number = 5) 0x000000DC 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write TIMINGS5 SMC Timings Register (CS_number = 5) 0x000000E0 32 read-write 0x00000000 TCLR CLE to REN Low Delay 0 4 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write NFSEL NAND Flash Selection 31 1 read-write MODE5 SMC Mode Register (CS_number = 5) 0x000000E4 32 read-write 0x10000003 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write SETUP6 SMC Setup Register (CS_number = 6) 0x000000E8 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write PULSE6 SMC Pulse Register (CS_number = 6) 0x000000EC 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE6 SMC Cycle Register (CS_number = 6) 0x000000F0 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write TIMINGS6 SMC Timings Register (CS_number = 6) 0x000000F4 32 read-write 0x00000000 TCLR CLE to REN Low Delay 0 4 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write NFSEL NAND Flash Selection 31 1 read-write MODE6 SMC Mode Register (CS_number = 6) 0x000000F8 32 read-write 0x10000003 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write SETUP7 SMC Setup Register (CS_number = 7) 0x000000FC 32 read-write 0x01010101 NWE_SETUP NWE Setup Length 0 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write PULSE7 SMC Pulse Register (CS_number = 7) 0x00000100 32 read-write 0x01010101 NWE_PULSE NWE Pulse Length 0 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write CYCLE7 SMC Cycle Register (CS_number = 7) 0x00000104 32 read-write 0x00030003 NWE_CYCLE Total Write Cycle Length 0 9 read-write NRD_CYCLE Total Read Cycle Length 16 9 read-write TIMINGS7 SMC Timings Register (CS_number = 7) 0x00000108 32 read-write 0x00000000 TCLR CLE to REN Low Delay 0 4 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write RBNSEL Ready/Busy Line Selection 28 3 read-write NFSEL NAND Flash Selection 31 1 read-write MODE7 SMC Mode Register (CS_number = 7) 0x0000010C 32 read-write 0x10000003 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal. 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled 0x0 FROZEN Frozen Mode 0x2 READY Ready Mode 0x3 BAT Byte Access Type 8 1 read-write DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write OCMS SMC OCMS Register 0x00000110 32 read-write 0x00000000 SMSE Static Memory Controller Scrambling Enable 0 1 read-write SRSE SRAM Scrambling Enable 1 1 read-write KEY1 SMC OCMS KEY1 Register 0x00000114 32 write-only 0x00000000 KEY1 Off Chip Memory Scrambling (OCMS) Key Part 1 0 32 write-only KEY2 SMC OCMS KEY2 Register 0x00000118 32 write-only 0x00000000 KEY2 Off Chip Memory Scrambling (OCMS) Key Part 2 0 32 write-only WPCR Write Protection Control Register 0x000001E4 32 write-only 0x00000000 WP_EN Write Protection Enable 0 1 write-only WP_KEY Write Protection KEY Password 8 24 write-only PASSWD Writing any other value in this field aborts the write operation of the WP_EN bit. Always reads as 0. 0x534D43 WPSR Write Protection Status Register 0x000001E8 32 read-only 0x00000000 WP_VS Write Protection Violation Status 0 4 read-only WP_VSRC Write Protection Violation Source 8 16 read-only MATRIX 11060A AHB Bus Matrix 0x400E0400 0 0x200 registers 6 4 0-5 MATRIX_MCFG[%s] Master Configuration Register 0x00000000 32 read-write ULBT Undefined Length Burst Type 0 3 read-write 9 4 0-8 MATRIX_SCFG[%s] Slave Configuration Register 0x00000040 32 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write DEFMSTR_TYPE Default Master Type 16 2 read-write FIXED_DEFMSTR Fixed Default Master 18 3 read-write ARBT Arbitration Type 24 2 read-write MATRIX_PRAS0 Priority Register A for Slave 0 0x00000080 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write MATRIX_PRAS1 Priority Register A for Slave 1 0x00000088 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write MATRIX_PRAS2 Priority Register A for Slave 2 0x00000090 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write MATRIX_PRAS3 Priority Register A for Slave 3 0x00000098 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write MATRIX_PRAS4 Priority Register A for Slave 4 0x000000A0 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write MATRIX_PRAS5 Priority Register A for Slave 5 0x000000A8 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write MATRIX_PRAS6 Priority Register A for Slave 6 0x000000B0 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write MATRIX_PRAS7 Priority Register A for Slave 7 0x000000B8 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write MATRIX_PRAS8 Priority Register A for Slave 8 0x000000C0 32 read-write 0x00000000 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write MATRIX_MRCR Master Remap Control Register 0x00000100 32 read-write 0x00000000 RCB0 Remap Command Bit for AHB Master 0 0 1 read-write RCB1 Remap Command Bit for AHB Master 1 1 1 read-write RCB2 Remap Command Bit for AHB Master 2 2 1 read-write RCB3 Remap Command Bit for AHB Master 3 3 1 read-write RCB4 Remap Command Bit for AHB Master 4 4 2 read-write RCB5 Remap Command Bit for AHB Master 5 6 1 read-write CCFG_SYSIO System I/O Configuration register 0x00000114 32 read-write 0x00000000 SYSIO12 PC0 or ERASE Assignment 12 1 read-write MATRIX_WPMR Write Protect Mode Register 0x000001E4 32 read-write 0x00000000 WPEN Write Protect ENable 0 1 read-write WPKEY Write Protect KEY (Write-only) 8 24 read-write MATRIX_WPSR Write Protect Status Register 0x000001E8 32 read-only 0x00000000 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PMC 11116I Power Management Controller 0x400E0600 0 0x140 registers PMC 5 PMC_SCER System Clock Enable Register 0x00000000 32 write-only UOTGCLK Enable USB OTG Clock (48 MHz, USB_48M) for UTMI 5 1 write-only PCK0 Programmable Clock 0 Output Enable 8 1 write-only PCK1 Programmable Clock 1 Output Enable 9 1 write-only PCK2 Programmable Clock 2 Output Enable 10 1 write-only PMC_SCDR System Clock Disable Register 0x00000004 32 write-only UOTGCLK Disable USB OTG Clock (48 MHz, USB_48M) for UTMI 5 1 write-only PCK0 Programmable Clock 0 Output Disable 8 1 write-only PCK1 Programmable Clock 1 Output Disable 9 1 write-only PCK2 Programmable Clock 2 Output Disable 10 1 write-only PMC_SCSR System Clock Status Register 0x00000008 32 read-only 0x00000001 UOTGCLK USB OTG Clock (48 MHz, USB_48M) Clock Status 5 1 read-only PCK0 Programmable Clock 0 Output Status 8 1 read-only PCK1 Programmable Clock 1 Output Status 9 1 read-only PCK2 Programmable Clock 2 Output Status 10 1 read-only PMC_PCER0 Peripheral Clock Enable Register 0 0x00000010 32 write-only PID8 Peripheral Clock 8 Enable 8 1 write-only PID9 Peripheral Clock 9 Enable 9 1 write-only PID10 Peripheral Clock 10 Enable 10 1 write-only PID11 Peripheral Clock 11 Enable 11 1 write-only PID12 Peripheral Clock 12 Enable 12 1 write-only PID13 Peripheral Clock 13 Enable 13 1 write-only PID14 Peripheral Clock 14 Enable 14 1 write-only PID15 Peripheral Clock 15 Enable 15 1 write-only PID16 Peripheral Clock 16 Enable 16 1 write-only PID17 Peripheral Clock 17 Enable 17 1 write-only PID18 Peripheral Clock 18 Enable 18 1 write-only PID19 Peripheral Clock 19 Enable 19 1 write-only PID20 Peripheral Clock 20 Enable 20 1 write-only PID21 Peripheral Clock 21 Enable 21 1 write-only PID22 Peripheral Clock 22 Enable 22 1 write-only PID23 Peripheral Clock 23 Enable 23 1 write-only PID24 Peripheral Clock 24 Enable 24 1 write-only PID25 Peripheral Clock 25 Enable 25 1 write-only PID26 Peripheral Clock 26 Enable 26 1 write-only PID27 Peripheral Clock 27 Enable 27 1 write-only PID28 Peripheral Clock 28 Enable 28 1 write-only PID29 Peripheral Clock 29 Enable 29 1 write-only PID30 Peripheral Clock 30 Enable 30 1 write-only PID31 Peripheral Clock 31 Enable 31 1 write-only PMC_PCDR0 Peripheral Clock Disable Register 0 0x00000014 32 write-only PID8 Peripheral Clock 8 Disable 8 1 write-only PID9 Peripheral Clock 9 Disable 9 1 write-only PID10 Peripheral Clock 10 Disable 10 1 write-only PID11 Peripheral Clock 11 Disable 11 1 write-only PID12 Peripheral Clock 12 Disable 12 1 write-only PID13 Peripheral Clock 13 Disable 13 1 write-only PID14 Peripheral Clock 14 Disable 14 1 write-only PID15 Peripheral Clock 15 Disable 15 1 write-only PID16 Peripheral Clock 16 Disable 16 1 write-only PID17 Peripheral Clock 17 Disable 17 1 write-only PID18 Peripheral Clock 18 Disable 18 1 write-only PID19 Peripheral Clock 19 Disable 19 1 write-only PID20 Peripheral Clock 20 Disable 20 1 write-only PID21 Peripheral Clock 21 Disable 21 1 write-only PID22 Peripheral Clock 22 Disable 22 1 write-only PID23 Peripheral Clock 23 Disable 23 1 write-only PID24 Peripheral Clock 24 Disable 24 1 write-only PID25 Peripheral Clock 25 Disable 25 1 write-only PID26 Peripheral Clock 26 Disable 26 1 write-only PID27 Peripheral Clock 27 Disable 27 1 write-only PID28 Peripheral Clock 28 Disable 28 1 write-only PID29 Peripheral Clock 29 Disable 29 1 write-only PID30 Peripheral Clock 30 Disable 30 1 write-only PID31 Peripheral Clock 31 Disable 31 1 write-only PMC_PCSR0 Peripheral Clock Status Register 0 0x00000018 32 read-only 0x00000000 PID8 Peripheral Clock 8 Status 8 1 read-only PID9 Peripheral Clock 9 Status 9 1 read-only PID10 Peripheral Clock 10 Status 10 1 read-only PID11 Peripheral Clock 11 Status 11 1 read-only PID12 Peripheral Clock 12 Status 12 1 read-only PID13 Peripheral Clock 13 Status 13 1 read-only PID14 Peripheral Clock 14 Status 14 1 read-only PID15 Peripheral Clock 15 Status 15 1 read-only PID16 Peripheral Clock 16 Status 16 1 read-only PID17 Peripheral Clock 17 Status 17 1 read-only PID18 Peripheral Clock 18 Status 18 1 read-only PID19 Peripheral Clock 19 Status 19 1 read-only PID20 Peripheral Clock 20 Status 20 1 read-only PID21 Peripheral Clock 21 Status 21 1 read-only PID22 Peripheral Clock 22 Status 22 1 read-only PID23 Peripheral Clock 23 Status 23 1 read-only PID24 Peripheral Clock 24 Status 24 1 read-only PID25 Peripheral Clock 25 Status 25 1 read-only PID26 Peripheral Clock 26 Status 26 1 read-only PID27 Peripheral Clock 27 Status 27 1 read-only PID28 Peripheral Clock 28 Status 28 1 read-only PID29 Peripheral Clock 29 Status 29 1 read-only PID30 Peripheral Clock 30 Status 30 1 read-only PID31 Peripheral Clock 31 Status 31 1 read-only CKGR_UCKR UTMI Clock Register 0x0000001C 32 read-write 0x10200800 UPLLEN UTMI PLL Enable 16 1 read-write UPLLCOUNT UTMI PLL Start-up Time 20 4 read-write CKGR_MOR Main Oscillator Register 0x00000020 32 read-write 0x00000008 MOSCXTEN Main Crystal Oscillator Enable 0 1 read-write MOSCXTBY Main Crystal Oscillator Bypass 1 1 read-write MOSCRCEN Main On-Chip RC Oscillator Enable 3 1 read-write MOSCRCF Main On-Chip RC Oscillator Frequency Selection 4 3 read-write 4_MHz The Fast RC Oscillator Frequency is at 4 MHz (default) 0x0 8_MHz The Fast RC Oscillator Frequency is at 8 MHz 0x1 12_MHz The Fast RC Oscillator Frequency is at 12 MHz 0x2 MOSCXTST Main Crystal Oscillator Start-up Time 8 8 read-write KEY Write Access Password 16 8 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x37 MOSCSEL Main Oscillator Selection 24 1 read-write CFDEN Clock Failure Detector Enable 25 1 read-write CKGR_MCFR Main Clock Frequency Register 0x00000024 32 read-only 0x00000000 MAINF Main Clock Frequency 0 16 read-only MAINFRDY Main Clock Ready 16 1 read-only CKGR_PLLAR PLLA Register 0x00000028 32 read-write 0x00003F00 DIVA Divider 0 8 read-write PLLACOUNT PLLA Counter 8 6 read-write MULA PLLA Multiplier 16 11 read-write ONE Must Be Set to 1 29 1 read-write PMC_MCKR Master Clock Register 0x00000030 32 read-write 0x00000001 CSS Master Clock Source Selection 0 2 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 PRES Processor Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 CLK_3 Selected clock divided by 3 0x7 PLLADIV2 PLLA Divisor by 2 12 1 read-write UPLLDIV2 13 1 read-write PMC_USB USB Clock Register 0x00000038 32 read-write 0x00000000 USBS USB Input Clock Selection 0 1 read-write USBDIV Divider for USB Clock. 8 4 read-write 3 4 0-2 PMC_PCK[%s] Programmable Clock 0 Register 0x00000040 32 read-write CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 PMC_IER Interrupt Enable Register 0x00000060 32 write-only MOSCXTS Main Crystal Oscillator Status Interrupt Enable 0 1 write-only LOCKA PLLA Lock Interrupt Enable 1 1 write-only MCKRDY Master Clock Ready Interrupt Enable 3 1 write-only LOCKU UTMI PLL Lock Interrupt Enable 6 1 write-only PCKRDY0 Programmable Clock Ready 0 Interrupt Enable 8 1 write-only PCKRDY1 Programmable Clock Ready 1 Interrupt Enable 9 1 write-only PCKRDY2 Programmable Clock Ready 2 Interrupt Enable 10 1 write-only MOSCSELS Main Oscillator Selection Status Interrupt Enable 16 1 write-only MOSCRCS Main On-Chip RC Status Interrupt Enable 17 1 write-only CFDEV Clock Failure Detector Event Interrupt Enable 18 1 write-only PMC_IDR Interrupt Disable Register 0x00000064 32 write-only MOSCXTS Main Crystal Oscillator Status Interrupt Disable 0 1 write-only LOCKA PLLA Lock Interrupt Disable 1 1 write-only MCKRDY Master Clock Ready Interrupt Disable 3 1 write-only LOCKU UTMI PLL Lock Interrupt Disable 6 1 write-only PCKRDY0 Programmable Clock Ready 0 Interrupt Disable 8 1 write-only PCKRDY1 Programmable Clock Ready 1 Interrupt Disable 9 1 write-only PCKRDY2 Programmable Clock Ready 2 Interrupt Disable 10 1 write-only MOSCSELS Main Oscillator Selection Status Interrupt Disable 16 1 write-only MOSCRCS Main On-Chip RC Status Interrupt Disable 17 1 write-only CFDEV Clock Failure Detector Event Interrupt Disable 18 1 write-only PMC_SR Status Register 0x00000068 32 read-only 0x00010008 MOSCXTS Main XTAL Oscillator Status 0 1 read-only LOCKA PLLA Lock Status 1 1 read-only MCKRDY Master Clock Status 3 1 read-only LOCKU UTMI PLL Lock Status 6 1 read-only OSCSELS Slow Clock Oscillator Selection 7 1 read-only PCKRDY0 Programmable Clock Ready Status 8 1 read-only PCKRDY1 Programmable Clock Ready Status 9 1 read-only PCKRDY2 Programmable Clock Ready Status 10 1 read-only MOSCSELS Main Oscillator Selection Status 16 1 read-only MOSCRCS Main On-Chip RC Oscillator Status 17 1 read-only CFDEV Clock Failure Detector Event 18 1 read-only CFDS Clock Failure Detector Status 19 1 read-only FOS Clock Failure Detector Fault Output Status 20 1 read-only PMC_IMR Interrupt Mask Register 0x0000006C 32 read-only 0x00000000 MOSCXTS Main Crystal Oscillator Status Interrupt Mask 0 1 read-only LOCKA PLLA Lock Interrupt Mask 1 1 read-only MCKRDY Master Clock Ready Interrupt Mask 3 1 read-only LOCKU UTMI PLL Lock Interrupt Mask 6 1 read-only PCKRDY0 Programmable Clock Ready 0 Interrupt Mask 8 1 read-only PCKRDY1 Programmable Clock Ready 1 Interrupt Mask 9 1 read-only PCKRDY2 Programmable Clock Ready 2 Interrupt Mask 10 1 read-only MOSCSELS Main Oscillator Selection Status Interrupt Mask 16 1 read-only MOSCRCS Main On-Chip RC Status Interrupt Mask 17 1 read-only CFDEV Clock Failure Detector Event Interrupt Mask 18 1 read-only PMC_FSMR Fast Start-up Mode Register 0x00000070 32 read-write 0x00000000 FSTT0 Fast Start-up Input Enable 0 0 1 read-write FSTT1 Fast Start-up Input Enable 1 1 1 read-write FSTT2 Fast Start-up Input Enable 2 2 1 read-write FSTT3 Fast Start-up Input Enable 3 3 1 read-write FSTT4 Fast Start-up Input Enable 4 4 1 read-write FSTT5 Fast Start-up Input Enable 5 5 1 read-write FSTT6 Fast Start-up Input Enable 6 6 1 read-write FSTT7 Fast Start-up Input Enable 7 7 1 read-write FSTT8 Fast Start-up Input Enable 8 8 1 read-write FSTT9 Fast Start-up Input Enable 9 9 1 read-write FSTT10 Fast Start-up Input Enable 10 10 1 read-write FSTT11 Fast Start-up Input Enable 11 11 1 read-write FSTT12 Fast Start-up Input Enable 12 12 1 read-write FSTT13 Fast Start-up Input Enable 13 13 1 read-write FSTT14 Fast Start-up Input Enable 14 14 1 read-write FSTT15 Fast Start-up Input Enable 15 15 1 read-write RTTAL RTT Alarm Enable 16 1 read-write RTCAL RTC Alarm Enable 17 1 read-write USBAL USB Alarm Enable 18 1 read-write LPM Low Power Mode 20 1 read-write PMC_FSPR Fast Start-up Polarity Register 0x00000074 32 read-write 0x00000000 FSTP0 Fast Start-up Input Polarityx 0 1 read-write FSTP1 Fast Start-up Input Polarityx 1 1 read-write FSTP2 Fast Start-up Input Polarityx 2 1 read-write FSTP3 Fast Start-up Input Polarityx 3 1 read-write FSTP4 Fast Start-up Input Polarityx 4 1 read-write FSTP5 Fast Start-up Input Polarityx 5 1 read-write FSTP6 Fast Start-up Input Polarityx 6 1 read-write FSTP7 Fast Start-up Input Polarityx 7 1 read-write FSTP8 Fast Start-up Input Polarityx 8 1 read-write FSTP9 Fast Start-up Input Polarityx 9 1 read-write FSTP10 Fast Start-up Input Polarityx 10 1 read-write FSTP11 Fast Start-up Input Polarityx 11 1 read-write FSTP12 Fast Start-up Input Polarityx 12 1 read-write FSTP13 Fast Start-up Input Polarityx 13 1 read-write FSTP14 Fast Start-up Input Polarityx 14 1 read-write FSTP15 Fast Start-up Input Polarityx 15 1 read-write PMC_FOCR Fault Output Clear Register 0x00000078 32 write-only FOCLR Fault Output Clear 0 1 write-only PMC_WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x504D43 PMC_WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PMC_PCER1 Peripheral Clock Enable Register 1 0x00000100 32 write-only PID32 Peripheral Clock 32 Enable 0 1 write-only PID33 Peripheral Clock 33 Enable 1 1 write-only PID34 Peripheral Clock 34 Enable 2 1 write-only PID35 Peripheral Clock 35 Enable 3 1 write-only PID36 Peripheral Clock 36 Enable 4 1 write-only PID37 Peripheral Clock 37 Enable 5 1 write-only PID38 Peripheral Clock 38 Enable 6 1 write-only PID39 Peripheral Clock 39 Enable 7 1 write-only PID40 Peripheral Clock 40 Enable 8 1 write-only PID41 Peripheral Clock 41 Enable 9 1 write-only PID42 Peripheral Clock 42 Enable 10 1 write-only PID43 Peripheral Clock 43 Enable 11 1 write-only PID44 Peripheral Clock 44 Enable 12 1 write-only PMC_PCDR1 Peripheral Clock Disable Register 1 0x00000104 32 write-only PID32 Peripheral Clock 32 Disable 0 1 write-only PID33 Peripheral Clock 33 Disable 1 1 write-only PID34 Peripheral Clock 34 Disable 2 1 write-only PID35 Peripheral Clock 35 Disable 3 1 write-only PID36 Peripheral Clock 36 Disable 4 1 write-only PID37 Peripheral Clock 37 Disable 5 1 write-only PID38 Peripheral Clock 38 Disable 6 1 write-only PID39 Peripheral Clock 39 Disable 7 1 write-only PID40 Peripheral Clock 40 Disable 8 1 write-only PID41 Peripheral Clock 41 Disable 9 1 write-only PID42 Peripheral Clock 42 Disable 10 1 write-only PID43 Peripheral Clock 43 Disable 11 1 write-only PID44 Peripheral Clock 44 Disable 12 1 write-only PMC_PCSR1 Peripheral Clock Status Register 1 0x00000108 32 read-only 0x00000000 PID32 Peripheral Clock 32 Status 0 1 read-only PID33 Peripheral Clock 33 Status 1 1 read-only PID34 Peripheral Clock 34 Status 2 1 read-only PID35 Peripheral Clock 35 Status 3 1 read-only PID36 Peripheral Clock 36 Status 4 1 read-only PID37 Peripheral Clock 37 Status 5 1 read-only PID38 Peripheral Clock 38 Status 6 1 read-only PID39 Peripheral Clock 39 Status 7 1 read-only PID40 Peripheral Clock 40 Status 8 1 read-only PID41 Peripheral Clock 41 Status 9 1 read-only PID42 Peripheral Clock 42 Status 10 1 read-only PID43 Peripheral Clock 43 Status 11 1 read-only PID44 Peripheral Clock 44 Status 12 1 read-only PMC_PCR Peripheral Control Register 0x0000010C 32 read-write 0x00000000 PID Peripheral ID 0 6 read-write CMD Command 12 1 read-write DIV Divisor Value 16 2 read-write PERIPH_DIV_MCK Peripheral clock is MCK 0x0 PERIPH_DIV2_MCK Peripheral clock is MCK/2 0x1 PERIPH_DIV4_MCK Peripheral clock is MCK/4 0x2 EN Enable 28 1 read-write UART 6418H Universal Asynchronous Receiver Transmitter UART_ 0x400E0800 0 0x128 registers UART 8 CR Control Register 0x00000000 32 write-only RSTRX Reset Receiver 2 1 write-only RSTTX Reset Transmitter 3 1 write-only RXEN Receiver Enable 4 1 write-only RXDIS Receiver Disable 5 1 write-only TXEN Transmitter Enable 6 1 write-only TXDIS Transmitter Disable 7 1 write-only RSTSTA Reset Status Bits 8 1 write-only MR Mode Register 0x00000004 32 read-write 0x00000000 PAR Parity Type 9 3 read-write EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No Parity 0x4 CHMODE Channel Mode 14 2 read-write NORMAL Normal Mode 0x0 AUTOMATIC Automatic Echo 0x1 LOCAL_LOOPBACK Local Loopback 0x2 REMOTE_LOOPBACK Remote Loopback 0x3 IER Interrupt Enable Register 0x00000008 32 write-only RXRDY Enable RXRDY Interrupt 0 1 write-only TXRDY Enable TXRDY Interrupt 1 1 write-only ENDRX Enable End of Receive Transfer Interrupt 3 1 write-only ENDTX Enable End of Transmit Interrupt 4 1 write-only OVRE Enable Overrun Error Interrupt 5 1 write-only FRAME Enable Framing Error Interrupt 6 1 write-only PARE Enable Parity Error Interrupt 7 1 write-only TXEMPTY Enable TXEMPTY Interrupt 9 1 write-only TXBUFE Enable Buffer Empty Interrupt 11 1 write-only RXBUFF Enable Buffer Full Interrupt 12 1 write-only IDR Interrupt Disable Register 0x0000000C 32 write-only RXRDY Disable RXRDY Interrupt 0 1 write-only TXRDY Disable TXRDY Interrupt 1 1 write-only ENDRX Disable End of Receive Transfer Interrupt 3 1 write-only ENDTX Disable End of Transmit Interrupt 4 1 write-only OVRE Disable Overrun Error Interrupt 5 1 write-only FRAME Disable Framing Error Interrupt 6 1 write-only PARE Disable Parity Error Interrupt 7 1 write-only TXEMPTY Disable TXEMPTY Interrupt 9 1 write-only TXBUFE Disable Buffer Empty Interrupt 11 1 write-only RXBUFF Disable Buffer Full Interrupt 12 1 write-only IMR Interrupt Mask Register 0x00000010 32 read-only 0x00000000 RXRDY Mask RXRDY Interrupt 0 1 read-only TXRDY Disable TXRDY Interrupt 1 1 read-only ENDRX Mask End of Receive Transfer Interrupt 3 1 read-only ENDTX Mask End of Transmit Interrupt 4 1 read-only OVRE Mask Overrun Error Interrupt 5 1 read-only FRAME Mask Framing Error Interrupt 6 1 read-only PARE Mask Parity Error Interrupt 7 1 read-only TXEMPTY Mask TXEMPTY Interrupt 9 1 read-only TXBUFE Mask TXBUFE Interrupt 11 1 read-only RXBUFF Mask RXBUFF Interrupt 12 1 read-only SR Status Register 0x00000014 32 read-only RXRDY Receiver Ready 0 1 read-only TXRDY Transmitter Ready 1 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only OVRE Overrun Error 5 1 read-only FRAME Framing Error 6 1 read-only PARE Parity Error 7 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only RXBUFF Receive Buffer Full 12 1 read-only RHR Receive Holding Register 0x00000018 32 read-only 0x00000000 RXCHR Received Character 0 8 read-only THR Transmit Holding Register 0x0000001C 32 write-only TXCHR Character to be Transmitted 0 8 write-only BRGR Baud Rate Generator Register 0x00000020 32 read-write 0x00000000 CD Clock Divisor 0 16 read-write RPR Receive Pointer Register 0x00000100 32 read-write 0x00000000 RXPTR Receive Pointer Register 0 32 read-write RCR Receive Counter Register 0x00000104 32 read-write 0x00000000 RXCTR Receive Counter Register 0 16 read-write TPR Transmit Pointer Register 0x00000108 32 read-write 0x00000000 TXPTR Transmit Counter Register 0 32 read-write TCR Transmit Counter Register 0x0000010C 32 read-write 0x00000000 TXCTR Transmit Counter Register 0 16 read-write RNPR Receive Next Pointer Register 0x00000110 32 read-write 0x00000000 RXNPTR Receive Next Pointer 0 32 read-write RNCR Receive Next Counter Register 0x00000114 32 read-write 0x00000000 RXNCTR Receive Next Counter 0 16 read-write TNPR Transmit Next Pointer Register 0x00000118 32 read-write 0x00000000 TXNPTR Transmit Next Pointer 0 32 read-write TNCR Transmit Next Counter Register 0x0000011C 32 read-write 0x00000000 TXNCTR Transmit Counter Next 0 16 read-write PTCR Transfer Control Register 0x00000120 32 write-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 write-only RXTDIS Receiver Transfer Disable 1 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only PTSR Transfer Status Register 0x00000124 32 read-only 0x00000000 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only CHIPID 6417R Chip Identifier CHIPID_ 0x400E0940 0 0x200 registers CIDR Chip ID Register 0x00000000 32 read-only VERSION Version of the Device 0 5 read-only EPROC Embedded Processor 5 3 read-only ARM946ES ARM946ES 0x1 ARM7TDMI ARM7TDMI 0x2 CM3 Cortex-M3 0x3 ARM920T ARM920T 0x4 ARM926EJS ARM926EJS 0x5 CA5 Cortex-A5 0x6 CM4 Cortex-M4 0x7 NVPSIZ Nonvolatile Program Memory Size 8 4 read-only NONE None 0x0 8K 8 Kbytes 0x1 16K 16 Kbytes 0x2 32K 32 Kbytes 0x3 64K 64 Kbytes 0x5 128K 128 Kbytes 0x7 256K 256 Kbytes 0x9 512K 512 Kbytes 0xA 1024K 1024 Kbytes 0xC 2048K 2048 Kbytes 0xE NVPSIZ2 Second Nonvolatile Program Memory Size 12 4 read-only NONE None 0x0 8K 8 Kbytes 0x1 16K 16 Kbytes 0x2 32K 32 Kbytes 0x3 64K 64 Kbytes 0x5 128K 128 Kbytes 0x7 256K 256 Kbytes 0x9 512K 512 Kbytes 0xA 1024K 1024 Kbytes 0xC 2048K 2048 Kbytes 0xE SRAMSIZ Internal SRAM Size 16 4 read-only 48K 48 Kbytes 0x0 192K 192 Kbytes 0x1 2K 2 Kbytes 0x2 6K 6 Kbytes 0x3 24K 24 Kbytes 0x4 4K 4 Kbytes 0x5 80K 80 Kbytes 0x6 160K 160 Kbytes 0x7 8K 8 Kbytes 0x8 16K 16 Kbytes 0x9 32K 32 Kbytes 0xA 64K 64 Kbytes 0xB 128K 128 Kbytes 0xC 256K 256 Kbytes 0xD 96K 96 Kbytes 0xE 512K 512 Kbytes 0xF ARCH Architecture Identifier 20 8 read-only SAM3AxC SAM3AxC (100-pin version) 0x83 SAM3XxC SAM3XxC (100-pin version) 0x84 SAM3XxE SAM3XxE (144-pin version) 0x85 SAM3XxG SAM3XxG (208/217-pin version) 0x86 NVPTYP Nonvolatile Program Memory Type 28 3 read-only ROM ROM 0x0 ROMLESS ROMless or on-chip Flash 0x1 FLASH Embedded Flash Memory 0x2 ROM_FLASH ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size 0x3 SRAM SRAM emulating ROM 0x4 EXT Extension Flag 31 1 read-only EXID Chip ID Extension Register 0x00000004 32 read-only EXID Chip ID Extension 0 32 read-only EFC0 6450J Embedded Flash Controller 0 EFC EFC0_ 0x400E0A00 0 0x200 registers EFC0 6 FMR EEFC Flash Mode Register 0x00000000 32 read-write 0x00000000 FRDY Ready Interrupt Enable 0 1 read-write FWS Flash Wait State 8 4 read-write SCOD Sequential Code Optimization Disable 16 1 read-write FAM Flash Access Mode 24 1 read-write FCR EEFC Flash Command Register 0x00000004 32 write-only FCMD Flash Command 0 8 write-only GETD Get Flash Descriptor 0x00 WP Write page 0x01 WPL Write page and lock 0x02 EWP Erase page and write page 0x03 EWPL Erase page and write page then lock 0x04 EA Erase all 0x05 SLB Set Lock Bit 0x08 CLB Clear Lock Bit 0x09 GLB Get Lock Bit 0x0A SGPB Set GPNVM Bit 0x0B CGPB Clear GPNVM Bit 0x0C GGPB Get GPNVM Bit 0x0D STUI Start Read Unique Identifier 0x0E SPUI Stop Read Unique Identifier 0x0F GCALB Get CALIB Bit 0x10 FARG Flash Command Argument 8 16 write-only FKEY Flash Writing Protection Key 24 8 write-only PASSWD The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. 0x5A FSR EEFC Flash Status Register 0x00000008 32 read-only 0x00000001 FRDY Flash Ready Status 0 1 read-only FCMDE Flash Command Error Status 1 1 read-only FLOCKE Flash Lock Error Status 2 1 read-only FRR EEFC Flash Result Register 0x0000000C 32 read-only 0x00000000 FVALUE Flash Result Value 0 32 read-only EFC1 6450J Embedded Flash Controller 1 EFC EFC1_ 0x400E0C00 0 0x200 registers EFC1 7 FMR EEFC Flash Mode Register 0x00000000 32 read-write 0x00000000 FRDY Ready Interrupt Enable 0 1 read-write FWS Flash Wait State 8 4 read-write SCOD Sequential Code Optimization Disable 16 1 read-write FAM Flash Access Mode 24 1 read-write FCR EEFC Flash Command Register 0x00000004 32 write-only FCMD Flash Command 0 8 write-only GETD Get Flash Descriptor 0x00 WP Write page 0x01 WPL Write page and lock 0x02 EWP Erase page and write page 0x03 EWPL Erase page and write page then lock 0x04 EA Erase all 0x05 SLB Set Lock Bit 0x08 CLB Clear Lock Bit 0x09 GLB Get Lock Bit 0x0A SGPB Set GPNVM Bit 0x0B CGPB Clear GPNVM Bit 0x0C GGPB Get GPNVM Bit 0x0D STUI Start Read Unique Identifier 0x0E SPUI Stop Read Unique Identifier 0x0F GCALB Get CALIB Bit 0x10 FARG Flash Command Argument 8 16 write-only FKEY Flash Writing Protection Key 24 8 write-only PASSWD The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. 0x5A FSR EEFC Flash Status Register 0x00000008 32 read-only 0x00000001 FRDY Flash Ready Status 0 1 read-only FCMDE Flash Command Error Status 1 1 read-only FLOCKE Flash Lock Error Status 2 1 read-only FRR EEFC Flash Result Register 0x0000000C 32 read-only 0x00000000 FVALUE Flash Result Value 0 32 read-only PIOA 6315C Parallel Input/Output Controller A PIO PIOA_ 0x400E0E00 0 0x200 registers PIOA 11 PER PIO Enable Register 0x00000000 32 write-only P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P2 PIO Enable 2 1 write-only P3 PIO Enable 3 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only PDR PIO Disable Register 0x00000004 32 write-only P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P2 PIO Disable 2 1 write-only P3 PIO Disable 3 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only PSR PIO Status Register 0x00000008 32 read-only P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P2 PIO Status 2 1 read-only P3 PIO Status 3 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only OER Output Enable Register 0x00000010 32 write-only P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P2 Output Enable 2 1 write-only P3 Output Enable 3 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only ODR Output Disable Register 0x00000014 32 write-only P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P2 Output Disable 2 1 write-only P3 Output Disable 3 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only OSR Output Status Register 0x00000018 32 read-only 0x00000000 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P2 Output Status 2 1 read-only P3 Output Status 3 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only IFER Glitch Input Filter Enable Register 0x00000020 32 write-only P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P2 Input Filter Enable 2 1 write-only P3 Input Filter Enable 3 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only IFDR Glitch Input Filter Disable Register 0x00000024 32 write-only P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P2 Input Filter Disable 2 1 write-only P3 Input Filter Disable 3 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only IFSR Glitch Input Filter Status Register 0x00000028 32 read-only 0x00000000 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P2 Input Filer Status 2 1 read-only P3 Input Filer Status 3 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only SODR Set Output Data Register 0x00000030 32 write-only P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P2 Set Output Data 2 1 write-only P3 Set Output Data 3 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only CODR Clear Output Data Register 0x00000034 32 write-only P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P2 Clear Output Data 2 1 write-only P3 Clear Output Data 3 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only ODSR Output Data Status Register 0x00000038 32 read-write P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P2 Output Data Status 2 1 read-write P3 Output Data Status 3 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write PDSR Pin Data Status Register 0x0000003C 32 read-only P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P2 Output Data Status 2 1 read-only P3 Output Data Status 3 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only IER Interrupt Enable Register 0x00000040 32 write-only P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only IDR Interrupt Disable Register 0x00000044 32 write-only P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only IMR Interrupt Mask Register 0x00000048 32 read-only 0x00000000 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only ISR Interrupt Status Register 0x0000004C 32 read-only 0x00000000 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P2 Input Change Interrupt Status 2 1 read-only P3 Input Change Interrupt Status 3 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only MDER Multi-driver Enable Register 0x00000050 32 write-only P0 Multi Drive Enable. 0 1 write-only P1 Multi Drive Enable. 1 1 write-only P2 Multi Drive Enable. 2 1 write-only P3 Multi Drive Enable. 3 1 write-only P4 Multi Drive Enable. 4 1 write-only P5 Multi Drive Enable. 5 1 write-only P6 Multi Drive Enable. 6 1 write-only P7 Multi Drive Enable. 7 1 write-only P8 Multi Drive Enable. 8 1 write-only P9 Multi Drive Enable. 9 1 write-only P10 Multi Drive Enable. 10 1 write-only P11 Multi Drive Enable. 11 1 write-only P12 Multi Drive Enable. 12 1 write-only P13 Multi Drive Enable. 13 1 write-only P14 Multi Drive Enable. 14 1 write-only P15 Multi Drive Enable. 15 1 write-only P16 Multi Drive Enable. 16 1 write-only P17 Multi Drive Enable. 17 1 write-only P18 Multi Drive Enable. 18 1 write-only P19 Multi Drive Enable. 19 1 write-only P20 Multi Drive Enable. 20 1 write-only P21 Multi Drive Enable. 21 1 write-only P22 Multi Drive Enable. 22 1 write-only P23 Multi Drive Enable. 23 1 write-only P24 Multi Drive Enable. 24 1 write-only P25 Multi Drive Enable. 25 1 write-only P26 Multi Drive Enable. 26 1 write-only P27 Multi Drive Enable. 27 1 write-only P28 Multi Drive Enable. 28 1 write-only P29 Multi Drive Enable. 29 1 write-only P30 Multi Drive Enable. 30 1 write-only P31 Multi Drive Enable. 31 1 write-only MDDR Multi-driver Disable Register 0x00000054 32 write-only P0 Multi Drive Disable. 0 1 write-only P1 Multi Drive Disable. 1 1 write-only P2 Multi Drive Disable. 2 1 write-only P3 Multi Drive Disable. 3 1 write-only P4 Multi Drive Disable. 4 1 write-only P5 Multi Drive Disable. 5 1 write-only P6 Multi Drive Disable. 6 1 write-only P7 Multi Drive Disable. 7 1 write-only P8 Multi Drive Disable. 8 1 write-only P9 Multi Drive Disable. 9 1 write-only P10 Multi Drive Disable. 10 1 write-only P11 Multi Drive Disable. 11 1 write-only P12 Multi Drive Disable. 12 1 write-only P13 Multi Drive Disable. 13 1 write-only P14 Multi Drive Disable. 14 1 write-only P15 Multi Drive Disable. 15 1 write-only P16 Multi Drive Disable. 16 1 write-only P17 Multi Drive Disable. 17 1 write-only P18 Multi Drive Disable. 18 1 write-only P19 Multi Drive Disable. 19 1 write-only P20 Multi Drive Disable. 20 1 write-only P21 Multi Drive Disable. 21 1 write-only P22 Multi Drive Disable. 22 1 write-only P23 Multi Drive Disable. 23 1 write-only P24 Multi Drive Disable. 24 1 write-only P25 Multi Drive Disable. 25 1 write-only P26 Multi Drive Disable. 26 1 write-only P27 Multi Drive Disable. 27 1 write-only P28 Multi Drive Disable. 28 1 write-only P29 Multi Drive Disable. 29 1 write-only P30 Multi Drive Disable. 30 1 write-only P31 Multi Drive Disable. 31 1 write-only MDSR Multi-driver Status Register 0x00000058 32 read-only 0x00000000 P0 Multi Drive Status. 0 1 read-only P1 Multi Drive Status. 1 1 read-only P2 Multi Drive Status. 2 1 read-only P3 Multi Drive Status. 3 1 read-only P4 Multi Drive Status. 4 1 read-only P5 Multi Drive Status. 5 1 read-only P6 Multi Drive Status. 6 1 read-only P7 Multi Drive Status. 7 1 read-only P8 Multi Drive Status. 8 1 read-only P9 Multi Drive Status. 9 1 read-only P10 Multi Drive Status. 10 1 read-only P11 Multi Drive Status. 11 1 read-only P12 Multi Drive Status. 12 1 read-only P13 Multi Drive Status. 13 1 read-only P14 Multi Drive Status. 14 1 read-only P15 Multi Drive Status. 15 1 read-only P16 Multi Drive Status. 16 1 read-only P17 Multi Drive Status. 17 1 read-only P18 Multi Drive Status. 18 1 read-only P19 Multi Drive Status. 19 1 read-only P20 Multi Drive Status. 20 1 read-only P21 Multi Drive Status. 21 1 read-only P22 Multi Drive Status. 22 1 read-only P23 Multi Drive Status. 23 1 read-only P24 Multi Drive Status. 24 1 read-only P25 Multi Drive Status. 25 1 read-only P26 Multi Drive Status. 26 1 read-only P27 Multi Drive Status. 27 1 read-only P28 Multi Drive Status. 28 1 read-only P29 Multi Drive Status. 29 1 read-only P30 Multi Drive Status. 30 1 read-only P31 Multi Drive Status. 31 1 read-only PUDR Pull-up Disable Register 0x00000060 32 write-only P0 Pull Up Disable. 0 1 write-only P1 Pull Up Disable. 1 1 write-only P2 Pull Up Disable. 2 1 write-only P3 Pull Up Disable. 3 1 write-only P4 Pull Up Disable. 4 1 write-only P5 Pull Up Disable. 5 1 write-only P6 Pull Up Disable. 6 1 write-only P7 Pull Up Disable. 7 1 write-only P8 Pull Up Disable. 8 1 write-only P9 Pull Up Disable. 9 1 write-only P10 Pull Up Disable. 10 1 write-only P11 Pull Up Disable. 11 1 write-only P12 Pull Up Disable. 12 1 write-only P13 Pull Up Disable. 13 1 write-only P14 Pull Up Disable. 14 1 write-only P15 Pull Up Disable. 15 1 write-only P16 Pull Up Disable. 16 1 write-only P17 Pull Up Disable. 17 1 write-only P18 Pull Up Disable. 18 1 write-only P19 Pull Up Disable. 19 1 write-only P20 Pull Up Disable. 20 1 write-only P21 Pull Up Disable. 21 1 write-only P22 Pull Up Disable. 22 1 write-only P23 Pull Up Disable. 23 1 write-only P24 Pull Up Disable. 24 1 write-only P25 Pull Up Disable. 25 1 write-only P26 Pull Up Disable. 26 1 write-only P27 Pull Up Disable. 27 1 write-only P28 Pull Up Disable. 28 1 write-only P29 Pull Up Disable. 29 1 write-only P30 Pull Up Disable. 30 1 write-only P31 Pull Up Disable. 31 1 write-only PUER Pull-up Enable Register 0x00000064 32 write-only P0 Pull Up Enable. 0 1 write-only P1 Pull Up Enable. 1 1 write-only P2 Pull Up Enable. 2 1 write-only P3 Pull Up Enable. 3 1 write-only P4 Pull Up Enable. 4 1 write-only P5 Pull Up Enable. 5 1 write-only P6 Pull Up Enable. 6 1 write-only P7 Pull Up Enable. 7 1 write-only P8 Pull Up Enable. 8 1 write-only P9 Pull Up Enable. 9 1 write-only P10 Pull Up Enable. 10 1 write-only P11 Pull Up Enable. 11 1 write-only P12 Pull Up Enable. 12 1 write-only P13 Pull Up Enable. 13 1 write-only P14 Pull Up Enable. 14 1 write-only P15 Pull Up Enable. 15 1 write-only P16 Pull Up Enable. 16 1 write-only P17 Pull Up Enable. 17 1 write-only P18 Pull Up Enable. 18 1 write-only P19 Pull Up Enable. 19 1 write-only P20 Pull Up Enable. 20 1 write-only P21 Pull Up Enable. 21 1 write-only P22 Pull Up Enable. 22 1 write-only P23 Pull Up Enable. 23 1 write-only P24 Pull Up Enable. 24 1 write-only P25 Pull Up Enable. 25 1 write-only P26 Pull Up Enable. 26 1 write-only P27 Pull Up Enable. 27 1 write-only P28 Pull Up Enable. 28 1 write-only P29 Pull Up Enable. 29 1 write-only P30 Pull Up Enable. 30 1 write-only P31 Pull Up Enable. 31 1 write-only PUSR Pad Pull-up Status Register 0x00000068 32 read-only 0x00000000 P0 Pull Up Status. 0 1 read-only P1 Pull Up Status. 1 1 read-only P2 Pull Up Status. 2 1 read-only P3 Pull Up Status. 3 1 read-only P4 Pull Up Status. 4 1 read-only P5 Pull Up Status. 5 1 read-only P6 Pull Up Status. 6 1 read-only P7 Pull Up Status. 7 1 read-only P8 Pull Up Status. 8 1 read-only P9 Pull Up Status. 9 1 read-only P10 Pull Up Status. 10 1 read-only P11 Pull Up Status. 11 1 read-only P12 Pull Up Status. 12 1 read-only P13 Pull Up Status. 13 1 read-only P14 Pull Up Status. 14 1 read-only P15 Pull Up Status. 15 1 read-only P16 Pull Up Status. 16 1 read-only P17 Pull Up Status. 17 1 read-only P18 Pull Up Status. 18 1 read-only P19 Pull Up Status. 19 1 read-only P20 Pull Up Status. 20 1 read-only P21 Pull Up Status. 21 1 read-only P22 Pull Up Status. 22 1 read-only P23 Pull Up Status. 23 1 read-only P24 Pull Up Status. 24 1 read-only P25 Pull Up Status. 25 1 read-only P26 Pull Up Status. 26 1 read-only P27 Pull Up Status. 27 1 read-only P28 Pull Up Status. 28 1 read-only P29 Pull Up Status. 29 1 read-only P30 Pull Up Status. 30 1 read-only P31 Pull Up Status. 31 1 read-only ABSR Peripheral AB Select Register 0x00000070 32 read-write 0x00000000 P0 Peripheral A Select. 0 1 read-write P1 Peripheral A Select. 1 1 read-write P2 Peripheral A Select. 2 1 read-write P3 Peripheral A Select. 3 1 read-write P4 Peripheral A Select. 4 1 read-write P5 Peripheral A Select. 5 1 read-write P6 Peripheral A Select. 6 1 read-write P7 Peripheral A Select. 7 1 read-write P8 Peripheral A Select. 8 1 read-write P9 Peripheral A Select. 9 1 read-write P10 Peripheral A Select. 10 1 read-write P11 Peripheral A Select. 11 1 read-write P12 Peripheral A Select. 12 1 read-write P13 Peripheral A Select. 13 1 read-write P14 Peripheral A Select. 14 1 read-write P15 Peripheral A Select. 15 1 read-write P16 Peripheral A Select. 16 1 read-write P17 Peripheral A Select. 17 1 read-write P18 Peripheral A Select. 18 1 read-write P19 Peripheral A Select. 19 1 read-write P20 Peripheral A Select. 20 1 read-write P21 Peripheral A Select. 21 1 read-write P22 Peripheral A Select. 22 1 read-write P23 Peripheral A Select. 23 1 read-write P24 Peripheral A Select. 24 1 read-write P25 Peripheral A Select. 25 1 read-write P26 Peripheral A Select. 26 1 read-write P27 Peripheral A Select. 27 1 read-write P28 Peripheral A Select. 28 1 read-write P29 Peripheral A Select. 29 1 read-write P30 Peripheral A Select. 30 1 read-write P31 Peripheral A Select. 31 1 read-write SCIFSR System Clock Glitch Input Filter Select Register 0x00000080 32 write-only P0 System Clock Glitch Filtering Select. 0 1 write-only P1 System Clock Glitch Filtering Select. 1 1 write-only P2 System Clock Glitch Filtering Select. 2 1 write-only P3 System Clock Glitch Filtering Select. 3 1 write-only P4 System Clock Glitch Filtering Select. 4 1 write-only P5 System Clock Glitch Filtering Select. 5 1 write-only P6 System Clock Glitch Filtering Select. 6 1 write-only P7 System Clock Glitch Filtering Select. 7 1 write-only P8 System Clock Glitch Filtering Select. 8 1 write-only P9 System Clock Glitch Filtering Select. 9 1 write-only P10 System Clock Glitch Filtering Select. 10 1 write-only P11 System Clock Glitch Filtering Select. 11 1 write-only P12 System Clock Glitch Filtering Select. 12 1 write-only P13 System Clock Glitch Filtering Select. 13 1 write-only P14 System Clock Glitch Filtering Select. 14 1 write-only P15 System Clock Glitch Filtering Select. 15 1 write-only P16 System Clock Glitch Filtering Select. 16 1 write-only P17 System Clock Glitch Filtering Select. 17 1 write-only P18 System Clock Glitch Filtering Select. 18 1 write-only P19 System Clock Glitch Filtering Select. 19 1 write-only P20 System Clock Glitch Filtering Select. 20 1 write-only P21 System Clock Glitch Filtering Select. 21 1 write-only P22 System Clock Glitch Filtering Select. 22 1 write-only P23 System Clock Glitch Filtering Select. 23 1 write-only P24 System Clock Glitch Filtering Select. 24 1 write-only P25 System Clock Glitch Filtering Select. 25 1 write-only P26 System Clock Glitch Filtering Select. 26 1 write-only P27 System Clock Glitch Filtering Select. 27 1 write-only P28 System Clock Glitch Filtering Select. 28 1 write-only P29 System Clock Glitch Filtering Select. 29 1 write-only P30 System Clock Glitch Filtering Select. 30 1 write-only P31 System Clock Glitch Filtering Select. 31 1 write-only DIFSR Debouncing Input Filter Select Register 0x00000084 32 write-only P0 Debouncing Filtering Select. 0 1 write-only P1 Debouncing Filtering Select. 1 1 write-only P2 Debouncing Filtering Select. 2 1 write-only P3 Debouncing Filtering Select. 3 1 write-only P4 Debouncing Filtering Select. 4 1 write-only P5 Debouncing Filtering Select. 5 1 write-only P6 Debouncing Filtering Select. 6 1 write-only P7 Debouncing Filtering Select. 7 1 write-only P8 Debouncing Filtering Select. 8 1 write-only P9 Debouncing Filtering Select. 9 1 write-only P10 Debouncing Filtering Select. 10 1 write-only P11 Debouncing Filtering Select. 11 1 write-only P12 Debouncing Filtering Select. 12 1 write-only P13 Debouncing Filtering Select. 13 1 write-only P14 Debouncing Filtering Select. 14 1 write-only P15 Debouncing Filtering Select. 15 1 write-only P16 Debouncing Filtering Select. 16 1 write-only P17 Debouncing Filtering Select. 17 1 write-only P18 Debouncing Filtering Select. 18 1 write-only P19 Debouncing Filtering Select. 19 1 write-only P20 Debouncing Filtering Select. 20 1 write-only P21 Debouncing Filtering Select. 21 1 write-only P22 Debouncing Filtering Select. 22 1 write-only P23 Debouncing Filtering Select. 23 1 write-only P24 Debouncing Filtering Select. 24 1 write-only P25 Debouncing Filtering Select. 25 1 write-only P26 Debouncing Filtering Select. 26 1 write-only P27 Debouncing Filtering Select. 27 1 write-only P28 Debouncing Filtering Select. 28 1 write-only P29 Debouncing Filtering Select. 29 1 write-only P30 Debouncing Filtering Select. 30 1 write-only P31 Debouncing Filtering Select. 31 1 write-only IFDGSR Glitch or Debouncing Input Filter Clock Selection Status Register 0x00000088 32 read-only 0x00000000 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only SCDR Slow Clock Divider Debouncing Register 0x0000008C 32 read-write 0x00000000 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write OWER Output Write Enable 0x000000A0 32 write-only P0 Output Write Enable. 0 1 write-only P1 Output Write Enable. 1 1 write-only P2 Output Write Enable. 2 1 write-only P3 Output Write Enable. 3 1 write-only P4 Output Write Enable. 4 1 write-only P5 Output Write Enable. 5 1 write-only P6 Output Write Enable. 6 1 write-only P7 Output Write Enable. 7 1 write-only P8 Output Write Enable. 8 1 write-only P9 Output Write Enable. 9 1 write-only P10 Output Write Enable. 10 1 write-only P11 Output Write Enable. 11 1 write-only P12 Output Write Enable. 12 1 write-only P13 Output Write Enable. 13 1 write-only P14 Output Write Enable. 14 1 write-only P15 Output Write Enable. 15 1 write-only P16 Output Write Enable. 16 1 write-only P17 Output Write Enable. 17 1 write-only P18 Output Write Enable. 18 1 write-only P19 Output Write Enable. 19 1 write-only P20 Output Write Enable. 20 1 write-only P21 Output Write Enable. 21 1 write-only P22 Output Write Enable. 22 1 write-only P23 Output Write Enable. 23 1 write-only P24 Output Write Enable. 24 1 write-only P25 Output Write Enable. 25 1 write-only P26 Output Write Enable. 26 1 write-only P27 Output Write Enable. 27 1 write-only P28 Output Write Enable. 28 1 write-only P29 Output Write Enable. 29 1 write-only P30 Output Write Enable. 30 1 write-only P31 Output Write Enable. 31 1 write-only OWDR Output Write Disable 0x000000A4 32 write-only P0 Output Write Disable. 0 1 write-only P1 Output Write Disable. 1 1 write-only P2 Output Write Disable. 2 1 write-only P3 Output Write Disable. 3 1 write-only P4 Output Write Disable. 4 1 write-only P5 Output Write Disable. 5 1 write-only P6 Output Write Disable. 6 1 write-only P7 Output Write Disable. 7 1 write-only P8 Output Write Disable. 8 1 write-only P9 Output Write Disable. 9 1 write-only P10 Output Write Disable. 10 1 write-only P11 Output Write Disable. 11 1 write-only P12 Output Write Disable. 12 1 write-only P13 Output Write Disable. 13 1 write-only P14 Output Write Disable. 14 1 write-only P15 Output Write Disable. 15 1 write-only P16 Output Write Disable. 16 1 write-only P17 Output Write Disable. 17 1 write-only P18 Output Write Disable. 18 1 write-only P19 Output Write Disable. 19 1 write-only P20 Output Write Disable. 20 1 write-only P21 Output Write Disable. 21 1 write-only P22 Output Write Disable. 22 1 write-only P23 Output Write Disable. 23 1 write-only P24 Output Write Disable. 24 1 write-only P25 Output Write Disable. 25 1 write-only P26 Output Write Disable. 26 1 write-only P27 Output Write Disable. 27 1 write-only P28 Output Write Disable. 28 1 write-only P29 Output Write Disable. 29 1 write-only P30 Output Write Disable. 30 1 write-only P31 Output Write Disable. 31 1 write-only OWSR Output Write Status Register 0x000000A8 32 read-only 0x00000000 P0 Output Write Status. 0 1 read-only P1 Output Write Status. 1 1 read-only P2 Output Write Status. 2 1 read-only P3 Output Write Status. 3 1 read-only P4 Output Write Status. 4 1 read-only P5 Output Write Status. 5 1 read-only P6 Output Write Status. 6 1 read-only P7 Output Write Status. 7 1 read-only P8 Output Write Status. 8 1 read-only P9 Output Write Status. 9 1 read-only P10 Output Write Status. 10 1 read-only P11 Output Write Status. 11 1 read-only P12 Output Write Status. 12 1 read-only P13 Output Write Status. 13 1 read-only P14 Output Write Status. 14 1 read-only P15 Output Write Status. 15 1 read-only P16 Output Write Status. 16 1 read-only P17 Output Write Status. 17 1 read-only P18 Output Write Status. 18 1 read-only P19 Output Write Status. 19 1 read-only P20 Output Write Status. 20 1 read-only P21 Output Write Status. 21 1 read-only P22 Output Write Status. 22 1 read-only P23 Output Write Status. 23 1 read-only P24 Output Write Status. 24 1 read-only P25 Output Write Status. 25 1 read-only P26 Output Write Status. 26 1 read-only P27 Output Write Status. 27 1 read-only P28 Output Write Status. 28 1 read-only P29 Output Write Status. 29 1 read-only P30 Output Write Status. 30 1 read-only P31 Output Write Status. 31 1 read-only AIMER Additional Interrupt Modes Enable Register 0x000000B0 32 write-only P0 Additional Interrupt Modes Enable. 0 1 write-only P1 Additional Interrupt Modes Enable. 1 1 write-only P2 Additional Interrupt Modes Enable. 2 1 write-only P3 Additional Interrupt Modes Enable. 3 1 write-only P4 Additional Interrupt Modes Enable. 4 1 write-only P5 Additional Interrupt Modes Enable. 5 1 write-only P6 Additional Interrupt Modes Enable. 6 1 write-only P7 Additional Interrupt Modes Enable. 7 1 write-only P8 Additional Interrupt Modes Enable. 8 1 write-only P9 Additional Interrupt Modes Enable. 9 1 write-only P10 Additional Interrupt Modes Enable. 10 1 write-only P11 Additional Interrupt Modes Enable. 11 1 write-only P12 Additional Interrupt Modes Enable. 12 1 write-only P13 Additional Interrupt Modes Enable. 13 1 write-only P14 Additional Interrupt Modes Enable. 14 1 write-only P15 Additional Interrupt Modes Enable. 15 1 write-only P16 Additional Interrupt Modes Enable. 16 1 write-only P17 Additional Interrupt Modes Enable. 17 1 write-only P18 Additional Interrupt Modes Enable. 18 1 write-only P19 Additional Interrupt Modes Enable. 19 1 write-only P20 Additional Interrupt Modes Enable. 20 1 write-only P21 Additional Interrupt Modes Enable. 21 1 write-only P22 Additional Interrupt Modes Enable. 22 1 write-only P23 Additional Interrupt Modes Enable. 23 1 write-only P24 Additional Interrupt Modes Enable. 24 1 write-only P25 Additional Interrupt Modes Enable. 25 1 write-only P26 Additional Interrupt Modes Enable. 26 1 write-only P27 Additional Interrupt Modes Enable. 27 1 write-only P28 Additional Interrupt Modes Enable. 28 1 write-only P29 Additional Interrupt Modes Enable. 29 1 write-only P30 Additional Interrupt Modes Enable. 30 1 write-only P31 Additional Interrupt Modes Enable. 31 1 write-only AIMDR Additional Interrupt Modes Disables Register 0x000000B4 32 write-only P0 Additional Interrupt Modes Disable. 0 1 write-only P1 Additional Interrupt Modes Disable. 1 1 write-only P2 Additional Interrupt Modes Disable. 2 1 write-only P3 Additional Interrupt Modes Disable. 3 1 write-only P4 Additional Interrupt Modes Disable. 4 1 write-only P5 Additional Interrupt Modes Disable. 5 1 write-only P6 Additional Interrupt Modes Disable. 6 1 write-only P7 Additional Interrupt Modes Disable. 7 1 write-only P8 Additional Interrupt Modes Disable. 8 1 write-only P9 Additional Interrupt Modes Disable. 9 1 write-only P10 Additional Interrupt Modes Disable. 10 1 write-only P11 Additional Interrupt Modes Disable. 11 1 write-only P12 Additional Interrupt Modes Disable. 12 1 write-only P13 Additional Interrupt Modes Disable. 13 1 write-only P14 Additional Interrupt Modes Disable. 14 1 write-only P15 Additional Interrupt Modes Disable. 15 1 write-only P16 Additional Interrupt Modes Disable. 16 1 write-only P17 Additional Interrupt Modes Disable. 17 1 write-only P18 Additional Interrupt Modes Disable. 18 1 write-only P19 Additional Interrupt Modes Disable. 19 1 write-only P20 Additional Interrupt Modes Disable. 20 1 write-only P21 Additional Interrupt Modes Disable. 21 1 write-only P22 Additional Interrupt Modes Disable. 22 1 write-only P23 Additional Interrupt Modes Disable. 23 1 write-only P24 Additional Interrupt Modes Disable. 24 1 write-only P25 Additional Interrupt Modes Disable. 25 1 write-only P26 Additional Interrupt Modes Disable. 26 1 write-only P27 Additional Interrupt Modes Disable. 27 1 write-only P28 Additional Interrupt Modes Disable. 28 1 write-only P29 Additional Interrupt Modes Disable. 29 1 write-only P30 Additional Interrupt Modes Disable. 30 1 write-only P31 Additional Interrupt Modes Disable. 31 1 write-only AIMMR Additional Interrupt Modes Mask Register 0x000000B8 32 read-only 0x00000000 P0 Peripheral CD Status. 0 1 read-only P1 Peripheral CD Status. 1 1 read-only P2 Peripheral CD Status. 2 1 read-only P3 Peripheral CD Status. 3 1 read-only P4 Peripheral CD Status. 4 1 read-only P5 Peripheral CD Status. 5 1 read-only P6 Peripheral CD Status. 6 1 read-only P7 Peripheral CD Status. 7 1 read-only P8 Peripheral CD Status. 8 1 read-only P9 Peripheral CD Status. 9 1 read-only P10 Peripheral CD Status. 10 1 read-only P11 Peripheral CD Status. 11 1 read-only P12 Peripheral CD Status. 12 1 read-only P13 Peripheral CD Status. 13 1 read-only P14 Peripheral CD Status. 14 1 read-only P15 Peripheral CD Status. 15 1 read-only P16 Peripheral CD Status. 16 1 read-only P17 Peripheral CD Status. 17 1 read-only P18 Peripheral CD Status. 18 1 read-only P19 Peripheral CD Status. 19 1 read-only P20 Peripheral CD Status. 20 1 read-only P21 Peripheral CD Status. 21 1 read-only P22 Peripheral CD Status. 22 1 read-only P23 Peripheral CD Status. 23 1 read-only P24 Peripheral CD Status. 24 1 read-only P25 Peripheral CD Status. 25 1 read-only P26 Peripheral CD Status. 26 1 read-only P27 Peripheral CD Status. 27 1 read-only P28 Peripheral CD Status. 28 1 read-only P29 Peripheral CD Status. 29 1 read-only P30 Peripheral CD Status. 30 1 read-only P31 Peripheral CD Status. 31 1 read-only ESR Edge Select Register 0x000000C0 32 write-only P0 Edge Interrupt Selection. 0 1 write-only P1 Edge Interrupt Selection. 1 1 write-only P2 Edge Interrupt Selection. 2 1 write-only P3 Edge Interrupt Selection. 3 1 write-only P4 Edge Interrupt Selection. 4 1 write-only P5 Edge Interrupt Selection. 5 1 write-only P6 Edge Interrupt Selection. 6 1 write-only P7 Edge Interrupt Selection. 7 1 write-only P8 Edge Interrupt Selection. 8 1 write-only P9 Edge Interrupt Selection. 9 1 write-only P10 Edge Interrupt Selection. 10 1 write-only P11 Edge Interrupt Selection. 11 1 write-only P12 Edge Interrupt Selection. 12 1 write-only P13 Edge Interrupt Selection. 13 1 write-only P14 Edge Interrupt Selection. 14 1 write-only P15 Edge Interrupt Selection. 15 1 write-only P16 Edge Interrupt Selection. 16 1 write-only P17 Edge Interrupt Selection. 17 1 write-only P18 Edge Interrupt Selection. 18 1 write-only P19 Edge Interrupt Selection. 19 1 write-only P20 Edge Interrupt Selection. 20 1 write-only P21 Edge Interrupt Selection. 21 1 write-only P22 Edge Interrupt Selection. 22 1 write-only P23 Edge Interrupt Selection. 23 1 write-only P24 Edge Interrupt Selection. 24 1 write-only P25 Edge Interrupt Selection. 25 1 write-only P26 Edge Interrupt Selection. 26 1 write-only P27 Edge Interrupt Selection. 27 1 write-only P28 Edge Interrupt Selection. 28 1 write-only P29 Edge Interrupt Selection. 29 1 write-only P30 Edge Interrupt Selection. 30 1 write-only P31 Edge Interrupt Selection. 31 1 write-only LSR Level Select Register 0x000000C4 32 write-only P0 Level Interrupt Selection. 0 1 write-only P1 Level Interrupt Selection. 1 1 write-only P2 Level Interrupt Selection. 2 1 write-only P3 Level Interrupt Selection. 3 1 write-only P4 Level Interrupt Selection. 4 1 write-only P5 Level Interrupt Selection. 5 1 write-only P6 Level Interrupt Selection. 6 1 write-only P7 Level Interrupt Selection. 7 1 write-only P8 Level Interrupt Selection. 8 1 write-only P9 Level Interrupt Selection. 9 1 write-only P10 Level Interrupt Selection. 10 1 write-only P11 Level Interrupt Selection. 11 1 write-only P12 Level Interrupt Selection. 12 1 write-only P13 Level Interrupt Selection. 13 1 write-only P14 Level Interrupt Selection. 14 1 write-only P15 Level Interrupt Selection. 15 1 write-only P16 Level Interrupt Selection. 16 1 write-only P17 Level Interrupt Selection. 17 1 write-only P18 Level Interrupt Selection. 18 1 write-only P19 Level Interrupt Selection. 19 1 write-only P20 Level Interrupt Selection. 20 1 write-only P21 Level Interrupt Selection. 21 1 write-only P22 Level Interrupt Selection. 22 1 write-only P23 Level Interrupt Selection. 23 1 write-only P24 Level Interrupt Selection. 24 1 write-only P25 Level Interrupt Selection. 25 1 write-only P26 Level Interrupt Selection. 26 1 write-only P27 Level Interrupt Selection. 27 1 write-only P28 Level Interrupt Selection. 28 1 write-only P29 Level Interrupt Selection. 29 1 write-only P30 Level Interrupt Selection. 30 1 write-only P31 Level Interrupt Selection. 31 1 write-only ELSR Edge/Level Status Register 0x000000C8 32 read-only 0x00000000 P0 Edge/Level Interrupt source selection. 0 1 read-only P1 Edge/Level Interrupt source selection. 1 1 read-only P2 Edge/Level Interrupt source selection. 2 1 read-only P3 Edge/Level Interrupt source selection. 3 1 read-only P4 Edge/Level Interrupt source selection. 4 1 read-only P5 Edge/Level Interrupt source selection. 5 1 read-only P6 Edge/Level Interrupt source selection. 6 1 read-only P7 Edge/Level Interrupt source selection. 7 1 read-only P8 Edge/Level Interrupt source selection. 8 1 read-only P9 Edge/Level Interrupt source selection. 9 1 read-only P10 Edge/Level Interrupt source selection. 10 1 read-only P11 Edge/Level Interrupt source selection. 11 1 read-only P12 Edge/Level Interrupt source selection. 12 1 read-only P13 Edge/Level Interrupt source selection. 13 1 read-only P14 Edge/Level Interrupt source selection. 14 1 read-only P15 Edge/Level Interrupt source selection. 15 1 read-only P16 Edge/Level Interrupt source selection. 16 1 read-only P17 Edge/Level Interrupt source selection. 17 1 read-only P18 Edge/Level Interrupt source selection. 18 1 read-only P19 Edge/Level Interrupt source selection. 19 1 read-only P20 Edge/Level Interrupt source selection. 20 1 read-only P21 Edge/Level Interrupt source selection. 21 1 read-only P22 Edge/Level Interrupt source selection. 22 1 read-only P23 Edge/Level Interrupt source selection. 23 1 read-only P24 Edge/Level Interrupt source selection. 24 1 read-only P25 Edge/Level Interrupt source selection. 25 1 read-only P26 Edge/Level Interrupt source selection. 26 1 read-only P27 Edge/Level Interrupt source selection. 27 1 read-only P28 Edge/Level Interrupt source selection. 28 1 read-only P29 Edge/Level Interrupt source selection. 29 1 read-only P30 Edge/Level Interrupt source selection. 30 1 read-only P31 Edge/Level Interrupt source selection. 31 1 read-only FELLSR Falling Edge/Low Level Select Register 0x000000D0 32 write-only P0 Falling Edge/Low Level Interrupt Selection. 0 1 write-only P1 Falling Edge/Low Level Interrupt Selection. 1 1 write-only P2 Falling Edge/Low Level Interrupt Selection. 2 1 write-only P3 Falling Edge/Low Level Interrupt Selection. 3 1 write-only P4 Falling Edge/Low Level Interrupt Selection. 4 1 write-only P5 Falling Edge/Low Level Interrupt Selection. 5 1 write-only P6 Falling Edge/Low Level Interrupt Selection. 6 1 write-only P7 Falling Edge/Low Level Interrupt Selection. 7 1 write-only P8 Falling Edge/Low Level Interrupt Selection. 8 1 write-only P9 Falling Edge/Low Level Interrupt Selection. 9 1 write-only P10 Falling Edge/Low Level Interrupt Selection. 10 1 write-only P11 Falling Edge/Low Level Interrupt Selection. 11 1 write-only P12 Falling Edge/Low Level Interrupt Selection. 12 1 write-only P13 Falling Edge/Low Level Interrupt Selection. 13 1 write-only P14 Falling Edge/Low Level Interrupt Selection. 14 1 write-only P15 Falling Edge/Low Level Interrupt Selection. 15 1 write-only P16 Falling Edge/Low Level Interrupt Selection. 16 1 write-only P17 Falling Edge/Low Level Interrupt Selection. 17 1 write-only P18 Falling Edge/Low Level Interrupt Selection. 18 1 write-only P19 Falling Edge/Low Level Interrupt Selection. 19 1 write-only P20 Falling Edge/Low Level Interrupt Selection. 20 1 write-only P21 Falling Edge/Low Level Interrupt Selection. 21 1 write-only P22 Falling Edge/Low Level Interrupt Selection. 22 1 write-only P23 Falling Edge/Low Level Interrupt Selection. 23 1 write-only P24 Falling Edge/Low Level Interrupt Selection. 24 1 write-only P25 Falling Edge/Low Level Interrupt Selection. 25 1 write-only P26 Falling Edge/Low Level Interrupt Selection. 26 1 write-only P27 Falling Edge/Low Level Interrupt Selection. 27 1 write-only P28 Falling Edge/Low Level Interrupt Selection. 28 1 write-only P29 Falling Edge/Low Level Interrupt Selection. 29 1 write-only P30 Falling Edge/Low Level Interrupt Selection. 30 1 write-only P31 Falling Edge/Low Level Interrupt Selection. 31 1 write-only REHLSR Rising Edge/ High Level Select Register 0x000000D4 32 write-only P0 Rising Edge /High Level Interrupt Selection. 0 1 write-only P1 Rising Edge /High Level Interrupt Selection. 1 1 write-only P2 Rising Edge /High Level Interrupt Selection. 2 1 write-only P3 Rising Edge /High Level Interrupt Selection. 3 1 write-only P4 Rising Edge /High Level Interrupt Selection. 4 1 write-only P5 Rising Edge /High Level Interrupt Selection. 5 1 write-only P6 Rising Edge /High Level Interrupt Selection. 6 1 write-only P7 Rising Edge /High Level Interrupt Selection. 7 1 write-only P8 Rising Edge /High Level Interrupt Selection. 8 1 write-only P9 Rising Edge /High Level Interrupt Selection. 9 1 write-only P10 Rising Edge /High Level Interrupt Selection. 10 1 write-only P11 Rising Edge /High Level Interrupt Selection. 11 1 write-only P12 Rising Edge /High Level Interrupt Selection. 12 1 write-only P13 Rising Edge /High Level Interrupt Selection. 13 1 write-only P14 Rising Edge /High Level Interrupt Selection. 14 1 write-only P15 Rising Edge /High Level Interrupt Selection. 15 1 write-only P16 Rising Edge /High Level Interrupt Selection. 16 1 write-only P17 Rising Edge /High Level Interrupt Selection. 17 1 write-only P18 Rising Edge /High Level Interrupt Selection. 18 1 write-only P19 Rising Edge /High Level Interrupt Selection. 19 1 write-only P20 Rising Edge /High Level Interrupt Selection. 20 1 write-only P21 Rising Edge /High Level Interrupt Selection. 21 1 write-only P22 Rising Edge /High Level Interrupt Selection. 22 1 write-only P23 Rising Edge /High Level Interrupt Selection. 23 1 write-only P24 Rising Edge /High Level Interrupt Selection. 24 1 write-only P25 Rising Edge /High Level Interrupt Selection. 25 1 write-only P26 Rising Edge /High Level Interrupt Selection. 26 1 write-only P27 Rising Edge /High Level Interrupt Selection. 27 1 write-only P28 Rising Edge /High Level Interrupt Selection. 28 1 write-only P29 Rising Edge /High Level Interrupt Selection. 29 1 write-only P30 Rising Edge /High Level Interrupt Selection. 30 1 write-only P31 Rising Edge /High Level Interrupt Selection. 31 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0x000000D8 32 read-only 0x00000000 P0 Edge /Level Interrupt Source Selection. 0 1 read-only P1 Edge /Level Interrupt Source Selection. 1 1 read-only P2 Edge /Level Interrupt Source Selection. 2 1 read-only P3 Edge /Level Interrupt Source Selection. 3 1 read-only P4 Edge /Level Interrupt Source Selection. 4 1 read-only P5 Edge /Level Interrupt Source Selection. 5 1 read-only P6 Edge /Level Interrupt Source Selection. 6 1 read-only P7 Edge /Level Interrupt Source Selection. 7 1 read-only P8 Edge /Level Interrupt Source Selection. 8 1 read-only P9 Edge /Level Interrupt Source Selection. 9 1 read-only P10 Edge /Level Interrupt Source Selection. 10 1 read-only P11 Edge /Level Interrupt Source Selection. 11 1 read-only P12 Edge /Level Interrupt Source Selection. 12 1 read-only P13 Edge /Level Interrupt Source Selection. 13 1 read-only P14 Edge /Level Interrupt Source Selection. 14 1 read-only P15 Edge /Level Interrupt Source Selection. 15 1 read-only P16 Edge /Level Interrupt Source Selection. 16 1 read-only P17 Edge /Level Interrupt Source Selection. 17 1 read-only P18 Edge /Level Interrupt Source Selection. 18 1 read-only P19 Edge /Level Interrupt Source Selection. 19 1 read-only P20 Edge /Level Interrupt Source Selection. 20 1 read-only P21 Edge /Level Interrupt Source Selection. 21 1 read-only P22 Edge /Level Interrupt Source Selection. 22 1 read-only P23 Edge /Level Interrupt Source Selection. 23 1 read-only P24 Edge /Level Interrupt Source Selection. 24 1 read-only P25 Edge /Level Interrupt Source Selection. 25 1 read-only P26 Edge /Level Interrupt Source Selection. 26 1 read-only P27 Edge /Level Interrupt Source Selection. 27 1 read-only P28 Edge /Level Interrupt Source Selection. 28 1 read-only P29 Edge /Level Interrupt Source Selection. 29 1 read-only P30 Edge /Level Interrupt Source Selection. 30 1 read-only P31 Edge /Level Interrupt Source Selection. 31 1 read-only LOCKSR Lock Status 0x000000E0 32 read-only 0x00000000 P0 Lock Status. 0 1 read-only P1 Lock Status. 1 1 read-only P2 Lock Status. 2 1 read-only P3 Lock Status. 3 1 read-only P4 Lock Status. 4 1 read-only P5 Lock Status. 5 1 read-only P6 Lock Status. 6 1 read-only P7 Lock Status. 7 1 read-only P8 Lock Status. 8 1 read-only P9 Lock Status. 9 1 read-only P10 Lock Status. 10 1 read-only P11 Lock Status. 11 1 read-only P12 Lock Status. 12 1 read-only P13 Lock Status. 13 1 read-only P14 Lock Status. 14 1 read-only P15 Lock Status. 15 1 read-only P16 Lock Status. 16 1 read-only P17 Lock Status. 17 1 read-only P18 Lock Status. 18 1 read-only P19 Lock Status. 19 1 read-only P20 Lock Status. 20 1 read-only P21 Lock Status. 21 1 read-only P22 Lock Status. 22 1 read-only P23 Lock Status. 23 1 read-only P24 Lock Status. 24 1 read-only P25 Lock Status. 25 1 read-only P26 Lock Status. 26 1 read-only P27 Lock Status. 27 1 read-only P28 Lock Status. 28 1 read-only P29 Lock Status. 29 1 read-only P30 Lock Status. 30 1 read-only P31 Lock Status. 31 1 read-only WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PIOB 6315C Parallel Input/Output Controller B PIO PIOB_ 0x400E1000 0 0x200 registers PIOB 12 PER PIO Enable Register 0x00000000 32 write-only P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P2 PIO Enable 2 1 write-only P3 PIO Enable 3 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only PDR PIO Disable Register 0x00000004 32 write-only P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P2 PIO Disable 2 1 write-only P3 PIO Disable 3 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only PSR PIO Status Register 0x00000008 32 read-only P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P2 PIO Status 2 1 read-only P3 PIO Status 3 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only OER Output Enable Register 0x00000010 32 write-only P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P2 Output Enable 2 1 write-only P3 Output Enable 3 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only ODR Output Disable Register 0x00000014 32 write-only P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P2 Output Disable 2 1 write-only P3 Output Disable 3 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only OSR Output Status Register 0x00000018 32 read-only 0x00000000 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P2 Output Status 2 1 read-only P3 Output Status 3 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only IFER Glitch Input Filter Enable Register 0x00000020 32 write-only P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P2 Input Filter Enable 2 1 write-only P3 Input Filter Enable 3 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only IFDR Glitch Input Filter Disable Register 0x00000024 32 write-only P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P2 Input Filter Disable 2 1 write-only P3 Input Filter Disable 3 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only IFSR Glitch Input Filter Status Register 0x00000028 32 read-only 0x00000000 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P2 Input Filer Status 2 1 read-only P3 Input Filer Status 3 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only SODR Set Output Data Register 0x00000030 32 write-only P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P2 Set Output Data 2 1 write-only P3 Set Output Data 3 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only CODR Clear Output Data Register 0x00000034 32 write-only P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P2 Clear Output Data 2 1 write-only P3 Clear Output Data 3 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only ODSR Output Data Status Register 0x00000038 32 read-write P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P2 Output Data Status 2 1 read-write P3 Output Data Status 3 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write PDSR Pin Data Status Register 0x0000003C 32 read-only P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P2 Output Data Status 2 1 read-only P3 Output Data Status 3 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only IER Interrupt Enable Register 0x00000040 32 write-only P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only IDR Interrupt Disable Register 0x00000044 32 write-only P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only IMR Interrupt Mask Register 0x00000048 32 read-only 0x00000000 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only ISR Interrupt Status Register 0x0000004C 32 read-only 0x00000000 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P2 Input Change Interrupt Status 2 1 read-only P3 Input Change Interrupt Status 3 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only MDER Multi-driver Enable Register 0x00000050 32 write-only P0 Multi Drive Enable. 0 1 write-only P1 Multi Drive Enable. 1 1 write-only P2 Multi Drive Enable. 2 1 write-only P3 Multi Drive Enable. 3 1 write-only P4 Multi Drive Enable. 4 1 write-only P5 Multi Drive Enable. 5 1 write-only P6 Multi Drive Enable. 6 1 write-only P7 Multi Drive Enable. 7 1 write-only P8 Multi Drive Enable. 8 1 write-only P9 Multi Drive Enable. 9 1 write-only P10 Multi Drive Enable. 10 1 write-only P11 Multi Drive Enable. 11 1 write-only P12 Multi Drive Enable. 12 1 write-only P13 Multi Drive Enable. 13 1 write-only P14 Multi Drive Enable. 14 1 write-only P15 Multi Drive Enable. 15 1 write-only P16 Multi Drive Enable. 16 1 write-only P17 Multi Drive Enable. 17 1 write-only P18 Multi Drive Enable. 18 1 write-only P19 Multi Drive Enable. 19 1 write-only P20 Multi Drive Enable. 20 1 write-only P21 Multi Drive Enable. 21 1 write-only P22 Multi Drive Enable. 22 1 write-only P23 Multi Drive Enable. 23 1 write-only P24 Multi Drive Enable. 24 1 write-only P25 Multi Drive Enable. 25 1 write-only P26 Multi Drive Enable. 26 1 write-only P27 Multi Drive Enable. 27 1 write-only P28 Multi Drive Enable. 28 1 write-only P29 Multi Drive Enable. 29 1 write-only P30 Multi Drive Enable. 30 1 write-only P31 Multi Drive Enable. 31 1 write-only MDDR Multi-driver Disable Register 0x00000054 32 write-only P0 Multi Drive Disable. 0 1 write-only P1 Multi Drive Disable. 1 1 write-only P2 Multi Drive Disable. 2 1 write-only P3 Multi Drive Disable. 3 1 write-only P4 Multi Drive Disable. 4 1 write-only P5 Multi Drive Disable. 5 1 write-only P6 Multi Drive Disable. 6 1 write-only P7 Multi Drive Disable. 7 1 write-only P8 Multi Drive Disable. 8 1 write-only P9 Multi Drive Disable. 9 1 write-only P10 Multi Drive Disable. 10 1 write-only P11 Multi Drive Disable. 11 1 write-only P12 Multi Drive Disable. 12 1 write-only P13 Multi Drive Disable. 13 1 write-only P14 Multi Drive Disable. 14 1 write-only P15 Multi Drive Disable. 15 1 write-only P16 Multi Drive Disable. 16 1 write-only P17 Multi Drive Disable. 17 1 write-only P18 Multi Drive Disable. 18 1 write-only P19 Multi Drive Disable. 19 1 write-only P20 Multi Drive Disable. 20 1 write-only P21 Multi Drive Disable. 21 1 write-only P22 Multi Drive Disable. 22 1 write-only P23 Multi Drive Disable. 23 1 write-only P24 Multi Drive Disable. 24 1 write-only P25 Multi Drive Disable. 25 1 write-only P26 Multi Drive Disable. 26 1 write-only P27 Multi Drive Disable. 27 1 write-only P28 Multi Drive Disable. 28 1 write-only P29 Multi Drive Disable. 29 1 write-only P30 Multi Drive Disable. 30 1 write-only P31 Multi Drive Disable. 31 1 write-only MDSR Multi-driver Status Register 0x00000058 32 read-only 0x00000000 P0 Multi Drive Status. 0 1 read-only P1 Multi Drive Status. 1 1 read-only P2 Multi Drive Status. 2 1 read-only P3 Multi Drive Status. 3 1 read-only P4 Multi Drive Status. 4 1 read-only P5 Multi Drive Status. 5 1 read-only P6 Multi Drive Status. 6 1 read-only P7 Multi Drive Status. 7 1 read-only P8 Multi Drive Status. 8 1 read-only P9 Multi Drive Status. 9 1 read-only P10 Multi Drive Status. 10 1 read-only P11 Multi Drive Status. 11 1 read-only P12 Multi Drive Status. 12 1 read-only P13 Multi Drive Status. 13 1 read-only P14 Multi Drive Status. 14 1 read-only P15 Multi Drive Status. 15 1 read-only P16 Multi Drive Status. 16 1 read-only P17 Multi Drive Status. 17 1 read-only P18 Multi Drive Status. 18 1 read-only P19 Multi Drive Status. 19 1 read-only P20 Multi Drive Status. 20 1 read-only P21 Multi Drive Status. 21 1 read-only P22 Multi Drive Status. 22 1 read-only P23 Multi Drive Status. 23 1 read-only P24 Multi Drive Status. 24 1 read-only P25 Multi Drive Status. 25 1 read-only P26 Multi Drive Status. 26 1 read-only P27 Multi Drive Status. 27 1 read-only P28 Multi Drive Status. 28 1 read-only P29 Multi Drive Status. 29 1 read-only P30 Multi Drive Status. 30 1 read-only P31 Multi Drive Status. 31 1 read-only PUDR Pull-up Disable Register 0x00000060 32 write-only P0 Pull Up Disable. 0 1 write-only P1 Pull Up Disable. 1 1 write-only P2 Pull Up Disable. 2 1 write-only P3 Pull Up Disable. 3 1 write-only P4 Pull Up Disable. 4 1 write-only P5 Pull Up Disable. 5 1 write-only P6 Pull Up Disable. 6 1 write-only P7 Pull Up Disable. 7 1 write-only P8 Pull Up Disable. 8 1 write-only P9 Pull Up Disable. 9 1 write-only P10 Pull Up Disable. 10 1 write-only P11 Pull Up Disable. 11 1 write-only P12 Pull Up Disable. 12 1 write-only P13 Pull Up Disable. 13 1 write-only P14 Pull Up Disable. 14 1 write-only P15 Pull Up Disable. 15 1 write-only P16 Pull Up Disable. 16 1 write-only P17 Pull Up Disable. 17 1 write-only P18 Pull Up Disable. 18 1 write-only P19 Pull Up Disable. 19 1 write-only P20 Pull Up Disable. 20 1 write-only P21 Pull Up Disable. 21 1 write-only P22 Pull Up Disable. 22 1 write-only P23 Pull Up Disable. 23 1 write-only P24 Pull Up Disable. 24 1 write-only P25 Pull Up Disable. 25 1 write-only P26 Pull Up Disable. 26 1 write-only P27 Pull Up Disable. 27 1 write-only P28 Pull Up Disable. 28 1 write-only P29 Pull Up Disable. 29 1 write-only P30 Pull Up Disable. 30 1 write-only P31 Pull Up Disable. 31 1 write-only PUER Pull-up Enable Register 0x00000064 32 write-only P0 Pull Up Enable. 0 1 write-only P1 Pull Up Enable. 1 1 write-only P2 Pull Up Enable. 2 1 write-only P3 Pull Up Enable. 3 1 write-only P4 Pull Up Enable. 4 1 write-only P5 Pull Up Enable. 5 1 write-only P6 Pull Up Enable. 6 1 write-only P7 Pull Up Enable. 7 1 write-only P8 Pull Up Enable. 8 1 write-only P9 Pull Up Enable. 9 1 write-only P10 Pull Up Enable. 10 1 write-only P11 Pull Up Enable. 11 1 write-only P12 Pull Up Enable. 12 1 write-only P13 Pull Up Enable. 13 1 write-only P14 Pull Up Enable. 14 1 write-only P15 Pull Up Enable. 15 1 write-only P16 Pull Up Enable. 16 1 write-only P17 Pull Up Enable. 17 1 write-only P18 Pull Up Enable. 18 1 write-only P19 Pull Up Enable. 19 1 write-only P20 Pull Up Enable. 20 1 write-only P21 Pull Up Enable. 21 1 write-only P22 Pull Up Enable. 22 1 write-only P23 Pull Up Enable. 23 1 write-only P24 Pull Up Enable. 24 1 write-only P25 Pull Up Enable. 25 1 write-only P26 Pull Up Enable. 26 1 write-only P27 Pull Up Enable. 27 1 write-only P28 Pull Up Enable. 28 1 write-only P29 Pull Up Enable. 29 1 write-only P30 Pull Up Enable. 30 1 write-only P31 Pull Up Enable. 31 1 write-only PUSR Pad Pull-up Status Register 0x00000068 32 read-only 0x00000000 P0 Pull Up Status. 0 1 read-only P1 Pull Up Status. 1 1 read-only P2 Pull Up Status. 2 1 read-only P3 Pull Up Status. 3 1 read-only P4 Pull Up Status. 4 1 read-only P5 Pull Up Status. 5 1 read-only P6 Pull Up Status. 6 1 read-only P7 Pull Up Status. 7 1 read-only P8 Pull Up Status. 8 1 read-only P9 Pull Up Status. 9 1 read-only P10 Pull Up Status. 10 1 read-only P11 Pull Up Status. 11 1 read-only P12 Pull Up Status. 12 1 read-only P13 Pull Up Status. 13 1 read-only P14 Pull Up Status. 14 1 read-only P15 Pull Up Status. 15 1 read-only P16 Pull Up Status. 16 1 read-only P17 Pull Up Status. 17 1 read-only P18 Pull Up Status. 18 1 read-only P19 Pull Up Status. 19 1 read-only P20 Pull Up Status. 20 1 read-only P21 Pull Up Status. 21 1 read-only P22 Pull Up Status. 22 1 read-only P23 Pull Up Status. 23 1 read-only P24 Pull Up Status. 24 1 read-only P25 Pull Up Status. 25 1 read-only P26 Pull Up Status. 26 1 read-only P27 Pull Up Status. 27 1 read-only P28 Pull Up Status. 28 1 read-only P29 Pull Up Status. 29 1 read-only P30 Pull Up Status. 30 1 read-only P31 Pull Up Status. 31 1 read-only ABSR Peripheral AB Select Register 0x00000070 32 read-write 0x00000000 P0 Peripheral A Select. 0 1 read-write P1 Peripheral A Select. 1 1 read-write P2 Peripheral A Select. 2 1 read-write P3 Peripheral A Select. 3 1 read-write P4 Peripheral A Select. 4 1 read-write P5 Peripheral A Select. 5 1 read-write P6 Peripheral A Select. 6 1 read-write P7 Peripheral A Select. 7 1 read-write P8 Peripheral A Select. 8 1 read-write P9 Peripheral A Select. 9 1 read-write P10 Peripheral A Select. 10 1 read-write P11 Peripheral A Select. 11 1 read-write P12 Peripheral A Select. 12 1 read-write P13 Peripheral A Select. 13 1 read-write P14 Peripheral A Select. 14 1 read-write P15 Peripheral A Select. 15 1 read-write P16 Peripheral A Select. 16 1 read-write P17 Peripheral A Select. 17 1 read-write P18 Peripheral A Select. 18 1 read-write P19 Peripheral A Select. 19 1 read-write P20 Peripheral A Select. 20 1 read-write P21 Peripheral A Select. 21 1 read-write P22 Peripheral A Select. 22 1 read-write P23 Peripheral A Select. 23 1 read-write P24 Peripheral A Select. 24 1 read-write P25 Peripheral A Select. 25 1 read-write P26 Peripheral A Select. 26 1 read-write P27 Peripheral A Select. 27 1 read-write P28 Peripheral A Select. 28 1 read-write P29 Peripheral A Select. 29 1 read-write P30 Peripheral A Select. 30 1 read-write P31 Peripheral A Select. 31 1 read-write SCIFSR System Clock Glitch Input Filter Select Register 0x00000080 32 write-only P0 System Clock Glitch Filtering Select. 0 1 write-only P1 System Clock Glitch Filtering Select. 1 1 write-only P2 System Clock Glitch Filtering Select. 2 1 write-only P3 System Clock Glitch Filtering Select. 3 1 write-only P4 System Clock Glitch Filtering Select. 4 1 write-only P5 System Clock Glitch Filtering Select. 5 1 write-only P6 System Clock Glitch Filtering Select. 6 1 write-only P7 System Clock Glitch Filtering Select. 7 1 write-only P8 System Clock Glitch Filtering Select. 8 1 write-only P9 System Clock Glitch Filtering Select. 9 1 write-only P10 System Clock Glitch Filtering Select. 10 1 write-only P11 System Clock Glitch Filtering Select. 11 1 write-only P12 System Clock Glitch Filtering Select. 12 1 write-only P13 System Clock Glitch Filtering Select. 13 1 write-only P14 System Clock Glitch Filtering Select. 14 1 write-only P15 System Clock Glitch Filtering Select. 15 1 write-only P16 System Clock Glitch Filtering Select. 16 1 write-only P17 System Clock Glitch Filtering Select. 17 1 write-only P18 System Clock Glitch Filtering Select. 18 1 write-only P19 System Clock Glitch Filtering Select. 19 1 write-only P20 System Clock Glitch Filtering Select. 20 1 write-only P21 System Clock Glitch Filtering Select. 21 1 write-only P22 System Clock Glitch Filtering Select. 22 1 write-only P23 System Clock Glitch Filtering Select. 23 1 write-only P24 System Clock Glitch Filtering Select. 24 1 write-only P25 System Clock Glitch Filtering Select. 25 1 write-only P26 System Clock Glitch Filtering Select. 26 1 write-only P27 System Clock Glitch Filtering Select. 27 1 write-only P28 System Clock Glitch Filtering Select. 28 1 write-only P29 System Clock Glitch Filtering Select. 29 1 write-only P30 System Clock Glitch Filtering Select. 30 1 write-only P31 System Clock Glitch Filtering Select. 31 1 write-only DIFSR Debouncing Input Filter Select Register 0x00000084 32 write-only P0 Debouncing Filtering Select. 0 1 write-only P1 Debouncing Filtering Select. 1 1 write-only P2 Debouncing Filtering Select. 2 1 write-only P3 Debouncing Filtering Select. 3 1 write-only P4 Debouncing Filtering Select. 4 1 write-only P5 Debouncing Filtering Select. 5 1 write-only P6 Debouncing Filtering Select. 6 1 write-only P7 Debouncing Filtering Select. 7 1 write-only P8 Debouncing Filtering Select. 8 1 write-only P9 Debouncing Filtering Select. 9 1 write-only P10 Debouncing Filtering Select. 10 1 write-only P11 Debouncing Filtering Select. 11 1 write-only P12 Debouncing Filtering Select. 12 1 write-only P13 Debouncing Filtering Select. 13 1 write-only P14 Debouncing Filtering Select. 14 1 write-only P15 Debouncing Filtering Select. 15 1 write-only P16 Debouncing Filtering Select. 16 1 write-only P17 Debouncing Filtering Select. 17 1 write-only P18 Debouncing Filtering Select. 18 1 write-only P19 Debouncing Filtering Select. 19 1 write-only P20 Debouncing Filtering Select. 20 1 write-only P21 Debouncing Filtering Select. 21 1 write-only P22 Debouncing Filtering Select. 22 1 write-only P23 Debouncing Filtering Select. 23 1 write-only P24 Debouncing Filtering Select. 24 1 write-only P25 Debouncing Filtering Select. 25 1 write-only P26 Debouncing Filtering Select. 26 1 write-only P27 Debouncing Filtering Select. 27 1 write-only P28 Debouncing Filtering Select. 28 1 write-only P29 Debouncing Filtering Select. 29 1 write-only P30 Debouncing Filtering Select. 30 1 write-only P31 Debouncing Filtering Select. 31 1 write-only IFDGSR Glitch or Debouncing Input Filter Clock Selection Status Register 0x00000088 32 read-only 0x00000000 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only SCDR Slow Clock Divider Debouncing Register 0x0000008C 32 read-write 0x00000000 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write OWER Output Write Enable 0x000000A0 32 write-only P0 Output Write Enable. 0 1 write-only P1 Output Write Enable. 1 1 write-only P2 Output Write Enable. 2 1 write-only P3 Output Write Enable. 3 1 write-only P4 Output Write Enable. 4 1 write-only P5 Output Write Enable. 5 1 write-only P6 Output Write Enable. 6 1 write-only P7 Output Write Enable. 7 1 write-only P8 Output Write Enable. 8 1 write-only P9 Output Write Enable. 9 1 write-only P10 Output Write Enable. 10 1 write-only P11 Output Write Enable. 11 1 write-only P12 Output Write Enable. 12 1 write-only P13 Output Write Enable. 13 1 write-only P14 Output Write Enable. 14 1 write-only P15 Output Write Enable. 15 1 write-only P16 Output Write Enable. 16 1 write-only P17 Output Write Enable. 17 1 write-only P18 Output Write Enable. 18 1 write-only P19 Output Write Enable. 19 1 write-only P20 Output Write Enable. 20 1 write-only P21 Output Write Enable. 21 1 write-only P22 Output Write Enable. 22 1 write-only P23 Output Write Enable. 23 1 write-only P24 Output Write Enable. 24 1 write-only P25 Output Write Enable. 25 1 write-only P26 Output Write Enable. 26 1 write-only P27 Output Write Enable. 27 1 write-only P28 Output Write Enable. 28 1 write-only P29 Output Write Enable. 29 1 write-only P30 Output Write Enable. 30 1 write-only P31 Output Write Enable. 31 1 write-only OWDR Output Write Disable 0x000000A4 32 write-only P0 Output Write Disable. 0 1 write-only P1 Output Write Disable. 1 1 write-only P2 Output Write Disable. 2 1 write-only P3 Output Write Disable. 3 1 write-only P4 Output Write Disable. 4 1 write-only P5 Output Write Disable. 5 1 write-only P6 Output Write Disable. 6 1 write-only P7 Output Write Disable. 7 1 write-only P8 Output Write Disable. 8 1 write-only P9 Output Write Disable. 9 1 write-only P10 Output Write Disable. 10 1 write-only P11 Output Write Disable. 11 1 write-only P12 Output Write Disable. 12 1 write-only P13 Output Write Disable. 13 1 write-only P14 Output Write Disable. 14 1 write-only P15 Output Write Disable. 15 1 write-only P16 Output Write Disable. 16 1 write-only P17 Output Write Disable. 17 1 write-only P18 Output Write Disable. 18 1 write-only P19 Output Write Disable. 19 1 write-only P20 Output Write Disable. 20 1 write-only P21 Output Write Disable. 21 1 write-only P22 Output Write Disable. 22 1 write-only P23 Output Write Disable. 23 1 write-only P24 Output Write Disable. 24 1 write-only P25 Output Write Disable. 25 1 write-only P26 Output Write Disable. 26 1 write-only P27 Output Write Disable. 27 1 write-only P28 Output Write Disable. 28 1 write-only P29 Output Write Disable. 29 1 write-only P30 Output Write Disable. 30 1 write-only P31 Output Write Disable. 31 1 write-only OWSR Output Write Status Register 0x000000A8 32 read-only 0x00000000 P0 Output Write Status. 0 1 read-only P1 Output Write Status. 1 1 read-only P2 Output Write Status. 2 1 read-only P3 Output Write Status. 3 1 read-only P4 Output Write Status. 4 1 read-only P5 Output Write Status. 5 1 read-only P6 Output Write Status. 6 1 read-only P7 Output Write Status. 7 1 read-only P8 Output Write Status. 8 1 read-only P9 Output Write Status. 9 1 read-only P10 Output Write Status. 10 1 read-only P11 Output Write Status. 11 1 read-only P12 Output Write Status. 12 1 read-only P13 Output Write Status. 13 1 read-only P14 Output Write Status. 14 1 read-only P15 Output Write Status. 15 1 read-only P16 Output Write Status. 16 1 read-only P17 Output Write Status. 17 1 read-only P18 Output Write Status. 18 1 read-only P19 Output Write Status. 19 1 read-only P20 Output Write Status. 20 1 read-only P21 Output Write Status. 21 1 read-only P22 Output Write Status. 22 1 read-only P23 Output Write Status. 23 1 read-only P24 Output Write Status. 24 1 read-only P25 Output Write Status. 25 1 read-only P26 Output Write Status. 26 1 read-only P27 Output Write Status. 27 1 read-only P28 Output Write Status. 28 1 read-only P29 Output Write Status. 29 1 read-only P30 Output Write Status. 30 1 read-only P31 Output Write Status. 31 1 read-only AIMER Additional Interrupt Modes Enable Register 0x000000B0 32 write-only P0 Additional Interrupt Modes Enable. 0 1 write-only P1 Additional Interrupt Modes Enable. 1 1 write-only P2 Additional Interrupt Modes Enable. 2 1 write-only P3 Additional Interrupt Modes Enable. 3 1 write-only P4 Additional Interrupt Modes Enable. 4 1 write-only P5 Additional Interrupt Modes Enable. 5 1 write-only P6 Additional Interrupt Modes Enable. 6 1 write-only P7 Additional Interrupt Modes Enable. 7 1 write-only P8 Additional Interrupt Modes Enable. 8 1 write-only P9 Additional Interrupt Modes Enable. 9 1 write-only P10 Additional Interrupt Modes Enable. 10 1 write-only P11 Additional Interrupt Modes Enable. 11 1 write-only P12 Additional Interrupt Modes Enable. 12 1 write-only P13 Additional Interrupt Modes Enable. 13 1 write-only P14 Additional Interrupt Modes Enable. 14 1 write-only P15 Additional Interrupt Modes Enable. 15 1 write-only P16 Additional Interrupt Modes Enable. 16 1 write-only P17 Additional Interrupt Modes Enable. 17 1 write-only P18 Additional Interrupt Modes Enable. 18 1 write-only P19 Additional Interrupt Modes Enable. 19 1 write-only P20 Additional Interrupt Modes Enable. 20 1 write-only P21 Additional Interrupt Modes Enable. 21 1 write-only P22 Additional Interrupt Modes Enable. 22 1 write-only P23 Additional Interrupt Modes Enable. 23 1 write-only P24 Additional Interrupt Modes Enable. 24 1 write-only P25 Additional Interrupt Modes Enable. 25 1 write-only P26 Additional Interrupt Modes Enable. 26 1 write-only P27 Additional Interrupt Modes Enable. 27 1 write-only P28 Additional Interrupt Modes Enable. 28 1 write-only P29 Additional Interrupt Modes Enable. 29 1 write-only P30 Additional Interrupt Modes Enable. 30 1 write-only P31 Additional Interrupt Modes Enable. 31 1 write-only AIMDR Additional Interrupt Modes Disables Register 0x000000B4 32 write-only P0 Additional Interrupt Modes Disable. 0 1 write-only P1 Additional Interrupt Modes Disable. 1 1 write-only P2 Additional Interrupt Modes Disable. 2 1 write-only P3 Additional Interrupt Modes Disable. 3 1 write-only P4 Additional Interrupt Modes Disable. 4 1 write-only P5 Additional Interrupt Modes Disable. 5 1 write-only P6 Additional Interrupt Modes Disable. 6 1 write-only P7 Additional Interrupt Modes Disable. 7 1 write-only P8 Additional Interrupt Modes Disable. 8 1 write-only P9 Additional Interrupt Modes Disable. 9 1 write-only P10 Additional Interrupt Modes Disable. 10 1 write-only P11 Additional Interrupt Modes Disable. 11 1 write-only P12 Additional Interrupt Modes Disable. 12 1 write-only P13 Additional Interrupt Modes Disable. 13 1 write-only P14 Additional Interrupt Modes Disable. 14 1 write-only P15 Additional Interrupt Modes Disable. 15 1 write-only P16 Additional Interrupt Modes Disable. 16 1 write-only P17 Additional Interrupt Modes Disable. 17 1 write-only P18 Additional Interrupt Modes Disable. 18 1 write-only P19 Additional Interrupt Modes Disable. 19 1 write-only P20 Additional Interrupt Modes Disable. 20 1 write-only P21 Additional Interrupt Modes Disable. 21 1 write-only P22 Additional Interrupt Modes Disable. 22 1 write-only P23 Additional Interrupt Modes Disable. 23 1 write-only P24 Additional Interrupt Modes Disable. 24 1 write-only P25 Additional Interrupt Modes Disable. 25 1 write-only P26 Additional Interrupt Modes Disable. 26 1 write-only P27 Additional Interrupt Modes Disable. 27 1 write-only P28 Additional Interrupt Modes Disable. 28 1 write-only P29 Additional Interrupt Modes Disable. 29 1 write-only P30 Additional Interrupt Modes Disable. 30 1 write-only P31 Additional Interrupt Modes Disable. 31 1 write-only AIMMR Additional Interrupt Modes Mask Register 0x000000B8 32 read-only 0x00000000 P0 Peripheral CD Status. 0 1 read-only P1 Peripheral CD Status. 1 1 read-only P2 Peripheral CD Status. 2 1 read-only P3 Peripheral CD Status. 3 1 read-only P4 Peripheral CD Status. 4 1 read-only P5 Peripheral CD Status. 5 1 read-only P6 Peripheral CD Status. 6 1 read-only P7 Peripheral CD Status. 7 1 read-only P8 Peripheral CD Status. 8 1 read-only P9 Peripheral CD Status. 9 1 read-only P10 Peripheral CD Status. 10 1 read-only P11 Peripheral CD Status. 11 1 read-only P12 Peripheral CD Status. 12 1 read-only P13 Peripheral CD Status. 13 1 read-only P14 Peripheral CD Status. 14 1 read-only P15 Peripheral CD Status. 15 1 read-only P16 Peripheral CD Status. 16 1 read-only P17 Peripheral CD Status. 17 1 read-only P18 Peripheral CD Status. 18 1 read-only P19 Peripheral CD Status. 19 1 read-only P20 Peripheral CD Status. 20 1 read-only P21 Peripheral CD Status. 21 1 read-only P22 Peripheral CD Status. 22 1 read-only P23 Peripheral CD Status. 23 1 read-only P24 Peripheral CD Status. 24 1 read-only P25 Peripheral CD Status. 25 1 read-only P26 Peripheral CD Status. 26 1 read-only P27 Peripheral CD Status. 27 1 read-only P28 Peripheral CD Status. 28 1 read-only P29 Peripheral CD Status. 29 1 read-only P30 Peripheral CD Status. 30 1 read-only P31 Peripheral CD Status. 31 1 read-only ESR Edge Select Register 0x000000C0 32 write-only P0 Edge Interrupt Selection. 0 1 write-only P1 Edge Interrupt Selection. 1 1 write-only P2 Edge Interrupt Selection. 2 1 write-only P3 Edge Interrupt Selection. 3 1 write-only P4 Edge Interrupt Selection. 4 1 write-only P5 Edge Interrupt Selection. 5 1 write-only P6 Edge Interrupt Selection. 6 1 write-only P7 Edge Interrupt Selection. 7 1 write-only P8 Edge Interrupt Selection. 8 1 write-only P9 Edge Interrupt Selection. 9 1 write-only P10 Edge Interrupt Selection. 10 1 write-only P11 Edge Interrupt Selection. 11 1 write-only P12 Edge Interrupt Selection. 12 1 write-only P13 Edge Interrupt Selection. 13 1 write-only P14 Edge Interrupt Selection. 14 1 write-only P15 Edge Interrupt Selection. 15 1 write-only P16 Edge Interrupt Selection. 16 1 write-only P17 Edge Interrupt Selection. 17 1 write-only P18 Edge Interrupt Selection. 18 1 write-only P19 Edge Interrupt Selection. 19 1 write-only P20 Edge Interrupt Selection. 20 1 write-only P21 Edge Interrupt Selection. 21 1 write-only P22 Edge Interrupt Selection. 22 1 write-only P23 Edge Interrupt Selection. 23 1 write-only P24 Edge Interrupt Selection. 24 1 write-only P25 Edge Interrupt Selection. 25 1 write-only P26 Edge Interrupt Selection. 26 1 write-only P27 Edge Interrupt Selection. 27 1 write-only P28 Edge Interrupt Selection. 28 1 write-only P29 Edge Interrupt Selection. 29 1 write-only P30 Edge Interrupt Selection. 30 1 write-only P31 Edge Interrupt Selection. 31 1 write-only LSR Level Select Register 0x000000C4 32 write-only P0 Level Interrupt Selection. 0 1 write-only P1 Level Interrupt Selection. 1 1 write-only P2 Level Interrupt Selection. 2 1 write-only P3 Level Interrupt Selection. 3 1 write-only P4 Level Interrupt Selection. 4 1 write-only P5 Level Interrupt Selection. 5 1 write-only P6 Level Interrupt Selection. 6 1 write-only P7 Level Interrupt Selection. 7 1 write-only P8 Level Interrupt Selection. 8 1 write-only P9 Level Interrupt Selection. 9 1 write-only P10 Level Interrupt Selection. 10 1 write-only P11 Level Interrupt Selection. 11 1 write-only P12 Level Interrupt Selection. 12 1 write-only P13 Level Interrupt Selection. 13 1 write-only P14 Level Interrupt Selection. 14 1 write-only P15 Level Interrupt Selection. 15 1 write-only P16 Level Interrupt Selection. 16 1 write-only P17 Level Interrupt Selection. 17 1 write-only P18 Level Interrupt Selection. 18 1 write-only P19 Level Interrupt Selection. 19 1 write-only P20 Level Interrupt Selection. 20 1 write-only P21 Level Interrupt Selection. 21 1 write-only P22 Level Interrupt Selection. 22 1 write-only P23 Level Interrupt Selection. 23 1 write-only P24 Level Interrupt Selection. 24 1 write-only P25 Level Interrupt Selection. 25 1 write-only P26 Level Interrupt Selection. 26 1 write-only P27 Level Interrupt Selection. 27 1 write-only P28 Level Interrupt Selection. 28 1 write-only P29 Level Interrupt Selection. 29 1 write-only P30 Level Interrupt Selection. 30 1 write-only P31 Level Interrupt Selection. 31 1 write-only ELSR Edge/Level Status Register 0x000000C8 32 read-only 0x00000000 P0 Edge/Level Interrupt source selection. 0 1 read-only P1 Edge/Level Interrupt source selection. 1 1 read-only P2 Edge/Level Interrupt source selection. 2 1 read-only P3 Edge/Level Interrupt source selection. 3 1 read-only P4 Edge/Level Interrupt source selection. 4 1 read-only P5 Edge/Level Interrupt source selection. 5 1 read-only P6 Edge/Level Interrupt source selection. 6 1 read-only P7 Edge/Level Interrupt source selection. 7 1 read-only P8 Edge/Level Interrupt source selection. 8 1 read-only P9 Edge/Level Interrupt source selection. 9 1 read-only P10 Edge/Level Interrupt source selection. 10 1 read-only P11 Edge/Level Interrupt source selection. 11 1 read-only P12 Edge/Level Interrupt source selection. 12 1 read-only P13 Edge/Level Interrupt source selection. 13 1 read-only P14 Edge/Level Interrupt source selection. 14 1 read-only P15 Edge/Level Interrupt source selection. 15 1 read-only P16 Edge/Level Interrupt source selection. 16 1 read-only P17 Edge/Level Interrupt source selection. 17 1 read-only P18 Edge/Level Interrupt source selection. 18 1 read-only P19 Edge/Level Interrupt source selection. 19 1 read-only P20 Edge/Level Interrupt source selection. 20 1 read-only P21 Edge/Level Interrupt source selection. 21 1 read-only P22 Edge/Level Interrupt source selection. 22 1 read-only P23 Edge/Level Interrupt source selection. 23 1 read-only P24 Edge/Level Interrupt source selection. 24 1 read-only P25 Edge/Level Interrupt source selection. 25 1 read-only P26 Edge/Level Interrupt source selection. 26 1 read-only P27 Edge/Level Interrupt source selection. 27 1 read-only P28 Edge/Level Interrupt source selection. 28 1 read-only P29 Edge/Level Interrupt source selection. 29 1 read-only P30 Edge/Level Interrupt source selection. 30 1 read-only P31 Edge/Level Interrupt source selection. 31 1 read-only FELLSR Falling Edge/Low Level Select Register 0x000000D0 32 write-only P0 Falling Edge/Low Level Interrupt Selection. 0 1 write-only P1 Falling Edge/Low Level Interrupt Selection. 1 1 write-only P2 Falling Edge/Low Level Interrupt Selection. 2 1 write-only P3 Falling Edge/Low Level Interrupt Selection. 3 1 write-only P4 Falling Edge/Low Level Interrupt Selection. 4 1 write-only P5 Falling Edge/Low Level Interrupt Selection. 5 1 write-only P6 Falling Edge/Low Level Interrupt Selection. 6 1 write-only P7 Falling Edge/Low Level Interrupt Selection. 7 1 write-only P8 Falling Edge/Low Level Interrupt Selection. 8 1 write-only P9 Falling Edge/Low Level Interrupt Selection. 9 1 write-only P10 Falling Edge/Low Level Interrupt Selection. 10 1 write-only P11 Falling Edge/Low Level Interrupt Selection. 11 1 write-only P12 Falling Edge/Low Level Interrupt Selection. 12 1 write-only P13 Falling Edge/Low Level Interrupt Selection. 13 1 write-only P14 Falling Edge/Low Level Interrupt Selection. 14 1 write-only P15 Falling Edge/Low Level Interrupt Selection. 15 1 write-only P16 Falling Edge/Low Level Interrupt Selection. 16 1 write-only P17 Falling Edge/Low Level Interrupt Selection. 17 1 write-only P18 Falling Edge/Low Level Interrupt Selection. 18 1 write-only P19 Falling Edge/Low Level Interrupt Selection. 19 1 write-only P20 Falling Edge/Low Level Interrupt Selection. 20 1 write-only P21 Falling Edge/Low Level Interrupt Selection. 21 1 write-only P22 Falling Edge/Low Level Interrupt Selection. 22 1 write-only P23 Falling Edge/Low Level Interrupt Selection. 23 1 write-only P24 Falling Edge/Low Level Interrupt Selection. 24 1 write-only P25 Falling Edge/Low Level Interrupt Selection. 25 1 write-only P26 Falling Edge/Low Level Interrupt Selection. 26 1 write-only P27 Falling Edge/Low Level Interrupt Selection. 27 1 write-only P28 Falling Edge/Low Level Interrupt Selection. 28 1 write-only P29 Falling Edge/Low Level Interrupt Selection. 29 1 write-only P30 Falling Edge/Low Level Interrupt Selection. 30 1 write-only P31 Falling Edge/Low Level Interrupt Selection. 31 1 write-only REHLSR Rising Edge/ High Level Select Register 0x000000D4 32 write-only P0 Rising Edge /High Level Interrupt Selection. 0 1 write-only P1 Rising Edge /High Level Interrupt Selection. 1 1 write-only P2 Rising Edge /High Level Interrupt Selection. 2 1 write-only P3 Rising Edge /High Level Interrupt Selection. 3 1 write-only P4 Rising Edge /High Level Interrupt Selection. 4 1 write-only P5 Rising Edge /High Level Interrupt Selection. 5 1 write-only P6 Rising Edge /High Level Interrupt Selection. 6 1 write-only P7 Rising Edge /High Level Interrupt Selection. 7 1 write-only P8 Rising Edge /High Level Interrupt Selection. 8 1 write-only P9 Rising Edge /High Level Interrupt Selection. 9 1 write-only P10 Rising Edge /High Level Interrupt Selection. 10 1 write-only P11 Rising Edge /High Level Interrupt Selection. 11 1 write-only P12 Rising Edge /High Level Interrupt Selection. 12 1 write-only P13 Rising Edge /High Level Interrupt Selection. 13 1 write-only P14 Rising Edge /High Level Interrupt Selection. 14 1 write-only P15 Rising Edge /High Level Interrupt Selection. 15 1 write-only P16 Rising Edge /High Level Interrupt Selection. 16 1 write-only P17 Rising Edge /High Level Interrupt Selection. 17 1 write-only P18 Rising Edge /High Level Interrupt Selection. 18 1 write-only P19 Rising Edge /High Level Interrupt Selection. 19 1 write-only P20 Rising Edge /High Level Interrupt Selection. 20 1 write-only P21 Rising Edge /High Level Interrupt Selection. 21 1 write-only P22 Rising Edge /High Level Interrupt Selection. 22 1 write-only P23 Rising Edge /High Level Interrupt Selection. 23 1 write-only P24 Rising Edge /High Level Interrupt Selection. 24 1 write-only P25 Rising Edge /High Level Interrupt Selection. 25 1 write-only P26 Rising Edge /High Level Interrupt Selection. 26 1 write-only P27 Rising Edge /High Level Interrupt Selection. 27 1 write-only P28 Rising Edge /High Level Interrupt Selection. 28 1 write-only P29 Rising Edge /High Level Interrupt Selection. 29 1 write-only P30 Rising Edge /High Level Interrupt Selection. 30 1 write-only P31 Rising Edge /High Level Interrupt Selection. 31 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0x000000D8 32 read-only 0x00000000 P0 Edge /Level Interrupt Source Selection. 0 1 read-only P1 Edge /Level Interrupt Source Selection. 1 1 read-only P2 Edge /Level Interrupt Source Selection. 2 1 read-only P3 Edge /Level Interrupt Source Selection. 3 1 read-only P4 Edge /Level Interrupt Source Selection. 4 1 read-only P5 Edge /Level Interrupt Source Selection. 5 1 read-only P6 Edge /Level Interrupt Source Selection. 6 1 read-only P7 Edge /Level Interrupt Source Selection. 7 1 read-only P8 Edge /Level Interrupt Source Selection. 8 1 read-only P9 Edge /Level Interrupt Source Selection. 9 1 read-only P10 Edge /Level Interrupt Source Selection. 10 1 read-only P11 Edge /Level Interrupt Source Selection. 11 1 read-only P12 Edge /Level Interrupt Source Selection. 12 1 read-only P13 Edge /Level Interrupt Source Selection. 13 1 read-only P14 Edge /Level Interrupt Source Selection. 14 1 read-only P15 Edge /Level Interrupt Source Selection. 15 1 read-only P16 Edge /Level Interrupt Source Selection. 16 1 read-only P17 Edge /Level Interrupt Source Selection. 17 1 read-only P18 Edge /Level Interrupt Source Selection. 18 1 read-only P19 Edge /Level Interrupt Source Selection. 19 1 read-only P20 Edge /Level Interrupt Source Selection. 20 1 read-only P21 Edge /Level Interrupt Source Selection. 21 1 read-only P22 Edge /Level Interrupt Source Selection. 22 1 read-only P23 Edge /Level Interrupt Source Selection. 23 1 read-only P24 Edge /Level Interrupt Source Selection. 24 1 read-only P25 Edge /Level Interrupt Source Selection. 25 1 read-only P26 Edge /Level Interrupt Source Selection. 26 1 read-only P27 Edge /Level Interrupt Source Selection. 27 1 read-only P28 Edge /Level Interrupt Source Selection. 28 1 read-only P29 Edge /Level Interrupt Source Selection. 29 1 read-only P30 Edge /Level Interrupt Source Selection. 30 1 read-only P31 Edge /Level Interrupt Source Selection. 31 1 read-only LOCKSR Lock Status 0x000000E0 32 read-only 0x00000000 P0 Lock Status. 0 1 read-only P1 Lock Status. 1 1 read-only P2 Lock Status. 2 1 read-only P3 Lock Status. 3 1 read-only P4 Lock Status. 4 1 read-only P5 Lock Status. 5 1 read-only P6 Lock Status. 6 1 read-only P7 Lock Status. 7 1 read-only P8 Lock Status. 8 1 read-only P9 Lock Status. 9 1 read-only P10 Lock Status. 10 1 read-only P11 Lock Status. 11 1 read-only P12 Lock Status. 12 1 read-only P13 Lock Status. 13 1 read-only P14 Lock Status. 14 1 read-only P15 Lock Status. 15 1 read-only P16 Lock Status. 16 1 read-only P17 Lock Status. 17 1 read-only P18 Lock Status. 18 1 read-only P19 Lock Status. 19 1 read-only P20 Lock Status. 20 1 read-only P21 Lock Status. 21 1 read-only P22 Lock Status. 22 1 read-only P23 Lock Status. 23 1 read-only P24 Lock Status. 24 1 read-only P25 Lock Status. 25 1 read-only P26 Lock Status. 26 1 read-only P27 Lock Status. 27 1 read-only P28 Lock Status. 28 1 read-only P29 Lock Status. 29 1 read-only P30 Lock Status. 30 1 read-only P31 Lock Status. 31 1 read-only WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PIOC 6315C Parallel Input/Output Controller C PIO PIOC_ 0x400E1200 0 0x200 registers PIOC 13 PER PIO Enable Register 0x00000000 32 write-only P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P2 PIO Enable 2 1 write-only P3 PIO Enable 3 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only PDR PIO Disable Register 0x00000004 32 write-only P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P2 PIO Disable 2 1 write-only P3 PIO Disable 3 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only PSR PIO Status Register 0x00000008 32 read-only P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P2 PIO Status 2 1 read-only P3 PIO Status 3 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only OER Output Enable Register 0x00000010 32 write-only P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P2 Output Enable 2 1 write-only P3 Output Enable 3 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only ODR Output Disable Register 0x00000014 32 write-only P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P2 Output Disable 2 1 write-only P3 Output Disable 3 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only OSR Output Status Register 0x00000018 32 read-only 0x00000000 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P2 Output Status 2 1 read-only P3 Output Status 3 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only IFER Glitch Input Filter Enable Register 0x00000020 32 write-only P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P2 Input Filter Enable 2 1 write-only P3 Input Filter Enable 3 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only IFDR Glitch Input Filter Disable Register 0x00000024 32 write-only P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P2 Input Filter Disable 2 1 write-only P3 Input Filter Disable 3 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only IFSR Glitch Input Filter Status Register 0x00000028 32 read-only 0x00000000 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P2 Input Filer Status 2 1 read-only P3 Input Filer Status 3 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only SODR Set Output Data Register 0x00000030 32 write-only P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P2 Set Output Data 2 1 write-only P3 Set Output Data 3 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only CODR Clear Output Data Register 0x00000034 32 write-only P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P2 Clear Output Data 2 1 write-only P3 Clear Output Data 3 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only ODSR Output Data Status Register 0x00000038 32 read-write P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P2 Output Data Status 2 1 read-write P3 Output Data Status 3 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write PDSR Pin Data Status Register 0x0000003C 32 read-only P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P2 Output Data Status 2 1 read-only P3 Output Data Status 3 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only IER Interrupt Enable Register 0x00000040 32 write-only P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only IDR Interrupt Disable Register 0x00000044 32 write-only P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only IMR Interrupt Mask Register 0x00000048 32 read-only 0x00000000 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only ISR Interrupt Status Register 0x0000004C 32 read-only 0x00000000 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P2 Input Change Interrupt Status 2 1 read-only P3 Input Change Interrupt Status 3 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only MDER Multi-driver Enable Register 0x00000050 32 write-only P0 Multi Drive Enable. 0 1 write-only P1 Multi Drive Enable. 1 1 write-only P2 Multi Drive Enable. 2 1 write-only P3 Multi Drive Enable. 3 1 write-only P4 Multi Drive Enable. 4 1 write-only P5 Multi Drive Enable. 5 1 write-only P6 Multi Drive Enable. 6 1 write-only P7 Multi Drive Enable. 7 1 write-only P8 Multi Drive Enable. 8 1 write-only P9 Multi Drive Enable. 9 1 write-only P10 Multi Drive Enable. 10 1 write-only P11 Multi Drive Enable. 11 1 write-only P12 Multi Drive Enable. 12 1 write-only P13 Multi Drive Enable. 13 1 write-only P14 Multi Drive Enable. 14 1 write-only P15 Multi Drive Enable. 15 1 write-only P16 Multi Drive Enable. 16 1 write-only P17 Multi Drive Enable. 17 1 write-only P18 Multi Drive Enable. 18 1 write-only P19 Multi Drive Enable. 19 1 write-only P20 Multi Drive Enable. 20 1 write-only P21 Multi Drive Enable. 21 1 write-only P22 Multi Drive Enable. 22 1 write-only P23 Multi Drive Enable. 23 1 write-only P24 Multi Drive Enable. 24 1 write-only P25 Multi Drive Enable. 25 1 write-only P26 Multi Drive Enable. 26 1 write-only P27 Multi Drive Enable. 27 1 write-only P28 Multi Drive Enable. 28 1 write-only P29 Multi Drive Enable. 29 1 write-only P30 Multi Drive Enable. 30 1 write-only P31 Multi Drive Enable. 31 1 write-only MDDR Multi-driver Disable Register 0x00000054 32 write-only P0 Multi Drive Disable. 0 1 write-only P1 Multi Drive Disable. 1 1 write-only P2 Multi Drive Disable. 2 1 write-only P3 Multi Drive Disable. 3 1 write-only P4 Multi Drive Disable. 4 1 write-only P5 Multi Drive Disable. 5 1 write-only P6 Multi Drive Disable. 6 1 write-only P7 Multi Drive Disable. 7 1 write-only P8 Multi Drive Disable. 8 1 write-only P9 Multi Drive Disable. 9 1 write-only P10 Multi Drive Disable. 10 1 write-only P11 Multi Drive Disable. 11 1 write-only P12 Multi Drive Disable. 12 1 write-only P13 Multi Drive Disable. 13 1 write-only P14 Multi Drive Disable. 14 1 write-only P15 Multi Drive Disable. 15 1 write-only P16 Multi Drive Disable. 16 1 write-only P17 Multi Drive Disable. 17 1 write-only P18 Multi Drive Disable. 18 1 write-only P19 Multi Drive Disable. 19 1 write-only P20 Multi Drive Disable. 20 1 write-only P21 Multi Drive Disable. 21 1 write-only P22 Multi Drive Disable. 22 1 write-only P23 Multi Drive Disable. 23 1 write-only P24 Multi Drive Disable. 24 1 write-only P25 Multi Drive Disable. 25 1 write-only P26 Multi Drive Disable. 26 1 write-only P27 Multi Drive Disable. 27 1 write-only P28 Multi Drive Disable. 28 1 write-only P29 Multi Drive Disable. 29 1 write-only P30 Multi Drive Disable. 30 1 write-only P31 Multi Drive Disable. 31 1 write-only MDSR Multi-driver Status Register 0x00000058 32 read-only 0x00000000 P0 Multi Drive Status. 0 1 read-only P1 Multi Drive Status. 1 1 read-only P2 Multi Drive Status. 2 1 read-only P3 Multi Drive Status. 3 1 read-only P4 Multi Drive Status. 4 1 read-only P5 Multi Drive Status. 5 1 read-only P6 Multi Drive Status. 6 1 read-only P7 Multi Drive Status. 7 1 read-only P8 Multi Drive Status. 8 1 read-only P9 Multi Drive Status. 9 1 read-only P10 Multi Drive Status. 10 1 read-only P11 Multi Drive Status. 11 1 read-only P12 Multi Drive Status. 12 1 read-only P13 Multi Drive Status. 13 1 read-only P14 Multi Drive Status. 14 1 read-only P15 Multi Drive Status. 15 1 read-only P16 Multi Drive Status. 16 1 read-only P17 Multi Drive Status. 17 1 read-only P18 Multi Drive Status. 18 1 read-only P19 Multi Drive Status. 19 1 read-only P20 Multi Drive Status. 20 1 read-only P21 Multi Drive Status. 21 1 read-only P22 Multi Drive Status. 22 1 read-only P23 Multi Drive Status. 23 1 read-only P24 Multi Drive Status. 24 1 read-only P25 Multi Drive Status. 25 1 read-only P26 Multi Drive Status. 26 1 read-only P27 Multi Drive Status. 27 1 read-only P28 Multi Drive Status. 28 1 read-only P29 Multi Drive Status. 29 1 read-only P30 Multi Drive Status. 30 1 read-only P31 Multi Drive Status. 31 1 read-only PUDR Pull-up Disable Register 0x00000060 32 write-only P0 Pull Up Disable. 0 1 write-only P1 Pull Up Disable. 1 1 write-only P2 Pull Up Disable. 2 1 write-only P3 Pull Up Disable. 3 1 write-only P4 Pull Up Disable. 4 1 write-only P5 Pull Up Disable. 5 1 write-only P6 Pull Up Disable. 6 1 write-only P7 Pull Up Disable. 7 1 write-only P8 Pull Up Disable. 8 1 write-only P9 Pull Up Disable. 9 1 write-only P10 Pull Up Disable. 10 1 write-only P11 Pull Up Disable. 11 1 write-only P12 Pull Up Disable. 12 1 write-only P13 Pull Up Disable. 13 1 write-only P14 Pull Up Disable. 14 1 write-only P15 Pull Up Disable. 15 1 write-only P16 Pull Up Disable. 16 1 write-only P17 Pull Up Disable. 17 1 write-only P18 Pull Up Disable. 18 1 write-only P19 Pull Up Disable. 19 1 write-only P20 Pull Up Disable. 20 1 write-only P21 Pull Up Disable. 21 1 write-only P22 Pull Up Disable. 22 1 write-only P23 Pull Up Disable. 23 1 write-only P24 Pull Up Disable. 24 1 write-only P25 Pull Up Disable. 25 1 write-only P26 Pull Up Disable. 26 1 write-only P27 Pull Up Disable. 27 1 write-only P28 Pull Up Disable. 28 1 write-only P29 Pull Up Disable. 29 1 write-only P30 Pull Up Disable. 30 1 write-only P31 Pull Up Disable. 31 1 write-only PUER Pull-up Enable Register 0x00000064 32 write-only P0 Pull Up Enable. 0 1 write-only P1 Pull Up Enable. 1 1 write-only P2 Pull Up Enable. 2 1 write-only P3 Pull Up Enable. 3 1 write-only P4 Pull Up Enable. 4 1 write-only P5 Pull Up Enable. 5 1 write-only P6 Pull Up Enable. 6 1 write-only P7 Pull Up Enable. 7 1 write-only P8 Pull Up Enable. 8 1 write-only P9 Pull Up Enable. 9 1 write-only P10 Pull Up Enable. 10 1 write-only P11 Pull Up Enable. 11 1 write-only P12 Pull Up Enable. 12 1 write-only P13 Pull Up Enable. 13 1 write-only P14 Pull Up Enable. 14 1 write-only P15 Pull Up Enable. 15 1 write-only P16 Pull Up Enable. 16 1 write-only P17 Pull Up Enable. 17 1 write-only P18 Pull Up Enable. 18 1 write-only P19 Pull Up Enable. 19 1 write-only P20 Pull Up Enable. 20 1 write-only P21 Pull Up Enable. 21 1 write-only P22 Pull Up Enable. 22 1 write-only P23 Pull Up Enable. 23 1 write-only P24 Pull Up Enable. 24 1 write-only P25 Pull Up Enable. 25 1 write-only P26 Pull Up Enable. 26 1 write-only P27 Pull Up Enable. 27 1 write-only P28 Pull Up Enable. 28 1 write-only P29 Pull Up Enable. 29 1 write-only P30 Pull Up Enable. 30 1 write-only P31 Pull Up Enable. 31 1 write-only PUSR Pad Pull-up Status Register 0x00000068 32 read-only 0x00000000 P0 Pull Up Status. 0 1 read-only P1 Pull Up Status. 1 1 read-only P2 Pull Up Status. 2 1 read-only P3 Pull Up Status. 3 1 read-only P4 Pull Up Status. 4 1 read-only P5 Pull Up Status. 5 1 read-only P6 Pull Up Status. 6 1 read-only P7 Pull Up Status. 7 1 read-only P8 Pull Up Status. 8 1 read-only P9 Pull Up Status. 9 1 read-only P10 Pull Up Status. 10 1 read-only P11 Pull Up Status. 11 1 read-only P12 Pull Up Status. 12 1 read-only P13 Pull Up Status. 13 1 read-only P14 Pull Up Status. 14 1 read-only P15 Pull Up Status. 15 1 read-only P16 Pull Up Status. 16 1 read-only P17 Pull Up Status. 17 1 read-only P18 Pull Up Status. 18 1 read-only P19 Pull Up Status. 19 1 read-only P20 Pull Up Status. 20 1 read-only P21 Pull Up Status. 21 1 read-only P22 Pull Up Status. 22 1 read-only P23 Pull Up Status. 23 1 read-only P24 Pull Up Status. 24 1 read-only P25 Pull Up Status. 25 1 read-only P26 Pull Up Status. 26 1 read-only P27 Pull Up Status. 27 1 read-only P28 Pull Up Status. 28 1 read-only P29 Pull Up Status. 29 1 read-only P30 Pull Up Status. 30 1 read-only P31 Pull Up Status. 31 1 read-only ABSR Peripheral AB Select Register 0x00000070 32 read-write 0x00000000 P0 Peripheral A Select. 0 1 read-write P1 Peripheral A Select. 1 1 read-write P2 Peripheral A Select. 2 1 read-write P3 Peripheral A Select. 3 1 read-write P4 Peripheral A Select. 4 1 read-write P5 Peripheral A Select. 5 1 read-write P6 Peripheral A Select. 6 1 read-write P7 Peripheral A Select. 7 1 read-write P8 Peripheral A Select. 8 1 read-write P9 Peripheral A Select. 9 1 read-write P10 Peripheral A Select. 10 1 read-write P11 Peripheral A Select. 11 1 read-write P12 Peripheral A Select. 12 1 read-write P13 Peripheral A Select. 13 1 read-write P14 Peripheral A Select. 14 1 read-write P15 Peripheral A Select. 15 1 read-write P16 Peripheral A Select. 16 1 read-write P17 Peripheral A Select. 17 1 read-write P18 Peripheral A Select. 18 1 read-write P19 Peripheral A Select. 19 1 read-write P20 Peripheral A Select. 20 1 read-write P21 Peripheral A Select. 21 1 read-write P22 Peripheral A Select. 22 1 read-write P23 Peripheral A Select. 23 1 read-write P24 Peripheral A Select. 24 1 read-write P25 Peripheral A Select. 25 1 read-write P26 Peripheral A Select. 26 1 read-write P27 Peripheral A Select. 27 1 read-write P28 Peripheral A Select. 28 1 read-write P29 Peripheral A Select. 29 1 read-write P30 Peripheral A Select. 30 1 read-write P31 Peripheral A Select. 31 1 read-write SCIFSR System Clock Glitch Input Filter Select Register 0x00000080 32 write-only P0 System Clock Glitch Filtering Select. 0 1 write-only P1 System Clock Glitch Filtering Select. 1 1 write-only P2 System Clock Glitch Filtering Select. 2 1 write-only P3 System Clock Glitch Filtering Select. 3 1 write-only P4 System Clock Glitch Filtering Select. 4 1 write-only P5 System Clock Glitch Filtering Select. 5 1 write-only P6 System Clock Glitch Filtering Select. 6 1 write-only P7 System Clock Glitch Filtering Select. 7 1 write-only P8 System Clock Glitch Filtering Select. 8 1 write-only P9 System Clock Glitch Filtering Select. 9 1 write-only P10 System Clock Glitch Filtering Select. 10 1 write-only P11 System Clock Glitch Filtering Select. 11 1 write-only P12 System Clock Glitch Filtering Select. 12 1 write-only P13 System Clock Glitch Filtering Select. 13 1 write-only P14 System Clock Glitch Filtering Select. 14 1 write-only P15 System Clock Glitch Filtering Select. 15 1 write-only P16 System Clock Glitch Filtering Select. 16 1 write-only P17 System Clock Glitch Filtering Select. 17 1 write-only P18 System Clock Glitch Filtering Select. 18 1 write-only P19 System Clock Glitch Filtering Select. 19 1 write-only P20 System Clock Glitch Filtering Select. 20 1 write-only P21 System Clock Glitch Filtering Select. 21 1 write-only P22 System Clock Glitch Filtering Select. 22 1 write-only P23 System Clock Glitch Filtering Select. 23 1 write-only P24 System Clock Glitch Filtering Select. 24 1 write-only P25 System Clock Glitch Filtering Select. 25 1 write-only P26 System Clock Glitch Filtering Select. 26 1 write-only P27 System Clock Glitch Filtering Select. 27 1 write-only P28 System Clock Glitch Filtering Select. 28 1 write-only P29 System Clock Glitch Filtering Select. 29 1 write-only P30 System Clock Glitch Filtering Select. 30 1 write-only P31 System Clock Glitch Filtering Select. 31 1 write-only DIFSR Debouncing Input Filter Select Register 0x00000084 32 write-only P0 Debouncing Filtering Select. 0 1 write-only P1 Debouncing Filtering Select. 1 1 write-only P2 Debouncing Filtering Select. 2 1 write-only P3 Debouncing Filtering Select. 3 1 write-only P4 Debouncing Filtering Select. 4 1 write-only P5 Debouncing Filtering Select. 5 1 write-only P6 Debouncing Filtering Select. 6 1 write-only P7 Debouncing Filtering Select. 7 1 write-only P8 Debouncing Filtering Select. 8 1 write-only P9 Debouncing Filtering Select. 9 1 write-only P10 Debouncing Filtering Select. 10 1 write-only P11 Debouncing Filtering Select. 11 1 write-only P12 Debouncing Filtering Select. 12 1 write-only P13 Debouncing Filtering Select. 13 1 write-only P14 Debouncing Filtering Select. 14 1 write-only P15 Debouncing Filtering Select. 15 1 write-only P16 Debouncing Filtering Select. 16 1 write-only P17 Debouncing Filtering Select. 17 1 write-only P18 Debouncing Filtering Select. 18 1 write-only P19 Debouncing Filtering Select. 19 1 write-only P20 Debouncing Filtering Select. 20 1 write-only P21 Debouncing Filtering Select. 21 1 write-only P22 Debouncing Filtering Select. 22 1 write-only P23 Debouncing Filtering Select. 23 1 write-only P24 Debouncing Filtering Select. 24 1 write-only P25 Debouncing Filtering Select. 25 1 write-only P26 Debouncing Filtering Select. 26 1 write-only P27 Debouncing Filtering Select. 27 1 write-only P28 Debouncing Filtering Select. 28 1 write-only P29 Debouncing Filtering Select. 29 1 write-only P30 Debouncing Filtering Select. 30 1 write-only P31 Debouncing Filtering Select. 31 1 write-only IFDGSR Glitch or Debouncing Input Filter Clock Selection Status Register 0x00000088 32 read-only 0x00000000 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only SCDR Slow Clock Divider Debouncing Register 0x0000008C 32 read-write 0x00000000 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write OWER Output Write Enable 0x000000A0 32 write-only P0 Output Write Enable. 0 1 write-only P1 Output Write Enable. 1 1 write-only P2 Output Write Enable. 2 1 write-only P3 Output Write Enable. 3 1 write-only P4 Output Write Enable. 4 1 write-only P5 Output Write Enable. 5 1 write-only P6 Output Write Enable. 6 1 write-only P7 Output Write Enable. 7 1 write-only P8 Output Write Enable. 8 1 write-only P9 Output Write Enable. 9 1 write-only P10 Output Write Enable. 10 1 write-only P11 Output Write Enable. 11 1 write-only P12 Output Write Enable. 12 1 write-only P13 Output Write Enable. 13 1 write-only P14 Output Write Enable. 14 1 write-only P15 Output Write Enable. 15 1 write-only P16 Output Write Enable. 16 1 write-only P17 Output Write Enable. 17 1 write-only P18 Output Write Enable. 18 1 write-only P19 Output Write Enable. 19 1 write-only P20 Output Write Enable. 20 1 write-only P21 Output Write Enable. 21 1 write-only P22 Output Write Enable. 22 1 write-only P23 Output Write Enable. 23 1 write-only P24 Output Write Enable. 24 1 write-only P25 Output Write Enable. 25 1 write-only P26 Output Write Enable. 26 1 write-only P27 Output Write Enable. 27 1 write-only P28 Output Write Enable. 28 1 write-only P29 Output Write Enable. 29 1 write-only P30 Output Write Enable. 30 1 write-only P31 Output Write Enable. 31 1 write-only OWDR Output Write Disable 0x000000A4 32 write-only P0 Output Write Disable. 0 1 write-only P1 Output Write Disable. 1 1 write-only P2 Output Write Disable. 2 1 write-only P3 Output Write Disable. 3 1 write-only P4 Output Write Disable. 4 1 write-only P5 Output Write Disable. 5 1 write-only P6 Output Write Disable. 6 1 write-only P7 Output Write Disable. 7 1 write-only P8 Output Write Disable. 8 1 write-only P9 Output Write Disable. 9 1 write-only P10 Output Write Disable. 10 1 write-only P11 Output Write Disable. 11 1 write-only P12 Output Write Disable. 12 1 write-only P13 Output Write Disable. 13 1 write-only P14 Output Write Disable. 14 1 write-only P15 Output Write Disable. 15 1 write-only P16 Output Write Disable. 16 1 write-only P17 Output Write Disable. 17 1 write-only P18 Output Write Disable. 18 1 write-only P19 Output Write Disable. 19 1 write-only P20 Output Write Disable. 20 1 write-only P21 Output Write Disable. 21 1 write-only P22 Output Write Disable. 22 1 write-only P23 Output Write Disable. 23 1 write-only P24 Output Write Disable. 24 1 write-only P25 Output Write Disable. 25 1 write-only P26 Output Write Disable. 26 1 write-only P27 Output Write Disable. 27 1 write-only P28 Output Write Disable. 28 1 write-only P29 Output Write Disable. 29 1 write-only P30 Output Write Disable. 30 1 write-only P31 Output Write Disable. 31 1 write-only OWSR Output Write Status Register 0x000000A8 32 read-only 0x00000000 P0 Output Write Status. 0 1 read-only P1 Output Write Status. 1 1 read-only P2 Output Write Status. 2 1 read-only P3 Output Write Status. 3 1 read-only P4 Output Write Status. 4 1 read-only P5 Output Write Status. 5 1 read-only P6 Output Write Status. 6 1 read-only P7 Output Write Status. 7 1 read-only P8 Output Write Status. 8 1 read-only P9 Output Write Status. 9 1 read-only P10 Output Write Status. 10 1 read-only P11 Output Write Status. 11 1 read-only P12 Output Write Status. 12 1 read-only P13 Output Write Status. 13 1 read-only P14 Output Write Status. 14 1 read-only P15 Output Write Status. 15 1 read-only P16 Output Write Status. 16 1 read-only P17 Output Write Status. 17 1 read-only P18 Output Write Status. 18 1 read-only P19 Output Write Status. 19 1 read-only P20 Output Write Status. 20 1 read-only P21 Output Write Status. 21 1 read-only P22 Output Write Status. 22 1 read-only P23 Output Write Status. 23 1 read-only P24 Output Write Status. 24 1 read-only P25 Output Write Status. 25 1 read-only P26 Output Write Status. 26 1 read-only P27 Output Write Status. 27 1 read-only P28 Output Write Status. 28 1 read-only P29 Output Write Status. 29 1 read-only P30 Output Write Status. 30 1 read-only P31 Output Write Status. 31 1 read-only AIMER Additional Interrupt Modes Enable Register 0x000000B0 32 write-only P0 Additional Interrupt Modes Enable. 0 1 write-only P1 Additional Interrupt Modes Enable. 1 1 write-only P2 Additional Interrupt Modes Enable. 2 1 write-only P3 Additional Interrupt Modes Enable. 3 1 write-only P4 Additional Interrupt Modes Enable. 4 1 write-only P5 Additional Interrupt Modes Enable. 5 1 write-only P6 Additional Interrupt Modes Enable. 6 1 write-only P7 Additional Interrupt Modes Enable. 7 1 write-only P8 Additional Interrupt Modes Enable. 8 1 write-only P9 Additional Interrupt Modes Enable. 9 1 write-only P10 Additional Interrupt Modes Enable. 10 1 write-only P11 Additional Interrupt Modes Enable. 11 1 write-only P12 Additional Interrupt Modes Enable. 12 1 write-only P13 Additional Interrupt Modes Enable. 13 1 write-only P14 Additional Interrupt Modes Enable. 14 1 write-only P15 Additional Interrupt Modes Enable. 15 1 write-only P16 Additional Interrupt Modes Enable. 16 1 write-only P17 Additional Interrupt Modes Enable. 17 1 write-only P18 Additional Interrupt Modes Enable. 18 1 write-only P19 Additional Interrupt Modes Enable. 19 1 write-only P20 Additional Interrupt Modes Enable. 20 1 write-only P21 Additional Interrupt Modes Enable. 21 1 write-only P22 Additional Interrupt Modes Enable. 22 1 write-only P23 Additional Interrupt Modes Enable. 23 1 write-only P24 Additional Interrupt Modes Enable. 24 1 write-only P25 Additional Interrupt Modes Enable. 25 1 write-only P26 Additional Interrupt Modes Enable. 26 1 write-only P27 Additional Interrupt Modes Enable. 27 1 write-only P28 Additional Interrupt Modes Enable. 28 1 write-only P29 Additional Interrupt Modes Enable. 29 1 write-only P30 Additional Interrupt Modes Enable. 30 1 write-only P31 Additional Interrupt Modes Enable. 31 1 write-only AIMDR Additional Interrupt Modes Disables Register 0x000000B4 32 write-only P0 Additional Interrupt Modes Disable. 0 1 write-only P1 Additional Interrupt Modes Disable. 1 1 write-only P2 Additional Interrupt Modes Disable. 2 1 write-only P3 Additional Interrupt Modes Disable. 3 1 write-only P4 Additional Interrupt Modes Disable. 4 1 write-only P5 Additional Interrupt Modes Disable. 5 1 write-only P6 Additional Interrupt Modes Disable. 6 1 write-only P7 Additional Interrupt Modes Disable. 7 1 write-only P8 Additional Interrupt Modes Disable. 8 1 write-only P9 Additional Interrupt Modes Disable. 9 1 write-only P10 Additional Interrupt Modes Disable. 10 1 write-only P11 Additional Interrupt Modes Disable. 11 1 write-only P12 Additional Interrupt Modes Disable. 12 1 write-only P13 Additional Interrupt Modes Disable. 13 1 write-only P14 Additional Interrupt Modes Disable. 14 1 write-only P15 Additional Interrupt Modes Disable. 15 1 write-only P16 Additional Interrupt Modes Disable. 16 1 write-only P17 Additional Interrupt Modes Disable. 17 1 write-only P18 Additional Interrupt Modes Disable. 18 1 write-only P19 Additional Interrupt Modes Disable. 19 1 write-only P20 Additional Interrupt Modes Disable. 20 1 write-only P21 Additional Interrupt Modes Disable. 21 1 write-only P22 Additional Interrupt Modes Disable. 22 1 write-only P23 Additional Interrupt Modes Disable. 23 1 write-only P24 Additional Interrupt Modes Disable. 24 1 write-only P25 Additional Interrupt Modes Disable. 25 1 write-only P26 Additional Interrupt Modes Disable. 26 1 write-only P27 Additional Interrupt Modes Disable. 27 1 write-only P28 Additional Interrupt Modes Disable. 28 1 write-only P29 Additional Interrupt Modes Disable. 29 1 write-only P30 Additional Interrupt Modes Disable. 30 1 write-only P31 Additional Interrupt Modes Disable. 31 1 write-only AIMMR Additional Interrupt Modes Mask Register 0x000000B8 32 read-only 0x00000000 P0 Peripheral CD Status. 0 1 read-only P1 Peripheral CD Status. 1 1 read-only P2 Peripheral CD Status. 2 1 read-only P3 Peripheral CD Status. 3 1 read-only P4 Peripheral CD Status. 4 1 read-only P5 Peripheral CD Status. 5 1 read-only P6 Peripheral CD Status. 6 1 read-only P7 Peripheral CD Status. 7 1 read-only P8 Peripheral CD Status. 8 1 read-only P9 Peripheral CD Status. 9 1 read-only P10 Peripheral CD Status. 10 1 read-only P11 Peripheral CD Status. 11 1 read-only P12 Peripheral CD Status. 12 1 read-only P13 Peripheral CD Status. 13 1 read-only P14 Peripheral CD Status. 14 1 read-only P15 Peripheral CD Status. 15 1 read-only P16 Peripheral CD Status. 16 1 read-only P17 Peripheral CD Status. 17 1 read-only P18 Peripheral CD Status. 18 1 read-only P19 Peripheral CD Status. 19 1 read-only P20 Peripheral CD Status. 20 1 read-only P21 Peripheral CD Status. 21 1 read-only P22 Peripheral CD Status. 22 1 read-only P23 Peripheral CD Status. 23 1 read-only P24 Peripheral CD Status. 24 1 read-only P25 Peripheral CD Status. 25 1 read-only P26 Peripheral CD Status. 26 1 read-only P27 Peripheral CD Status. 27 1 read-only P28 Peripheral CD Status. 28 1 read-only P29 Peripheral CD Status. 29 1 read-only P30 Peripheral CD Status. 30 1 read-only P31 Peripheral CD Status. 31 1 read-only ESR Edge Select Register 0x000000C0 32 write-only P0 Edge Interrupt Selection. 0 1 write-only P1 Edge Interrupt Selection. 1 1 write-only P2 Edge Interrupt Selection. 2 1 write-only P3 Edge Interrupt Selection. 3 1 write-only P4 Edge Interrupt Selection. 4 1 write-only P5 Edge Interrupt Selection. 5 1 write-only P6 Edge Interrupt Selection. 6 1 write-only P7 Edge Interrupt Selection. 7 1 write-only P8 Edge Interrupt Selection. 8 1 write-only P9 Edge Interrupt Selection. 9 1 write-only P10 Edge Interrupt Selection. 10 1 write-only P11 Edge Interrupt Selection. 11 1 write-only P12 Edge Interrupt Selection. 12 1 write-only P13 Edge Interrupt Selection. 13 1 write-only P14 Edge Interrupt Selection. 14 1 write-only P15 Edge Interrupt Selection. 15 1 write-only P16 Edge Interrupt Selection. 16 1 write-only P17 Edge Interrupt Selection. 17 1 write-only P18 Edge Interrupt Selection. 18 1 write-only P19 Edge Interrupt Selection. 19 1 write-only P20 Edge Interrupt Selection. 20 1 write-only P21 Edge Interrupt Selection. 21 1 write-only P22 Edge Interrupt Selection. 22 1 write-only P23 Edge Interrupt Selection. 23 1 write-only P24 Edge Interrupt Selection. 24 1 write-only P25 Edge Interrupt Selection. 25 1 write-only P26 Edge Interrupt Selection. 26 1 write-only P27 Edge Interrupt Selection. 27 1 write-only P28 Edge Interrupt Selection. 28 1 write-only P29 Edge Interrupt Selection. 29 1 write-only P30 Edge Interrupt Selection. 30 1 write-only P31 Edge Interrupt Selection. 31 1 write-only LSR Level Select Register 0x000000C4 32 write-only P0 Level Interrupt Selection. 0 1 write-only P1 Level Interrupt Selection. 1 1 write-only P2 Level Interrupt Selection. 2 1 write-only P3 Level Interrupt Selection. 3 1 write-only P4 Level Interrupt Selection. 4 1 write-only P5 Level Interrupt Selection. 5 1 write-only P6 Level Interrupt Selection. 6 1 write-only P7 Level Interrupt Selection. 7 1 write-only P8 Level Interrupt Selection. 8 1 write-only P9 Level Interrupt Selection. 9 1 write-only P10 Level Interrupt Selection. 10 1 write-only P11 Level Interrupt Selection. 11 1 write-only P12 Level Interrupt Selection. 12 1 write-only P13 Level Interrupt Selection. 13 1 write-only P14 Level Interrupt Selection. 14 1 write-only P15 Level Interrupt Selection. 15 1 write-only P16 Level Interrupt Selection. 16 1 write-only P17 Level Interrupt Selection. 17 1 write-only P18 Level Interrupt Selection. 18 1 write-only P19 Level Interrupt Selection. 19 1 write-only P20 Level Interrupt Selection. 20 1 write-only P21 Level Interrupt Selection. 21 1 write-only P22 Level Interrupt Selection. 22 1 write-only P23 Level Interrupt Selection. 23 1 write-only P24 Level Interrupt Selection. 24 1 write-only P25 Level Interrupt Selection. 25 1 write-only P26 Level Interrupt Selection. 26 1 write-only P27 Level Interrupt Selection. 27 1 write-only P28 Level Interrupt Selection. 28 1 write-only P29 Level Interrupt Selection. 29 1 write-only P30 Level Interrupt Selection. 30 1 write-only P31 Level Interrupt Selection. 31 1 write-only ELSR Edge/Level Status Register 0x000000C8 32 read-only 0x00000000 P0 Edge/Level Interrupt source selection. 0 1 read-only P1 Edge/Level Interrupt source selection. 1 1 read-only P2 Edge/Level Interrupt source selection. 2 1 read-only P3 Edge/Level Interrupt source selection. 3 1 read-only P4 Edge/Level Interrupt source selection. 4 1 read-only P5 Edge/Level Interrupt source selection. 5 1 read-only P6 Edge/Level Interrupt source selection. 6 1 read-only P7 Edge/Level Interrupt source selection. 7 1 read-only P8 Edge/Level Interrupt source selection. 8 1 read-only P9 Edge/Level Interrupt source selection. 9 1 read-only P10 Edge/Level Interrupt source selection. 10 1 read-only P11 Edge/Level Interrupt source selection. 11 1 read-only P12 Edge/Level Interrupt source selection. 12 1 read-only P13 Edge/Level Interrupt source selection. 13 1 read-only P14 Edge/Level Interrupt source selection. 14 1 read-only P15 Edge/Level Interrupt source selection. 15 1 read-only P16 Edge/Level Interrupt source selection. 16 1 read-only P17 Edge/Level Interrupt source selection. 17 1 read-only P18 Edge/Level Interrupt source selection. 18 1 read-only P19 Edge/Level Interrupt source selection. 19 1 read-only P20 Edge/Level Interrupt source selection. 20 1 read-only P21 Edge/Level Interrupt source selection. 21 1 read-only P22 Edge/Level Interrupt source selection. 22 1 read-only P23 Edge/Level Interrupt source selection. 23 1 read-only P24 Edge/Level Interrupt source selection. 24 1 read-only P25 Edge/Level Interrupt source selection. 25 1 read-only P26 Edge/Level Interrupt source selection. 26 1 read-only P27 Edge/Level Interrupt source selection. 27 1 read-only P28 Edge/Level Interrupt source selection. 28 1 read-only P29 Edge/Level Interrupt source selection. 29 1 read-only P30 Edge/Level Interrupt source selection. 30 1 read-only P31 Edge/Level Interrupt source selection. 31 1 read-only FELLSR Falling Edge/Low Level Select Register 0x000000D0 32 write-only P0 Falling Edge/Low Level Interrupt Selection. 0 1 write-only P1 Falling Edge/Low Level Interrupt Selection. 1 1 write-only P2 Falling Edge/Low Level Interrupt Selection. 2 1 write-only P3 Falling Edge/Low Level Interrupt Selection. 3 1 write-only P4 Falling Edge/Low Level Interrupt Selection. 4 1 write-only P5 Falling Edge/Low Level Interrupt Selection. 5 1 write-only P6 Falling Edge/Low Level Interrupt Selection. 6 1 write-only P7 Falling Edge/Low Level Interrupt Selection. 7 1 write-only P8 Falling Edge/Low Level Interrupt Selection. 8 1 write-only P9 Falling Edge/Low Level Interrupt Selection. 9 1 write-only P10 Falling Edge/Low Level Interrupt Selection. 10 1 write-only P11 Falling Edge/Low Level Interrupt Selection. 11 1 write-only P12 Falling Edge/Low Level Interrupt Selection. 12 1 write-only P13 Falling Edge/Low Level Interrupt Selection. 13 1 write-only P14 Falling Edge/Low Level Interrupt Selection. 14 1 write-only P15 Falling Edge/Low Level Interrupt Selection. 15 1 write-only P16 Falling Edge/Low Level Interrupt Selection. 16 1 write-only P17 Falling Edge/Low Level Interrupt Selection. 17 1 write-only P18 Falling Edge/Low Level Interrupt Selection. 18 1 write-only P19 Falling Edge/Low Level Interrupt Selection. 19 1 write-only P20 Falling Edge/Low Level Interrupt Selection. 20 1 write-only P21 Falling Edge/Low Level Interrupt Selection. 21 1 write-only P22 Falling Edge/Low Level Interrupt Selection. 22 1 write-only P23 Falling Edge/Low Level Interrupt Selection. 23 1 write-only P24 Falling Edge/Low Level Interrupt Selection. 24 1 write-only P25 Falling Edge/Low Level Interrupt Selection. 25 1 write-only P26 Falling Edge/Low Level Interrupt Selection. 26 1 write-only P27 Falling Edge/Low Level Interrupt Selection. 27 1 write-only P28 Falling Edge/Low Level Interrupt Selection. 28 1 write-only P29 Falling Edge/Low Level Interrupt Selection. 29 1 write-only P30 Falling Edge/Low Level Interrupt Selection. 30 1 write-only P31 Falling Edge/Low Level Interrupt Selection. 31 1 write-only REHLSR Rising Edge/ High Level Select Register 0x000000D4 32 write-only P0 Rising Edge /High Level Interrupt Selection. 0 1 write-only P1 Rising Edge /High Level Interrupt Selection. 1 1 write-only P2 Rising Edge /High Level Interrupt Selection. 2 1 write-only P3 Rising Edge /High Level Interrupt Selection. 3 1 write-only P4 Rising Edge /High Level Interrupt Selection. 4 1 write-only P5 Rising Edge /High Level Interrupt Selection. 5 1 write-only P6 Rising Edge /High Level Interrupt Selection. 6 1 write-only P7 Rising Edge /High Level Interrupt Selection. 7 1 write-only P8 Rising Edge /High Level Interrupt Selection. 8 1 write-only P9 Rising Edge /High Level Interrupt Selection. 9 1 write-only P10 Rising Edge /High Level Interrupt Selection. 10 1 write-only P11 Rising Edge /High Level Interrupt Selection. 11 1 write-only P12 Rising Edge /High Level Interrupt Selection. 12 1 write-only P13 Rising Edge /High Level Interrupt Selection. 13 1 write-only P14 Rising Edge /High Level Interrupt Selection. 14 1 write-only P15 Rising Edge /High Level Interrupt Selection. 15 1 write-only P16 Rising Edge /High Level Interrupt Selection. 16 1 write-only P17 Rising Edge /High Level Interrupt Selection. 17 1 write-only P18 Rising Edge /High Level Interrupt Selection. 18 1 write-only P19 Rising Edge /High Level Interrupt Selection. 19 1 write-only P20 Rising Edge /High Level Interrupt Selection. 20 1 write-only P21 Rising Edge /High Level Interrupt Selection. 21 1 write-only P22 Rising Edge /High Level Interrupt Selection. 22 1 write-only P23 Rising Edge /High Level Interrupt Selection. 23 1 write-only P24 Rising Edge /High Level Interrupt Selection. 24 1 write-only P25 Rising Edge /High Level Interrupt Selection. 25 1 write-only P26 Rising Edge /High Level Interrupt Selection. 26 1 write-only P27 Rising Edge /High Level Interrupt Selection. 27 1 write-only P28 Rising Edge /High Level Interrupt Selection. 28 1 write-only P29 Rising Edge /High Level Interrupt Selection. 29 1 write-only P30 Rising Edge /High Level Interrupt Selection. 30 1 write-only P31 Rising Edge /High Level Interrupt Selection. 31 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0x000000D8 32 read-only 0x00000000 P0 Edge /Level Interrupt Source Selection. 0 1 read-only P1 Edge /Level Interrupt Source Selection. 1 1 read-only P2 Edge /Level Interrupt Source Selection. 2 1 read-only P3 Edge /Level Interrupt Source Selection. 3 1 read-only P4 Edge /Level Interrupt Source Selection. 4 1 read-only P5 Edge /Level Interrupt Source Selection. 5 1 read-only P6 Edge /Level Interrupt Source Selection. 6 1 read-only P7 Edge /Level Interrupt Source Selection. 7 1 read-only P8 Edge /Level Interrupt Source Selection. 8 1 read-only P9 Edge /Level Interrupt Source Selection. 9 1 read-only P10 Edge /Level Interrupt Source Selection. 10 1 read-only P11 Edge /Level Interrupt Source Selection. 11 1 read-only P12 Edge /Level Interrupt Source Selection. 12 1 read-only P13 Edge /Level Interrupt Source Selection. 13 1 read-only P14 Edge /Level Interrupt Source Selection. 14 1 read-only P15 Edge /Level Interrupt Source Selection. 15 1 read-only P16 Edge /Level Interrupt Source Selection. 16 1 read-only P17 Edge /Level Interrupt Source Selection. 17 1 read-only P18 Edge /Level Interrupt Source Selection. 18 1 read-only P19 Edge /Level Interrupt Source Selection. 19 1 read-only P20 Edge /Level Interrupt Source Selection. 20 1 read-only P21 Edge /Level Interrupt Source Selection. 21 1 read-only P22 Edge /Level Interrupt Source Selection. 22 1 read-only P23 Edge /Level Interrupt Source Selection. 23 1 read-only P24 Edge /Level Interrupt Source Selection. 24 1 read-only P25 Edge /Level Interrupt Source Selection. 25 1 read-only P26 Edge /Level Interrupt Source Selection. 26 1 read-only P27 Edge /Level Interrupt Source Selection. 27 1 read-only P28 Edge /Level Interrupt Source Selection. 28 1 read-only P29 Edge /Level Interrupt Source Selection. 29 1 read-only P30 Edge /Level Interrupt Source Selection. 30 1 read-only P31 Edge /Level Interrupt Source Selection. 31 1 read-only LOCKSR Lock Status 0x000000E0 32 read-only 0x00000000 P0 Lock Status. 0 1 read-only P1 Lock Status. 1 1 read-only P2 Lock Status. 2 1 read-only P3 Lock Status. 3 1 read-only P4 Lock Status. 4 1 read-only P5 Lock Status. 5 1 read-only P6 Lock Status. 6 1 read-only P7 Lock Status. 7 1 read-only P8 Lock Status. 8 1 read-only P9 Lock Status. 9 1 read-only P10 Lock Status. 10 1 read-only P11 Lock Status. 11 1 read-only P12 Lock Status. 12 1 read-only P13 Lock Status. 13 1 read-only P14 Lock Status. 14 1 read-only P15 Lock Status. 15 1 read-only P16 Lock Status. 16 1 read-only P17 Lock Status. 17 1 read-only P18 Lock Status. 18 1 read-only P19 Lock Status. 19 1 read-only P20 Lock Status. 20 1 read-only P21 Lock Status. 21 1 read-only P22 Lock Status. 22 1 read-only P23 Lock Status. 23 1 read-only P24 Lock Status. 24 1 read-only P25 Lock Status. 25 1 read-only P26 Lock Status. 26 1 read-only P27 Lock Status. 27 1 read-only P28 Lock Status. 28 1 read-only P29 Lock Status. 29 1 read-only P30 Lock Status. 30 1 read-only P31 Lock Status. 31 1 read-only WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only PIOD 6315C Parallel Input/Output Controller D PIO PIOD_ 0x400E1400 0 0x200 registers PIOD 14 PER PIO Enable Register 0x00000000 32 write-only P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P2 PIO Enable 2 1 write-only P3 PIO Enable 3 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only PDR PIO Disable Register 0x00000004 32 write-only P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P2 PIO Disable 2 1 write-only P3 PIO Disable 3 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only PSR PIO Status Register 0x00000008 32 read-only P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P2 PIO Status 2 1 read-only P3 PIO Status 3 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only OER Output Enable Register 0x00000010 32 write-only P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P2 Output Enable 2 1 write-only P3 Output Enable 3 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only ODR Output Disable Register 0x00000014 32 write-only P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P2 Output Disable 2 1 write-only P3 Output Disable 3 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only OSR Output Status Register 0x00000018 32 read-only 0x00000000 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P2 Output Status 2 1 read-only P3 Output Status 3 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only IFER Glitch Input Filter Enable Register 0x00000020 32 write-only P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P2 Input Filter Enable 2 1 write-only P3 Input Filter Enable 3 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only IFDR Glitch Input Filter Disable Register 0x00000024 32 write-only P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P2 Input Filter Disable 2 1 write-only P3 Input Filter Disable 3 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only IFSR Glitch Input Filter Status Register 0x00000028 32 read-only 0x00000000 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P2 Input Filer Status 2 1 read-only P3 Input Filer Status 3 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only SODR Set Output Data Register 0x00000030 32 write-only P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P2 Set Output Data 2 1 write-only P3 Set Output Data 3 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only CODR Clear Output Data Register 0x00000034 32 write-only P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P2 Clear Output Data 2 1 write-only P3 Clear Output Data 3 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only ODSR Output Data Status Register 0x00000038 32 read-write P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P2 Output Data Status 2 1 read-write P3 Output Data Status 3 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write PDSR Pin Data Status Register 0x0000003C 32 read-only P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P2 Output Data Status 2 1 read-only P3 Output Data Status 3 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only IER Interrupt Enable Register 0x00000040 32 write-only P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only IDR Interrupt Disable Register 0x00000044 32 write-only P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only IMR Interrupt Mask Register 0x00000048 32 read-only 0x00000000 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only ISR Interrupt Status Register 0x0000004C 32 read-only 0x00000000 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P2 Input Change Interrupt Status 2 1 read-only P3 Input Change Interrupt Status 3 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only MDER Multi-driver Enable Register 0x00000050 32 write-only P0 Multi Drive Enable. 0 1 write-only P1 Multi Drive Enable. 1 1 write-only P2 Multi Drive Enable. 2 1 write-only P3 Multi Drive Enable. 3 1 write-only P4 Multi Drive Enable. 4 1 write-only P5 Multi Drive Enable. 5 1 write-only P6 Multi Drive Enable. 6 1 write-only P7 Multi Drive Enable. 7 1 write-only P8 Multi Drive Enable. 8 1 write-only P9 Multi Drive Enable. 9 1 write-only P10 Multi Drive Enable. 10 1 write-only P11 Multi Drive Enable. 11 1 write-only P12 Multi Drive Enable. 12 1 write-only P13 Multi Drive Enable. 13 1 write-only P14 Multi Drive Enable. 14 1 write-only P15 Multi Drive Enable. 15 1 write-only P16 Multi Drive Enable. 16 1 write-only P17 Multi Drive Enable. 17 1 write-only P18 Multi Drive Enable. 18 1 write-only P19 Multi Drive Enable. 19 1 write-only P20 Multi Drive Enable. 20 1 write-only P21 Multi Drive Enable. 21 1 write-only P22 Multi Drive Enable. 22 1 write-only P23 Multi Drive Enable. 23 1 write-only P24 Multi Drive Enable. 24 1 write-only P25 Multi Drive Enable. 25 1 write-only P26 Multi Drive Enable. 26 1 write-only P27 Multi Drive Enable. 27 1 write-only P28 Multi Drive Enable. 28 1 write-only P29 Multi Drive Enable. 29 1 write-only P30 Multi Drive Enable. 30 1 write-only P31 Multi Drive Enable. 31 1 write-only MDDR Multi-driver Disable Register 0x00000054 32 write-only P0 Multi Drive Disable. 0 1 write-only P1 Multi Drive Disable. 1 1 write-only P2 Multi Drive Disable. 2 1 write-only P3 Multi Drive Disable. 3 1 write-only P4 Multi Drive Disable. 4 1 write-only P5 Multi Drive Disable. 5 1 write-only P6 Multi Drive Disable. 6 1 write-only P7 Multi Drive Disable. 7 1 write-only P8 Multi Drive Disable. 8 1 write-only P9 Multi Drive Disable. 9 1 write-only P10 Multi Drive Disable. 10 1 write-only P11 Multi Drive Disable. 11 1 write-only P12 Multi Drive Disable. 12 1 write-only P13 Multi Drive Disable. 13 1 write-only P14 Multi Drive Disable. 14 1 write-only P15 Multi Drive Disable. 15 1 write-only P16 Multi Drive Disable. 16 1 write-only P17 Multi Drive Disable. 17 1 write-only P18 Multi Drive Disable. 18 1 write-only P19 Multi Drive Disable. 19 1 write-only P20 Multi Drive Disable. 20 1 write-only P21 Multi Drive Disable. 21 1 write-only P22 Multi Drive Disable. 22 1 write-only P23 Multi Drive Disable. 23 1 write-only P24 Multi Drive Disable. 24 1 write-only P25 Multi Drive Disable. 25 1 write-only P26 Multi Drive Disable. 26 1 write-only P27 Multi Drive Disable. 27 1 write-only P28 Multi Drive Disable. 28 1 write-only P29 Multi Drive Disable. 29 1 write-only P30 Multi Drive Disable. 30 1 write-only P31 Multi Drive Disable. 31 1 write-only MDSR Multi-driver Status Register 0x00000058 32 read-only 0x00000000 P0 Multi Drive Status. 0 1 read-only P1 Multi Drive Status. 1 1 read-only P2 Multi Drive Status. 2 1 read-only P3 Multi Drive Status. 3 1 read-only P4 Multi Drive Status. 4 1 read-only P5 Multi Drive Status. 5 1 read-only P6 Multi Drive Status. 6 1 read-only P7 Multi Drive Status. 7 1 read-only P8 Multi Drive Status. 8 1 read-only P9 Multi Drive Status. 9 1 read-only P10 Multi Drive Status. 10 1 read-only P11 Multi Drive Status. 11 1 read-only P12 Multi Drive Status. 12 1 read-only P13 Multi Drive Status. 13 1 read-only P14 Multi Drive Status. 14 1 read-only P15 Multi Drive Status. 15 1 read-only P16 Multi Drive Status. 16 1 read-only P17 Multi Drive Status. 17 1 read-only P18 Multi Drive Status. 18 1 read-only P19 Multi Drive Status. 19 1 read-only P20 Multi Drive Status. 20 1 read-only P21 Multi Drive Status. 21 1 read-only P22 Multi Drive Status. 22 1 read-only P23 Multi Drive Status. 23 1 read-only P24 Multi Drive Status. 24 1 read-only P25 Multi Drive Status. 25 1 read-only P26 Multi Drive Status. 26 1 read-only P27 Multi Drive Status. 27 1 read-only P28 Multi Drive Status. 28 1 read-only P29 Multi Drive Status. 29 1 read-only P30 Multi Drive Status. 30 1 read-only P31 Multi Drive Status. 31 1 read-only PUDR Pull-up Disable Register 0x00000060 32 write-only P0 Pull Up Disable. 0 1 write-only P1 Pull Up Disable. 1 1 write-only P2 Pull Up Disable. 2 1 write-only P3 Pull Up Disable. 3 1 write-only P4 Pull Up Disable. 4 1 write-only P5 Pull Up Disable. 5 1 write-only P6 Pull Up Disable. 6 1 write-only P7 Pull Up Disable. 7 1 write-only P8 Pull Up Disable. 8 1 write-only P9 Pull Up Disable. 9 1 write-only P10 Pull Up Disable. 10 1 write-only P11 Pull Up Disable. 11 1 write-only P12 Pull Up Disable. 12 1 write-only P13 Pull Up Disable. 13 1 write-only P14 Pull Up Disable. 14 1 write-only P15 Pull Up Disable. 15 1 write-only P16 Pull Up Disable. 16 1 write-only P17 Pull Up Disable. 17 1 write-only P18 Pull Up Disable. 18 1 write-only P19 Pull Up Disable. 19 1 write-only P20 Pull Up Disable. 20 1 write-only P21 Pull Up Disable. 21 1 write-only P22 Pull Up Disable. 22 1 write-only P23 Pull Up Disable. 23 1 write-only P24 Pull Up Disable. 24 1 write-only P25 Pull Up Disable. 25 1 write-only P26 Pull Up Disable. 26 1 write-only P27 Pull Up Disable. 27 1 write-only P28 Pull Up Disable. 28 1 write-only P29 Pull Up Disable. 29 1 write-only P30 Pull Up Disable. 30 1 write-only P31 Pull Up Disable. 31 1 write-only PUER Pull-up Enable Register 0x00000064 32 write-only P0 Pull Up Enable. 0 1 write-only P1 Pull Up Enable. 1 1 write-only P2 Pull Up Enable. 2 1 write-only P3 Pull Up Enable. 3 1 write-only P4 Pull Up Enable. 4 1 write-only P5 Pull Up Enable. 5 1 write-only P6 Pull Up Enable. 6 1 write-only P7 Pull Up Enable. 7 1 write-only P8 Pull Up Enable. 8 1 write-only P9 Pull Up Enable. 9 1 write-only P10 Pull Up Enable. 10 1 write-only P11 Pull Up Enable. 11 1 write-only P12 Pull Up Enable. 12 1 write-only P13 Pull Up Enable. 13 1 write-only P14 Pull Up Enable. 14 1 write-only P15 Pull Up Enable. 15 1 write-only P16 Pull Up Enable. 16 1 write-only P17 Pull Up Enable. 17 1 write-only P18 Pull Up Enable. 18 1 write-only P19 Pull Up Enable. 19 1 write-only P20 Pull Up Enable. 20 1 write-only P21 Pull Up Enable. 21 1 write-only P22 Pull Up Enable. 22 1 write-only P23 Pull Up Enable. 23 1 write-only P24 Pull Up Enable. 24 1 write-only P25 Pull Up Enable. 25 1 write-only P26 Pull Up Enable. 26 1 write-only P27 Pull Up Enable. 27 1 write-only P28 Pull Up Enable. 28 1 write-only P29 Pull Up Enable. 29 1 write-only P30 Pull Up Enable. 30 1 write-only P31 Pull Up Enable. 31 1 write-only PUSR Pad Pull-up Status Register 0x00000068 32 read-only 0x00000000 P0 Pull Up Status. 0 1 read-only P1 Pull Up Status. 1 1 read-only P2 Pull Up Status. 2 1 read-only P3 Pull Up Status. 3 1 read-only P4 Pull Up Status. 4 1 read-only P5 Pull Up Status. 5 1 read-only P6 Pull Up Status. 6 1 read-only P7 Pull Up Status. 7 1 read-only P8 Pull Up Status. 8 1 read-only P9 Pull Up Status. 9 1 read-only P10 Pull Up Status. 10 1 read-only P11 Pull Up Status. 11 1 read-only P12 Pull Up Status. 12 1 read-only P13 Pull Up Status. 13 1 read-only P14 Pull Up Status. 14 1 read-only P15 Pull Up Status. 15 1 read-only P16 Pull Up Status. 16 1 read-only P17 Pull Up Status. 17 1 read-only P18 Pull Up Status. 18 1 read-only P19 Pull Up Status. 19 1 read-only P20 Pull Up Status. 20 1 read-only P21 Pull Up Status. 21 1 read-only P22 Pull Up Status. 22 1 read-only P23 Pull Up Status. 23 1 read-only P24 Pull Up Status. 24 1 read-only P25 Pull Up Status. 25 1 read-only P26 Pull Up Status. 26 1 read-only P27 Pull Up Status. 27 1 read-only P28 Pull Up Status. 28 1 read-only P29 Pull Up Status. 29 1 read-only P30 Pull Up Status. 30 1 read-only P31 Pull Up Status. 31 1 read-only ABSR Peripheral AB Select Register 0x00000070 32 read-write 0x00000000 P0 Peripheral A Select. 0 1 read-write P1 Peripheral A Select. 1 1 read-write P2 Peripheral A Select. 2 1 read-write P3 Peripheral A Select. 3 1 read-write P4 Peripheral A Select. 4 1 read-write P5 Peripheral A Select. 5 1 read-write P6 Peripheral A Select. 6 1 read-write P7 Peripheral A Select. 7 1 read-write P8 Peripheral A Select. 8 1 read-write P9 Peripheral A Select. 9 1 read-write P10 Peripheral A Select. 10 1 read-write P11 Peripheral A Select. 11 1 read-write P12 Peripheral A Select. 12 1 read-write P13 Peripheral A Select. 13 1 read-write P14 Peripheral A Select. 14 1 read-write P15 Peripheral A Select. 15 1 read-write P16 Peripheral A Select. 16 1 read-write P17 Peripheral A Select. 17 1 read-write P18 Peripheral A Select. 18 1 read-write P19 Peripheral A Select. 19 1 read-write P20 Peripheral A Select. 20 1 read-write P21 Peripheral A Select. 21 1 read-write P22 Peripheral A Select. 22 1 read-write P23 Peripheral A Select. 23 1 read-write P24 Peripheral A Select. 24 1 read-write P25 Peripheral A Select. 25 1 read-write P26 Peripheral A Select. 26 1 read-write P27 Peripheral A Select. 27 1 read-write P28 Peripheral A Select. 28 1 read-write P29 Peripheral A Select. 29 1 read-write P30 Peripheral A Select. 30 1 read-write P31 Peripheral A Select. 31 1 read-write SCIFSR System Clock Glitch Input Filter Select Register 0x00000080 32 write-only P0 System Clock Glitch Filtering Select. 0 1 write-only P1 System Clock Glitch Filtering Select. 1 1 write-only P2 System Clock Glitch Filtering Select. 2 1 write-only P3 System Clock Glitch Filtering Select. 3 1 write-only P4 System Clock Glitch Filtering Select. 4 1 write-only P5 System Clock Glitch Filtering Select. 5 1 write-only P6 System Clock Glitch Filtering Select. 6 1 write-only P7 System Clock Glitch Filtering Select. 7 1 write-only P8 System Clock Glitch Filtering Select. 8 1 write-only P9 System Clock Glitch Filtering Select. 9 1 write-only P10 System Clock Glitch Filtering Select. 10 1 write-only P11 System Clock Glitch Filtering Select. 11 1 write-only P12 System Clock Glitch Filtering Select. 12 1 write-only P13 System Clock Glitch Filtering Select. 13 1 write-only P14 System Clock Glitch Filtering Select. 14 1 write-only P15 System Clock Glitch Filtering Select. 15 1 write-only P16 System Clock Glitch Filtering Select. 16 1 write-only P17 System Clock Glitch Filtering Select. 17 1 write-only P18 System Clock Glitch Filtering Select. 18 1 write-only P19 System Clock Glitch Filtering Select. 19 1 write-only P20 System Clock Glitch Filtering Select. 20 1 write-only P21 System Clock Glitch Filtering Select. 21 1 write-only P22 System Clock Glitch Filtering Select. 22 1 write-only P23 System Clock Glitch Filtering Select. 23 1 write-only P24 System Clock Glitch Filtering Select. 24 1 write-only P25 System Clock Glitch Filtering Select. 25 1 write-only P26 System Clock Glitch Filtering Select. 26 1 write-only P27 System Clock Glitch Filtering Select. 27 1 write-only P28 System Clock Glitch Filtering Select. 28 1 write-only P29 System Clock Glitch Filtering Select. 29 1 write-only P30 System Clock Glitch Filtering Select. 30 1 write-only P31 System Clock Glitch Filtering Select. 31 1 write-only DIFSR Debouncing Input Filter Select Register 0x00000084 32 write-only P0 Debouncing Filtering Select. 0 1 write-only P1 Debouncing Filtering Select. 1 1 write-only P2 Debouncing Filtering Select. 2 1 write-only P3 Debouncing Filtering Select. 3 1 write-only P4 Debouncing Filtering Select. 4 1 write-only P5 Debouncing Filtering Select. 5 1 write-only P6 Debouncing Filtering Select. 6 1 write-only P7 Debouncing Filtering Select. 7 1 write-only P8 Debouncing Filtering Select. 8 1 write-only P9 Debouncing Filtering Select. 9 1 write-only P10 Debouncing Filtering Select. 10 1 write-only P11 Debouncing Filtering Select. 11 1 write-only P12 Debouncing Filtering Select. 12 1 write-only P13 Debouncing Filtering Select. 13 1 write-only P14 Debouncing Filtering Select. 14 1 write-only P15 Debouncing Filtering Select. 15 1 write-only P16 Debouncing Filtering Select. 16 1 write-only P17 Debouncing Filtering Select. 17 1 write-only P18 Debouncing Filtering Select. 18 1 write-only P19 Debouncing Filtering Select. 19 1 write-only P20 Debouncing Filtering Select. 20 1 write-only P21 Debouncing Filtering Select. 21 1 write-only P22 Debouncing Filtering Select. 22 1 write-only P23 Debouncing Filtering Select. 23 1 write-only P24 Debouncing Filtering Select. 24 1 write-only P25 Debouncing Filtering Select. 25 1 write-only P26 Debouncing Filtering Select. 26 1 write-only P27 Debouncing Filtering Select. 27 1 write-only P28 Debouncing Filtering Select. 28 1 write-only P29 Debouncing Filtering Select. 29 1 write-only P30 Debouncing Filtering Select. 30 1 write-only P31 Debouncing Filtering Select. 31 1 write-only IFDGSR Glitch or Debouncing Input Filter Clock Selection Status Register 0x00000088 32 read-only 0x00000000 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only SCDR Slow Clock Divider Debouncing Register 0x0000008C 32 read-write 0x00000000 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write OWER Output Write Enable 0x000000A0 32 write-only P0 Output Write Enable. 0 1 write-only P1 Output Write Enable. 1 1 write-only P2 Output Write Enable. 2 1 write-only P3 Output Write Enable. 3 1 write-only P4 Output Write Enable. 4 1 write-only P5 Output Write Enable. 5 1 write-only P6 Output Write Enable. 6 1 write-only P7 Output Write Enable. 7 1 write-only P8 Output Write Enable. 8 1 write-only P9 Output Write Enable. 9 1 write-only P10 Output Write Enable. 10 1 write-only P11 Output Write Enable. 11 1 write-only P12 Output Write Enable. 12 1 write-only P13 Output Write Enable. 13 1 write-only P14 Output Write Enable. 14 1 write-only P15 Output Write Enable. 15 1 write-only P16 Output Write Enable. 16 1 write-only P17 Output Write Enable. 17 1 write-only P18 Output Write Enable. 18 1 write-only P19 Output Write Enable. 19 1 write-only P20 Output Write Enable. 20 1 write-only P21 Output Write Enable. 21 1 write-only P22 Output Write Enable. 22 1 write-only P23 Output Write Enable. 23 1 write-only P24 Output Write Enable. 24 1 write-only P25 Output Write Enable. 25 1 write-only P26 Output Write Enable. 26 1 write-only P27 Output Write Enable. 27 1 write-only P28 Output Write Enable. 28 1 write-only P29 Output Write Enable. 29 1 write-only P30 Output Write Enable. 30 1 write-only P31 Output Write Enable. 31 1 write-only OWDR Output Write Disable 0x000000A4 32 write-only P0 Output Write Disable. 0 1 write-only P1 Output Write Disable. 1 1 write-only P2 Output Write Disable. 2 1 write-only P3 Output Write Disable. 3 1 write-only P4 Output Write Disable. 4 1 write-only P5 Output Write Disable. 5 1 write-only P6 Output Write Disable. 6 1 write-only P7 Output Write Disable. 7 1 write-only P8 Output Write Disable. 8 1 write-only P9 Output Write Disable. 9 1 write-only P10 Output Write Disable. 10 1 write-only P11 Output Write Disable. 11 1 write-only P12 Output Write Disable. 12 1 write-only P13 Output Write Disable. 13 1 write-only P14 Output Write Disable. 14 1 write-only P15 Output Write Disable. 15 1 write-only P16 Output Write Disable. 16 1 write-only P17 Output Write Disable. 17 1 write-only P18 Output Write Disable. 18 1 write-only P19 Output Write Disable. 19 1 write-only P20 Output Write Disable. 20 1 write-only P21 Output Write Disable. 21 1 write-only P22 Output Write Disable. 22 1 write-only P23 Output Write Disable. 23 1 write-only P24 Output Write Disable. 24 1 write-only P25 Output Write Disable. 25 1 write-only P26 Output Write Disable. 26 1 write-only P27 Output Write Disable. 27 1 write-only P28 Output Write Disable. 28 1 write-only P29 Output Write Disable. 29 1 write-only P30 Output Write Disable. 30 1 write-only P31 Output Write Disable. 31 1 write-only OWSR Output Write Status Register 0x000000A8 32 read-only 0x00000000 P0 Output Write Status. 0 1 read-only P1 Output Write Status. 1 1 read-only P2 Output Write Status. 2 1 read-only P3 Output Write Status. 3 1 read-only P4 Output Write Status. 4 1 read-only P5 Output Write Status. 5 1 read-only P6 Output Write Status. 6 1 read-only P7 Output Write Status. 7 1 read-only P8 Output Write Status. 8 1 read-only P9 Output Write Status. 9 1 read-only P10 Output Write Status. 10 1 read-only P11 Output Write Status. 11 1 read-only P12 Output Write Status. 12 1 read-only P13 Output Write Status. 13 1 read-only P14 Output Write Status. 14 1 read-only P15 Output Write Status. 15 1 read-only P16 Output Write Status. 16 1 read-only P17 Output Write Status. 17 1 read-only P18 Output Write Status. 18 1 read-only P19 Output Write Status. 19 1 read-only P20 Output Write Status. 20 1 read-only P21 Output Write Status. 21 1 read-only P22 Output Write Status. 22 1 read-only P23 Output Write Status. 23 1 read-only P24 Output Write Status. 24 1 read-only P25 Output Write Status. 25 1 read-only P26 Output Write Status. 26 1 read-only P27 Output Write Status. 27 1 read-only P28 Output Write Status. 28 1 read-only P29 Output Write Status. 29 1 read-only P30 Output Write Status. 30 1 read-only P31 Output Write Status. 31 1 read-only AIMER Additional Interrupt Modes Enable Register 0x000000B0 32 write-only P0 Additional Interrupt Modes Enable. 0 1 write-only P1 Additional Interrupt Modes Enable. 1 1 write-only P2 Additional Interrupt Modes Enable. 2 1 write-only P3 Additional Interrupt Modes Enable. 3 1 write-only P4 Additional Interrupt Modes Enable. 4 1 write-only P5 Additional Interrupt Modes Enable. 5 1 write-only P6 Additional Interrupt Modes Enable. 6 1 write-only P7 Additional Interrupt Modes Enable. 7 1 write-only P8 Additional Interrupt Modes Enable. 8 1 write-only P9 Additional Interrupt Modes Enable. 9 1 write-only P10 Additional Interrupt Modes Enable. 10 1 write-only P11 Additional Interrupt Modes Enable. 11 1 write-only P12 Additional Interrupt Modes Enable. 12 1 write-only P13 Additional Interrupt Modes Enable. 13 1 write-only P14 Additional Interrupt Modes Enable. 14 1 write-only P15 Additional Interrupt Modes Enable. 15 1 write-only P16 Additional Interrupt Modes Enable. 16 1 write-only P17 Additional Interrupt Modes Enable. 17 1 write-only P18 Additional Interrupt Modes Enable. 18 1 write-only P19 Additional Interrupt Modes Enable. 19 1 write-only P20 Additional Interrupt Modes Enable. 20 1 write-only P21 Additional Interrupt Modes Enable. 21 1 write-only P22 Additional Interrupt Modes Enable. 22 1 write-only P23 Additional Interrupt Modes Enable. 23 1 write-only P24 Additional Interrupt Modes Enable. 24 1 write-only P25 Additional Interrupt Modes Enable. 25 1 write-only P26 Additional Interrupt Modes Enable. 26 1 write-only P27 Additional Interrupt Modes Enable. 27 1 write-only P28 Additional Interrupt Modes Enable. 28 1 write-only P29 Additional Interrupt Modes Enable. 29 1 write-only P30 Additional Interrupt Modes Enable. 30 1 write-only P31 Additional Interrupt Modes Enable. 31 1 write-only AIMDR Additional Interrupt Modes Disables Register 0x000000B4 32 write-only P0 Additional Interrupt Modes Disable. 0 1 write-only P1 Additional Interrupt Modes Disable. 1 1 write-only P2 Additional Interrupt Modes Disable. 2 1 write-only P3 Additional Interrupt Modes Disable. 3 1 write-only P4 Additional Interrupt Modes Disable. 4 1 write-only P5 Additional Interrupt Modes Disable. 5 1 write-only P6 Additional Interrupt Modes Disable. 6 1 write-only P7 Additional Interrupt Modes Disable. 7 1 write-only P8 Additional Interrupt Modes Disable. 8 1 write-only P9 Additional Interrupt Modes Disable. 9 1 write-only P10 Additional Interrupt Modes Disable. 10 1 write-only P11 Additional Interrupt Modes Disable. 11 1 write-only P12 Additional Interrupt Modes Disable. 12 1 write-only P13 Additional Interrupt Modes Disable. 13 1 write-only P14 Additional Interrupt Modes Disable. 14 1 write-only P15 Additional Interrupt Modes Disable. 15 1 write-only P16 Additional Interrupt Modes Disable. 16 1 write-only P17 Additional Interrupt Modes Disable. 17 1 write-only P18 Additional Interrupt Modes Disable. 18 1 write-only P19 Additional Interrupt Modes Disable. 19 1 write-only P20 Additional Interrupt Modes Disable. 20 1 write-only P21 Additional Interrupt Modes Disable. 21 1 write-only P22 Additional Interrupt Modes Disable. 22 1 write-only P23 Additional Interrupt Modes Disable. 23 1 write-only P24 Additional Interrupt Modes Disable. 24 1 write-only P25 Additional Interrupt Modes Disable. 25 1 write-only P26 Additional Interrupt Modes Disable. 26 1 write-only P27 Additional Interrupt Modes Disable. 27 1 write-only P28 Additional Interrupt Modes Disable. 28 1 write-only P29 Additional Interrupt Modes Disable. 29 1 write-only P30 Additional Interrupt Modes Disable. 30 1 write-only P31 Additional Interrupt Modes Disable. 31 1 write-only AIMMR Additional Interrupt Modes Mask Register 0x000000B8 32 read-only 0x00000000 P0 Peripheral CD Status. 0 1 read-only P1 Peripheral CD Status. 1 1 read-only P2 Peripheral CD Status. 2 1 read-only P3 Peripheral CD Status. 3 1 read-only P4 Peripheral CD Status. 4 1 read-only P5 Peripheral CD Status. 5 1 read-only P6 Peripheral CD Status. 6 1 read-only P7 Peripheral CD Status. 7 1 read-only P8 Peripheral CD Status. 8 1 read-only P9 Peripheral CD Status. 9 1 read-only P10 Peripheral CD Status. 10 1 read-only P11 Peripheral CD Status. 11 1 read-only P12 Peripheral CD Status. 12 1 read-only P13 Peripheral CD Status. 13 1 read-only P14 Peripheral CD Status. 14 1 read-only P15 Peripheral CD Status. 15 1 read-only P16 Peripheral CD Status. 16 1 read-only P17 Peripheral CD Status. 17 1 read-only P18 Peripheral CD Status. 18 1 read-only P19 Peripheral CD Status. 19 1 read-only P20 Peripheral CD Status. 20 1 read-only P21 Peripheral CD Status. 21 1 read-only P22 Peripheral CD Status. 22 1 read-only P23 Peripheral CD Status. 23 1 read-only P24 Peripheral CD Status. 24 1 read-only P25 Peripheral CD Status. 25 1 read-only P26 Peripheral CD Status. 26 1 read-only P27 Peripheral CD Status. 27 1 read-only P28 Peripheral CD Status. 28 1 read-only P29 Peripheral CD Status. 29 1 read-only P30 Peripheral CD Status. 30 1 read-only P31 Peripheral CD Status. 31 1 read-only ESR Edge Select Register 0x000000C0 32 write-only P0 Edge Interrupt Selection. 0 1 write-only P1 Edge Interrupt Selection. 1 1 write-only P2 Edge Interrupt Selection. 2 1 write-only P3 Edge Interrupt Selection. 3 1 write-only P4 Edge Interrupt Selection. 4 1 write-only P5 Edge Interrupt Selection. 5 1 write-only P6 Edge Interrupt Selection. 6 1 write-only P7 Edge Interrupt Selection. 7 1 write-only P8 Edge Interrupt Selection. 8 1 write-only P9 Edge Interrupt Selection. 9 1 write-only P10 Edge Interrupt Selection. 10 1 write-only P11 Edge Interrupt Selection. 11 1 write-only P12 Edge Interrupt Selection. 12 1 write-only P13 Edge Interrupt Selection. 13 1 write-only P14 Edge Interrupt Selection. 14 1 write-only P15 Edge Interrupt Selection. 15 1 write-only P16 Edge Interrupt Selection. 16 1 write-only P17 Edge Interrupt Selection. 17 1 write-only P18 Edge Interrupt Selection. 18 1 write-only P19 Edge Interrupt Selection. 19 1 write-only P20 Edge Interrupt Selection. 20 1 write-only P21 Edge Interrupt Selection. 21 1 write-only P22 Edge Interrupt Selection. 22 1 write-only P23 Edge Interrupt Selection. 23 1 write-only P24 Edge Interrupt Selection. 24 1 write-only P25 Edge Interrupt Selection. 25 1 write-only P26 Edge Interrupt Selection. 26 1 write-only P27 Edge Interrupt Selection. 27 1 write-only P28 Edge Interrupt Selection. 28 1 write-only P29 Edge Interrupt Selection. 29 1 write-only P30 Edge Interrupt Selection. 30 1 write-only P31 Edge Interrupt Selection. 31 1 write-only LSR Level Select Register 0x000000C4 32 write-only P0 Level Interrupt Selection. 0 1 write-only P1 Level Interrupt Selection. 1 1 write-only P2 Level Interrupt Selection. 2 1 write-only P3 Level Interrupt Selection. 3 1 write-only P4 Level Interrupt Selection. 4 1 write-only P5 Level Interrupt Selection. 5 1 write-only P6 Level Interrupt Selection. 6 1 write-only P7 Level Interrupt Selection. 7 1 write-only P8 Level Interrupt Selection. 8 1 write-only P9 Level Interrupt Selection. 9 1 write-only P10 Level Interrupt Selection. 10 1 write-only P11 Level Interrupt Selection. 11 1 write-only P12 Level Interrupt Selection. 12 1 write-only P13 Level Interrupt Selection. 13 1 write-only P14 Level Interrupt Selection. 14 1 write-only P15 Level Interrupt Selection. 15 1 write-only P16 Level Interrupt Selection. 16 1 write-only P17 Level Interrupt Selection. 17 1 write-only P18 Level Interrupt Selection. 18 1 write-only P19 Level Interrupt Selection. 19 1 write-only P20 Level Interrupt Selection. 20 1 write-only P21 Level Interrupt Selection. 21 1 write-only P22 Level Interrupt Selection. 22 1 write-only P23 Level Interrupt Selection. 23 1 write-only P24 Level Interrupt Selection. 24 1 write-only P25 Level Interrupt Selection. 25 1 write-only P26 Level Interrupt Selection. 26 1 write-only P27 Level Interrupt Selection. 27 1 write-only P28 Level Interrupt Selection. 28 1 write-only P29 Level Interrupt Selection. 29 1 write-only P30 Level Interrupt Selection. 30 1 write-only P31 Level Interrupt Selection. 31 1 write-only ELSR Edge/Level Status Register 0x000000C8 32 read-only 0x00000000 P0 Edge/Level Interrupt source selection. 0 1 read-only P1 Edge/Level Interrupt source selection. 1 1 read-only P2 Edge/Level Interrupt source selection. 2 1 read-only P3 Edge/Level Interrupt source selection. 3 1 read-only P4 Edge/Level Interrupt source selection. 4 1 read-only P5 Edge/Level Interrupt source selection. 5 1 read-only P6 Edge/Level Interrupt source selection. 6 1 read-only P7 Edge/Level Interrupt source selection. 7 1 read-only P8 Edge/Level Interrupt source selection. 8 1 read-only P9 Edge/Level Interrupt source selection. 9 1 read-only P10 Edge/Level Interrupt source selection. 10 1 read-only P11 Edge/Level Interrupt source selection. 11 1 read-only P12 Edge/Level Interrupt source selection. 12 1 read-only P13 Edge/Level Interrupt source selection. 13 1 read-only P14 Edge/Level Interrupt source selection. 14 1 read-only P15 Edge/Level Interrupt source selection. 15 1 read-only P16 Edge/Level Interrupt source selection. 16 1 read-only P17 Edge/Level Interrupt source selection. 17 1 read-only P18 Edge/Level Interrupt source selection. 18 1 read-only P19 Edge/Level Interrupt source selection. 19 1 read-only P20 Edge/Level Interrupt source selection. 20 1 read-only P21 Edge/Level Interrupt source selection. 21 1 read-only P22 Edge/Level Interrupt source selection. 22 1 read-only P23 Edge/Level Interrupt source selection. 23 1 read-only P24 Edge/Level Interrupt source selection. 24 1 read-only P25 Edge/Level Interrupt source selection. 25 1 read-only P26 Edge/Level Interrupt source selection. 26 1 read-only P27 Edge/Level Interrupt source selection. 27 1 read-only P28 Edge/Level Interrupt source selection. 28 1 read-only P29 Edge/Level Interrupt source selection. 29 1 read-only P30 Edge/Level Interrupt source selection. 30 1 read-only P31 Edge/Level Interrupt source selection. 31 1 read-only FELLSR Falling Edge/Low Level Select Register 0x000000D0 32 write-only P0 Falling Edge/Low Level Interrupt Selection. 0 1 write-only P1 Falling Edge/Low Level Interrupt Selection. 1 1 write-only P2 Falling Edge/Low Level Interrupt Selection. 2 1 write-only P3 Falling Edge/Low Level Interrupt Selection. 3 1 write-only P4 Falling Edge/Low Level Interrupt Selection. 4 1 write-only P5 Falling Edge/Low Level Interrupt Selection. 5 1 write-only P6 Falling Edge/Low Level Interrupt Selection. 6 1 write-only P7 Falling Edge/Low Level Interrupt Selection. 7 1 write-only P8 Falling Edge/Low Level Interrupt Selection. 8 1 write-only P9 Falling Edge/Low Level Interrupt Selection. 9 1 write-only P10 Falling Edge/Low Level Interrupt Selection. 10 1 write-only P11 Falling Edge/Low Level Interrupt Selection. 11 1 write-only P12 Falling Edge/Low Level Interrupt Selection. 12 1 write-only P13 Falling Edge/Low Level Interrupt Selection. 13 1 write-only P14 Falling Edge/Low Level Interrupt Selection. 14 1 write-only P15 Falling Edge/Low Level Interrupt Selection. 15 1 write-only P16 Falling Edge/Low Level Interrupt Selection. 16 1 write-only P17 Falling Edge/Low Level Interrupt Selection. 17 1 write-only P18 Falling Edge/Low Level Interrupt Selection. 18 1 write-only P19 Falling Edge/Low Level Interrupt Selection. 19 1 write-only P20 Falling Edge/Low Level Interrupt Selection. 20 1 write-only P21 Falling Edge/Low Level Interrupt Selection. 21 1 write-only P22 Falling Edge/Low Level Interrupt Selection. 22 1 write-only P23 Falling Edge/Low Level Interrupt Selection. 23 1 write-only P24 Falling Edge/Low Level Interrupt Selection. 24 1 write-only P25 Falling Edge/Low Level Interrupt Selection. 25 1 write-only P26 Falling Edge/Low Level Interrupt Selection. 26 1 write-only P27 Falling Edge/Low Level Interrupt Selection. 27 1 write-only P28 Falling Edge/Low Level Interrupt Selection. 28 1 write-only P29 Falling Edge/Low Level Interrupt Selection. 29 1 write-only P30 Falling Edge/Low Level Interrupt Selection. 30 1 write-only P31 Falling Edge/Low Level Interrupt Selection. 31 1 write-only REHLSR Rising Edge/ High Level Select Register 0x000000D4 32 write-only P0 Rising Edge /High Level Interrupt Selection. 0 1 write-only P1 Rising Edge /High Level Interrupt Selection. 1 1 write-only P2 Rising Edge /High Level Interrupt Selection. 2 1 write-only P3 Rising Edge /High Level Interrupt Selection. 3 1 write-only P4 Rising Edge /High Level Interrupt Selection. 4 1 write-only P5 Rising Edge /High Level Interrupt Selection. 5 1 write-only P6 Rising Edge /High Level Interrupt Selection. 6 1 write-only P7 Rising Edge /High Level Interrupt Selection. 7 1 write-only P8 Rising Edge /High Level Interrupt Selection. 8 1 write-only P9 Rising Edge /High Level Interrupt Selection. 9 1 write-only P10 Rising Edge /High Level Interrupt Selection. 10 1 write-only P11 Rising Edge /High Level Interrupt Selection. 11 1 write-only P12 Rising Edge /High Level Interrupt Selection. 12 1 write-only P13 Rising Edge /High Level Interrupt Selection. 13 1 write-only P14 Rising Edge /High Level Interrupt Selection. 14 1 write-only P15 Rising Edge /High Level Interrupt Selection. 15 1 write-only P16 Rising Edge /High Level Interrupt Selection. 16 1 write-only P17 Rising Edge /High Level Interrupt Selection. 17 1 write-only P18 Rising Edge /High Level Interrupt Selection. 18 1 write-only P19 Rising Edge /High Level Interrupt Selection. 19 1 write-only P20 Rising Edge /High Level Interrupt Selection. 20 1 write-only P21 Rising Edge /High Level Interrupt Selection. 21 1 write-only P22 Rising Edge /High Level Interrupt Selection. 22 1 write-only P23 Rising Edge /High Level Interrupt Selection. 23 1 write-only P24 Rising Edge /High Level Interrupt Selection. 24 1 write-only P25 Rising Edge /High Level Interrupt Selection. 25 1 write-only P26 Rising Edge /High Level Interrupt Selection. 26 1 write-only P27 Rising Edge /High Level Interrupt Selection. 27 1 write-only P28 Rising Edge /High Level Interrupt Selection. 28 1 write-only P29 Rising Edge /High Level Interrupt Selection. 29 1 write-only P30 Rising Edge /High Level Interrupt Selection. 30 1 write-only P31 Rising Edge /High Level Interrupt Selection. 31 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0x000000D8 32 read-only 0x00000000 P0 Edge /Level Interrupt Source Selection. 0 1 read-only P1 Edge /Level Interrupt Source Selection. 1 1 read-only P2 Edge /Level Interrupt Source Selection. 2 1 read-only P3 Edge /Level Interrupt Source Selection. 3 1 read-only P4 Edge /Level Interrupt Source Selection. 4 1 read-only P5 Edge /Level Interrupt Source Selection. 5 1 read-only P6 Edge /Level Interrupt Source Selection. 6 1 read-only P7 Edge /Level Interrupt Source Selection. 7 1 read-only P8 Edge /Level Interrupt Source Selection. 8 1 read-only P9 Edge /Level Interrupt Source Selection. 9 1 read-only P10 Edge /Level Interrupt Source Selection. 10 1 read-only P11 Edge /Level Interrupt Source Selection. 11 1 read-only P12 Edge /Level Interrupt Source Selection. 12 1 read-only P13 Edge /Level Interrupt Source Selection. 13 1 read-only P14 Edge /Level Interrupt Source Selection. 14 1 read-only P15 Edge /Level Interrupt Source Selection. 15 1 read-only P16 Edge /Level Interrupt Source Selection. 16 1 read-only P17 Edge /Level Interrupt Source Selection. 17 1 read-only P18 Edge /Level Interrupt Source Selection. 18 1 read-only P19 Edge /Level Interrupt Source Selection. 19 1 read-only P20 Edge /Level Interrupt Source Selection. 20 1 read-only P21 Edge /Level Interrupt Source Selection. 21 1 read-only P22 Edge /Level Interrupt Source Selection. 22 1 read-only P23 Edge /Level Interrupt Source Selection. 23 1 read-only P24 Edge /Level Interrupt Source Selection. 24 1 read-only P25 Edge /Level Interrupt Source Selection. 25 1 read-only P26 Edge /Level Interrupt Source Selection. 26 1 read-only P27 Edge /Level Interrupt Source Selection. 27 1 read-only P28 Edge /Level Interrupt Source Selection. 28 1 read-only P29 Edge /Level Interrupt Source Selection. 29 1 read-only P30 Edge /Level Interrupt Source Selection. 30 1 read-only P31 Edge /Level Interrupt Source Selection. 31 1 read-only LOCKSR Lock Status 0x000000E0 32 read-only 0x00000000 P0 Lock Status. 0 1 read-only P1 Lock Status. 1 1 read-only P2 Lock Status. 2 1 read-only P3 Lock Status. 3 1 read-only P4 Lock Status. 4 1 read-only P5 Lock Status. 5 1 read-only P6 Lock Status. 6 1 read-only P7 Lock Status. 7 1 read-only P8 Lock Status. 8 1 read-only P9 Lock Status. 9 1 read-only P10 Lock Status. 10 1 read-only P11 Lock Status. 11 1 read-only P12 Lock Status. 12 1 read-only P13 Lock Status. 13 1 read-only P14 Lock Status. 14 1 read-only P15 Lock Status. 15 1 read-only P16 Lock Status. 16 1 read-only P17 Lock Status. 17 1 read-only P18 Lock Status. 18 1 read-only P19 Lock Status. 19 1 read-only P20 Lock Status. 20 1 read-only P21 Lock Status. 21 1 read-only P22 Lock Status. 22 1 read-only P23 Lock Status. 23 1 read-only P24 Lock Status. 24 1 read-only P25 Lock Status. 25 1 read-only P26 Lock Status. 26 1 read-only P27 Lock Status. 27 1 read-only P28 Lock Status. 28 1 read-only P29 Lock Status. 29 1 read-only P30 Lock Status. 30 1 read-only P31 Lock Status. 31 1 read-only WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write WPSR Write Protect Status Register 0x000000E8 32 read-only 0x00000000 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only RSTC 11009D Reset Controller SYSC RSTC_ 0x400E1A00 0 0x10 registers CR Control Register 0x00000000 32 write-only PROCRST Processor Reset 0 1 write-only PERRST Peripheral Reset 2 1 write-only EXTRST External Reset 3 1 write-only KEY System Reset Key 24 8 write-only PASSWD Writing any other value in this field aborts the write operation. 0xA5 SR Status Register 0x00000004 32 read-only 0x00000000 URSTS User Reset Status 0 1 read-only RSTTYP Reset Type 8 3 read-only GeneralReset First power-up Reset 0x0 BackupReset Return from Backup Mode 0x1 WatchdogReset Watchdog fault occurred 0x2 SoftwareReset Processor reset required by the software 0x3 UserReset NRST pin detected low 0x4 NRSTL NRST Pin Level 16 1 read-only SRCMP Software Reset Command in Progress 17 1 read-only MR Mode Register 0x00000008 32 read-write 0x00000001 URSTEN User Reset Enable 0 1 read-write URSTIEN User Reset Interrupt Enable 4 1 read-write ERSTL External Reset Length 8 4 read-write KEY Write Access Password 24 8 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0xA5 SUPC 6452S Supply Controller SYSC SUPC_ 0x400E1A10 0 0x18 registers CR Supply Controller Control Register 0x00000000 32 write-only VROFF Voltage Regulator Off 2 1 write-only NO_EFFECT no effect. 0 STOP_VREG if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. 1 XTALSEL Crystal Oscillator Select 3 1 write-only NO_EFFECT no effect. 0 CRYSTAL_SEL if KEY is correct, switches the slow clock on the crystal oscillator output. 1 KEY Password 24 8 write-only PASSWD Writing any other value in this field aborts the write operation. 0xA5 SMMR Supply Controller Supply Monitor Mode Register 0x00000004 32 read-write 0x00000000 SMTH Supply Monitor Threshold 0 4 read-write SMSMPL Supply Monitor Sampling Period 8 3 read-write SMD Supply Monitor disabled 0x0 CSM Continuous Supply Monitor 0x1 32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods 0x2 256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods 0x3 2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods 0x4 SMRSTEN Supply Monitor Reset Enable 12 1 read-write NOT_ENABLE the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. 0 ENABLE the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. 1 SMIEN Supply Monitor Interrupt Enable 13 1 read-write NOT_ENABLE the SUPC interrupt signal is not affected when a supply monitor detection occurs. 0 ENABLE the SUPC interrupt signal is asserted when a supply monitor detection occurs. 1 MR Supply Controller Mode Register 0x00000008 32 read-write 0x00005A00 BODRSTEN Brownout Detector Reset Enable 12 1 read-write NOT_ENABLE the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. 0 ENABLE the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. 1 BODDIS Brownout Detector Disable 13 1 read-write ENABLE the core brownout detector is enabled. 0 DISABLE the core brownout detector is disabled. 1 VDDIORDY VDDIO Ready 14 1 read-write VDDIO_REMOVED VDDIO is removed (used before going to backup mode when backup batteries are used) 0 VDDIO_PRESENT VDDIO is present (used before going to backup mode when backup batteries are used) 1 OSCBYPASS Oscillator Bypass 20 1 read-write NO_EFFECT no effect. Clock selection depends on XTALSEL value. 0 BYPASS the 32-KHz XTAL oscillator is selected and is put in bypass mode. 1 KEY Password Key 24 8 read-write PASSWD Writing any other value in this field aborts the write operation. 0xA5 WUMR Supply Controller Wake-up Mode Register 0x0000000C 32 read-write 0x00000000 FWUPEN Force Wake-up Enable 0 1 read-write NOT_ENABLE the Force Wake-up pin has no wake-up effect. 0 ENABLE the Force Wake-up pin low forces the wake-up of the core power supply. 1 SMEN Supply Monitor Wake-up Enable 1 1 read-write NOT_ENABLE the supply monitor detection has no wake-up effect. 0 ENABLE the supply monitor detection forces the wake-up of the core power supply. 1 RTTEN Real Time Timer Wake-up Enable 2 1 read-write NOT_ENABLE the RTT alarm signal has no wake-up effect. 0 ENABLE the RTT alarm signal forces the wake-up of the core power supply. 1 RTCEN Real Time Clock Wake-up Enable 3 1 read-write NOT_ENABLE the RTC alarm signal has no wake-up effect. 0 ENABLE the RTC alarm signal forces the wake-up of the core power supply. 1 FWUPDBC Force Wake-up Debouncer Period 8 3 read-write IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge. 0x0 3_SCLK FWUP shall be low for at least 3 SLCK periods 0x1 32_SCLK FWUP shall be low for at least 32 SLCK periods 0x2 512_SCLK FWUP shall be low for at least 512 SLCK periods 0x3 4096_SCLK FWUP shall be low for at least 4,096 SLCK periods 0x4 32768_SCLK FWUP shall be low for at least 32,768 SLCK periods 0x5 WKUPDBC Wake-up Inputs Debouncer Period 12 3 read-write IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge. 0x0 3_SCLK WKUPx shall be in its active state for at least 3 SLCK periods 0x1 32_SCLK WKUPx shall be in its active state for at least 32 SLCK periods 0x2 512_SCLK WKUPx shall be in its active state for at least 512 SLCK periods 0x3 4096_SCLK WKUPx shall be in its active state for at least 4,096 SLCK periods 0x4 32768_SCLK WKUPx shall be in its active state for at least 32,768 SLCK periods 0x5 WUIR Supply Controller Wake-up Inputs Register 0x00000010 32 read-write 0x00000000 WKUPEN0 Wake-up Input Enable 0 0 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN1 Wake-up Input Enable 1 1 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN2 Wake-up Input Enable 2 2 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN3 Wake-up Input Enable 3 3 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN4 Wake-up Input Enable 4 4 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN5 Wake-up Input Enable 5 5 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN6 Wake-up Input Enable 6 6 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN7 Wake-up Input Enable 7 7 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN8 Wake-up Input Enable 8 8 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN9 Wake-up Input Enable 9 9 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN10 Wake-up Input Enable 10 10 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN11 Wake-up Input Enable 11 11 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN12 Wake-up Input Enable 12 12 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN13 Wake-up Input Enable 13 13 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN14 Wake-up Input Enable 14 14 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN15 Wake-up Input Enable 15 15 1 read-write DISABLE the corresponding wake-up input has no wake-up effect. 0 ENABLE the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPT0 Wake-up Input Type 0 16 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT1 Wake-up Input Type 1 17 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT2 Wake-up Input Type 2 18 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT3 Wake-up Input Type 3 19 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT4 Wake-up Input Type 4 20 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT5 Wake-up Input Type 5 21 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT6 Wake-up Input Type 6 22 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT7 Wake-up Input Type 7 23 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT8 Wake-up Input Type 8 24 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT9 Wake-up Input Type 9 25 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT10 Wake-up Input Type 10 26 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT11 Wake-up Input Type 11 27 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT12 Wake-up Input Type 12 28 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT13 Wake-up Input Type 13 29 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT14 Wake-up Input Type 14 30 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 WKUPT15 Wake-up Input Type 15 31 1 read-write HIGH_TO_LOW a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 0 LOW_TO_HIGH a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. 1 SR Supply Controller Status Register 0x00000014 32 read-only 0x00000000 FWUPS FWUP Wake-up Status 0 1 read-only NO no wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. 0 PRESENT at least one wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. 1 WKUPS WKUP Wake-up Status 1 1 read-only NO no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 0 PRESENT at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 1 SMWS Supply Monitor Detection Wake-up Status 2 1 read-only NO no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. 0 PRESENT at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. 1 BODRSTS Brownout Detector Reset Status 3 1 read-only NO no core brownout rising edge event has been detected since the last read of the SUPC_SR. 0 PRESENT at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. 1 SMRSTS Supply Monitor Reset Status 4 1 read-only NO no supply monitor detection has generated a core reset since the last read of the SUPC_SR. 0 PRESENT at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. 1 SMS Supply Monitor Status 5 1 read-only NO no supply monitor detection since the last read of SUPC_SR. 0 PRESENT at least one supply monitor detection since the last read of SUPC_SR. 1 SMOS Supply Monitor Output Status 6 1 read-only HIGH the supply monitor detected VDDUTMI higher than its threshold at its last measurement. 0 LOW the supply monitor detected VDDUTMI lower than its threshold at its last measurement. 1 OSCSEL 32-kHz Oscillator Selection Status 7 1 read-only RC the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. 0 CRYST the slow clock, SLCK is generated by the 32-kHz crystal oscillator. 1 FWUPIS FWUP Input Status 12 1 read-only LOW FWUP input is tied low. 0 HIGH FWUP input is tied high. 1 WKUPIS0 WKUP Input Status 0 16 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS1 WKUP Input Status 1 17 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS2 WKUP Input Status 2 18 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS3 WKUP Input Status 3 19 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS4 WKUP Input Status 4 20 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS5 WKUP Input Status 5 21 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS6 WKUP Input Status 6 22 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS7 WKUP Input Status 7 23 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS8 WKUP Input Status 8 24 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS9 WKUP Input Status 9 25 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS10 WKUP Input Status 10 26 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS11 WKUP Input Status 11 27 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS12 WKUP Input Status 12 28 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS13 WKUP Input Status 13 29 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS14 WKUP Input Status 14 30 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS15 WKUP Input Status 15 31 1 read-only DIS the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 RTT 6081I Real-time Timer SYSC RTT_ 0x400E1A30 0 0x10 registers MR Mode Register 0x00000000 32 read-write 0x00008000 RTPRES Real-time Timer Prescaler Value 0 16 read-write ALMIEN Alarm Interrupt Enable 16 1 read-write RTTINCIEN Real-time Timer Increment Interrupt Enable 17 1 read-write RTTRST Real-time Timer Restart 18 1 read-write AR Alarm Register 0x00000004 32 read-write 0xFFFFFFFF ALMV Alarm Value 0 32 read-write VR Value Register 0x00000008 32 read-only 0x00000000 CRTV Current Real-time Value 0 32 read-only SR Status Register 0x0000000C 32 read-only 0x00000000 ALMS Real-time Alarm Status 0 1 read-only RTTINC Real-time Timer Increment 1 1 read-only WDT 6080F Watchdog Timer SYSC WDT_ 0x400E1A50 0 0x10 registers CR Control Register 0x00000000 32 write-only WDRSTT Watchdog Restart 0 1 write-only KEY Password. 24 8 write-only PASSWD Writing any other value in this field aborts the write operation. 0xA5 MR Mode Register 0x00000004 32 read-write 0x3FFF2FFF WDV Watchdog Counter Value 0 12 read-write WDFIEN Watchdog Fault Interrupt Enable 12 1 read-write WDRSTEN Watchdog Reset Enable 13 1 read-write WDRPROC Watchdog Reset Processor 14 1 read-write WDDIS Watchdog Disable 15 1 read-write WDD Watchdog Delta Value 16 12 read-write WDDBGHLT Watchdog Debug Halt 28 1 read-write WDIDLEHLT Watchdog Idle Halt 29 1 read-write SR Status Register 0x00000008 32 read-only 0x00000000 WDUNF Watchdog Underflow 0 1 read-only WDERR Watchdog Error 1 1 read-only RTC 6056O Real-time Clock SYSC RTC_ 0x400E1A60 0 0xE8 registers CR Control Register 0x00000000 32 read-write 0x00000000 UPDTIM Update Request Time Register 0 1 read-write UPDCAL Update Request Calendar Register 1 1 read-write TIMEVSEL Time Event Selection 8 2 read-write MINUTE Minute change 0x0 HOUR Hour change 0x1 MIDNIGHT Every day at midnight 0x2 NOON Every day at noon 0x3 CALEVSEL Calendar Event Selection 16 2 read-write WEEK Week change (every Monday at time 00:00:00) 0x0 MONTH Month change (every 01 of each month at time 00:00:00) 0x1 YEAR Year change (every January 1 at time 00:00:00) 0x2 MR Mode Register 0x00000004 32 read-write 0x00000000 HRMOD 12-/24-hour Mode 0 1 read-write TIMR Time Register 0x00000008 32 read-write 0x00000000 SEC Current Second 0 7 read-write MIN Current Minute 8 7 read-write HOUR Current Hour 16 6 read-write AMPM Ante Meridiem Post Meridiem Indicator 22 1 read-write CALR Calendar Register 0x0000000C 32 read-write 0x01210720 CENT Current Century 0 7 read-write YEAR Current Year 8 8 read-write MONTH Current Month 16 5 read-write DAY Current Day in Current Week 21 3 read-write DATE Current Day in Current Month 24 6 read-write TIMALR Time Alarm Register 0x00000010 32 read-write 0x00000000 SEC Second Alarm 0 7 read-write SECEN Second Alarm Enable 7 1 read-write MIN Minute Alarm 8 7 read-write MINEN Minute Alarm Enable 15 1 read-write HOUR Hour Alarm 16 6 read-write AMPM AM/PM Indicator 22 1 read-write HOUREN Hour Alarm Enable 23 1 read-write CALALR Calendar Alarm Register 0x00000014 32 read-write 0x01010000 MONTH Month Alarm 16 5 read-write MTHEN Month Alarm Enable 23 1 read-write DATE Date Alarm 24 6 read-write DATEEN Date Alarm Enable 31 1 read-write SR Status Register 0x00000018 32 read-only 0x00000000 ACKUPD Acknowledge for Update 0 1 read-only FREERUN Time and calendar registers cannot be updated. 0 UPDATE Time and calendar registers can be updated. 1 ALARM Alarm Flag 1 1 read-only NO_ALARMEVENT No alarm matching condition occurred. 0 ALARMEVENT An alarm matching condition has occurred. 1 SEC Second Event 2 1 read-only NO_SECEVENT No second event has occurred since the last clear. 0 SECEVENT At least one second event has occurred since the last clear. 1 TIMEV Time Event 3 1 read-only NO_TIMEVENT No time event has occurred since the last clear. 0 TIMEVENT At least one time event has occurred since the last clear. 1 CALEV Calendar Event 4 1 read-only NO_CALEVENT No calendar event has occurred since the last clear. 0 CALEVENT At least one calendar event has occurred since the last clear. 1 SCCR Status Clear Command Register 0x0000001C 32 write-only ACKCLR Acknowledge Clear 0 1 write-only ALRCLR Alarm Clear 1 1 write-only SECCLR Second Clear 2 1 write-only TIMCLR Time Clear 3 1 write-only CALCLR Calendar Clear 4 1 write-only IER Interrupt Enable Register 0x00000020 32 write-only ACKEN Acknowledge Update Interrupt Enable 0 1 write-only ALREN Alarm Interrupt Enable 1 1 write-only SECEN Second Event Interrupt Enable 2 1 write-only TIMEN Time Event Interrupt Enable 3 1 write-only CALEN Calendar Event Interrupt Enable 4 1 write-only IDR Interrupt Disable Register 0x00000024 32 write-only ACKDIS Acknowledge Update Interrupt Disable 0 1 write-only ALRDIS Alarm Interrupt Disable 1 1 write-only SECDIS Second Event Interrupt Disable 2 1 write-only TIMDIS Time Event Interrupt Disable 3 1 write-only CALDIS Calendar Event Interrupt Disable 4 1 write-only IMR Interrupt Mask Register 0x00000028 32 read-only 0x00000000 ACK Acknowledge Update Interrupt Mask 0 1 read-only ALR Alarm Interrupt Mask 1 1 read-only SEC Second Event Interrupt Mask 2 1 read-only TIM Time Event Interrupt Mask 3 1 read-only CAL Calendar Event Interrupt Mask 4 1 read-only VER Valid Entry Register 0x0000002C 32 read-only 0x00000000 NVTIM Non-valid Time 0 1 read-only NVCAL Non-valid Calendar 1 1 read-only NVTIMALR Non-valid Time Alarm 2 1 read-only NVCALALR Non-valid Calendar Alarm 3 1 read-only WPMR Write Protect Mode Register 0x000000E4 32 read-write 0x00000000 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x525443 GPBR 6378D General Purpose Backup Registers SYSC GPBR_ 0x400E1A90 0 0x20 registers 8 4 0-7 GPBR[%s] General Purpose Backup Register 0x00000000 32 read-write GPBR_VALUE Value of GPBR x 0 32 read-write