TIM: Timer $IpInstance Base_Init TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_DIRECTTI RemapConfig_TIM11_TI1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH1 TIM_CHANNEL_1 TIM_ICSELECTION_INDIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init SlaveConfigSynchronization IC_ConfigChannel_TRC1 TIM_CHANNEL_1 TIM_ICSELECTION_TRC TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH2 TIM_CHANNEL_2 TIM_ICSELECTION_DIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH2 TIM_CHANNEL_2 TIM_ICSELECTION_INDIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime SlaveConfigSynchronization IC_Init IC_ConfigChannel_TRC2 TIM_CHANNEL_2 TIM_ICSELECTION_TRC TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH3 TIM_CHANNEL_3 TIM_ICSELECTION_DIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH3 TIM_CHANNEL_3 TIM_ICSELECTION_INDIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init SlaveConfigSynchronization IC_ConfigChannel_TRC3 TIM_CHANNEL_3 TIM_ICSELECTION_TRC TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH4 TIM_CHANNEL_4 TIM_ICSELECTION_DIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH4 TIM_CHANNEL_4 TIM_ICSELECTION_DIRECTTI RemapConfig_TIM5_TI4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime IC_Init IC_ConfigChannel_CH4 TIM_CHANNEL_4 TIM_ICSELECTION_INDIRECTTI TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime SlaveConfigSynchronization IC_Init IC_ConfigChannel_TRC4 TIM_CHANNEL_4 TIM_ICSELECTION_TRC TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_1 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_2 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_3 TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_4 TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_1 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_2 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_3 TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_4 TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_1 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_2 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_3 TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_1 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_2 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_3 TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_1 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_2 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_3 TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_4 TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_1 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_2 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_3 TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_1 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_2 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OC_Init OC_ConfigChannel_forced_3 TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_1 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_2 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_3 TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_4 TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_1 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_2 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_3 TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_4 TIM_CHANNEL_4 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_1 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_2 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_3 TIM_CHANNEL_3 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_1 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_2 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Init PWM_ConfigChannel_3 TIM_CHANNEL_3 OnePulse_Init TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OPM_ConfigChannel_1 TIM_CHANNEL_1 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OPM_ConfigChannel_2 TIM_CHANNEL_2 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OPM_ConfigChannel_1 TIM_CHANNEL_1 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OPM_ConfigChannel_2 TIM_CHANNEL_2 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OPM_ConfigChannel_1 TIM_CHANNEL_1 TIM_CHANNEL_2 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime OPM_ConfigChannel_2 TIM_CHANNEL_2 TIM_CHANNEL_1 TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime HallSensor_Init TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime Encoder_Init TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Input_mode_CH1 TIM_TS_TI1FP1 TIM_SLAVEMODE_RESET TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime PWM_Input_mode_CH2 TIM_TS_TI2FP2 TIM_SLAVEMODE_RESET ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_CLOCKPOLARITY_INVERTED TIM_CLOCKPOLARITY_NONINVERTED TIM_CLOCKPRESCALER_DIV1 TIM_CLOCKPRESCALER_DIV2 TIM_CLOCKPRESCALER_DIV4 TIM_CLOCKPRESCALER_DIV8 ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_CLOCKPOLARITY_BOTHEDGE ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_CLOCKPOLARITY_RISING TIM_CLOCKPOLARITY_FALLING TIM_CLOCKPOLARITY_BOTHEDGE ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime TIM_CLOCKPOLARITY_RISING TIM_CLOCKPOLARITY_FALLING TIM_CLOCKPOLARITY_BOTHEDGE ConfigClockSource TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime RemapConfig_TIM5_ITR1 RemapConfig_TIM9_ITR1 ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime RemapConfig_TIM2_ITR1 ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime RemapConfig_TIM1_ITR2 ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigClockSource SlaveConfigSynchronization TIM_MasterConfigSynchronization TIM_ConfigBreakDeadTime ConfigOCrefClear ConfigTI1Input Semaphore_ClockSourceInternal$IpInstance Semaphore_Activated$IpInstance Semaphore_ControllerMode$IpInstance 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