Common ADC registers ADC 0x0 0x400 registers CSR CSR ADC Common status register 0x0 0x20 read-only 0x00000000 OVR3 Overrun flag of ADC3 21 1 STRT3 Regular channel Start flag of ADC 3 20 1 JSTRT3 Injected channel Start flag of ADC 3 19 1 JEOC3 Injected channel end of conversion of ADC 3 18 1 EOC3 End of conversion of ADC 3 17 1 AWD3 Analog watchdog flag of ADC 3 16 1 OVR2 Overrun flag of ADC 2 13 1 STRT2 Regular channel Start flag of ADC 2 12 1 JSTRT2 Injected channel Start flag of ADC 2 11 1 JEOC2 Injected channel end of conversion of ADC 2 10 1 EOC2 End of conversion of ADC 2 9 1 AWD2 Analog watchdog flag of ADC 2 8 1 OVR1 Overrun flag of ADC 1 5 1 STRT1 Regular channel Start flag of ADC 1 4 1 JSTRT1 Injected channel Start flag of ADC 1 3 1 JEOC1 Injected channel end of conversion of ADC 1 2 1 EOC1 End of conversion of ADC 1 1 1 AWD1 Analog watchdog flag of ADC 1 0 1 CCR CCR ADC common control register 0x4 0x20 read-write 0x00000000 TSVREFE Temperature sensor and VREFINT enable 23 1 VBATE VBAT enable 22 1 ADCPRE ADC prescaler 16 2 DMA Direct memory access mode for multi ADC mode 14 2 DDS DMA disable selection for multi-ADC mode 13 1 DELAY Delay between 2 sampling phases 8 4 MULT Multi ADC mode selection 0 5 CDR CDR ADC common regular data register for dual and triple modes 0x8 0x20 read-only 0x00000000 DATA2 2nd data item of a pair of regular conversions 16 16 DATA1 1st data item of a pair of regular conversions 0 16