Reset and clock control
RCC
0x0
0x400
registers
CR
CR
clock control register
0x0
0x20
0x00000083
PLLI2SRDY
PLLI2S clock ready flag
27
1
read-only
PLLI2SON
PLLI2S enable
26
1
read-write
PLLRDY
Main PLL (PLL) clock ready
flag
25
1
read-only
PLLON
Main PLL (PLL) enable
24
1
read-write
CSSON
Clock security system
enable
19
1
read-write
HSEBYP
HSE clock bypass
18
1
read-write
HSERDY
HSE clock ready flag
17
1
read-only
HSEON
HSE clock enable
16
1
read-write
HSICAL
Internal high-speed clock
calibration
8
8
read-only
HSITRIM
Internal high-speed clock
trimming
3
5
read-write
HSIRDY
Internal high-speed clock ready
flag
1
1
read-only
HSION
Internal high-speed clock
enable
0
1
read-write
PLLCFGR
PLLCFGR
PLL configuration register
0x4
0x20
read-write
0x24003010
PLLQ3
Main PLL (PLL) division factor for USB
OTG FS, SDIO and random number generator
clocks
27
1
PLLQ2
Main PLL (PLL) division factor for USB
OTG FS, SDIO and random number generator
clocks
26
1
PLLQ1
Main PLL (PLL) division factor for USB
OTG FS, SDIO and random number generator
clocks
25
1
PLLQ0
Main PLL (PLL) division factor for USB
OTG FS, SDIO and random number generator
clocks
24
1
PLLSRC
Main PLL(PLL) and audio PLL (PLLI2S)
entry clock source
22
1
PLLP1
Main PLL (PLL) division factor for main
system clock
17
1
PLLP0
Main PLL (PLL) division factor for main
system clock
16
1
PLLN8
Main PLL (PLL) multiplication factor for
VCO
14
1
PLLN7
Main PLL (PLL) multiplication factor for
VCO
13
1
PLLN6
Main PLL (PLL) multiplication factor for
VCO
12
1
PLLN5
Main PLL (PLL) multiplication factor for
VCO
11
1
PLLN4
Main PLL (PLL) multiplication factor for
VCO
10
1
PLLN3
Main PLL (PLL) multiplication factor for
VCO
9
1
PLLN2
Main PLL (PLL) multiplication factor for
VCO
8
1
PLLN1
Main PLL (PLL) multiplication factor for
VCO
7
1
PLLN0
Main PLL (PLL) multiplication factor for
VCO
6
1
PLLM5
Division factor for the main PLL (PLL)
and audio PLL (PLLI2S) input clock
5
1
PLLM4
Division factor for the main PLL (PLL)
and audio PLL (PLLI2S) input clock
4
1
PLLM3
Division factor for the main PLL (PLL)
and audio PLL (PLLI2S) input clock
3
1
PLLM2
Division factor for the main PLL (PLL)
and audio PLL (PLLI2S) input clock
2
1
PLLM1
Division factor for the main PLL (PLL)
and audio PLL (PLLI2S) input clock
1
1
PLLM0
Division factor for the main PLL (PLL)
and audio PLL (PLLI2S) input clock
0
1
CFGR
CFGR
clock configuration register
0x8
0x20
0x00000000
MCO2
Microcontroller clock output
2
30
2
read-write
MCO2PRE
MCO2 prescaler
27
3
read-write
MCO1PRE
MCO1 prescaler
24
3
read-write
I2SSRC
I2S clock selection
23
1
read-write
MCO1
Microcontroller clock output
1
21
2
read-write
RTCPRE
HSE division factor for RTC
clock
16
5
read-write
PPRE2
APB high-speed prescaler
(APB2)
13
3
read-write
PPRE1
APB Low speed prescaler
(APB1)
10
3
read-write
HPRE
AHB prescaler
4
4
read-write
SWS1
System clock switch status
3
1
read-only
SWS0
System clock switch status
2
1
read-only
SW1
System clock switch
1
1
read-write
SW0
System clock switch
0
1
read-write
CIR
CIR
clock interrupt register
0xC
0x20
0x00000000
CSSC
Clock security system interrupt
clear
23
1
write-only
PLLI2SRDYC
PLLI2S ready interrupt
clear
21
1
write-only
PLLRDYC
Main PLL(PLL) ready interrupt
clear
20
1
write-only
HSERDYC
HSE ready interrupt clear
19
1
write-only
HSIRDYC
HSI ready interrupt clear
18
1
write-only
LSERDYC
LSE ready interrupt clear
17
1
write-only
LSIRDYC
LSI ready interrupt clear
16
1
write-only
PLLI2SRDYIE
PLLI2S ready interrupt
enable
13
1
read-write
PLLRDYIE
Main PLL (PLL) ready interrupt
enable
12
1
read-write
HSERDYIE
HSE ready interrupt enable
11
1
read-write
HSIRDYIE
HSI ready interrupt enable
10
1
read-write
LSERDYIE
LSE ready interrupt enable
9
1
read-write
LSIRDYIE
LSI ready interrupt enable
8
1
read-write
CSSF
Clock security system interrupt
flag
7
1
read-only
PLLI2SRDYF
PLLI2S ready interrupt
flag
5
1
read-only
PLLRDYF
Main PLL (PLL) ready interrupt
flag
4
1
read-only
HSERDYF
HSE ready interrupt flag
3
1
read-only
HSIRDYF
HSI ready interrupt flag
2
1
read-only
LSERDYF
LSE ready interrupt flag
1
1
read-only
LSIRDYF
LSI ready interrupt flag
0
1
read-only
#ifdef __HAVE_SAI
PLLSAIRDYC
PLLSAI Ready Interrupt
Clear
22
1
write-only
PLLSAIRDYIE
PLLSAI Ready Interrupt
Enable
14
1
read-write
PLLSAIRDYF
PLLSAI ready interrupt
flag
6
1
read-only
#endif
AHB1RSTR
AHB1RSTR
AHB1 peripheral reset register
0x10
0x20
read-write
0x00000000
OTGHSRST
USB OTG HS module reset
29
1
#ifdef __HAVE_ETHERNET
ETHMACRST
Ethernet MAC reset
25
1
#endif
#ifdef __HAVE_DMA2D
DMA2DRST
DMA2D reset
23
1
#endif
DMA2RST
DMA2 reset
22
1
DMA1RST
DMA2 reset
21
1
CRCRST
CRC reset
12
1
GPIOIRST
IO port I reset
8
1
GPIOHRST
IO port H reset
7
1
GPIOGRST
IO port G reset
6
1
GPIOFRST
IO port F reset
5
1
GPIOERST
IO port E reset
4
1
GPIODRST
IO port D reset
3
1
GPIOCRST
IO port C reset
2
1
GPIOBRST
IO port B reset
1
1
GPIOARST
IO port A reset
0
1
#if defined(STM32F427) || defined(STM32F437) || defined(STM32F429) || defined(STM32F439)
GPIOKRST
IO port K reset
10
1
GPIOJRST
IO port J reset
9
1
#endif
AHB2RSTR
AHB2RSTR
AHB2 peripheral reset register
0x14
0x20
read-write
0x00000000
OTGFSRST
USB OTG FS module reset
7
1
RNGRST
Random number generator module
reset
6
1
#ifdef __HAVE_CRYPTO
HSAHRST
Hash module reset
5
1
CRYPRST
Cryptographic module reset
4
1
#endif
#ifdef __HAVE_DCMI
DCMIRST
Camera interface reset
0
1
#endif
AHB3RSTR
AHB3RSTR
AHB3 peripheral reset register
0x18
0x20
read-write
0x00000000
#ifdef __HAVE_FSMC
FSMCRST
Flexible static memory controller module
reset
0
1
#endif
#ifdef __HAVE_FMC
FMCRST
Flexible static memory controller module
reset
0
1
#endif
APB1RSTR
APB1RSTR
APB1 peripheral reset register
0x20
0x20
read-write
0x00000000
DACRST
DAC reset
29
1
PWRRST
Power interface reset
28
1
CAN2RST
CAN2 reset
26
1
CAN1RST
CAN1 reset
25
1
I2C3RST
I2C3 reset
23
1
I2C2RST
I2C 2 reset
22
1
I2C1RST
I2C 1 reset
21
1
UART5RST
USART 5 reset
20
1
UART4RST
USART 4 reset
19
1
UART3RST
USART 3 reset
18
1
UART2RST
USART 2 reset
17
1
SPI3RST
SPI 3 reset
15
1
SPI2RST
SPI 2 reset
14
1
WWDGRST
Window watchdog reset
11
1
TIM14RST
TIM14 reset
8
1
TIM13RST
TIM13 reset
7
1
TIM12RST
TIM12 reset
6
1
TIM7RST
TIM7 reset
5
1
TIM6RST
TIM6 reset
4
1
TIM5RST
TIM5 reset
3
1
TIM4RST
TIM4 reset
2
1
TIM3RST
TIM3 reset
1
1
TIM2RST
TIM2 reset
0
1
#if defined(STM32F427) || defined(STM32F437) || defined(STM32F429) || defined(STM32F439)
UART7RST
UART7 reset
30
1
UART8RST
UART8 reset
31
1
#endif
APB2RSTR
APB2RSTR
APB2 peripheral reset register
0x24
0x20
read-write
0x00000000
TIM11RST
TIM11 reset
18
1
TIM10RST
TIM10 reset
17
1
TIM9RST
TIM9 reset
16
1
SYSCFGRST
System configuration controller
reset
14
1
SPI1RST
SPI 1 reset
12
1
SDIORST
SDIO reset
11
1
ADCRST
ADC interface reset (common to all
ADCs)
8
1
USART6RST
USART6 reset
5
1
USART1RST
USART1 reset
4
1
TIM8RST
TIM8 reset
1
1
TIM1RST
TIM1 reset
0
1
#if defined(STM32F427) || defined(STM32F437) || defined(STM32F429) || defined(STM32F439)
SPI4RST
SPI4 reset
13
1
SPI5RST
SPI5 reset
20
1
SPI6RST
SPI6 reset
21
1
#endif
#ifdef __HAVE_SAI
SAI1RST
SAI1 reset
22
1
#endif
#ifdef __HAVE_LTDC
LTDCRST
LTDC reset
26
1
#endif
AHB1ENR
AHB1ENR
AHB1 peripheral clock register
0x30
0x20
read-write
0x00100000
OTGHSULPIEN
USB OTG HSULPI clock
enable
30
1
ENABLED
Disabled
Disabled.
0
Enabled
Enabled.
1
OTGHSEN
USB OTG HS clock enable
29
1
#ifdef __HAVE_ETHERNET
ETHMACPTPEN
Ethernet PTP clock enable
28
1
ETHMACRXEN
Ethernet Reception clock
enable
27
1
ETHMACTXEN
Ethernet Transmission clock
enable
26
1
ETHMACEN
Ethernet MAC clock enable
25
1
#endif
#ifdef __HAVE_DMA2D
DMA2DEN
DMA2D clock enable
23
1
#endif
DMA2EN
DMA2 clock enable
22
1
DMA1EN
DMA1 clock enable
21
1
CCMDATARAMEN
CCM data RAM clock enable
20
1
BKPSRAMEN
Backup SRAM interface clock
enable
18
1
CRCEN
CRC clock enable
12
1
GPIOIEN
IO port I clock enable
8
1
GPIOHEN
IO port H clock enable
7
1
GPIOGEN
IO port G clock enable
6
1
GPIOFEN
IO port F clock enable
5
1
GPIOEEN
IO port E clock enable
4
1
GPIODEN
IO port D clock enable
3
1
GPIOCEN
IO port C clock enable
2
1
GPIOBEN
IO port B clock enable
1
1
GPIOAEN
IO port A clock enable
0
1
#if defined(STM32F427) || defined(STM32F437) || defined(STM32F429) || defined(STM32F439)
GPIOKEN
IO port K clock enable
10
1
GPIOJEN
IO port J clock enable
9
1
#endif
AHB2ENR
AHB2ENR
AHB2 peripheral clock enable
register
0x34
0x20
read-write
0x00000000
OTGFSEN
USB OTG FS clock enable
7
1
RNGEN
Random number generator clock
enable
6
1
#ifdef __HAVE_CRYPTO
HASHEN
Hash modules clock enable
5
1
CRYPEN
Cryptographic modules clock
enable
4
1
#endif
#ifdef __HAVE_DCMI
DCMIEN
Camera interface enable
0
1
#endif
AHB3ENR
AHB3ENR
AHB3 peripheral clock enable
register
0x38
0x20
read-write
0x00000000
#ifdef __HAVE_FSMC
FSMCEN
Flexible static memory controller module
clock enable
0
1
#endif
#ifdef __HAVE_FMC
FMCEN
Flexible static memory controller module
clock enable
0
1
#endif
APB1ENR
APB1ENR
APB1 peripheral clock enable
register
0x40
0x20
read-write
0x00000000
DACEN
DAC interface clock enable
29
1
PWREN
Power interface clock
enable
28
1
CAN2EN
CAN 2 clock enable
26
1
CAN1EN
CAN 1 clock enable
25
1
I2C3EN
I2C3 clock enable
23
1
I2C2EN
I2C2 clock enable
22
1
I2C1EN
I2C1 clock enable
21
1
UART5EN
UART5 clock enable
20
1
UART4EN
UART4 clock enable
19
1
USART3EN
USART3 clock enable
18
1
USART2EN
USART 2 clock enable
17
1
SPI3EN
SPI3 clock enable
15
1
SPI2EN
SPI2 clock enable
14
1
WWDGEN
Window watchdog clock
enable
11
1
TIM14EN
TIM14 clock enable
8
1
TIM13EN
TIM13 clock enable
7
1
TIM12EN
TIM12 clock enable
6
1
TIM7EN
TIM7 clock enable
5
1
TIM6EN
TIM6 clock enable
4
1
TIM5EN
TIM5 clock enable
3
1
TIM4EN
TIM4 clock enable
2
1
TIM3EN
TIM3 clock enable
1
1
TIM2EN
TIM2 clock enable
0
1
#if defined(STM32F427) || defined(STM32F437) || defined(STM32F429) || defined(STM32F439)
UART7ENR
UART7 clock enable
30
1
UART8ENR
UART8 clock enable
31
1
#endif
APB2ENR
APB2ENR
APB2 peripheral clock enable
register
0x44
0x20
read-write
0x00000000
TIM11EN
TIM11 clock enable
18
1
TIM10EN
TIM10 clock enable
17
1
TIM9EN
TIM9 clock enable
16
1
SYSCFGEN
System configuration controller clock
enable
14
1
SPI1EN
SPI1 clock enable
12
1
SDIOEN
SDIO clock enable
11
1
ADC3EN
ADC3 clock enable
10
1
ADC2EN
ADC2 clock enable
9
1
ADC1EN
ADC1 clock enable
8
1
USART6EN
USART6 clock enable
5
1
USART1EN
USART1 clock enable
4
1
TIM8EN
TIM8 clock enable
1
1
TIM1EN
TIM1 clock enable
0
1
#if defined(STM32F427) || defined(STM32F437) || defined(STM32F429) || defined(STM32F439)
SPI4ENR
SPI4 clock enable
13
1
SPI5ENR
SPI5 clock enable
20
1
SPI6ENR
SPI6 clock enable
21
1
#endif
#ifdef __HAVE_SAI
SAI1EN
SAI1 clock enable
22
1
#endif
#ifdef __HAVE_LTDC
LTDCEN
LTDC clock enable
26
1
#endif
AHB1LPENR
AHB1LPENR
AHB1 peripheral clock enable in low power
mode register
0x50
0x20
read-write
0x7E6791FF
OTGHSULPILPEN
USB OTG HS ULPI clock enable during
Sleep mode
30
1
OTGHSLPEN
USB OTG HS clock enable during Sleep
mode
29
1
#ifdef __HAVE_ETHERNET
ETHMACPTPLPEN
Ethernet PTP clock enable during Sleep
mode
28
1
ETHMACRXLPEN
Ethernet reception clock enable during
Sleep mode
27
1
ETHMACTXLPEN
Ethernet transmission clock enable
during Sleep mode
26
1
ETHMACLPEN
Ethernet MAC clock enable during Sleep
mode
25
1
#endif
#ifdef __HAVE_DMA2D
DMA2DLPEN
DMA2D clock enable during Sleep
23
1
#endif
DMA2LPEN
DMA2 clock enable during Sleep
mode
22
1
DMA1LPEN
DMA1 clock enable during Sleep
mode
21
1
BKPSRAMLPEN
Backup SRAM interface clock enable
during Sleep mode
18
1
SRAM2LPEN
SRAM 2 interface clock enable during
Sleep mode
17
1
SRAM1LPEN
SRAM 1interface clock enable during
Sleep mode
16
1
FLITFLPEN
Flash interface clock enable during
Sleep mode
15
1
CRCLPEN
CRC clock enable during Sleep
mode
12
1
GPIOILPEN
IO port I clock enable during Sleep
mode
8
1
GPIOHLPEN
IO port H clock enable during Sleep
mode
7
1
GPIOGLPEN
IO port G clock enable during Sleep
mode
6
1
GPIOFLPEN
IO port F clock enable during Sleep
mode
5
1
GPIOELPEN
IO port E clock enable during Sleep
mode
4
1
GPIODLPEN
IO port D clock enable during Sleep
mode
3
1
GPIOCLPEN
IO port C clock enable during Sleep
mode
2
1
GPIOBLPEN
IO port B clock enable during Sleep
mode
1
1
GPIOALPEN
IO port A clock enable during sleep
mode
0
1
#if defined(STM32F427) || defined(STM32F437) || defined(STM32F429) || defined(STM32F439)
GPIOJLPEN
IO port J clock enable during Sleep
mode
9
1
GPIOKLPEN
IO port K clock enable during Sleep
mode
10
1
#endif
AHB2LPENR
AHB2LPENR
AHB2 peripheral clock enable in low power
mode register
0x54
0x20
read-write
0x000000F1
OTGFSLPEN
USB OTG FS clock enable during Sleep
mode
7
1
RNGLPEN
Random number generator clock enable
during Sleep mode
6
1
#ifdef __HAVE_CRYPTO
HASHLPEN
Hash modules clock enable during Sleep
mode
5
1
CRYPLPEN
Cryptography modules clock enable during
Sleep mode
4
1
#endif
#ifdef __HAVE_DCMI
DCMILPEN
Camera interface enable during Sleep
mode
0
1
#endif
AHB3LPENR
AHB3LPENR
AHB3 peripheral clock enable in low power
mode register
0x58
0x20
read-write
0x00000001
#ifdef __HAVE_FSMC
FSMCLPEN
Flexible static memory controller module
clock enable during Sleep mode
0
1
#endif
#ifdef __HAVE_FMC
FMCLPEN
Flexible static memory controller module
clock enable during Sleep mode
0
1
#endif
APB1LPENR
APB1LPENR
APB1 peripheral clock enable in low power
mode register
0x60
0x20
read-write
0x36FEC9FF
DACLPEN
DAC interface clock enable during Sleep
mode
29
1
PWRLPEN
Power interface clock enable during
Sleep mode
28
1
CAN2LPEN
CAN 2 clock enable during Sleep
mode
26
1
CAN1LPEN
CAN 1 clock enable during Sleep
mode
25
1
I2C3LPEN
I2C3 clock enable during Sleep
mode
23
1
I2C2LPEN
I2C2 clock enable during Sleep
mode
22
1
I2C1LPEN
I2C1 clock enable during Sleep
mode
21
1
UART5LPEN
UART5 clock enable during Sleep
mode
20
1
UART4LPEN
UART4 clock enable during Sleep
mode
19
1
USART3LPEN
USART3 clock enable during Sleep
mode
18
1
USART2LPEN
USART2 clock enable during Sleep
mode
17
1
SPI3LPEN
SPI3 clock enable during Sleep
mode
15
1
SPI2LPEN
SPI2 clock enable during Sleep
mode
14
1
WWDGLPEN
Window watchdog clock enable during
Sleep mode
11
1
TIM14LPEN
TIM14 clock enable during Sleep
mode
8
1
TIM13LPEN
TIM13 clock enable during Sleep
mode
7
1
TIM12LPEN
TIM12 clock enable during Sleep
mode
6
1
TIM7LPEN
TIM7 clock enable during Sleep
mode
5
1
TIM6LPEN
TIM6 clock enable during Sleep
mode
4
1
TIM5LPEN
TIM5 clock enable during Sleep
mode
3
1
TIM4LPEN
TIM4 clock enable during Sleep
mode
2
1
TIM3LPEN
TIM3 clock enable during Sleep
mode
1
1
TIM2LPEN
TIM2 clock enable during Sleep
mode
0
1
#if defined(STM32F427) || defined(STM32F437) || defined(STM32F429) || defined(STM32F439)
UART7LPEN
UART7 clock enable during Sleep
mode
30
1
UART8LPEN
UART8 clock enable during Sleep
mode
31
1
#endif
APB2LPENR
APB2LPENR
APB2 peripheral clock enabled in low power
mode register
0x64
0x20
read-write
0x00075F33
TIM11LPEN
TIM11 clock enable during Sleep
mode
18
1
TIM10LPEN
TIM10 clock enable during Sleep
mode
17
1
TIM9LPEN
TIM9 clock enable during sleep
mode
16
1
SYSCFGLPEN
System configuration controller clock
enable during Sleep mode
14
1
SPI1LPEN
SPI 1 clock enable during Sleep
mode
12
1
SDIOLPEN
SDIO clock enable during Sleep
mode
11
1
ADC3LPEN
ADC 3 clock enable during Sleep
mode
10
1
ADC2LPEN
ADC2 clock enable during Sleep
mode
9
1
ADC1LPEN
ADC1 clock enable during Sleep
mode
8
1
USART6LPEN
USART6 clock enable during Sleep
mode
5
1
USART1LPEN
USART1 clock enable during Sleep
mode
4
1
TIM8LPEN
TIM8 clock enable during Sleep
mode
1
1
TIM1LPEN
TIM1 clock enable during Sleep
mode
0
1
#if defined(STM32F427) || defined(STM32F437) || defined(STM32F429) || defined(STM32F439)
SPI4LPEN
SPI 4 clock enable during Sleep
mode
13
1
SPI5LPEN
SPI 5 clock enable during Sleep
mode
20
1
SPI6LPEN
SPI 6 clock enable during Sleep
mode
21
1
#endif
#ifdef __HAVE_SAI
SAI1LPEN
SAI1 clock enable
22
1
#endif
#ifdef __HAVE_LTDC
LTDCLPEN
LTDC clock enable
26
1
#endif
BDCR
BDCR
Backup domain control register
0x70
0x20
0x00000000
BDRST
Backup domain software
reset
16
1
read-write
RTCEN
RTC clock enable
15
1
read-write
RTCSEL1
RTC clock source selection
9
1
read-write
RTCSEL0
RTC clock source selection
8
1
read-write
LSEBYP
External low-speed oscillator
bypass
2
1
read-write
LSERDY
External low-speed oscillator
ready
1
1
read-only
LSEON
External low-speed oscillator
enable
0
1
read-write
CSR
CSR
clock control & status
register
0x74
0x20
0x0E000000
LPWRRSTF
Low-power reset flag
31
1
read-write
WWDGRSTF
Window watchdog reset flag
30
1
read-write
WDGRSTF
Independent watchdog reset
flag
29
1
read-write
SFTRSTF
Software reset flag
28
1
read-write
PORRSTF
POR/PDR reset flag
27
1
read-write
PADRSTF
PIN reset flag
26
1
read-write
BORRSTF
BOR reset flag
25
1
read-write
RMVF
Remove reset flag
24
1
read-write
LSIRDY
Internal low-speed oscillator
ready
1
1
read-only
LSION
Internal low-speed oscillator
enable
0
1
read-write
SSCGR
SSCGR
spread spectrum clock generation
register
0x80
0x20
read-write
0x00000000
SSCGEN
Spread spectrum modulation
enable
31
1
SPREADSEL
Spread Select
30
1
INCSTEP
Incrementation step
13
15
MODPER
Modulation period
0
13
PLLI2SCFGR
PLLI2SCFGR
PLLI2S configuration register
0x84
0x20
read-write
0x20003000
PLLI2SRx
PLLI2S division factor for I2S
clocks
28
3
#ifdef __HAVE_SAI
PLLI2SQx
PLLI2S division factor for SAI1
clocks
24
4
#endif
PLLI2SNx
PLLI2S multiplication factor for
VCO
6
9
#if defined(STM32F427) || defined(STM32F437) || defined(STM32F429) || defined(STM32F439)
PLLSAICFGR
PLLSAICFGR
PLLSAICFGR
0x88
0x20
read-write
0x24003000
PLLSAIN
PLLSAIN
6
9
PLLSAIQ
PLLSAIN
24
4
PLLSAIR
PLLSAIN
28
3
DCKCFGR
DCKCFGR
DCKCFGR
0x8C
0x20
read-write
0x00000000
PLLI2SDIVQ
PLLI2SDIVQ
0
5
PLLSAIDIVQ
PLLSAIDIVQ
8
5
PLLSAIDIVR
PLLSAIDIVR
16
2
SAI1ASRC
SAI1ASRC
20
2
SAI1BSRC
SAI1BSRC
22
2
TIMPRE
TIMPRE
24
1
#endif