#if !defined(__TIMER_ADVANCED) && !defined(__TIMER_GP) && !defined(__TIMER_GP_WITH_SYNC) && !defined(__TIMER_GP_WITH_TRIG) #define __TIMER_BASIC #endif #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_SYNC) || defined(__TIMER_GP) || defined(__TIMER_BASIC) #define __TIMER_WIDTH16 #endif #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) #define __TIMER_NUM_CCR 4 #elif defined(__TIMER_GP_WITH_SYNC) #define __TIMER_NUM_CCR 2 #elif defined(__TIMER_GP) #define __TIMER_NUM_CCR 1 #else #define __TIMER_NUM_CCR 0 #endif TIM 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 #ifndef __TIMER_BASIC CKD Clock division 8 2 #endif ARPE Auto-reload preload enable 7 1 #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) CMS Center-aligned mode selection 5 2 DIR Direction 4 1 #endif #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) || defined(__TIMER_GP_WITH_SYNC) || defined(__TIMER_BASIC) OPM One-pulse mode 3 1 Continuous Counter is not stopped at update event 0 OnePulse Counter stops counting at the next update event (clearing the CEN bit) 1 #endif URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 Disabled Counter disabled 0 Enabled Counter enabled 1 #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) || defined(__TIMER_GP_WITH_SYNC) || defined(__TIMER_BASIC) CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 #ifdef __TIMER_ADVANCED OIS4 Output Idle state 4 14 1 OIS3N Output Idle state 3 13 1 OIS3 Output Idle state 3 12 1 OIS2N Output Idle state 2 11 1 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 #endif #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) TI1S TI1 selection 7 1 #endif MMS Master mode selection 4 3 #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) CCDS Capture/compare DMA selection 3 1 #endif #ifdef __TIMER_ADVANCED CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 #endif #ifndef __TIMER_BASIC SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 #endif MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 #endif #endif DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) TDE Trigger DMA request enable 14 1 #ifdef __TIMER_ADVANCED COMDE COM DMA request enable 13 1 #endif CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 #endif #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) || defined(__TIMER_BASIC) UDE Update DMA request enable 8 1 #endif #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) || defined(__TIMER_GP_WITH_SYNC) TIE Trigger interrupt enable 6 1 #endif #if __TIMER_NUM_CCR >= 4 CC4IE Capture/Compare 4 interrupt enable 4 1 #endif #if __TIMER_NUM_CCR >= 3 CC3IE Capture/Compare 3 interrupt enable 3 1 #endif #if __TIMER_NUM_CCR >= 2 CC2IE Capture/Compare 2 interrupt enable 2 1 #endif #if __TIMER_NUM_CCR >= 1 CC1IE Capture/Compare 1 interrupt enable 1 1 #endif UIE Update interrupt enable 0 1 #ifdef __TIMER_ADVANCED BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 #endif SR SR status register 0x10 0x20 read-write 0x0000 #if __TIMER_NUM_CCR >= 4 CC4OF Capture/Compare 4 overcapture flag 12 1 #endif #if __TIMER_NUM_CCR >= 3 CC3OF Capture/Compare 3 overcapture flag 11 1 #endif #if __TIMER_NUM_CCR >= 2 CC2OF Capture/compare 2 overcapture flag 10 1 #endif #if __TIMER_NUM_CCR >= 1 CC1OF Capture/Compare 1 overcapture flag 9 1 #endif #ifdef __TIMER_ADVANCED BIF Break interrupt flag 7 1 #endif #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) || defined(__TIMER_GP_WITH_SYNC) TIF Trigger interrupt flag 6 1 #endif #ifdef __TIMER_ADVANCED COMIF COM interrupt flag 5 1 #endif #if __TIMER_NUM_CCR >= 4 CC4IF Capture/Compare 4 interrupt flag 4 1 #endif #if __TIMER_NUM_CCR >= 3 CC3IF Capture/Compare 3 interrupt flag 3 1 #endif #if __TIMER_NUM_CCR >= 2 CC2IF Capture/Compare 2 interrupt flag 2 1 #endif #if __TIMER_NUM_CCR >= 1 CC1IF Capture/compare 1 interrupt flag 1 1 #endif UIF Update interrupt flag 0 1 read NoUpdate No update occurred 0 Pending Update interrupt pending 1 write Clear Clears the update interrupt flag 0 EGR EGR event generation register 0x14 0x20 write-only 0x0000 #ifdef __TIMER_ADVANCED BG Break generation 7 1 #endif #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) || defined(__TIMER_GP_WITH_SYNC) TG Trigger generation 6 1 #endif #ifdef __TIMER_ADVANCED COMG Capture/Compare control update generation 5 1 #endif #if __TIMER_NUM_CCR >= 4 CC4G Capture/compare 4 generation 4 1 #endif #if __TIMER_NUM_CCR >= 3 CC3G Capture/compare 3 generation 3 1 #endif #if __TIMER_NUM_CCR >= 2 CC2G Capture/compare 2 generation 2 1 #endif #if __TIMER_NUM_CCR >= 1 CC1G Capture/compare 1 generation 1 1 #endif UG Update generation 0 1 #if __TIMER_NUM_CCR >= 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 #if __TIMER_NUM_CCR >= 2 #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) OC2CE Output Compare 2 clear enable 15 1 #endif OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 #endif #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) OC1CE Output Compare 1 clear enable 7 1 #endif OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 #if __TIMER_NUM_CCR >= 2 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 #endif IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 #endif #if __TIMER_NUM_CCR >= 3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 #if __TIMER_NUM_CCR >= 4 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 #endif OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 #if __TIMER_NUM_CCR >= 4 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 #endif IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 #endif #if __TIMER_NUM_CCR > 0 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 #if __TIMER_NUM_CCR >= 4 #ifndef __TIMER_ADVANCED CC4NP Capture/Compare 4 output Polarity 15 1 #endif CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 #endif #if __TIMER_NUM_CCR >= 3 CC3NP Capture/Compare 3 output Polarity 11 1 #ifdef __TIMER_ADVANCED CC3NE Capture/Compare 3 complementary output enable 10 1 #endif CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 #endif #if __TIMER_NUM_CCR >= 2 CC2NP Capture/Compare 2 output Polarity 7 1 #ifdef __TIMER_ADVANCED CC2NE Capture/Compare 2 complementary output enable 6 1 #endif CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 #endif #if __TIMER_NUM_CCR >= 1 CC1NP Capture/Compare 1 output Polarity 3 1 #ifdef __TIMER_ADVANCED CC1NE Capture/Compare 1 complementary output enable 2 1 #endif CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 #endif #endif CNT CNT counter 0x24 0x20 read-write 0x00000000 #ifdef __TIMER_WIDTH16 CNT counter value 0 16 #else CNT_H High counter value 16 16 CNT_L Low counter value 0 16 #endif PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 0 65535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 #ifdef __TIMER_WIDTH16 ARR Auto-reload value 0 16 0 65535 #else ARR_H High Auto-reload value 16 16 0 65535 ARR_L Low Auto-reload value 0 16 0 65535 #endif #if __TIMER_NUM_CCR >= 1 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 #ifdef __TIMER_WIDTH16 CCR1 Capture/Compare 1 value 0 16 #else CCR1_H High Capture/Compare 1 value 16 16 CCR1_L Low Capture/Compare 1 value 0 16 #endif #endif #if __TIMER_NUM_CCR >= 2 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 #ifdef __TIMER_WIDTH16 CCR2 Capture/Compare 2 value 0 16 #else CCR2_H High Capture/Compare 2 value 16 16 CCR2_L Low Capture/Compare 2 value 0 16 #endif #endif #if __TIMER_NUM_CCR >= 3 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 #ifdef __TIMER_WIDTH16 CCR3 Capture/Compare value 0 16 #else CCR3_H High Capture/Compare value 16 16 CCR3_L Low Capture/Compare value 0 16 #endif #endif #if __TIMER_NUM_CCR >= 4 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 #ifdef __TIMER_WIDTH16 CCR4 Capture/Compare value 0 16 #else CCR4_H High Capture/Compare value 16 16 CCR4_L Low Capture/Compare value 0 16 #endif #endif #if defined(__TIMER_ADVANCED) || defined(__TIMER_GP_WITH_TRIG) DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 #endif #ifdef __TIMER_ADVANCED RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 #endif #ifdef __TIMER_TIM2 OR OR TIM2 option register 0x50 0x20 read-write 0x0000 ITR1_RMP Internal trigger 1 remap 10 2 #endif #ifdef __TIMER_TIM5 OR OR TIM5 option register 0x50 0x20 read-write 0x0000 IT4_RMP Timer Input 4 remap 6 2 #endif #ifdef __TIMER_TIM11 OR OR option register 0x50 0x20 read-write 0x00000000 RMP Input 1 remapping capability 0 2 #endif #undef __TIMER_BASIC #undef __TIMER_ADVANCED #undef __TIMER_GP #undef __TIMER_GP_WITH_SYNC #undef __TIMER_GP_WITH_TRIG #undef __TIMER_TIM2 #undef __TIMER_TIM5 #undef __TIMER_TIM11 #undef __TIMER_WIDTH16 #undef __TIMER_NUM_CCR