STM32F0x0 1.2 STM32F0x0 CM0 r0p0 little false false 3 false 8 32 0x20 0x0 0xFFFFFFFF CRC cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 8-bit data register bits 0 8 CR CR Control register 0x8 0x20 read-write 0x00000000 RESET reset bit 0 1 POLYSIZE Polynomial size 3 2 REV_IN Reverse input data 5 2 REV_OUT Reverse output data 7 1 INIT INIT Initial CRC value 0xC 0x20 read-write 0xFFFFFFFF INIT Programmable initial CRC value 0 32 GPIOF General-purpose I/Os GPIO 0x48001400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000000 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bit 15 15 1 OT14 Port x configuration bit 14 14 1 OT13 Port x configuration bit 13 13 1 OT12 Port x configuration bit 12 12 1 OT11 Port x configuration bit 11 11 1 OT10 Port x configuration bit 10 10 1 OT9 Port x configuration bit 9 9 1 OT8 Port x configuration bit 8 8 1 OT7 Port x configuration bit 7 7 1 OT6 Port x configuration bit 6 6 1 OT5 Port x configuration bit 5 5 1 OT4 Port x configuration bit 4 4 1 OT3 Port x configuration bit 3 3 1 OT2 Port x configuration bit 2 2 1 OT1 Port x configuration bit 1 1 1 OT0 Port x configuration bit 0 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR Port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port x Reset bit y 0 1 BR1 Port x Reset bit y 1 1 BR2 Port x Reset bit y 2 1 BR3 Port x Reset bit y 3 1 BR4 Port x Reset bit y 4 1 BR5 Port x Reset bit y 5 1 BR6 Port x Reset bit y 6 1 BR7 Port x Reset bit y 7 1 BR8 Port x Reset bit y 8 1 BR9 Port x Reset bit y 9 1 BR10 Port x Reset bit y 10 1 BR11 Port x Reset bit y 11 1 BR12 Port x Reset bit y 12 1 BR13 Port x Reset bit y 13 1 BR14 Port x Reset bit y 14 1 BR15 Port x Reset bit y 15 1 GPIOD 0x48000C00 GPIOC 0x48000800 GPIOB 0x48000400 GPIOA General-purpose I/Os GPIO 0x48000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x28000000 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x24000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR Port bit reset register 0x28 0x20 write-only 0x00000000 BR0 Port x Reset bit y 0 1 BR1 Port x Reset bit y 1 1 BR2 Port x Reset bit y 2 1 BR3 Port x Reset bit y 3 1 BR4 Port x Reset bit y 4 1 BR5 Port x Reset bit y 5 1 BR6 Port x Reset bit y 6 1 BR7 Port x Reset bit y 7 1 BR8 Port x Reset bit y 8 1 BR9 Port x Reset bit y 9 1 BR10 Port x Reset bit y 10 1 BR11 Port x Reset bit y 11 1 BR12 Port x Reset bit y 12 1 BR13 Port x Reset bit y 13 1 BR14 Port x Reset bit y 14 1 BR15 Port x Reset bit y 15 1 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1_global_interrupt 25 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 RXONLY Receive only 10 1 SSM Software slave management 9 1 SSI Internal slave select 8 1 LSBFIRST Frame format 7 1 SPE SPI enable 6 1 BR Baud rate control 3 3 MSTR Master selection 2 1 CPOL Clock polarity 1 1 CPHA Clock phase 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 RXDMAEN Rx buffer DMA enable 0 1 TXDMAEN Tx buffer DMA enable 1 1 SSOE SS output enable 2 1 NSSP NSS pulse management 3 1 FRF Frame format 4 1 ERRIE Error interrupt enable 5 1 RXNEIE RX buffer not empty interrupt enable 6 1 TXEIE Tx buffer empty interrupt enable 7 1 DS Data size 8 4 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 SR SR status register 0x8 0x20 0x0002 RXNE Receive buffer not empty 0 1 read-only TXE Transmit buffer empty 1 1 read-only CHSIDE Channel side 2 1 read-only UDR Underrun flag 3 1 read-only CRCERR CRC error flag 4 1 read-write MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only BSY Busy flag 7 1 read-only TIFRFE TI frame format error 8 1 read-only FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only DR DR data register 0xC 0x20 read-write 0x0000 DR Data register 0 16 CRCPR CRCPR CRC polynomial register 0x10 0x20 read-write 0x0007 CRCPOLY CRC polynomial register 0 16 RXCRCR RXCRCR RX CRC register 0x14 0x20 read-only 0x0000 RxCRC Rx CRC register 0 16 TXCRCR TXCRCR TX CRC register 0x18 0x20 read-only 0x0000 TxCRC Tx CRC register 0 16 I2SCFGR I2SCFGR I2S configuration register 0x1C 0x20 read-write 0x0000 I2SMOD I2S mode selection 11 1 I2SE I2S Enable 10 1 I2SCFG I2S configuration mode 8 2 PCMSYNC PCM frame synchronization 7 1 I2SSTD I2S standard selection 4 2 CKPOL Steady state clock polarity 3 1 DATLEN Data length to be transferred 1 2 CHLEN Channel length (number of bits per audio channel) 0 1 I2SPR I2SPR I2S prescaler register 0x20 0x20 read-write 0x00000010 MCKOE Master clock output enable 9 1 ODD Odd factor for the prescaler 8 1 I2SDIV I2S Linear prescaler 0 8 SPI2 0x40003800 SPI2 SPI2 global interrupt 26 PWR Power control PWR 0x40007000 0x0 0x400 registers CR CR power control register 0x0 0x20 read-write 0x00000000 DBP Disable backup domain write protection 8 1 CSBF Clear standby flag 3 1 CWUF Clear wakeup flag 2 1 PDDS Power down deepsleep 1 1 LPDS Low-power deep sleep 0 1 CSR CSR power control/status register 0x4 0x20 0x00000000 WUF Wakeup flag 0 1 read-only SBF Standby flag 1 1 read-only EWUP1 Enable WKUP pin 1 8 1 read-write EWUP2 Enable WKUP pin 2 9 1 read-write EWUP4 Enable WKUP pin 4 11 1 read-write EWUP5 Enable WKUP pin 5 12 1 read-write EWUP6 Enable WKUP pin 6 13 1 read-write EWUP7 Enable WKUP pin 7 14 1 read-write I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1 I2C1 global interrupt 23 CR1 CR1 Control register 1 0x0 0x20 0x00000000 PE Peripheral enable 0 1 read-write TXIE TX Interrupt enable 1 1 read-write RXIE RX Interrupt enable 2 1 read-write ADDRIE Address match interrupt enable (slave only) 3 1 read-write NACKIE Not acknowledge received interrupt enable 4 1 read-write STOPIE STOP detection Interrupt enable 5 1 read-write TCIE Transfer Complete interrupt enable 6 1 read-write ERRIE Error interrupts enable 7 1 read-write DNF Digital noise filter 8 4 read-write ANFOFF Analog noise filter OFF 12 1 read-write SWRST Software reset 13 1 write-only TXDMAEN DMA transmission requests enable 14 1 read-write RXDMAEN DMA reception requests enable 15 1 read-write SBC Slave byte control 16 1 read-write NOSTRETCH Clock stretching disable 17 1 read-write WUPEN Wakeup from STOP enable 18 1 read-write GCEN General call enable 19 1 read-write SMBHEN SMBus Host address enable 20 1 read-write SMBDEN SMBus Device Default address enable 21 1 read-write ALERTEN SMBUS alert enable 22 1 read-write PECEN PEC enable 23 1 read-write CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 AUTOEND Automatic end mode (master mode) 25 1 RELOAD NBYTES reload mode 24 1 NBYTES Number of bytes 16 8 NACK NACK generation (slave mode) 15 1 STOP Stop generation (master mode) 14 1 START Start generation 13 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 ADD10 10-bit addressing mode (master mode) 11 1 RD_WRN Transfer direction (master mode) 10 1 SADD8 Slave address bit 9:8 (master mode) 8 2 SADD1 Slave address bit 7:1 (master mode) 1 7 SADD0 Slave address bit 0 (master mode) 0 1 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1_0 Interface address 0 1 OA1_1 Interface address 1 7 OA1_8 Interface address 8 2 OA1MODE Own Address 1 10-bit mode 10 1 OA1EN Own Address 1 enable 15 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 OA2MSK Own Address 2 masks 8 3 OA2EN Own Address 2 enable 15 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 SCLH SCL high period (master mode) 8 8 SDADEL Data hold time 16 4 SCLDEL Data setup time 20 4 PRESC Timing prescaler 28 4 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 TIDLE Idle clock timeout detection 12 1 TIMOUTEN Clock timeout enable 15 1 TIMEOUTB Bus timeout B 16 12 TEXTEN Extended clock timeout enable 31 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only DIR Transfer direction (Slave mode) 16 1 read-only BUSY Bus busy 15 1 read-only ALERT SMBus alert 13 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only PECERR PEC Error in reception 11 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only TCR Transfer Complete Reload 7 1 read-only TC Transfer Complete (master mode) 6 1 read-only STOPF Stop detection flag 5 1 read-only NACKF Not acknowledge received flag 4 1 read-only ADDR Address matched (slave mode) 3 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only TXIS Transmit interrupt status (transmitters) 1 1 read-write TXE Transmit data register empty (transmitters) 0 1 read-write ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 TIMOUTCF Timeout detection flag clear 12 1 PECCF PEC Error flag clear 11 1 OVRCF Overrun/Underrun flag clear 10 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 STOPCF Stop detection flag clear 5 1 NACKCF Not Acknowledge flag clear 4 1 ADDRCF Address Matched flag clear 3 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 I2C2 0x40005800 I2C2 I2C2 global interrupt 24 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x20 write-only 0x00000000 KEY Key value 0 16 PR PR Prescaler register 0x4 0x20 read-write 0x00000000 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 0x20 read-write 0x00000FFF RL Watchdog counter reload value 0 12 SR SR Status register 0xC 0x20 read-only 0x00000000 PVU Watchdog prescaler value update 0 1 RVU Watchdog counter reload value update 1 1 WVU Watchdog counter window value update 2 1 WINR WINR Window register 0x10 0x20 read-write 0x00000FFF WIN Watchdog counter window value 0 12 WWDG Window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 0 CR CR Control register 0x0 0x20 read-write 0x0000007F WDGA Activation bit 7 1 T 7-bit counter 0 7 CFR CFR Configuration register 0x4 0x20 read-write 0x0000007F EWI Early wakeup interrupt 9 1 WDGTB Timer base 7 2 W 7-bit window value 0 7 SR SR Status register 0x8 0x20 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 TIM1 Advanced-timers TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_UP_TRG_COM TIM1 break, update, trigger and commutation interrupt 13 TIM1_CC TIM1 Capture Compare interrupt 14 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS4 Output Idle state 4 14 1 OIS3N Output Idle state 3 13 1 OIS3 Output Idle state 3 12 1 OIS2N Output Idle state 2 11 1 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 TIE Trigger interrupt enable 6 1 COMIE COM interrupt enable 5 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 OC2CE Output Compare 2 clear enable 15 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3 Capture/Compare 3 value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4 Capture/Compare 3 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 TIM3 General-purpose-timers TIM 0x40000400 0x0 0x400 registers TIM3 TIM3 global interrupt 16 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE Output compare 2 clear enable 15 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/Compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAR DMA register for burst accesses 0 16 TIM14 General-purpose-timers TIM 0x40002000 0x0 0x400 registers TIM14 TIM14 global interrupt 19 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/Compare 1 overcapture flag 9 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 CC1S Capture/Compare 1 selection 0 2 OC1FE Output compare 1 fast enable 2 1 OC1PE Output Compare 1 preload enable 3 1 OC1M Output Compare 1 mode 4 3 CCMR1_Input CCMR1_Input capture/compare mode register (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 OR OR option register 0x50 0x20 read-write 0x00000000 RMP Timer input 1 remap 0 2 TIM6 Basic-timers TIM 0x40001000 0x0 0x400 registers TIM6 TIM6 global interrupt 17 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 ARPE Auto-reload preload enable 7 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 MMS Master mode selection 4 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Low counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Low Auto-reload value 0 16 TIM7 0x40001400 EXTI External interrupt/event controller EXTI 0x40010400 0x0 0x400 registers PVD PVD and VDDIO2 supply comparator interrupt 1 EXTI0_1 EXTI Line[1:0] interrupts 5 EXTI2_3 EXTI Line[3:2] interrupts 6 EXTI4_15 EXTI Line15 and EXTI4 interrupts 7 IMR IMR Interrupt mask register (EXTI_IMR) 0x0 0x20 read-write 0x0F940000 MR0 Interrupt Mask on line 0 0 1 MR1 Interrupt Mask on line 1 1 1 MR2 Interrupt Mask on line 2 2 1 MR3 Interrupt Mask on line 3 3 1 MR4 Interrupt Mask on line 4 4 1 MR5 Interrupt Mask on line 5 5 1 MR6 Interrupt Mask on line 6 6 1 MR7 Interrupt Mask on line 7 7 1 MR8 Interrupt Mask on line 8 8 1 MR9 Interrupt Mask on line 9 9 1 MR10 Interrupt Mask on line 10 10 1 MR11 Interrupt Mask on line 11 11 1 MR12 Interrupt Mask on line 12 12 1 MR13 Interrupt Mask on line 13 13 1 MR14 Interrupt Mask on line 14 14 1 MR15 Interrupt Mask on line 15 15 1 MR16 Interrupt Mask on line 16 16 1 MR17 Interrupt Mask on line 17 17 1 MR18 Interrupt Mask on line 18 18 1 MR19 Interrupt Mask on line 19 19 1 MR20 Interrupt Mask on line 20 20 1 MR21 Interrupt Mask on line 21 21 1 MR22 Interrupt Mask on line 22 22 1 MR23 Interrupt Mask on line 23 23 1 MR24 Interrupt Mask on line 24 24 1 MR25 Interrupt Mask on line 25 25 1 MR26 Interrupt Mask on line 26 26 1 MR27 Interrupt Mask on line 27 27 1 EMR EMR Event mask register (EXTI_EMR) 0x4 0x20 read-write 0x00000000 MR0 Event Mask on line 0 0 1 MR1 Event Mask on line 1 1 1 MR2 Event Mask on line 2 2 1 MR3 Event Mask on line 3 3 1 MR4 Event Mask on line 4 4 1 MR5 Event Mask on line 5 5 1 MR6 Event Mask on line 6 6 1 MR7 Event Mask on line 7 7 1 MR8 Event Mask on line 8 8 1 MR9 Event Mask on line 9 9 1 MR10 Event Mask on line 10 10 1 MR11 Event Mask on line 11 11 1 MR12 Event Mask on line 12 12 1 MR13 Event Mask on line 13 13 1 MR14 Event Mask on line 14 14 1 MR15 Event Mask on line 15 15 1 MR16 Event Mask on line 16 16 1 MR17 Event Mask on line 17 17 1 MR18 Event Mask on line 18 18 1 MR19 Event Mask on line 19 19 1 MR20 Event Mask on line 20 20 1 MR21 Event Mask on line 21 21 1 MR22 Event Mask on line 22 22 1 MR23 Event Mask on line 23 23 1 MR24 Event Mask on line 24 24 1 MR25 Event Mask on line 25 25 1 MR26 Event Mask on line 26 26 1 MR27 Event Mask on line 27 27 1 RTSR RTSR Rising Trigger selection register (EXTI_RTSR) 0x8 0x20 read-write 0x00000000 TR0 Rising trigger event configuration of line 0 0 1 TR1 Rising trigger event configuration of line 1 1 1 TR2 Rising trigger event configuration of line 2 2 1 TR3 Rising trigger event configuration of line 3 3 1 TR4 Rising trigger event configuration of line 4 4 1 TR5 Rising trigger event configuration of line 5 5 1 TR6 Rising trigger event configuration of line 6 6 1 TR7 Rising trigger event configuration of line 7 7 1 TR8 Rising trigger event configuration of line 8 8 1 TR9 Rising trigger event configuration of line 9 9 1 TR10 Rising trigger event configuration of line 10 10 1 TR11 Rising trigger event configuration of line 11 11 1 TR12 Rising trigger event configuration of line 12 12 1 TR13 Rising trigger event configuration of line 13 13 1 TR14 Rising trigger event configuration of line 14 14 1 TR15 Rising trigger event configuration of line 15 15 1 TR16 Rising trigger event configuration of line 16 16 1 TR17 Rising trigger event configuration of line 17 17 1 TR19 Rising trigger event configuration of line 19 19 1 FTSR FTSR Falling Trigger selection register (EXTI_FTSR) 0xC 0x20 read-write 0x00000000 TR0 Falling trigger event configuration of line 0 0 1 TR1 Falling trigger event configuration of line 1 1 1 TR2 Falling trigger event configuration of line 2 2 1 TR3 Falling trigger event configuration of line 3 3 1 TR4 Falling trigger event configuration of line 4 4 1 TR5 Falling trigger event configuration of line 5 5 1 TR6 Falling trigger event configuration of line 6 6 1 TR7 Falling trigger event configuration of line 7 7 1 TR8 Falling trigger event configuration of line 8 8 1 TR9 Falling trigger event configuration of line 9 9 1 TR10 Falling trigger event configuration of line 10 10 1 TR11 Falling trigger event configuration of line 11 11 1 TR12 Falling trigger event configuration of line 12 12 1 TR13 Falling trigger event configuration of line 13 13 1 TR14 Falling trigger event configuration of line 14 14 1 TR15 Falling trigger event configuration of line 15 15 1 TR16 Falling trigger event configuration of line 16 16 1 TR17 Falling trigger event configuration of line 17 17 1 TR19 Falling trigger event configuration of line 19 19 1 SWIER SWIER Software interrupt event register (EXTI_SWIER) 0x10 0x20 read-write 0x00000000 SWIER0 Software Interrupt on line 0 0 1 SWIER1 Software Interrupt on line 1 1 1 SWIER2 Software Interrupt on line 2 2 1 SWIER3 Software Interrupt on line 3 3 1 SWIER4 Software Interrupt on line 4 4 1 SWIER5 Software Interrupt on line 5 5 1 SWIER6 Software Interrupt on line 6 6 1 SWIER7 Software Interrupt on line 7 7 1 SWIER8 Software Interrupt on line 8 8 1 SWIER9 Software Interrupt on line 9 9 1 SWIER10 Software Interrupt on line 10 10 1 SWIER11 Software Interrupt on line 11 11 1 SWIER12 Software Interrupt on line 12 12 1 SWIER13 Software Interrupt on line 13 13 1 SWIER14 Software Interrupt on line 14 14 1 SWIER15 Software Interrupt on line 15 15 1 SWIER16 Software Interrupt on line 16 16 1 SWIER17 Software Interrupt on line 17 17 1 SWIER19 Software Interrupt on line 19 19 1 PR PR Pending register (EXTI_PR) 0x14 0x20 read-write 0x00000000 PR0 Pending bit 0 0 1 PR1 Pending bit 1 1 1 PR2 Pending bit 2 2 1 PR3 Pending bit 3 3 1 PR4 Pending bit 4 4 1 PR5 Pending bit 5 5 1 PR6 Pending bit 6 6 1 PR7 Pending bit 7 7 1 PR8 Pending bit 8 8 1 PR9 Pending bit 9 9 1 PR10 Pending bit 10 10 1 PR11 Pending bit 11 11 1 PR12 Pending bit 12 12 1 PR13 Pending bit 13 13 1 PR14 Pending bit 14 14 1 PR15 Pending bit 15 15 1 PR16 Pending bit 16 16 1 PR17 Pending bit 17 17 1 PR19 Pending bit 19 19 1 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0x0 0x33D registers ISER ISER Interrupt Set Enable Register 0x0 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER ICER Interrupt Clear Enable Register 0x80 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR ISPR Interrupt Set-Pending Register 0x100 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR ICPR Interrupt Clear-Pending Register 0x180 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IPR0 IPR0 Interrupt Priority Register 0 0x300 0x20 read-write 0x00000000 PRI_00 PRI_00 6 2 PRI_01 PRI_01 14 2 PRI_02 PRI_02 22 2 PRI_03 PRI_03 30 2 IPR1 IPR1 Interrupt Priority Register 1 0x304 0x20 read-write 0x00000000 PRI_40 PRI_40 6 2 PRI_41 PRI_41 14 2 PRI_42 PRI_42 22 2 PRI_43 PRI_43 30 2 IPR2 IPR2 Interrupt Priority Register 2 0x308 0x20 read-write 0x00000000 PRI_80 PRI_80 6 2 PRI_81 PRI_81 14 2 PRI_82 PRI_82 22 2 PRI_83 PRI_83 30 2 IPR3 IPR3 Interrupt Priority Register 3 0x30C 0x20 read-write 0x00000000 PRI_120 PRI_120 6 2 PRI_121 PRI_121 14 2 PRI_122 PRI_122 22 2 PRI_123 PRI_123 30 2 IPR4 IPR4 Interrupt Priority Register 4 0x310 0x20 read-write 0x00000000 PRI_160 PRI_160 6 2 PRI_161 PRI_161 14 2 PRI_162 PRI_162 22 2 PRI_163 PRI_163 30 2 IPR5 IPR5 Interrupt Priority Register 5 0x314 0x20 read-write 0x00000000 PRI_200 PRI_200 6 2 PRI_201 PRI_201 14 2 PRI_202 PRI_202 22 2 PRI_203 PRI_203 30 2 IPR6 IPR6 Interrupt Priority Register 6 0x318 0x20 read-write 0x00000000 PRI_240 PRI_240 6 2 PRI_241 PRI_241 14 2 PRI_242 PRI_242 22 2 PRI_243 PRI_243 30 2 IPR7 IPR7 Interrupt Priority Register 7 0x31C 0x20 read-write 0x00000000 PRI_280 PRI_280 6 2 PRI_281 PRI_281 14 2 PRI_282 PRI_282 22 2 PRI_283 PRI_283 30 2 DMA1 DMA controller DMA 0x40020000 0x0 0x400 registers DMA1_CH1 DMA1 channel 1 interrupt 9 DMA1_CH2_3 DMA1 channel 2 and 3 interrupt 10 DMA1_CH4_5 DMA1 channel 4 and 5 interrupt 11 ISR ISR DMA interrupt status register (DMA_ISR) 0x0 0x20 read-only 0x00000000 GIF1 Channel 1 Global interrupt flag 0 1 TCIF1 Channel 1 Transfer Complete flag 1 1 HTIF1 Channel 1 Half Transfer Complete flag 2 1 TEIF1 Channel 1 Transfer Error flag 3 1 GIF2 Channel 2 Global interrupt flag 4 1 TCIF2 Channel 2 Transfer Complete flag 5 1 HTIF2 Channel 2 Half Transfer Complete flag 6 1 TEIF2 Channel 2 Transfer Error flag 7 1 GIF3 Channel 3 Global interrupt flag 8 1 TCIF3 Channel 3 Transfer Complete flag 9 1 HTIF3 Channel 3 Half Transfer Complete flag 10 1 TEIF3 Channel 3 Transfer Error flag 11 1 GIF4 Channel 4 Global interrupt flag 12 1 TCIF4 Channel 4 Transfer Complete flag 13 1 HTIF4 Channel 4 Half Transfer Complete flag 14 1 TEIF4 Channel 4 Transfer Error flag 15 1 GIF5 Channel 5 Global interrupt flag 16 1 TCIF5 Channel 5 Transfer Complete flag 17 1 HTIF5 Channel 5 Half Transfer Complete flag 18 1 TEIF5 Channel 5 Transfer Error flag 19 1 GIF6 Channel 6 Global interrupt flag 20 1 TCIF6 Channel 6 Transfer Complete flag 21 1 HTIF6 Channel 6 Half Transfer Complete flag 22 1 TEIF6 Channel 6 Transfer Error flag 23 1 GIF7 Channel 7 Global interrupt flag 24 1 TCIF7 Channel 7 Transfer Complete flag 25 1 HTIF7 Channel 7 Half Transfer Complete flag 26 1 TEIF7 Channel 7 Transfer Error flag 27 1 IFCR IFCR DMA interrupt flag clear register (DMA_IFCR) 0x4 0x20 write-only 0x00000000 CGIF1 Channel 1 Global interrupt clear 0 1 CTCIF1 Channel 1 Transfer Complete clear 1 1 CHTIF1 Channel 1 Half Transfer clear 2 1 CTEIF1 Channel 1 Transfer Error clear 3 1 CGIF2 Channel 2 Global interrupt clear 4 1 CTCIF2 Channel 2 Transfer Complete clear 5 1 CHTIF2 Channel 2 Half Transfer clear 6 1 CTEIF2 Channel 2 Transfer Error clear 7 1 CGIF3 Channel 3 Global interrupt clear 8 1 CTCIF3 Channel 3 Transfer Complete clear 9 1 CHTIF3 Channel 3 Half Transfer clear 10 1 CTEIF3 Channel 3 Transfer Error clear 11 1 CGIF4 Channel 4 Global interrupt clear 12 1 CTCIF4 Channel 4 Transfer Complete clear 13 1 CHTIF4 Channel 4 Half Transfer clear 14 1 CTEIF4 Channel 4 Transfer Error clear 15 1 CGIF5 Channel 5 Global interrupt clear 16 1 CTCIF5 Channel 5 Transfer Complete clear 17 1 CHTIF5 Channel 5 Half Transfer clear 18 1 CTEIF5 Channel 5 Transfer Error clear 19 1 CGIF6 Channel 6 Global interrupt clear 20 1 CTCIF6 Channel 6 Transfer Complete clear 21 1 CHTIF6 Channel 6 Half Transfer clear 22 1 CTEIF6 Channel 6 Transfer Error clear 23 1 CGIF7 Channel 7 Global interrupt clear 24 1 CTCIF7 Channel 7 Transfer Complete clear 25 1 CHTIF7 Channel 7 Half Transfer clear 26 1 CTEIF7 Channel 7 Transfer Error clear 27 1 CCR1 CCR1 DMA channel configuration register (DMA_CCR) 0x8 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNDTR1 CNDTR1 DMA channel 1 number of data register 0xC 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR1 CPAR1 DMA channel 1 peripheral address register 0x10 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR1 CMAR1 DMA channel 1 memory address register 0x14 0x20 read-write 0x00000000 MA Memory address 0 32 CCR2 CCR2 DMA channel configuration register (DMA_CCR) 0x1C 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNDTR2 CNDTR2 DMA channel 2 number of data register 0x20 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR2 CPAR2 DMA channel 2 peripheral address register 0x24 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR2 CMAR2 DMA channel 2 memory address register 0x28 0x20 read-write 0x00000000 MA Memory address 0 32 CCR3 CCR3 DMA channel configuration register (DMA_CCR) 0x30 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNDTR3 CNDTR3 DMA channel 3 number of data register 0x34 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR3 CPAR3 DMA channel 3 peripheral address register 0x38 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR3 CMAR3 DMA channel 3 memory address register 0x3C 0x20 read-write 0x00000000 MA Memory address 0 32 CCR4 CCR4 DMA channel configuration register (DMA_CCR) 0x44 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNDTR4 CNDTR4 DMA channel 4 number of data register 0x48 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR4 CPAR4 DMA channel 4 peripheral address register 0x4C 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR4 CMAR4 DMA channel 4 memory address register 0x50 0x20 read-write 0x00000000 MA Memory address 0 32 CCR5 CCR5 DMA channel configuration register (DMA_CCR) 0x58 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNDTR5 CNDTR5 DMA channel 5 number of data register 0x5C 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR5 CPAR5 DMA channel 5 peripheral address register 0x60 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR5 CMAR5 DMA channel 5 memory address register 0x64 0x20 read-write 0x00000000 MA Memory address 0 32 CCR6 CCR6 DMA channel configuration register (DMA_CCR) 0x6C 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNDTR6 CNDTR6 DMA channel 6 number of data register 0x70 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR6 CPAR6 DMA channel 6 peripheral address register 0x74 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR6 CMAR6 DMA channel 6 memory address register 0x78 0x20 read-write 0x00000000 MA Memory address 0 32 CCR7 CCR7 DMA channel configuration register (DMA_CCR) 0x80 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNDTR7 CNDTR7 DMA channel 7 number of data register 0x84 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR7 CPAR7 DMA channel 7 peripheral address register 0x88 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR7 CMAR7 DMA channel 7 memory address register 0x8C 0x20 read-write 0x00000000 MA Memory address 0 32 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global interruptr 4 CR CR Clock control register 0x0 0x20 0x00000083 HSION Internal High Speed clock enable 0 1 read-write HSIRDY Internal High Speed clock ready flag 1 1 read-only HSITRIM Internal High Speed clock trimming 3 5 read-write HSICAL Internal High Speed clock Calibration 8 8 read-only HSEON External High Speed clock enable 16 1 read-write HSERDY External High Speed clock ready flag 17 1 read-only HSEBYP External High Speed clock Bypass 18 1 read-write CSSON Clock Security System enable 19 1 read-write PLLON PLL enable 24 1 read-write PLLRDY PLL clock ready flag 25 1 read-only CFGR CFGR Clock configuration register (RCC_CFGR) 0x4 0x20 0x00000000 SW System clock Switch 0 2 read-write SWS System Clock Switch Status 2 2 read-only HPRE AHB prescaler 4 4 read-write PPRE APB Low speed prescaler (APB1) 8 3 read-write ADCPRE ADC prescaler 14 1 read-write PLLSRC PLL input clock source 15 2 read-write PLLXTPRE HSE divider for PLL entry 17 1 read-write PLLMUL PLL Multiplication Factor 18 4 read-write MCO Microcontroller clock output 24 3 read-write MCOPRE Microcontroller Clock Output Prescaler 28 3 read-write PLLNODIV PLL clock not divided for MCO 31 1 read-write CIR CIR Clock interrupt register (RCC_CIR) 0x8 0x20 0x00000000 LSIRDYF LSI Ready Interrupt flag 0 1 read-only LSERDYF LSE Ready Interrupt flag 1 1 read-only HSIRDYF HSI Ready Interrupt flag 2 1 read-only HSERDYF HSE Ready Interrupt flag 3 1 read-only PLLRDYF PLL Ready Interrupt flag 4 1 read-only HSI14RDYF HSI14 ready interrupt flag 5 1 read-only HSI48RDYF HSI48 ready interrupt flag 6 1 read-only CSSF Clock Security System Interrupt flag 7 1 read-only LSIRDYIE LSI Ready Interrupt Enable 8 1 read-write LSERDYIE LSE Ready Interrupt Enable 9 1 read-write HSIRDYIE HSI Ready Interrupt Enable 10 1 read-write HSERDYIE HSE Ready Interrupt Enable 11 1 read-write PLLRDYIE PLL Ready Interrupt Enable 12 1 read-write HSI14RDYE HSI14 ready interrupt enable 13 1 read-write HSI48RDYIE HSI48 ready interrupt enable 14 1 read-write LSIRDYC LSI Ready Interrupt Clear 16 1 write-only LSERDYC LSE Ready Interrupt Clear 17 1 write-only HSIRDYC HSI Ready Interrupt Clear 18 1 write-only HSERDYC HSE Ready Interrupt Clear 19 1 write-only PLLRDYC PLL Ready Interrupt Clear 20 1 write-only HSI14RDYC HSI 14 MHz Ready Interrupt Clear 21 1 write-only HSI48RDYC HSI48 Ready Interrupt Clear 22 1 write-only CSSC Clock security system interrupt clear 23 1 write-only APB2RSTR APB2RSTR APB2 peripheral reset register (RCC_APB2RSTR) 0xC 0x20 read-write 0x00000000 SYSCFGRST SYSCFG and COMP reset 0 1 ADCRST ADC interface reset 9 1 TIM1RST TIM1 timer reset 11 1 SPI1RST SPI 1 reset 12 1 USART1RST USART1 reset 14 1 TIM15RST TIM15 timer reset 16 1 TIM16RST TIM16 timer reset 17 1 TIM17RST TIM17 timer reset 18 1 DBGMCURST Debug MCU reset 22 1 APB1RSTR APB1RSTR APB1 peripheral reset register (RCC_APB1RSTR) 0x10 0x20 read-write 0x00000000 TIM3RST Timer 3 reset 1 1 TIM6RST Timer 6 reset 4 1 TIM7RST TIM7 timer reset 5 1 TIM14RST Timer 14 reset 8 1 WWDGRST Window watchdog reset 11 1 SPI2RST SPI2 reset 14 1 USART2RST USART 2 reset 17 1 USART3RST USART3 reset 18 1 USART4RST USART4 reset 19 1 USART5RST USART5 reset 20 1 I2C1RST I2C1 reset 21 1 I2C2RST I2C2 reset 22 1 USBRST USB interface reset 23 1 PWRRST Power interface reset 28 1 AHBENR AHBENR AHB Peripheral Clock enable register (RCC_AHBENR) 0x14 0x20 read-write 0x00000014 DMA1EN DMA1 clock enable 0 1 SRAMEN SRAM interface clock enable 2 1 FLITFEN FLITF clock enable 4 1 CRCEN CRC clock enable 6 1 IOPAEN I/O port A clock enable 17 1 IOPBEN I/O port B clock enable 18 1 IOPCEN I/O port C clock enable 19 1 IOPFEN I/O port F clock enable 22 1 APB2ENR APB2ENR APB2 peripheral clock enable register (RCC_APB2ENR) 0x18 0x20 read-write 0x00000000 SYSCFGEN SYSCFG clock enable 0 1 ADCEN ADC 1 interface clock enable 9 1 TIM1EN TIM1 Timer clock enable 11 1 SPI1EN SPI 1 clock enable 12 1 USART1EN USART1 clock enable 14 1 TIM15EN TIM15 timer clock enable 16 1 TIM16EN TIM16 timer clock enable 17 1 TIM17EN TIM17 timer clock enable 18 1 DBGMCUEN MCU debug module clock enable 22 1 APB1ENR APB1ENR APB1 peripheral clock enable register (RCC_APB1ENR) 0x1C 0x20 read-write 0x00000000 TIM3EN Timer 3 clock enable 1 1 TIM6EN Timer 6 clock enable 4 1 TIM7EN TIM7 timer clock enable 5 1 TIM14EN Timer 14 clock enable 8 1 WWDGEN Window watchdog clock enable 11 1 SPI2EN SPI 2 clock enable 14 1 USART2EN USART 2 clock enable 17 1 USART3EN USART3 clock enable 18 1 USART4EN USART4 clock enable 19 1 USART5EN USART5 clock enable 20 1 I2C1EN I2C 1 clock enable 21 1 I2C2EN I2C 2 clock enable 22 1 USBRST USB interface clock enable 23 1 PWREN Power interface clock enable 28 1 BDCR BDCR Backup domain control register (RCC_BDCR) 0x20 0x20 0x00000000 LSEON External Low Speed oscillator enable 0 1 read-write LSERDY External Low Speed oscillator ready 1 1 read-only LSEBYP External Low Speed oscillator bypass 2 1 read-write LSEDRV LSE oscillator drive capability 3 2 read-write RTCSEL RTC clock source selection 8 2 read-write RTCEN RTC clock enable 15 1 read-write BDRST Backup domain software reset 16 1 read-write CSR CSR Control/status register (RCC_CSR) 0x24 0x20 0x0C000000 LSION Internal low speed oscillator enable 0 1 read-write LSIRDY Internal low speed oscillator ready 1 1 read-only RMVF Remove reset flag 24 1 read-write OBLRSTF Option byte loader reset flag 25 1 read-write PINRSTF PIN reset flag 26 1 read-write PORRSTF POR/PDR reset flag 27 1 read-write SFTRSTF Software reset flag 28 1 read-write IWDGRSTF Independent watchdog reset flag 29 1 read-write WWDGRSTF Window watchdog reset flag 30 1 read-write LPWRRSTF Low-power reset flag 31 1 read-write AHBRSTR AHBRSTR AHB peripheral reset register 0x28 0x20 read-write 0x00000000 IOPARST I/O port A reset 17 1 IOPBRST I/O port B reset 18 1 IOPCRST I/O port C reset 19 1 IOPDRST I/O port D reset 20 1 IOPFRST I/O port F reset 22 1 CFGR2 CFGR2 Clock configuration register 2 0x2C 0x20 read-write 0x00000000 PREDIV PREDIV division factor 0 4 CFGR3 CFGR3 Clock configuration register 3 0x30 0x20 read-write 0x00000000 USART1SW USART1 clock source selection 0 2 I2C1SW I2C1 clock source selection 4 1 CECSW HDMI CEC clock source selection 6 1 USBSW USB clock source selection 7 1 ADCSW ADC clock source selection 8 1 USART2SW USART2 clock source selection 16 2 CR2 CR2 Clock control register 2 0x34 0x20 0x00000080 HSI14ON HSI14 clock enable 0 1 read-write HSI14RDY HR14 clock ready flag 1 1 read-only HSI14DIS HSI14 clock request from ADC disable 2 1 read-write HSI14TRIM HSI14 clock trimming 3 5 read-write HSI14CAL HSI14 clock calibration 8 8 read-only HSI48ON HSI48 clock enable 16 1 read-write HSI48RDY HSI48 clock ready flag 17 1 read-only HSI48CAL HSI48 factory clock calibration 24 1 read-only SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x400 registers CFGR1 CFGR1 configuration register 1 0x0 0x20 read-write 0x00000000 MEM_MODE Memory mapping selection bits 0 2 ADC_DMA_RMP ADC DMA remapping bit 8 1 USART1_TX_DMA_RMP USART1_TX DMA remapping bit 9 1 USART1_RX_DMA_RMP USART1_RX DMA request remapping bit 10 1 TIM16_DMA_RMP TIM16 DMA request remapping bit 11 1 TIM17_DMA_RMP TIM17 DMA request remapping bit 12 1 I2C_PB6_FM Fast Mode Plus (FM plus) driving capability activation bits. 16 1 I2C_PB7_FM Fast Mode Plus (FM+) driving capability activation bits. 17 1 I2C_PB8_FM Fast Mode Plus (FM+) driving capability activation bits. 18 1 I2C_PB9_FM Fast Mode Plus (FM+) driving capability activation bits. 19 1 I2C1_FM_plus FM+ driving capability activation for I2C1 20 1 I2C2_FM_plus FM+ driving capability activation for I2C2 21 1 SPI2_DMA_RMP SPI2 DMA request remapping bit 24 1 USART2_DMA_RMP USART2 DMA request remapping bit 25 1 USART3_DMA_RMP USART3 DMA request remapping bit 26 1 I2C1_DMA_RMP I2C1 DMA request remapping bit 27 1 TIM1_DMA_RMP TIM1 DMA request remapping bit 28 1 TIM2_DMA_RMP TIM2 DMA request remapping bit 29 1 TIM3_DMA_RMP TIM3 DMA request remapping bit 30 1 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x0000 EXTI3 EXTI 3 configuration bits 12 4 EXTI2 EXTI 2 configuration bits 8 4 EXTI1 EXTI 1 configuration bits 4 4 EXTI0 EXTI 0 configuration bits 0 4 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x0000 EXTI7 EXTI 7 configuration bits 12 4 EXTI6 EXTI 6 configuration bits 8 4 EXTI5 EXTI 5 configuration bits 4 4 EXTI4 EXTI 4 configuration bits 0 4 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x0000 EXTI11 EXTI 11 configuration bits 12 4 EXTI10 EXTI 10 configuration bits 8 4 EXTI9 EXTI 9 configuration bits 4 4 EXTI8 EXTI 8 configuration bits 0 4 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x0000 EXTI15 EXTI 15 configuration bits 12 4 EXTI14 EXTI 14 configuration bits 8 4 EXTI13 EXTI 13 configuration bits 4 4 EXTI12 EXTI 12 configuration bits 0 4 CFGR2 CFGR2 configuration register 2 0x18 0x20 read-write 0x0000 SRAM_PEF SRAM parity flag 8 1 PVD_LOCK PVD lock enable bit 2 1 SRAM_PARITY_LOCK SRAM parity lock bit 1 1 LOCUP_LOCK Cortex-M0 LOCKUP bit enable bit 0 1 ADC Analog-to-digital converter ADC 0x40012400 0x0 0x400 registers ADC ADC interrupt 12 ISR ISR interrupt and status register 0x0 0x20 read-write 0x00000000 AWD Analog watchdog flag 7 1 OVR ADC overrun 4 1 EOS End of sequence flag 3 1 EOC End of conversion flag 2 1 EOSMP End of sampling flag 1 1 ADRDY ADC ready 0 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 AWDIE Analog watchdog interrupt enable 7 1 OVRIE Overrun interrupt enable 4 1 EOSIE End of conversion sequence interrupt enable 3 1 EOCIE End of conversion interrupt enable 2 1 EOSMPIE End of sampling flag interrupt enable 1 1 ADRDYIE ADC ready interrupt enable 0 1 CR CR control register 0x8 0x20 read-write 0x00000000 ADCAL ADC calibration 31 1 ADSTP ADC stop conversion command 4 1 ADSTART ADC start conversion command 2 1 ADDIS ADC disable command 1 1 ADEN ADC enable command 0 1 CFGR1 CFGR1 configuration register 1 0xC 0x20 read-write 0x00000000 AWDCH Analog watchdog channel selection 26 5 AWDEN Analog watchdog enable 23 1 AWDSGL Enable the watchdog on a single channel or on all channels 22 1 DISCEN Discontinuous mode 16 1 AUTOFF Auto-off mode 15 1 AUTDLY Auto-delayed conversion mode 14 1 CONT Single / continuous conversion mode 13 1 OVRMOD Overrun management mode 12 1 EXTEN External trigger enable and polarity selection 10 2 EXTSEL External trigger selection 6 3 ALIGN Data alignment 5 1 RES Data resolution 3 2 SCANDIR Scan sequence direction 2 1 DMACFG Direct memery access configuration 1 1 DMAEN Direct memory access enable 0 1 CFGR2 CFGR2 configuration register 2 0x10 0x20 read-write 0x00008000 JITOFF_D4 JITOFF_D4 31 1 JITOFF_D2 JITOFF_D2 30 1 SMPR SMPR sampling time register 0x14 0x20 read-write 0x00000000 SMPR Sampling time selection 0 3 TR TR watchdog threshold register 0x20 0x20 read-write 0x00000FFF HT Analog watchdog higher threshold 16 12 LT Analog watchdog lower threshold 0 12 CHSELR CHSELR channel selection register 0x28 0x20 read-write 0x00000000 CHSEL18 Channel-x selection 18 1 CHSEL17 Channel-x selection 17 1 CHSEL16 Channel-x selection 16 1 CHSEL15 Channel-x selection 15 1 CHSEL14 Channel-x selection 14 1 CHSEL13 Channel-x selection 13 1 CHSEL12 Channel-x selection 12 1 CHSEL11 Channel-x selection 11 1 CHSEL10 Channel-x selection 10 1 CHSEL9 Channel-x selection 9 1 CHSEL8 Channel-x selection 8 1 CHSEL7 Channel-x selection 7 1 CHSEL6 Channel-x selection 6 1 CHSEL5 Channel-x selection 5 1 CHSEL4 Channel-x selection 4 1 CHSEL3 Channel-x selection 3 1 CHSEL2 Channel-x selection 2 1 CHSEL1 Channel-x selection 1 1 CHSEL0 Channel-x selection 0 1 DR DR data register 0x40 0x20 read-only 0x00000000 DATA Converted data 0 16 CCR CCR common configuration register 0x308 0x20 read-write 0x00000000 VBATEN VBAT enable 24 1 TSEN Temperature sensor enable 23 1 VREFEN Temperature sensor and VREFINT enable 22 1 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 27 CR1 CR1 Control register 1 0x0 0x20 read-write 0x0000 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 RE Receiver enable 2 1 TE Transmitter enable 3 1 IDLEIE IDLE interrupt enable 4 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TXEIE interrupt enable 7 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 PCE Parity control enable 10 1 WAKE Receiver wakeup method 11 1 M Word length 12 1 MME Mute mode enable 13 1 CMIE Character match interrupt enable 14 1 OVER8 Oversampling mode 15 1 DEDT Driver Enable deassertion time 16 5 DEAT Driver Enable assertion time 21 5 RTOIE Receiver timeout interrupt enable 26 1 EOBIE End of Block interrupt enable 27 1 M1 Word length 28 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 ADD4 Address of the USART node 28 4 ADD0 Address of the USART node 24 4 RTOEN Receiver timeout enable 23 1 ABRMOD Auto baud rate mode 21 2 ABREN Auto baud rate enable 20 1 MSBFIRST Most significant bit first 19 1 DATAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x0000 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 SCARCNT Smartcard auto-retry count 17 3 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 ONEBIT One sample bit method enable 11 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 SCEN Smartcard mode enable 5 1 NACK Smartcard NACK enable 4 1 HDSEL Half-duplex selection 3 1 IRLP IrDA low-power 2 1 IREN IrDA mode enable 1 1 EIE Error interrupt enable 0 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x0000 DIV_Mantissa mantissa of USARTDIV 4 12 DIV_Fraction fraction of USARTDIV 0 4 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x0000 GT Guard time value 8 8 PSC Prescaler value 0 8 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x0000 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 RQR RQR Request register 0x18 0x20 read-write 0x0000 TXFRQ Transmit data flush request 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ABRRQ Auto baud rate request 0 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x00C0 REACK Receive enable acknowledge flag 22 1 TEACK Transmit enable acknowledge flag 21 1 WUF Wakeup from Stop mode flag 20 1 RWU Receiver wakeup from Mute mode 19 1 SBKF Send break flag 18 1 CMF character match flag 17 1 BUSY Busy flag 16 1 ABRF Auto baud rate flag 15 1 ABRE Auto baud rate error 14 1 EOBF End of block flag 12 1 RTOF Receiver timeout 11 1 CTS CTS flag 10 1 CTSIF CTS interrupt flag 9 1 LBDF LIN break detection flag 8 1 TXE Transmit data register empty 7 1 TC Transmission complete 6 1 RXNE Read data register not empty 5 1 IDLE Idle line detected 4 1 ORE Overrun error 3 1 NF Noise detected flag 2 1 FE Framing error 1 1 PE Parity error 0 1 ICR ICR Interrupt flag clear register 0x20 0x20 read-write 0x0000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 EOBCF End of timeout clear flag 12 1 RTOCF Receiver timeout clear flag 11 1 CTSCF CTS clear flag 9 1 LBDCF LIN break detection clear flag 8 1 TCCF Transmission complete clear flag 6 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 0x20 read-only 0x0000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x0000 TDR Transmit data value 0 9 USART2 0x40004400 USART2 USART2 global interrupt 28 USART3 0x40004800 USART3_4_5_6 USART3, USART4, USART5, USART6 global interrupt 29 USART4 0x40004C00 USART6 0x40011400 USART5 0x40005000 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC RTC interrupts 2 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 YU Year units in BCD format 16 4 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 CR CR control register 0x8 0x20 0x00000000 TSEDGE Time-stamp event active edge 3 1 read-write REFCKON RTC_REFIN reference clock detection enable (50 or 60 Hz) 4 1 read-write BYPSHAD Bypass the shadow registers 5 1 read-write FMT Hour format 6 1 read-write ALRAE Alarm A enable 8 1 read-write TSE timestamp enable 11 1 read-write ALRAIE Alarm A interrupt enable 12 1 read-write TSIE Time-stamp interrupt enable 15 1 read-write ADD1H Add 1 hour (summer time change) 16 1 write-only SUB1H Subtract 1 hour (winter time change) 17 1 write-only BKP Backup 18 1 read-write COSEL Calibration output selection 19 1 read-write POL Output polarity 20 1 read-write OSEL Output selection 21 2 read-write COE Calibration output enable 23 1 read-write ISR ISR initialization and status register 0xC 0x20 0x00000007 ALRAWF Alarm A write flag 0 1 read-only SHPF Shift operation pending 3 1 read-write INITS Initialization status flag 4 1 read-only RSF Registers synchronization flag 5 1 read-write INITF Initialization flag 6 1 read-only INIT Initialization mode 7 1 read-write ALRAF Alarm A flag 8 1 read-write TSF Time-stamp flag 11 1 read-write TSOVF Time-stamp overflow flag 12 1 read-write TAMP1F RTC_TAMP1 detection flag 13 1 read-write TAMP2F RTC_TAMP2 detection flag 14 1 read-write RECALPF Recalibration pending Flag 16 1 read-only PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 PREDIV_S Synchronous prescaler factor 0 15 ALRMAR ALRMAR alarm A register 0x1C 0x20 read-write 0x00000000 MSK4 Alarm A date mask 31 1 WDSEL Week day selection 30 1 DT Date tens in BCD format. 28 2 DU Date units or day in BCD format. 24 4 MSK3 Alarm A hours mask 23 1 PM AM/PM notation 22 1 HT Hour tens in BCD format. 20 2 HU Hour units in BCD format. 16 4 MSK2 Alarm A minutes mask 15 1 MNT Minute tens in BCD format. 12 3 MNU Minute units in BCD format. 8 4 MSK1 Alarm A seconds mask 7 1 ST Second tens in BCD format. 4 3 SU Second units in BCD format. 0 4 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 SSR SSR sub second register 0x28 0x20 read-only 0x00000000 SS Sub second value 0 16 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 SUBFS Subtract a fraction of a second 0 15 TSTR TSTR timestamp time register 0x30 0x20 read-only 0x00000000 PM AM/PM notation 22 1 HT Hour tens in BCD format. 20 2 HU Hour units in BCD format. 16 4 MNT Minute tens in BCD format. 12 3 MNU Minute units in BCD format. 8 4 ST Second tens in BCD format. 4 3 SU Second units in BCD format. 0 4 TSDR TSDR timestamp date register 0x34 0x20 read-only 0x00000000 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 TSSSR TSSSR time-stamp sub second register 0x38 0x20 read-only 0x00000000 SS Sub second value 0 16 CALR CALR calibration register 0x3C 0x20 read-write 0x00000000 CALP Use an 8-second calibration cycle period 15 1 CALW8 Use a 16-second calibration cycle period 14 1 CALW16 Use a 16-second calibration cycle period 13 1 CALM Calibration minus 0 9 TAFCR TAFCR tamper and alternate function configuration register 0x40 0x20 read-write 0x00000000 PC15MODE PC15 mode 23 1 PC15VALUE PC15 value 22 1 PC14MODE PC14 mode 21 1 PC14VALUE PC14 value 20 1 PC13MODE PC13 mode 19 1 PC13VALUE RTC_ALARM output type/PC13 value 18 1 TAMP_PUDIS RTC_TAMPx pull-up disable 15 1 TAMP_PRCH RTC_TAMPx precharge duration 13 2 TAMPFLT RTC_TAMPx filter count 11 2 TAMPFREQ Tamper sampling frequency 8 3 TAMPTS Activate timestamp on tamper detection event 7 1 TAMP2_TRG Active level for RTC_TAMP2 input 4 1 TAMP2E RTC_TAMP2 input detection enable 3 1 TAMPIE Tamper interrupt enable 2 1 TAMP1TRG Active level for RTC_TAMP1 input 1 1 TAMP1E RTC_TAMP1 input detection enable 0 1 ALRMASSR ALRMASSR alarm A sub second register 0x44 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 BKP0R BKP0R backup register 0x50 0x20 read-write 0x00000000 BKP BKP 0 32 BKP1R BKP1R backup register 0x54 0x20 read-write 0x00000000 BKP BKP 0 32 BKP2R BKP2R backup register 0x58 0x20 read-write 0x00000000 BKP BKP 0 32 BKP3R BKP3R backup register 0x5C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP4R BKP4R backup register 0x60 0x20 read-write 0x00000000 BKP BKP 0 32 TIM15 General-purpose-timers TIM 0x40014000 0x0 0x400 registers TIM15 TIM15 global interrupt 20 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 TIE Trigger interrupt enable 6 1 COMIE COM interrupt enable 5 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 TIM16 General-purpose-timers TIM 0x40014400 0x0 0x400 registers TIM16 TIM16 global interrupt 21 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 TIE Trigger interrupt enable 6 1 COMIE COM interrupt enable 5 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 TIM17 0x40014800 TIM17 TIM17 global interrupt 22 Flash Flash Flash 0x40022000 0x0 0x400 registers FLASH Flash global interrupt 3 ACR ACR Flash access control register 0x0 0x20 0x00000030 LATENCY LATENCY 0 3 read-write PRFTBE PRFTBE 4 1 read-write PRFTBS PRFTBS 5 1 read-only KEYR KEYR Flash key register 0x4 0x20 write-only 0x00000000 FKEYR Flash Key 0 32 OPTKEYR OPTKEYR Flash option key register 0x8 0x20 write-only 0x00000000 OPTKEYR Option byte key 0 32 SR SR Flash status register 0xC 0x20 0x00000000 EOP End of operation 5 1 read-write WRPRT Write protection error 4 1 read-write PGERR Programming error 2 1 read-write BSY Busy 0 1 read-only CR CR Flash control register 0x10 0x20 read-write 0x00000080 FORCE_OPTLOAD Force option byte loading 13 1 EOPIE End of operation interrupt enable 12 1 ERRIE Error interrupt enable 10 1 OPTWRE Option bytes write enable 9 1 LOCK Lock 7 1 STRT Start 6 1 OPTER Option byte erase 5 1 OPTPG Option byte programming 4 1 MER Mass erase 2 1 PER Page erase 1 1 PG Programming 0 1 AR AR Flash address register 0x14 0x20 write-only 0x00000000 FAR Flash address 0 32 OBR OBR Option byte register 0x1C 0x20 read-only 0x03FFFFF2 OPTERR Option byte error 0 1 RDPRT Read protection level status 1 2 WDG_SW WDG_SW 8 1 nRST_STOP nRST_STOP 9 1 nRST_STDBY nRST_STDBY 10 1 nBOOT1 BOOT1 12 1 VDDA_MONITOR VDDA_MONITOR 13 1 RAM_PARITY_CHECK_ RAM_PARITY_CHECK 14 1 Data0 Data0 16 8 Data1 Data1 24 8 WRPR WRPR Write protection register 0x20 0x20 read-only 0xFFFFFFFF WRP Write protect 0 32 DBGMCU Debug support DBGMCU 0x40015800 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 0x20 read-only 0x0 DEV_ID Device Identifier 0 12 DIV_ID Division Identifier 12 4 REV_ID Revision Identifier 16 16 CR CR Debug MCU Configuration Register 0x4 0x20 read-write 0x0 DBG_STOP Debug Stop Mode 1 1 DBG_STANDBY Debug Standby Mode 2 1 APB1_FZ APB1_FZ Debug MCU APB1 freeze register 0x8 0x20 read-write 0x0 DBG_TIM3_STOP TIM3 counter stopped when core is halted 1 1 DBG_TIM6_STOP TIM6 counter stopped when core is halted 4 1 DBG_TIM7_STOP TIM7 counter stopped when core is halted 5 1 DBG_TIM14_STOP TIM14 counter stopped when core is halted 8 1 DBG_WWDG_STOP Debug window watchdog stopped when core is halted 11 1 DBG_IWDG_STOP Debug independent watchdog stopped when core is halted 12 1 DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted 21 1 APB2_FZ APB2_FZ Debug MCU APB2 freeze register 0xC 0x20 read-write 0x0 DBG_TIM1_STOP TIM1 counter stopped when core is halted 11 1 DBG_TIM15_STOP TIM15 counter stopped when core is halted 16 1 DBG_TIM16_STOP TIM16 counter stopped when core is halted 17 1 DBG_TIM17_STOP TIM17 counter stopped when core is halted 18 1 USB Universal serial bus full-speed device interface USB 0x40005C00 0x0 0x400 registers USB USB global interrupt 31 EP0R EP0R endpoint 0 register 0x0 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP1R EP1R endpoint 1 register 0x4 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP2R EP2R endpoint 2 register 0x8 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP3R EP3R endpoint 3 register 0xC 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP4R EP4R endpoint 4 register 0x10 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP5R EP5R endpoint 5 register 0x14 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP6R EP6R endpoint 6 register 0x18 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP7R EP7R endpoint 7 register 0x1C 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 CNTR CNTR control register 0x40 0x20 read-write 0x00000003 FRES Force USB Reset 0 1 PDWN Power down 1 1 LPMODE Low-power mode 2 1 FSUSP Force suspend 3 1 RESUME Resume request 4 1 L1RESUME LPM L1 Resume request 5 1 L1REQM LPM L1 state request interrupt mask 7 1 ESOFM Expected start of frame interrupt mask 8 1 SOFM Start of frame interrupt mask 9 1 RESETM USB reset interrupt mask 10 1 SUSPM Suspend mode interrupt mask 11 1 WKUPM Wakeup interrupt mask 12 1 ERRM Error interrupt mask 13 1 PMAOVRM Packet memory area over / underrun interrupt mask 14 1 CTRM Correct transfer interrupt mask 15 1 ISTR ISTR interrupt status register 0x44 0x20 0x00000000 EP_ID Endpoint Identifier 0 4 read-only DIR Direction of transaction 4 1 read-only L1REQ LPM L1 state request 7 1 read-write ESOF Expected start frame 8 1 read-write SOF start of frame 9 1 read-write RESET reset request 10 1 read-write SUSP Suspend mode request 11 1 read-write WKUP Wakeup 12 1 read-write ERR Error 13 1 read-write PMAOVR Packet memory area over / underrun 14 1 read-write CTR Correct transfer 15 1 read-only FNR FNR frame number register 0x48 0x20 read-only 0x0000 FN Frame number 0 11 LSOF Lost SOF 11 2 LCK Locked 13 1 RXDM Receive data - line status 14 1 RXDP Receive data + line status 15 1 DADDR DADDR device address 0x4C 0x20 read-write 0x0000 ADD Device address 0 7 EF Enable function 7 1 BTABLE BTABLE Buffer table address 0x50 0x20 read-write 0x0000 BTABLE Buffer table 3 13 LPMCSR LPMCSR LPM control and status register 0x54 0x20 0x0000 LPMEN LPM support enable 0 1 read-write LPMACK LPM Token acknowledge enable 1 1 read-write REMWAKE bRemoteWake value 3 1 read-only BESL BESL value 4 4 read-only BCDR BCDR Battery charging detector 0x58 0x20 0x0000 BCDEN Battery charging detector (BCD) enable 0 1 read-write DCDEN Data contact detection (DCD) mode enable 1 1 read-write PDEN Primary detection (PD) mode enable 2 1 read-write SDEN Secondary detection (SD) mode enable 3 1 read-write DCDET Data contact detection (DCD) status 4 1 read-only PDET Primary detection (PD) status 5 1 read-only SDET Secondary detection (SD) status 6 1 read-only PS2DET DM pull-up detection status 7 1 read-only DPPU DP pull-up control 15 1 read-write SCB System control block SCB 0xE000ED00 0x0 0x41 registers CPUID CPUID CPUID base register 0x0 0x20 read-only 0x410FC241 Revision Revision number 0 4 PartNo Part number of the processor 4 12 Constant Reads as 0xF 16 4 Variant Variant number 20 4 Implementer Implementer code 24 8 ICSR ICSR Interrupt control and state register 0x4 0x20 read-write 0x00000000 VECTACTIVE Active vector 0 6 VECTPENDING Pending vector 12 6 ISRPENDING Interrupt pending flag 22 1 PENDSTCLR SysTick exception clear-pending bit 25 1 PENDSTSET SysTick exception set-pending bit 26 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVSET PendSV set-pending bit 28 1 NMIPENDSET NMI set-pending bit. 31 1 AIRCR AIRCR Application interrupt and reset control register 0xC 0x20 read-write 0x00000000 VECTCLRACTIVE VECTCLRACTIVE 1 1 SYSRESETREQ SYSRESETREQ 2 1 ENDIANESS ENDIANESS 15 1 VECTKEYSTAT Register key 16 16 SCR SCR System control register 0x10 0x20 read-write 0x00000000 SLEEPONEXIT SLEEPONEXIT 1 1 SLEEPDEEP SLEEPDEEP 2 1 SEVEONPEND Send Event on Pending bit 4 1 CCR CCR Configuration and control register 0x14 0x20 read-write 0x00000000 UNALIGN__TRP UNALIGN_ TRP 3 1 STKALIGN STKALIGN 9 1 SHPR2 SHPR2 System handler priority registers 0x1C 0x20 read-write 0x00000000 PRI_11 Priority of system handler 11 24 8 SHPR3 SHPR3 System handler priority registers 0x20 0x20 read-write 0x00000000 PRI_14 Priority of system handler 14 16 8 PRI_15 Priority of system handler 15 24 8 STK SysTick timer STK 0xE000E010 0x0 0x11 registers CSR CSR SysTick control and status register 0x0 0x20 read-write 0X00000000 ENABLE Counter enable 0 1 TICKINT SysTick exception request enable 1 1 CLKSOURCE Clock source selection 2 1 COUNTFLAG COUNTFLAG 16 1 RVR RVR SysTick reload value register 0x4 0x20 read-write 0X00000000 RELOAD RELOAD value 0 24 CVR CVR SysTick current value register 0x8 0x20 read-write 0X00000000 CURRENT Current counter value 0 24 CALIB CALIB SysTick calibration value register 0xC 0x20 read-write 0X00000000 TENMS Calibration value 0 24 SKEW SKEW flag: Indicates whether the TENMS value is exact 30 1 NOREF NOREF flag. Reads as zero 31 1