--- STM32F103xx.svd.raw 2018-01-27 16:49:54.160000001 +0100 +++ STM32F103xx.svd 2018-01-27 16:52:09.116666668 +0100 @@ -3,6 +3,16 @@ xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> STM32F103xx + + CM3 + r1p1 + little + false + false + true + 4 + false + 1.3 STM32F103xx @@ -1645,6 +1655,18 @@ 16 1 read-write + + + Disabled + HSE disabled + 0 + + + Enabled + HSE enabled + 1 + + HSERDY @@ -1653,6 +1675,18 @@ 17 1 read-only + + + Notready + HSE Not Ready + 0 + + + Ready + HSE Ready + 1 + + HSEBYP @@ -1661,6 +1695,18 @@ 18 1 read-write + + + Disabled + external 4-16 MHz oscillator not bypassed + 0 + + + Enabled + external 4-16 MHz oscillator bypassed with external clock + 1 + + CSSON @@ -1676,6 +1722,18 @@ 24 1 read-write + + + Disabled + PLL disabled + 0 + + + Enabled + Pll enabled + 1 + + PLLRDY @@ -1683,6 +1741,18 @@ 25 1 read-only + + + Unlocked + PLL Unlocked + 0 + + + Locked + PLL Locked + 1 + + @@ -1701,6 +1771,23 @@ 0 2 read-write + + + Hsi + HSI selected as system clock + 0 + + + Hse + HSE selected as system clock + 1 + + + Pll + PLL selected as system clock + 2 + + SWS @@ -1708,6 +1795,23 @@ 2 2 read-only + + + Hsi + HSI selected as system clock + 0 + + + Hse + HSE selected as system clock + 1 + + + Pll + PLL selected as system clock + 2 + + HPRE @@ -1715,6 +1819,53 @@ 4 4 read-write + + + NoDiv + SYSCLK not divided + 0 + + + Div2 + SYSCLK divided by 2 + 8 + + + Div4 + SYSCLK divided by 4 + 9 + + + Div8 + SYSCLK divided by 8 + 10 + + + Div16 + SYSCLK divided by 16 + 11 + + + Div64 + SYSCLK divided by 64 + 12 + + + Div128 + SYSCLK divided by 128 + 13 + + + Div256 + SYSCLK divided by 256 + 14 + + + Div512 + SYSCLK divided by 512 + 15 + + PPRE1 @@ -1723,6 +1874,33 @@ 8 3 read-write + + + NoDiv + HCLK not divided + 0 + + + Div2 + HCLK divided by 2 + 4 + + + Div4 + HCLK divided by 4 + 5 + + + Div8 + HCLK divided by 8 + 6 + + + Div16 + HCLK divided by 16 + 7 + + PPRE2 @@ -1731,6 +1909,33 @@ 11 3 read-write + + + NoDiv + HCLK not divided + 0 + + + Div2 + HCLK divided by 2 + 4 + + + Div4 + HCLK divided by 4 + 5 + + + Div8 + HCLK divided by 8 + 6 + + + Div16 + HCLK divided by 16 + 7 + + ADCPRE @@ -1738,6 +1943,28 @@ 14 2 read-write + + + Div2 + PCLK2 divided by 2 + 0 + + + Div4 + PCLK2 divided by 4 + 1 + + + Div6 + PCLK2 divided by 6 + 2 + + + Div8 + PCLK2 divided by 8 + 3 + + PLLSRC @@ -1745,6 +1972,18 @@ 16 1 read-write + + + Internal + HSI oscillator clock / 2 + 0 + + + External + HSE oscillator clock + 1 + + PLLXTPRE @@ -1752,6 +1991,18 @@ 17 1 read-write + + + NoDiv + HSE not divided + 0 + + + Div2 + HSE divided by 2 + 8 + + PLLMUL @@ -1759,13 +2010,102 @@ 18 4 read-write + + + Mul2 + PLL input clock x 2 + 0 + + + Mul3 + PLL input clock x 3 + 1 + + + Mul4 + PLL input clock x 4 + 2 + + + Mul5 + PLL input clock x 5 + 3 + + + Mul6 + PLL input clock x 6 + 4 + + + Mul7 + PLL input clock x 7 + 5 + + + Mul8 + PLL input clock x 8 + 6 + + + Mul9 + PLL input clock x 9 + 7 + + + Mul10 + PLL input clock x 10 + 8 + + + Mul11 + PLL input clock x 11 + 9 + + + Mul12 + PLL input clock x 12 + 10 + + + Mul13 + PLL input clock x 13 + 11 + + + Mul14 + PLL input clock x 14 + 12 + + + Mul15 + PLL input clock x 15 + 13 + + + Mul16 + PLL input clock x 16 + 14 + + - OTGFSPRE - USB OTG FS prescaler + USBPRE + USB prescaler 22 1 read-write + + + Div15 + PLL clock is divided by 1.5 + 0 + + + NoDiv + PLL clock is not divided + 1 + + MCO @@ -2195,12 +2535,27 @@ DMA1 clock enable 0 1 + + ENABLED + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + DMA2EN DMA2 clock enable 1 1 + + SRAMEN @@ -2208,30 +2563,40 @@ enable 2 1 + + FLITFEN FLITF clock enable 4 1 + + CRCEN CRC clock enable 6 1 + + FSMCEN FSMC clock enable 8 1 + + SDIOEN SDIO clock enable 10 1 + + @@ -2251,48 +2616,64 @@ enable 0 1 + + IOPAEN I/O port A clock enable 2 1 + + IOPBEN I/O port B clock enable 3 1 + + IOPCEN I/O port C clock enable 4 1 + + IOPDEN I/O port D clock enable 5 1 + + IOPEEN I/O port E clock enable 6 1 + + IOPFEN I/O port F clock enable 7 1 + + IOPGEN I/O port G clock enable 8 1 + + ADC1EN @@ -2300,6 +2681,8 @@ enable 9 1 + + ADC2EN @@ -2307,30 +2690,40 @@ enable 10 1 + + TIM1EN TIM1 Timer clock enable 11 1 + + SPI1EN SPI 1 clock enable 12 1 + + TIM8EN TIM8 Timer clock enable 13 1 + + USART1EN USART1 clock enable 14 1 + + ADC3EN @@ -2338,24 +2731,32 @@ enable 15 1 + + TIM9EN TIM9 Timer clock enable 19 1 + + TIM10EN TIM10 Timer clock enable 20 1 + + TIM11EN TIM11 Timer clock enable 21 1 + + @@ -2374,54 +2775,72 @@ Timer 2 clock enable 0 1 + + TIM3EN Timer 3 clock enable 1 1 + + TIM4EN Timer 4 clock enable 2 1 + + TIM5EN Timer 5 clock enable 3 1 + + TIM6EN Timer 6 clock enable 4 1 + + TIM7EN Timer 7 clock enable 5 1 + + TIM12EN Timer 12 clock enable 6 1 + + TIM13EN Timer 13 clock enable 7 1 + + TIM14EN Timer 14 clock enable 8 1 + + WWDGEN @@ -2429,66 +2848,88 @@ enable 11 1 + + SPI2EN SPI 2 clock enable 14 1 + + SPI3EN SPI 3 clock enable 15 1 + + USART2EN USART 2 clock enable 17 1 + + USART3EN USART 3 clock enable 18 1 + + UART4EN UART 4 clock enable 19 1 + + UART5EN UART 5 clock enable 20 1 + + I2C1EN I2C 1 clock enable 21 1 + + I2C2EN I2C 2 clock enable 22 1 + + USBEN USB clock enable 23 1 + + CANEN CAN clock enable 25 1 + + BKPEN @@ -2496,6 +2937,8 @@ enable 27 1 + + PWREN @@ -2503,12 +2946,16 @@ enable 28 1 + + DACEN DAC interface clock enable 29 1 + + @@ -2551,6 +2998,28 @@ 8 2 read-write + + + NoClk + No clock + 0 + + + Lse + LSE oscillator clock used as RTC clock + 1 + + + Lsi + LSI oscillator clock used as RTC clock + 2 + + + Hse + HSE oscillator clock divided by 128 used as RTC clock + 3 + + RTCEN @@ -2558,6 +3027,8 @@ 15 1 read-write + + BDRST @@ -2674,6 +3145,29 @@ Port n.0 mode bits 0 2 + + MODE + + Input + Input mode + 0 + + + Output + Output mode 10 MHz + 1 + + + Output2 + Output mode 2 MHz + 2 + + + Output50 + Output mode 50 MHz + 3 + + CNF0 @@ -2681,12 +3175,37 @@ bits 2 2 + + CONFIG + + Push + Push-Pull mode + 0 + + + Open + Open Drain-Mode + 1 + + + AltPush + Alternate Function Push-Pull Mode + 2 + + + AltOpen + Alternate Function Open-Drain Mode + 3 + + MODE1 Port n.1 mode bits 4 2 + + CNF1 @@ -2694,12 +3213,16 @@ bits 6 2 + + MODE2 Port n.2 mode bits 8 2 + + CNF2 @@ -2707,12 +3230,16 @@ bits 10 2 + + MODE3 Port n.3 mode bits 12 2 + + CNF3 @@ -2720,12 +3247,16 @@ bits 14 2 + + MODE4 Port n.4 mode bits 16 2 + + CNF4 @@ -2733,12 +3264,16 @@ bits 18 2 + + MODE5 Port n.5 mode bits 20 2 + + CNF5 @@ -2746,12 +3281,16 @@ bits 22 2 + + MODE6 Port n.6 mode bits 24 2 + + CNF6 @@ -2759,12 +3298,16 @@ bits 26 2 + + MODE7 Port n.7 mode bits 28 2 + + CNF7 @@ -2772,6 +3315,8 @@ bits 30 2 + + @@ -2790,6 +3335,8 @@ Port n.8 mode bits 0 2 + + CNF8 @@ -2797,12 +3344,16 @@ bits 2 2 + + MODE9 Port n.9 mode bits 4 2 + + CNF9 @@ -2810,12 +3361,16 @@ bits 6 2 + + MODE10 Port n.10 mode bits 8 2 + + CNF10 @@ -2823,12 +3378,16 @@ bits 10 2 + + MODE11 Port n.11 mode bits 12 2 + + CNF11 @@ -2836,12 +3395,16 @@ bits 14 2 + + MODE12 Port n.12 mode bits 16 2 + + CNF12 @@ -2849,12 +3412,16 @@ bits 18 2 + + MODE13 Port n.13 mode bits 20 2 + + CNF13 @@ -2862,12 +3429,16 @@ bits 22 2 + + MODE14 Port n.14 mode bits 24 2 + + CNF14 @@ -2875,12 +3446,16 @@ bits 26 2 + + MODE15 Port n.15 mode bits 28 2 + + CNF15 @@ -2888,6 +3463,8 @@ bits 30 2 + + @@ -3122,192 +3699,270 @@ Set bit 0 0 1 + + SET + write + + Set + Sets the corresponding ODRx bit + 1 + + BS1 Set bit 1 1 1 + + BS2 Set bit 1 2 1 + + BS3 Set bit 3 3 1 + + BS4 Set bit 4 4 1 + + BS5 Set bit 5 5 1 + + BS6 Set bit 6 6 1 + + BS7 Set bit 7 7 1 + + BS8 Set bit 8 8 1 + + BS9 Set bit 9 9 1 + + BS10 Set bit 10 10 1 + + BS11 Set bit 11 11 1 + + BS12 Set bit 12 12 1 + + BS13 Set bit 13 13 1 + + BS14 Set bit 14 14 1 + + BS15 Set bit 15 15 1 + + BR0 Reset bit 0 16 1 + + RESET + write + + Reset + Resets the corresponding ODRx bit + 1 + + BR1 Reset bit 1 17 1 + + BR2 Reset bit 2 18 1 + + BR3 Reset bit 3 19 1 + + BR4 Reset bit 4 20 1 + + BR5 Reset bit 5 21 1 + + BR6 Reset bit 6 22 1 + + BR7 Reset bit 7 23 1 + + BR8 Reset bit 8 24 1 + + BR9 Reset bit 9 25 1 + + BR10 Reset bit 10 26 1 + + BR11 Reset bit 11 27 1 + + BR12 Reset bit 12 28 1 + + BR13 Reset bit 13 29 1 + + BR14 Reset bit 14 30 1 + + BR15 Reset bit 15 31 1 + + @@ -5272,6 +5927,8 @@ Channel enable 0 1 + + TCIE @@ -5323,18 +5980,61 @@ Peripheral size 8 2 + + PSIZE + + Bit8 + 8-bits + 0 + + + Bit16 + 16-bits + 1 + + + Bit32 + 32-bits + 2 + + MSIZE Memory size 10 2 + + PL Channel Priority level 12 2 + + PL + + Low + Low + 0 + + + Medium + Medium + 1 + + + High + High + 2 + + + VeryHigh + Very High + 3 + + MEM2MEM @@ -5413,6 +6113,8 @@ Channel enable 0 1 + + TCIE @@ -5464,18 +6166,24 @@ Peripheral size 8 2 + + MSIZE Memory size 10 2 + + PL Channel Priority level 12 2 + + MEM2MEM @@ -5554,6 +6262,8 @@ Channel enable 0 1 + + TCIE @@ -5605,18 +6315,24 @@ Peripheral size 8 2 + + MSIZE Memory size 10 2 + + PL Channel Priority level 12 2 + + MEM2MEM @@ -5695,6 +6411,8 @@ Channel enable 0 1 + + TCIE @@ -5746,18 +6464,24 @@ Peripheral size 8 2 + + MSIZE Memory size 10 2 + + PL Channel Priority level 12 2 + + MEM2MEM @@ -5836,6 +6560,8 @@ Channel enable 0 1 + + TCIE @@ -5887,18 +6613,24 @@ Peripheral size 8 2 + + MSIZE Memory size 10 2 + + PL Channel Priority level 12 2 + + MEM2MEM @@ -5977,6 +6709,8 @@ Channel enable 0 1 + + TCIE @@ -6028,18 +6762,24 @@ Peripheral size 8 2 + + MSIZE Memory size 10 2 + + PL Channel Priority level 12 2 + + MEM2MEM @@ -6118,6 +6858,8 @@ Channel enable 0 1 + + TCIE @@ -6169,18 +6911,24 @@ Peripheral size 8 2 + + MSIZE Memory size 10 2 + + PL Channel Priority level 12 2 + + MEM2MEM @@ -8400,9 +9148,27 @@ CKD - Clock division + Division ratio between the timer clock (CK_INT) frequency and sampling clock 8 2 + + CKD + + NoDiv + Clock is not divided + 0 + + + Div2 + Clock is divided by 2 + 1 + + + Div4 + Clock is divided by 4 + 2 + + ARPE @@ -8422,12 +9188,38 @@ Direction 4 1 + + DIR + + Up + Up + 0 + + + Down + Down + 1 + + OPM One-pulse mode 3 1 + + OPM + + Continuous + Counter is not stopped at update event + 0 + + + OnePulse + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + URS @@ -8446,6 +9238,19 @@ Counter enable 0 1 + + CEN + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + @@ -8579,12 +9384,98 @@ Trigger selection 4 3 + + TS + + ITR0 + Internal Trigger 0 (ITR0) + 0 + + + ITR1 + Internal Trigger 1 (ITR1) + 1 + + + ITR2 + Internal Trigger 2 (ITR2) + 2 + + + ITR3 + Internal Trigger 3 (ITR3) + 3 + + + TI1F_ED + TI1 Edge Detector + 4 + + + TI1FP1 + Filtered Timer Input 1 + 5 + + + TI2FP2 + Filtered Timer Input 2 + 6 + + + (ETRF) + External Trigger input + 7 + + SMS Slave mode selection 0 3 + + SMS + + Disabled + Counter disabled + 0 + + + EncoderTI2 + Encoder mode, count up/down on TI2FP1 + 1 + + + EncoderTI1 + Encoder mode, count up/down on TI1FP2 + 2 + + + EncoderTI1TI2 + Encoder mode, count up/down on both TI1FP1 and TI2FP2 + 3 + + + Reset + Rising edge of the selected trigger input (TRGI) reinitializes the counter + 4 + + + Gated + The counter clock is enabled when the trigger input (TRGI) is high + 5 + + + Trigger + The counter starts at a rising edge of the trigger TRGI + 6 + + + External + Rising edges of the selected trigger (TRGI) clock the counter + 7 + + @@ -8785,6 +9676,29 @@ Update interrupt flag 0 1 + + UIFR + read + + NoUpdate + No update occurred + 0 + + + Pending + Update interrupt pending + 1 + + + + UIFW + write + + Clear + Clears the update interrupt flag + 0 + + @@ -8874,6 +9788,8 @@ Output Compare 2 mode 12 3 + + OC2PE @@ -8908,6 +9824,56 @@ Output Compare 1 mode 4 3 + + OC1M + + Frozen + The comparison between the output compare register TIMx_CCRy and the + counter TIMx_CNT has no effect on the outputs( + 0 + + + SetActive + Set channel y to active level on match. OCyREF signal is forced high when the counter + TIMx_CNT matches the capture/compare register y (TIMx_CCRy). + 1 + + + SetInactive + Set channel y to inactive level on match. OCyREF signal is forced low when the + counter TIMx_CNT matches the capture/compare register y (TIMx_CCRy). + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy. + 3 + + + ForceInactive + OCyREF is forced low. + 4 + + + ForceActive + OCyREF is forced high. + 5 + + + PWM1 + In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCRy + else inactive. In downcounting, channel 1 is inactive (OCyREF=‘0) as long as + TIMx_CNT>TIMx_CCRy else active (OCyREF=1). + 6 + + + PWM2 + In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy + else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else + inactive. + 7 + + OC1PE @@ -8950,7 +9916,7 @@ 4 - IC2PCS + IC2PSC Input capture 2 prescaler 10 2 @@ -8969,7 +9935,7 @@ 4 - ICPCS + IC1PSC Input capture 1 prescaler 2 2 @@ -9005,6 +9971,8 @@ Output compare 4 mode 12 3 + + OC4PE @@ -9039,6 +10007,8 @@ Output compare 3 mode 4 3 + + OC3PE @@ -9238,6 +10208,12 @@ counter value 0 16 + + + 0 + 65535 + + @@ -9255,6 +10231,12 @@ Prescaler value 0 16 + + + 0 + 65535 + + @@ -9272,6 +10254,12 @@ Auto-reload value 0 16 + + + 0 + 65535 + + @@ -9289,6 +10277,12 @@ Capture/Compare 1 value 0 16 + + + 0 + 65535 + + @@ -9306,6 +10300,12 @@ Capture/Compare 2 value 0 16 + + + 0 + 65535 + + @@ -9323,6 +10323,12 @@ Capture/Compare value 0 16 + + + 0 + 65535 + + @@ -9340,6 +10346,12 @@ Capture/Compare value 0 16 + + + 0 + 65535 + + @@ -9521,6 +10533,8 @@ Clock division 8 2 + + ARPE @@ -9540,12 +10554,16 @@ Direction 4 1 + + OPM One-pulse mode 3 1 + + URS @@ -9564,6 +10582,8 @@ Counter enable 0 1 + + @@ -9641,12 +10661,16 @@ Trigger selection 4 3 + + SMS Slave mode selection 0 3 + + @@ -9817,6 +10841,10 @@ Update interrupt flag 0 1 + + + + @@ -9893,6 +10921,8 @@ Output compare 2 mode 12 3 + + OC2PE @@ -9927,6 +10957,8 @@ Output compare 1 mode 4 3 + + OC1PE @@ -10013,7 +11045,7 @@ 0x00000000 - O24CE + OC4CE Output compare 4 clear enable 15 @@ -10024,6 +11056,8 @@ Output compare 4 mode 12 3 + + OC4PE @@ -10058,6 +11092,8 @@ Output compare 3 mode 4 3 + + OC3PE @@ -10215,6 +11251,12 @@ counter value 0 16 + + + 0 + 65535 + + @@ -10232,6 +11274,12 @@ Prescaler value 0 16 + + + 0 + 65535 + + @@ -10249,6 +11297,12 @@ Auto-reload value 0 16 + + + 0 + 65535 + + @@ -10266,6 +11320,12 @@ Capture/Compare 1 value 0 16 + + + 0 + 65535 + + @@ -10283,6 +11343,12 @@ Capture/Compare 2 value 0 16 + + + 0 + 65535 + + @@ -10300,6 +11366,12 @@ Capture/Compare value 0 16 + + + 0 + 65535 + + @@ -10317,6 +11389,12 @@ Capture/Compare value 0 16 + + + 0 + 65535 + + @@ -10421,6 +11499,8 @@ Clock division 8 2 + + ARPE @@ -10433,6 +11513,8 @@ One-pulse mode 3 1 + + URS @@ -10451,6 +11533,8 @@ Counter enable 0 1 + + @@ -10491,12 +11575,78 @@ Trigger selection 4 3 + + TS + + ITR0 + Internal Trigger 0 (ITR0) + 0 + + + ITR1 + Internal Trigger 1 (ITR1) + 1 + + + ITR2 + Internal Trigger 2 (ITR2) + 2 + + + ITR3 + Internal Trigger 3 (ITR3) + 3 + + + TI1F_ED + TI1 Edge Detector + 4 + + + TI1FP1 + Filtered Timer Input 1 + 5 + + + TI2FP2 + Filtered Timer Input 2 + 6 + + SMS Slave mode selection 0 3 + + SMS + + Disabled + Counter disabled + 0 + + + Reset + Rising edge of the selected trigger input (TRGI) reinitializes the counter + 4 + + + Gated + The counter clock is enabled when the trigger input (TRGI) is high + 5 + + + Trigger + The counter starts at a rising edge of the trigger TRGI + 6 + + + External + Rising edges of the selected trigger (TRGI) clock the counter + 7 + + @@ -10585,6 +11735,10 @@ Update interrupt flag 0 1 + + + + @@ -10640,6 +11794,8 @@ Output Compare 2 mode 12 3 + + OC2PE @@ -10667,6 +11823,8 @@ Output Compare 1 mode 4 3 + + OC1PE @@ -10810,6 +11968,12 @@ counter value 0 16 + + + 0 + 65535 + + @@ -10827,6 +11991,12 @@ Prescaler value 0 16 + + + 0 + 65535 + + @@ -10844,6 +12014,12 @@ Auto-reload value 0 16 + + + 0 + 65535 + + @@ -10861,6 +12037,12 @@ Capture/Compare 1 value 0 16 + + + 0 + 65535 + + @@ -10878,6 +12060,12 @@ Capture/Compare 2 value 0 16 + + + 0 + 65535 + + @@ -10924,6 +12112,8 @@ Clock division 8 2 + + ARPE @@ -10948,6 +12138,8 @@ Counter enable 0 1 + + @@ -11020,6 +12212,10 @@ Update interrupt flag 0 1 + + + + @@ -11062,6 +12258,8 @@ Output Compare 1 mode 4 3 + + OC1PE @@ -11158,6 +12356,12 @@ counter value 0 16 + + + 0 + 65535 + + @@ -11280,6 +12484,8 @@ One-pulse mode 3 1 + + URS @@ -11298,6 +12504,8 @@ Counter enable 0 1 + + @@ -11355,6 +12563,10 @@ Update interrupt flag 0 1 + + + + @@ -11389,6 +12601,12 @@ Low counter value 0 16 + + + 0 + 65535 + + @@ -11406,6 +12624,12 @@ Prescaler value 0 16 + + + 0 + 65535 + + @@ -11423,6 +12647,12 @@ Low Auto-reload value 0 16 + + + 0 + 65535 + + @@ -11853,6 +13083,18 @@ Master/slave 0 1 + + + Slave + Slave Mode + 0 + + + Master + Master Mode + 1 + + @@ -11977,6 +13219,18 @@ Data frame format 11 1 + + + Bit8 + 8-bit data frame format is selected for transmission/reception + 0 + + + Bit16 + 16-bit data frame format is selected for transmission/reception + 1 + + RXONLY @@ -12007,18 +13261,74 @@ SPI enable 6 1 + + BR Baud rate control 3 3 + + + Div2 + f_PCLK/2 + 0 + + + Div4 + f_PCLK/4 + 1 + + + Div8 + f_PCLK/8 + 2 + + + Div16 + f_PCLK/16 + 3 + + + Div32 + f_PCLK/32 + 4 + + + Div64 + f_PCLK/64 + 5 + + + Div128 + f_PCLK/128 + 6 + + + Div256 + f_PCLK/256 + 7 + + MSTR Master selection 2 1 + + + Slave + Slave configuration + 0 + + + Master + Master configuration + 1 + + CPOL @@ -18918,7 +20228,7 @@ - + F7R1 F7R1 @@ -23020,6 +24330,24 @@ 0 3 read-write + + LATENCY + + Zero + Zero wait state, if 0hz SYSCLK to 24 MHz + 0 + + + One + One wait state, if 24 MHz SYSCLK to 48 MHz + 1 + + + Two + Two wait states, if 48 MHz SYSCLK to 72 MHz + 2 + + HLFCYA @@ -23035,6 +24363,19 @@ 4 1 read-write + + ENABLED + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + PRFTBS @@ -24047,9 +25388,12 @@ - EP0R - EP0R - endpoint 0 register + EP%sR + EPnR + 8 + 0-7 + 0x4 + endpoint register array 0x0 0x20 read-write @@ -24060,6 +25404,12 @@ Endpoint address 0 4 + + + 0 + 15 + + STAT_TX @@ -24093,552 +25443,28 @@ Endpoint type 9 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP1R - EP1R - endpoint 1 register - 0x4 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP2R - EP2R - endpoint 2 register - 0x8 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP3R - EP3R - endpoint 3 register - 0xC - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP4R - EP4R - endpoint 4 register - 0x10 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP5R - EP5R - endpoint 5 register - 0x14 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP6R - EP6R - endpoint 6 register - 0x18 - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 - - - SETUP - Setup transaction - completed - 11 - 1 - - - STAT_RX - Status bits, for reception - transfers - 12 - 2 - - - DTOG_RX - Data Toggle, for reception - transfers - 14 - 1 - - - CTR_RX - Correct transfer for - reception - 15 - 1 - - - - - EP7R - EP7R - endpoint 7 register - 0x1C - 0x20 - read-write - 0x00000000 - - - EA - Endpoint address - 0 - 4 - - - STAT_TX - Status bits, for transmission - transfers - 4 - 2 - - - DTOG_TX - Data Toggle, for transmission - transfers - 6 - 1 - - - CTR_TX - Correct Transfer for - transmission - 7 - 1 - - - EP_KIND - Endpoint kind - 8 - 1 - - - EP_TYPE - Endpoint type - 9 - 2 + + + BULK + This endpoint is a bulk endpoint + 0 + + + CONTROL + This endpoint is a control endpoint + 1 + + + ISO + This endpoint is an isochronous endpoint + 2 + + + INTERRUPT + This endpoint is an interrupt endpoint + 3 + + SETUP