diff --git a/STM32F429.svd b/STM32F429_new.svd index fb4f5d4..67d145a 100644 --- a/STM32F429.svd +++ b/STM32F429_new.svd @@ -4,16 +4,16 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> STM32F429 1.2 - STM32F429 - - - CM4 - r1p0 - little - false - false - 3 - false + STM32F429 + + + CM4 + r1p0 + little + false + false + 3 + false @@ -6817,6 +6817,24 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> TRACE_MODE 6 2 + + + ASYNC + 0 + + + SYNC1 + 1 + + + SYNC2 + 2 + + + SYNC4 + 3 + + @@ -9814,6 +9832,20 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0x00000083 + PLLSAIRDY + PLLSAI clock ready flag + 29 + 1 + read-only + + + PLLSAION + PLLSAI enable + 28 + 1 + read-write + + PLLI2SRDY PLLI2S clock ready flag 27 @@ -9915,36 +9947,19 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0x24003010 - PLLQ3 - Main PLL (PLL) division factor for USB - OTG FS, SDIO and random number generator - clocks - 27 - 1 - - - PLLQ2 - Main PLL (PLL) division factor for USB - OTG FS, SDIO and random number generator - clocks - 26 - 1 - - - PLLQ1 - Main PLL (PLL) division factor for USB - OTG FS, SDIO and random number generator - clocks - 25 - 1 - - - PLLQ0 + PLLQ Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks 24 - 1 + 4 + read-write + + + 2 + 15 + + PLLSRC @@ -9952,125 +9967,55 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> entry clock source 22 1 + + + HSI + 0 + + + HSE + 1 + + - PLLP1 - Main PLL (PLL) division factor for main - system clock - 17 - 1 - - - PLLP0 + PLLP Main PLL (PLL) division factor for main system clock 16 - 1 - - - PLLN8 - Main PLL (PLL) multiplication factor for - VCO - 14 - 1 - - - PLLN7 - Main PLL (PLL) multiplication factor for - VCO - 13 - 1 - - - PLLN6 - Main PLL (PLL) multiplication factor for - VCO - 12 - 1 - - - PLLN5 - Main PLL (PLL) multiplication factor for - VCO - 11 - 1 - - - PLLN4 - Main PLL (PLL) multiplication factor for - VCO - 10 - 1 - - - PLLN3 - Main PLL (PLL) multiplication factor for - VCO - 9 - 1 - - - PLLN2 - Main PLL (PLL) multiplication factor for - VCO - 8 - 1 - - - PLLN1 - Main PLL (PLL) multiplication factor for - VCO - 7 - 1 + 2 + + + DIV2 + 0 + + + DIV4 + 1 + + + DIV6 + 2 + + + DIV8 + 3 + + - PLLN0 + PLLN Main PLL (PLL) multiplication factor for VCO 6 - 1 - - - PLLM5 - Division factor for the main PLL (PLL) - and audio PLL (PLLI2S) input clock - 5 - 1 - - - PLLM4 - Division factor for the main PLL (PLL) - and audio PLL (PLLI2S) input clock - 4 - 1 - - - PLLM3 - Division factor for the main PLL (PLL) - and audio PLL (PLLI2S) input clock - 3 - 1 - - - PLLM2 - Division factor for the main PLL (PLL) - and audio PLL (PLLI2S) input clock - 2 - 1 - - - PLLM1 - Division factor for the main PLL (PLL) - and audio PLL (PLLI2S) input clock - 1 - 1 + 9 - PLLM0 + PLLM Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock 0 - 1 + 6 @@ -10089,6 +10034,25 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 30 2 read-write + + MCO2 + + SYSCLK + 0 + + + PLLI2S + 1 + + + HSE + 2 + + + PLL + 3 + + MCO2PRE @@ -10096,6 +10060,41 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 27 3 read-write + + + 0 + 7 + + + + MCOPRE + + No division + NO_DIV + true + 0 + + + Division by 2 + DIV2 + 4 + + + Division by 3 + DIV3 + 5 + + + Division by 4 + DIV4 + 6 + + + Division by 5 + DIV5 + 7 + + MCO1PRE @@ -10103,6 +10102,13 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 24 3 read-write + + + 0 + 7 + + + I2SSRC @@ -10110,6 +10116,16 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 23 1 read-write + + + PLLI2S + 0 + + + I2S_CKIN + 1 + + MCO1 @@ -10118,6 +10134,28 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 21 2 read-write + + + HSI clock selected + HSI + 0 + + + LSE oscillator selected + LSE + 1 + + + HSE oscillator clock selected + HSE + 2 + + + PLL clock selected + PLL + 3 + + RTCPRE @@ -10134,6 +10172,12 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 13 3 read-write + + + 0 + 7 + + PPRE1 @@ -10142,6 +10186,12 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 10 3 read-write + + + 0 + 7 + + HPRE @@ -10149,34 +10199,54 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 4 4 read-write + + + 0 + 15 + + - SWS1 - System clock switch status - 3 - 1 - read-only - - - SWS0 + SWS System clock switch status 2 - 1 + 2 read-only + + + HSI + 0 + + + HSE + 1 + + + PLL + 2 + + - SW1 - System clock switch - 1 - 1 - read-write - - - SW0 + SW System clock switch 0 - 1 + 2 read-write + + + HSI + 0 + + + HSE + 1 + + + PLL + 2 + + @@ -10360,6 +10430,12 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 1 + DMA2DRST + DMA2D reset + 23 + 1 + + DMA2RST DMA2 reset 22 @@ -10640,6 +10716,18 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 29 1 + + UART7RST + UART 7 reset + 30 + 1 + + + UART8RST + UART 8 reset + 31 + 1 + @@ -10695,6 +10783,12 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 1 + SPI4RST + SPI 4 reset + 13 + 1 + + SYSCFGRST System configuration controller reset @@ -10719,6 +10813,30 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 18 1 + + SPI5RST + SPI 5 reset + 20 + 1 + + + SPI6RST + SPI 6 reset + 21 + 1 + + + SAI1RST + SAI 1 reset + 22 + 1 + + + LTDCRST + LTDC reset + 26 + 1 + @@ -10770,6 +10888,12 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 1 + DMA2DEN + DMA2D clock enable + 23 + 1 + + DMA2EN DMA2 clock enable 22 @@ -11069,6 +11193,18 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 29 1 + + UART7EN + UART7 clock enable + 30 + 1 + + + UART8EN + UART8 clock enable + 31 + 1 + @@ -11136,6 +11272,12 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 1 + SPI4EN + SPI4 clock enable + 13 + 1 + + SYSCFGEN System configuration controller clock enable @@ -11160,6 +11302,30 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 18 1 + + SPI5EN + SPI5 clock enable + 20 + 1 + + + SPI6EN + SPI6 clock enable + 21 + 1 + + + SAI1EN + SAI1 clock enable + 22 + 1 + + + LTDCEN + LTDC clock enable + 26 + 1 + @@ -11271,6 +11437,13 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 1 + SRAM3LPEN + SRAM 3 interface clock enable during + Sleep mode + 19 + 1 + + DMA1LPEN DMA1 clock enable during Sleep mode @@ -11285,6 +11458,13 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 1 + DMA2DLPEN + DMA2D clock enable during Sleep + mode + 23 + 1 + + ETHMACLPEN Ethernet MAC clock enable during Sleep mode @@ -11565,6 +11745,20 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 29 1 + + UART7LPEN + UART7 clock enable during Sleep + mode + 30 + 1 + + + UART8LPEN + UART8 clock enable during Sleep + mode + 31 + 1 + @@ -11641,6 +11835,13 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 1 + SPI4LPEN + SPI 4 clock enable during Sleep + mode + 13 + 1 + + SYSCFGLPEN System configuration controller clock enable during Sleep mode @@ -11668,6 +11869,34 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 18 1 + + SPI5LPEN + SPI5 clock enable during Sleep + mode + 20 + 1 + + + SPI6LPEN + SPI6 clock enable during Sleep + mode + 21 + 1 + + + SAI1LPEN + SAI1 clock enable during Sleep + mode + 22 + 1 + + + LTDCLPEN + LTDC clock enable during Sleep + mode + 26 + 1 + @@ -12000,6 +12229,29 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 30 2 + + MODER + + Input (reset state) + input + 0 + + + General purpose output mode + output + 1 + + + af + Alternate Function mode + 2 + + + Analog + Analog mode + 3 + + MODER14 @@ -12007,6 +12259,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 28 2 + MODER13 @@ -12014,6 +12267,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 26 2 + MODER12 @@ -12021,6 +12275,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 24 2 + MODER11 @@ -12028,6 +12283,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 22 2 + MODER10 @@ -12035,6 +12291,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 20 2 + MODER9 @@ -12042,6 +12299,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 18 2 + MODER8 @@ -12049,6 +12307,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 16 2 + MODER7 @@ -12056,6 +12315,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 14 2 + MODER6 @@ -12063,6 +12323,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 12 2 + MODER5 @@ -12070,6 +12331,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 10 2 + MODER4 @@ -12077,6 +12339,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 8 2 + MODER3 @@ -12084,6 +12347,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 6 2 + MODER2 @@ -12091,6 +12355,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 4 2 + MODER1 @@ -12098,6 +12363,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 2 2 + MODER0 @@ -12105,6 +12371,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 0 2 + @@ -12123,6 +12390,19 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 15 1 + + OTYPER + + Output push pull (reset state) + push_pull + 0 + + + Output open drain + open_drain + 1 + + OT14 @@ -12130,6 +12410,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 14 1 + OT13 @@ -12137,6 +12418,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 13 1 + OT12 @@ -12144,6 +12426,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 12 1 + OT11 @@ -12151,6 +12434,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 11 1 + OT10 @@ -12158,6 +12442,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 10 1 + OT9 @@ -12165,6 +12450,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 9 1 + OT8 @@ -12172,6 +12458,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 8 1 + OT7 @@ -12179,6 +12466,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 7 1 + OT6 @@ -12186,6 +12474,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 6 1 + OT5 @@ -12193,6 +12482,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 5 1 + OT4 @@ -12200,6 +12490,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 4 1 + OT3 @@ -12207,6 +12498,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 3 1 + OT2 @@ -12214,6 +12506,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 2 1 + OT1 @@ -12221,6 +12514,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 1 1 + OT0 @@ -12228,6 +12522,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 0 1 + @@ -12247,6 +12542,29 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 30 2 + + OSPEEDR + + Low speed + low + 0 + + + Medium speed + medium + 1 + + + High speed + high + 2 + + + Very high speed + VERY_HIGH + 3 + + OSPEEDR14 @@ -12254,6 +12572,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 28 2 + OSPEEDR13 @@ -12261,6 +12580,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 26 2 + OSPEEDR12 @@ -12268,6 +12588,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 24 2 + OSPEEDR11 @@ -12275,6 +12596,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 22 2 + OSPEEDR10 @@ -12282,6 +12604,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 20 2 + OSPEEDR9 @@ -12289,6 +12612,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 18 2 + OSPEEDR8 @@ -12296,6 +12620,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 16 2 + OSPEEDR7 @@ -12303,6 +12628,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 14 2 + OSPEEDR6 @@ -12310,6 +12636,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 12 2 + OSPEEDR5 @@ -12317,6 +12644,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 10 2 + OSPEEDR4 @@ -12324,6 +12652,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 8 2 + OSPEEDR3 @@ -12331,6 +12660,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 6 2 + OSPEEDR2 @@ -12338,6 +12668,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 4 2 + OSPEEDR1 @@ -12345,6 +12676,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 2 2 + OSPEEDR0 @@ -12352,6 +12684,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0..15) 0 2 + @@ -26712,99 +27045,156 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> RE - RE + Recieve enable 2 1 TE - TE + Transmit enable 3 1 DC - DC + Deferral check 4 1 BL - BL + Back-off limit 5 2 + + + r10 + 0 + + + r8 + 1 + + + r4 + 2 + + + r1 + 3 + + APCS - APCS + Automatic pad/CRC stripping 7 1 RD - RD + Retry disable 9 1 IPCO - IPCO + IPv4 Checksum offload 10 1 DM - DM + Duplex mode 11 1 LM - LM + Loopback mode 12 1 ROD - ROD + Recieve own disable 13 1 FES - FES + Fast Ethernet Speed 14 1 + + + rate_10 + 0 + + + rate_100 + 1 + + CSD - CSD + Carrier sense disable 16 1 IFG - IFG + Interframe gap (96,86,80, ... 40) 17 3 + + + 31 + 0 + + JD - JD + Jabber disable (transmitter) 22 1 + + WD + + limit2048 + 0 + + + limit16384 + 1 + + WD - WD + Watchdog Disable (reciever) 23 1 + CSTF - CSTF + CRC stripping for type frames 25 1 + + CSTF + + keep_ether_crc + 0 + + + strip_ether_crc + 1 + + @@ -26820,67 +27210,95 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> PM - PM + Promiscuous mode 0 1 HU - HU + Hash unicast 1 1 HM - HM + Hash multicast 2 1 DAIF - DAIF + Destination address inverse filtering 3 1 - RAM - RAM + PAM + Pass all multicast 4 1 BFD - BFD + Broadcast frames enable 5 1 PCF - PCF + Pass control frames 6 - 1 + 2 + + + no_control_frames + 0 + + + no_pause_frames + 1 + + + control_frames_bypass_filter + 2 + + + control_frames + 3 + + SAIF - SAIF - 7 + Source address inverse filtering + 8 1 SAF - SAF - 8 + Source address filter + 9 1 HPF - HPF - 9 + Hash or perfect filter + 10 1 + + + both_filters + 0 + + + only_hash_filter + 1 + + RA - RA + Recieve All 31 1 @@ -26901,6 +27319,12 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> HTH 0 32 + + + 0xffffffff + 0 + + @@ -26919,6 +27343,12 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> HTL 0 32 + + + 0xffffffff + 0 + + @@ -26946,21 +27376,61 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> CR - CR + Clock Range 2 3 + + CR + + div42 + 60-100 MHz HCLK/42 + 0 + + + div62 + 100-150 MHz HCLK/62 + 1 + + + div16 + 20-35 MHz HCLK/16 + 2 + + + div26 + 35-60 MHz HCLK/26 + 3 + + + div102 + 150-168 MHz HCLK/102 + 4 + + MR - MR + MII Register - select the desired MII register in the PHY device 6 5 + + + 31 + 0 + + PA - PA + PHY address - select which of possible 32 phys is being accessed 11 5 + + + 31 + 0 + + @@ -26974,10 +27444,16 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 0x00000000 - TD - TD + MD + MII data read from the PHY or to be written to the PHY 0 16 + + + 0xffff + 0 + + @@ -26993,45 +27469,51 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> FCB - FCB + Flow control busy/back pressure activate 0 1 TFCE - TFCE + Transmit flow control enable 1 1 RFCE - RFCE + Recieve flow control enable 2 1 UPFD - UPFD + Unicast pause frame detect 3 1 PLT - PLT + Pause low threshold 4 2 ZQPD - ZQPD + Zero-quanta pause disable 7 1 PT - PT + Pause time 16 16 + + + 0xffff + 0 + + @@ -27046,15 +27528,32 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> VLANTI - VLANTI + VLAN tag identifier (for recieve frames) 0 16 + + + 0xffff + 0 + + VLANTC - VLANTC + 12-bit VLAN tag comparison 16 1 + + VLANTC + + cmp16 + 0 + + + cmp12 + 1 + + @@ -48476,8 +48975,14 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> LATENCY Latency 0 - 3 + 4 read-write + + + 0 + 15 + + PRFTEN @@ -59074,7 +59579,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> AAV - AAV + Accumulated Active Width 16 10 @@ -63430,5 +63935,76 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> + + + DEVICE_ID + Unique device ID + DEVICE_ID + 0x1FFF7A10 + + 0x0 + 0x60 + registers + + + + UID1 + UID1 + X and Y coordinates on the wafer + 0x0 + 0x20 + read-only + + + UID + X and Y coordinates on the wafer + 0 + 32 + read-only + + + + + UID2 + UID2 + Lot/wafer number + 0x4 + 0x20 + + + LOT_NUM + Lot number (ASCII encoded, end) + 8 + 24 + read-only + + + WAF_NUM + Wafer number (ASCII encoded) + 0 + 8 + read-only + + + + + UID3 + UID3 + Lot number + 0x8 + 0x20 + + + LOT_NUM + Lot number (ASCII encoded, start) + 0 + 32 + read-only + + + + + +