\8U\(aU$,starfive,visionfive-2-v1.2astarfive,jh7110 &StarFive VisionFive 2 v1.2Acpus ,= cpu@0sifive,s7riscv?CcpuO@b@o@|rv64imac_zba_zbb disabledinterrupt-controllerriscv,cpu-intc cpu@1sifive,u74-mcriscv?@@(CcpuO@b@o( %riscv,sv39|rv64imafdc_zba_zbb.8LScpu_interrupt-controllerriscv,cpu-intccpu@2sifive,u74-mcriscv?@@(CcpuO@b@o( %riscv,sv39|rv64imafdc_zba_zbb.8LScpu_interrupt-controllerriscv,cpu-intccpu@3sifive,u74-mcriscv?@@(CcpuO@b@o( %riscv,sv39|rv64imafdc_zba_zbb.8LScpu_interrupt-controllerriscv,cpu-intccpu@4sifive,u74-mcriscv?@@(CcpuO@b@o( %riscv,sv39|rv64imafdc_zba_zbb.8LScpu_ interrupt-controllerriscv,cpu-intcopp-table-0operating-points-v2ndvp-clock fixed-clockydvp_clkl5gmac0-rgmii-rxin-clock fixed-clockygmac0_rgmii_rxinsY@3gmac0-rmii-refin-clock fixed-clockygmac0_rmii_refin2gmac1-rgmii-rxin-clock fixed-clockygmac1_rgmii_rxinsY@ gmac1-rmii-refin-clock fixed-clockygmac1_rmii_refinhdmitx0-pixel-clock fixed-clockyhdmitx0_pixelclk@7i2srx-bclk-ext-clock fixed-clockyi2srx_bclk_ext#i2srx-lrck-ext-clock fixed-clockyi2srx_lrck_ext$i2stx-bclk-ext-clock fixed-clockyi2stx_bclk_ext!i2stx-lrck-ext-clock fixed-clockyi2stx_lrck_ext"mclk-ext-clock fixed-clock ymclk_ext%oscillator fixed-clockyoscn6rtc-oscillator fixed-clockyrtc_osc4stmmac-axi-config@ .tdm-ext-clock fixed-clockytdm_extsoc simple-bus  timer@2000000"starfive,jh7110-clintriscv,clint?P  cache-controller@2010000,starfive,jh7110-ccachesifive,ccache0cache?@ Q@dq "interrupt-controller@c000000 starfive,jh7110-plicriscv,plic? H          0 sram@8000000=starfive,jh7110-sramsifive,u74-mc-sramsifive,u74-mc-l2-lim? serial@10000000snps,dw-apb-uart?LSbaudclkapb_pclk;S BOokayYdefaultgserial@10010000snps,dw-apb-uart?LSbaudclkapb_pclk;U !BO disabledserial@10020000snps,dw-apb-uart?LSbaudclkapb_pclk;W "BO disabledi2c@10030000snps,designware-i2c?LSref;L # okayq,Ydefaultgi2c@10040000snps,designware-i2c?LSref;M $  disabledi2c@10050000snps,designware-i2c?LSref;N % okayq,Ydefaultgspi@10060000arm,pl022arm,primecell?LSsspclkapb_pclk;E &" okayYdefaultgspi@0rohm,dh2228fv?spi@10070000arm,pl022arm,primecell?LSsspclkapb_pclk;F '"  disabledspi@10080000arm,pl022arm,primecell?LSsspclkapb_pclk;G ("  disabledtdm@10090000starfive,jh7110-tdm? ,L4Stdm_ahbtdm_apbtdm_internaltdmmclk_innertdm_ext;ikjrxtxokayYdefaultgdmc@15700000'starfive,jh7110-dmc-ctrlopenedges,omc?p;&'( axioscapbUdmc@13000000'starfive,jh7110-dmc-phyopenedges,ophy?;&'( axioscapbUusb@10100000starfive,jh7110-usb (LSlpmstbapbaxiutmi_apb ;  pwrupapbaxiutmi_apb disabled &peripheralusb@0 cdns,usb3? .otgxhcidev  dln8hostperipheralotgHMcdns3,usb2-phyphy@10200000starfive,jh7110-usb-phy? L_S125mapp_125mWphy@10210000starfive,jh7110-pcie-phy?!Wphy@10220000starfive,jh7110-pcie-phy?"Wclock-controller@10230000starfive,jh7110-stgcrg?#<L6_7 HSoschifi4_corestg_axiahbusb_125mcpu_bushifi4_axinocstg_busapb_busbsyscon@10240000"starfive,jh7110-stg-sysconsyscon?$serial@12000000snps,dw-apb-uart?LSbaudclkapb_pclk;Y -BO disabledserial@12010000snps,dw-apb-uart?LSbaudclkapb_pclk;[ .BO disabledserial@12020000snps,dw-apb-uart?LSbaudclkapb_pclk;] /BO disabledi2c@12030000snps,designware-i2c?LSref;O 0  disabledi2c@12040000snps,designware-i2c?LSref;P 1  disabledi2c@12050000snps,designware-i2c?LSref;Q 2 okayq,Ydefaultgi2c@12060000snps,designware-i2c?LSref;R 3 okayq,Ydefaultgspi@12070000arm,pl022arm,primecell?LSsspclkapb_pclk;H 4"  disabledspi@12080000arm,pl022arm,primecell?LSsspclkapb_pclk;I 5"  disabledspi@12090000arm,pl022arm,primecell? LSsspclkapb_pclk;J 6"  disabledspi@120a0000arm,pl022arm,primecell? LSsspclkapb_pclk;K 7"  disabledtemperature-sensor@120e0000starfive,jh7110-temp?L Ssensebus;|{ sensebuso spi@13010000#starfive,jh7110-qspicdns,qspi-nor? LZWX Srefahbapb;>=?qspiqspi-ocprstc_refokay flash@0jedec,spi-nor?spi@21000000#starfive,jh7110-xspicdns,xspi-nor?!@LZWX Srefahbapb;>=?xspiqspirstc_refokay flash@0jedec,spi-nor?pwm@120d0000%starfive,jh7110-pwmopencores,pwm-v1? Ly;l disabledclock-controller@13020000starfive,jh7110-syscrg?<L !"#$%&&&Soscgmac1_rmii_refingmac1_rgmii_rxini2stx_bclk_exti2stx_lrck_exti2srx_bclk_exti2srx_lrck_exttdm_extmclk_extpll0_outpll1_outpll2_outbsyscon@13030000-starfive,jh7110-sys-sysconsysconsimple-mfd?(clock-controllerstarfive,jh7110-pllL&pinctrl@13040000starfive,jh7110-sys-pinctrl?Lp; V 8i2c0-0i2c-pins) 9 :0=Ji2c2-0i2c-pins);x<|0=Ji2c5-0i2c-pins)OP0=Ji2c6-0i2c-pins)VW0=Jmmc0-0)rst-pins)>_l {mmc-pins()@ABCDEFGHI_l =mmc1-0,clk-pins)7 _l {mmc-pins),9L -:P .;T /okayYdefaultg,ethernet@160300001starfive,jh7110-dwmacsnps,dwmac-5.20snps,dwmac?(L--m-oSstmmacethpclkptp_reftxgtx;--stmmacethahb  8macirqeth_wake_irqeth_lpi@(7R.bk / okay rgmii-idethernet@160400001starfive,jh7110-dwmacsnps,dwmac-5.20snps,dwmac?(LbafjkSstmmacethpclkptp_reftxgtx;BCstmmacethahb  NML8macirqeth_wake_irqeth_lpi@(7R.bk (okayrmiiigeedma-controller@16050000)starfive,jh7110-axi-dmasnps,dw-axi-dmac?LScore-clkcfgr-clk; I (clock-controller@17000000starfive,jh7110-aoncrg?(L23 l4NSoscgmac0_rmii_refingmac0_rgmii_rxinstg_axiahbapb_busgmac0_gtxclkrtc_oscb-syscon@17010000"starfive,jh7110-aon-sysconsyscon??/pinctrl@17020000starfive,jh7110-aon-pinctrl?;- U power-controller@17030000starfive,jh7110-pmu? o?6clock-controller@19810000starfive,jh7110-ispcrg?L34551Sisp_top_coreisp_top_axinoc_bus_isp_axidvp_clk;)*bS6syscon@19840000starfive,jh7110-isp-syscon?syscon@295b0000starfive,jh7110-vout-syscon?)[clock-controller@295c0000starfive,jh7110-voutcrg?)\,L:=>?7VSvout_srcvout_top_ahbvout_top_axivout_top_hdmitx0_mclki2stx0_bclkhdmitx0_pixelclk;+bS6syscon@295e0000starfive,jh7110-mipitx-dphy?)^ compatible#address-cells#size-cellsmodeltimebase-frequencyregdevice_typei-cache-block-sizei-cache-setsi-cache-sizenext-level-cacheriscv,isastatusphandleinterrupt-controller#interrupt-cellsd-cache-block-sized-cache-setsd-cache-sized-tlb-setsd-tlb-sizei-tlb-setsi-tlb-sizemmu-typetlb-splitoperating-points-v2clocksclock-names#cooling-cellsopp-sharedclock-output-names#clock-cellsclock-frequencysnps,lpi_ensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,bleninterrupt-parentrangesinterrupts-extendedinterruptscache-levelcache-unifiedriscv,ndevresetsreg-io-widthreg-shiftpinctrl-namespinctrl-0i2c-sda-hold-time-nsi2c-sda-falling-time-nsi2c-scl-falling-time-nsarm,primecell-periphidnum-csspi-max-frequencydmasdma-names#sound-dai-cellsreset-namesstarfive,stg-syscondr_modereg-namesinterrupt-namesphysphy-names#phy-cells#reset-cells#thermal-sensor-cellscdns,fifo-depthcdns,fifo-widthcdns,trigger-addresscdns,read-delaycdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-ns#pwm-cellsgpio-controller#gpio-cellspinmuxbias-disableinput-enableinput-schmitt-enablebias-pull-updrive-strengthinput-disableinput-schmitt-disableslew-ratelli-bus-interface-ahb1mem-bus-interface-ahb1memcpy-burst-sizememcpy-bus-width#dma-cellsfifo-watermark-aligneddata-addrstarfive,sysregcap-mmc-highspeedmmc-ddr-1_8vmmc-hs200-1_8vnon-removablecap-mmc-hw-resetpost-power-on-delay-msno-sdiono-mmcbroken-cdcap-sd-highspeedrx-fifo-depthtx-fifo-depthsnps,multicast-filter-binssnps,perfect-filter-entriessnps,fixed-burstsnps,no-pbl-x8snps,force_thresh_dma_modesnps,axi-configsnps,tsosnps,en-tx-lpi-clockgatingsnps,txpblsnps,rxpblstarfive,sysconphy-modeassigned-clocksassigned-clock-parentsdma-channelssnps,dma-masterssnps,data-widthsnps,block-sizesnps,prioritysnps,axi-max-burst-len#power-domain-cellspower-domains