Infineon IFX Test_pac ARMCM3 1.2 SVD Test for Rust PAC generator Test license\n CM3 r1p0 little true true 3 false 8 32 32 read-write 0x00000000 0xFFFFFFFF TIMER 1.0 Description of peripheral TIMER 0x40010000 read-write 0 0x100000 registers TIMER0 Timer 0 interrupt 0 BITFIELD_REG Register to test basic bitfield features 0x00 read-write 0x1337F7F BoolR Boolean Bitfield Read Only [0:0] read-only BoolW Boolean Bitfield Write Only [1:1] write-only BoolRW Boolean bitfield Read Write [2:2] read-write BitfieldR Raw Bitfield Read Only [5:3] read-only BitfieldW Bitfield Raw Write Only [7:6] write-only BitfieldRW BitField Raw Read Write [11:8] read-write BitfieldEnumerated Bitfield with enumerated field [15:12] read-write CClk Core Clock 0 GPIOA_0 GPIO A, PIN 0 1 GPIOA_1 GPIO A, PIN 1 2 GPIOA_2 GPIO A, PIN 2 3 GPIOA_3 GPIO A, PIN 3 4 GPIOA_4 GPIO A, PIN 4 5 GPIOA_5 GPIO A, PIN 5 6 GPIOA_6 GPIO A, PIN 6 7 GPIOA_7 GPIO A, PIN 7 8 GPIOB_0 GPIO B, PIN 0 9 GPIOB_1 GPIO B, PIN 1 10 GPIOB_2 GPIO B, PIN 2 11 GPIOB_3 GPIO B, PIN 3 12 GPIOC_0 GPIO C, PIN 0 13 GPIOC_5 GPIO C, PIN 1 14 GPIOC_6 GPIO C, PIN 2 15 8 2 Field%sArray Array of bitfields [17:16] read-write RISING Only rising edges result in a counter increment or decrement 0 FALLING Only falling edges result in a counter increment or decrement 1 BOTH Rising and falling edges result in a counter increment or decrement 2 SR Status Register 0x04 16 read-only 0x00000000 0xD701 RUN Shows if Timer is running or not [0:0] read-only Stopped Timer is not running 0 Running Timer is running 1 MATCH Shows if the MATCH was hit [8:8] read-write No_Match The MATCH condition was not hit 0 Match_Hit The MATCH condition was hit 1 UN Shows if an underflow occured. This flag is sticky [9:9] read-write No_Underflow No underflow occured since last clear 0 Underflow A minimum of one underflow occured since last clear 1 OV Shows if an overflow occured. This flag is sticky [10:10] read-write No_Overflow No overflow occured since last clear 0 Overflow_occured A minimum of one overflow occured since last clear 1 RST Shows if Timer is in RESET state [12:12] read-only Ready Timer is not in RESET state and can operate 0 In_Reset Timer is in RESET state and can not operate 1 RELOAD Shows the currently active RELOAD Register [15:14] read-only RELOAD0 Reload Register number 0 is active 0 RELOAD1 Reload Register number 1 is active 1 RELOAD2 Reload Register number 2 is active 2 RELOAD3 Reload Register number 3 is active 3 INT Interrupt Register 0x10 16 write-only 0x00000000 0x0771 EN Interrupt Enable [0:0] read-write Disabled Timer does not generate Interrupts 0 Enable Timer triggers the TIMERn Interrupt 1 MODE Interrupt Mode, selects on which condition the Timer should generate an Interrupt [6:4] read-write Match Timer generates an Interrupt when the MATCH condition is hit 0 Underflow Timer generates an Interrupt when it underflows 1 Overflow Timer generates an Interrupt when it overflows 2 NOBITFIELD_REG The Counter Register reflects the actual Value of the Timer/Counter 0x20 read-write 0x00000000 0xFFFFFFFF MATCH The Match Register stores the compare Value for the MATCH condition 0x24 read-writeOnce PRESCALE_RD The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value 0x28 read-only PRESCALE_WR The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value 0x2C write-only 0x00000000 0xFFFFFFFF 4 4 ARRAYREG[%s] Array of register 0x50 read-write 0x00000000 0xFFFFFFFF BITFIELD_REG Another defintion register using alternate group alt_group 0x00 register64bit 64 bit register 0x60 64 read-write 0xFFFFFFFFFFFFFFFF 0xFFFFFFFFFFFFFFFF boolean 0 0 read-write True 1 False 0 TIMER Register to test when peripheral has same name as register 0x2000 read-write Cluster1 Test Cluster 0x100 Cluster1 A cluster inside another cluster 0x100 NestedReg 0x00 read-write 0x12345 1 16 HSSL[%s] HSSL HSSL_HSSL 0x200 2 4 CH[%s] CH HSSL_HSSL_CH 0x0 HSSLxCOKy HSSL0 Channel 0 OK Service Request resetvalue={Application Reset:0x0} 0x0 32 0x0 0x0FFFFFFFF CR 0x00 read-write 0x0 filed1 0 2 read-write PSC 3 4 read-write val1 1 4 0x100 ClusterDim[%s] Test Cluster array 0x1000 CR 0x00 read-write 0x1000 filed1 0 2 read-write PSC 3 4 read-write val1 1 3 0x1000 UART[%s] 1.0 Test cluster 0x50000000 read-write 0 0x1000000 registers UartInt Uart interrupt 2 2 0x4 Reg1_[%s] read-write reg 0x0 read-write 0x000 0xFFFFFFFF RegBitfieldRaw Register with bitfields without enumeration 0x100 read-write 0x000 0xFFFFFFFF Bitfield9bits 0 8 read-write Bitfield17bits 9 26 read-write Bool 27 27 read-write Reg16bitEnum read write reg enum 0x104 16 read-write 0x000 0xFFFF Bitfield9bitsEnum Check when bitfield size is not standard 0 8 read-write Val0 0 Val256 256 Boolenum Boolean with enum 9 15 read-write bool0 0 bool1 1 Reg8bitRaw Read write whithout enum 0x106 8 read-write 0x00 0xFF Reg16bitRaw Read write without enum 0x107 16 read-write 0x0000 0xFFFF Reg32bitRaw Read write without enum 0x109 read-write 0x0000000 0xFFFFFFFF UART Cluster to test when peripheral has same name as register 0x1000 UART 0x00 read-write UART 0 2 read-write FOO 1.0 Fake peripheral containing registers with names starting with non XID_Start characters that cannot be directly used as Rust identifier names. FOO 0x60000000 read-write 0 0x100 registers INT_FOO Foo interrupt 3 IN FOO Input Register 0x0 8 read-write 0x0 0xFF SELF SELF element of FOO 1 1 read-write 0_VALUE Input is on low level. 0 1_VALUE Input is on high level. 1 EscapeTest 1.0 Fake peripheral containing register with characters that may need to be escaped (and some UTF-8) when documentation is inserted. 0x70000000 read-write 0 0x100 registers interrupt []\"😀"\n\a multi-line \r'𒀀𒀽 42 register []\"😀"\n\a\r'𒀀𒀽 0x0 8 read-write 0x0 0xFF field []\"😀"\n\a\r'𒀀𒀽 1 1 read-write enum_value []\"😀"\n\a\r'𒀀𒀽 0 DerivedTest 1.0 Fake Peripheral to test cluster and register with derivedFrom attribute 0xA0000 read-write 0 0x2000 registers BaseRegister BaseRegister 0x1000 16 read-write 0x00000000 0xD701 RUN Shows if Timer is running or not [0:0] read-only Stopped Timer is not running 0 Running Timer is running 1 DerivedRegister 0x1002 DerivedFromFarAway 0x1004 BaseCluster Cluster that defines the base type BaseClusterType 0x0 Reg1 0x00 Reg2 0x4 4 8 ArrayCluster[%s] ArrayCluster 0x8 1 16 DerivedDerivedCluster[%s] 0x100 DerivedFromFarAwayCluster 0x200 P33 Port naming peripheral struct and peripheral const are the same 0x70100000 read-write 0 0x2000 registers I2C2 Cluster that defines the base type 0x0 Reg1 0x00 Reg2 0x4 DerivedPeripheral DerivedPeripheral 0x70200000 HasHeaderStruct HeaderStruct 1.0 Peripheral with a headerStructName 0x70300000 read-write 0 0x100 registers I2C2 Cluster that defines the base type 0x0 Reg1 0x00 Reg2 0x4 HdrStrDer HdrStructDerivedP33 1.0 Peripheral with a headerStructName and derived from another peripheral 0x70400000 HdrStrDerHdrStruct HdrStructDerivedHdr 1.0 Peripheral with a headerStructName and derived from peripheral with headerStructName 0x70500000 CPU0 100 CPU 0 0 65472 registers 18 8 DPR[%s] DPR 49152 DPRy_L CPUx Data Protection Range 0 Lower Bound Register resetvalue={Application Reset:0x0} 0 32 0 4294967295 LOWBND DPRy Lower Boundary Address LOWBND 3 31 read-write DPRy_U CPUx Data Protection Range 0 Upper Bound Register resetvalue={Application Reset:0x0} 4 32 0 4294967295 UPPBND DPRy Upper Boundary Address UPPBND 3 31 read-write 10 8 CPR[%s] CPR 53248 CPRy_L CPUx Code Protection Range 0 Lower Bound Register resetvalue={Application Reset:0x0} 0 32 0 4294967295 LOWBND CPRy Lower Boundary Address LOWBND 5 31 read-write CPRy_U CPUx Code Protection Range 0 Upper Bound Register resetvalue={Application Reset:0x0} 4 32 0 4294967295 UPPBND CPR0 m Upper Boundary Address UPPBND 5 31 read-write TPS TPS 58368 CON CPUx Temporal Protection System Control Register resetvalue={Application Reset:0x0} 0 32 0 4294967295 TEXP0 Timer0 Expired Flag TEXP0. Set when the corresponding timer expires. Cleared on any write to the TIMER0 register. 0 0 read-only TEXP1 Timer1 Expired Flag TEXP1. Set when the corresponding timer expires. Cleared on any write to the TIMER1 register. 1 1 read-only TEXP2 Timer1 Expired Flag TEXP2. Set when the corresponding timer expires. Cleared on any write to the TIMER1 register. 2 2 read-only TTRAP Temporal Protection Trap TTRAP. If set indicates that a TAE trap has been requested. Any subsequent TAE traps are disabled. A write clears the flag and re enables TAE traps. 16 16 read-only 3 4 TIMER[%s] CPUx Temporal Protection System Timer Register 0 resetvalue={Application Reset:0x0} 4 32 0 4294967295 Timer Temporal Protection Timer Timer. Writing zero de activates the Timer. Writing a non zero value starts the Timer. Any write clears the corresponding TPS CON.TEXP flag. Read returns the current Timer value. 0 31 read-write TPS_EXTIM TPS EXTIM 58432 ENTRY_LVAL CPUx Exception Entry Timer Load Value resetvalue={Application Reset:0x0} 0 32 0 4294967295 ENTRY_LVAL Exception Entry Timer Load value ENTRY LVAL. Value loaded into the exception entry timer on detection of an enabled exception. Bits 3 0 are constrained to be 0 4 11 read-write ENTRY_CVAL CPUx Exception Entry Timer Current Value resetvalue={Application Reset:0x0} 4 32 0 4294967295 ENTRY_CVAL Exception Entry Timer Current Value ENTRY CVAL. Current value of the exception entry timer. 0 11 read-only EXIT_LVAL CPUx Exception Exit Timer Load Value resetvalue={Application Reset:0x0} 8 32 0 4294967295 EXIT_LVAL Exception Exit Timer Load value EXIT LVAL. Value loaded into the exception exit timer on detection of an enabled exception. Bits 3 0 are constrained to be 0 4 23 read-write EXIT_CVAL CPUx Exception Exit Timer Current Value resetvalue={Application Reset:0x0} 12 32 0 4294967295 EXIT_CVAL Exception Exit Timer Current Value EXIT CVAL. Current value of the exception exit timer. 0 23 read-only CLASS_EN CPUx Exception Timer Class Enable Register resetvalue={Application Reset:0x0} 16 32 0 4294967295 EXTIM_CLASS_EN Exception Timer Class Enables EXTIM CLASS EN. Trap Class enables for exception timer. 0 7 read-write STAT CPUx Exception Timer Status Register resetvalue={Application Reset:0x0} 20 32 0 4294967295 EXIT_TIN Exception Exit Timer TIN EXIT TIN. Exception Exit Timer TIN of triggering trap. 0 7 read-write EXIT_CLASS Exception Exit Timer Class EXIT CLASS. Exception exit Timer Class of triggering trap. 8 10 read-write EXIT_AT Exception Exit Timer Alarm Triggered EXIT AT. Exception Exit Timer Alarm triggered sticky bit. Alarm triggered since last cleared. 15 15 read-only ENTRY_TIN Exception Entry Timer TIN ENTRY TIN. Exception Entry Timer TIN of triggering trap. 16 23 read-write ENTRY_CLASS Exception Entry Timer Class ENTRY CLASS. Exception Entry Timer Class of triggering trap. 24 26 read-write ENTRY_AT Exception Entry Timer Alarm Triggered ENTRY AT. Exception Entry Timer Alarm triggered sticky bit. Alarm triggered since last cleared. 31 31 read-only FCX CPUx Exception Timer FCX Register resetvalue={Application Reset:0x0} 24 32 0 4294967295 EXIT_FCX Exception Exit Timer FCX EXIT FCX. Exception Exit Timer FCX of triggering trap. 0 19 read-only FPU_TRAP FPU TRAP 40960 CON CPUx Trap Control Register resetvalue={Application Reset:0x0} 0 32 0 4294967295 TST Trap Status TST 0 0 read-only Const_00 0 No instruction captured. The next enabled exception will cause the exceptional instruction to be captured. 0 Const_11 1 Instruction captured. No further enabled exceptions will be captured until TST is cleared. 1 TCL Trap Clear TCL. Read always reads as 0. 1 1 write-only Const_00 0 No effect. 0 Const_11 1 Clears the trapped instruction TST will be negated . 1 RM Captured Rounding Mode RM. The rounding mode of the captured instruction. Only valid when TST is asserted. Note that this is the rounding mode supplied to the FPU for the exceptional instruction. UPDFL instructions may cause a trap and change the rounding mode. In this case the RM bits capture the input rounding mode 8 9 read-only FXE FX Trap Enable FXE. When set an instruction generating an FX exception will trigger a trap. 18 18 read-write FUE FU Trap Enable FUE. When set an instruction generating an FU exception will trigger a trap. 19 19 read-write FZE FZ Trap Enable FZE. When set an instruction generating an FZ exception will trigger a trap. 20 20 read-write FVE FV Trap Enable FVE. When set an instruction generating an FV exception will trigger a trap. 21 21 read-write FIE FI Trap Enable FIE. When set an instruction generating an FI exception will trigger a trap. 22 22 read-write FX Captured FX FX. Asserted if the captured instruction asserted FX. Only valid when TST is asserted. 26 26 read-only FU Captured FU FU. Asserted if the captured instruction asserted FU. Only valid when TST is asserted. 27 27 read-only FZ Captured FZ FZ. Asserted if the captured instruction asserted FZ. Only valid when TST is asserted 28 28 read-only FV Captured FV FV. Asserted if the captured instruction asserted FV. Only valid when TST is asserted 29 29 read-only FI Captured FI FI. Asserted if the captured instruction asserted FI. Only valid when TST is asserted 30 30 read-only PC CPUx Trapping Instruction Program Counter Register resetvalue={Application Reset:0x0} 4 32 0 4294967295 PC Captured Program Counter PC. The program counter virtual address of the captured instruction. Only valid when FPU TRAP CON.TST is asserted. 0 31 read-only OPC CPUx Trapping Instruction Opcode Register resetvalue={Application Reset:0x0} 8 32 0 4294967295 OPC Captured Opcode OPC. The secondary opcode of the captured instruction. When FPU TRAP OPC.FMT 0 only bits 3 0 are defined. OPC is valid only when FPU TRAP CON.TST is asserted. 0 7 read-only FMT Captured Instruction Format FMT. The format of the captured instruction s opcode. Only valid when FPU TRAP CON.TST is asserted. 8 8 read-only Const_00 0 RRR 0 Const_11 1 RR 1 DREG Captured Destination Register DREG. The destination register of the captured instruction. ... Only valid when FPU TRAP CON.TST is asserted. 16 19 read-only Const_00 0 Data general purpose register 0. 0 Const_1515 F Data general purpose register 15. 15 SRC1 CPUx Trapping Instruction Operand Register resetvalue={Application Reset:0x0} 16 32 0 4294967295 SRC1 Captured SRC1 Operand SRC1. The SRC1 operand of the captured instruction. Only valid when FPU TRAP CON.TST is asserted. 0 31 read-only SRC2 CPUx Trapping Instruction Operand Register resetvalue={Application Reset:0x0} 20 32 0 4294967295 SRC2 Captured SRC2 Operand SRC2. The SRC2 operand of the captured instruction. Only valid when FPU TRAP CON.TST is asserted. 0 31 read-only SRC3 CPUx Trapping Instruction Operand Register resetvalue={Application Reset:0x0} 24 32 0 4294967295 SRC3 Captured SRC3 Operand SRC3. The SRC3 operand of the captured instruction. Only valid when FPU TRAP CON.TST is asserted. 0 31 read-only 8 8 TR[%s] Trigger 61440 TRiEVT CPUx Trigger Event 0 resetvalue={Debug Reset:0x0} 0 32 0 4294967295 EVTA Event Associated EVTA. Specifies the Debug Action associated with the Debug Event 0 2 read-write Const_00 000 BOD 0 Disabled. BOD 1 Disabled. 0 Const_11 001 BOD 0 Pulse BRKOUT Signal. BOD 1 None. 1 Const_22 010 BOD 0 Halt and pulse BRKOUT Signal. BOD 1 Halt. 2 Const_33 011 BOD 0 Breakpoint trap and pulse BRKOUT Signal. BOD 1 Breakpoint trap. 3 Const_44 100 BOD 0 Breakpoint interrupt 0 and pulse BRKOUT Signal. BOD 1 Breakpoint interrupt 0. 4 Const_55 101 BOD 0 If implemented breakpoint interrupt 1 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 1. If not implemented None. 5 Const_66 110 BOD 0 If implemented breakpoint interrupt 2 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 2. If not implemented None. 6 Const_77 111 BOD 0 If implemented breakpoint interrupt 3 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 3. If not implemented None. 7 BBM Break Before Make BBM or Break After Make BAM Selection BBM. Code triggers BBM or BAM selection. Data access and data code combination access triggers can only create BAM Debug Events. When these triggers occur TRnEVT.BBM is ignored. 3 3 read-write Const_00 0 Code only triggers Break After Make BAM . 0 Const_11 1 Code only triggers Break Before Make BBM . 1 BOD Breakout Disable BOD 4 4 read-write Const_00 0 BRKOUT signal asserted according to the action specified in the EVTA field. 0 Const_11 1 BRKOUT signal not asserted. This takes priority over any assertion generated by the EVTA field. 1 SUSP CDC Suspend Out Signal State SUSP. Value to be assigned to the CDC suspend out signal when the Debug Event is raised. 5 5 read-write CNT Counter CNT. When this event occurs adjust the control of the performance counters in task mode as follows 6 7 read-write Const_00 00 No change. 0 Const_11 01 Start the performance counters. 1 Const_22 10 Stop the performance counters. 2 Const_33 11 Toggle the performance counter control i.e. start it if it is currently stopped stop it if it is currently running . 3 TYP Input Selection TYP 12 12 read-write Const_00 0 Address 0 Const_11 1 PC 1 RNG Compare Type RNG. Once an even numbered comparator has been set to range the EVTR settings of its associated upper neighbour will be ignored. 13 13 read-write Const_11 1 Range 1 Const_00 0 Equality 0 ASI_EN Enable ASI Comparison ASI EN 15 15 read-write Const_00 0 No ASI comparison performed. Debug Trigger is valid for all processes. 0 Const_11 1 Enable ASI comparison. Debug Events are only triggered when the current process ASI matches TRnEVT.ASI. 1 ASI Address Space Identifier ASI. The ASI of the Debug Trigger process. 16 20 read-write AST Address Store AST. Used in conjunction with TYP 0 27 27 read-write ALD Address Load ALD. Used in conjunction with TYP 0 28 28 read-write TRiADR CPUx Trigger Address 0 resetvalue={Debug Reset:0x0} 4 32 0 4294967295 ADDR Comparison Address ADDR. For PC comparison bit 0 is always zero. 0 31 read-write SMACON CPUx SIST Mode Access Control Register resetvalue={Application Reset:0x0} 36876 32 0 4294967295 IODT In Order Data Transactions IODT 24 24 read-write Const_00 0 Normal operation Non dependent loads bypass stores. 0 Const_11 1 In order operation Loads always flush preceding stores processor store buffer disabled. 1 DIEAR CPUx Data Integrity Error Address Register resetvalue={Application Reset:0x0} 36896 32 0 4294967295 TA Transaction Address TA. Physical address being accessed by operation that encountered data integrity error. 0 31 read-only DIETR CPUx Data Integrity Error Trap Register resetvalue={Application Reset:0x0} 36900 32 0 4294967295 IED Integrity Error Detected IED 0 0 read-write Const_00 0 Write Clear IED bit re enable DIETR and DIEAR update. Read No data integrity error condition occurred 0 Const_11 1 Write No Effect. Read Data integrity error condition detected. DIETR and DIEAR contents valid further DIETR and DIEAR updates disabled.. 1 IE_T Integrity Error Tag Memory IE T 1 1 read-only IE_C Integrity Error Cache Memory IE C 2 2 read-only IE_S Integrity Error Scratchpad Memory IE S 3 3 read-only IE_BI Integrity Error Bus Interface IE BI 4 4 read-only E_INFO Error Information E INFO. If IE BS 1 Bus Master Tag ID of requesting masterIf IE C 1 Cache way. 5 10 read-only IE_UNC Dual Bit Error Detected IE UNC 11 11 read-only IE_SP Safety Protection Error Detected IE SP 12 12 read-only IE_BS Bus Slave Access Indicator IE BS 13 13 read-only IE_DLMU Integrity Error DLMU IE DLMU 14 14 read-only IE_LPB Integrity Error Local Pflash Bank IE LPB 15 15 read-only IE_MTMV Memory Test Mode Violation detected IE MTMV 16 16 read-only PIEAR CPUx Program Integrity Error Address Register resetvalue={Application Reset:0x0} 37392 32 0 4294967295 TA Transaction Address TA. Physical address being accessed by operation that encountered program integrity error. 0 31 read-only PIETR CPUx Program Integrity Error Trap Register resetvalue={Application Reset:0x0} 37396 32 0 4294967295 IED Integrity Error Detected IED 0 0 read-write Const_00 0 Write Clear IED bit re enable PIETR and PIEAR update. Read No data integrity error condition occurred 0 Const_11 1 Write No Effect. Read Data integrity error condition detected. PIETR and PIEAR contents valid further PIETR and PIEAR updates disabled.. 1 IE_T Integrity Error TAG Memory IE T 1 1 read-only IE_C Integrity Error Cache Memory IE C 2 2 read-only IE_S Integrity Error Scratchpad Memory IE S 3 3 read-only IE_BI Integrity Error Bus Interface IE BI 4 4 read-only E_INFO Error Information E INFO. If IE BS 1 Bus Master Tag ID of requesting masterIf IE C 1 Cache way. 5 10 read-only IE_UNC Integrity Error Uncorrectable Error Detected IE UNC 11 11 read-only IE_SP Safety Protection Error Detected IE SP 12 12 read-only IE_BS Bus Slave Access Indicator IE BS 13 13 read-only IE_ADDR Address Phase error detected at SRI slave interface IE ADDR 14 14 read-only IE_LPB Integrity Error Local Pflash bank IE LPB 15 15 read-only IE_MTMV Memory Test Mode Violation detected IE MTMV 16 16 read-only TASK_ASI CPUx Task Address Space Identifier Register resetvalue={Application Reset:0x1F} 32772 32 31 4294967295 ASI Address Space Identifier ASI. The ASI register contains the Address Space Identifier of the current process. 0 4 read-write PMA0 CPUx Data Access CacheabilityRegister resetvalue={Application Reset:0x300} 33024 32 768 4294967295 DAC Data Access Cacheability Segments FHto 0H DAC. Note segments F H E H D H and A H are constrained to be non cacheable 0 15 read-write PMA1 CPUx Code Access CacheabilityRegister resetvalue={Application Reset:0x300} 33028 32 768 4294967295 CAC Code Access Cacheability Segments FH 0H CAC. Note Segments F H E H C H A H are constrained to be non cacheable 0 15 read-write PMA2 CPUx Peripheral Space Identifier register resetvalue={Application Reset:0x0C000} 33032 32 49152 4294967295 PSI Peripheral Space Identifier Segments FH 0H PSI 0 15 read-only COMPAT CPUx Compatibility Control Register resetvalue={Application Reset:0x0FFFFFFFF} 37888 32 4294967295 4294967295 RM Rounding Mode Compatibility RM 3 3 read-write Const_00 0 PSW.RM not restored by RET. 0 Const_11 1 PSW.RM restored by RET TC1.3 behavior . 1 SP SYSCON Safety Protection Mode Compatibility SP 4 4 read-write Const_00 0 SYSCON 31 1 safety endinit protected. 0 Const_11 1 SYSCON 31 1 not safety endinit protected TC1.3 behavior . 1 PCXI CPUx Previous Context Information Register resetvalue={Application Reset:0x0} 65024 32 0 4294967295 PCXO Previous Context Pointer Offset Field PCXO. The PCXO and PCXS fields form the pointer PCX which points to the CSA of the previous context. 0 15 read-write PCXS Previous Context Pointer Segment Address PCXS. Contains the segment address portion of the PCX. This field is used in conjunction with the PCXO field. 16 19 read-write UL Upper or Lower Context Tag UL. Identifies the type of context saved. If the type does not match the type expected when a context restore operation is performed a trap is generated. 20 20 read-write Const_00 0 Lower Context 0 Const_11 1 Upper Context 1 PIE Previous Interrupt Enable PIE. Indicates the state of the interrupt enable bit ICR.IE for the interrupted task. 21 21 read-write PCPN Previous CPU Priority Number PCPN. Contains the priority level number of the interrupted task. 22 29 read-write PSW CPUx Program Status Word resetvalue={Application Reset:0x0B80} 65028 32 2944 4294967295 CDC Call Depth Counter CDC. Consists of two variable width subfields. The first subfield consists of a string of zero or more initial 1 bits terminated by the first 0 bit. The remaining bits form the second subfield CDC.COUNT which constitutes the Call Depth Count value. The count value is incremented on each Call and is decremented on a Return. 0cccccc B 6 bit counter trap on overflow. 10ccccc B 5 bit counter trap on overflow. 110cccc B 4 bit counter trap on overflow. 1110ccc B 3 bit counter trap on overflow. 11110cc B 2 bit counter trap on overflow. 111110c B 1 bit counter trap on overflow. 1111110 B Trap every call Call Trace mode . 1111111 B Disable Call Depth Counting. When the call depth count CDC.COUNT overflows a trap CDO is generated. Setting the CDC to 1111110 B allows no bits for the counter and causes every call to be trapped. This is used for Call Depth Tracing. Setting the CDC to 1111111 B disables Call Depth Counting. 0 6 read-write CDE Call Depth Count Enable CDE. Enables call depth counting provided that the PSW.CDC mask field is not all set to 1. If PSW.CDC 1111111 B call depth counting is disabled regardless of the setting on the PSW.CDE bit. 7 7 read-write Const_00 0 Call depth counting is temporarily disabled. It is automatically re enabled after execution of the next Call instruction. 0 Const_11 1 Call depth counting is enabled. 1 IS Interrupt Stack Control IS. Determines if the current execution thread is using the shared global interrupt stack or a user stack. 9 9 read-write Const_00 0 User Stack. If an interrupt is taken when the IS bit is 0 then the stack pointer register is loaded from the ISP register before execution starts at the first instruction of the Interrupt Service Routine ISR . 0 Const_11 1 Shared Global Stack. If an interrupt is taken when the PSW.IS bit is 1 then the current value of the stack pointer is used by the Interrupt Service Routine ISR . 1 IO Access Privilege Level Control I O Privilege IO. Determines the access level to special function registers and peripheral devices. 10 11 read-write Const_00 00 User 0 Mode No peripheral access. Access to memory regions with the peripheral space attribute are prohibited and results in a PSE or MPP trap. This access level is given to tasks that need not directly access peripheral devices. Tasks at this level do not have permission to enable or disable interrupts. 0 Const_11 01 User 1 Mode Regular peripheral access. Enables access to common peripheral devices that are not specially protected including read write access to serial I O ports read access to timers and access to most I O status registers. Tasks at this level may disable interrupts. 1 Const_22 10 Supervisor Mode Enables access to all peripheral devices. It enables read write access to core registers and protected peripheral devices. Tasks at this level may disable interrupts. 2 S Safe Task Identifier S 14 14 read-write USB User Status Bits USB. The eight most significant bits of the PSW are designated as User Status Bits. These bits may be set or cleared as side effects of instruction execution. Refer to the TriCore Architecture manual for details. 24 31 read-write PC CPUx Program Counter resetvalue={Application Reset:0x0} 65032 32 0 0 PC Program Counter PC 1 31 read-write SYSCON CPUx System Configuration Register resetvalue={Application Reset:0x0,Application Reset:0x0} 65044 32 0 0 FCDSF Free Context List Depleted Sticky Flag FCDSF. This sticky bit indicates that a FCD Free Context List Depleted trap occurred since the bit was last cleared by software. 0 0 read-write Const_00 0 No FCD trap occurred since the last clear. 0 Const_11 1 An FCD trap occurred since the last clear. 1 PROTEN Memory Protection Enable PROTEN. Enables the memory protection system. Memory protection is controlled through the memory protection register sets. Note Initialize the protection register sets prior to setting PROTEN to one. 1 1 read-write Const_00 0 Memory Protection is disabled. 0 Const_11 1 Memory Protection is enabled. 1 TPROTEN Temporal Protection Enable TPROTEN. Enable the Temporal Protection system. 2 2 read-write Const_00 0 Temporal Protection is disabled. 0 Const_11 1 Temporal Protection is enabled. 1 IS Initial State Interrupt IS. of PSW.S bit in interrupt handle 3 3 read-write TS Initial State Trap TS. of PSW.S bit in trap handle 4 4 read-write ESDIS Emulator Space Disable. Disable the Emulator Space system 8 8 read-write U1_IED User 1 Instruction execution disable U1 IED. Disable the execution of User 1 mode instructions in User 1 IO mode. Disables User 1 ability to enable and disable interrupts. 16 16 read-write U1_IOS User 1 Peripheral access as supervisor U1 IOS. Allow User 1 mode tasks to access peripherals as if in Supervisor mode. Enables User 1 access to all peripheral registers. 17 17 read-write BHALT Boot Halt BHALT 24 24 read-write Const_00 0 Core is not in boot halt. 0 Const_11 1 Core is in boot halt write to 0 will exit 1 CPU_ID CPUx Identification Register TC1.6.2P resetvalue={Application Reset:0x0C0C021} 65048 32 12632097 4294967295 MOD_REV Revision Number MOD REV 0 7 read-only Const_3232 20 Reset value 32 MOD_32B 32 Bit Module Enable MOD 32B 8 15 read-only Const_192192 C0 A value of C0 H in this field indicates a 32 bit module with a 32 bit module ID register. 192 MOD Module Identification Number MOD 16 31 read-only Const_192192 00C0 For module identification. 192 CORE_ID CPUx Core Identification Register resetvalue={Application Reset:0x0} 65052 32 0 4294967288 CORE_ID Core Identification Number CORE ID. The identification number of the core. 0 2 read-only BIV CPUx Base Interrupt Vector Table Pointer resetvalue={Application Reset:0x0} 65056 32 0 4294967295 VSS Vector Spacing Select VSS. 0 32 byte vector spacing. 1 8 Byte vector spacing. 0 0 read-write BIV Base Address of Interrupt Vector Table BIV. The address in the BIV register must be aligned to an even byte address halfword address . Because of the simple ORing of the left shifted priority number and the contents of the BIV register the alignment of the base address of the vector table must be to a power of two boundary dependent on the number of interrupt entries used. For the full range of 256 interrupt entries an alignment to an 8 KByte boundary is required. If fewer sources are used the alignment requirements are correspondingly relaxed. 1 31 read-write BTV CPUx Base Trap Vector Table Pointer resetvalue={Application Reset:0x0A0000100} 65060 32 2684354816 4294967295 BTV Base Address of Trap Vector Table BTV. The address in the BTV register must be aligned to an even byte address halfword address . Also due to the simple ORing of the left shifted trap identification number and the contents of the BTV register the alignment of the base address of the vector table must be to a power of two boundary. There are eight different trap classes resulting in Trap Classes from 0 to 7. The contents of BTV should therefore be set to at least a 256 byte boundary 8 Trap Classes 8 word spacing . 1 31 read-write ISP CPUx Interrupt Stack Pointer resetvalue={Application Reset:0x100} 65064 32 256 4294967295 ISP Interrupt Stack Pointer ISP 0 31 read-write ICR CPUx Interrupt Control Register resetvalue={Application Reset:0x0} 65068 32 0 4294967295 CCPN Current CPU Priority Number CCPN. The Current CPU Priority Number CCPN bit field indicates the current priority level of the CPU. It is automatically updated by hardware on entry or exit of Interrupt Service Routines ISRs and through the execution of a BISR instruction. CCPN can also be updated through an MTCR instruction. 0 7 read-write IE Global Interrupt Enable Bit IE. The interrupt enable bit globally enables the CPU service request system. Whether a service request is delivered to the CPU depends on the individual Service Request Enable Bits SRE in the SRNs and the current state of the CPU. ICR.IE is automatically updated by hardware on entry and exit of an Interrupt Service Routine ISR . ICR.IE is cleared to 0 when an interrupt is taken and is restored to the previous value when the ISR executes an RFE instruction to terminate itself. ICR.IE can also be updated through the execution of the ENABLE DISABLE MTCR and BISR instructions. 15 15 read-write Const_00 0 Interrupt system is globally disabled 0 Const_11 1 Interrupt system is globally enabled 1 PIPN Pending Interrupt Priority Number PIPN. A read only bit field that is updated by the ICU at the end of each interrupt arbitration process. It indicates the priority number of the pending service request. ICR.PIPN is set to 0 when no request is pending and at the beginning of each new arbitration process. ... 16 23 read-only Const_00 00 No valid pending request. 0 Const_11 01 Request pending lowest priority. 1 Const_255255 FF Request pending highest priority. 255 FCX CPUx Free CSA List Head Pointer resetvalue={Application Reset:0x0} 65080 32 0 4294967295 FCXO FCX Offset Address Field FCXO. The FCXO and FCXS fields together form the FCX pointer which points to the next available CSA. 0 15 read-write FCXS FCX Segment Address Field FCXS. Used in conjunction with the FCXO field. 16 19 read-write LCX CPUx Free CSA List Limit Pointer resetvalue={Application Reset:0x0} 65084 32 0 4294967295 LCXO LCX Offset Field LCXO. The LCXO and LCXS fields form the pointer LCX which points to the last available CSA. 0 15 read-write LCXS LCX Segment Address LCXS. This field is used in conjunction with the LCXO field. 16 19 read-write CUS_ID CPUx Customer ID register resetvalue={Application Reset:0x0} 65104 32 0 4294967288 CID Customer ID CID. See CROSSREFERENCE for the relation between CUS ID and CORE ID for each derivative 0 2 read-only 16 4 Dy[%s] CPUx Data General Purpose Register 0 resetvalue={Application Reset:0x0} 65280 32 0 0 DATA Data Register DATA. General purpose registers 0 31 read-write 16 4 Ay[%s] CPUx Address General Purpose Register 0 resetvalue={Application Reset:0x0} 65408 32 0 0 ADDR Address Register ADDR. General purpose registers 0 31 read-write CPXE_0 CPUx Code Protection Execute Enable Register Set 3 resetvalue={Application Reset:0x0} 57344 32 0 4294967295 XE_n Execute Enable Range select XE n 0 9 read-write Const_00 0 Code Protection Range n not enabled for execution 0 Const_11 1 Code Protection Range n enabled for execution 1 CPXE_1 CPUx Code Protection Execute Enable Register Set 3 resetvalue={Application Reset:0x0} 57348 32 0 4294967295 XE_n Execute Enable Range select XE n 0 9 read-write Const_00 0 Code Protection Range n not enabled for execution 0 Const_11 1 Code Protection Range n enabled for execution 1 CPXE_2 CPUx Code Protection Execute Enable Register Set 3 resetvalue={Application Reset:0x0} 57352 32 0 4294967295 XE_n Execute Enable Range select XE n 0 9 read-write Const_00 0 Code Protection Range n not enabled for execution 0 Const_11 1 Code Protection Range n enabled for execution 1 CPXE_3 CPUx Code Protection Execute Enable Register Set 3 resetvalue={Application Reset:0x0} 57356 32 0 4294967295 XE_n Execute Enable Range select XE n 0 9 read-write Const_00 0 Code Protection Range n not enabled for execution 0 Const_11 1 Code Protection Range n enabled for execution 1 DPRE_0 CPUx Data Protection Read Enable Register Set 3 resetvalue={Application Reset:0x0} 57360 32 0 4294967295 RE_n Read Enable Range Select RE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data read 0 Const_11 1 Data Protection Range n enabled for data read 1 DPRE_1 CPUx Data Protection Read Enable Register Set 3 resetvalue={Application Reset:0x0} 57364 32 0 4294967295 RE_n Read Enable Range Select RE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data read 0 Const_11 1 Data Protection Range n enabled for data read 1 DPRE_2 CPUx Data Protection Read Enable Register Set 3 resetvalue={Application Reset:0x0} 57368 32 0 4294967295 RE_n Read Enable Range Select RE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data read 0 Const_11 1 Data Protection Range n enabled for data read 1 DPRE_3 CPUx Data Protection Read Enable Register Set 3 resetvalue={Application Reset:0x0} 57372 32 0 4294967295 RE_n Read Enable Range Select RE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data read 0 Const_11 1 Data Protection Range n enabled for data read 1 DPWE_0 CPUx Data Protection Write Enable Register Set 3 resetvalue={Application Reset:0x0} 57376 32 0 4294967295 WE_n Write Enable Range Select WE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data write 0 Const_11 1 Data Protection Range n enabled for data write 1 DPWE_1 CPUx Data Protection Write Enable Register Set 3 resetvalue={Application Reset:0x0} 57380 32 0 4294967295 WE_n Write Enable Range Select WE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data write 0 Const_11 1 Data Protection Range n enabled for data write 1 DPWE_2 CPUx Data Protection Write Enable Register Set 3 resetvalue={Application Reset:0x0} 57384 32 0 4294967295 WE_n Write Enable Range Select WE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data write 0 Const_11 1 Data Protection Range n enabled for data write 1 DPWE_3 CPUx Data Protection Write Enable Register Set 3 resetvalue={Application Reset:0x0} 57388 32 0 4294967295 WE_n Write Enable Range Select WE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data write 0 Const_11 1 Data Protection Range n enabled for data write 1 CPXE_4 CPUx Code Protection Execute Enable Register Set 5 resetvalue={Application Reset:0x0} 57408 32 0 4294967295 XE_n Execute Enable Range select XE n 0 9 read-write Const_00 0 Code Protection Range n not enabled for execution 0 Const_11 1 Code Protection Range n enabled for execution 1 CPXE_5 CPUx Code Protection Execute Enable Register Set 5 resetvalue={Application Reset:0x0} 57412 32 0 4294967295 XE_n Execute Enable Range select XE n 0 9 read-write Const_00 0 Code Protection Range n not enabled for execution 0 Const_11 1 Code Protection Range n enabled for execution 1 DPRE_4 CPUx Data Protection Read Enable Register Set 5 resetvalue={Application Reset:0x0} 57424 32 0 4294967295 RE_n Read Enable Range Select RE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data read 0 Const_11 1 Data Protection Range n enabled for data read 1 DPRE_5 CPUx Data Protection Read Enable Register Set 5 resetvalue={Application Reset:0x0} 57428 32 0 4294967295 RE_n Read Enable Range Select RE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data read 0 Const_11 1 Data Protection Range n enabled for data read 1 DPWE_4 CPUx Data Protection Write Enable Register Set 5 resetvalue={Application Reset:0x0} 57440 32 0 4294967295 WE_n Write Enable Range Select WE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data write 0 Const_11 1 Data Protection Range n enabled for data write 1 DPWE_5 CPUx Data Protection Write Enable Register Set 5 resetvalue={Application Reset:0x0} 57444 32 0 4294967295 WE_n Write Enable Range Select WE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data write 0 Const_11 1 Data Protection Range n enabled for data write 1 CCTRL CPUx Counter Control resetvalue={Debug Reset:0x0} 64512 32 0 4294967295 CM Counter Mode CM 0 0 read-write Const_00 0 Normal Mode. 0 Const_11 1 Task Mode. 1 CE Count Enable CE 1 1 read-write Const_00 0 Disable the counters CCNT ICNT M1CNT M2CNT M3CNT. 0 Const_11 1 Enable the counters CCNT ICNT M1CNT M2CNT M3CNT. 1 M1 M1CNT Configuration M1 2 4 read-write M2 M2CNT Configuration M2 5 7 read-write M3 M3CNT Configuration M3 8 10 read-write CCNT CPUx CPU Clock Cycle Count resetvalue={Debug Reset:0x0} 64516 32 0 4294967295 CountValue Count Value CountValue. Current Count of the CPU Clock Cycles. 0 30 read-write SOvf Sticky Overflow Bit SOvf. This bit is set by hardware when count value 30 0 31 h7FFF FFFF. It can only be cleared by software. 31 31 read-write ICNT CPUx Instruction Count resetvalue={Debug Reset:0x0} 64520 32 0 4294967295 CountValue Count Value CountValue. Count of the Instructions Executed. 0 30 read-write SOvf Sticky Overflow Bit SOvf. This bit is set by hardware when count value 30 0 31 h7FFF FFFF. It can only be cleared by software. 31 31 read-write M1CNT CPUx Multi Count Register 1 resetvalue={Debug Reset:0x0} 64524 32 0 4294967295 CountValue Count Value CountValue. Count of the Selected Event. 0 30 read-write SOvf Sticky Overflow Bit SOvf. This bit is set by hardware when count value 30 0 31 h7FFF FFFF. It can only be cleared by software. 31 31 read-write M2CNT CPUx Multi Count Register 2 resetvalue={Debug Reset:0x0} 64528 32 0 4294967295 CountValue Count Value CountValue. Count of the Selected Event. 0 30 read-write SOvf Sticky Overflow Bit SOvf. This bit is set by hardware when count value 30 0 31 h7FFF FFFF. It can only be cleared by software. 31 31 read-write M3CNT CPUx Multi Count Register 3 resetvalue={Debug Reset:0x0} 64532 32 0 4294967295 CountValue Count Value CountValue. Count of the Selected Event. 0 30 read-write SOvf Sticky Overflow Bit SOvf. This bit is set by hardware when count value 30 0 31 h7FFF FFFF. It can only be cleared by software. 31 31 read-write DBGSR CPUx Debug Status Register resetvalue={Debug Reset:0x0} 64768 32 0 4294967295 DE Debug Enable DE. Determines whether the CDC is enabled or not. 0 0 read-only Const_00 0 The CDC is disabled. 0 Const_11 1 The CDC is enabled. 1 HALT CPU Halt Request Status Field HALT. HALT can be set or cleared by software. HALT 0 is the actual Halt bit. HALT 1 is a mask bit to specify whether or not HALT 0 is to be updated on a software write. HALT 1 is always read as 0. HALT 1 must be set to 1 in order to update HALT 0 by software R read W write . 1 2 read-write Const_00 00 R CPU running. W HALT 0 unchanged. 0 Const_11 01 R CPU halted. W HALT 0 unchanged. 1 Const_22 10 R Not Applicable. W reset HALT 0 . 2 Const_33 11 R Not Applicable. W If DBGSR.DE 1 The CDC is enabled set HALT 0 . If DBGSR.DE 0 The CDC is not enabled HALT 0 is left unchanged. 3 SIH Suspend in Halt SIH. State of the Suspend In signal. 3 3 read-only Const_00 0 The Suspend In signal is negated. The CPU is not in Halt Mode except when the Halt mechanism is set following a Debug Event or a write to DBGSR.HALT . 0 Const_11 1 The Suspend In signal is asserted. The CPU is in Halt Mode. 1 SUSP Current State of the Core Suspend Out Signal SUSP 4 4 read-write Const_00 0 Core suspend out inactive. 0 Const_11 1 Core suspend out active. 1 PREVSUSP Previous State of Core Suspend Out Signal PREVSUSP. Updated when a Debug Event causes a hardware update of DBGSR.SUSP. This field is not updated for writes to DBGSR.SUSP. 6 6 read-only Const_00 0 Previous core suspend out inactive. 0 Const_11 1 Previous core suspend out active. 1 PEVT Posted Event PEVT 7 7 read-write Const_00 0 No posted event. 0 Const_11 1 Posted event. 1 EXEVT CPUx External Event Register resetvalue={Debug Reset:0x0} 64776 32 0 4294967295 EVTA Event Associated EVTA. Specifies the Debug Action associated with the Debug Event 0 2 read-write Const_00 000 BOD 0 Disabled. BOD 1 Disabled. 0 Const_11 001 BOD 0 Pulse BRKOUT Signal. BOD 1 None. 1 Const_22 010 BOD 0 Halt and pulse BRKOUT Signal. BOD 1 Halt. 2 Const_33 011 BOD 0 Breakpoint trap and pulse. BRKOUT Signal. BOD 1 Breakpoint trap. 3 Const_44 100 BOD 0 Breakpoint interrupt 0 and pulse BRKOUT Signal. BOD 1 Breakpoint interrupt 0. 4 Const_55 101 BOD 0 If implemented breakpoint interrupt 1 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 1. If not implemented None. 5 Const_66 110 BOD 0 If implemented breakpoint interrupt 2 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 2. If not implemented None. 6 Const_77 111 BOD 0 If implemented breakpoint interrupt 3 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 3. If not implemented None. 7 BBM Break Before Make BBM or Break After Make BAM Selection BBM 3 3 read-write Const_00 0 Break after make BAM . 0 Const_11 1 Break before make BBM . 1 BOD Breakout Disable BOD 4 4 read-write Const_00 0 BRKOUT signal asserted according to the Debug Action specified in the EVTA field. 0 Const_11 1 BRKOUT signal not asserted. This takes priority over any assertion generated by the EVTA field. 1 SUSP CDC Suspend Out Signal State SUSP. Value to be assigned to the CDC suspend out signal when the Debug Event is raised. 5 5 read-write CNT Counter CNT. When this event occurs adjust the control of the performance counters in task mode as follows 6 7 read-write Const_00 00 No change. 0 Const_11 01 Start the performance counters. 1 Const_22 10 Stop the performance counters. 2 Const_33 11 Toggle the performance counter control i.e. start it if it is currently stopped stop it if it is currently running . 3 CREVT CPUx Core Register Access Event resetvalue={Debug Reset:0x0} 64780 32 0 4294967295 EVTA Event Associated EVTA. Debug Action associated with the Debug Event 0 2 read-write Const_00 000 BOD 0 Disabled. BOD 1 Disabled. 0 Const_11 001 BOD 0 Pulse BRKOUT Signal. BOD 1 None. 1 Const_22 010 BOD 0 Halt and pulse BRKOUT Signal. BOD 1 Halt. 2 Const_33 011 BOD 0 Breakpoint trap and pulse BRKOUT Signal. BOD 1 Breakpoint trap. 3 Const_44 100 BOD 0 Breakpoint interrupt 0 and pulse BRKOUT Signal. BOD 1 Breakpoint interrupt 0. 4 Const_55 101 BOD 0 If implemented breakpoint interrupt 1 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 1. If not implemented None. 5 Const_66 110 BOD 0 If implemented breakpoint interrupt 2 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 2. If not implemented None. 6 Const_77 111 BOD 0 If implemented breakpoint interrupt 3 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 3. If not implemented None. 7 BBM Break Before Make BBM or Break After Make BAM Selection BBM 3 3 read-write Const_00 0 Break after make BAM . 0 Const_11 1 Break before make BBM . 1 BOD Breakout Disable BOD 4 4 read-write Const_00 0 BRKOUT signal asserted according to the action specified in the EVTA field. 0 Const_11 1 BRKOUT signal not asserted. This takes priority over any assertion generated by the EVTA field. 1 SUSP CDC Suspend Out Signal State SUSP. Value to be assigned to the CDC suspend out signal when the Debug Event is raised. 5 5 read-write CNT Counter CNT. When this event occurs adjust the control of the performance counters in task mode as follows 6 7 read-write Const_00 00 No change. 0 Const_11 01 Start the performance counters. 1 Const_22 10 Stop the performance counters. 2 Const_33 11 Toggle the performance counter control i.e. start it if it is currently stopped stop it if it is currently running . 3 SWEVT CPUx Software Debug Event resetvalue={Debug Reset:0x0} 64784 32 0 4294967295 EVTA Event Associated EVTA. Debug Action associated with the Debug Event 0 2 read-write Const_00 000 BOD 0 Disabled. BOD 1 Disabled. 0 Const_11 001 BOD 0 Pulse BRKOUT Signal. BOD 1 None. 1 Const_22 010 BOD 0 Halt and pulse BRKOUT Signal. BOD 1 Halt. 2 Const_33 011 BOD 0 Breakpoint trap and pulse BRKOUT Signal. BOD 1 Breakpoint trap. 3 Const_44 100 BOD 0 Breakpoint interrupt 0 and pulse BRKOUT Signal. BOD 1 Breakpoint interrupt 0. 4 Const_55 101 BOD 0 If implemented breakpoint interrupt 1 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 1. If not implemented None. 5 Const_66 110 BOD 0 If implemented breakpoint interrupt 2 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 2. If not implemented None. 6 Const_77 111 BOD 0 If implemented breakpoint interrupt 3 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 3. If not implemented None. 7 BBM Break Before Make BBM or Break After Make BAM Selection BBM 3 3 read-write Const_00 0 Break after make BAM . 0 Const_11 1 Break before make BBM . 1 BOD Breakout Disable BOD 4 4 read-write Const_00 0 BRKOUT signal asserted according to the action specified in the EVTA field. 0 Const_11 1 BRKOUT signal not asserted. This takes priority over any assertion generated by the EVTA field. 1 SUSP CDC Suspend Out Signal State SUSP. Value to be assigned to the CDC suspend out signal when the event is raised. 5 5 read-write CNT Counter CNT. When this event occurs adjust the control of the performance counters in task mode as follows 6 7 read-write Const_00 00 No change. 0 Const_11 01 Start the performance counters. 1 Const_22 10 Stop the performance counters. 2 Const_33 11 Toggle the performance counter control i.e. start it if it is currently stopped stop it if it is currently running . 3 TRIG_ACC CPUx TriggerAddressx resetvalue={Debug Reset:0x0} 64816 32 0 4294967295 T0 Trigger 0 T0. active since last cleared 0 0 read-only T1 Trigger 1 T1. active since last cleared 1 1 read-only T2 Trigger 2 T2. active since last cleared 2 2 read-only T3 Trigger 3 T3. active since last cleared 3 3 read-only T4 Trigger 4 T4. active since last cleared 4 4 read-only T5 Trigger 5 T5. active since last cleared 5 5 read-only T6 Trigger 6 T6. active since last cleared 6 6 read-only T7 Trigger 7 T7. active since last cleared 7 7 read-only DMS CPUx Debug Monitor Start Address resetvalue={Application Reset:0x0} 64832 32 0 0 DMSValue Debug Monitor Start Address DMSValue. The address at which monitor code execution begins when a breakpoint trap is taken. 1 31 read-write DCX CPUx Debug Context Save Area Pointer resetvalue={Application Reset:0x0} 64836 32 0 0 DCXValue Debug Context Save Area Pointer DCXValue. Address where the debug context is stored following a breakpoint trap. 6 31 read-write DBGTCR CPUx Debug Trap Control Register resetvalue={Application Reset:0x1} 64840 32 1 4294967295 DTA Debug Trap Active Bit DTA. A breakpoint trap may only be taken in the condition DTA 0. Taking a breakpoint trap sets the DTA bit to one. Further breakpoint traps are therefore disabled until such time as the breakpoint trap handler clears the DTA bit or until the breakpoint trap handler terminates with a RFM. 0 0 read-write Const_00 0 No breakpoint trap is active. 0 Const_11 1 A breakpoint Trap is active 1 SEGEN CPUx SRI Error Generation Register resetvalue={Application Reset:0x0} 4144 32 0 4294967295 ADFLIP Address ECC Bit Flip ADFLIP. SRI address ECC Bits to be flipped on the next read or write transaction from the DMI when enabled by AE. 0 7 read-write Const_00 0 No Flip 0 Const_11 1 Flip 1 ADTYPE Type of error ADTYPE 8 9 read-write Const_00 00 Data Master Address Phase 0 Const_11 01 Data Master Write Data 1 Const_22 10 Data Slave Read Data 2 AE Activate Error Enable AE. Enabled the selective inverting of SRI ECC packet bits defined by ADFLIP. This bit will be cleared by hardware after the next SRI read or write transaction from the DMI. 31 31 read-write Const_00 0 Not Enabled 0 Const_11 1 Enabled 1 DCON2 CPUx Data Control Register 2 resetvalue={Application Reset:0x0} 36864 32 0 0 DCACHE_SZE Data Cache Size DCACHE SZE. In KBytes 0 15 read-only DSCRATCH_SZE Data Scratch Size DSCRATCH SZE. In KBytes 16 31 read-only DSTR CPUx Data Synchronous Trap Register resetvalue={Application Reset:0x0} 36880 32 0 4294967295 SRE Scratch Range Error SRE. A scratch Range Error occurs whenever an access to the data scratch is outside the range of the SRAM. 0 0 read-write GAE Global Address Error GAE. Load or store to local code scratch address outside of the lower 1MByte. 1 1 read-write LBE Load Bus Error LBE. A Load Bus Error will be set whenever the SRI flags an error due a load from external memory. 2 2 read-write DRE Local DLMU Range Error DRE. A DLMU Range Error occurs whenever an access to the local DLMU region is outside the physically implemented memory. 3 3 read-write CRE Cache Refill Error CRE. A Cache Refill Error will be set whenever the SRI flags an error due a cache refill from external memory. 6 6 read-write DTME DTAG MSIST Error DTME. Access to memory mapped DTAG range outside of physically implemented memory. 14 14 read-write LOE Load Overlay Error LOE. Load to invalid overlay address. 15 15 read-write SDE Segment Difference Error SDE. Load or store access where base address is in different segment to access address. 16 16 read-write SCE Segment Crossing Error SCE. Load or store access across segment boundary. 17 17 read-write CAC CSFR Access Error CAC. Load or store to local CSFR space. 18 18 read-write MPE Memory Protection Error MPE. Data access violating memory protection. 19 19 read-write CLE Context Location Error CLE. Context operation to invalid location. 20 20 read-write ALN Alignment Error ALN. Data access causing alignment error. 24 24 read-write DATR CPUx Data Asynchronous Trap Register resetvalue={Application Reset:0x0} 36888 32 0 4294967295 SBE Store Bus Error SBE 3 3 read-write CWE Cache Writeback Error CWE 9 9 read-write CFE Cache Flush Error CFE 10 10 read-write SOE Store Overlay Error SOE 14 14 read-write DEADD CPUx Data Error Address Register resetvalue={Application Reset:0x0} 36892 32 0 4294967295 ERROR_ADDRESS Error Address ERROR ADDRESS 0 31 read-only DCON0 CPUx Data Memory Control Register resetvalue={Application Reset:0x2} 36928 32 2 4294967295 DCBYP Data Cache Bypass DCBYP 1 1 read-write Const_00 0 DCache DRB enabled 0 Const_11 1 DCache DRB Bypass disabled 1 PSTR CPUx Program Synchronous Trap Register resetvalue={Application Reset:0x0} 37376 32 0 4294967295 FRE Fetch Range Error FRE. A Fetch Range Error occurs whenever an access to the Program Scratch is outside the range of the SRAM. 0 0 read-write FBE Fetch Bus Error FBE. A Fetch bus error will be set whenever the SRI flags an error due a fetch from external memory. This will be set for both direct fetches from the bus and for cache refills. 2 2 read-write FPE Fetch Peripheral Error FPE. A Fetch peripheral error will be flagged whenever a fetch is attempted to peripheral space. 12 12 read-write FME Fetch MSIST Error FME. During SIST mode a fetch from the PTAG will cause a PSE trap to occur. 14 14 read-write PCON1 CPUx Program Control 1 resetvalue={Application Reset:0x0} 37380 32 0 4294967295 PCINV Program Cache Invalidate PCINV 0 0 read-write Const_00 0 Write No effect normal instruction cache operation. Read Normal operation instruction cache available 0 Const_11 1 Write Initiate invalidation of entire instruction cache. Read Instruction cache invalidation in progress. Instruction cache unavailable. 1 PBINV Program Buffer Invalidate PBINV. Write Operation This field returns 0 when read. 1 1 read-write Const_00 0 Write No effect. Normal program line buffer operation. 0 Const_11 1 Write Invalidate the program line buffer. 1 PCON2 CPUx Program Control 2 resetvalue={Application Reset:0x0} 37384 32 0 0 PCACHE_SZE Program Cache Size ICACHE in KBytes PCACHE SZE. In KBytes 0 15 read-only PSCRATCH_SZE Program Scratch Size in KBytes PSCRATCH SZE. In KBytes 16 31 read-only PCON0 CPUx Program Control 0 resetvalue={Application Reset:0x2} 37388 32 2 4294967295 PCBYP Program Cache Bypass PCBYP 1 1 read-write Const_00 0 Cache enabled 0 Const_11 1 Cache bypass disabled 1 CPU1 100 CPU CPU0 0 0 65472 registers 18 8 DPR[%s] DPR 49152 DPRy_L CPUx Data Protection Range 0 Lower Bound Register resetvalue={Application Reset:0x0} 0 32 0 4294967295 LOWBND DPRy Lower Boundary Address LOWBND 3 31 read-write DPRy_U CPUx Data Protection Range 0 Upper Bound Register resetvalue={Application Reset:0x0} 4 32 0 4294967295 UPPBND DPRy Upper Boundary Address UPPBND 3 31 read-write 10 8 CPR[%s] CPR 53248 CPRy_L CPUx Code Protection Range 0 Lower Bound Register resetvalue={Application Reset:0x0} 0 32 0 4294967295 LOWBND CPRy Lower Boundary Address LOWBND 5 31 read-write CPRy_U CPUx Code Protection Range 0 Upper Bound Register resetvalue={Application Reset:0x0} 4 32 0 4294967295 UPPBND CPR0 m Upper Boundary Address UPPBND 5 31 read-write TPS TPS 58368 CON CPUx Temporal Protection System Control Register resetvalue={Application Reset:0x0} 0 32 0 4294967295 TEXP0 Timer0 Expired Flag TEXP0. Set when the corresponding timer expires. Cleared on any write to the TIMER0 register. 0 0 read-only TEXP1 Timer1 Expired Flag TEXP1. Set when the corresponding timer expires. Cleared on any write to the TIMER1 register. 1 1 read-only TEXP2 Timer1 Expired Flag TEXP2. Set when the corresponding timer expires. Cleared on any write to the TIMER1 register. 2 2 read-only TTRAP Temporal Protection Trap TTRAP. If set indicates that a TAE trap has been requested. Any subsequent TAE traps are disabled. A write clears the flag and re enables TAE traps. 16 16 read-only 3 4 TIMER[%s] CPUx Temporal Protection System Timer Register 0 resetvalue={Application Reset:0x0} 4 32 0 4294967295 Timer Temporal Protection Timer Timer. Writing zero de activates the Timer. Writing a non zero value starts the Timer. Any write clears the corresponding TPS CON.TEXP flag. Read returns the current Timer value. 0 31 read-write TPS_EXTIM TPS EXTIM 58432 ENTRY_LVAL CPUx Exception Entry Timer Load Value resetvalue={Application Reset:0x0} 0 32 0 4294967295 ENTRY_LVAL Exception Entry Timer Load value ENTRY LVAL. Value loaded into the exception entry timer on detection of an enabled exception. Bits 3 0 are constrained to be 0 4 11 read-write ENTRY_CVAL CPUx Exception Entry Timer Current Value resetvalue={Application Reset:0x0} 4 32 0 4294967295 ENTRY_CVAL Exception Entry Timer Current Value ENTRY CVAL. Current value of the exception entry timer. 0 11 read-only EXIT_LVAL CPUx Exception Exit Timer Load Value resetvalue={Application Reset:0x0} 8 32 0 4294967295 EXIT_LVAL Exception Exit Timer Load value EXIT LVAL. Value loaded into the exception exit timer on detection of an enabled exception. Bits 3 0 are constrained to be 0 4 23 read-write EXIT_CVAL CPUx Exception Exit Timer Current Value resetvalue={Application Reset:0x0} 12 32 0 4294967295 EXIT_CVAL Exception Exit Timer Current Value EXIT CVAL. Current value of the exception exit timer. 0 23 read-only CLASS_EN CPUx Exception Timer Class Enable Register resetvalue={Application Reset:0x0} 16 32 0 4294967295 EXTIM_CLASS_EN Exception Timer Class Enables EXTIM CLASS EN. Trap Class enables for exception timer. 0 7 read-write STAT CPUx Exception Timer Status Register resetvalue={Application Reset:0x0} 20 32 0 4294967295 EXIT_TIN Exception Exit Timer TIN EXIT TIN. Exception Exit Timer TIN of triggering trap. 0 7 read-write EXIT_CLASS Exception Exit Timer Class EXIT CLASS. Exception exit Timer Class of triggering trap. 8 10 read-write EXIT_AT Exception Exit Timer Alarm Triggered EXIT AT. Exception Exit Timer Alarm triggered sticky bit. Alarm triggered since last cleared. 15 15 read-only ENTRY_TIN Exception Entry Timer TIN ENTRY TIN. Exception Entry Timer TIN of triggering trap. 16 23 read-write ENTRY_CLASS Exception Entry Timer Class ENTRY CLASS. Exception Entry Timer Class of triggering trap. 24 26 read-write ENTRY_AT Exception Entry Timer Alarm Triggered ENTRY AT. Exception Entry Timer Alarm triggered sticky bit. Alarm triggered since last cleared. 31 31 read-only FCX CPUx Exception Timer FCX Register resetvalue={Application Reset:0x0} 24 32 0 4294967295 EXIT_FCX Exception Exit Timer FCX EXIT FCX. Exception Exit Timer FCX of triggering trap. 0 19 read-only FPU_TRAP FPU TRAP 40960 CON CPUx Trap Control Register resetvalue={Application Reset:0x0} 0 32 0 4294967295 TST Trap Status TST 0 0 read-only Const_00 0 No instruction captured. The next enabled exception will cause the exceptional instruction to be captured. 0 Const_11 1 Instruction captured. No further enabled exceptions will be captured until TST is cleared. 1 TCL Trap Clear TCL. Read always reads as 0. 1 1 write-only Const_00 0 No effect. 0 Const_11 1 Clears the trapped instruction TST will be negated . 1 RM Captured Rounding Mode RM. The rounding mode of the captured instruction. Only valid when TST is asserted. Note that this is the rounding mode supplied to the FPU for the exceptional instruction. UPDFL instructions may cause a trap and change the rounding mode. In this case the RM bits capture the input rounding mode 8 9 read-only FXE FX Trap Enable FXE. When set an instruction generating an FX exception will trigger a trap. 18 18 read-write FUE FU Trap Enable FUE. When set an instruction generating an FU exception will trigger a trap. 19 19 read-write FZE FZ Trap Enable FZE. When set an instruction generating an FZ exception will trigger a trap. 20 20 read-write FVE FV Trap Enable FVE. When set an instruction generating an FV exception will trigger a trap. 21 21 read-write FIE FI Trap Enable FIE. When set an instruction generating an FI exception will trigger a trap. 22 22 read-write FX Captured FX FX. Asserted if the captured instruction asserted FX. Only valid when TST is asserted. 26 26 read-only FU Captured FU FU. Asserted if the captured instruction asserted FU. Only valid when TST is asserted. 27 27 read-only FZ Captured FZ FZ. Asserted if the captured instruction asserted FZ. Only valid when TST is asserted 28 28 read-only FV Captured FV FV. Asserted if the captured instruction asserted FV. Only valid when TST is asserted 29 29 read-only FI Captured FI FI. Asserted if the captured instruction asserted FI. Only valid when TST is asserted 30 30 read-only PC CPUx Trapping Instruction Program Counter Register resetvalue={Application Reset:0x0} 4 32 0 4294967295 PC Captured Program Counter PC. The program counter virtual address of the captured instruction. Only valid when FPU TRAP CON.TST is asserted. 0 31 read-only OPC CPUx Trapping Instruction Opcode Register resetvalue={Application Reset:0x0} 8 32 0 4294967295 OPC Captured Opcode OPC. The secondary opcode of the captured instruction. When FPU TRAP OPC.FMT 0 only bits 3 0 are defined. OPC is valid only when FPU TRAP CON.TST is asserted. 0 7 read-only FMT Captured Instruction Format FMT. The format of the captured instruction s opcode. Only valid when FPU TRAP CON.TST is asserted. 8 8 read-only Const_00 0 RRR 0 Const_11 1 RR 1 DREG Captured Destination Register DREG. The destination register of the captured instruction. ... Only valid when FPU TRAP CON.TST is asserted. 16 19 read-only Const_00 0 Data general purpose register 0. 0 Const_1515 F Data general purpose register 15. 15 SRC1 CPUx Trapping Instruction Operand Register resetvalue={Application Reset:0x0} 16 32 0 4294967295 SRC1 Captured SRC1 Operand SRC1. The SRC1 operand of the captured instruction. Only valid when FPU TRAP CON.TST is asserted. 0 31 read-only SRC2 CPUx Trapping Instruction Operand Register resetvalue={Application Reset:0x0} 20 32 0 4294967295 SRC2 Captured SRC2 Operand SRC2. The SRC2 operand of the captured instruction. Only valid when FPU TRAP CON.TST is asserted. 0 31 read-only SRC3 CPUx Trapping Instruction Operand Register resetvalue={Application Reset:0x0} 24 32 0 4294967295 SRC3 Captured SRC3 Operand SRC3. The SRC3 operand of the captured instruction. Only valid when FPU TRAP CON.TST is asserted. 0 31 read-only 8 8 TR[%s] Trigger 61440 TRiEVT CPUx Trigger Event 0 resetvalue={Debug Reset:0x0} 0 32 0 4294967295 EVTA Event Associated EVTA. Specifies the Debug Action associated with the Debug Event 0 2 read-write Const_00 000 BOD 0 Disabled. BOD 1 Disabled. 0 Const_11 001 BOD 0 Pulse BRKOUT Signal. BOD 1 None. 1 Const_22 010 BOD 0 Halt and pulse BRKOUT Signal. BOD 1 Halt. 2 Const_33 011 BOD 0 Breakpoint trap and pulse BRKOUT Signal. BOD 1 Breakpoint trap. 3 Const_44 100 BOD 0 Breakpoint interrupt 0 and pulse BRKOUT Signal. BOD 1 Breakpoint interrupt 0. 4 Const_55 101 BOD 0 If implemented breakpoint interrupt 1 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 1. If not implemented None. 5 Const_66 110 BOD 0 If implemented breakpoint interrupt 2 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 2. If not implemented None. 6 Const_77 111 BOD 0 If implemented breakpoint interrupt 3 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 3. If not implemented None. 7 BBM Break Before Make BBM or Break After Make BAM Selection BBM. Code triggers BBM or BAM selection. Data access and data code combination access triggers can only create BAM Debug Events. When these triggers occur TRnEVT.BBM is ignored. 3 3 read-write Const_00 0 Code only triggers Break After Make BAM . 0 Const_11 1 Code only triggers Break Before Make BBM . 1 BOD Breakout Disable BOD 4 4 read-write Const_00 0 BRKOUT signal asserted according to the action specified in the EVTA field. 0 Const_11 1 BRKOUT signal not asserted. This takes priority over any assertion generated by the EVTA field. 1 SUSP CDC Suspend Out Signal State SUSP. Value to be assigned to the CDC suspend out signal when the Debug Event is raised. 5 5 read-write CNT Counter CNT. When this event occurs adjust the control of the performance counters in task mode as follows 6 7 read-write Const_00 00 No change. 0 Const_11 01 Start the performance counters. 1 Const_22 10 Stop the performance counters. 2 Const_33 11 Toggle the performance counter control i.e. start it if it is currently stopped stop it if it is currently running . 3 TYP Input Selection TYP 12 12 read-write Const_00 0 Address 0 Const_11 1 PC 1 RNG Compare Type RNG. Once an even numbered comparator has been set to range the EVTR settings of its associated upper neighbour will be ignored. 13 13 read-write Const_11 1 Range 1 Const_00 0 Equality 0 ASI_EN Enable ASI Comparison ASI EN 15 15 read-write Const_00 0 No ASI comparison performed. Debug Trigger is valid for all processes. 0 Const_11 1 Enable ASI comparison. Debug Events are only triggered when the current process ASI matches TRnEVT.ASI. 1 ASI Address Space Identifier ASI. The ASI of the Debug Trigger process. 16 20 read-write AST Address Store AST. Used in conjunction with TYP 0 27 27 read-write ALD Address Load ALD. Used in conjunction with TYP 0 28 28 read-write TRiADR CPUx Trigger Address 0 resetvalue={Debug Reset:0x0} 4 32 0 4294967295 ADDR Comparison Address ADDR. For PC comparison bit 0 is always zero. 0 31 read-write SMACON CPUx SIST Mode Access Control Register resetvalue={Application Reset:0x0} 36876 32 0 4294967295 IODT In Order Data Transactions IODT 24 24 read-write Const_00 0 Normal operation Non dependent loads bypass stores. 0 Const_11 1 In order operation Loads always flush preceding stores processor store buffer disabled. 1 DIEAR CPUx Data Integrity Error Address Register resetvalue={Application Reset:0x0} 36896 32 0 4294967295 TA Transaction Address TA. Physical address being accessed by operation that encountered data integrity error. 0 31 read-only DIETR CPUx Data Integrity Error Trap Register resetvalue={Application Reset:0x0} 36900 32 0 4294967295 IED Integrity Error Detected IED 0 0 read-write Const_00 0 Write Clear IED bit re enable DIETR and DIEAR update. Read No data integrity error condition occurred 0 Const_11 1 Write No Effect. Read Data integrity error condition detected. DIETR and DIEAR contents valid further DIETR and DIEAR updates disabled.. 1 IE_T Integrity Error Tag Memory IE T 1 1 read-only IE_C Integrity Error Cache Memory IE C 2 2 read-only IE_S Integrity Error Scratchpad Memory IE S 3 3 read-only IE_BI Integrity Error Bus Interface IE BI 4 4 read-only E_INFO Error Information E INFO. If IE BS 1 Bus Master Tag ID of requesting masterIf IE C 1 Cache way. 5 10 read-only IE_UNC Dual Bit Error Detected IE UNC 11 11 read-only IE_SP Safety Protection Error Detected IE SP 12 12 read-only IE_BS Bus Slave Access Indicator IE BS 13 13 read-only IE_DLMU Integrity Error DLMU IE DLMU 14 14 read-only IE_LPB Integrity Error Local Pflash Bank IE LPB 15 15 read-only IE_MTMV Memory Test Mode Violation detected IE MTMV 16 16 read-only PIEAR CPUx Program Integrity Error Address Register resetvalue={Application Reset:0x0} 37392 32 0 4294967295 TA Transaction Address TA. Physical address being accessed by operation that encountered program integrity error. 0 31 read-only PIETR CPUx Program Integrity Error Trap Register resetvalue={Application Reset:0x0} 37396 32 0 4294967295 IED Integrity Error Detected IED 0 0 read-write Const_00 0 Write Clear IED bit re enable PIETR and PIEAR update. Read No data integrity error condition occurred 0 Const_11 1 Write No Effect. Read Data integrity error condition detected. PIETR and PIEAR contents valid further PIETR and PIEAR updates disabled.. 1 IE_T Integrity Error TAG Memory IE T 1 1 read-only IE_C Integrity Error Cache Memory IE C 2 2 read-only IE_S Integrity Error Scratchpad Memory IE S 3 3 read-only IE_BI Integrity Error Bus Interface IE BI 4 4 read-only E_INFO Error Information E INFO. If IE BS 1 Bus Master Tag ID of requesting masterIf IE C 1 Cache way. 5 10 read-only IE_UNC Integrity Error Uncorrectable Error Detected IE UNC 11 11 read-only IE_SP Safety Protection Error Detected IE SP 12 12 read-only IE_BS Bus Slave Access Indicator IE BS 13 13 read-only IE_ADDR Address Phase error detected at SRI slave interface IE ADDR 14 14 read-only IE_LPB Integrity Error Local Pflash bank IE LPB 15 15 read-only IE_MTMV Memory Test Mode Violation detected IE MTMV 16 16 read-only TASK_ASI CPUx Task Address Space Identifier Register resetvalue={Application Reset:0x1F} 32772 32 31 4294967295 ASI Address Space Identifier ASI. The ASI register contains the Address Space Identifier of the current process. 0 4 read-write PMA0 CPUx Data Access CacheabilityRegister resetvalue={Application Reset:0x300} 33024 32 768 4294967295 DAC Data Access Cacheability Segments FHto 0H DAC. Note segments F H E H D H and A H are constrained to be non cacheable 0 15 read-write PMA1 CPUx Code Access CacheabilityRegister resetvalue={Application Reset:0x300} 33028 32 768 4294967295 CAC Code Access Cacheability Segments FH 0H CAC. Note Segments F H E H C H A H are constrained to be non cacheable 0 15 read-write PMA2 CPUx Peripheral Space Identifier register resetvalue={Application Reset:0x0C000} 33032 32 49152 4294967295 PSI Peripheral Space Identifier Segments FH 0H PSI 0 15 read-only COMPAT CPUx Compatibility Control Register resetvalue={Application Reset:0x0FFFFFFFF} 37888 32 4294967295 4294967295 RM Rounding Mode Compatibility RM 3 3 read-write Const_00 0 PSW.RM not restored by RET. 0 Const_11 1 PSW.RM restored by RET TC1.3 behavior . 1 SP SYSCON Safety Protection Mode Compatibility SP 4 4 read-write Const_00 0 SYSCON 31 1 safety endinit protected. 0 Const_11 1 SYSCON 31 1 not safety endinit protected TC1.3 behavior . 1 PCXI CPUx Previous Context Information Register resetvalue={Application Reset:0x0} 65024 32 0 4294967295 PCXO Previous Context Pointer Offset Field PCXO. The PCXO and PCXS fields form the pointer PCX which points to the CSA of the previous context. 0 15 read-write PCXS Previous Context Pointer Segment Address PCXS. Contains the segment address portion of the PCX. This field is used in conjunction with the PCXO field. 16 19 read-write UL Upper or Lower Context Tag UL. Identifies the type of context saved. If the type does not match the type expected when a context restore operation is performed a trap is generated. 20 20 read-write Const_00 0 Lower Context 0 Const_11 1 Upper Context 1 PIE Previous Interrupt Enable PIE. Indicates the state of the interrupt enable bit ICR.IE for the interrupted task. 21 21 read-write PCPN Previous CPU Priority Number PCPN. Contains the priority level number of the interrupted task. 22 29 read-write PSW CPUx Program Status Word resetvalue={Application Reset:0x0B80} 65028 32 2944 4294967295 CDC Call Depth Counter CDC. Consists of two variable width subfields. The first subfield consists of a string of zero or more initial 1 bits terminated by the first 0 bit. The remaining bits form the second subfield CDC.COUNT which constitutes the Call Depth Count value. The count value is incremented on each Call and is decremented on a Return. 0cccccc B 6 bit counter trap on overflow. 10ccccc B 5 bit counter trap on overflow. 110cccc B 4 bit counter trap on overflow. 1110ccc B 3 bit counter trap on overflow. 11110cc B 2 bit counter trap on overflow. 111110c B 1 bit counter trap on overflow. 1111110 B Trap every call Call Trace mode . 1111111 B Disable Call Depth Counting. When the call depth count CDC.COUNT overflows a trap CDO is generated. Setting the CDC to 1111110 B allows no bits for the counter and causes every call to be trapped. This is used for Call Depth Tracing. Setting the CDC to 1111111 B disables Call Depth Counting. 0 6 read-write CDE Call Depth Count Enable CDE. Enables call depth counting provided that the PSW.CDC mask field is not all set to 1. If PSW.CDC 1111111 B call depth counting is disabled regardless of the setting on the PSW.CDE bit. 7 7 read-write Const_00 0 Call depth counting is temporarily disabled. It is automatically re enabled after execution of the next Call instruction. 0 Const_11 1 Call depth counting is enabled. 1 IS Interrupt Stack Control IS. Determines if the current execution thread is using the shared global interrupt stack or a user stack. 9 9 read-write Const_00 0 User Stack. If an interrupt is taken when the IS bit is 0 then the stack pointer register is loaded from the ISP register before execution starts at the first instruction of the Interrupt Service Routine ISR . 0 Const_11 1 Shared Global Stack. If an interrupt is taken when the PSW.IS bit is 1 then the current value of the stack pointer is used by the Interrupt Service Routine ISR . 1 IO Access Privilege Level Control I O Privilege IO. Determines the access level to special function registers and peripheral devices. 10 11 read-write Const_00 00 User 0 Mode No peripheral access. Access to memory regions with the peripheral space attribute are prohibited and results in a PSE or MPP trap. This access level is given to tasks that need not directly access peripheral devices. Tasks at this level do not have permission to enable or disable interrupts. 0 Const_11 01 User 1 Mode Regular peripheral access. Enables access to common peripheral devices that are not specially protected including read write access to serial I O ports read access to timers and access to most I O status registers. Tasks at this level may disable interrupts. 1 Const_22 10 Supervisor Mode Enables access to all peripheral devices. It enables read write access to core registers and protected peripheral devices. Tasks at this level may disable interrupts. 2 S Safe Task Identifier S 14 14 read-write USB User Status Bits USB. The eight most significant bits of the PSW are designated as User Status Bits. These bits may be set or cleared as side effects of instruction execution. Refer to the TriCore Architecture manual for details. 24 31 read-write PC CPUx Program Counter resetvalue={Application Reset:0x0} 65032 32 0 0 PC Program Counter PC 1 31 read-write SYSCON CPUx System Configuration Register resetvalue={Application Reset:0x0,Application Reset:0x0} 65044 32 0 0 FCDSF Free Context List Depleted Sticky Flag FCDSF. This sticky bit indicates that a FCD Free Context List Depleted trap occurred since the bit was last cleared by software. 0 0 read-write Const_00 0 No FCD trap occurred since the last clear. 0 Const_11 1 An FCD trap occurred since the last clear. 1 PROTEN Memory Protection Enable PROTEN. Enables the memory protection system. Memory protection is controlled through the memory protection register sets. Note Initialize the protection register sets prior to setting PROTEN to one. 1 1 read-write Const_00 0 Memory Protection is disabled. 0 Const_11 1 Memory Protection is enabled. 1 TPROTEN Temporal Protection Enable TPROTEN. Enable the Temporal Protection system. 2 2 read-write Const_00 0 Temporal Protection is disabled. 0 Const_11 1 Temporal Protection is enabled. 1 IS Initial State Interrupt IS. of PSW.S bit in interrupt handle 3 3 read-write TS Initial State Trap TS. of PSW.S bit in trap handle 4 4 read-write ESDIS Emulator Space Disable. Disable the Emulator Space system 8 8 read-write U1_IED User 1 Instruction execution disable U1 IED. Disable the execution of User 1 mode instructions in User 1 IO mode. Disables User 1 ability to enable and disable interrupts. 16 16 read-write U1_IOS User 1 Peripheral access as supervisor U1 IOS. Allow User 1 mode tasks to access peripherals as if in Supervisor mode. Enables User 1 access to all peripheral registers. 17 17 read-write BHALT Boot Halt BHALT 24 24 read-write Const_00 0 Core is not in boot halt. 0 Const_11 1 Core is in boot halt write to 0 will exit 1 CPU_ID CPUx Identification Register TC1.6.2P resetvalue={Application Reset:0x0C0C021} 65048 32 12632097 4294967295 MOD_REV Revision Number MOD REV 0 7 read-only Const_3232 20 Reset value 32 MOD_32B 32 Bit Module Enable MOD 32B 8 15 read-only Const_192192 C0 A value of C0 H in this field indicates a 32 bit module with a 32 bit module ID register. 192 MOD Module Identification Number MOD 16 31 read-only Const_192192 00C0 For module identification. 192 CORE_ID CPUx Core Identification Register resetvalue={Application Reset:0x0} 65052 32 0 4294967288 CORE_ID Core Identification Number CORE ID. The identification number of the core. 0 2 read-only BIV CPUx Base Interrupt Vector Table Pointer resetvalue={Application Reset:0x0} 65056 32 0 4294967295 VSS Vector Spacing Select VSS. 0 32 byte vector spacing. 1 8 Byte vector spacing. 0 0 read-write BIV Base Address of Interrupt Vector Table BIV. The address in the BIV register must be aligned to an even byte address halfword address . Because of the simple ORing of the left shifted priority number and the contents of the BIV register the alignment of the base address of the vector table must be to a power of two boundary dependent on the number of interrupt entries used. For the full range of 256 interrupt entries an alignment to an 8 KByte boundary is required. If fewer sources are used the alignment requirements are correspondingly relaxed. 1 31 read-write BTV CPUx Base Trap Vector Table Pointer resetvalue={Application Reset:0x0A0000100} 65060 32 2684354816 4294967295 BTV Base Address of Trap Vector Table BTV. The address in the BTV register must be aligned to an even byte address halfword address . Also due to the simple ORing of the left shifted trap identification number and the contents of the BTV register the alignment of the base address of the vector table must be to a power of two boundary. There are eight different trap classes resulting in Trap Classes from 0 to 7. The contents of BTV should therefore be set to at least a 256 byte boundary 8 Trap Classes 8 word spacing . 1 31 read-write ISP CPUx Interrupt Stack Pointer resetvalue={Application Reset:0x100} 65064 32 256 4294967295 ISP Interrupt Stack Pointer ISP 0 31 read-write ICR CPUx Interrupt Control Register resetvalue={Application Reset:0x0} 65068 32 0 4294967295 CCPN Current CPU Priority Number CCPN. The Current CPU Priority Number CCPN bit field indicates the current priority level of the CPU. It is automatically updated by hardware on entry or exit of Interrupt Service Routines ISRs and through the execution of a BISR instruction. CCPN can also be updated through an MTCR instruction. 0 7 read-write IE Global Interrupt Enable Bit IE. The interrupt enable bit globally enables the CPU service request system. Whether a service request is delivered to the CPU depends on the individual Service Request Enable Bits SRE in the SRNs and the current state of the CPU. ICR.IE is automatically updated by hardware on entry and exit of an Interrupt Service Routine ISR . ICR.IE is cleared to 0 when an interrupt is taken and is restored to the previous value when the ISR executes an RFE instruction to terminate itself. ICR.IE can also be updated through the execution of the ENABLE DISABLE MTCR and BISR instructions. 15 15 read-write Const_00 0 Interrupt system is globally disabled 0 Const_11 1 Interrupt system is globally enabled 1 PIPN Pending Interrupt Priority Number PIPN. A read only bit field that is updated by the ICU at the end of each interrupt arbitration process. It indicates the priority number of the pending service request. ICR.PIPN is set to 0 when no request is pending and at the beginning of each new arbitration process. ... 16 23 read-only Const_00 00 No valid pending request. 0 Const_11 01 Request pending lowest priority. 1 Const_255255 FF Request pending highest priority. 255 FCX CPUx Free CSA List Head Pointer resetvalue={Application Reset:0x0} 65080 32 0 4294967295 FCXO FCX Offset Address Field FCXO. The FCXO and FCXS fields together form the FCX pointer which points to the next available CSA. 0 15 read-write FCXS FCX Segment Address Field FCXS. Used in conjunction with the FCXO field. 16 19 read-write LCX CPUx Free CSA List Limit Pointer resetvalue={Application Reset:0x0} 65084 32 0 4294967295 LCXO LCX Offset Field LCXO. The LCXO and LCXS fields form the pointer LCX which points to the last available CSA. 0 15 read-write LCXS LCX Segment Address LCXS. This field is used in conjunction with the LCXO field. 16 19 read-write CUS_ID CPUx Customer ID register resetvalue={Application Reset:0x0} 65104 32 0 4294967288 CID Customer ID CID. See CROSSREFERENCE for the relation between CUS ID and CORE ID for each derivative 0 2 read-only 16 4 Dy[%s] CPUx Data General Purpose Register 0 resetvalue={Application Reset:0x0} 65280 32 0 0 DATA Data Register DATA. General purpose registers 0 31 read-write 16 4 Ay[%s] CPUx Address General Purpose Register 0 resetvalue={Application Reset:0x0} 65408 32 0 0 ADDR Address Register ADDR. General purpose registers 0 31 read-write CPXE_0 CPUx Code Protection Execute Enable Register Set 3 resetvalue={Application Reset:0x0} 57344 32 0 4294967295 XE_n Execute Enable Range select XE n 0 9 read-write Const_00 0 Code Protection Range n not enabled for execution 0 Const_11 1 Code Protection Range n enabled for execution 1 CPXE_1 CPUx Code Protection Execute Enable Register Set 3 resetvalue={Application Reset:0x0} 57348 32 0 4294967295 XE_n Execute Enable Range select XE n 0 9 read-write Const_00 0 Code Protection Range n not enabled for execution 0 Const_11 1 Code Protection Range n enabled for execution 1 CPXE_2 CPUx Code Protection Execute Enable Register Set 3 resetvalue={Application Reset:0x0} 57352 32 0 4294967295 XE_n Execute Enable Range select XE n 0 9 read-write Const_00 0 Code Protection Range n not enabled for execution 0 Const_11 1 Code Protection Range n enabled for execution 1 CPXE_3 CPUx Code Protection Execute Enable Register Set 3 resetvalue={Application Reset:0x0} 57356 32 0 4294967295 XE_n Execute Enable Range select XE n 0 9 read-write Const_00 0 Code Protection Range n not enabled for execution 0 Const_11 1 Code Protection Range n enabled for execution 1 DPRE_0 CPUx Data Protection Read Enable Register Set 3 resetvalue={Application Reset:0x0} 57360 32 0 4294967295 RE_n Read Enable Range Select RE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data read 0 Const_11 1 Data Protection Range n enabled for data read 1 DPRE_1 CPUx Data Protection Read Enable Register Set 3 resetvalue={Application Reset:0x0} 57364 32 0 4294967295 RE_n Read Enable Range Select RE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data read 0 Const_11 1 Data Protection Range n enabled for data read 1 DPRE_2 CPUx Data Protection Read Enable Register Set 3 resetvalue={Application Reset:0x0} 57368 32 0 4294967295 RE_n Read Enable Range Select RE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data read 0 Const_11 1 Data Protection Range n enabled for data read 1 DPRE_3 CPUx Data Protection Read Enable Register Set 3 resetvalue={Application Reset:0x0} 57372 32 0 4294967295 RE_n Read Enable Range Select RE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data read 0 Const_11 1 Data Protection Range n enabled for data read 1 DPWE_0 CPUx Data Protection Write Enable Register Set 3 resetvalue={Application Reset:0x0} 57376 32 0 4294967295 WE_n Write Enable Range Select WE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data write 0 Const_11 1 Data Protection Range n enabled for data write 1 DPWE_1 CPUx Data Protection Write Enable Register Set 3 resetvalue={Application Reset:0x0} 57380 32 0 4294967295 WE_n Write Enable Range Select WE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data write 0 Const_11 1 Data Protection Range n enabled for data write 1 DPWE_2 CPUx Data Protection Write Enable Register Set 3 resetvalue={Application Reset:0x0} 57384 32 0 4294967295 WE_n Write Enable Range Select WE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data write 0 Const_11 1 Data Protection Range n enabled for data write 1 DPWE_3 CPUx Data Protection Write Enable Register Set 3 resetvalue={Application Reset:0x0} 57388 32 0 4294967295 WE_n Write Enable Range Select WE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data write 0 Const_11 1 Data Protection Range n enabled for data write 1 CPXE_4 CPUx Code Protection Execute Enable Register Set 5 resetvalue={Application Reset:0x0} 57408 32 0 4294967295 XE_n Execute Enable Range select XE n 0 9 read-write Const_00 0 Code Protection Range n not enabled for execution 0 Const_11 1 Code Protection Range n enabled for execution 1 CPXE_5 CPUx Code Protection Execute Enable Register Set 5 resetvalue={Application Reset:0x0} 57412 32 0 4294967295 XE_n Execute Enable Range select XE n 0 9 read-write Const_00 0 Code Protection Range n not enabled for execution 0 Const_11 1 Code Protection Range n enabled for execution 1 DPRE_4 CPUx Data Protection Read Enable Register Set 5 resetvalue={Application Reset:0x0} 57424 32 0 4294967295 RE_n Read Enable Range Select RE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data read 0 Const_11 1 Data Protection Range n enabled for data read 1 DPRE_5 CPUx Data Protection Read Enable Register Set 5 resetvalue={Application Reset:0x0} 57428 32 0 4294967295 RE_n Read Enable Range Select RE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data read 0 Const_11 1 Data Protection Range n enabled for data read 1 DPWE_4 CPUx Data Protection Write Enable Register Set 5 resetvalue={Application Reset:0x0} 57440 32 0 4294967295 WE_n Write Enable Range Select WE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data write 0 Const_11 1 Data Protection Range n enabled for data write 1 DPWE_5 CPUx Data Protection Write Enable Register Set 5 resetvalue={Application Reset:0x0} 57444 32 0 4294967295 WE_n Write Enable Range Select WE n 0 17 read-write Const_00 0 Data Protection Range n not enabled for data write 0 Const_11 1 Data Protection Range n enabled for data write 1 CCTRL CPUx Counter Control resetvalue={Debug Reset:0x0} 64512 32 0 4294967295 CM Counter Mode CM 0 0 read-write Const_00 0 Normal Mode. 0 Const_11 1 Task Mode. 1 CE Count Enable CE 1 1 read-write Const_00 0 Disable the counters CCNT ICNT M1CNT M2CNT M3CNT. 0 Const_11 1 Enable the counters CCNT ICNT M1CNT M2CNT M3CNT. 1 M1 M1CNT Configuration M1 2 4 read-write M2 M2CNT Configuration M2 5 7 read-write M3 M3CNT Configuration M3 8 10 read-write CCNT CPUx CPU Clock Cycle Count resetvalue={Debug Reset:0x0} 64516 32 0 4294967295 CountValue Count Value CountValue. Current Count of the CPU Clock Cycles. 0 30 read-write SOvf Sticky Overflow Bit SOvf. This bit is set by hardware when count value 30 0 31 h7FFF FFFF. It can only be cleared by software. 31 31 read-write ICNT CPUx Instruction Count resetvalue={Debug Reset:0x0} 64520 32 0 4294967295 CountValue Count Value CountValue. Count of the Instructions Executed. 0 30 read-write SOvf Sticky Overflow Bit SOvf. This bit is set by hardware when count value 30 0 31 h7FFF FFFF. It can only be cleared by software. 31 31 read-write M1CNT CPUx Multi Count Register 1 resetvalue={Debug Reset:0x0} 64524 32 0 4294967295 CountValue Count Value CountValue. Count of the Selected Event. 0 30 read-write SOvf Sticky Overflow Bit SOvf. This bit is set by hardware when count value 30 0 31 h7FFF FFFF. It can only be cleared by software. 31 31 read-write M2CNT CPUx Multi Count Register 2 resetvalue={Debug Reset:0x0} 64528 32 0 4294967295 CountValue Count Value CountValue. Count of the Selected Event. 0 30 read-write SOvf Sticky Overflow Bit SOvf. This bit is set by hardware when count value 30 0 31 h7FFF FFFF. It can only be cleared by software. 31 31 read-write M3CNT CPUx Multi Count Register 3 resetvalue={Debug Reset:0x0} 64532 32 0 4294967295 CountValue Count Value CountValue. Count of the Selected Event. 0 30 read-write SOvf Sticky Overflow Bit SOvf. This bit is set by hardware when count value 30 0 31 h7FFF FFFF. It can only be cleared by software. 31 31 read-write DBGSR CPUx Debug Status Register resetvalue={Debug Reset:0x0} 64768 32 0 4294967295 DE Debug Enable DE. Determines whether the CDC is enabled or not. 0 0 read-only Const_00 0 The CDC is disabled. 0 Const_11 1 The CDC is enabled. 1 HALT CPU Halt Request Status Field HALT. HALT can be set or cleared by software. HALT 0 is the actual Halt bit. HALT 1 is a mask bit to specify whether or not HALT 0 is to be updated on a software write. HALT 1 is always read as 0. HALT 1 must be set to 1 in order to update HALT 0 by software R read W write . 1 2 read-write Const_00 00 R CPU running. W HALT 0 unchanged. 0 Const_11 01 R CPU halted. W HALT 0 unchanged. 1 Const_22 10 R Not Applicable. W reset HALT 0 . 2 Const_33 11 R Not Applicable. W If DBGSR.DE 1 The CDC is enabled set HALT 0 . If DBGSR.DE 0 The CDC is not enabled HALT 0 is left unchanged. 3 SIH Suspend in Halt SIH. State of the Suspend In signal. 3 3 read-only Const_00 0 The Suspend In signal is negated. The CPU is not in Halt Mode except when the Halt mechanism is set following a Debug Event or a write to DBGSR.HALT . 0 Const_11 1 The Suspend In signal is asserted. The CPU is in Halt Mode. 1 SUSP Current State of the Core Suspend Out Signal SUSP 4 4 read-write Const_00 0 Core suspend out inactive. 0 Const_11 1 Core suspend out active. 1 PREVSUSP Previous State of Core Suspend Out Signal PREVSUSP. Updated when a Debug Event causes a hardware update of DBGSR.SUSP. This field is not updated for writes to DBGSR.SUSP. 6 6 read-only Const_00 0 Previous core suspend out inactive. 0 Const_11 1 Previous core suspend out active. 1 PEVT Posted Event PEVT 7 7 read-write Const_00 0 No posted event. 0 Const_11 1 Posted event. 1 EXEVT CPUx External Event Register resetvalue={Debug Reset:0x0} 64776 32 0 4294967295 EVTA Event Associated EVTA. Specifies the Debug Action associated with the Debug Event 0 2 read-write Const_00 000 BOD 0 Disabled. BOD 1 Disabled. 0 Const_11 001 BOD 0 Pulse BRKOUT Signal. BOD 1 None. 1 Const_22 010 BOD 0 Halt and pulse BRKOUT Signal. BOD 1 Halt. 2 Const_33 011 BOD 0 Breakpoint trap and pulse. BRKOUT Signal. BOD 1 Breakpoint trap. 3 Const_44 100 BOD 0 Breakpoint interrupt 0 and pulse BRKOUT Signal. BOD 1 Breakpoint interrupt 0. 4 Const_55 101 BOD 0 If implemented breakpoint interrupt 1 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 1. If not implemented None. 5 Const_66 110 BOD 0 If implemented breakpoint interrupt 2 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 2. If not implemented None. 6 Const_77 111 BOD 0 If implemented breakpoint interrupt 3 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 3. If not implemented None. 7 BBM Break Before Make BBM or Break After Make BAM Selection BBM 3 3 read-write Const_00 0 Break after make BAM . 0 Const_11 1 Break before make BBM . 1 BOD Breakout Disable BOD 4 4 read-write Const_00 0 BRKOUT signal asserted according to the Debug Action specified in the EVTA field. 0 Const_11 1 BRKOUT signal not asserted. This takes priority over any assertion generated by the EVTA field. 1 SUSP CDC Suspend Out Signal State SUSP. Value to be assigned to the CDC suspend out signal when the Debug Event is raised. 5 5 read-write CNT Counter CNT. When this event occurs adjust the control of the performance counters in task mode as follows 6 7 read-write Const_00 00 No change. 0 Const_11 01 Start the performance counters. 1 Const_22 10 Stop the performance counters. 2 Const_33 11 Toggle the performance counter control i.e. start it if it is currently stopped stop it if it is currently running . 3 CREVT CPUx Core Register Access Event resetvalue={Debug Reset:0x0} 64780 32 0 4294967295 EVTA Event Associated EVTA. Debug Action associated with the Debug Event 0 2 read-write Const_00 000 BOD 0 Disabled. BOD 1 Disabled. 0 Const_11 001 BOD 0 Pulse BRKOUT Signal. BOD 1 None. 1 Const_22 010 BOD 0 Halt and pulse BRKOUT Signal. BOD 1 Halt. 2 Const_33 011 BOD 0 Breakpoint trap and pulse BRKOUT Signal. BOD 1 Breakpoint trap. 3 Const_44 100 BOD 0 Breakpoint interrupt 0 and pulse BRKOUT Signal. BOD 1 Breakpoint interrupt 0. 4 Const_55 101 BOD 0 If implemented breakpoint interrupt 1 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 1. If not implemented None. 5 Const_66 110 BOD 0 If implemented breakpoint interrupt 2 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 2. If not implemented None. 6 Const_77 111 BOD 0 If implemented breakpoint interrupt 3 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 3. If not implemented None. 7 BBM Break Before Make BBM or Break After Make BAM Selection BBM 3 3 read-write Const_00 0 Break after make BAM . 0 Const_11 1 Break before make BBM . 1 BOD Breakout Disable BOD 4 4 read-write Const_00 0 BRKOUT signal asserted according to the action specified in the EVTA field. 0 Const_11 1 BRKOUT signal not asserted. This takes priority over any assertion generated by the EVTA field. 1 SUSP CDC Suspend Out Signal State SUSP. Value to be assigned to the CDC suspend out signal when the Debug Event is raised. 5 5 read-write CNT Counter CNT. When this event occurs adjust the control of the performance counters in task mode as follows 6 7 read-write Const_00 00 No change. 0 Const_11 01 Start the performance counters. 1 Const_22 10 Stop the performance counters. 2 Const_33 11 Toggle the performance counter control i.e. start it if it is currently stopped stop it if it is currently running . 3 SWEVT CPUx Software Debug Event resetvalue={Debug Reset:0x0} 64784 32 0 4294967295 EVTA Event Associated EVTA. Debug Action associated with the Debug Event 0 2 read-write Const_00 000 BOD 0 Disabled. BOD 1 Disabled. 0 Const_11 001 BOD 0 Pulse BRKOUT Signal. BOD 1 None. 1 Const_22 010 BOD 0 Halt and pulse BRKOUT Signal. BOD 1 Halt. 2 Const_33 011 BOD 0 Breakpoint trap and pulse BRKOUT Signal. BOD 1 Breakpoint trap. 3 Const_44 100 BOD 0 Breakpoint interrupt 0 and pulse BRKOUT Signal. BOD 1 Breakpoint interrupt 0. 4 Const_55 101 BOD 0 If implemented breakpoint interrupt 1 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 1. If not implemented None. 5 Const_66 110 BOD 0 If implemented breakpoint interrupt 2 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 2. If not implemented None. 6 Const_77 111 BOD 0 If implemented breakpoint interrupt 3 and pulse BRKOUT Signal. BOD 1 If implemented breakpoint interrupt 3. If not implemented None. 7 BBM Break Before Make BBM or Break After Make BAM Selection BBM 3 3 read-write Const_00 0 Break after make BAM . 0 Const_11 1 Break before make BBM . 1 BOD Breakout Disable BOD 4 4 read-write Const_00 0 BRKOUT signal asserted according to the action specified in the EVTA field. 0 Const_11 1 BRKOUT signal not asserted. This takes priority over any assertion generated by the EVTA field. 1 SUSP CDC Suspend Out Signal State SUSP. Value to be assigned to the CDC suspend out signal when the event is raised. 5 5 read-write CNT Counter CNT. When this event occurs adjust the control of the performance counters in task mode as follows 6 7 read-write Const_00 00 No change. 0 Const_11 01 Start the performance counters. 1 Const_22 10 Stop the performance counters. 2 Const_33 11 Toggle the performance counter control i.e. start it if it is currently stopped stop it if it is currently running . 3 TRIG_ACC CPUx TriggerAddressx resetvalue={Debug Reset:0x0} 64816 32 0 4294967295 T0 Trigger 0 T0. active since last cleared 0 0 read-only T1 Trigger 1 T1. active since last cleared 1 1 read-only T2 Trigger 2 T2. active since last cleared 2 2 read-only T3 Trigger 3 T3. active since last cleared 3 3 read-only T4 Trigger 4 T4. active since last cleared 4 4 read-only T5 Trigger 5 T5. active since last cleared 5 5 read-only T6 Trigger 6 T6. active since last cleared 6 6 read-only T7 Trigger 7 T7. active since last cleared 7 7 read-only DMS CPUx Debug Monitor Start Address resetvalue={Application Reset:0x0} 64832 32 0 0 DMSValue Debug Monitor Start Address DMSValue. The address at which monitor code execution begins when a breakpoint trap is taken. 1 31 read-write DCX CPUx Debug Context Save Area Pointer resetvalue={Application Reset:0x0} 64836 32 0 0 DCXValue Debug Context Save Area Pointer DCXValue. Address where the debug context is stored following a breakpoint trap. 6 31 read-write DBGTCR CPUx Debug Trap Control Register resetvalue={Application Reset:0x1} 64840 32 1 4294967295 DTA Debug Trap Active Bit DTA. A breakpoint trap may only be taken in the condition DTA 0. Taking a breakpoint trap sets the DTA bit to one. Further breakpoint traps are therefore disabled until such time as the breakpoint trap handler clears the DTA bit or until the breakpoint trap handler terminates with a RFM. 0 0 read-write Const_00 0 No breakpoint trap is active. 0 Const_11 1 A breakpoint Trap is active 1 SEGEN CPUx SRI Error Generation Register resetvalue={Application Reset:0x0} 4144 32 0 4294967295 ADFLIP Address ECC Bit Flip ADFLIP. SRI address ECC Bits to be flipped on the next read or write transaction from the DMI when enabled by AE. 0 7 read-write Const_00 0 No Flip 0 Const_11 1 Flip 1 ADTYPE Type of error ADTYPE 8 9 read-write Const_00 00 Data Master Address Phase 0 Const_11 01 Data Master Write Data 1 Const_22 10 Data Slave Read Data 2 AE Activate Error Enable AE. Enabled the selective inverting of SRI ECC packet bits defined by ADFLIP. This bit will be cleared by hardware after the next SRI read or write transaction from the DMI. 31 31 read-write Const_00 0 Not Enabled 0 Const_11 1 Enabled 1 DCON2 CPUx Data Control Register 2 resetvalue={Application Reset:0x0} 36864 32 0 0 DCACHE_SZE Data Cache Size DCACHE SZE. In KBytes 0 15 read-only DSCRATCH_SZE Data Scratch Size DSCRATCH SZE. In KBytes 16 31 read-only DSTR CPUx Data Synchronous Trap Register resetvalue={Application Reset:0x0} 36880 32 0 4294967295 SRE Scratch Range Error SRE. A scratch Range Error occurs whenever an access to the data scratch is outside the range of the SRAM. 0 0 read-write GAE Global Address Error GAE. Load or store to local code scratch address outside of the lower 1MByte. 1 1 read-write LBE Load Bus Error LBE. A Load Bus Error will be set whenever the SRI flags an error due a load from external memory. 2 2 read-write DRE Local DLMU Range Error DRE. A DLMU Range Error occurs whenever an access to the local DLMU region is outside the physically implemented memory. 3 3 read-write CRE Cache Refill Error CRE. A Cache Refill Error will be set whenever the SRI flags an error due a cache refill from external memory. 6 6 read-write DTME DTAG MSIST Error DTME. Access to memory mapped DTAG range outside of physically implemented memory. 14 14 read-write LOE Load Overlay Error LOE. Load to invalid overlay address. 15 15 read-write SDE Segment Difference Error SDE. Load or store access where base address is in different segment to access address. 16 16 read-write SCE Segment Crossing Error SCE. Load or store access across segment boundary. 17 17 read-write CAC CSFR Access Error CAC. Load or store to local CSFR space. 18 18 read-write MPE Memory Protection Error MPE. Data access violating memory protection. 19 19 read-write CLE Context Location Error CLE. Context operation to invalid location. 20 20 read-write ALN Alignment Error ALN. Data access causing alignment error. 24 24 read-write DATR CPUx Data Asynchronous Trap Register resetvalue={Application Reset:0x0} 36888 32 0 4294967295 SBE Store Bus Error SBE 3 3 read-write CWE Cache Writeback Error CWE 9 9 read-write CFE Cache Flush Error CFE 10 10 read-write SOE Store Overlay Error SOE 14 14 read-write DEADD CPUx Data Error Address Register resetvalue={Application Reset:0x0} 36892 32 0 4294967295 ERROR_ADDRESS Error Address ERROR ADDRESS 0 31 read-only DCON0 CPUx Data Memory Control Register resetvalue={Application Reset:0x2} 36928 32 2 4294967295 DCBYP Data Cache Bypass DCBYP 1 1 read-write Const_00 0 DCache DRB enabled 0 Const_11 1 DCache DRB Bypass disabled 1 PSTR CPUx Program Synchronous Trap Register resetvalue={Application Reset:0x0} 37376 32 0 4294967295 FRE Fetch Range Error FRE. A Fetch Range Error occurs whenever an access to the Program Scratch is outside the range of the SRAM. 0 0 read-write FBE Fetch Bus Error FBE. A Fetch bus error will be set whenever the SRI flags an error due a fetch from external memory. This will be set for both direct fetches from the bus and for cache refills. 2 2 read-write FPE Fetch Peripheral Error FPE. A Fetch peripheral error will be flagged whenever a fetch is attempted to peripheral space. 12 12 read-write FME Fetch MSIST Error FME. During SIST mode a fetch from the PTAG will cause a PSE trap to occur. 14 14 read-write PCON1 CPUx Program Control 1 resetvalue={Application Reset:0x0} 37380 32 0 4294967295 PCINV Program Cache Invalidate PCINV 0 0 read-write Const_00 0 Write No effect normal instruction cache operation. Read Normal operation instruction cache available 0 Const_11 1 Write Initiate invalidation of entire instruction cache. Read Instruction cache invalidation in progress. Instruction cache unavailable. 1 PBINV Program Buffer Invalidate PBINV. Write Operation This field returns 0 when read. 1 1 read-write Const_00 0 Write No effect. Normal program line buffer operation. 0 Const_11 1 Write Invalidate the program line buffer. 1 PCON2 CPUx Program Control 2 resetvalue={Application Reset:0x0} 37384 32 0 0 PCACHE_SZE Program Cache Size ICACHE in KBytes PCACHE SZE. In KBytes 0 15 read-only PSCRATCH_SZE Program Scratch Size in KBytes PSCRATCH SZE. In KBytes 16 31 read-only PCON0 CPUx Program Control 0 resetvalue={Application Reset:0x2} 37388 32 2 4294967295 PCBYP Program Cache Bypass PCBYP 1 1 read-write Const_00 0 Cache enabled 0 Const_11 1 Cache bypass disabled 1