MSPM0G350x 1.0 8 32 GPIOB 1.0 PERIPHERALREGION GPIOB 0x400A2000 0x0 0x1F00 registers FSUB_0 Subsciber Port 0 0x400 0x20 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0 4 UNCONNECTED A value of 0 specifies that the event is not connected 0 PWREN Power enable 0x800 0x20 read-write ENABLE Enable the power 0 1 DISABLE Disable Power 0 ENABLE Enable Power 1 RSTCTL Reset Control 0x804 0x20 write-only RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 1 1 write-only NOP Writing 0 has no effect 0 CLR Clear reset sticky bit 1 RESETASSERT Assert reset to the peripheral 0 1 write-only NOP Writing 0 has no effect 0 ASSERT Assert reset 1 STAT Status Register 0x814 0x20 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 16 1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0 RESET The peripheral was reset since the last bit clear 1 TEST_REG_0 Reg Description 0x800 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 3 0x18 X,Y,Z TEST_NESTED_CLUSTER_0[%s] 0x1000 TEST_NC_REG Reg Description 0x0 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 TEST_REG_1 Reg Description 0x818 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 3 0x18 X,Y,Z TEST_NESTED_CLUSTER_1[%s] 0x1018 TEST_NC_REG Reg Description 0x0 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 TEST_REG_2 Reg Description 0x830 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 3 0x18 X,Y,Z TEST_NESTED_CLUSTER_2[%s] 0x1030 TEST_NC_REG Reg Description 0x0 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 TEST_REG_3 Reg Description 0x848 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 3 0x18 X,Y,Z TEST_NESTED_CLUSTER_3[%s] 0x1048 TEST_NC_REG Reg Description 0x0 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 TEST_REG_A Reg Description 0x800 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 3 0x18 X,Y,Z TEST_NESTED_CLUSTER_A[%s] 0x1000 TEST_NC_REG Reg Description 0x0 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 TEST_REG_B Reg Description 0x818 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 3 0x18 X,Y,Z TEST_NESTED_CLUSTER_B[%s] 0x1018 TEST_NC_REG Reg Description 0x0 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 TEST_REG_C Reg Description 0x830 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 3 0x18 X,Y,Z TEST_NESTED_CLUSTER_C[%s] 0x1030 TEST_NC_REG Reg Description 0x0 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 TEST_REG_D Reg Description 0x848 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 3 0x18 X,Y,Z TEST_NESTED_CLUSTER_D[%s] 0x1048 TEST_NC_REG Reg Description 0x0 0x20 read-write ENABLE Enable the reg 0 1 DISABLE Disable regster 0 ENABLE Enable register 1 DAC0 1.0 PERIPHERALREGION DAC 0x40018000 0x0 0x1F00 registers DAC0_IIDX_0 Interrupt index 0x1020 0x20 read-only 0x00000000 STAT Interrupt index status 0 4 read-only NO_INTR No pending interrupt 0 MODRDYIFG Module ready interrupt 2 FIFOFULLIFG FIFO full interrupt 9 FIFO1B4IFG FIFO one fourth empty interrupt 10 FIFO1B2IFG FIFO half empty interrupt 11 FIFO3B4IFG FIFO three fourth empty interrupt 12 FIFOEMPTYIFG FIFO empty interrupt 13 FIFOURUNIFG FIFO underrun interrupt 14 DMADONEIFG DMA done interrupt 15 DAC0_IMASK_0 Interrupt mask 0x1028 0x20 read-write 0x00000000 MODRDYIFG Masks MODRDYIFG 1 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 FIFO1B2IFG Masks FIFO1B2IFG 10 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 FIFOEMPTYIFG Masks FIFOEMPTYIFG 12 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 FIFO1B4IFG Masks FIFO1B4IFG 9 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 FIFO3B4IFG Masks FIFO3B4IFG 11 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 FIFOFULLIFG Masks FIFOFULLIFG 8 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 FIFOURUNIFG Masks FIFOURUNIFG 13 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 DMADONEIFG Masks DMADONEIFG 14 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 DAC0_IIDX_1 Interrupt index 0x104C 0x20 read-only 0x00000000 STAT Interrupt index status 0 4 read-only NO_INTR No pending interrupt 0 MODRDYIFG Module ready interrupt 2 FIFOFULLIFG FIFO full interrupt 9 FIFO1B4IFG FIFO one fourth empty interrupt 10 FIFO1B2IFG FIFO half empty interrupt 11 FIFO3B4IFG FIFO three fourth empty interrupt 12 FIFOEMPTYIFG FIFO empty interrupt 13 FIFOURUNIFG FIFO underrun interrupt 14 DMADONEIFG DMA done interrupt 15 DAC0_IMASK_1 Interrupt mask 0x1054 0x20 read-write 0x00000000 MODRDYIFG Masks MODRDYIFG 1 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 FIFO1B2IFG Masks FIFO1B2IFG 10 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 FIFOEMPTYIFG Masks FIFOEMPTYIFG 12 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 FIFO1B4IFG Masks FIFO1B4IFG 9 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 FIFO3B4IFG Masks FIFO3B4IFG 11 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 FIFOFULLIFG Masks FIFOFULLIFG 8 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 FIFOURUNIFG Masks FIFOURUNIFG 13 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 DMADONEIFG Masks DMADONEIFG 14 1 CLR Interrupt is masked out 0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 1 CRC 1.0 PERIPHERALREGION CRC 0x40440000 0x0 0x2000 registers 1 0x18 TEST_CLUSTER_WITH_REG_ARRAY_MEMBER[%s] 0x800 CRC_PWREN Power enable 0x0 0x20 read-write 0x00000000 ENABLE Enable the power 0 1 read-write DISABLE Disable Power 0 ENABLE Enable Power 1 512 0x4 0-511 TEST_REGISTER_ARRAY_IN_CLUSTER_%s CRC Input Data Array Register 0x1800 0x20 write-only 0x00000000 0xFFFFFFFF DATA Input Data 0 32 write-only