MSPM0G350x GPIOB GPIOB 1.0 PERIPHERALREGION 0x400A2000 0x0 0x1F00 registers GPIOB_FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x4 UNCONNECTED A value of 0 specifies that the event is not connected 0x0 4 24 TEST_CLUSTER_NO_INDEX[%s] 0x800 TEST_REG Reg Description 0x0 32 read-write ENABLE Enable the reg 0x0 0x1 DISABLE Disable regster 0x0 ENABLE Enable register 0x1 3 24 X,Y,Z TEST_NESTED_CLUSTER%s 0x800 TEST_NC_REG Reg Description 0x0 32 read-write ENABLE Enable the reg 0x0 0x1 DISABLE Disable regster 0x0 ENABLE Enable register 0x1 4 24 A,B,C,D TEST_CLUSTER_WITH_INDEX%s 0x800 TEST_REG Reg Description 0x0 32 read-write ENABLE Enable the reg 0x0 0x1 DISABLE Disable regster 0x0 ENABLE Enable register 0x1 3 24 X,Y,Z TEST_NESTED_CLUSTER[%s] 0x800 TEST_NC_REG Reg Description 0x0 32 read-write ENABLE Enable the reg 0x0 0x1 DISABLE Disable regster 0x0 ENABLE Enable register 0x1 1 24 0 GPIOB_GPRCM[%s] 0x800 GPIOB_PWREN Power enable 0x0 32 read-write ENABLE Enable the power 0x0 0x1 DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 GPIOB_RSTCTL Reset Control 0x4 32 write-only RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only NOP Writing 0 has no effect 0x0 CLR Clear reset sticky bit 0x1 RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only NOP Writing 0 has no effect 0x0 ASSERT Assert reset 0x1 GPIOB_STAT Status Register 0x14 32 read-only RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only NORES The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 0x0 RESET The peripheral was reset since the last bit clear 0x1 DAC0 DAC 1.0 PERIPHERALREGION 0x40018000 0x0 0x1F00 registers 2 44 0,1 DAC0_INT_EVENT[%s] 0x1020 DAC0_IIDX Interrupt index 0x0 32 read-only 0x00000000 STAT Interrupt index status 0x0 0x4 read-only NO_INTR No pending interrupt 0x0 MODRDYIFG Module ready interrupt 0x2 FIFOFULLIFG FIFO full interrupt 0x9 FIFO1B4IFG FIFO one fourth empty interrupt 0xA FIFO1B2IFG FIFO half empty interrupt 0xB FIFO3B4IFG FIFO three fourth empty interrupt 0xC FIFOEMPTYIFG FIFO empty interrupt 0xD FIFOURUNIFG FIFO underrun interrupt 0xE DMADONEIFG DMA done interrupt 0xF DAC0_IMASK Interrupt mask 0x8 32 read-write 0x00000000 MODRDYIFG Masks MODRDYIFG 0x1 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFO1B2IFG Masks FIFO1B2IFG 0xA 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFOEMPTYIFG Masks FIFOEMPTYIFG 0xC 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFO1B4IFG Masks FIFO1B4IFG 0x9 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFO3B4IFG Masks FIFO3B4IFG 0xB 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFOFULLIFG Masks FIFOFULLIFG 0x8 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 FIFOURUNIFG Masks FIFOURUNIFG 0xD 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 DMADONEIFG Masks DMADONEIFG 0xE 0x1 CLR Interrupt is masked out 0x0 SET Interrupt will request an interrupt service routine and corresponding bit in MIS will be set 0x1 CRC CRC 1.0 PERIPHERALREGION 0x40440000 0x0 0x2000 registers 1 24 0 TEST_CLUSTER_WITH_REG_ARRAY_MEMBER[%s] 0x800 CRC_PWREN Power enable 0x0 32 read-write 0x00000000 ENABLE Enable the power 0x0 0x1 read-write DISABLE Disable Power 0x0 ENABLE Enable Power 0x1 512 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,288,289,290,291,292,293,294,295,296,297,298,299,300,301,302,303,304,305,306,307,308,309,310,311,312,313,314,315,316,317,318,319,320,321,322,323,324,325,326,327,328,329,330,331,332,333,334,335,336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,368,369,370,371,372,373,374,375,376,377,378,379,380,381,382,383,384,385,386,387,388,389,390,391,392,393,394,395,396,397,398,399,400,401,402,403,404,405,406,407,408,409,410,411,412,413,414,415,416,417,418,419,420,421,422,423,424,425,426,427,428,429,430,431,432,433,434,435,436,437,438,439,440,441,442,443,444,445,446,447,448,449,450,451,452,453,454,455,456,457,458,459,460,461,462,463,464,465,466,467,468,469,470,471,472,473,474,475,476,477,478,479,480,481,482,483,484,485,486,487,488,489,490,491,492,493,494,495,496,497,498,499,500,501,502,503,504,505,506,507,508,509,510,511 TEST_REGISTER_ARRAY_IN_CLUSTER_%s CRC Input Data Array Register 0x1800 32 write-only 0x00000000 0xffffffff DATA Input Data 0x0 0x20 write-only