; this file was created with wlalink by ville helin . ; wla symbolic information for "/home/runner/work/mooneye-test-suite/mooneye-test-suite/build/acceptance/ppu/lcdon_timing-GS.gb". [information] version 2 [labels] 01:4d0d clear_oam 01:4d17 clear_vram 01:4ccc disable_lcd_safe 01:4cd2 disable_lcd_safe@wait_ly_0 01:4d2b memcpy 01:4d34 memset 01:4cea print_hex4 01:4d21 print_hex8 01:4d44 print_inline_string 01:4cf6 print_load_font 01:4d02 print_newline 01:4d3d print_string 01:4c38 quit 01:4c4d quit@cb_return 01:4c52 quit@wait_ly_1 01:4c58 quit@wait_ly_2 01:4c5e quit@wait_ly_3 01:4c64 quit@wait_ly_4 01:4c6e quit@success 01:4c95 quit@failure 01:4cb4 quit@halt 01:4cb5 quit@halt_execution_0 01:4cb8 reset_screen 01:4cdb serial_send_byte 01:4000 font 00:0150 main 00:015c test_ly 00:0168 test_stat_lyc0 00:0177 test_stat_lyc1 00:0187 test_oam_access 00:0193 test_vram_access 00:019f test_finish 00:01a6 test_finish@quit_inline_1 01:4ac9 cycle_counts 01:4ae1 expect_ly 01:4afc expect_stat_lyc0 01:4b1f expect_stat_lyc1 01:4b42 expect_oam_access 01:4b65 expect_vram_access 01:4b89 verify_results 01:4ba0 verify_fail 01:4bc1 verify_fail@quit_inline_2 00:ff80 hram.pass1_results 00:ff88 hram.pass2_results 00:ff90 hram.pass3_results 00:ff98 hram.fail_round 00:ff99 hram.fail_expect 00:ff9a hram.fail_actual 00:ff9b hram.fail_str 00:ff9b hram.fail_str_l 00:ff9c hram.fail_str_h 01:47f0 test_passes 01:47f0 test_pass1 01:48e2 test_pass2 01:49d5 test_pass3 00:ff80 RAM_USAGE_SLOT_4_BANK_0_START 00:ff9c RAM_USAGE_SLOT_4_BANK_0_END [definitions] 0000000a _sizeof_clear_oam 0000000a _sizeof_clear_vram 0000000f _sizeof_disable_lcd_safe 00000009 _sizeof_memcpy 00000009 _sizeof_memset 0000000c _sizeof_print_hex4 0000000a _sizeof_print_hex8 00000006 _sizeof_print_inline_string 0000000c _sizeof_print_load_font 0000000b _sizeof_print_newline 00000007 _sizeof_print_string 00000080 _sizeof_quit 00000014 _sizeof_reset_screen 0000000f _sizeof_serial_send_byte 000007f0 _sizeof_font 00000018 _sizeof_cycle_counts 0000001b _sizeof_expect_ly 00000023 _sizeof_expect_stat_lyc0 00000023 _sizeof_expect_stat_lyc1 00000023 _sizeof_expect_oam_access 00000024 _sizeof_expect_vram_access 00000017 _sizeof_verify_results 00000098 _sizeof_verify_fail 00000008 _sizeof_hram.pass1_results 00000008 _sizeof_hram.pass2_results 00000008 _sizeof_hram.pass3_results 00000001 _sizeof_hram.fail_round 00000001 _sizeof_hram.fail_expect 00000001 _sizeof_hram.fail_actual 00000002 _sizeof_hram.fail_str 00000001 _sizeof_hram.fail_str_l 00000001 _sizeof_hram.fail_str_h 00000000 _sizeof_test_passes 000000f2 _sizeof_test_pass1 000000f3 _sizeof_test_pass2 000000f4 _sizeof_test_pass3 0000001c _sizeof_RAM_USAGE_SLOT_4_BANK_0_START 0000000c _sizeof_main 0000000c _sizeof_test_ly 0000000f _sizeof_test_stat_lyc0 00000010 _sizeof_test_stat_lyc1 0000000c _sizeof_test_oam_access 0000000c _sizeof_test_vram_access