; this file was created with wlalink by ville helin . ; wla symbolic information for "/home/runner/work/mooneye-test-suite/mooneye-test-suite/build/misc/ppu/vblank_stat_intr-C.gb". [information] version 2 [labels] 01:47f0 check_asserts_cb 01:4842 check_asserts_cb@check_asserts 01:4864 check_asserts_cb@fail0 01:4870 check_asserts_cb@ok0 01:487a check_asserts_cb@skip0 01:4885 check_asserts_cb@out0 01:489c check_asserts_cb@fail1 01:48a8 check_asserts_cb@ok1 01:48b2 check_asserts_cb@skip1 01:48bd check_asserts_cb@out1 01:48dd check_asserts_cb@fail2 01:48e9 check_asserts_cb@ok2 01:48f3 check_asserts_cb@skip2 01:48fe check_asserts_cb@out2 01:4915 check_asserts_cb@fail3 01:4921 check_asserts_cb@ok3 01:492b check_asserts_cb@skip3 01:4936 check_asserts_cb@out3 01:4956 check_asserts_cb@fail4 01:4962 check_asserts_cb@ok4 01:496c check_asserts_cb@skip4 01:4977 check_asserts_cb@out4 01:498e check_asserts_cb@fail5 01:499a check_asserts_cb@ok5 01:49a4 check_asserts_cb@skip5 01:49af check_asserts_cb@out5 01:49cf check_asserts_cb@fail6 01:49db check_asserts_cb@ok6 01:49e5 check_asserts_cb@skip6 01:49f0 check_asserts_cb@out6 01:4a07 check_asserts_cb@fail7 01:4a13 check_asserts_cb@ok7 01:4a1d check_asserts_cb@skip7 01:4a28 check_asserts_cb@out7 00:ff80 hram.regs_save 00:ff80 hram.regs_save.reg_f 00:ff81 hram.regs_save.reg_a 00:ff82 hram.regs_save.reg_c 00:ff83 hram.regs_save.reg_b 00:ff84 hram.regs_save.reg_e 00:ff85 hram.regs_save.reg_d 00:ff86 hram.regs_save.reg_l 00:ff87 hram.regs_save.reg_h 00:ff88 hram.regs_flags 00:ff89 hram.regs_assert 00:ff89 hram.regs_assert.reg_f 00:ff8a hram.regs_assert.reg_a 00:ff8b hram.regs_assert.reg_c 00:ff8c hram.regs_assert.reg_b 00:ff8d hram.regs_assert.reg_e 00:ff8e hram.regs_assert.reg_d 00:ff8f hram.regs_assert.reg_l 00:ff90 hram.regs_assert.reg_h 01:4b85 clear_vram 01:4b44 disable_lcd_safe 01:4b4a disable_lcd_safe@wait_ly_0 01:4b99 memcpy 01:4ba2 memset 01:4b62 print_hex4 01:4b8f print_hex8 01:4bb2 print_inline_string 01:4b6e print_load_font 01:4b7a print_newline 01:4a2b print_reg_dump 01:4bab print_string 01:4ab0 quit 01:4ac5 quit@cb_return 01:4aca quit@wait_ly_1 01:4ad0 quit@wait_ly_2 01:4ad6 quit@wait_ly_3 01:4adc quit@wait_ly_4 01:4ae6 quit@success 01:4b0d quit@failure 01:4b2c quit@halt 01:4b2d quit@halt_execution_0 01:4b30 reset_screen 01:4b53 serial_send_byte 01:4000 font 00:0150 main 00:016c fail_halt 00:0173 fail_halt@quit_inline_1 00:0181 test_round1 00:018d test_round1@wait_ly_5 00:01d8 finish_round1 00:01f6 test_round2 00:0202 test_round2@wait_ly_6 00:024e finish_round2 00:0270 test_round3 00:027c test_round3@wait_ly_7 00:02c6 finish_round3 00:02e4 test_round4 00:02f0 test_round4@wait_ly_8 00:033b finish_round4 00:033d test_finish 00:ff91 intr_vec_vblank 00:ff94 intr_vec_stat 00:ff97 round1 00:ff98 round2 00:ff99 round3 00:ff80 RAM_USAGE_SLOT_4_BANK_0_START 00:ff99 RAM_USAGE_SLOT_4_BANK_0_END [definitions] 0000023b _sizeof_check_asserts_cb 00000008 _sizeof_hram.regs_save 00000001 _sizeof_hram.regs_save.reg_f 00000001 _sizeof_hram.regs_save.reg_a 00000001 _sizeof_hram.regs_save.reg_c 00000001 _sizeof_hram.regs_save.reg_b 00000001 _sizeof_hram.regs_save.reg_e 00000001 _sizeof_hram.regs_save.reg_d 00000001 _sizeof_hram.regs_save.reg_l 00000001 _sizeof_hram.regs_save.reg_h 00000001 _sizeof_hram.regs_flags 00000008 _sizeof_hram.regs_assert 00000001 _sizeof_hram.regs_assert.reg_f 00000001 _sizeof_hram.regs_assert.reg_a 00000001 _sizeof_hram.regs_assert.reg_c 00000001 _sizeof_hram.regs_assert.reg_b 00000001 _sizeof_hram.regs_assert.reg_e 00000001 _sizeof_hram.regs_assert.reg_d 00000001 _sizeof_hram.regs_assert.reg_l 00000001 _sizeof_hram.regs_assert.reg_h 0000000a _sizeof_clear_vram 0000000f _sizeof_disable_lcd_safe 00000009 _sizeof_memcpy 00000009 _sizeof_memset 0000000c _sizeof_print_hex4 0000000a _sizeof_print_hex8 00000006 _sizeof_print_inline_string 0000000c _sizeof_print_load_font 0000000b _sizeof_print_newline 00000085 _sizeof_print_reg_dump 00000007 _sizeof_print_string 00000080 _sizeof_quit 00000014 _sizeof_reset_screen 0000000f _sizeof_serial_send_byte 000007f0 _sizeof_font 00000003 _sizeof_intr_vec_vblank 00000003 _sizeof_intr_vec_stat 00000001 _sizeof_round1 00000001 _sizeof_round2 00000001 _sizeof_round3 00000019 _sizeof_RAM_USAGE_SLOT_4_BANK_0_START 0000001c _sizeof_main 00000015 _sizeof_fail_halt 00000057 _sizeof_test_round1 0000001e _sizeof_finish_round1 00000058 _sizeof_test_round2 00000022 _sizeof_finish_round2 00000056 _sizeof_test_round3 0000001e _sizeof_finish_round3 00000057 _sizeof_test_round4 00000002 _sizeof_finish_round4