## This is a most popular repository list for VHDL sorted by number of stars
|STARS|FORKS|ISSUES|LAST COMMIT|NAME/PLACE|DESCRIPTION|
| --- | --- | --- | --- | --- | --- |
| 1364 | 238 | 266 | 3 days ago | [ghdl](https://github.com/ghdl/ghdl)/1 | VHDL 2008/93/87 simulator |
| 1126 | 409 | 1 | 6 days ago | [aws-fpga](https://github.com/aws/aws-fpga)/2 | Official repository of the AWS EC2 FPGA Hardware and Software Development Kit |
| 1037 | 518 | 18 | 7 years ago | [Open-Source-FPGA-Bitcoin-Miner](https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner)/3 | A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards. |
| 763 | 38 | 1 | 5 years ago | [FPGA_Webserver](https://github.com/hamsternz/FPGA_Webserver)/4 | A work-in-progress for what is to be a software-free web server for static content. |
| 520 | 122 | 7 | 6 years ago | [gplgpu](https://github.com/asicguy/gplgpu)/5 | GPL v3 2D/3D graphics engine in verilog |
| 461 | 177 | 132 | a month ago | [vunit](https://github.com/VUnit/vunit)/6 | VUnit is a unit testing framework for VHDL/SystemVerilog |
| 400 | 62 | 13 | 6 months ago | [gcvideo](https://github.com/ikorb/gcvideo)/7 | GameCube Digital AV converter |
| 389 | 173 | 5 | 3 years ago | [parallella-hw](https://github.com/parallella/parallella-hw)/8 | Parallella board design files |
| 387 | 85 | 31 | 1 year, 5 months ago | [PoC](https://github.com/VLSI-EDA/PoC)/9 | IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany |
| 386 | 143 | 3 | 3 years ago | [parallella-examples](https://github.com/parallella/parallella-examples)/10 | Community created parallella projects |
| 383 | 51 | 8 | 9 hours ago | [neorv32](https://github.com/stnolting/neorv32)/11 | A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL. |
| 354 | 113 | 10 | 2 years ago | [dsi-shield](https://github.com/twlostow/dsi-shield)/12 | Arduino MIPI DSI Shield |
| 353 | 56 | 14 | 4 days ago | [nvc](https://github.com/nickg/nvc)/13 | VHDL compiler and simulator |
| 341 | 91 | 22 | 11 months ago | [f32c](https://github.com/f32c/f32c)/14 | A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz |
| 323 | 42 | 1 | a month ago | [awesome-model-quantization](https://github.com/htqin/awesome-model-quantization)/15 | A list of papers, docs, codes about model quantization. This repo is aimed to provide the info for model quantization research, we are continuously improving the project. Welcome to PR the works (papers, repositories) that are missed by the repo. |
| 316 | 39 | 12 | 14 hours ago | [hal](https://github.com/emsec/hal)/16 | HAL – The Hardware Analyzer |
| 278 | 82 | 2 | 2 years ago | [CSI2Rx](https://github.com/gatecat/CSI2Rx)/17 | Open Source 4k CSI-2 Rx core for Xilinx FPGAs |
| 270 | 34 | 6 | 1 year, 7 months ago | [opl3_fpga](https://github.com/gtaylormb/opl3_fpga)/18 | Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer |
| 256 | 20 | 0 | 1 year, 1 month ago | [forth-cpu](https://github.com/howerj/forth-cpu)/19 | A Forth CPU and System on a Chip, based on the J1, written in VHDL |
| 227 | 37 | 8 | a month ago | [a2i](https://github.com/openpower-cores/a2i)/20 | None |
| 214 | 25 | 0 | 5 months ago | [bladeRF-wiphy](https://github.com/Nuand/bladeRF-wiphy)/21 | bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem |
| 205 | 65 | 13 | 15 days ago | [UVVM](https://github.com/UVVM/UVVM)/22 | UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement.    Community forum: https://forum.uvvm.org/    UVVM.org: https://uvvm.org/ |
| 202 | 37 | 2 | 5 years ago | [FPGA_DisplayPort](https://github.com/hamsternz/FPGA_DisplayPort)/23 | An implementation of DisplayPort protocol for FPGAs |
| 200 | 19 | 17 | 3 months ago | [ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin)/24 | VHDL synthesis (based on ghdl) |
| 189 | 31 | 3 | 3 months ago | [potato](https://github.com/skordal/potato)/25 | A simple RISC-V processor for use in FPGA designs. |
| 167 | 49 | 5 | 3 years ago | [hardh264](https://github.com/bcattle/hardh264)/26 | A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx. |
| 167 | 32 | 1 | 2 years ago | [tinyTPU](https://github.com/jofrfu/tinyTPU)/27 | Implementation of a Tensor Processing Unit for embedded systems and the IoT. |
| 166 | 20 | 4 | 3 months ago | [neo430](https://github.com/stnolting/neo430)/28 | A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL. |
| 154 | 26 | 13 | 3 months ago | [C64-Video-Enhancement](https://github.com/c0pperdragon/C64-Video-Enhancement)/29 | Component video modification for the C64 8-bit computer |
| 154 | 44 | 1 | 3 years ago | [vna2](https://github.com/Ttl/vna2)/30 | Second version of homemade 30 MHz - 6 GHz VNA |
| 151 | 22 | 14 | 14 days ago | [fletcher](https://github.com/abs-tudelft/fletcher)/31 | Fletcher: A framework to integrate FPGA accelerators with Apache Arrow |
| 149 | 42 | 19 | 3 months ago | [OSVVM](https://github.com/OSVVM/OSVVM)/32 | OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ... |
| 149 | 57 | 217 | 11 days ago | [mega65-core](https://github.com/MEGA65/mega65-core)/33 | MEGA65 FPGA core |
| 146 | 61 | 0 | 4 years ago | [VHDL_Lib](https://github.com/xesscorp/VHDL_Lib)/34 | Library of VHDL components that are useful in larger designs. |
| 143 | 18 | 0 | 5 years ago | [space-invaders-vhdl](https://github.com/fabioperez/space-invaders-vhdl)/35 | Space Invaders game implemented with VHDL |
| 132 | 58 | 2 | 1 year, 7 months ago | [fmcw3](https://github.com/Ttl/fmcw3)/36 | Two RX-channel 6 GHz FMCW radar design files |
| 130 | 27 | 19 | 2 months ago | [rust_hdl](https://github.com/VHDL-LS/rust_hdl)/37 | None |
| 122 | 23 | 1 | 6 years ago | [zpu](https://github.com/zylin/zpu)/38 | The Zylin ZPU |
| 120 | 13 | 1 | 10 months ago | [hdl4fpga](https://github.com/hdl4fpga/hdl4fpga)/39 | VHDL library 4 FPGAs |
| 119 | 46 | 8 | 2 years ago | [Artix-7-HDMI-processing](https://github.com/hamsternz/Artix-7-HDMI-processing)/40 | Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA |
| 117 | 69 | 15 | 2 years ago | [Cosmos-plus-OpenSSD](https://github.com/Cosmos-OpenSSD/Cosmos-plus-OpenSSD)/41 | Cosmos OpenSSD + Hardware and Software source distribution |
| 115 | 24 | 0 | 5 years ago | [neppielight](https://github.com/drxzcl/neppielight)/42 | FPGA-based HDMI ambient lighting |
| 114 | 23 | 5 | 4 months ago | [OpenXenium](https://github.com/Ryzee119/OpenXenium)/43 | OpenXenium - Open Source Xenium Modchip CPLD replacement project for the Original Xbox |
| 113 | 14 | 0 | 5 months ago | [nexys4ddr](https://github.com/MJoergen/nexys4ddr)/44 | Various projects for the Nexys4DDR board from Digilent |
| 112 | 34 | 4 | 3 years ago | [vhdl-extras](https://github.com/kevinpt/vhdl-extras)/45 | Flexible VHDL library |
| 111 | 4 | 5 | 1 year, 1 month ago | [FPGBA](https://github.com/RobertPeip/FPGBA)/46 | GBA on FPGA |
| 109 | 27 | 2 | 3 months ago | [ZYNQ7010-7020_AD9363](https://github.com/kangyuzhe666/ZYNQ7010-7020_AD9363)/47 | 基于ZYNQ+AD9363的开源SDR硬件 |
| 105 | 34 | 0 | 1 year, 8 months ago | [XJTU-Tripler](https://github.com/venturezhao/XJTU-Tripler)/48 | This repository is the backup of XJTU-Tripler project, participating dac19 system design contest |
| 102 | 10 | 0 | 9 months ago | [RPU](https://github.com/Domipheus/RPU)/49 | Basic RISC-V CPU implementation in VHDL. |
| 101 | 48 | 20 | 6 days ago | [SNES_MiSTer](https://github.com/MiSTer-devel/SNES_MiSTer)/50 | SNES for MiSTer |
| 100 | 27 | 0 | 5 years ago | [HDMI2USB-jahanzeb-firmware](https://github.com/timvideos/HDMI2USB-jahanzeb-firmware)/51 | Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project |
| 98 | 11 | 1 | 4 years ago | [TPU](https://github.com/Domipheus/TPU)/52 | TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+. |
| 97 | 41 | 0 | 4 years ago | [ethernet_mac](https://github.com/yol/ethernet_mac)/53 | Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL |
| 93 | 53 | 10 | 22 days ago | [patmos](https://github.com/t-crest/patmos)/54 | Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project |
| 91 | 11 | 2 | 2 years ago | [freezing-spice](https://github.com/inforichland/freezing-spice)/55 | A pipelined RISCV implementation in VHDL |
| 87 | 41 | 58 | a day ago | [axiom-firmware](https://github.com/apertus-open-source-cinema/axiom-firmware)/56 | AXIOM firmware (linux image, gateware and software tools) |
| 86 | 20 | 0 | Unknown | [PYNQ-DL](https://github.com/Xilinx/PYNQ-DL)/57 | Xilinx Deep Learning IP |
| 86 | 42 | 1 | Unknown | [hard-cv](https://github.com/jpiat/hard-cv)/58 | A repository of IPs for hardware computer vision (FPGA) |
| 85 | 10 | 0 | Unknown | [greta](https://github.com/endofexclusive/greta)/59 | GRETA expansion board for the Amiga 500 computer with Fast RAM, microSD mass storage and Ethernet controller, powered by FPGA technology. |
| 85 | 93 | 2 | Unknown | [Digital-Design-Lab](https://github.com/xupsh/Digital-Design-Lab)/60 | None |
| 83 | 32 | 1 | Unknown | [ZynqBTC](https://github.com/stiggy87/ZynqBTC)/61 | A Bitcoin miner for the Zynq chip utilizing the Zedboard. |
| 79 | 48 | 1 | Unknown | [ZPUino-HDL](https://github.com/alvieboy/ZPUino-HDL)/62 | ZPUino HDL implementation |
| 78 | 37 | 0 | Unknown | [Simon_Speck_Ciphers](https://github.com/inmcm/Simon_Speck_Ciphers)/63 | Implementations of the Simon and Speck Block Ciphers |
| 78 | 18 | 8 | Unknown | [AtomBusMon](https://github.com/hoglet67/AtomBusMon)/64 | This project is an open-source In-Circuit Emulator for the 6502, 65C02, Z80, 6809 and 6809E 8-bit processors.  See:  |
| 76 | 12 | 17 | Unknown | [w11](https://github.com/wfjm/w11)/65 | PDP-11/70 CPU core and SoC |
| 75 | 21 | 9 | Unknown | [bladeRF-adsb](https://github.com/Nuand/bladeRF-adsb)/66 | bladeRF ADS-B hardware decoder |
| 74 | 50 | 2 | Unknown | [LimeSDR-USB_GW](https://github.com/myriadrf/LimeSDR-USB_GW)/67 | Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board |
| 73 | 26 | 7 | Unknown | [GBA_MiSTer](https://github.com/MiSTer-devel/GBA_MiSTer)/68 | GBA for MiSTer |
| 73 | 48 | 2 | Unknown | [Hackster](https://github.com/ATaylorCEngFIET/Hackster)/69 | Files used with hackster examples  |
| 72 | 17 | 6 | Unknown | [sdram-fpga](https://github.com/nullobject/sdram-fpga)/70 | A FPGA core for a simple SDRAM controller. |
| 72 | 28 | 4 | Unknown | [surf](https://github.com/slaclab/surf)/71 | A huge VHDL library for FPGA development |
| 68 | 19 | 0 | Unknown | [fpga-multi-effect](https://github.com/Vladilit/fpga-multi-effect)/72 | FPGA-based Multi-Effects system for the electric guitar |
| 68 | 42 | 2 | Unknown | [spi-master](https://github.com/nandland/spi-master)/73 | SPI Master for FPGA - VHDL and Verilog |
| 68 | 3 | 1 | Unknown | [yafc](https://github.com/inforichland/yafc)/74 | Yet Another Forth Core... |
| 67 | 15 | 0 | Unknown | [spi-fpga](https://github.com/jakubcabal/spi-fpga)/75 | SPI master and SPI slave for FPGA written in VHDL |
| 67 | 6 | 0 | Unknown | [Gauntlet_FPGA](https://github.com/d18c7db/Gauntlet_FPGA)/76 | FPGA implementation of Atari's Gauntlet arcade game |
| 63 | 52 | 9 | Unknown | [logi-projects](https://github.com/fpga-logi/logi-projects)/77 | None |
| 63 | 8 | 6 | Unknown | [gbaHD](https://github.com/zwenergy/gbaHD)/78 | A GBA to DVI converter. |
| 62 | 7 | 1 | Unknown | [q27](https://github.com/preusser/q27)/79 | 27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting |
| 61 | 12 | 0 | Unknown | [vpcie](https://github.com/texane/vpcie)/80 | implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture |
| 61 | 28 | 2 | Unknown | [IIoT-EDDP](https://github.com/Xilinx/IIoT-EDDP)/81 | The repository contains the design database and documentation for Electric Drives Demonstration Platform |
| 60 | 25 | 5 | Unknown | [haddoc2](https://github.com/DreamIP/haddoc2)/82 | Caffe to VHDL |
| 59 | 43 | 3 | Unknown | [sublime-vhdl](https://github.com/yangsu/sublime-vhdl)/83 | VHDL Package for Sublime Text |
| 59 | 21 | 2 | Unknown | [Arduino-Soft-Core](https://github.com/GadgetFactory/Arduino-Soft-Core)/84 | None |
| 57 | 8 | 3 | Unknown | [jt51](https://github.com/jotego/jt51)/85 | YM2151 clone in verilog. FPGA proven. |
| 56 | 17 | 0 | Unknown | [RFToolSDR](https://github.com/daveshah1/RFToolSDR)/86 | AD9361 based USB3 SDR |
| 56 | 5 | 0 | Unknown | [bit-serial](https://github.com/howerj/bit-serial)/87 | A bit-serial CPU written in VHDL, with a simulator written in C. |
| 54 | 31 | 1 | Unknown | [uart](https://github.com/pabennett/uart)/88 | A VHDL UART for communicating over a serial link with an FPGA |
| 54 | 19 | 3 | Unknown | [zxuno](https://github.com/zxdos/zxuno)/89 | None |
| 54 | 19 | 0 | Unknown | [FpgasNowWhat](https://github.com/devbisme/FpgasNowWhat)/90 | Source for the "FPGAs?! Now What?" Book |
| 53 | 7 | 2 | Unknown | [Rudi-RV32I](https://github.com/hamsternz/Rudi-RV32I)/91 | A rudimental RISCV CPU supporting RV32I instructions, in VHDL |
| 53 | 33 | 2 | Unknown | [TurboGrafx16_MiSTer](https://github.com/MiSTer-devel/TurboGrafx16_MiSTer)/92 | TurboGrafx-16 CD / PC Engine CD for MiSTer |
| 51 | 9 | 6 | Unknown | [ReonV](https://github.com/lcbcFoo/ReonV)/93 | ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA. |
| 51 | 29 | 1 | Unknown | [SiaFpgaMiner](https://github.com/pedrorivera/SiaFpgaMiner)/94 | VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin |
| 50 | 14 | 4 | Unknown | [A-VideoBoard](https://github.com/c0pperdragon/A-VideoBoard)/95 | FPGA board to create a component video signal for vintage computers. |
| 50 | 123 | 3 | Unknown | [Basys3](https://github.com/Digilent/Basys3)/96 | None |
| 50 | 25 | 0 | Unknown | [FPGA-Oscilloscope](https://github.com/agural/FPGA-Oscilloscope)/97 | Design, Documentation, Schematic, Board, Code files for the FPGA Oscilloscope project using an Altera Cyclone III FPGA. |
| 50 | 19 | 0 | Unknown | [CNN_for_SLR](https://github.com/ilaydayaman/CNN_for_SLR)/98 | A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA. |
| 48 | 11 | 2 | Unknown | [JSON-for-VHDL](https://github.com/Paebbels/JSON-for-VHDL)/99 | A JSON library implemented in VHDL. |
| 48 | 35 | 0 | Unknown | [ODriveFPGA](https://github.com/madcowswe/ODriveFPGA)/100 | High performance motor control |
| 47 | 10 | 1 | 2 years ago | [CoPro6502](https://github.com/hoglet67/CoPro6502)/101 | FPGA implementations of BBC Micro Co Processors (65C02, Z80, 6809, 68000, x86, ARM2, PDP-11, 32016) |
| 46 | 8 | 2 | 4 months ago | [fpga-fft](https://github.com/owocomm-0/fpga-fft)/102 | A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm |
| 46 | 17 | 0 | 7 months ago | [Image-Processing](https://github.com/Gowtham1729/Image-Processing)/103 | Image Processing Toolbox in Verilog using Basys3 FPGA |
| 46 | 27 | 0 | 8 years ago | [VHDL](https://github.com/silverjam/VHDL)/104 | VHDL Samples |
| 46 | 16 | 3 | a month ago | [leros](https://github.com/leros-dev/leros)/105 | A Tiny Processor Core |
| 45 | 8 | 0 | 19 days ago | [scaffold](https://github.com/Ledger-Donjon/scaffold)/106 | Donjon hardware tool for circuits security evaluation |
| 45 | 14 | 3 | 7 years ago | [libv](https://github.com/martinjthompson/libv)/107 | Useful set of library functions for VHDL |
| 45 | 65 | 0 | 1 year, 5 months ago | [FPGA](https://github.com/suisuisi/FPGA)/108 | FPGA |
| 45 | 6 | 1 | 1 year, 1 month ago | [1bitSDR](https://github.com/alberto-grl/1bitSDR)/109 | Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom |
| 44 | 26 | 1 | 1 year, 7 months ago | [FPGA-I2C-Minion](https://github.com/oetr/FPGA-I2C-Minion)/110 | A simple I2C minion in VHDL |
| 44 | 24 | 1 | 1 year, 8 months ago | [fpgagen](https://github.com/Torlus/fpgagen)/111 | SEGA Genesis/Megadrive core, running on a Altera/Terasic DE1 board. |
| 44 | 0 | 0 | a month ago | [fpga-dns-adtm](https://github.com/magetron/fpga-dns-adtm)/112 | High-performance/Low-Latency FPGA-based DNS attack detector and threat mitigator |
| 43 | 33 | 1 | 1 year, 5 months ago | [LimeSDR-Mini_GW](https://github.com/myriadrf/LimeSDR-Mini_GW)/113 | LimeSDR-Mini board FPGA project |
| 43 | 21 | 2 | 6 days ago | [Mist_FPGA](https://github.com/Gehstock/Mist_FPGA)/114 | None |
| 43 | 23 | 2 | 3 years ago | [Vivado-KMeans](https://github.com/FelixWinterstein/Vivado-KMeans)/115 | Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs |
| 43 | 69 | 6 | 3 months ago | [mlib_devel](https://github.com/casper-astro/mlib_devel)/116 | None |
| 43 | 26 | 0 | 3 years ago | [AX7010](https://github.com/alinxalinx/AX7010)/117 | None |
| 42 | 17 | 20 | 3 years ago | [HDMI2USB-numato-opsis-sample-code](https://github.com/timvideos/HDMI2USB-numato-opsis-sample-code)/118 | Example code for the Numato Opsis board, the first HDMI2USB production board. |
| 42 | 29 | 7 | 5 years ago | [Papilio-Arcade](https://github.com/GadgetFactory/Papilio-Arcade)/119 | A collection of arcade games targeted for Papilio FPGA boards. Many of the games are from FPGAArcade.com. |
| 41 | 10 | 0 | 1 year, 3 months ago | [flexray-interceptor](https://github.com/pd0wm/flexray-interceptor)/120 | FPGA project to man-in-the-middle attack Flexray |
| 41 | 12 | 1 | 3 months ago | [phywhispererusb](https://github.com/newaetech/phywhispererusb)/121 | PhyWhisperer-USB: Hardware USB Trigger |
| 40 | 6 | 1 | 8 months ago | [fos](https://github.com/FPGA-Research-Manchester/fos)/122 | FOS - FPGA Operating System |
| 40 | 8 | 3 | 1 year, 6 days ago | [FlowBlaze](https://github.com/axbryd/FlowBlaze)/123 | FlowBlaze: Stateful Packet Processing in Hardware |
| 39 | 13 | 0 | 10 months ago | [intfftk](https://github.com/capitanov/intfftk)/124 | Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0. |
| 38 | 6 | 1 | 7 months ago | [wasca](https://github.com/hitomi2500/wasca)/125 | Sega Saturn multipurporse cartridge |
| 38 | 2 | 0 | 4 months ago | [MandelbrotInVHDL](https://github.com/ttsiodras/MandelbrotInVHDL)/126 | What better way to learn VHDL, than to do some fractals? |
| 37 | 14 | 0 | 5 years ago | [flearadio](https://github.com/emard/flearadio)/127 | Digital FM Radio Receiver for FPGA |
| 37 | 12 | 0 | 2 months ago | [uart-for-fpga](https://github.com/jakubcabal/uart-for-fpga)/128 | Simple UART controller for FPGA  written in VHDL |
| 36 | 17 | 0 | a day ago | [MultiComp](https://github.com/douggilliland/MultiComp)/129 | Spins of Grant Searle's MultiComp project on various hardware |
| 36 | 29 | 2 | a month ago | [rfsoc_qpsk](https://github.com/strath-sdr/rfsoc_qpsk)/130 | PYNQ example of using the RFSoC as a QPSK transceiver. |
| 36 | 14 | 0 | 5 years ago | [fpga-spectrum](https://github.com/mikestir/fpga-spectrum)/131 | Sinclair ZX Spectrum 48k and 128k on an Altera DE1 FPGA board |
| 36 | 2 | 6 | 2 days ago | [mc1](https://github.com/mrisc32/mc1)/132 | A computer (FPGA SoC) based on the MRISC32-A1 CPU |
| 35 | 21 | 0 | 3 years ago | [jTDC](https://github.com/jobisoft/jTDC)/133 | FPGA based 30ps RMS TDCs |
| 35 | 11 | 2 | 4 months ago | [AppleIISd](https://github.com/freitz85/AppleIISd)/134 | SD card based ProFile replacement for IIe |
| 35 | 20 | 0 | 5 years ago | [MIPS-processor](https://github.com/PiJoules/MIPS-processor)/135 | MIPS processor designed in VHDL |
| 34 | 23 | 2 | 11 months ago | [Zybo-Z7-20-pcam-5c](https://github.com/Digilent/Zybo-Z7-20-pcam-5c)/136 | None |
| 34 | 5 | 0 | 30 days ago | [R3DUX](https://github.com/Kekule-OXC/R3DUX)/137 | None |
| 33 | 13 | 4 | 3 years ago | [mce2vga](https://github.com/lfantoniosi/mce2vga)/138 | MDA/CGA/EGA to VGA FPGA Converter V2.00 |
| 33 | 13 | 0 | 7 years ago | [FPGAPCE](https://github.com/Torlus/FPGAPCE)/139 | PC-Engine / Turbografx-16 clone running on an Altera DE1 board. |
| 33 | 4 | 2 | 2 years ago | [UnAmiga](https://github.com/benitoss/UnAmiga)/140 | Implementation of Amiga 500/1200 in Altera Cyclone IV FPGA |
| 32 | 9 | 5 | 9 months ago | [BeebFpga](https://github.com/hoglet67/BeebFpga)/141 | None |
| 32 | 13 | 3 | 4 years ago | [fphdl](https://github.com/FPHDL/fphdl)/142 | VHDL-2008 Support Library |
| 32 | 10 | 0 | 5 years ago | [rgb2vga](https://github.com/lfantoniosi/rgb2vga)/143 | Analog RGB 15Khz to VGA 31Khz in FGPA |
| 31 | 12 | 0 | 4 years ago | [openMixR](https://github.com/daveshah1/openMixR)/144 | 4k Mixed Reality headset |
| 31 | 9 | 0 | 10 months ago | [karabas-128](https://github.com/andykarpov/karabas-128)/145 | Karabas-128. ZX Spectrum 128k clone, based on CPLD Altera EPM7128STC100 |
| 31 | 4 | 0 | 12 days ago | [apis_anatolia](https://github.com/mbaykenar/apis_anatolia)/146 | "Apis Anatolia" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir. |
| 31 | 17 | 0 | 1 year, 1 month ago | [tinycrypt](https://github.com/odzhan/tinycrypt)/147 | Crypto stuff. Don't use. |
| 31 | 5 | 1 | a month ago | [SneakySnake](https://github.com/CMU-SAFARI/SneakySnake)/148 | SneakySnake:snake: is the first and the only pre-alignment filtering algorithm that works efficiently and fast on modern CPU, FPGA, and GPU architectures. It greatly (by more than two orders of magnitude) expedites sequence alignment calculation for both short and long reads. Described in the Bioinformatics (2020) by Alser et al. https://arxiv.org/abs/1910.09020. |
| 31 | 8 | 1 | 5 years ago | [FPGA_GigabitTx](https://github.com/hamsternz/FPGA_GigabitTx)/149 | Sending UDP packets out over a Gigabit PHY with an FPGA. |
| 31 | 10 | 0 | 4 years ago | [FPGA-radio](https://github.com/dawsonjon/FPGA-radio)/150 | Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC |
| 31 | 14 | 1 | 6 years ago | [img_process_vhdl](https://github.com/BG2BKK/img_process_vhdl)/151 | Image Processing on FPGA using VHDL |
| 31 | 32 | 17 | a month ago | [SMS_MiSTer](https://github.com/MiSTer-devel/SMS_MiSTer)/152 | Sega Master System for MiSTer |
| 30 | 8 | 0 | 8 years ago | [MIPS32](https://github.com/BYVoid/MIPS32)/153 | A MIPS32 CPU implemented by VHDL |
| 30 | 16 | 0 | 3 years ago | [FPGA-Speech-Recognition](https://github.com/MohammedRashad/FPGA-Speech-Recognition)/154 | Expiremental Speech Recognition System using VHDL & MATLAB. |
| 30 | 16 | 0 | 3 years ago | [Designing-a-Custom-AXI-Slave-Peripheral](https://github.com/Architech-Silica/Designing-a-Custom-AXI-Slave-Peripheral)/155 | A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools |
| 30 | 2 | 0 | 5 years ago | [Sweet32-CPU](https://github.com/Basman74/Sweet32-CPU)/156 | Sweet32 32bit MRISC CPU - VHDL and software toolchain sources (including documentation) |
| 30 | 4 | 0 | 11 months ago | [PYNQ-Torch](https://github.com/manoharvhr/PYNQ-Torch)/157 | PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform |
| 30 | 16 | 0 | 7 years ago | [XuLA](https://github.com/xesscorp/XuLA)/158 | Everything to do with the XuLA FPGA board: schematics, layout, firmware, example FPGA designs, documentation, etc. |
| 29 | 15 | 1 | 2 years ago | [FGPU](https://github.com/malkadi/FGPU)/159 | FGPU is a soft GPU architecture general purpose computing |
| 29 | 6 | 1 | 3 years ago | [riscv-tomthumb](https://github.com/maikmerten/riscv-tomthumb)/160 | A small RISC-V RV32I core written in VHDL, intended as testbed for my personal VHDL learning |
| 29 | 23 | 3 | 5 years ago | [altera-de2-ann](https://github.com/ziyan/altera-de2-ann)/161 | Artificial Neural Network on Altera DE2 |
| 29 | 6 | 1 | a month ago | [AXI4](https://github.com/OSVVM/AXI4)/162 | AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components |
| 29 | 7 | 0 | 1 year, 7 months ago | [pano_man](https://github.com/skiphansen/pano_man)/163 | Simulation of the classic Pacman arcade game on a PanoLogic thin client. |
| 29 | 241 | 0 | 3 years ago | [vivado-library](https://github.com/DigilentInc/vivado-library)/164 | None |
| 29 | 1 | 0 | 5 years ago | [fpga-vt](https://github.com/howardjones/fpga-vt)/165 | VT100-style terminal implemented on FPGA in VHDL |
| 28 | 8 | 0 | 2 years ago | [PYNQ_softmax](https://github.com/9334swjtu/PYNQ_softmax)/166 | achieve softmax in PYNQ with heterogeneous computing. |
| 28 | 8 | 2 | 5 years ago | [ZPUFlex](https://github.com/robinsonb5/ZPUFlex)/167 | A highly-configurable and compact variant of the ZPU processor core |
| 27 | 10 | 0 | 5 months ago | [X68000_MiSTer](https://github.com/MiSTer-devel/X68000_MiSTer)/168 | Sharp X68000 for MiSTer |
| 27 | 1 | 0 | 1 year, 5 months ago | [router](https://github.com/CO-CN-Group1/router)/169 | 清华大学2019计网联合实验第一组 |
| 27 | 19 | 9 | 3 months ago | [Atari2600_MiSTer](https://github.com/MiSTer-devel/Atari2600_MiSTer)/170 | Atari 2600 for MiSTer |
| 27 | 1 | 0 | 7 years ago | [arm4u](https://github.com/freecores/arm4u)/171 | ARM4U |
| 27 | 9 | 2 | 1 year, 13 days ago | [AtomFpga](https://github.com/hoglet67/AtomFpga)/172 | Dave's version of the Acorn Atom FPGA, based on AlanD's original from stardot.org.uk |
| 27 | 10 | 0 | 9 years ago | [vhdl-nes](https://github.com/chenxiao07/vhdl-nes)/173 | nes emulator based on VHDL |
| 27 | 33 | 3 | 5 years ago | [logi-hard](https://github.com/fpga-logi/logi-hard)/174 | All Logi specific HDL code (platform specific interface, extension boards, specific hdl, etc) |
| 27 | 2 | 1 | 4 months ago | [psl_with_ghdl](https://github.com/tmeissner/psl_with_ghdl)/175 | Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) |
| 27 | 7 | 13 | 12 hours ago | [FPGA-robotics](https://github.com/JdeRobot/FPGA-robotics)/176 | Blocks for visual design of robot behaviors using FPGA and IceStudio |
| 27 | 3 | 1 | 2 months ago | [FPGACosmacELF](https://github.com/wel97459/FPGACosmacELF)/177 | A re-creation of a Cosmac ELF computer, Coded in SpinalHDL |
| 27 | 13 | 0 | 3 years ago | [SpaceInvadersFpgaGame](https://github.com/nikkatsa7/SpaceInvadersFpgaGame)/178 | Verilog implementation of the classic arcade game Space Invaders for the Zedboard FPGA board  |
| 26 | 16 | 3 | 5 years ago | [OpenRIO](https://github.com/magro732/OpenRIO)/179 | Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints. |
| 26 | 14 | 0 | 7 years ago | [FPGA-FAST](https://github.com/PUTvision/FPGA-FAST)/180 | FPGA FAST image feature detector implementation in VHDL |
| 26 | 17 | 19 | 30 days ago | [Orio](https://github.com/brnorris03/Orio)/181 | Orio is an open-source extensible framework for the definition of domain-specific languages and generation of optimized code for multiple architecture targets, including support for empirical autotuning of the generated code. |
| 26 | 12 | 0 | 5 years ago | [FPGA-OV7670-cam](https://github.com/ShoeShi/FPGA-OV7670-cam)/182 | VHDL/FPGA/OV7670 |
| 26 | 10 | 1 | 6 hours ago | [dvb_fpga](https://github.com/phase4ground/dvb_fpga)/183 | RTL implementation of components for DVB-S2  |
| 26 | 4 | 0 | 1 year, 8 months ago | [BenEaterVHDL](https://github.com/XarkLabs/BenEaterVHDL)/184 | VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net) |
| 26 | 10 | 1 | 10 months ago | [fp23fftk](https://github.com/capitanov/fp23fftk)/185 | Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL). |
| 26 | 9 | 3 | a month ago | [cps2_digiav](https://github.com/marqs85/cps2_digiav)/186 | CPS2 digital AV interface |
| 25 | 2 | 0 | 1 year, 1 month ago | [aes](https://github.com/mmattioli/aes)/187 | AES-128 hardware implementation |
| 25 | 16 | 0 | 3 years ago | [MIPI_CSI2_TX](https://github.com/VideoGPU/MIPI_CSI2_TX)/188 | VHDL code for using Xilinx MGT gigabit transceivers/LVDS lines for MIPI CSI-2 TX  protocol |
| 25 | 15 | 0 | 1 year, 7 months ago | [Rattlesnake](https://github.com/PulseRain/Rattlesnake)/189 | PulseRain Rattlesnake - RISCV RV32IMC Soft CPU  |
| 25 | 13 | 3 | 15 days ago | [ahir](https://github.com/madhavPdesai/ahir)/190 | Algorithm to hardware compilation tools (e.g. C to VHDL). |
| 25 | 4 | 5 | 3 years ago | [MARK_II](https://github.com/VladisM/MARK_II)/191 | Simple SoC in VHDL with full toolchain and custom board. |
| 25 | 18 | 1 | 3 years ago | [Designing-a-Custom-AXI-Master-using-BFMs](https://github.com/Architech-Silica/Designing-a-Custom-AXI-Master-using-BFMs)/192 | A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models |
| 25 | 3 | 0 | 1 year, 1 month ago | [fpga-nat64](https://github.com/twd2/fpga-nat64)/193 | A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support. |
| 25 | 13 | 0 | 5 years ago | [STREAM](https://github.com/myriadrf/STREAM)/194 | FPGA development platform for high-performance RF and digital design |
| 24 | 10 | 1 | 9 years ago | [Floating_Point_Library-JHU](https://github.com/xesscorp/Floating_Point_Library-JHU)/195 | VHDL for basic floating-point operations. |
| 24 | 5 | 0 | 1 year, 2 months ago | [NTSC-composite-encoder](https://github.com/elpuri/NTSC-composite-encoder)/196 | How to generate NTSC compliant(?) composite color video with an FPGA |
| 24 | 11 | 4 | 2 years ago | [ppa-pcmcia-sram](https://github.com/Sakura-IT/ppa-pcmcia-sram)/197 | PCMCIA SRAM card project (Sakura) |
| 24 | 11 | 0 | 4 years ago | [FPGA_Neural-Network](https://github.com/agostini01/FPGA_Neural-Network)/198 | The objective is to implement a Neural Network in VHDL code. It is aiming the Cyclone II FPGA Starter Development Kit hardware, but the Neural Network part is meant to be generic, thus it can be used along with different hardware setups. |
| 24 | 8 | 1 | 3 years ago | [snickerdoodle-examples](https://github.com/krtkl/snickerdoodle-examples)/199 | Example projects for snickerdoodle |
| 24 | 17 | 5 | 2 years ago | [blockmon](https://github.com/sysml/blockmon)/200 | A Modular System for Flexible, High-Performance Traffic http://www.ict-mplane.eu/  |
| 24 | 8 | 0 | 6 months ago | [PoC-Examples](https://github.com/VLSI-EDA/PoC-Examples)/201 | This repository contains synthesizable examples which use the PoC-Library. |
| 24 | 10 | 0 | a month ago | [rfsoc_sam](https://github.com/strath-sdr/rfsoc_sam)/202 | RFSoC Spectrum Analyser Module on PYNQ. |
| 24 | 20 | 0 | 5 years ago | [alpha-software](https://github.com/apertus-open-source-cinema/alpha-software)/203 | Axiom Alpha prototype software (FPGA, Linux, etc.) |
| 23 | 12 | 5 | 10 months ago | [msx1fpga](https://github.com/fbelavenuto/msx1fpga)/204 | MSX1 cloned in FPGA |
| 23 | 3 | 0 | 8 months ago | [ArtyS7-RPU-SoC](https://github.com/Domipheus/ArtyS7-RPU-SoC)/205 | Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board. |
| 23 | 18 | 10 | 4 months ago | [MSX_MiSTer](https://github.com/MiSTer-devel/MSX_MiSTer)/206 | MSX for MiSTer |
| 23 | 19 | 0 | 5 years ago | [zynq_examples](https://github.com/jiangjiali66/zynq_examples)/207 | None |
| 23 | 17 | 0 | 1 year, 9 months ago | [mist-cores](https://github.com/wsoltys/mist-cores)/208 | core files for the MiST fpga |
| 23 | 1 | 0 | 3 years ago | [N.I.G.E.-Machine](https://github.com/Anding/N.I.G.E.-Machine)/209 | A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is currently hosted on the Digilent Nexys 4 and Nexys 4 DDR |
| 23 | 7 | 0 | 3 years ago | [memsec](https://github.com/IAIK/memsec)/210 | Framework for building transparent memory encryption and authentication solutions |
| 23 | 11 | 0 | 7 years ago | [FP-V-GA-Text](https://github.com/MadLittleMods/FP-V-GA-Text)/211 | A simple to use VHDL module to display text on VGA display. |
| 23 | 8 | 1 | 5 days ago | [TG68K.C](https://github.com/TobiFlex/TG68K.C)/212 | switchable 68K CPU-Core |
| 23 | 3 | 0 | 5 years ago | [opa](https://github.com/terpstra/opa)/213 | Open Processor Architecture |
| 23 | 7 | 0 | 1 year, 6 months ago | [Nexys4DDR-ARM-M3-Plate-Recognition](https://github.com/Starrynightzyq/Nexys4DDR-ARM-M3-Plate-Recognition)/214 | 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛 |
| 23 | 10 | 2 | 1 year, 3 months ago | [Pynq-CV-OV5640](https://github.com/xupsh/Pynq-CV-OV5640)/215 | Pynq computer vision examples with an OV5640 camera |
| 23 | 1 | 0 | 5 years ago | [fpga-trace](https://github.com/justingallagher/fpga-trace)/216 | FPGA accelerated ray tracer, implemented in C++ and HLS |
| 23 | 9 | 1 | 1 year, 7 months ago | [ZipML-XeonFPGA](https://github.com/fpgasystems/ZipML-XeonFPGA)/217 | FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware) |
| 23 | 1 | 0 | 21 days ago | [FABulous](https://github.com/FPGA-Research-Manchester/FABulous)/218 | Fabric generator and CAD tools |
| 22 | 29 | 0 | 4 years ago | [Zedboard-old](https://github.com/Digilent/Zedboard-old)/219 | None |
| 22 | 1 | 33 | a month ago | [Codelib](https://github.com/Wycers/Codelib)/220 | None |
| 22 | 7 | 0 | 2 years ago | [nesfpga](https://github.com/strfry/nesfpga)/221 | A Simple FPGA Implementation of the Nintendo Entertainment System |
| 22 | 5 | 0 | 1 year, 18 days ago | [FPGA-Class-D-Amplifier](https://github.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier)/222 | None |
| 22 | 14 | 1 | 4 years ago | [fpga](https://github.com/dmpro2014/fpga)/223 | VHDL description of the custom Demolicious GPU. Built during a single semester at NTNU |
| 22 | 2 | 0 | 7 years ago | [noasic](https://github.com/noasic/noasic)/224 | An open-source VHDL library for FPGA design, licensed under the GNU lesser general public license. |
| 22 | 8 | 6 | 2 years ago | [EP994A](https://github.com/Speccery/EP994A)/225 | My TI-99/4A clone, two versions: FPGA+TMS99105 CPU and FPGA with my CPU core |
| 22 | 4 | 0 | a month ago | [Xoodoo](https://github.com/KeccakTeam/Xoodoo)/226 | None |
| 22 | 7 | 0 | 3 months ago | [AES-VHDL](https://github.com/hadipourh/AES-VHDL)/227 | VHDL Implementation of AES Algorithm |
| 22 | 1 | 0 | 3 years ago | [from-key-array-to-the-LED-lattice](https://github.com/HengRuiZ/from-key-array-to-the-LED-lattice)/228 | None |
| 22 | 11 | 0 | 7 years ago | [Camera-Tracking](https://github.com/Rutgers-FPGA-Projects/Camera-Tracking)/229 |  Our project is the system that enables a moving camera to track a moving object in real time. We plan on doing this by having a camera mounted to a swivel using two servo motors to allow for the camera’s direction to be controlled. The camera data will be read into the FPGA board and some basic object recognition algorithm will be used to  identify an some object and determine if the camera needs to be moved to keep the object in the field of vision. In addition to the auto tracking mode, we plan on having an IR remote to allow for manual panning, mode selection, and power on and off. If there is additional time we would like to also interface the FPGA to a Raspberry Pi board running a linux web server to allow for email alerts (when object moves) and web based control. |
| 22 | 9 | 0 | 5 years ago | [PicoBlaze-Library](https://github.com/Paebbels/PicoBlaze-Library)/230 | The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA). |
| 21 | 10 | 2 | Unknown | [WishboneAXI](https://github.com/qermit/WishboneAXI)/231 | Wishbone to AXI bridge (VHDL) |
| 21 | 9 | 1 | Unknown | [la16fw](https://github.com/gregani/la16fw)/232 | Alternative Logic16 Firmware |
| 21 | 7 | 0 | Unknown | [Motion-Detection-System-Based-On-Background-Reconstruction](https://github.com/2cc2ic/Motion-Detection-System-Based-On-Background-Reconstruction)/233 | This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to build a DMA based image data cache transmission system.  On this basis, Verilog HDL was used to design the axi4-stream interface based IP core for image processing, so as to build a high real-time moving target detection system.  In our design, we focus on the optimization of processing pipeline, improve the traditional frame difference method, and achieve the optimization goal of saving logical resources through the accumulation compression and reconstruction expansion of cached background frames. |
| 21 | 29 | 17 | Unknown | [mksocfpga](https://github.com/machinekit/mksocfpga)/234 | Hostmot2 FPGA code for SoC/FPGA platforms from Altera and Xilinx |
| 21 | 7 | 11 | Unknown | [r-vex](https://github.com/tvanas/r-vex)/235 | A reconfigurable and extensible VLIW processor implemented in VHDL |
| 21 | 19 | 0 | Unknown | [rgbmatrix-fpga](https://github.com/DuinoPilot/rgbmatrix-fpga)/236 | Adafruit RGB LED Matrix Display Driver for use with FPGAs (written in VHDL)  |
| 21 | 12 | 0 | Unknown | [fpga_examples](https://github.com/pwsoft/fpga_examples)/237 | Example code in vhdl to help starting new projects using FPGA devices. |
| 21 | 1 | 2 | Unknown | [FPGA-OV2640](https://github.com/lllbbbyyy/FPGA-OV2640)/238 | This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA. |
| 20 | 6 | 0 | Unknown | [hdl](https://github.com/laurivosandi/hdl)/239 | Collection of hardware description languages writings and code snippets |
| 20 | 7 | 0 | Unknown | [robotron-fpga](https://github.com/sharebrained/robotron-fpga)/240 | FPGA implementation of Robotron: 2084 |
| 20 | 7 | 1 | Unknown | [VHDL-Pong](https://github.com/ress/VHDL-Pong)/241 | A Pong game written in VHDL using a Xilinx Spartan 3 board. VGA + PS/2 Keyboard + Sound support. |
| 20 | 10 | 0 | Unknown | [fft](https://github.com/thasti/fft)/242 | synthesizable FFT IP block for FPGA designs |
| 20 | 11 | 6 | Unknown | [OneChipMSX](https://github.com/robinsonb5/OneChipMSX)/243 | A port of the OneChipMSX project to the Turbo Chameleon 64 and in time, hopefully other boards, too. |
| 20 | 3 | 1 | Unknown | [whirlyfly](https://github.com/zdavkeos/whirlyfly)/244 | Hardware RNG for Papilio One based on the original Whirlygig |
| 20 | 0 | 1 | Unknown | [ese-vdp](https://github.com/kunichiko/ese-vdp)/245 | VHDL implementation of YAMAHA V9938 |
| 20 | 8 | 0 | Unknown | [vga_generator](https://github.com/tibor-electronics/vga_generator)/246 | A collection of VHDL projects for generating VGA output |
| 20 | 5 | 5 | Unknown | [karabas-pro](https://github.com/andykarpov/karabas-pro)/247 | FPGA based retrocomputer with FDD and HDD controllers |
| 20 | 26 | 22 | Unknown | [ipbus-firmware](https://github.com/ipbus/ipbus-firmware)/248 | Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol |
| 20 | 5 | 0 | Unknown | [secd](https://github.com/hanshuebner/secd)/249 | SECD microprocessor reimplementation in VHDL |
| 20 | 4 | 2 | Unknown | [AladdinLCD](https://github.com/Ryzee119/AladdinLCD)/250 | Convert the cheap AladdinXT 4032 Original Xbox modchip to an LCD driver for TSOP modded consoles. |
| 20 | 9 | 10 | Unknown | [Atari800_MiSTer](https://github.com/MiSTer-devel/Atari800_MiSTer)/251 | Atari 800XL/65XE/130XE for MiSTer |
| 20 | 5 | 0 | Unknown | [hd6309sbc](https://github.com/tomcircuit/hd6309sbc)/252 | Hitachi HD6309 Singleboard Computer  |
| 19 | 9 | 1 | Unknown | [jcore-cpu](https://github.com/j-core/jcore-cpu)/253 | J-Core J2/J32 5 stage pipeline CPU core |
| 19 | 13 | 2 | Unknown | [Nexys-4-DDR-OOB](https://github.com/Digilent/Nexys-4-DDR-OOB)/254 | None |
| 19 | 4 | 0 | Unknown | [tiny_z80](https://github.com/skiselev/tiny_z80)/255 | Business Card Sized Z80 Single Board Computer |
| 19 | 10 | 0 | Unknown | [vhdl_prng](https://github.com/jorisvr/vhdl_prng)/256 | Pseudo Random Number Generators as synthesizable VHDL code |
| 19 | 8 | 0 | Unknown | [vhdl-hdmi-out](https://github.com/fcayci/vhdl-hdmi-out)/257 | HDMI Out VHDL code for 7-series Xilinx FPGAs |
| 19 | 4 | 0 | Unknown | [FPGA-LVDS-LCD-Hack](https://github.com/hubmartin/FPGA-LVDS-LCD-Hack)/258 | Basic code that displays simple shapes generated from Lattice FPGA directly to LVDS display |
| 19 | 13 | 4 | Unknown | [Apple-II_MiSTer](https://github.com/MiSTer-devel/Apple-II_MiSTer)/259 | Apple II+ for MiSTer |
| 19 | 6 | 0 | Unknown | [pid-fpga-vhdl](https://github.com/deepc94/pid-fpga-vhdl)/260 | This project was part of the VLSI Lab. It implements PID control using an FPGA. |
| 19 | 8 | 1 | Unknown | [VGA-Text-Generator](https://github.com/Derek-X-Wang/VGA-Text-Generator)/261 | A basic VGA text generator for verilog and vhdl |
| 19 | 11 | 1 | Unknown | [ReVerSE-U16](https://github.com/mvvproject/ReVerSE-U16)/262 | Development Kit |
| 19 | 3 | 1 | Unknown | [karabas-nano](https://github.com/andykarpov/karabas-nano)/263 | Karabas Nano prototype |
| 19 | 1 | 0 | Unknown | [formal_hw_verification](https://github.com/tmeissner/formal_hw_verification)/264 | Trying to verify Verilog/VHDL designs with formal methods and tools |
| 18 | 11 | 3 | Unknown | [pauloBlaze](https://github.com/krabo0om/pauloBlaze)/265 | A plain VHDL implementation of a small microprocessor fully compatible with the ISA of the well known PicoBlaze by Ken Chapman. |
| 18 | 1 | 0 | Unknown | [ZXNext_Mister](https://github.com/benitoss/ZXNext_Mister)/266 | ZX Next core for Mister |
| 18 | 10 | 1 | Unknown | [vcnn](https://github.com/g0kul/vcnn)/267 | Verilog Convolutional Neural Network on PYNQ |
| 18 | 19 | 7 | Unknown | [Arcade-Pacman_MiSTer](https://github.com/MiSTer-devel/Arcade-Pacman_MiSTer)/268 | Arcade: Pacman for MiSTer |
| 18 | 7 | 0 | Unknown | [lemberg](https://github.com/jeuneS2/lemberg)/269 | Lemberg is a time-predictable VLIW processor optimized for performance. |
| 18 | 6 | 2 | Unknown | [dso-quad-usb-analyzer](https://github.com/PetteriAimonen/dso-quad-usb-analyzer)/270 | USB Full-Speed (12Mbps) protocol analyzer for the DSO Quad |
| 18 | 5 | 4 | Unknown | [cv2PYNQ-The-project-behind-the-library](https://github.com/wbrueckner/cv2PYNQ-The-project-behind-the-library)/271 | This project describes how the cv2PYNQ python library was built |
| 18 | 9 | 6 | Unknown | [SimpleSDHC](https://github.com/ibm2030/SimpleSDHC)/272 | A basic SD Card SPI interface in VHDL, supports SD V1, V2 and SDHC |
| 18 | 4 | 1 | Unknown | [BBot](https://github.com/andygikling/BBot)/273 | BBot! An open source, wireless beer serving robot reference design featuring a C++ program running on a BeagleBone Black, a .Net WPF control GUI and even low level FPGA integration! |
| 18 | 17 | 1 | Unknown | [StickIt](https://github.com/xesscorp/StickIt)/274 | StickIt! board and modules that support the XuLA FPGA board. |
| 18 | 8 | 1 | Unknown | [FPGA_SDR](https://github.com/marsohod4you/FPGA_SDR)/275 | Software Defined Radio receiver in Marsohod2 Altera Cyclone III board |
| 18 | 1 | 9 | Unknown | [vhdeps](https://github.com/abs-tudelft/vhdeps)/276 | VHDL dependency analyzer |
| 18 | 0 | 0 | Unknown | [C88](https://github.com/danieljabailey/C88)/277 | C88 is Homebrew CPU that has a ram that is only 8x8 Bits in size. It'll fit on a papilio one 500k which has enough pins for all the switches you need too. |
| 18 | 3 | 1 | Unknown | [ym2608](https://github.com/mtrberzi/ym2608)/278 | VHDL clone of YM2608 (OPNA) sound chip |
| 18 | 12 | 0 | Unknown | [Hardware-Implementation-of-AES-VHDL](https://github.com/pnvamshi/Hardware-Implementation-of-AES-VHDL)/279 | Hardware Implementation of Advanced Encryption Standard Algorithm in VHDL |
| 18 | 9 | 0 | Unknown | [Digital-Hardware-Modelling](https://github.com/varunnagpaal/Digital-Hardware-Modelling)/280 | Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)  |
| 17 | 15 | 1 | Unknown | [zedboard_audio](https://github.com/ems-kl/zedboard_audio)/281 | A Audio Interface for the Zedboard |
| 17 | 2 | 1 | Unknown | [fpgaNES](https://github.com/Feuerwerk/fpgaNES)/282 | None |
| 17 | 10 | 1 | Unknown | [axi_custom_ip_tb](https://github.com/frobino/axi_custom_ip_tb)/283 | A testbench for an axi lite custom IP |
| 17 | 1 | 1 | Unknown | [NISC](https://github.com/BillBohan/NISC)/284 | A single instruction set processor architecture |
| 17 | 8 | 0 | Unknown | [Spectrum](https://github.com/delhatch/Spectrum)/285 | Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action. |
| 17 | 16 | 5 | Unknown | [PothosZynq](https://github.com/pothosware/PothosZynq)/286 | DMA source and sink blocks for Xilinx Zynq FPGAs |
| 17 | 2 | 0 | Unknown | [gs4502b](https://github.com/gardners/gs4502b)/287 | Experimental pipelined 4502 CPU design |
| 17 | 4 | 0 | Unknown | [Z-turn-examples](https://github.com/wzab/Z-turn-examples)/288 | The repository with my simple Z-turn examples, to be used as templates for more serious project |
| 17 | 7 | 0 | Unknown | [Hi-DMM](https://github.com/zslwyuan/Hi-DMM)/289 | Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis) |
| 17 | 11 | 0 | Unknown | [sha256](https://github.com/skordal/sha256)/290 | A simple SHA-256 implementation in VHDL |
| 17 | 2 | 0 | Unknown | [myhdl_simple_uart](https://github.com/andrecp/myhdl_simple_uart)/291 | A very simple UART implementation in MyHDL |
| 17 | 0 | 0 | Unknown | [ArtyS7](https://github.com/Domipheus/ArtyS7)/292 | Where Arty S7 projects are kept. MIT License unless file headers state otherwise. |
| 17 | 3 | 4 | Unknown | [tusSAT](https://github.com/Sumith1896/tusSAT)/293 | A SAT solver implementation in VHDL, team tussle |
| 16 | 10 | 1 | Unknown | [hashvoodoo-fpga-bitcoin-miner](https://github.com/pmumby/hashvoodoo-fpga-bitcoin-miner)/294 | HashVoodoo FPGA Bitcoin Miner |
| 16 | 2 | 3 | Unknown | [buryak-pi-2020](https://github.com/tank-uk/buryak-pi-2020)/295 | ZX Spectrum совместимый компьютер, с реальным Z80, VGA, Turbosound, PS/2 клавиатурой, Kempston джойстиком, заточенный под корпус от Raspberry Pi 3B |
| 16 | 19 | 0 | Unknown | [Nexys4DDR](https://github.com/Digilent/Nexys4DDR)/296 | None |
| 16 | 6 | 0 | Unknown | [fpga-bbc](https://github.com/mikestir/fpga-bbc)/297 | Acorn BBC Micro on an Altera DE1 FPGA board |
| 16 | 8 | 0 | Unknown | [c64pla](https://github.com/FrankBuss/c64pla)/298 | C64 PLA implementation in VHDL |
| 16 | 6 | 0 | Unknown | [MIPS-Lite](https://github.com/jncraton/MIPS-Lite)/299 | A pipelined MIPS-Lite CPU implementation |
| 16 | 7 | 5 | Unknown | [rygar-fpga](https://github.com/nullobject/rygar-fpga)/300 | A FPGA core for the arcade game, Rygar (1986). |
| 16 | 11 | 1 | 10 months ago | [Accelerating-Quantized-CNN-Inference-on-FPGA](https://github.com/CNILeo/Accelerating-Quantized-CNN-Inference-on-FPGA)/301 | Accelerating-Quantized-CNN-Inference-on-FPGA(RTL) |
| 16 | 9 | 1 | 4 years ago | [Nexys4](https://github.com/Digilent/Nexys4)/302 | None |
| 16 | 4 | 0 | 3 years ago | [Mips54](https://github.com/LiuChangFreeman/Mips54)/303 | None |
| 16 | 6 | 0 | 3 years ago | [revCtrl](https://github.com/Xilinx/revCtrl)/304 | Revision Control Labs and Materials |
| 16 | 10 | 1 | 9 years ago | [Network-on-Chip-in-VHDL](https://github.com/mattbirman/Network-on-Chip-in-VHDL)/305 | None |
| 16 | 9 | 0 | 1 year, 5 months ago | [EP2C5-Cyclone-II-Mini-Board](https://github.com/land-boards/EP2C5-Cyclone-II-Mini-Board)/306 | EP2C5 Cyclone II Mini Board |
| 16 | 13 | 0 | 8 years ago | [grlib](https://github.com/philippefaes/grlib)/307 | None |
| 16 | 9 | 0 | 5 years ago | [fpga_fibre_scan](https://github.com/takeshineshiro/fpga_fibre_scan)/308 |   本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互，CYUSB3.0主要完成协议数据的传输。      2.2.1  FPGA模块         处理流程：   1. 链路初始化： 在上位机完成USB固件的下载，并读取固件的信息状态描述后，通过上电复位或者手动复位，通过串口发送0X55给上位机，表明链路打通，一次握手成功。 2. 超声波发射与AD数据接收：在收到上位机通过串口发送的0X02指令后，开启（START），发送超声方波信号，（注：该START信号在处理过程被改变成包络信号）因为只是单阵元，所以就没有接收延迟聚焦的问题，但有皮肤表皮的客观实际和单阵元回波的时间消耗，所以在等到C_CORDIC_DELAY（1000）后，才开始AD数据的采集。（注：具体多少厚度，需要细算）。每次采集4096个数据，形成一个扫描线；总共需要采集300根扫描线，若不够，则需重新发送方波，并接收AD数据。 3.  剪切波发送： 在采集到第33根扫描线后，开始剪切波的发送，简单的发送50HZ的单载波就可以，此后的AD数据就含有剪切波的信息。 4.  控制通路的信息：  这里通过CYUSB3.0的串口来传送上位机发送的控制端口信息 ，包括数据通路的读和写指令（注：这里只需要通过BULK读取数据通路的数据，不需要通过BULK向数据通路写数据）；通过CYUSB3.0的串口来传送下位机FPGA的状态信息指令给上位机。（由于采用的是URAT，所以有FIFO缓存和数据发送接收状态控制操作） 5. 数据通路的信息： 这里通过上位机的读写指令来将数据存储到FIFO中，这里默认发送的是0X00指令，一直读取AD采集到的数据。并且采用的是BULK的Xfer->read的同步传输，一直要等到指定数目数据（4096*300）采集完才结束采集。     2.2.2   USB3.0模块          1. 这里首先要进行存储划分和寄存器映射，一般汇编或者其他CMD格式，然后编写BOOTLOAD汇编，最后中断跳转处理（汇编）。      2. 这里主要配置GPIF的异步串口参数和读写操作。      3. 这里需要给出CTL端口和BULK端口的配置和读写。     2.3  上位机软件      这里主要完成算法的处理和界面的显示和控制。 关于算法部分需要后面补充，目前没有完全消化。       处理流程：   1. 初始化USB，然后上位机通过控制端点发送写命令控制字（不加帧头命令）下位机未处理，开启监视工作线程循环，主要内容是：通过控制端点发送读命令控制字，通过控制端点读回串口信息，用来验证设备是否启动握手成功（0X55）。 2. 启动成功后引发响应的启动触发方法。启动触发方法中，先要延时大于0.36s，如果选中check_box，则使用存储的测试数据，若未选中，通过控制端点发送写start命令，开启bulk端口读循环线程，最后每次测量发送一次读bulk数据消息到消息队列。 3. 在bulk端口读循环线程中引发响应的bulk读方法，在bulk读方法中，主要调用底层的USB3.0的bulkin读方法，数据读上来后，post一个getData消息，交由绑定的函数来处理数据。 4.  数据处理包括二独立部分，一部分是原始数据产生MotionMOdel信息 ,一部分是原始数据产生剪切波速度和杨氏模量信息。 |
| 16 | 10 | 1 | 7 years ago | [cmake-verilog-vhdl-fpga-template](https://github.com/yansyaf/cmake-verilog-vhdl-fpga-template)/309 | CMake template for Verilog and VHDL project and Altera/Xilinx FPGA target  |
| 16 | 3 | 0 | 3 years ago | [THU-MIPS16-CPU](https://github.com/747929791/THU-MIPS16-CPU)/310 | Tsinghua University Computer Composition Principle Experiment |
| 16 | 3 | 0 | 14 days ago | [vboard](https://github.com/dbhi/vboard)/311 | Virtual development board for HDL design |
| 16 | 8 | 1 | 4 years ago | [zybo_petalinux_video_hls](https://github.com/andrewandrepowell/zybo_petalinux_video_hls)/312 | Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output. |
| 16 | 20 | 0 | 1 year, 1 month ago | [gnss-baseband](https://github.com/j-core/gnss-baseband)/313 | Baseband Receiver IP for GPS like DSSS signals |
| 16 | 3 | 0 | 3 months ago | [satcat5](https://github.com/the-aerospace-corporation/satcat5)/314 | SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network. |
| 15 | 5 | 0 | 4 years ago | [MIPS](https://github.com/dugagjin/MIPS)/315 | VHDL implementation of a MIPS processor for Spartan-6 FPGA |
| 15 | 6 | 0 | 11 months ago | [Altera-Cyclone-II-EP2C5T144-blink](https://github.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink)/316 | A very junior "Hello World" for the low price Altera Cypress II EP2C5T144 FPGA Mini dev board from amazon/ebay |
| 15 | 3 | 0 | 1 year, 1 month ago | [skrach-synth](https://github.com/docquantum/skrach-synth)/317 | An FPGA synthesizer with MIDI support |
| 15 | 7 | 1 | 1 year, 1 month ago | [jcore-soc](https://github.com/j-core/jcore-soc)/318 | J-Core SoC Base Platfrom. Top level for FPGA platforms, pulls in CPU, BootROM and various IP blocks. |
| 15 | 6 | 0 | 2 years ago | [REAPR](https://github.com/ted-xie/REAPR)/319 | REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications such as regular expressions. REAPR is currently only compatible with SDAccel-capable Xilinx FPGA boards. |
| 15 | 5 | 0 | 1 year, 22 days ago | [FPGA-Audio-IIR](https://github.com/YetAnotherElectronicsChannel/FPGA-Audio-IIR)/320 | None |
| 15 | 9 | 0 | 2 years ago | [EM070_New-FPGA-family-for-CNN-architectures-High-Speed-Soft-Neuron-Design](https://github.com/Hossamomar/EM070_New-FPGA-family-for-CNN-architectures-High-Speed-Soft-Neuron-Design)/321 | Who doesn’t dream of a new FPGA family that can provide embedded hard neurons in its silicon architecture fabric instead of the conventional DSP and multiplier blocks? The optimized hard neuron design will allow all the software and hardware designers to create or test different deep learning network architectures, especially the convolutional neural networks (CNN), more easily and faster in comparing to any previous FPGA family in the market nowadays. The revolutionary idea about this project is to open the gate of creativity for a precise-tailored new generation of FPGA families that can solve the problems of wasting logic resources and/or unneeded buses width as in the conventional DSP blocks nowadays. The project focusing on the anchor point of the any deep learning architecture, which is to design an optimized high-speed neuron block which should replace the conventional DSP blocks to avoid the drawbacks that designers face while trying to fit the CNN architecture design to it. The design of the proposed neuron also takes the parallelism operation concept as it’s primary keystone, beside the minimization of logic elements usage to construct the proposed neuron cell. The targeted neuron design resource usage is not to exceeds 500 ALM and the expected maximum operating frequency of 834.03 MHz for each neuron. In this project, ultra-fast, adaptive, and parallel modules are designed as soft blocks using VHDL code such as parallel Multipliers-Accumulators (MACs), RELU activation function that will contribute to open a new horizon for all the FPGA designers to build their own Convolutional Neural Networks (CNN). We couldn’t stop imagining INTEL ALTERA to lead the market by converting the proposed designed CNN block and to be a part of their new FPGA architecture fabrics in a separated new Logic Family so soon. The users of such proposed CNN blocks will be amazed from the high-speed operation per seconds that it can provide to them while they are trying to design their own CNN architectures. For instance, and according to the first coding trial, the initial speed of just one MAC unit can reach 3.5 Giga Operations per Second (GOPS) and has the ability to multiply up to 4 different inputs beside a common weight value, which will lead to a revolution in the FPGA capabilities for adopting the era of deep learning algorithms especially if we take in our consideration that also the blocks can work in parallel mode which can lead to increasing the data throughput of the proposed project to about 16 Tera Operations per Second (TOPS). Finally, we believe that this proposed CNN block for FPGA is just the first step that will leave no areas for competitions with the conventional CPUs and GPUs due to the massive speed that it can provide and its flexible scalability that it can be achieved from the parallelism concept of operation of such FPGA-based CNN blocks. |
| 15 | 8 | 0 | 3 years ago | [S2NN-HLS](https://github.com/eejlny/S2NN-HLS)/322 | Spiking neural network for Zynq devices with Vivado HLS |
| 15 | 12 | 0 | 1 year, 5 months ago | [jpeg_open](https://github.com/lulinchen/jpeg_open)/323 | A hardware MJPEG encoder and RTP transmitter |
| 15 | 2 | 1 | 5 months ago | [second_order_sigma_delta_DAC](https://github.com/hamsternz/second_order_sigma_delta_DAC)/324 | A comparison of 1st and 2nd order sigma delta DAC for FPGA |
| 15 | 8 | 2 | 4 years ago | [PYNQ_PR_Overlay](https://github.com/AEW2015/PYNQ_PR_Overlay)/325 | Adding PR to the PYNQ Overlay |
| 15 | 16 | 6 | 19 days ago | [Arcade-DonkeyKong_MiSTer](https://github.com/MiSTer-devel/Arcade-DonkeyKong_MiSTer)/326 | Arcade: Donkey Kong for MiSTer |
| 15 | 6 | 1 | 1 year, 3 months ago | [fmh_gpib_core](https://github.com/fmhess/fmh_gpib_core)/327 | GPIB IEEE 488.1 core |
| 15 | 3 | 0 | 6 years ago | [R-JTOP](https://github.com/DrSchottky/R-JTOP)/328 | Open source implementation of CB fusecheck glitch |
| 15 | 1 | 0 | 3 years ago | [cosmac](https://github.com/brouhaha/cosmac)/329 | RCA COSMAC CDP1802 functional equivalent CPU core in VHDL |
| 15 | 11 | 1 | 4 years ago | [ZedBoard-OLED](https://github.com/mmattioli/ZedBoard-OLED)/330 | Driving the OLED display on the ZedBoard |
| 15 | 4 | 0 | 4 years ago | [neuron-vhdl](https://github.com/dicearr/neuron-vhdl)/331 | Implementation of a neuron and 2 neuronal networks in vhdl |
| 15 | 15 | 3 | 2 years ago | [VHDL-JESD204b](https://github.com/BBN-Q/VHDL-JESD204b)/332 | JESD204b modules in VHDL |
| 15 | 2 | 0 | 3 years ago | [vm2413](https://github.com/digital-sound-antiques/vm2413)/333 | A YM2413 clone module written in VHDL. |
| 15 | 3 | 0 | 10 months ago | [libvhdl](https://github.com/tmeissner/libvhdl)/334 | Library of reusable VHDL components |
| 15 | 5 | 1 | 10 months ago | [WonderMadeleine](https://github.com/986-Studio/WonderMadeleine)/335 | WonderMadeleine is a Bandai 2001/2003 clone chip |
| 15 | 9 | 0 | 1 year, 6 months ago | [itc99-poli](https://github.com/squillero/itc99-poli)/336 | ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino (I99T) |
| 15 | 6 | 0 | 2 years ago | [light52](https://github.com/jaruiz/light52)/337 | Yet another free 8051 FPGA core |
| 15 | 5 | 1 | 1 year, 3 days ago | [cpu86](https://github.com/nsauzede/cpu86)/338 | 🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA |
| 14 | 4 | 0 | 7 years ago | [multicomp](https://github.com/wsoltys/multicomp)/339 | Simple custom computer on a FPGA |
| 14 | 6 | 1 | 5 years ago | [ArtyEtherentTX](https://github.com/hamsternz/ArtyEtherentTX)/340 | Sending raw data from the Digilent Arty FPGA board |
| 14 | 5 | 0 | 3 years ago | [OSXA](https://github.com/aghoghoobi/OSXA)/341 | The OSXA repository contains the design files for an LPC flash addon to the original xbox video game console.  |
| 14 | 1 | 0 | 1 year, 10 months ago | [VHDLBoy](https://github.com/RobertPeip/VHDLBoy)/342 | VHDL Gameboy implementation |
| 14 | 1 | 0 | 3 months ago | [Z80-512K](https://github.com/skiselev/Z80-512K)/343 | Z80 CPU and Memory Module |
| 14 | 2 | 0 | 2 months ago | [MicroPET](https://github.com/fachat/MicroPET)/344 | None |
| 14 | 4 | 0 | 3 years ago | [OSXANF](https://github.com/aghoghoobi/OSXANF)/345 | The OSXA repository contains the design files for a NOR flash addon to the original xbox video game console.  |
| 14 | 8 | 0 | 2 years ago | [Arty-A7-35-GPIO](https://github.com/Digilent/Arty-A7-35-GPIO)/346 | None |
| 14 | 9 | 1 | 1 year, 11 months ago | [fpga-miner](https://github.com/diogofferreira/fpga-miner)/347 |  :moneybag: A simplified version of an FPGA bitcoin miner :moneybag: |
| 14 | 3 | 1 | 5 years ago | [6502](https://github.com/bernardo-andreeti/6502)/348 | VHDL description of 6502 processor with FPGA synthesis support. |
| 14 | 8 | 2 | 4 years ago | [netv2-fpga-basic-overlay](https://github.com/bunnie/netv2-fpga-basic-overlay)/349 | Vivado design for basic NeTV2 FPGA with chroma-based overlay |
| 14 | 10 | 2 | 11 months ago | [Arcade-Arkanoid_MISTer](https://github.com/Ace9921/Arcade-Arkanoid_MISTer)/350 | None |
| 14 | 1 | 0 | 1 year, 1 month ago | [fppa-pdk-emulator-vhdl](https://github.com/free-pdk/fppa-pdk-emulator-vhdl)/351 | VHDL simulation model for PADAUK PDK microcontrollers  |
| 14 | 4 | 0 | 4 years ago | [Cache](https://github.com/Tabrizian/Cache)/352 | Simple implementation of cache using VHDL |
| 14 | 3 | 0 | 1 year, 11 months ago | [antDev](https://github.com/Winters123/antDev)/353 | Agile Network Tester with FPGA & multi-cores |
| 14 | 1 | 0 | 4 years ago | [IBM2030](https://github.com/ibm2030/IBM2030)/354 | An IBM System/360 Model 30 in VHDL |
| 14 | 3 | 0 | 3 years ago | [subleq-machine-vhdl](https://github.com/rongcuid/subleq-machine-vhdl)/355 | The final code of a two-hour challenge to simulate and implement a SUBLEQ SISC machine |
| 14 | 3 | 0 | 6 years ago | [GAIA3](https://github.com/nyuichi/GAIA3)/356 | GAIA Processor |
| 14 | 5 | 0 | 3 years ago | [SMSMapper](https://github.com/db-electronics/SMSMapper)/357 | Sega Master System Homebrew Flash Cart |
| 14 | 14 | 0 | 1 year, 3 months ago | [LMAC_CORE3](https://github.com/lewiz-support/LMAC_CORE3)/358 | Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps |
| 14 | 5 | 0 | 6 years ago | [uart-vhdl](https://github.com/tvanas/uart-vhdl)/359 | An RS232 communication controller implemented in VHDL |
| 14 | 10 | 0 | 4 months ago | [NN_RGB_FPGA](https://github.com/Marco-Winzker/NN_RGB_FPGA)/360 | FPGA Design of a Neural Network for Color Detection |
| 14 | 5 | 0 | 2 years ago | [ZYNQ-PYNQ-Z2-Gobang](https://github.com/Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang)/361 | 参加2018第二届全国大学生FPGA创新设计邀请赛的作品 |
| 14 | 0 | 0 | 1 year, 2 months ago | [VHDL6526](https://github.com/bwack/VHDL6526)/362 | None |
| 14 | 6 | 0 | 9 months ago | [getting-started-FV](https://github.com/SymbioticEDA/getting-started-FV)/363 | None |
| 14 | 3 | 10 | 7 days ago | [mrisc32-a1](https://github.com/mrisc32/mrisc32-a1)/364 | A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA |
| 14 | 11 | 0 | 3 years ago | [SRAI_HW_ACCEL_WINDOWS10_PCIe](https://github.com/SanjayRai/SRAI_HW_ACCEL_WINDOWS10_PCIe)/365 | PCIe based accelerator for VCU1525  with xDMA based on Windows10 and Windows Server 2016 development environment |
| 14 | 3 | 1 | 3 years ago | [ASP-SoC](https://github.com/ASP-SoC/ASP-SoC)/366 | Audio Signal Processing SoC |
| 13 | 2 | 0 | 2 years ago | [deocmpldcv](https://github.com/uniabis/deocmpldcv)/367 | This project is a port of the 1chipMSX to DEOCM + DE0-CV including modification of OCM-PLD. |
| 13 | 26 | 0 | 3 months ago | [hostmot2-firmware](https://github.com/LinuxCNC/hostmot2-firmware)/368 | HostMot2 FPGA firmware |
| 13 | 4 | 0 | 2 years ago | [ultra96_design](https://github.com/fixstars/ultra96_design)/369 | Repository of HW design and SW for Ultra96 board + MIPI board |
| 13 | 5 | 0 | 4 months ago | [cryptocores](https://github.com/tmeissner/cryptocores)/370 | cryptography ip-cores in vhdl / verilog |
| 13 | 12 | 0 | 4 years ago | [Hardware-Neural-Network](https://github.com/Skydes/Hardware-Neural-Network)/371 | Embedded hardware accelerator of multilayer perceptrons for lightweight machine learning |
| 13 | 4 | 0 | 1 year, 6 months ago | [j-core-ice40](https://github.com/j-core/j-core-ice40)/372 | J-core SOC for ice40 FPGA |
| 13 | 8 | 2 | 3 months ago | [BBCMicro_MiSTer](https://github.com/MiSTer-devel/BBCMicro_MiSTer)/373 | BBC Micro B and Master 128K for MiSTer |
| 13 | 4 | 1 | 2 years ago | [Shouji](https://github.com/CMU-SAFARI/Shouji)/374 | Shouji is fast and accurate pre-alignment filter for banded sequence alignment calculation. Described in the Bioinformatics journal paper (2019) by Alser et al. at https://academic.oup.com/bioinformatics/advance-article-pdf/doi/10.1093/bioinformatics/btz234/28533771/btz234.pdf |
| 13 | 10 | 0 | 14 days ago | [Learn-FPGA-Programming](https://github.com/PacktPublishing/Learn-FPGA-Programming)/375 | Learn FPGA Programming, published by Packt |
| 13 | 5 | 0 | 2 years ago | [FpChip8](https://github.com/VitorVilela7/FpChip8)/376 | FPGA implementation of CHIP-8 using VHDL. |
| 13 | 2 | 0 | 9 months ago | [Homebrew-65C02-Computer](https://github.com/LIV2/Homebrew-65C02-Computer)/377 | A homebrew 65C02 based computer with PS/2 Keyboard, Serial & Parallel IO + 3 Expansion slots |
| 13 | 3 | 0 | 1 year, 10 months ago | [probe-scope-fpga](https://github.com/probe-scope/probe-scope-fpga)/378 | FPGA Software for the Probe-Scope |
| 13 | 1 | 0 | 1 year, 8 months ago | [synthowheel](https://github.com/emard/synthowheel)/379 | Polyphonic additive wheeltone synthesizer core |
| 13 | 9 | 0 | 1 year, 10 months ago | [Basys-3-GPIO](https://github.com/Digilent/Basys-3-GPIO)/380 | None |
| 13 | 3 | 0 | 2 years ago | [Pixblasters-MicroDemo](https://github.com/PixiGreen/Pixblasters-MicroDemo)/381 | Create video LED displays by RGB LED strips |
| 13 | 22 | 1 | 7 years ago | [AD](https://github.com/awersatos/AD)/382 | Altium Desinger |
| 13 | 0 | 0 | 7 years ago | [xentral](https://github.com/drxzcl/xentral)/383 | XENTRAL is a simple Harvard Architecture CPU. |
| 13 | 6 | 0 | 5 years ago | [Zynq_Project](https://github.com/snikrepmada/Zynq_Project)/384 | Zynq project to interface OV2640 camera module |
| 13 | 2 | 0 | 2 years ago | [AnalogCPU](https://github.com/whoisnian/AnalogCPU)/385 | 8位模型机（数字电子课程设计） |
| 13 | 3 | 0 | 9 days ago | [osvb](https://github.com/umarcor/osvb)/386 | Open Source Verification Bundle for VHDL and System Verilog |
| 13 | 9 | 0 | 4 years ago | [aes-over-pcie](https://github.com/jevinskie/aes-over-pcie)/387 | A VHDL implementation of 128 bit AES encryption with a PCIe interface. |
| 13 | 9 | 1 | 7 years ago | [SpaceWireCODECIP_100MHz](https://github.com/shimafujigit/SpaceWireCODECIP_100MHz)/388 | None |
| 13 | 0 | 0 | a month ago | [simple-riscv](https://github.com/hamsternz/simple-riscv)/389 | A simple three-stage RISC-V CPU |
| 13 | 2 | 1 | 2 months ago | [ZXNext_MISTer](https://github.com/MiSTer-devel/ZXNext_MISTer)/390 | None |
| 12 | 10 | 0 | 9 years ago | [VHDL-Mips-Pipeline-Microprocessor](https://github.com/renataghisloti/VHDL-Mips-Pipeline-Microprocessor)/391 | VHDL-Mips-Pipeline-Microprocessor |
| 12 | 10 | 7 | a month ago | [TI-99_4A_MiSTer](https://github.com/MiSTer-devel/TI-99_4A_MiSTer)/392 | Texas Instrument 99/4A Home Computer |
| 12 | 2 | 1 | 5 years ago | [keyboard-ip](https://github.com/theshadowx/keyboard-ip)/393 | PS/2 Keyboard IP written in VHDL for Xilinx FPGA |
| 12 | 12 | 1 | 3 years ago | [Arty-Z7-old](https://github.com/Digilent/Arty-Z7-old)/394 | Board repository for the Arty Z7 |
| 12 | 1 | 1 | 6 months ago | [Sudoku-Solver](https://github.com/sourabh-suri/Sudoku-Solver)/395 | A brute force algorithm on hardware is used to solve a sudoku. When a valid fill is not found backtracking is done. Backtracking is repeated until last number is a valid guess i.e guess out of 1 to 9. Digital logic realised using priority encoders and multiplexers. |
| 12 | 7 | 0 | a month ago | [fpga_ip](https://github.com/oscimp/fpga_ip)/396 | OscillatorIMP ecosystem FPGA IP sources |
| 12 | 5 | 1 | 3 years ago | [tdc](https://github.com/gonzagab/tdc)/397 | A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA. |
| 12 | 9 | 0 | 7 years ago | [VHDL-Pong](https://github.com/MadLittleMods/VHDL-Pong)/398 | Straightforward Pong Game written in VHDL. Scoring and Multiplayer |
| 12 | 0 | 0 | 3 years ago | [k1208-cpld](https://github.com/mikestir/k1208-cpld)/399 | K1208 A1200 fastmem board CPLD logic |
| 12 | 2 | 0 | 12 years ago | [zpu](https://github.com/freecores/zpu)/400 | ZPU - the worlds smallest 32 bit CPU with GCC toolchain |
| 12 | 5 | 1 | 1 year, 11 months ago | [LimeSDR_DVBSGateware](https://github.com/natsfr/LimeSDR_DVBSGateware)/401 | Optimised gateware for lime sdr mini |
| 12 | 0 | 0 | 5 years ago | [YM2612](https://github.com/sauraen/YM2612)/402 | VHDL description and documentation of architecture and undocumented features in Yamaha YM2203 (OPN) and YM2612 (OPN2) |
| 12 | 2 | 0 | 7 years ago | [myhdl-examples](https://github.com/jandecaluwe/myhdl-examples)/403 | None |
| 12 | 4 | 0 | 4 months ago | [Demo_project](https://github.com/Pillar1989/Demo_project)/404 | None |
| 12 | 0 | 1 | 3 years ago | [mips-cpu](https://github.com/fkd19/mips-cpu)/405 | None |
| 12 | 0 | 0 | 6 months ago | [xpm_vhdl](https://github.com/fransschreuder/xpm_vhdl)/406 | A translation of the Xilinx XPM library to VHDL for simulation purposes |
| 12 | 5 | 1 | 3 years ago | [capi-streaming-framework](https://github.com/mbrobbel/capi-streaming-framework)/407 | AFU framework for streaming applications with CAPI. |
| 12 | 9 | 0 | 8 years ago | [fpga-camera](https://github.com/bitflippersanonymous/fpga-camera)/408 | FPGA digital camera controller and frame capture device in VHDL |
| 12 | 1 | 0 | 3 years ago | [gimli](https://github.com/jedisct1/gimli)/409 | Reference implementations of the GIMLI permutation |
| 12 | 16 | 1 | 18 days ago | [Arcade-Galaga_MiSTer](https://github.com/MiSTer-devel/Arcade-Galaga_MiSTer)/410 | Arcade: Galaga for MiSTer |
| 12 | 1 | 0 | 3 years ago | [VIIRF](https://github.com/MauererM/VIIRF)/411 | Hardware description (VHDL) and configuration scripts (Python) of a versatile IIR Filter implemented as cascaded SOS/biquads. No vendor-specific hardware constructs used.  |
| 12 | 9 | 0 | 4 years ago | [zybo_petalinux](https://github.com/andrewandrepowell/zybo_petalinux)/412 | Small projects intended to run on the Digilent Zybo development board, utilizing PetaLinux on the Zynq's ARM processor. |
| 12 | 5 | 0 | 1 year, 3 months ago | [maestro](https://github.com/Artoriuz/maestro)/413 | A 5 stage-pipeline RV32I implementation in VHDL |
| 12 | 3 | 1 | 5 months ago | [agc_monitor](https://github.com/thewonderidiot/agc_monitor)/414 | Modern implementation of the AGC Monitor, for use with a real Apollo Guidance Computer |
| 11 | 9 | 0 | 9 months ago | [Getting-to-Know-Vivado](https://github.com/ATaylorCEngFIET/Getting-to-Know-Vivado)/415 | Source files for Getting to Know Vivado course |
| 11 | 17 | 0 | 8 years ago | [LEON2](https://github.com/Galland/LEON2)/416 | LEON2 SPARC CPU IP core LGPL by Gaisler Research |
| 11 | 2 | 0 | 6 months ago | [16x16-bit-Dada-multiplication](https://github.com/sourabh-suri/16x16-bit-Dada-multiplication)/417 | Design a Dadda multiplier for unsigned 16x16 bit multiplication with a Brent Kung adder for the final addition in synthesizable VHDL. |
| 11 | 1 | 0 | 5 years ago | [vhdl_sincos_gen](https://github.com/jorisvr/vhdl_sincos_gen)/418 | Sine / cosine function core in VHDL |
| 11 | 3 | 0 | 2 years ago | [vgg16-on-Zynq](https://github.com/flymin/vgg16-on-Zynq)/419 | Simulating implement of vgg16 network on Zynq-7020 FPGA |
| 11 | 6 | 0 | 3 months ago | [VCS-1](https://github.com/SundanceMultiprocessorTechnology/VCS-1)/420 | VCS-1 system |
| 11 | 13 | 0 | 5 years ago | [team_psx](https://github.com/anitazha/team_psx)/421 | 18545 Repo |
| 11 | 0 | 0 | 1 year, 8 months ago | [seqpu](https://github.com/pepijndevos/seqpu)/422 | A bit-serial CPU |
| 11 | 3 | 10 | 3 months ago | [spartan-edge-accelerator-graphical-system](https://github.com/smartperson/spartan-edge-accelerator-graphical-system)/423 | WIP Graphics layer and inter IC communication for the Spartan Edge Accelerator fpga/mcu hybrid board |
| 11 | 5 | 1 | 5 years ago | [RSA-Encryption](https://github.com/scarter93/RSA-Encryption)/424 | VHDL implementation of RSA encryption/decryption using Montgomery modular multipliers  |
| 11 | 5 | 7 | 1 year, 7 months ago | [fpgasdr](https://github.com/danupp/fpgasdr)/425 | FPGA firmware for FPGA radio baseband board. Scroll down for README. |
| 11 | 4 | 0 | 3 years ago | [srio_test](https://github.com/GOOD-Stuff/srio_test)/426 | Test SRIO connection between FPGA (Kintex-7) and DSP (C6678) |
| 11 | 1 | 0 | a month ago | [GBADVI](https://github.com/GameboxSystems/GBADVI)/427 | None |
| 11 | 1 | 0 | 9 years ago | [DCPU16-VHDL](https://github.com/isuru-c-p/DCPU16-VHDL)/428 | An implementation of the DCPU-16 from 0x10c in VHDL. |
| 11 | 2 | 2 | 2 years ago | [reVISION-Zybo-Z7-20](https://github.com/Digilent/reVISION-Zybo-Z7-20)/429 | None |
| 11 | 2 | 0 | 10 years ago | [cpu_arm](https://github.com/yuriks/cpu_arm)/430 | An ARMv4 compatible CPU core. (INCOMPLETE) |
| 11 | 1 | 0 | 3 months ago | [kpi-stuff](https://github.com/smithros/kpi-stuff)/431 | Some of my laboratories work in KPI and stuff connected with it. Can be called "palevo".  |
| 11 | 3 | 0 | 2 years ago | [BoostDSP](https://github.com/Cognoscan/BoostDSP)/432 | VHDL Library for implementing common DSP functionality. |
| 11 | 15 | 10 | 17 days ago | [Arcade-Galaxian_MiSTer](https://github.com/MiSTer-devel/Arcade-Galaxian_MiSTer)/433 | Arcade: Galaxian for MiSTer |
| 11 | 6 | 0 | 6 years ago | [FIRFilter](https://github.com/digibird1/FIRFilter)/434 | This project is a High and Low pass filter designer written in Octave to design and calculate the filter coefficients for a windows sinc filter. The coefficients can be used in the vhdl code for signal processing. |
| 11 | 3 | 0 | 9 years ago | [fpga-midi-synth](https://github.com/rene-dev/fpga-midi-synth)/435 | MIDI synthesizer written in VHDL |
| 11 | 7 | 0 | 2 years ago | [Sha256_Hw_Accelerator](https://github.com/martinafogliato/Sha256_Hw_Accelerator)/436 | SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent |
| 11 | 2 | 0 | 2 years ago | [prjtrellis-dvi](https://github.com/daveshah1/prjtrellis-dvi)/437 | DVI video out example for prjtrellis |
| 11 | 8 | 0 | 6 years ago | [Cameralink-LPC-FMC-Module](https://github.com/roy77/Cameralink-LPC-FMC-Module)/438 | None |
| 11 | 7 | 0 | 6 years ago | [miniOV7670](https://github.com/ahmadabbas55/miniOV7670)/439 | Interfacing OV7670 Camera module to miniSpartan6+ |
| 11 | 5 | 0 | 2 years ago | [GateKeeper](https://github.com/BilkentCompGen/GateKeeper)/440 | GateKeeper: Fast Alignment Filter for DNA Short Read Mapping |
| 11 | 0 | 2 | 9 years ago | [Papilio-Master-System](https://github.com/ben0109/Papilio-Master-System)/441 | None |
| 11 | 5 | 0 | 6 years ago | [fpga-led-matrix](https://github.com/ncortot/fpga-led-matrix)/442 | HDMI decoder and LED matrix controller on a Spartan-6 FPGA |
| 11 | 0 | 0 | 1 year, 1 month ago | [UK101onFPGA](https://github.com/emard/UK101onFPGA)/443 | Fork of the emulator for Compukit UK101 on FPGA |
| 11 | 0 | 0 | 3 years ago | [SAYEH](https://github.com/aminrashidbeigi/SAYEH)/444 | SAYEH cpu-memory basic computer |
| 11 | 6 | 0 | 6 years ago | [vhdl-project](https://github.com/alessandro-montanari/vhdl-project)/445 | Implementation in VHDL of the Sobel edge detection operator |
| 11 | 13 | 0 | 5 years ago | [miilink](https://github.com/jsyk/miilink)/446 | Connecting FPGA and MCU using Ethernet RMII |
| 11 | 10 | 1 | 9 months ago | [OpenHT](https://github.com/TonyBrewer/OpenHT)/447 | Hybrid Threading Tool Set |
| 11 | 3 | 0 | 2 years ago | [RealTimeVideo](https://github.com/MaksGolub/RealTimeVideo)/448 | High-speed real time streaming video on Zybo Z7-10 |
| 11 | 2 | 0 | 3 years ago | [adpll](https://github.com/filipamator/adpll)/449 | All digital PLL |
| 11 | 2 | 0 | 2 years ago | [Xilinx-Deep-Learning-Nexys4](https://github.com/TurtleTaco/Xilinx-Deep-Learning-Nexys4)/450 | Implemented Darius IP (originally target PYNQ) of convolution and maxpool on Xilinx FPGA with SDK |
| 11 | 8 | 0 | 4 years ago | [16-bit-HDLC-using-VHDL](https://github.com/shaan07/16-bit-HDLC-using-VHDL)/451 | High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language. |
| 11 | 2 | 0 | 9 months ago | [FPGA-X68k-DE0CV](https://github.com/kunichiko/FPGA-X68k-DE0CV)/452 | None |
| 10 | 2 | 0 | 11 years ago | [Pong](https://github.com/GarstgerUnhold/Pong)/453 | Pong for Spartan3 FPGA-Board written in VHDL |
| 10 | 0 | 0 | 5 years ago | [ADC_Sigma_Delta_VHDL](https://github.com/akukulanski/ADC_Sigma_Delta_VHDL)/454 | Sigma-Delta Analog to Digital Converter in FPGA (VHDL) |
| 10 | 6 | 1 | 1 year, 1 month ago | [ps2_cpld_kbd](https://github.com/andykarpov/ps2_cpld_kbd)/455 | ZX Spectrum PS/2 keyboard adapter |
| 10 | 2 | 0 | 1 year, 1 month ago | [hardware-sort](https://github.com/mmattioli/hardware-sort)/456 | Hardware-accelerated sorting algorithm |
| 10 | 10 | 4 | 5 months ago | [TRS-80_MiSTer](https://github.com/MiSTer-devel/TRS-80_MiSTer)/457 | Tandy TRS-80 Model I (port of HT1080Z to MiSTer) |
| 10 | 4 | 1 | 1 year, 6 months ago | [T-DLA](https://github.com/microideax/T-DLA)/458 | None |
| 10 | 4 | 0 | 3 years ago | [Aeon-Lite](https://github.com/ILoveSpeccy/Aeon-Lite)/459 | Aeon Lite - Open Source Reconfigurable Computer |
| 10 | 4 | 0 | 2 years ago | [s4noc](https://github.com/t-crest/s4noc)/460 | A Statically-scheduled TDM Network-on-Chip for Real-Time Systems |
| 10 | 7 | 0 | 4 years ago | [wireless-mac-processor](https://github.com/ict-flavia/wireless-mac-processor)/461 | None |
| 10 | 7 | 1 | 10 months ago | [camera-filters](https://github.com/olivier-le-sage/camera-filters)/462 | Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA. |
| 10 | 2 | 0 | 8 months ago | [cocotbExamples](https://github.com/qarlosalberto/cocotbExamples)/463 | None |
| 10 | 7 | 0 | 3 years ago | [pacedev](https://github.com/wsoltys/pacedev)/464 | Programmable Arcade Circuit Emulation |
| 10 | 0 | 0 | 1 year, 3 months ago | [32-bit-Brent-Kung-architecture](https://github.com/sourabh-suri/32-bit-Brent-Kung-architecture)/465 | Brent Kung architecture for adding 32 bit operands. |
| 10 | 6 | 1 | 2 years ago | [aws-fpga-miner](https://github.com/fpga-guide/aws-fpga-miner)/466 | None |
| 10 | 14 | 18 | 7 months ago | [bel_projects](https://github.com/GSI-CS-CO/bel_projects)/467 | GSI Timing Gateware and Tools |
| 10 | 2 | 0 | 10 days ago | [RISC-CPU](https://github.com/alirezakay/RISC-CPU)/468 | A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation ) |
| 10 | 4 | 2 | 5 years ago | [aes-fpga](https://github.com/parthpower/aes-fpga)/469 | AES implementation on FPGA  |
| 10 | 1 | 0 | 7 years ago | [PSP-Display-Driver](https://github.com/Hyvok/PSP-Display-Driver)/470 | VHDL code for driving a playstation portable display |
| 10 | 1 | 0 | 7 years ago | [vsim](https://github.com/grwlf/vsim)/471 | VHDL simulator in Haskell |
| 10 | 1 | 8 | 1 year, 8 months ago | [Arcade-DonkeyKongJunior_MiSTer](https://github.com/gaz68/Arcade-DonkeyKongJunior_MiSTer)/472 | Donkey Kong Junior arcade clone for MiSTer. |
| 10 | 1 | 0 | 1 year, 5 months ago | [cod19grp4](https://github.com/LyricZhao/cod19grp4)/473 | 奋战一学期 造台联网计算机（MIPS32 CPU + 硬件 RIP 路由器） |
| 10 | 1 | 1 | 1 year, 1 month ago | [360-NAND-X](https://github.com/Element18592/360-NAND-X)/474 | Clone of the NAND-X |
| 10 | 2 | 1 | 4 years ago | [tetris-vhdl](https://github.com/primiano/tetris-vhdl)/475 | A bare-metal pure hardware implementation of the Tetris game for FPGA |
| 10 | 4 | 0 | 20 days ago | [Mini_System](https://github.com/UniqueMR/Mini_System)/476 | Signal generator designed with Nexy4 FPGA |
| 10 | 4 | 1 | 7 years ago | [snes-flash](https://github.com/aiju/snes-flash)/477 | None |
| 10 | 4 | 2 | 7 years ago | [vhdl-csv-file-reader](https://github.com/ricardo-jasinski/vhdl-csv-file-reader)/478 | VHDL package for reading formatted data from comma-separated-values (CSV) files |
| 10 | 0 | 0 | 8 months ago | [VGA-6502](https://github.com/LIV2/VGA-6502)/479 | A VGA card for my homebrew 65C02 based computer |
| 10 | 3 | 0 | 4 years ago | [ImageCaptureSystem](https://github.com/Wissance/ImageCaptureSystem)/480 | A Xilinx IP Core and App for line scanner image capture and store |
| 10 | 2 | 1 | 3 years ago | [argh2600](https://github.com/elpuri/argh2600)/481 | VHDL implementation of an Atari 2600 |
| 10 | 1 | 0 | 8 years ago | [fp68060](https://github.com/amigabill/fp68060)/482 | PCB to plug FPGA softcore CPU into 68060 microprocessor socket |
| 10 | 1 | 0 | 6 years ago | [siphash](https://github.com/pemb/siphash)/483 | A VHDL implementation of SipHash |
| 10 | 95 | 0 | 7 days ago | [Digital-electronics-1](https://github.com/tomas-fryza/Digital-electronics-1)/484 | VHDL course at Brno University of Technology |
| 10 | 8 | 1 | 3 years ago | [Zybo-Z7-20-base-linux](https://github.com/Digilent/Zybo-Z7-20-base-linux)/485 | None |
| 10 | 1 | 0 | 3 years ago | [vu_meter](https://github.com/filipamator/vu_meter)/486 | FPGA-based FFT audio spectrum analyzer |
| 10 | 0 | 2 | Unknown | [AlteraMeatBoyHD](https://github.com/alteraMeatBoy/AlteraMeatBoyHD)/487 | Quartus project files for an Altera DE2 Meat Boy game. Proper functionality not guaranteed. |
| 10 | 0 | 0 | Unknown | [PingPongGame_CAD_VGA](https://github.com/avestura/PingPongGame_CAD_VGA)/488 | 🏓 A Ping Pong game written in VHDL with VGA support |
| 10 | 8 | 0 | Unknown | [VGA](https://github.com/AntonZero/VGA)/489 | VGA Tutorial for DE1  |
| 10 | 26 | 0 | Unknown | [riscv-multicycle](https://github.com/xtarke/riscv-multicycle)/490 | RISC-V muticycle implementation in VHDL. Core supports multiple peripherals and interruptions using a simple local interrupt controller. |
| 10 | 4 | 0 | Unknown | [fpga_cores](https://github.com/suoto/fpga_cores)/491 | None |
| 10 | 4 | 0 | Unknown | [MQP](https://github.com/glgauthier/MQP)/492 | Electrical and Computer Engineering Capstone |
| 10 | 2 | 0 | Unknown | [absenc](https://github.com/texane/absenc)/493 | Absolute encoder VHDL core |
| 10 | 2 | 1 | Unknown | [vextproj](https://github.com/wzab/vextproj)/494 | VEXTPROJ - the version control friendly system for creation of Vivado projects |
| 10 | 4 | 1 | Unknown | [FPGA_Mandelbrot](https://github.com/hamsternz/FPGA_Mandelbrot)/495 | A real-time Mandelbrot fractal viewer for FPGAs  |
| 10 | 6 | 0 | Unknown | [image_processing_examples](https://github.com/martinjthompson/image_processing_examples)/496 | Examples of image processing |
| 10 | 4 | 0 | Unknown | [2DImageProcessing](https://github.com/Wissance/2DImageProcessing)/497 | 2d Images processing system with FPGA (Zynq 7k) from two dragster linescanner (DR-2k-7) |
| 10 | 3 | 0 | Unknown | [FISC-VHDL](https://github.com/FISC-Project/FISC-VHDL)/498 | FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64 |
| 10 | 3 | 0 | Unknown | [MIPS](https://github.com/buccolo/MIPS)/499 | A pipelined MIPS processor written in VHDL (Unicamp/MC542) |
| 10 | 2 | 1 | Unknown | [Tiffany](https://github.com/bradleyeckert/Tiffany)/500 | A scalable MachineForth for PCs, MCUs and FPGAs. |
| 10 | 2 | 0 | 2 years ago | [8_bit_cpu](https://github.com/HellooYing/8_bit_cpu)/501 | ALINX ALTERA FPGA黑金开发学习板 CYCLONE IV 数电课设八位模型机 |
| 10 | 7 | 0 | 2 years ago | [AX7035](https://github.com/alinxalinx/AX7035)/502 | None |
| 10 | 8 | 1 | 4 months ago | [psi_common](https://github.com/paulscherrerinstitute/psi_common)/503 | Common elements for FPGA Design (FIFOs, RAMs, etc.) |
| 10 | 1 | 0 | 1 year, 6 months ago | [naiverouter](https://github.com/jiegec/naiverouter)/504 | A router IP written in Verilog. |
| 10 | 5 | 0 | 6 years ago | [NfcEmu](https://github.com/0xee/NfcEmu)/505 | SDR/FPGA-based NFC/RFID Emulator |
| 10 | 2 | 1 | 2 days ago | [AtariLynx_MiSTer](https://github.com/MiSTer-devel/AtariLynx_MiSTer)/506 | None |
| 9 | 10 | 0 | 1 year, 1 month ago | [FPGA-Vision](https://github.com/Marco-Winzker/FPGA-Vision)/507 | Learn about image processing with an FPGA. Video lectures explain algorithm and implementation of lane detection for automotive driving. Real hardware is available as a remote lab.  |
| 9 | 3 | 0 | 11 months ago | [FPGA-SPI-Flash](https://github.com/GOOD-Stuff/FPGA-SPI-Flash)/508 | Various projects of SPI loader module for xilinx fpga |
| 9 | 4 | 1 | 2 years ago | [Nexys-4-DDR-GPIO](https://github.com/Digilent/Nexys-4-DDR-GPIO)/509 | None |
| 9 | 7 | 0 | 4 years ago | [fpga](https://github.com/labnation/fpga)/510 | None |
| 9 | 1 | 0 | 4 years ago | [SimpleComputer](https://github.com/WilliamYi96/SimpleComputer)/511 | The design and implementation of simple computer by quartus. |
| 9 | 1 | 0 | 1 year, 2 months ago | [ImpeccableCircuits](https://github.com/emsec/ImpeccableCircuits)/512 | Hardware designs for fault detection |
| 9 | 6 | 5 | 4 months ago | [dsp-cores](https://github.com/lnls-dig/dsp-cores)/513 | Repository containing the DSP gateware cores |
| 9 | 8 | 1 | 2 months ago | [QL_MiSTer](https://github.com/MiSTer-devel/QL_MiSTer)/514 | Sinclair QL for MiSTer |
| 9 | 3 | 0 | 8 years ago | [fpgasynth](https://github.com/ksnieck/fpgasynth)/515 | VHDL for an FPGA based MIDI music synthesizer |
| 9 | 6 | 0 | 3 years ago | [bce-fpga-dev-kit](https://github.com/Cwndmiao/bce-fpga-dev-kit)/516 | bce-fpga-dev-kit |
| 9 | 12 | 1 | 2 years ago | [cnn-fpga-rtl](https://github.com/jhrabovsky/cnn-fpga-rtl)/517 | The CNN architecture elements implemented with RTL approach in VHDL. |
| 9 | 3 | 5 | 21 days ago | [pocket-cnn](https://github.com/marph91/pocket-cnn)/518 | CNN-to-FPGA-framework for small CNN, written in VHDL and Python |
| 9 | 10 | 0 | 6 years ago | [HLS-Axi-Master-on-Microzed-with-Yocto-Linux-device-driver](https://github.com/Architech-Silica/HLS-Axi-Master-on-Microzed-with-Yocto-Linux-device-driver)/519 | Creation of a AXI Master and Yocto device driver for Zynq, using High Level Synthesis (HLS) techniques. |
| 9 | 0 | 0 | 6 years ago | [macMonitor](https://github.com/bobparadiso/macMonitor)/520 | Xilinx VHDL project to drive a Mac Classic CRT |
| 9 | 2 | 1 | 8 months ago | [vhdl-cfg](https://github.com/eine/vhdl-cfg)/521 | Playground to explore and compare how configuration is handled by different tools for development of VHDL projects |
| 9 | 0 | 0 | 1 year, 28 days ago | [VHDL-FPGA-LAB_PROJECTS](https://github.com/mcagriaksoy/VHDL-FPGA-LAB_PROJECTS)/522 | Lab Assigments, Projects for digital systems II Lecture (EEM334) |
| 9 | 10 | 3 | 20 days ago | [Arcade-Tecmo_MiSTer](https://github.com/MiSTer-devel/Arcade-Tecmo_MiSTer)/523 | MiSTer arcade core for Tecmo arcade classics: Rygar (1986), Gemini Wing (1987), and Silkworm (1988). |
| 9 | 2 | 0 | a month ago | [atari_system1_fpga](https://github.com/d18c7db/atari_system1_fpga)/524 | FPGA implementation of Atari System 1 LSI arcade |
| 9 | 1 | 0 | 6 years ago | [ZPUino_miniSpartn6_plus](https://github.com/ahmadabbas55/ZPUino_miniSpartn6_plus)/525 | ZPUino for miniSpartan6+  |
| 9 | 3 | 0 | 4 years ago | [uCPUvhdl](https://github.com/reed-foster/uCPUvhdl)/526 | An 8-bit soft processor in VHDL |
| 9 | 4 | 0 | 10 years ago | [coded_aperture_vhdl](https://github.com/xcthulhu/coded_aperture_vhdl)/527 | vhdl code for simulating/synthesizing an FPGA backend of a coded aperture |
| 9 | 6 | 0 | 2 years ago | [LeNet-on-Zynq](https://github.com/flymin/LeNet-on-Zynq)/528 | Simulating implement of LeNet network on Zynq-7020 FPGA |
| 9 | 0 | 1 | 3 years ago | [maplebus](https://github.com/ismell/maplebus)/529 | Sega Dreamcast Maplebus Transceiver |
| 9 | 10 | 0 | 6 years ago | [VHDL_IP-Cores](https://github.com/OpenAutomationTechnologies/VHDL_IP-Cores)/530 | None |
| 9 | 0 | 1 | 4 years ago | [vertcl](https://github.com/kevinpt/vertcl)/531 | VHDL Tcl interpreter |
| 9 | 3 | 0 | 3 years ago | [Arty-Pmod-VGA](https://github.com/Digilent/Arty-Pmod-VGA)/532 | None |
| 9 | 2 | 1 | 5 years ago | [UART](https://github.com/Domipheus/UART)/533 | Simple UART implementation in VHDL |
| 9 | 3 | 0 | 7 years ago | [gandalf-miner](https://github.com/FrankBuss/gandalf-miner)/534 | bitcoin miner for the A3255-Q48 chip |
| 9 | 4 | 0 | 2 years ago | [UniversalPPU](https://github.com/RetroEmbedded/UniversalPPU)/535 | An FPGA replacement for the graphics chip used in the NES and related systems |
| 9 | 2 | 0 | 14 days ago | [RedPitaya_Acquisition](https://github.com/alex123go/RedPitaya_Acquisition)/536 | Transform the Red Pitaya in an acquisition card |
| 9 | 3 | 0 | 1 year, 4 months ago | [hashpipe](https://github.com/thinkski/hashpipe)/537 | SHA-256 Bitcoin hashing engine implemented as a systolic pipeline |
| 9 | 13 | 0 | 4 years ago | [SDSoC-platforms](https://github.com/Digilent/SDSoC-platforms)/538 | SDSoC platforms for Digilent Zynq boards |
| 9 | 6 | 17 | 7 years ago | [ECE383](https://github.com/toddbranch/ECE383)/539 | USAFA ECE383 course website. |
| 9 | 3 | 0 | 2 years ago | [robotter](https://github.com/robotter/robotter)/540 | Rob'Otter's code for Eurobot and the Coupe de France de robotique |
| 9 | 5 | 1 | 9 months ago | [CryptoHDL](https://github.com/hadipourh/CryptoHDL)/541 | A list of VHDL codes implementing cryptographic algorithms |
| 9 | 9 | 1 | 5 years ago | [zycap](https://github.com/warclab/zycap)/542 | Zynq PR Management |
| 9 | 2 | 5 | 6 months ago | [cpu](https://github.com/bit-mips/cpu)/543 | MIPS CPU |
| 9 | 5 | 0 | a day ago | [dsd](https://github.com/kevinwlu/dsd)/544 | Digital System Design |
| 9 | 5 | 0 | 1 year, 4 months ago | [vhdl-digital-design](https://github.com/fcayci/vhdl-digital-design)/545 | VHDL code examples for a digital design course |
| 9 | 7 | 1 | 6 years ago | [BeMicro-CV](https://github.com/tommythorn/BeMicro-CV)/546 | A "hello world" style designs for the Cyclone V based $49 Arrow BeMicro CV |
| 9 | 5 | 0 | 2 years ago | [cmips](https://github.com/rhexsel/cmips)/547 | All things related to cMIPS, a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core. |
| 9 | 3 | 0 | 3 months ago | [LMAC_CORE1](https://github.com/lewiz-support/LMAC_CORE1)/548 | LMAC Core1 - Ethernet 1G/100M/10M |
| 9 | 2 | 1 | 8 months ago | [ulx3s-ghdl-examples](https://github.com/kost/ulx3s-ghdl-examples)/549 | ulx3s ghdl examples |
| 9 | 4 | 0 | 2 years ago | [acoustic-levitation](https://github.com/leastrobino/acoustic-levitation)/550 | Acoustic levitation on SoC FPGA (DE0-Nano-SoC). Notice: this repository has moved to GitLab. All issues and pull requests should be created there. |
| 9 | 2 | 0 | 7 years ago | [zpu-lattice](https://github.com/iabdalkader/zpu-lattice)/551 | ZPU Core for Lattice ICE40HX8K |
| 9 | 15 | 0 | 8 years ago | [VinxFs](https://github.com/baranovmv/VinxFs)/552 | Small FAT16/FAT32 filesystem for ATMega8 (AVR / STM / PIC) with create/delete file |
| 9 | 1 | 0 | 4 years ago | [bcomp](https://github.com/MJoergen/bcomp)/553 | 8-bit computer |
| 9 | 1 | 0 | 5 years ago | [vhdl_verification](https://github.com/tmeissner/vhdl_verification)/554 | Examples and design pattern for VHDL verification |
| 9 | 4 | 0 | 2 years ago | [100cerebros](https://github.com/obiwit/100cerebros)/555 | Resoluções de exercícios e guiões de diversas disciplinas de MIECT, na UA |
| 9 | 8 | 2 | 7 years ago | [VHDL-Project-16-bit-RISC-Processor](https://github.com/sameersondur/VHDL-Project-16-bit-RISC-Processor)/556 | Designed a RISC processor with 16 bit instruction set, 4-stage pipeline and a non-pre-emptive interrupt handler. Implemented it in VHDL and tested it by simulating in ModelSim. |
| 9 | 4 | 0 | 4 years ago | [VGA_1.0](https://github.com/andrewandrepowell/VGA_1.0)/557 | AXI memory-mapped VGA module originally designed for the Avent Zedboard  |
| 9 | 2 | 0 | 1 year, 9 months ago | [udp_ip_stack](https://github.com/LarsAsplund/udp_ip_stack)/558 | UDP IP stack example project from this VUnit getting started blog (https://www.linkedin.com/pulse/vunit-best-value-initial-effort-lars-asplund) |
| 9 | 6 | 0 | 9 years ago | [simple-mips](https://github.com/tcamolesi/simple-mips)/559 | Simple MIPS processor written in VHDL |
| 9 | 5 | 0 | 4 years ago | [vhdl2008c](https://github.com/peteut/vhdl2008c)/560 | VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl |
| 9 | 8 | 1 | 5 months ago | [go2uvm](https://github.com/go2uvm/go2uvm)/561 | Main repo for Go2UVM source code, examples and apps |
| 9 | 0 | 0 | 2 years ago | [courses](https://github.com/mmaghajani/courses)/562 | About university courses and homeworks ... |
| 9 | 7 | 0 | 5 years ago | [wavelet-image-compression](https://github.com/isovic/wavelet-image-compression)/563 | Simple FPGA-based Wavelet Image Compression |
| 9 | 6 | 0 | 4 years ago | [VHDL](https://github.com/fabiopjve/VHDL)/564 | Some VHDL code |
| 9 | 6 | 5 | 1 year, 1 month ago | [cnn_vhdl_generator](https://github.com/mhamdan91/cnn_vhdl_generator)/565 | AUTOMATIC VHDL GENERATION FOR CNN MODELS |
| 9 | 4 | 1 | 3 years ago | [CPU-Adelie](https://github.com/Adelie-project/CPU-Adelie)/566 | None |
| 9 | 2 | 0 | 3 years ago | [Ultrasound-Beamforming-](https://github.com/abhishekgb/Ultrasound-Beamforming-)/567 | This project is basically ultrasound Beamformer prototype and FPGA is used to control all the modules of the Hardware. |
| 9 | 6 | 2 | 1 year, 6 months ago | [DivGMX](https://github.com/mvvproject/DivGMX)/568 | Development Kit |
| 9 | 6 | 0 | 3 years ago | [FPGA-shared-mem](https://github.com/FelixWinterstein/FPGA-shared-mem)/569 | Exploring Shared Virtual Memory Abstractions in OpenCL Tools for FPGAs |
| 9 | 1 | 0 | 2 years ago | [XNOR-net-Binary-connect](https://github.com/prateek22sri/XNOR-net-Binary-connect)/570 | A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacement of vector-matrix multiplication to “XNOR + Popcount” operation  |
| 9 | 2 | 0 | 4 years ago | [msgpack-vhdl](https://github.com/ikwzm/msgpack-vhdl)/571 | MessagePack  implementation for VHDL |
| 9 | 7 | 0 | 1 year, 8 months ago | [COD-Resources-2017](https://github.com/ustc-cs/COD-Resources-2017)/572 | 中科大 2017 级数字电路实验/组成原理实验的同学经验和资料分享 |
| 9 | 5 | 0 | 1 year, 16 days ago | [de10-nano-examples](https://github.com/nullobject/de10-nano-examples)/573 | DE10 Nano Sample Cores |
| 9 | 7 | 0 | 6 years ago | [aeshw](https://github.com/szanni/aeshw)/574 | None |
| 9 | 12 | 0 | 2 months ago | [realtimeEMTP](https://github.com/dickler/realtimeEMTP)/575 | FPGA and CPU-Based power system's simulator |
| 9 | 2 | 4 | 22 days ago | [Intv_MiSTer](https://github.com/MiSTer-devel/Intv_MiSTer)/576 | Intellivision for MiSTer |
| 8 | 0 | 0 | 7 years ago | [i2s-interface-vhdl](https://github.com/meriororen/i2s-interface-vhdl)/577 | A simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.  |
| 8 | 11 | 5 | 3 months ago | [VIC20_MiSTer](https://github.com/MiSTer-devel/VIC20_MiSTer)/578 | Commodore VIC-20 for MiSTer |
| 8 | 5 | 0 | 1 year, 3 months ago | [can-lite-vhdl](https://github.com/bggardner/can-lite-vhdl)/579 | A lightweight Controller Area Network (CAN) controller in VHDL |
| 8 | 2 | 0 | 1 year, 9 months ago | [Zynq_HLS_DDR_Dataflow_kernel_2mm](https://github.com/zslwyuan/Zynq_HLS_DDR_Dataflow_kernel_2mm)/580 | This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3  access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation |
| 8 | 6 | 0 | 11 months ago | [pipelineCPU](https://github.com/HandsomeBrotherShuaiLi/pipelineCPU)/581 | Five-Stage Pipeline CPU Implemented by Verilog on FPGA  Written By LI Shuai, it supports static and dynamic pipeline cpu. I am not  maintaining this repo for years. If there are bugs when you try it, debug by youself! :) |
| 8 | 2 | 0 | 1 year, 10 months ago | [efficient_checksum-offload-engine](https://github.com/hpcn-uam/efficient_checksum-offload-engine)/582 | Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream interface. |
| 8 | 3 | 2 | 2 years ago | [pim-vhdl](https://github.com/RandomReaper/pim-vhdl)/583 | My VHDL code |
| 8 | 3 | 0 | a year ago | [leon3-grlib-gpl-mirror](https://github.com/TUT-ASI/leon3-grlib-gpl-mirror)/584 | Git mirror of Gaisler's GRLIB/Leon3 releases |
| 8 | 8 | 0 | 6 years ago | [SHA3-VHDL](https://github.com/vishpbharadwaj/SHA3-VHDL)/585 | Hardware implementation of cryptographic Hash function SHA-3 (keccak) using VHDL |
| 8 | 2 | 0 | 6 years ago | [vhdl-game-engine](https://github.com/ricardo-jasinski/vhdl-game-engine)/586 | A game engine implemented purely in hardware using the VHDL language |
| 8 | 1 | 0 | 4 years ago | [16x2-LCD-Controller-VHDL](https://github.com/Maeur1/16x2-LCD-Controller-VHDL)/587 | A little program I wrote to control the LCD on my FPGA |
| 8 | 2 | 0 | 4 months ago | [chisel-study](https://github.com/horie-t/chisel-study)/588 | ハードウェア構築言語Chiselでちょっとしたコードを書き溜めておくプロジェクト |
| 8 | 4 | 0 | 3 years ago | [SECURE_HASH](https://github.com/ikwzm/SECURE_HASH)/589 | SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera). |
| 8 | 2 | 0 | 11 months ago | [blp](https://github.com/Martoni/blp)/590 | Blinking Led Project |
| 8 | 6 | 0 | 5 years ago | [pre-mipsfpga](https://github.com/MIPSfpga/pre-mipsfpga)/591 | Various Verilog examples to gain knowledge and basic skills before working with MIPSfpga |
| 8 | 1 | 0 | 4 months ago | [imagesensor_system](https://github.com/Kopei/imagesensor_system)/592 | This document is a project of cmos image sensor system. The doc mainly includes LUPA4000 Cmos sensor driving, SDRAM storage, LVDS data readout etc. The code is written in VHDL. |
| 8 | 3 | 0 | 4 years ago | [mdsynth](https://github.com/dcliche/mdsynth)/593 | FPGA-based synthesizer in VHDL for the Xilinx Spartan-3A and Spartan-3E Starter Kits |
| 8 | 8 | 0 | 1 year, 10 months ago | [SidewinderFPGA](https://github.com/ManuFerHi/SidewinderFPGA)/594 | Sidewinder FPGA |
| 8 | 0 | 0 | 5 months ago | [risc63](https://github.com/dominiksalvet/risc63)/595 | 💻 Custom 64-bit pipelined RISC processor. |
| 8 | 1 | 0 | 7 months ago | [VHDL](https://github.com/datacipy/VHDL)/596 | Příklady ke knize Data, čipy, procesory |
| 8 | 2 | 2 | 5 years ago | [oram_fpga](https://github.com/kwonalbert/oram_fpga)/597 | FPGA related files for ORAM |
| 8 | 1 | 0 | 3 years ago | [Team-SDK-545](https://github.com/kkudrolli/Team-SDK-545)/598 | An FPGA design project by Kais Kudrolli, Sohil Shah, and DongJoon Park for 18-545 at Carnegie Mellon University. |
| 8 | 1 | 0 | 3 months ago | [Pynq-Accelerator](https://github.com/LeiWang1999/Pynq-Accelerator)/599 | A easy general acc. |
| 8 | 6 | 3 | 4 years ago | [Zybo-hdmi-in](https://github.com/Digilent/Zybo-hdmi-in)/600 | None |
| 8 | 2 | 0 | 1 year, 6 months ago | [Handwritten-Digit-Recognition-Painter](https://github.com/j3soon/Handwritten-Digit-Recognition-Painter)/601 | A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog. |
| 8 | 2 | 0 | 9 days ago | [zxuno](https://github.com/spark2k06/zxuno)/602 | None |
| 8 | 3 | 0 | 1 year, 11 months ago | [DES-cracker](https://github.com/aletempiac/DES-cracker)/603 | DES cracking machine on FPGA |
| 8 | 0 | 1 | 1 year, 4 months ago | [posit_blas_hdl](https://github.com/lvandam/posit_blas_hdl)/604 | Posit Arithmetic Accelerator interfacing with Apache Arrow & CAPI SNAP |
| 8 | 11 | 0 | 4 years ago | [WM8731-Audio-codec-on-DE10Standard-FPGA-board](https://github.com/AntonZero/WM8731-Audio-codec-on-DE10Standard-FPGA-board)/605 | None |
| 8 | 0 | 0 | 1 year, 6 months ago | [tangnano_sample](https://github.com/osafune/tangnano_sample)/606 | Tang-nano LCD sample |
| 8 | 2 | 1 | 8 years ago | [gbcpu](https://github.com/jdeblese/gbcpu)/607 | A CPU and peripherals implementing the Gameboy (TM) instruction set and functionality |
| 8 | 1 | 0 | 6 years ago | [PothosFPGA](https://github.com/pothosware/PothosFPGA)/608 | Pothos FPGA computational offload and buffer integration support |
| 8 | 4 | 0 | 5 years ago | [FPGA-LCD-Driver](https://github.com/goran-mahovlic/FPGA-LCD-Driver)/609 | FPGA LVDS LCD driver |
| 8 | 5 | 0 | 8 years ago | [soc_leon3](https://github.com/teeshina/soc_leon3)/610 | System on Chip SPARC V8 using leon3 CPU by Gaisler. C++, vhdl, v files. |
| 8 | 2 | 0 | 8 years ago | [sdr](https://github.com/rcls/sdr)/611 | A software-defined radio. |
| 8 | 4 | 0 | 5 years ago | [rdsfpga](https://github.com/emard/rdsfpga)/612 | RDS FM modulator for FPGA |
| 8 | 0 | 0 | 3 years ago | [zlogan](https://github.com/eltvor/zlogan)/613 | High-througput logic analyzer for FPGA |
| 8 | 2 | 0 | 2 years ago | [GNSS-VHDL](https://github.com/danipascual/GNSS-VHDL)/614 | VHDL codes to generate GPS L1 C/A and Galileo E1OS and E5 PRNs and dataless signals. Secondary codes not included. |
| 8 | 2 | 1 | 3 years ago | [FpgaMicrotubule](https://github.com/urock/FpgaMicrotubule)/615 | HPC Implementation of dynamic microtubules calculations on CPU, GPU and FPGA Platforms |
| 8 | 0 | 0 | 6 years ago | [AM2901](https://github.com/Amrnasr/AM2901)/616 | None |
| 8 | 7 | 0 | 6 years ago | [Xilinx-GPIO-Interrupt](https://github.com/Micro-Studios/Xilinx-GPIO-Interrupt)/617 | It is a GPIO interrupt example for xilinx ZYNQ FPGA.  |
| 8 | 5 | 0 | 1 year, 9 months ago | [Zedboard-DMA](https://github.com/Digilent/Zedboard-DMA)/618 | None |
| 8 | 3 | 0 | 1 year, 9 months ago | [Hardware-Course](https://github.com/yujincheng08/Hardware-Course)/619 | All the verilog code I wrote in hardware Course |
| 8 | 11 | 0 | 3 years ago | [AX7015](https://github.com/alinxalinx/AX7015)/620 | AX7015 |
| 8 | 1 | 0 | 2 years ago | [OscilloscopeBoom](https://github.com/wtywtykk/OscilloscopeBoom)/621 | Display something on an analog oscilloscope |
| 8 | 0 | 4 | 5 years ago | [tis100cpu](https://github.com/jdryg/tis100cpu)/622 | TIS-100 CPU in VHDL |
| 8 | 4 | 0 | 7 years ago | [mbc5-clone](https://github.com/sth0r/mbc5-clone)/623 | this is a clone of zakos mbcx found at https://gitorious.org/mbcx/mbcx. I'll try to make my own itteration of the mbcx. |
| 8 | 15 | 0 | 1 year, 11 months ago | [GlobalCorrelator](https://github.com/p2l1pfp/GlobalCorrelator)/624 | Firmware for Level-1 Particle Reconstruction |
| 8 | 13 | 4 | 3 months ago | [Vectrex_MiSTer](https://github.com/MiSTer-devel/Vectrex_MiSTer)/625 | Vectrex for MiSTer |
| 8 | 5 | 0 | 4 months ago | [TMS5220_FPGA](https://github.com/d18c7db/TMS5220_FPGA)/626 | VHDL model of TMS5220 voice synthesizer processor |
| 8 | 0 | 0 | 1 year, 11 months ago | [Digital-Recognition](https://github.com/liuweistrong/Digital-Recognition)/627 | 2019年Xilinx FPGA暑期学校项目学习 数字识别项目 Digital Recognition  |
| 8 | 1 | 1 | 5 months ago | [Brutzelkarte_FPGA](https://github.com/jago85/Brutzelkarte_FPGA)/628 | The Brutzelkarte FPGA description code in VHDL |
| 8 | 2 | 3 | 4 days ago | [WonderSwan_MiSTer](https://github.com/MiSTer-devel/WonderSwan_MiSTer)/629 | WonderSwan Color for MiSTer |
| 8 | 0 | 0 | 8 years ago | [rekonstrukt](https://github.com/hanshuebner/rekonstrukt)/630 | FPGA based Forth development environment / Forth based FPGA development environment |
| 8 | 2 | 0 | 6 years ago | [hls_stream](https://github.com/sukinull/hls_stream)/631 | Xilinx HLS video library using hls::stream w/ Vivado 2014.4 or Later |
| 8 | 1 | 0 | 4 years ago | [ws2812b-vhdl](https://github.com/m42uko/ws2812b-vhdl)/632 | A controller for the WorldSemi WS2812B RGB LEDs written in plain VHDL. |
| 8 | 0 | 0 | 1 year, 6 months ago | [MiSTer-Arcade-AtariTetris](https://github.com/MrX-8B/MiSTer-Arcade-AtariTetris)/633 | FPGA implementation of ATARI's Tetris arcade game |
| 8 | 6 | 0 | 4 years ago | [GBA](https://github.com/mara-kr/GBA)/634 | GameBoy Advance Zedboard Implementation |
| 8 | 1 | 0 | 3 years ago | [MIST_C64](https://github.com/Braincell1973/MIST_C64)/635 | FPGA implementation of a Commodore 64 |
| 8 | 2 | 7 | 15 days ago | [R32V2020](https://github.com/douggilliland/R32V2020)/636 | My 32-bit RISC CPU for smallish FPGAs |
| 8 | 2 | 2 | 5 years ago | [VHDL-FIR-filters](https://github.com/BBN-Q/VHDL-FIR-filters)/637 | Synthesizable FIR filters in VHDL |
| 8 | 2 | 0 | 9 months ago | [hdl_string_format](https://github.com/suoto/hdl_string_format)/638 | VHDL package to provide C-like string formatting |
| 8 | 1 | 0 | 4 months ago | [hitsz-eie-codes](https://github.com/bugstep/hitsz-eie-codes)/639 | 哈工大深圳 电信学院 通信工程 部分实验课程代码仓库 |
| 8 | 4 | 0 | 6 years ago | [AVR-Processor](https://github.com/agural/AVR-Processor)/640 | VHDL implementation of an AVR processor. |
| 8 | 2 | 0 | 6 years ago | [dmkonst](https://github.com/lionleaf/dmkonst)/641 | An optimized pipelined MIPS CPU written in VHDL |
| 8 | 2 | 0 | 5 months ago | [fsva](https://github.com/m-kru/fsva)/642 | FuseSoc Verification Automation |
| 8 | 2 | 0 | 3 years ago | [GNSS-VHDL](https://github.com/ganlubbq/GNSS-VHDL)/643 | GNSS codes and signal generation for VHDL. GPS (L1 C/A, L5), Galileo (E1OS, E5). Includes Xilinx ISE testbench and wave configuration files. |
| 8 | 2 | 0 | a month ago | [ReconROS](https://github.com/Lien182/ReconROS)/644 | Easy to use framework for ROS2 FPGA-based hardware acceleration; Supports Pub/Sub communication, Actions and Services and costum ROS Messages |
| 8 | 2 | 0 | 1 year, 5 days ago | [CycloneV_UnAmiga_v2](https://github.com/benitoss/CycloneV_UnAmiga_v2)/645 | Cyclone V FPGA board for UnAmiga project with new addon 6 Buttons Megadrive Joystick |
| 8 | 1 | 1 | 6 months ago | [vhlib](https://github.com/abs-tudelft/vhlib)/646 | Package of miscellaneous VHDL libraries |
| 8 | 2 | 3 | 1 year, 1 month ago | [SAMCoupe_MIST](https://github.com/sorgelig/SAMCoupe_MIST)/647 | SAM Coupe for MiST board |
| 8 | 4 | 0 | 5 years ago | [vhdI2CMaster](https://github.com/tirfil/vhdI2CMaster)/648 | I2C Master FSM (vhdl) |
| 8 | 0 | 1 | 2 years ago | [pipemania-fpga-game](https://github.com/jakubcabal/pipemania-fpga-game)/649 | Pipe Mania - Game for FPGA written in VHDL |
| 8 | 4 | 0 | 5 years ago | [kvcordic](https://github.com/nkkav/kvcordic)/650 | Multi-function, universal, fixed-point CORDIC |
| 8 | 5 | 0 | 7 years ago | [lzw_verilog](https://github.com/arshadri/lzw_verilog)/651 | LZW Compressoion algorithm in verilog |
| 8 | 7 | 1 | 6 years ago | [OLED_on_ZedBoard](https://github.com/faab64/OLED_on_ZedBoard)/652 | OLED test code from Digilink modified to work on the Zedboard |
| 8 | 12 | 0 | 3 years ago | [AX7020](https://github.com/alinxalinx/AX7020)/653 | None |
| 8 | 7 | 0 | 2 years ago | [AD9361_TX_GMSK](https://github.com/Grootzz/AD9361_TX_GMSK)/654 | A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK |
| 8 | 8 | 1 | 1 year, 1 month ago | [capi2-bsp](https://github.com/open-power/capi2-bsp)/655 | CAPI 2.0 Board Support Package |
| 8 | 2 | 1 | a month ago | [b01lers-library](https://github.com/b01lers/b01lers-library)/656 | None |
| 8 | 12 | 2 | 18 days ago | [Arcade-BombJack_MiSTer](https://github.com/MiSTer-devel/Arcade-BombJack_MiSTer)/657 | Arcade: Bomb Jack for MiSTer |
| 8 | 0 | 0 | 3 years ago | [VHDLMatrixMultiplier](https://github.com/federicorossifr/VHDLMatrixMultiplier)/658 | VHDL implementation for a Matrix Multiplier |
| 8 | 2 | 0 | 3 years ago | [snickerdoodle-hls-data-mover](https://github.com/krtkl/snickerdoodle-hls-data-mover)/659 | A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S defaults to 8 bits and AXI-MM to 64 bits) |
| 8 | 2 | 0 | 2 months ago | [6_semestre](https://github.com/aMurryFly/6_semestre)/660 | Repositorio de todo el material del 6° semestre de Ingeniería en Computación, Facultad de Ingeniería, UNAM |
| 8 | 9 | 8 | 14 days ago | [Arcade-IremM62_MiSTer](https://github.com/MiSTer-devel/Arcade-IremM62_MiSTer)/661 | Irem62 from pace, and mist including Lode Runner, etc |
| 8 | 8 | 0 | 10 years ago | [udp_ip__core](https://github.com/freecores/udp_ip__core)/662 | UDP/IP Core |
| 8 | 2 | 1 | 5 years ago | [gpib](https://github.com/brouhaha/gpib)/663 | IEEE-488 (GP-IB, HP-IB) synthesizable core in VHDL |
| 7 | 0 | 0 | 10 years ago | [Brainfuck-Processor](https://github.com/konne88/Brainfuck-Processor)/664 | A simple brainfuck processor implemented in VHDL. |
| 7 | 6 | 0 | 15 years ago | [ofdm](https://github.com/freecores/ofdm)/665 | OFDM modem |
| 7 | 2 | 0 | 1 year, 11 months ago | [NexysPsram](https://github.com/andrewsil1/NexysPsram)/666 | AXI PSRAM Controller IP for use with Digilent Nexys 4 |
| 7 | 4 | 0 | 1 year, 2 months ago | [vhdl](https://github.com/texane/vhdl)/667 | vhdl related contents |
| 7 | 4 | 0 | 1 year, 11 months ago | [Circuitos_Reconfiguraveis](https://github.com/DanielMunozArboleda/Circuitos_Reconfiguraveis)/668 | Repositório da disciplina de Projeto com Circuitos Reconfiguráveis do curso de Engenharia Eletrônica da Faculdade UnB Gama. | Repository for the discipline  Reconfigurable Circuits Design at the Electronics Engineering course at Faculty of Gama, UnB. |
| 7 | 2 | 0 | 2 years ago | [Amiga600GALFirmware](https://github.com/fdivitto/Amiga600GALFirmware)/669 | Amiga 600 with Gayle 1: VHDL implementation of PAL16L8B (XU1) with Lattice GAL16V8 |
| 7 | 1 | 0 | 2 years ago | [I2S_sender](https://github.com/dwjbosman/I2S_sender)/670 | VHDL I2S transmitter |
| 7 | 0 | 0 | 1 year, 8 months ago | [DIYPOV](https://github.com/im-pro-at/DIYPOV)/671 |  One POV Display to rule them all! |
| 7 | 1 | 1 | 1 year, 6 months ago | [metamachine](https://github.com/losfair/metamachine)/672 | Experimental CPU with software-defined instruction set. |
| 7 | 2 | 0 | 4 years ago | [USTC-tMIPS](https://github.com/suquark/USTC-tMIPS)/673 | None |
| 7 | 2 | 0 | 17 days ago | [VHDPlus_Libraries_and_Examples](https://github.com/leonbeier/VHDPlus_Libraries_and_Examples)/674 | This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with future updates. |
| 7 | 0 | 0 | 6 days ago | [GettingStarted_Examples](https://github.com/Accelize/GettingStarted_Examples)/675 | This repository contains a collection of reference designs and software application to get starter with Accelize Distribution Platform |
| 7 | 0 | 0 | 6 years ago | [TicksPicker](https://github.com/DrSchottky/TicksPicker)/676 | Tiny VHDL  postbit length extractor |
| 7 | 11 | 1 | 4 years ago | [OFDM_Synchronization](https://github.com/NeilJudson/OFDM_Synchronization)/677 | Design a new OFDM synchronization algorithm, and implement it with both Matlab and Verilog. |
| 7 | 0 | 0 | 2 years ago | [adc_configurator](https://github.com/capitanov/adc_configurator)/678 | ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on) |
| 7 | 1 | 0 | 8 months ago | [NeoVGA](https://github.com/Mikejmoffitt/NeoVGA)/679 | Old / abandoned NeoVGA VHDL source. Will not be maintained. |
| 7 | 13 | 0 | 2 years ago | [RTL-collection](https://github.com/x724/RTL-collection)/680 | a collection of open sourced VHDL for cryptography |
| 7 | 3 | 1 | 2 years ago | [Space-Invaders-for-MiSTer](https://github.com/davewoo999/Space-Invaders-for-MiSTer)/681 | None |
| 7 | 4 | 1 | 4 years ago | [digital-storage-oscilloscope](https://github.com/Gripnook/digital-storage-oscilloscope)/682 | An FPGA implementation of a digital storage oscilloscope. |
| 7 | 6 | 0 | 6 years ago | [FPGA_ADC](https://github.com/digibird1/FPGA_ADC)/683 | Interface the AD9057 with a cyclone III FPGA |
| 7 | 2 | 0 | 4 years ago | [FPGA_Flappy_Bird](https://github.com/lukehsiao/FPGA_Flappy_Bird)/684 | :bird: a simple hardware-implementation of the viral game "Flappy Bird" built for use on the Digilent NEXYS 2 Development Board (XC3S500E-FG320) |
| 7 | 3 | 0 | 6 years ago | [Stepper-Motor-Control](https://github.com/gismo141/Stepper-Motor-Control)/685 | System on a Chip - Design for a stepper-motor-control with NIOS II/s µC on Cyclone IV/V FPGA |
| 7 | 5 | 2 | 8 years ago | [ethernet_mac](https://github.com/pabennett/ethernet_mac)/686 | A VHDL implementation of an Ethernet MAC |
| 7 | 2 | 1 | 1 year, 10 months ago | [light8080](https://github.com/jaruiz/light8080)/687 | Synthesizable i8080-compatible CPU core. |
| 7 | 3 | 0 | 4 years ago | [ADC_LCD_FPGA](https://github.com/jaspreetsingh009/ADC_LCD_FPGA)/688 | ADC & LCD Interfacing using Verilog & VHDL |
| 7 | 2 | 0 | 5 months ago | [PDP-11](https://github.com/Moodrammer/PDP-11)/689 | :computer: Simulation for the architecture of a processor inspired by the ideas of PDP-11 processor |
| 7 | 3 | 0 | 8 years ago | [vhdl-examples](https://github.com/khaledhassan/vhdl-examples)/690 | VHDL example code |
| 7 | 1 | 0 | 10 years ago | [CPLD_USBHxCFloppyEmulator](https://github.com/jfdelnero/CPLD_USBHxCFloppyEmulator)/691 | CPLD USB HxC Floppy Emulator |
| 7 | 3 | 0 | 7 years ago | [FIX](https://github.com/sufengniu/FIX)/692 | FIX for (High Frequency Trading) HFT |
| 7 | 4 | 1 | 4 years ago | [ece5775-final](https://github.com/shivarajagopal/ece5775-final)/693 | Voice Recognition using FPGA-Based Neural Networks |
| 7 | 0 | 0 | 4 years ago | [UART_in_VHDL](https://github.com/ttsiodras/UART_in_VHDL)/694 | My successful first experiment in VHDL - creating my own UART |
| 7 | 0 | 2 | 1 year, 2 months ago | [big80](https://github.com/toptensoftware/big80)/695 | FPGA Implementation of a TRS-80 Model 1 |
| 7 | 5 | 0 | 3 years ago | [ZYBO_IoT_Vivado](https://github.com/iwatake2222/ZYBO_IoT_Vivado)/696 | This is a Vivado project to create an IoT device with ZYBO (Zynq). |
| 7 | 4 | 1 | 3 years ago | [Nexys-4-OOB](https://github.com/Digilent/Nexys-4-OOB)/697 | None |
| 7 | 0 | 0 | 3 years ago | [SAYEH-Cache](https://github.com/aminrashidbeigi/SAYEH-Cache)/698 | implementing SAYEH cache using VHDL |
| 7 | 1 | 0 | 8 months ago | [MasterThesis](https://github.com/SpyrosMouselinos/MasterThesis)/699 | VHDL implementation of a customizable CNN |
| 7 | 4 | 1 | 2 years ago | [kvm-ip-zynq](https://github.com/ssincan/kvm-ip-zynq)/700 | KVM over IP Gateway targeting Zynq-7000 SoC |
| 7 | 4 | 1 | 2 years ago | [kvm-ip-zynq](https://github.com/ssincan/kvm-ip-zynq)/701 | KVM over IP Gateway targeting Zynq-7000 SoC |
| 7 | 8 | 3 | 13 days ago | [PandABlocks-FPGA](https://github.com/PandABlocks/PandABlocks-FPGA)/702 | VHDL functional blocks with their simulations and test sequences |
| 7 | 1 | 0 | 9 months ago | [A500-EXT-CFIDE](https://github.com/EmberHeavyIndustries/A500-EXT-CFIDE)/703 | None |
| 7 | 3 | 0 | 4 years ago | [mips--](https://github.com/jevinskie/mips--)/704 | A dual core MIPS subset CPU written in behavioral, synthesizable VHDL |
| 7 | 4 | 0 | 3 years ago | [reloc](https://github.com/bgottschall/reloc)/705 | Designing Relocatable FPGA Partitions with Vivado Design Suite |
| 7 | 8 | 0 | 11 months ago | [Amstrad_MiST](https://github.com/sorgelig/Amstrad_MiST)/706 | None |
| 7 | 4 | 0 | 6 months ago | [MSHR-rich](https://github.com/m-asiatici/MSHR-rich)/707 | A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency-insensitive hardware accelerators with irregular memory access patterns. |
| 7 | 6 | 0 | 1 year, 3 months ago | [Backup-of-undergraduate-study-materials](https://github.com/JairZhu/Backup-of-undergraduate-study-materials)/708 | 本科学习资料备份 |
| 7 | 0 | 0 | 1 year, 10 months ago | [PIC16C6XX](https://github.com/Ernegien/PIC16C6XX)/709 | Original Xbox SMC Power Glitching Attack (WIP) |
| 7 | 0 | 0 | 3 months ago | [CRYSTALS-Kyber](https://github.com/xingyf14/CRYSTALS-Kyber)/710 | None |
| 7 | 8 | 0 | 21 days ago | [LimeADPD](https://github.com/myriadrf/LimeADPD)/711 | Lime Adaptive Digital Predistortion |
| 7 | 3 | 0 | 6 years ago | [CPME48](https://github.com/DeathKing/CPME48)/712 | Why CP-YOU? Let's CP-ME! 非常简单的8位CPU的VHDL实现，拥有精简的RISC式指令集。更有配套扩展指令集IR48*、汇编器DASM48、高级语言Cheme，你值得拥有。（课程作业，仅供交流，切勿抄袭！） |
| 7 | 6 | 0 | 9 years ago | [grlib](https://github.com/trondd/grlib)/713 | None |
| 7 | 6 | 0 | 6 years ago | [montecarlo-fpga](https://github.com/cyenko/montecarlo-fpga)/714 | Black-Scholes style options pricing using Monte Carlo methods. Written in VHDL for the Cyclone IV FPGA board. |
| 7 | 0 | 0 | 4 years ago | [MyRISC](https://github.com/bigbrett/MyRISC)/715 | VHDL implementation of a 16-bit RISC processor targeting the BASYS3 FPGA |
| 7 | 9 | 0 | 6 years ago | [TE0720-GigaZee-Reference-Designs](https://github.com/Trenz-Electronic/TE0720-GigaZee-Reference-Designs)/716 | Reference Projects for TE0720 ZYNQ module |
| 7 | 3 | 0 | 5 years ago | [SNN_vhdl](https://github.com/isadorasophia/SNN_vhdl)/717 | Implementation of an Artificial Neural Network (ANN) on FPGA using VHDL |
| 7 | 6 | 0 | 5 years ago | [aes-dom](https://github.com/hgrosz/aes-dom)/718 | DOM Protected Hardware Implementation of AES |
| 7 | 0 | 0 | 4 months ago | [8-bit-Computer](https://github.com/oddek/8-bit-Computer)/719 | Implementation of an 8-bit computer in VHDL, along with a minimal assembler |
| 7 | 5 | 2 | 5 years ago | [riffa](https://github.com/farhanrahman/riffa)/720 | RIFFA (Reusable Integration Framework for FPGA Accelerators) is a framework developed in University of California, San Diego. This project utilises the RIFFA framework to define an interface to interact with a user's IP core on the FPGA to send and receive data to and from the PC. This particular project is being developed under Imperial College London. |
| 7 | 2 | 0 | 3 years ago | [VGA_mem_mapped](https://github.com/delhatch/VGA_mem_mapped)/721 | Memory-mapped VGA display for Xilinx/Zynq/Zedboard, with demo code for using it. |
| 7 | 0 | 0 | 1 year, 10 months ago | [SoC-Nios](https://github.com/ihabadly/SoC-Nios)/722 | Building an example System on Chip (SoC) using Nios II processor. |
| 7 | 1 | 2 | 7 years ago | [S76D](https://github.com/domoritz/S76D)/723 | Singing Very High Speed Integrated Circuit Hardware Description Language Board |
| 7 | 2 | 0 | 3 years ago | [fpga_fifo](https://github.com/bradkahn/fpga_fifo)/724 | Asynchronous FIFO for FPGAs |
| 7 | 3 | 0 | 1 year, 9 months ago | [single-cycle-processor](https://github.com/spencerwooo/single-cycle-processor)/725 | An implementation of the simplest single cycle processor. |
| 7 | 0 | 0 | 5 months ago | [2021_CQU_NSCSCC](https://github.com/wang-sy/2021_CQU_NSCSCC)/726 | 2021_CQU_NSCSCC_RTL_CODE |
| 7 | 7 | 5 | 15 days ago | [aws-fpga-firesim](https://github.com/firesim/aws-fpga-firesim)/727 | AWS Shell for FireSim |
| 7 | 1 | 5 | 4 years ago | [ProjectZ](https://github.com/AasthaGupta/ProjectZ)/728 | Attempt to implement MultiLayer Perceptron in hardware descriptive language like VHDL. |
| 7 | 1 | 0 | 1 year, 2 months ago | [Zybo-Linux](https://github.com/Kampi/Zybo-Linux)/729 | A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary to run your own embedded Linux on your ZYBO here. |
| 7 | 11 | 1 | 20 days ago | [Arcade-Xevious_MiSTer](https://github.com/MiSTer-devel/Arcade-Xevious_MiSTer)/730 | Arcade: Xevious for MiSTer |
| 7 | 0 | 0 | 9 years ago | [BLOB-Detection](https://github.com/ThadeuMelo/BLOB-Detection)/731 | Blob Detection in HDL |
| 7 | 12 | 3 | 4 months ago | [ColecoVision_MiSTer](https://github.com/MiSTer-devel/ColecoVision_MiSTer)/732 | ColecoVision for MiSTer |
| 7 | 4 | 0 | 1 year, 10 months ago | [Nexys-A7-100T-OOB](https://github.com/Digilent/Nexys-A7-100T-OOB)/733 | None |
| 7 | 4 | 4 | 5 months ago | [SharpMZ_MiSTer](https://github.com/MiSTer-devel/SharpMZ_MiSTer)/734 | Sharp MZ Series Personal/Business Computer Emulator for FPGA |
| 7 | 1 | 0 | 1 year, 8 months ago | [LSTM_FPGA](https://github.com/mahi97/LSTM_FPGA)/735 | ~ Implementation of LSTM ANN in FPGA with VHDL |
| 7 | 3 | 0 | 1 year, 8 months ago | [VHDL-CPU](https://github.com/murilodepa/VHDL-CPU)/736 | Simple CPU written in VHDL. |
| 7 | 4 | 0 | 3 months ago | [CrowdSupplyWorkShop1](https://github.com/ATaylorCEngFIET/CrowdSupplyWorkShop1)/737 | None |
| 7 | 14 | 0 | 5 years ago | [xapp1026](https://github.com/tmatsuya/xapp1026)/738 | LightWeight IP Application Examples for Xilinx FPGA |
| 7 | 1 | 0 | 5 years ago | [scanline-stereo-vision-FPGA](https://github.com/euler2dot7/scanline-stereo-vision-FPGA)/739 | Implementazione VHDL dell’algoritmo Scanline |
| 7 | 5 | 2 | 5 years ago | [purisc](https://github.com/purisc-group/purisc)/740 | Pipelined Ultimate Reduced Instruction Set Computer |
| 7 | 1 | 0 | 3 years ago | [patmos_HLS](https://github.com/A-T-Kristensen/patmos_HLS)/741 | Hardware Accelerators (HwAs) constructed in Vivado HLS |
| 7 | 2 | 0 | 3 years ago | [Bitmap-VHDL-Package](https://github.com/mr-kenhoff/Bitmap-VHDL-Package)/742 | A vhdl package for reading and writing bitmap files. |
| 7 | 7 | 0 | 7 years ago | [SpaceWireRMAPTargetIP](https://github.com/shimafujigit/SpaceWireRMAPTargetIP)/743 | None |
| 7 | 0 | 0 | 19 days ago | [MicroCodeCompiler](https://github.com/zpekic/MicroCodeCompiler)/744 | Initial publish |
| 7 | 2 | 0 | 2 years ago | [Architecture-of-CPU-projects](https://github.com/MaorAssayag/Architecture-of-CPU-projects)/745 | VHDL , ModelSIM, Quartus, FPGA, Image Processing |
| 7 | 4 | 0 | 1 year, 3 months ago | [Verilog_Module](https://github.com/WayneGong/Verilog_Module)/746 | 常用Verilog模块 |
| 7 | 8 | 0 | 7 years ago | [fpga](https://github.com/HighlandersFRC/fpga)/747 | This repository holds all the projects and docs relating to our work with the Xilinx Zynq 7000 series FPGAs. |
| 7 | 0 | 0 | 1 year, 4 months ago | [Basic-Computer-design](https://github.com/Pooryamn/Basic-Computer-design)/748 | A Computer description using VHDL and ModelSim software |
| 7 | 5 | 0 | 6 years ago | [SDRAM-and-FIFO-for-DE1-SoC](https://github.com/AntonZero/SDRAM-and-FIFO-for-DE1-SoC)/749 | tutorial |
| 7 | 0 | 0 | 5 years ago | [65816_Interface_System](https://github.com/tropical-peach/65816_Interface_System)/750 | Soft Core of 65816 in VHDL |
| 7 | 1 | 0 | 8 years ago | [Mandelbrot-VHDL](https://github.com/imr/Mandelbrot-VHDL)/751 | Mandelbrot Set in VHDL targetting the Cyclone IVE found on a DE2-115 board. |
| 7 | 1 | 0 | 5 years ago | [MT32_Rand_Gen](https://github.com/ikwzm/MT32_Rand_Gen)/752 | Mersenne Twister Pseudo Random Number Generator written in VHDL(RTL) for FPGA(Xilinx and Altera). |
| 7 | 2 | 0 | 4 years ago | [FPGADisplay-ipcore](https://github.com/zxcmehran/FPGADisplay-ipcore)/753 | FPGA VGA Display Handler - IP Core Repository |
| 7 | 6 | 0 | 1 year, 5 months ago | [UVVM_Community_VIPs](https://github.com/UVVM/UVVM_Community_VIPs)/754 | Repository for the UVVM community to share VIPs.      Community forum: https://forum.uvvm.org/    UVVM.org: https://uvvm.org/ |
| 7 | 2 | 0 | 10 months ago | [RISCV-32I](https://github.com/NikosDelijohn/RISCV-32I)/755 | RISC V 32 bit Base ISA Implementation.  |
| 7 | 1 | 0 | 1 year, 8 days ago | [CQU_Computer_Organization](https://github.com/barryZZJ/CQU_Computer_Organization)/756 | 重庆大学计组实验vivado工程文件+项目汇编语言 |
| 7 | 7 | 1 | 1 year, 9 months ago | [LimeNET-Micro_GW](https://github.com/myriadrf/LimeNET-Micro_GW)/757 | Intel MAX10 FPGA project for the LimeNet-Mini board  |
| 7 | 3 | 24 | 1 year, 1 month ago | [FPGA_MNIST](https://github.com/marbleton/FPGA_MNIST)/758 | None |
| 7 | 2 | 0 | 3 years ago | [POV](https://github.com/im-pro-at/POV)/759 | 131*131*12bit 16FPS POV Display |
| 7 | 7 | 0 | 7 years ago | [SpaceWireRouterIP_6PortVersion](https://github.com/shimafujigit/SpaceWireRouterIP_6PortVersion)/760 | None |
| 7 | 3 | 0 | 8 years ago | [bf_cpu](https://github.com/Ttl/bf_cpu)/761 | Brainfuck microprocessor |
| 7 | 3 | 0 | 10 months ago | [Async-Click-Library](https://github.com/zuzkajelcicova/Async-Click-Library)/762 | None |
| 6 | 28 | 3 | 5 years ago | [vhdl-exercise](https://github.com/laurivosandi/vhdl-exercise)/763 | A little exercise for VHDL newbies |
| 6 | 2 | 0 | 4 years ago | [ECE368-Lab](https://github.com/Reiuiji/ECE368-Lab)/764 | ECE368 | Lab |
| 6 | 2 | 0 | 4 years ago | [SHA-256-HDL](https://github.com/lostpfg/SHA-256-HDL)/765 | An implementation of original SHA-256 hash function in (RTL) VHDL |
| 6 | 0 | 0 | 4 years ago | [ov7670_zybo](https://github.com/kkumt93/ov7670_zybo)/766 | None |
| 6 | 3 | 1 | 1 year, 10 months ago | [mining-shell](https://github.com/allmine-pub/mining-shell)/767 | Development shell repo for creation of fpga bitstreams |
| 6 | 1 | 0 | 4 years ago | [Rotary-encoder-VHDL-design](https://github.com/Yourigh/Rotary-encoder-VHDL-design)/768 | VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface. |
| 6 | 1 | 6 | 2 years ago | [OS2018spring-projects-g05](https://github.com/oscourse-tsinghua/OS2018spring-projects-g05)/769 | Dual-core MIPS CPU SoC |
| 6 | 0 | 0 | a month ago | [demomachine](https://github.com/zerkman/demomachine)/770 | Simple architecture to make demos on a FPGA |
| 6 | 1 | 0 | 11 years ago | [sdram_controller](https://github.com/freecores/sdram_controller)/771 | Scratch DDR SDRAM Controller |
| 6 | 5 | 0 | 5 years ago | [VHDL-Emporium](https://github.com/Reiuiji/VHDL-Emporium)/772 | Collection of Various created VHDL code |
| 6 | 7 | 2 | 5 years ago | [bluedbm_connectald](https://github.com/sangwoojun/bluedbm_connectald)/773 | BlueDBM |
| 6 | 3 | 0 | 3 years ago | [axi_stream_master](https://github.com/chclau/axi_stream_master)/774 | Source files for AXI Stream tutorial |
| 6 | 8 | 0 | 2 years ago | [Zybo-Z7-20-DMA](https://github.com/Digilent/Zybo-Z7-20-DMA)/775 | None |
| 6 | 0 | 0 | Unknown | [4Bit-Calculator](https://github.com/aryclenio/4Bit-Calculator)/776 | A bit calculator, implemented in VDHL that provides 4 bits sum, subtraction, inversion, major and minor verification. The result is shown in a 7 segment display on a FPGA board. This code was tested in Altera Quartus II. |
| 6 | 0 | 0 | Unknown | [Computer-Organization-and-Architecture-Course-Design](https://github.com/Jyxseu/Computer-Organization-and-Architecture-Course-Design)/777 | 这是东南大学信息学院本科三年级开设的计算机组织与结构课程的后续配套实验课程，包含POC设计和简单CPU设计。以下是我与小组完成的POC与CPU的设计，采用vivado2018.2的设计环境。 |
| 6 | 1 | 0 | Unknown | [pld](https://github.com/xtarke/pld)/778 | VHDL examples. IFSC lecture notes.  |
| 6 | 4 | 0 | Unknown | [PYNQ-Z2project](https://github.com/Mculover666/PYNQ-Z2project)/779 | PYNQ-Z2工程 |
| 6 | 6 | 0 | Unknown | [MIPS-CPU-System](https://github.com/xxr3376/MIPS-CPU-System)/780 | my mips cpu design in vhdl. support vga and PS/2 keyboard |
| 6 | 1 | 0 | Unknown | [usb11_phy_translation](https://github.com/freecores/usb11_phy_translation)/781 | USB 1.1  PHY  (VHDL) |
| 6 | 2 | 0 | Unknown | [MoxieLite](https://github.com/toptensoftware/MoxieLite)/782 | Lightweight VHDL implementation of a Moxie Processor |
| 6 | 3 | 0 | 7 years ago | [Plong](https://github.com/armandas/Plong)/783 | Simple pong implementation in vhdl |
| 6 | 6 | 0 | Unknown | [Rhino-Processing-Blocks](https://github.com/lekhobola/Rhino-Processing-Blocks)/784 | A library of IP cores needed for FPGA-based SDR development using RHINO board with SPARTAN-6 xc6slx150t device. |
| 6 | 1 | 0 | 3 years ago | [blake2](https://github.com/christian-krieg/blake2)/785 | VHDL implementation of BLAKE2 cryptographic hash and message authentication code (MAC) |
| 6 | 4 | 0 | 11 months ago | [vercolib_pcie](https://github.com/TI-Bonn/vercolib_pcie)/786 | VHDL PCIe Transceiver |
| 6 | 7 | 0 | Unknown | [WallTree](https://github.com/gagan405/WallTree)/787 | A VHDL code generator for wallace tree multiplier |
| 6 | 1 | 0 | Unknown | [UART](https://github.com/AntonZero/UART)/788 | UEART Project for DE1 Board |
| 6 | 0 | 0 | 6 years ago | [Cache-CPU](https://github.com/JamisHoo/Cache-CPU)/789 | MIPS32 instruction subset based processor |
| 6 | 0 | 0 | 7 years ago | [ws2812](https://github.com/freecores/ws2812)/790 | WS2812 RGB LED string driver |
| 6 | 2 | 0 | 6 years ago | [LED-Matrix-with-DE0-Nano-SoC-Board](https://github.com/AntonZero/LED-Matrix-with-DE0-Nano-SoC-Board)/791 | tutorial |
| 6 | 1 | 0 | Unknown | [MIPS16_CPU](https://github.com/Jackey-Huo/MIPS16_CPU)/792 | cpu project for  principles of computer organization |
| 6 | 0 | 0 | Unknown | [computer_aid_design_assignments_CAD](https://github.com/mehran75/computer_aid_design_assignments_CAD)/793 | None |
| 6 | 1 | 0 | Unknown | [snes_cic_fpga](https://github.com/rgalland/snes_cic_fpga)/794 | snes cic implementation with FPGA FireAnt board |
| 6 | 3 | 0 | Unknown | [SABER_HW](https://github.com/sujoyetc/SABER_HW)/795 | Hardware implementation of Saber |
| 6 | 2 | 0 | Unknown | [riscv-fpu](https://github.com/taneroksuz/riscv-fpu)/796 |  IEEE 754 standard floating point unit fpu single double precision verilog vhdl riscv |
| 6 | 0 | 0 | Unknown | [Malinki](https://github.com/32bitmicro/Malinki)/797 | Malinki - Hardware Cluster with Switch Fabric for Raspberry Pi |
| 6 | 2 | 1 | 6 years ago | [mz80b_de0](https://github.com/NibblesLab/mz80b_de0)/798 | MZ-80B/MZ-2000 series implementation for Altera DE0 board |
| 6 | 0 | 0 | 11 years ago | [backplane](https://github.com/somaproject/backplane)/799 | Soma Backplane Hardware |
| 6 | 1 | 0 | Unknown | [THCOMIPS16e](https://github.com/twd2/THCOMIPS16e)/800 | Yet Another Implementation of THCO MIPS16e |
| 6 | 2 | 1 | 2 years ago | [Bonfire](https://github.com/Project-Bonfire/Bonfire)/801 | A implementation of a NoC router with credit based flow control |
| 6 | 5 | 0 | 2 years ago | [Silicon_Peasant](https://github.com/NingHeChuan/Silicon_Peasant)/802 | None |
| 6 | 4 | 0 | 1 year, 5 months ago | [LPC2LCD](https://github.com/Kekule-OXC/LPC2LCD)/803 | LCD adapter for the LPC bus of the OG xbox |
| 6 | 1 | 0 | 10 years ago | [simplifiedmipscpu](https://github.com/davidscolgan/simplifiedmipscpu)/804 | Complete working simulation of both a single-cycle and pipelined CPU.  Implements a subset of the MIPS instruction set. |
| 6 | 3 | 0 | 11 months ago | [MSXPi2](https://github.com/costarc/MSXPi2)/805 | An attempt to improve the MSXPi |
| 6 | 12 | 9 | 20 days ago | [Arcade-Scramble_MiSTer](https://github.com/MiSTer-devel/Arcade-Scramble_MiSTer)/806 | Arcade: Scramble for MiSTer |
| 6 | 1 | 0 | 1 year, 7 months ago | [vhdl-axis-uart](https://github.com/fcayci/vhdl-axis-uart)/807 | UART to AXI Stream interface written in VHDL |
| 6 | 2 | 0 | 5 years ago | [hdmi2usb_designs](https://github.com/hamsternz/hdmi2usb_designs)/808 | Various HDL designs for the Numato Labs/Timvideos HDMI2USB FPGA board |
| 6 | 6 | 0 | 1 year, 5 months ago | [SDAccel](https://github.com/zakinder/SDAccel)/809 | SDAccel: Architecture to enable CPU/GPU developers to easily migrate their applications to FPGAs while maintaining and reusing their OpenCL, C, and C++ code in a familiar workflow.  |
| 6 | 1 | 0 | 1 year, 2 months ago | [canopen-vhdl](https://github.com/bggardner/canopen-vhdl)/810 | A lightweight CANopen controller in VHDL |
| 6 | 1 | 0 | 1 year, 10 months ago | [Basys3-Pulse-Generator](https://github.com/soundjuice/Basys3-Pulse-Generator)/811 | Pulse generator on Basys 3 FPGA board |
| 6 | 2 | 0 | 5 years ago | [simon_vhdl](https://github.com/samvartaka/simon_vhdl)/812 | VHDL implementations of various architectural designs of the SIMON 64/128 block cipher |
| 6 | 4 | 0 | 10 months ago | [LibHSA](https://github.com/HSA-on-FPGA/LibHSA)/813 | HSA compatible dispatch infrastructure for FPGAs |
| 6 | 2 | 0 | 19 days ago | [theremin](https://github.com/fpga-theremin/theremin)/814 | Open source digital FPGA based theremin project |
| 6 | 1 | 1 | 7 years ago | [Guimauve2ooo](https://github.com/Torlus/Guimauve2ooo)/815 | VGA output for Apple //c computers |
| 6 | 1 | 0 | 6 years ago | [FreeRTOS-Zybo](https://github.com/circuitsenses/FreeRTOS-Zybo)/816 | FreeRTOS implemented on the Digilent ZYBO Zynq 7000 |
| 6 | 4 | 0 | 6 years ago | [minispartan6](https://github.com/ultraembedded/minispartan6)/817 | Projects for the Scarab Minispartan6+ FPGA board |
| 6 | 1 | 2 | 3 years ago | [mz80c_de0](https://github.com/NibblesLab/mz80c_de0)/818 | MZ-80 series implementation for Altera DE0 board |
| 6 | 1 | 0 | 9 years ago | [casper_myhdl](https://github.com/amitbansod/casper_myhdl)/819 | Development of DSP blocks found in CASPER library using MyHDL package and Python |
| 6 | 3 | 2 | 4 years ago | [ZedBoardAudio](https://github.com/Laxer3a/ZedBoardAudio)/820 | AXI Slave Audio Component. |
| 6 | 3 | 5 | 2 years ago | [CuckooHashingHLS](https://github.com/AakashKT/CuckooHashingHLS)/821 | HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/ |
| 6 | 4 | 1 | 2 years ago | [FPGA_1942](https://github.com/d18c7db/FPGA_1942)/822 | FPGA 1942 arcade game |
| 6 | 1 | 0 | 11 months ago | [vhdl-maze-solver](https://github.com/mohamin1995/vhdl-maze-solver)/823 | Cellular Automata Maze Solver Hardware Implementation |
| 6 | 0 | 0 | 1 year, 9 months ago | [CA-AUT](https://github.com/University-Archive/CA-AUT)/824 | Computer Architecture Course @ AUT |
| 6 | 8 | 2 | 19 days ago | [Arcade-Defender_MiSTer](https://github.com/MiSTer-devel/Arcade-Defender_MiSTer)/825 | Arcade: Defender for MiSTer |
| 6 | 1 | 1 | 1 year, 6 months ago | [sdram](https://github.com/dnotq/sdram)/826 | Simple fixed-cycle SDRAM Controller |
| 6 | 3 | 0 | 1 year, 5 months ago | [Gr0estl-Miner](https://github.com/atomminer/Gr0estl-Miner)/827 | Gr0estl mining algo FPGA implementation by AtomMiner |
| 6 | 0 | 0 | 2 years ago | [vhdllib](https://github.com/sinkswim/vhdllib)/828 | My own VHDL components library.  Anything from a flip flop to an ALU. |
| 6 | 3 | 0 | 10 years ago | [VHDL-Snake-Game](https://github.com/freaktm/VHDL-Snake-Game)/829 | A simple snake game in vhdl - designed for the Spartan-3 Starter Board (work in progress) |
| 6 | 4 | 2 | 4 years ago | [C64_MIST](https://github.com/sorgelig/C64_MIST)/830 | None |
| 6 | 1 | 0 | 3 years ago | [MDE2](https://github.com/livingcomputermuseum/MDE2)/831 | MASSBUS Disk Emulator Hardware |
| 6 | 0 | 0 | 1 year, 22 days ago | [VHDL-LAB](https://github.com/AdeboyeOyeniyi/VHDL-LAB)/832 | Some basic electronic structures implemented in VHDL |
| 6 | 9 | 2 | 1 year, 2 months ago | [SPI-FPGA-VHDL](https://github.com/Nematollahi/SPI-FPGA-VHDL)/833 | SPI Master and Slave components to be used in all of FPGAs, written in VHDL. |
| 6 | 3 | 1 | 7 months ago | [CoreAmstrad](https://github.com/renaudhelias/CoreAmstrad)/834 | CoreAmstrad source code, a physical clone of Amstrad from JavaCPC Markus's emulator, currently running on a final FPGA end-user platform : MiST-board. |
| 6 | 4 | 0 | 8 years ago | [busblaster_v4](https://github.com/dergraaf/busblaster_v4)/835 | CPLD designs for the BusBlaster v4 from Dangerous Prototypes |
| 6 | 3 | 2 | 1 year, 11 months ago | [fast-p2a](https://github.com/Mythir/fast-p2a)/836 | None |
| 6 | 3 | 0 | 4 months ago | [apple2fpga](https://github.com/emard/apple2fpga)/837 | port of Stephen A. Edwards apple2fpga to ULX3S |
| 6 | 0 | 0 | 5 years ago | [libcapi](https://github.com/sbates130272/libcapi)/838 | A library of things IBM CAPI related including common C and RTL code for AFUs. |
| 6 | 0 | 0 | 1 year, 1 month ago | [hw-sike](https://github.com/pmassolino/hw-sike)/839 | FPGA implementation of the Supersingular Isogeny Key Encapsulation |
| 6 | 3 | 0 | 3 years ago | [Game-of-Balance-on-Nexys4DDR](https://github.com/g0kul/Game-of-Balance-on-Nexys4DDR)/840 | Game of Balance is an accelerometer based maze navigation game, with added features of score and life, that is built on Nexys 4 DDR development board. |
| 6 | 0 | 0 | 21 days ago | [Computer-Arch](https://github.com/3omar-mostafa/Computer-Arch)/841 | None |
| 6 | 1 | 0 | 7 years ago | [VHDL-School](https://github.com/armandas/VHDL-School)/842 | My VHDL sources |
| 6 | 1 | 0 | 5 years ago | [ipxact](https://github.com/tudortimi/ipxact)/843 | IP-XACT XML binding library |
| 6 | 1 | 0 | 4 years ago | [Template-Matching-FPGA](https://github.com/ralbertazzi/Template-Matching-FPGA)/844 | None |
| 6 | 1 | 0 | 2 years ago | [DDS](https://github.com/spr02/DDS)/845 | A DDS core written in VHDL. |
| 6 | 6 | 0 | 5 months ago | [mrf-openevr](https://github.com/jpietari/mrf-openevr)/846 | Open source Event Receiver implementation |
| 6 | 1 | 0 | 10 months ago | [Binocular-Stereo-Vision-PYNQ](https://github.com/marshmallow911/Binocular-Stereo-Vision-PYNQ)/847 | None |
| 6 | 1 | 0 | 5 months ago | [spu-mark-ii](https://github.com/MasterQ32/spu-mark-ii)/848 | CPU and home computer project |
| 6 | 0 | 0 | 4 years ago | [tinycomputer](https://github.com/zpekic/tinycomputer)/849 | Tiny 4-bit CPU using AMD2901 bit slice (https://github.com/Amrnasr/AM2901) and program memory initialized from a file |
| 6 | 2 | 3 | a month ago | [stdcores](https://github.com/rftafas/stdcores)/850 | Standard and Curated cores, tested and working. |
| 6 | 4 | 2 | 3 years ago | [colecofpga](https://github.com/fbelavenuto/colecofpga)/851 | Colecovision FGPA port from old PACE project. |
| 6 | 0 | 1 | 4 days ago | [cordicHDL](https://github.com/qarlosalberto/cordicHDL)/852 | None |
| 6 | 1 | 0 | 4 years ago | [ftdi-async-fifo](https://github.com/rohitk-singh/ftdi-async-fifo)/853 | FTDI FT2232H Asynchronous FIFO communication with FPGA over USB |
| 6 | 3 | 0 | 3 years ago | [Scalable-Bilateral-Filtering-on-FPGA](https://github.com/swapnildabhade/Scalable-Bilateral-Filtering-on-FPGA)/854 | VHDL implimentation of A Reconfigurable and Scalable FPGA Architecture for Bilateral Filtering. |
| 6 | 7 | 0 | 4 years ago | [multicore-architecture](https://github.com/kevinsala/multicore-architecture)/855 | Simple multicore processor implemented in VHDL |
| 6 | 1 | 0 | 4 years ago | [1802-pico-basic](https://github.com/Steve-Teal/1802-pico-basic)/856 | VHDL 1802 Core with TinyBASIC for the Lattice MachXO2 Pico board |
| 6 | 14 | 1 | 1 year, 2 months ago | [KC705-AD9371](https://github.com/coralhu123/KC705-AD9371)/857 | The implementation of AD9371 on KC705 |
| 6 | 3 | 1 | 2 years ago | [Ethash](https://github.com/violetsolo/Ethash)/858 | ethash project in vhdl |
| 6 | 0 | 0 | 6 years ago | [vhdl-simple-processor](https://github.com/plorefice/vhdl-simple-processor)/859 | Implementation of a simple processor using VHDL for logic synthesis in FPGA |
| 6 | 6 | 1 | 14 days ago | [Arcade-MCR3Mono_MiSTer](https://github.com/MiSTer-devel/Arcade-MCR3Mono_MiSTer)/860 | Arcade: MCR3 Monoboard games |
| 6 | 0 | 0 | 5 years ago | [SysAlloc](https://github.com/Hilx/SysAlloc)/861 | SysAlloc, a FPGA implemented hardware memory allocator for heterogeneous systems. |
| 6 | 16 | 2 | 3 years ago | [NexysVideo](https://github.com/Digilent/NexysVideo)/862 | None |
| 6 | 0 | 0 | 8 years ago | [vhdl-svf](https://github.com/hansiglaser/vhdl-svf)/863 | SVF (Serial Vector Format) interpreter to control a JTAG TAP |
| 6 | 12 | 1 | 1 year, 5 months ago | [sysdesign](https://github.com/luojike/sysdesign)/864 | Code base for computer system design |
| 6 | 3 | 0 | 2 months ago | [UVVM_Light](https://github.com/UVVM/UVVM_Light)/865 | This repository is a subset of UVVM with Utility library and BFMs, and is intended as a UVVM starting platform for thos who only need the Utility Library and BFMs.    Community forum: https://forum.uvvm.org/    UVVM.org: https://uvvm.org/ |
| 6 | 1 | 0 | 2 years ago | [fp23_logic](https://github.com/capitanov/fp23_logic)/866 | Floating point FP23 core on VHDL. For Xilinx FPGAs. Include base converters and some math functions. |
| 6 | 1 | 0 | 3 years ago | [PWM-in-VHDL](https://github.com/kiranjose/PWM-in-VHDL)/867 | PWM in VHDL |
| 6 | 4 | 0 | 7 years ago | [THCO-MIPS-CPU](https://github.com/Piasy/THCO-MIPS-CPU)/868 | Computer Organization course project:THCO-MIPS CPU |
| 6 | 4 | 0 | 4 years ago | [zybo-examples](https://github.com/coldnew/zybo-examples)/869 | A series of examples on zybo board for my blog tutorials. |
| 6 | 2 | 0 | 4 years ago | [VGA_example](https://github.com/andrewandrepowell/VGA_example)/870 | This repository contains a Vivado 2015.3 Project that runs an example application for the VGA_1.0 IP core. Althrough the core had originally been created for the Avnet Zedboard, this example was created for the Digilent Zybo. |
| 6 | 2 | 0 | 2 years ago | [My_Design](https://github.com/gehujun/My_Design)/871 | 带有tlb的五级流水CPU |
| 6 | 1 | 0 | 3 years ago | [iir-audio-filter-fpga](https://github.com/gabrielebaris/iir-audio-filter-fpga)/872 | Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA |
| 6 | 0 | 0 | 3 years ago | [CAD_2018](https://github.com/Nikronic/CAD_2018)/873 | Some of small codes and implementation of modules in Computer Aided Design in VHDL by ActiveHDL |
| 6 | 0 | 0 | 3 years ago | [vhdl-snake](https://github.com/xtrinch/vhdl-snake)/874 | Snake game with PS2 and VGA drivers written in VHDL for the Nexys 2 development board |
| 6 | 6 | 0 | 6 years ago | [Papilio-Schematic-Library](https://github.com/GadgetFactory/Papilio-Schematic-Library)/875 | A library of Soft Processors and peripherals that can be used with Webpack schematic editor to build a custom SOC for the Papilio |
| 6 | 2 | 0 | 3 years ago | [FPGA_Harris_Corner](https://github.com/chaotaklon/FPGA_Harris_Corner)/876 | An efficient FPGA implementation of the Harris Corner feature detector |
| 6 | 1 | 0 | 5 months ago | [rv16poc](https://github.com/AntonMause/rv16poc)/877 | 16 bit RISC-V proof of concept |
| 6 | 6 | 0 | 1 year, 6 months ago | [SHA-256](https://github.com/dsaves/SHA-256)/878 | An SHA-256 module implementation in VHDL.  Based on NIST FIPS 180-4. |
| 6 | 1 | 0 | 5 years ago | [wr-switch-hdl](https://github.com/jlgutierrez/wr-switch-hdl)/879 | White Rabbit HSR gateware development. Forked from OHWR |
| 6 | 0 | 0 | 23 days ago | [EECS31_L](https://github.com/ffyuanda/EECS31_L)/880 | EECS 31 L course code and homework |
| 6 | 5 | 0 | 3 years ago | [Kalman-Filter-verilog](https://github.com/abhishekgb/Kalman-Filter-verilog)/881 | Hey guys this the project where i have implemented the Kalman filter for MPPT for solar PV module  |
| 6 | 4 | 1 | 3 years ago | [ultrasonic-levitation-with-Xilinx-Zynq](https://github.com/eejlny/ultrasonic-levitation-with-Xilinx-Zynq)/882 | This github contains the Vivado project, PCB schematic and control software for levitation framework at Bristol University |
| 6 | 0 | 0 | 7 years ago | [PapilioPro-AnimatedShapes](https://github.com/kosak/PapilioPro-AnimatedShapes)/883 | Driving the VGA protocol, displaying some animated shapes on an FPGA |
| 6 | 1 | 0 | 11 years ago | [AX8](https://github.com/G33KatWork/AX8)/884 | The AVR softcore from opencores.org with a makefile and some useable demo code |
| 6 | 0 | 0 | 5 years ago | [2D-Image-Filtering-on-FPGA](https://github.com/fujy/2D-Image-Filtering-on-FPGA)/885 | None |
| 6 | 0 | 4 | 1 year, 9 months ago | [fpga_lib](https://github.com/INTI-CMNB-FPGA/fpga_lib)/886 | Library of utilities such as cores, procedures and functions, commonly shared between FPGA projects. |
| 6 | 1 | 0 | 2 years ago | [vhdl_tarning](https://github.com/mehdisavari/vhdl_tarning)/887 | VHDL Source Code |
| 6 | 4 | 0 | 2 months ago | [psi_fix](https://github.com/paulscherrerinstitute/psi_fix)/888 | Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation) |
| 6 | 0 | 0 | 11 months ago | [multi-TB-progetto-Reti-PoliMi](https://github.com/Mark-Zampedroni/multi-TB-progetto-Reti-PoliMi)/889 | Test bench di test automatico per la prova finale del corso di Reti Logiche al Politecnico di Milano, anno 2019/2020. |
| 6 | 0 | 0 | 5 months ago | [icestick-remote](https://github.com/marph91/icestick-remote)/890 | Remote control in VHDL, which fits on a Lattice icestick. |
| 6 | 0 | 0 | 8 years ago | [kanto](https://github.com/kanto-player/kanto)/891 | Kanto Audio Player |
| 6 | 2 | 0 | 3 years ago | [pqhw](https://github.com/mupq/pqhw)/892 | None |
| 6 | 4 | 0 | 5 years ago | [hdmi-audio](https://github.com/fintros/hdmi-audio)/893 | HDMI Audio/Video signal generation for HW emulators of retro comuters |
| 6 | 1 | 0 | 4 years ago | [Mandelbrot-Explorer](https://github.com/elkayem/Mandelbrot-Explorer)/894 | An FPGA-based Mandelbrot Set explorer using the Papilio Duo board from Gadget Factory. |
| 6 | 1 | 3 | 2 years ago | [Music5000](https://github.com/hoglet67/Music5000)/895 | FPGA implementation of the 1980's "Music 5000" wavetable synthesiser |
| 6 | 5 | 0 | 5 years ago | [xilinx-zynq-zc702-linuxapplication](https://github.com/JunghoYoo/xilinx-zynq-zc702-linuxapplication)/896 | Linux application and Device driver porting on Xilinx Zynq ZC702 board |
| 6 | 1 | 0 | 2 years ago | [kalman_mppt](https://github.com/diecaptain/kalman_mppt)/897 | mppt algorithm using kalman filter in VHDL |
| 6 | 1 | 0 | 3 years ago | [ip_cores](https://github.com/Bucknalla/ip_cores)/898 | Verilog IP Cores & Tests |
| 6 | 2 | 0 | 2 years ago | [ustogo-lsi](https://github.com/ibrahimaya/ustogo-lsi)/899 | The repository includes two main directories; (i) "ustogo": for our complete ultrasound processing pipeline (Matlab-based), and (ii) "fpgabeamformer": for the single-FPGA 3D/2D ultrasound digital imager;  hardware side (Vivado designs) and software side (Xilinx SDK applications + visual studio GUI). |
| 6 | 0 | 0 | 1 year, 11 days ago | [vhdl-experiments](https://github.com/PKazm/vhdl-experiments)/900 | All the mumbo jumbo code that is me learning VHDL. Primarily targeted for Microsemi Smartfusion2 |
| 6 | 0 | 0 | 1 year, 11 days ago | [vhdl-experiments](https://github.com/PKazm/vhdl-experiments)/901 | All the mumbo jumbo code that is me learning VHDL. Primarily targeted for Microsemi Smartfusion2 |
| 6 | 4 | 3 | 2 months ago | [Oric_Mist_48K](https://github.com/rampa069/Oric_Mist_48K)/902 | Oric Atmos Mist core |
| 6 | 0 | 0 | 5 months ago | [AES-128-with-an-Instruction-Set](https://github.com/wap12358/AES-128-with-an-Instruction-Set)/903 | None |
| 6 | 5 | 1 | 4 months ago | [SAM-Coupe_MiSTer](https://github.com/MiSTer-devel/SAM-Coupe_MiSTer)/904 | None |
| 5 | 0 | 1 | 3 years ago | [VDHL-SD-Library](https://github.com/simon-77/VDHL-SD-Library)/905 | A VHDL-Library for reading a SD-Card with a FPGA in a small test project |
| 5 | 23 | 0 | 1 year, 5 months ago | [cpudesign](https://github.com/luojike/cpudesign)/906 | CPU设计的代码站 |
| 5 | 0 | 1 | 2 months ago | [t80](https://github.com/EisernSchild/t80)/907 | Configurable cpu core that supports Z80, 8080 and gameboy instruction sets. |
| 5 | 0 | 0 | 1 year, 9 months ago | [Grain-128AEAD-VHDL](https://github.com/Noxet/Grain-128AEAD-VHDL)/908 | The VHDL reference implementation along with optimized versions of the stream cipher Grain-128AEAD |
| 5 | 6 | 1 | 2 months ago | [Oric_MiSTer](https://github.com/MiSTer-devel/Oric_MiSTer)/909 | Oric-1 and Oric Atmos for MiSTer |
| 5 | 6 | 5 | 19 days ago | [Arcade-MarioBros_MiSTer](https://github.com/MiSTer-devel/Arcade-MarioBros_MiSTer)/910 | Mario Bros arcade core for MiSTer |
| 5 | 1 | 0 | 11 months ago | [FPGA_BASED_RADAR_ACQUISITION_AND_PREPROCESSING_UNIT](https://github.com/ramonblancocaamano/FPGA_BASED_RADAR_ACQUISITION_AND_PREPROCESSING_UNIT)/911 | FPGA BASED RADAR ACQUISITION AND PREPROCESSING UNIT |
| 5 | 9 | 0 | 1 year, 6 months ago | [fpga_cyclone4](https://github.com/alientek-fpga/fpga_cyclone4)/912 | 正点原子开拓者&新起点FPGA开发板例程 |
| 5 | 2 | 0 | 6 years ago | [fpu](https://github.com/is-cpuex2014-5/fpu)/913 | FPU written in VHDL |
| 5 | 0 | 0 | 3 years ago | [Arty_s7_example](https://github.com/ATaylorCEngFIET/Arty_s7_example)/914 | Arty S7 Example with Pmods and MTDS |
| 5 | 2 | 0 | 1 year, 6 months ago | [rmii-firewall-fpga](https://github.com/jakubcabal/rmii-firewall-fpga)/915 | RMII Firewall FPGA |
| 5 | 0 | 0 | 2 months ago | [SGen](https://github.com/fserre/SGen)/916 | SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset is divided into several chunks that are processed during several cycles, thus allowing a reduced use of resources. The size of these chunks is referred as the streaming width. It outputs a Verilog file that can be used for FPGAs. |
| 5 | 1 | 0 | 6 days ago | [Arch-Pipelined-Processor](https://github.com/nadaabdelmaboud/Arch-Pipelined-Processor)/917 | 32-bit 5-stage pipelined processor has a RISC-like instruction set and Harvard Archeticure  |
| 5 | 0 | 0 | 4 years ago | [VHDL](https://github.com/saw235/VHDL)/918 | Everything related to VHDL design. Image Filters, PS/2 Keyboard Controller, VGA Controller... |
| 5 | 3 | 0 | 2 years ago | [fpga-colossus](https://github.com/bennorth/fpga-colossus)/919 | Implementation of part of the World-War-II code-breaking machine 'Colossus' on an FPGA |
| 5 | 0 | 0 | 2 years ago | [InfraRed-LED-Controller](https://github.com/rj-jesus/InfraRed-LED-Controller)/920 | InfraRed decoder written in VHDL + Pulse width modulation on Green LEDs |
| 5 | 3 | 0 | 1 year, 6 months ago | [SBA-Library](https://github.com/mriscoc/SBA-Library)/921 | SBA IP Cores  http://sba.accesus.com |
| 5 | 1 | 0 | 4 years ago | [RSA_Security_Token](https://github.com/GustaMagik/RSA_Security_Token)/922 | A Security token system for (two-factor) authentication to Linux / Unix using an FPGA and a PAM-module. Either A: 72-bit or B: 512-bit RSA. Version A is air-gapped. Version B uses USB UART. BSD-3 licensed. |
| 5 | 1 | 0 | 3 years ago | [CADSD-homeworks](https://github.com/aminrashidbeigi/CADSD-homeworks)/923 | Solutions of Computer Aided Digital System Design (FPGA) Course Homeworks |
| 5 | 3 | 0 | 3 years ago | [PongGameVHDL](https://github.com/efeacer/PongGameVHDL)/924 | Here is the code of my digital design term project, which is an implementation of the classic arcade game Pong in VGA using basys3 board. The game is implemented using VHDL hardware description language. You can find a video description from the link: https://www.youtube.com/watch?v=LqOlgilpCYc&t=36s |
| 5 | 1 | 0 | 3 years ago | [FPGA-Acceleration-of-Canny-Edge-Detection-Algorithm](https://github.com/deepaktabraham/FPGA-Acceleration-of-Canny-Edge-Detection-Algorithm)/925 | HW and SW based implementation of Canny Edge Detection Algorithm. |
| 5 | 2 | 0 | 2 years ago | [mips-computer](https://github.com/joker-xii/mips-computer)/926 | A simple computer based on the design in "Digital Design and Computer Architecture - 2nd Edition" |
| 5 | 1 | 0 | 1 year, 11 months ago | [VCU1525_HLS_acceleration_framework](https://github.com/SanjayRai/VCU1525_HLS_acceleration_framework)/927 | VCU1525_HLS_acceleration_framework  |
| 5 | 0 | 0 | 2 years ago | [USTC_CS_digital_labs](https://github.com/yuxguo/USTC_CS_digital_labs)/928 | Verilog code of Digital circuit lab in 2018 Fall |
| 5 | 0 | 0 | 2 years ago | [Connect4VHDL](https://github.com/pcruiher08/Connect4VHDL)/929 | Spartan3 implementation of the popular game Connect 4 written in VHDL |
| 5 | 3 | 0 | 7 years ago | [crush](https://github.com/jpendlum/crush)/930 | Cognitive Radio Universal Software Hardware |
| 5 | 0 | 0 | 23 days ago | [unicamp](https://github.com/seijihirao/unicamp)/931 | My unicamp experience |
| 5 | 1 | 0 | a month ago | [riscv-debug-dtm](https://github.com/stnolting/riscv-debug-dtm)/932 | VHDL RISC-V JTAG debug transport module (DTM) - compatible to the RISC-V debug specification |
| 5 | 0 | 0 | 10 years ago | [fpgaSynths](https://github.com/LOGre/fpgaSynths)/933 | Making oldskool music with FPGA VHDL soundchips core and the ZPUino SoC |
| 5 | 0 | 0 | 15 years ago | [t80](https://github.com/lipro/t80)/934 | The T80 (VHDL) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,t80) |
| 5 | 3 | 0 | 5 years ago | [firmware-ethernet](https://github.com/PsiStarPsi/firmware-ethernet)/935 | Firmware modules and packages for implementing Ethernet control and data acquisition interfaces on Xilinx FPGAs. |
| 5 | 2 | 2 | 9 years ago | [h264](https://github.com/hdhzero/h264)/936 | motion estimation in VHDL |
| 5 | 5 | 0 | 6 years ago | [1553-Firmware](https://github.com/phillipjohnston/1553-Firmware)/937 | Contains VHDL implementing an 8085, Holt HI-6130 1553 IC, and Memory.  Also includes firmware used to demo the system. |
| 5 | 2 | 0 | 4 years ago | [afu-walkthrough](https://github.com/ibm-capi/afu-walkthrough)/938 |  Simple overview of the PSL-AFU Interface for CAPI |
| 5 | 0 | 0 | 3 years ago | [SAYEH](https://github.com/1997alireza/SAYEH)/939 | SAYEH (Simple Architecture, Yet Enough Hardware) Basic Computer |
| 5 | 3 | 1 | 4 years ago | [Arty-GPIO](https://github.com/Digilent/Arty-GPIO)/940 | None |
| 5 | 0 | 0 | 3 years ago | [vhdl-aes-gcm](https://github.com/parrisha/vhdl-aes-gcm)/941 | VHDL implementation of GCM mode of AES |
| 5 | 5 | 0 | 3 years ago | [AX7103](https://github.com/alinxalinx/AX7103)/942 | None |
| 5 | 0 | 0 | 2 years ago | [Arty-Z7-20-OOB](https://github.com/Digilent/Arty-Z7-20-OOB)/943 | None |
| 5 | 1 | 0 | 1 year, 11 days ago | [erbium](https://github.com/fpgasystems/erbium)/944 | Business Rule Engine Hardware Accelerator |
| 5 | 1 | 0 | 1 year, 3 months ago | [super-reu](https://github.com/zeldin/super-reu)/945 | An advanced FPGA-based ram expansion module for C64/C128 |
| 5 | 1 | 0 | 1 year, 9 months ago | [riscv-fpga](https://github.com/shenyaming/riscv-fpga)/946 | Share JTAG chain within RISCV core and Xilinx FPGA. |
| 5 | 0 | 0 | 3 months ago | [AdderNet-FPGA](https://github.com/mqhuangGit/AdderNet-FPGA)/947 | None |
| 5 | 1 | 0 | a month ago | [IPDBG](https://github.com/IPDBG/IPDBG)/948 | IPDBG |
| 5 | 1 | 0 | 4 years ago | [Microprocessor-Projects](https://github.com/martiansideofthemoon/Microprocessor-Projects)/949 | A set of two microprocessor projects as a part of EE 309 / 337 at IIT Bombay. |
| 5 | 1 | 0 | 2 months ago | [c64fpga](https://github.com/ovalcode/c64fpga)/950 | None |
| 5 | 7 | 0 | 5 years ago | [Zynq-Configuration-Controller](https://github.com/Architech-Silica/Zynq-Configuration-Controller)/951 | A configuration controller solution allowing a Zynq device to configure downstream FPGAs |
| 5 | 4 | 0 | 6 years ago | [CCD_Cam](https://github.com/AntonZero/CCD_Cam)/952 | Cam interface to FPGA using ADV7180 |
| 5 | 8 | 1 | 7 years ago | [zynq_echo_servers](https://github.com/mohamed/zynq_echo_servers)/953 | UDP and TCP echo servers using lwIP RAW API running on Xilinx Zynq Platform |
| 5 | 5 | 0 | 7 years ago | [fpga-sdr-platform](https://github.com/JacekGreniger/fpga-sdr-platform)/954 | FPGA SDR platform: AD9963 + XC6SLX9 + CY7C68013 |
| 5 | 1 | 0 | 6 years ago | [speccy-wxeda](https://github.com/andykarpov/speccy-wxeda)/955 | Порт конфигурации Reverse u16_speccy на плату ZrTech WXEDA |
| 5 | 2 | 0 | 3 years ago | [fpga-mmu](https://github.com/argos-research/fpga-mmu)/956 | internship |
| 5 | 1 | 0 | 4 years ago | [present-vhdl](https://github.com/huljar/present-vhdl)/957 | Implementation of the PRESENT lightweight block cipher in VHDL. |
| 5 | 1 | 0 | 1 year, 6 months ago | [ultrasonic-sensor](https://github.com/santifs/ultrasonic-sensor)/958 | Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs. |
| 5 | 1 | 0 | 3 years ago | [FPGA-Homework](https://github.com/9231058/FPGA-Homework)/959 | Dr.SahebZamani FPGA Homework |
| 5 | 0 | 0 | 3 years ago | [AXI4_Master](https://github.com/jackodirks/AXI4_Master)/960 | A VHDL implementation of an AXI4 Master |
| 5 | 4 | 0 | 3 years ago | [ConvFPGA](https://github.com/antonpaquin/ConvFPGA)/961 | None |
| 5 | 3 | 0 | 10 years ago | [async_8b10b_encoder_decoder](https://github.com/freecores/async_8b10b_encoder_decoder)/962 | Async 8b/10b enc/dec |
| 5 | 1 | 0 | 12 years ago | [fpu_double](https://github.com/freecores/fpu_double)/963 | FPU Double VHDL |
| 5 | 1 | 0 | 9 years ago | [Sump_Blaze_Core](https://github.com/GadgetFactory/Sump_Blaze_Core)/964 | VHDL Sump Logic Analyzer |
| 5 | 0 | 0 | 5 years ago | [ledsign](https://github.com/sgstair/ledsign)/965 | A software/hardware stack to display information on a group of LED panels |
| 5 | 2 | 0 | 7 years ago | [LevOS](https://github.com/levex/LevOS)/966 | A hobbyist operating system. |
| 5 | 2 | 0 | 5 months ago | [FPGA-MIPS-based-CPU-APP-Flappy-Bird](https://github.com/Ssssseason/FPGA-MIPS-based-CPU-APP-Flappy-Bird)/967 | Project for computer organization and design course, implementing a simple popular game flappy bird in FPGA. |
| 5 | 2 | 0 | 1 year, 1 month ago | [MIPS-Processor-VHDL](https://github.com/cm4233/MIPS-Processor-VHDL)/968 | Emulation of a 32-bit MIPS processor on Artix-7 FPGA using VHDL. The emulated MIPS processor is tested by executing RC5 encryption and decryption algorithms. |
| 5 | 4 | 1 | 3 years ago | [grlib](https://github.com/jeandet/grlib)/969 | None |
| 5 | 1 | 0 | 3 years ago | [arm_nyuzi](https://github.com/chuan573906361/arm_nyuzi)/970 | a multi-cpu with gpgpu project running on the xilinx zynq board(zc706) |
| 5 | 3 | 0 | 2 years ago | [donkey-kong-fpga](https://github.com/d18c7db/donkey-kong-fpga)/971 | FPGA implementation of arcade game Donkey Kong |
| 5 | 0 | 0 | 1 year, 6 months ago | [Computer-aided-Design](https://github.com/parsa-abbasi/Computer-aided-Design)/972 | The implementation of some modules and basic projects of CAD in VHDL |
| 5 | 0 | 0 | 2 years ago | [VHSIC-Hardware-Description-Language](https://github.com/aliyevorkhan/VHSIC-Hardware-Description-Language)/973 | None |
| 5 | 1 | 0 | 2 years ago | [Pmod-NIC100](https://github.com/carljohnsen/Pmod-NIC100)/974 | VHDL implementation of the SPI interface for Pmod NIC100 https://store.digilentinc.com/pmod-nic100-network-interface-controller/ |
| 5 | 0 | 0 | 2 years ago | [vhdl_practices](https://github.com/aliyevorkhan/vhdl_practices)/975 | None |
| 5 | 1 | 2 | 8 months ago | [yaaes](https://github.com/marph91/yaaes)/976 | Yet Another AES implementation in hardware. |
| 5 | 0 | 2 | 1 year, 7 months ago | [vhdl_phoenix](https://github.com/emard/vhdl_phoenix)/977 | Phoenix arcade for FPGA forked from DarFPGA |
| 5 | 2 | 0 | 5 years ago | [VhdI2CSlave](https://github.com/tirfil/VhdI2CSlave)/978 | I2C Slave Interface (Vhdl)  |
| 5 | 0 | 0 | 15 days ago | [VHDL](https://github.com/Komarovec/VHDL)/979 | VHDL learning repository |
| 5 | 2 | 0 | 11 years ago | [acqboard](https://github.com/somaproject/acqboard)/980 | Soma 8+2 Acquisition Module, hardware and software |
| 5 | 1 | 0 | 7 years ago | [cpu](https://github.com/xsoameix/cpu)/981 | a simple cpu written by vhdl. |
| 5 | 1 | 0 | 7 months ago | [fixed_extensions](https://github.com/nkkav/fixed_extensions)/982 | VHDL fixed-point arithmetic extensions package |
| 5 | 1 | 0 | 5 years ago | [sparcv8-monocycle](https://github.com/cgutierr3z/sparcv8-monocycle)/983 | Procesador monociclo arquitectura SPARC V8 modelado en VHDL. |
| 5 | 11 | 0 | 3 years ago | [ComputerOrganizationDesign](https://github.com/SWORDfpga/ComputerOrganizationDesign)/984 | 计算机组成课程资料 |
| 5 | 2 | 0 | 2 years ago | [AXI_DMA_FIFO](https://github.com/absolutezero2730/AXI_DMA_FIFO)/985 | Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA |
| 5 | 3 | 0 | 6 months ago | [UCAS-CS](https://github.com/Hambaobao/UCAS-CS)/986 | Undergraduate 2017-2021 |
| 5 | 1 | 0 | Unknown | [myCPU](https://github.com/wzcboy/myCPU)/987 | make a simple mips CPU |
| 5 | 1 | 0 | Unknown | [ece5760](https://github.com/jpwright/ece5760)/988 | labs for ECE 5760 |
| 5 | 2 | 0 | a month ago | [vunit_action](https://github.com/VUnit/vunit_action)/989 | VUnit GitHub action |
| 5 | 10 | 0 | 19 days ago | [Arcade-Phoenix_MiSTer](https://github.com/MiSTer-devel/Arcade-Phoenix_MiSTer)/990 | Arcade: Phoenix for MiSTer |
| 5 | 3 | 0 | 1 year, 7 months ago | [TransformCodingInference](https://github.com/CompressTeam/TransformCodingInference)/991 | None |
| 5 | 0 | 0 | 4 days ago | [DeMiSTify](https://github.com/robinsonb5/DeMiSTify)/992 | Code to support porting MiST cores to other boards. |
| 5 | 4 | 0 | Unknown | [AtomGodilVideo](https://github.com/hoglet67/AtomGodilVideo)/993 | New Video Adapter for Acorn Atom implemented in a GODIL FPGA |
| 5 | 0 | 0 | 6 years ago | [2048-DE1](https://github.com/dokson/2048-DE1)/994 | VHDL implementation of 2048 Game on Altera DE1 FPGA Board |
| 5 | 5 | 2 | 5 years ago | [logi-mt9v034](https://github.com/jpiat/logi-mt9v034)/995 | None |
| 5 | 4 | 0 | 9 years ago | [umn_simaudio](https://github.com/mjbrown/umn_simaudio)/996 | Univ. of MN Simultaneous Audio Recording Interface Software and Firmware |
| 5 | 1 | 0 | 10 years ago | [frogvivor](https://github.com/funchal/frogvivor)/997 | A frogger-clone, in hardware :) for the Papilio One FPGA |
| 5 | 0 | 0 | Unknown | [fpgapong](https://github.com/alecain/fpgapong)/998 | Fpga implementation of pong |
| 5 | 5 | 0 | Unknown | [DE1-SoC-HPSFPGA](https://github.com/norxander/DE1-SoC-HPSFPGA)/999 | Image to column FPGA implementation (im2col by caffe) |
| 5 | 8 | 0 | Unknown | [Zybo-Open-Source-Video-IP-Toolbox](https://github.com/lasalvavida/Zybo-Open-Source-Video-IP-Toolbox)/1000 | A few tools for doing video processing on the Zybo FPGA board using VHDL |