## This is a most popular repository list for Verilog sorted by number of stars
|STARS|FORKS|ISSUES|LAST COMMIT|NAME/PLACE|DESCRIPTION|
| --- | --- | --- | --- | --- | --- |
| 1773 | 799 | 33 | 3 months ago | [e200_opensource](https://github.com/SI-RISCV/e200_opensource)/1 | Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2 |
| 1694 | 459 | 34 | 1 year, 2 months ago | [picorv32](https://github.com/cliffordwolf/picorv32)/2 | PicoRV32 - A Size-Optimized RISC-V CPU |
| 1314 | 446 | 24 | a day ago | [wujian100_open](https://github.com/T-head-Semi/wujian100_open)/3 | IC design and development should be faster，simpler and more reliable |
| 1134 | 176 | 10 | 3 months ago | [darkriscv](https://github.com/darklife/darkriscv)/4 | opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| 1092 | 426 | 186 | 3 years ago | [hw](https://github.com/nvdla/hw)/5 | RTL, Cmodel, and testbench for NVDLA |
| 946 | 69 | 2 | 2 years ago | [amiga2000-gfxcard](https://github.com/mntmn/amiga2000-gfxcard)/6 | MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog |
| 821 | 277 | 39 | a day ago | [verilog-ethernet](https://github.com/alexforencich/verilog-ethernet)/7 | Verilog Ethernet components for FPGA implementation |
| 788 | 1071 | 16 | 18 days ago | [hdl](https://github.com/analogdevicesinc/hdl)/8 | HDL libraries and projects |
| 680 | 79 | 1 | 7 months ago | [zipcpu](https://github.com/ZipCPU/zipcpu)/9 | A small, light weight, RISC CPU soft core |
| 674 | 181 | 10 | 3 years ago | [miaow](https://github.com/VerticalResearchGroup/miaow)/10 | An open source GPU based off of the AMD Southern Islands ISA. |
| 630 | 136 | 33 | 18 hours ago | [corundum](https://github.com/corundum/corundum)/11 | Open source, high performance, FPGA-based NIC |
| 625 | 217 | 30 | 13 days ago | [oh](https://github.com/aolofsson/oh)/12 | Verilog library for ASIC and FPGA designers |
| 577 | 477 | 48 | a day ago | [uhd](https://github.com/EttusResearch/uhd)/13 | The USRP™ Hardware Driver Repository |
| 548 | 277 | 7 | 2 years ago | [ODriveHardware](https://github.com/madcowswe/ODriveHardware)/14 | High performance motor control |
| 491 | 155 | 4 | 1 year, 2 months ago | [open-fpga-verilog-tutorial](https://github.com/Obijuan/open-fpga-verilog-tutorial)/15 | Learn how to design digital systems and synthesize them into an FPGA using only opensource tools |
| 438 | 79 | 2 | 1 year, 5 months ago | [LeFlow](https://github.com/danielholanda/LeFlow)/16 | Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks |
| 438 | 77 | 12 | a day ago | [serv](https://github.com/olofk/serv)/17 | SERV - The SErial RISC-V CPU |
| 434 | 167 | 1 | 3 years ago | [mips-cpu](https://github.com/jmahler/mips-cpu)/18 | MIPS CPU implemented in Verilog |
| 427 | 94 | 45 | 16 days ago | [sd2snes](https://github.com/mrehkopf/sd2snes)/19 | SD card based multi-purpose cartridge for the SNES |
| 418 | 69 | 34 | 8 days ago | [microwatt](https://github.com/antonblanchard/microwatt)/20 | A tiny Open POWER ISA softcore written in VHDL 2008 |
| 406 | 149 | 8 | 26 days ago | [verilog-axi](https://github.com/alexforencich/verilog-axi)/21 | Verilog AXI components for FPGA implementation |
| 363 | 116 | 47 | 8 days ago | [OpenLane](https://github.com/The-OpenROAD-Project/OpenLane)/22 | NOTE: The master branch is frozen for OpenMPW2. Please direct any PRs to the develop branch. :: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. |
| 349 | 110 | 42 | 4 hours ago | [OpenROAD](https://github.com/The-OpenROAD-Project/OpenROAD)/23 | OpenROAD's unified application implementing an RTL-to-GDS Flow |
| 346 | 71 | 18 | 8 months ago | [riscv-formal](https://github.com/SymbioticEDA/riscv-formal)/24 | RISC-V Formal Verification Framework |
| 341 | 172 | 38 | 4 years ago | [riffa](https://github.com/KastnerRG/riffa)/25 | The RIFFA development repository |
| 337 | 158 | 1 | 6 years ago | [FPGA-Imaging-Library](https://github.com/dtysky/FPGA-Imaging-Library)/26 | An open source library for image processing on FPGA. |
| 336 | 126 | 27 | 5 days ago | [mor1kx](https://github.com/openrisc/mor1kx)/27 | mor1kx - an OpenRISC 1000 processor IP core |
| 323 | 71 | 4 | 1 year, 1 month ago | [riscv](https://github.com/ultraembedded/riscv)/28 | RISC-V CPU Core (RV32IM) |
| 314 | 115 | 0 | 3 years ago | [verilog](https://github.com/seldridge/verilog)/29 | Repository for basic (and not so basic) Verilog blocks with high re-use potential |
| 305 | 11 | 4 | 14 days ago | [graphics-gremlin](https://github.com/schlae/graphics-gremlin)/30 | Open source retro ISA video card |
| 300 | 118 | 3 | 24 days ago | [cores](https://github.com/ultraembedded/cores)/31 | Various HDL (Verilog) IP Cores |
| 299 | 40 | 10 | 5 months ago | [VerilogBoy](https://github.com/zephray/VerilogBoy)/32 | A Pi emulating a GameBoy sounds cheap. What about an FPGA? |
| 299 | 106 | 9 | 2 days ago | [verilog-pcie](https://github.com/alexforencich/verilog-pcie)/33 | Verilog PCI express components |
| 287 | 94 | 0 | 18 days ago | [basic_verilog](https://github.com/pConst/basic_verilog)/34 | Must-have verilog systemverilog modules |
| 286 | 93 | 7 | 2 years ago | [icezum](https://github.com/FPGAwars/icezum)/35 | :star2: IceZUM Alhambra: an Arduino-like Open FPGA electronic board |
| 286 | 132 | 14 | 9 years ago | [netfpga](https://github.com/NetFPGA/netfpga)/36 | NetFPGA 1G infrastructure and gateware |
| 281 | 25 | 69 | 4 months ago | [ucr-eecs168-lab](https://github.com/sheldonucr/ucr-eecs168-lab)/37 | The lab schedules for EECS168 at UC Riverside |
| 260 | 49 | 6 | 1 year, 2 months ago | [biriscv](https://github.com/ultraembedded/biriscv)/38 | 32-bit Superscalar RISC-V CPU |
| 258 | 117 | 18 | 3 years ago | [convolution_network_on_FPGA](https://github.com/hunterlew/convolution_network_on_FPGA)/39 | CNN acceleration on virtex-7 FPGA with verilog HDL |
| 258 | 119 | 6 | 7 years ago | [FPGA-Litecoin-Miner](https://github.com/kramble/FPGA-Litecoin-Miner)/40 | A litecoin scrypt miner implemented with FPGA on-chip memory.  |
| 251 | 35 | 8 | 2 years ago | [Project-Zipline](https://github.com/opencomputeproject/Project-Zipline)/41 | Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm. |
| 233 | 86 | 12 | 25 days ago | [fpu](https://github.com/dawsonjon/fpu)/42 | synthesiseable ieee 754 floating point library in verilog  |
| 231 | 26 | 21 | 1 year, 8 months ago | [spispy](https://github.com/osresearch/spispy)/43 | An open source SPI flash emulator and monitor |
| 230 | 56 | 2 | 3 years ago | [zet](https://github.com/marmolejo/zet)/44 | Open source implementation of a x86 processor |
| 228 | 35 | 6 | 4 days ago | [Flute](https://github.com/bluespec/Flute)/45 | RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance |
| 220 | 70 | 1 | 8 months ago | [verilog-6502](https://github.com/Arlet/verilog-6502)/46 | A Verilog HDL model of the MOS 6502 CPU |
| 218 | 93 | 0 | a month ago | [openwifi-hw](https://github.com/open-sdr/openwifi-hw)/47 | FPGA/hardware design of openwifi |
| 216 | 37 | 13 | 18 days ago | [Piccolo](https://github.com/bluespec/Piccolo)/48 | RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT) |
| 216 | 44 | 7 | a month ago | [litepcie](https://github.com/enjoy-digital/litepcie)/49 | Small footprint and configurable PCIe core |
| 206 | 38 | 1 | a day ago | [wb2axip](https://github.com/ZipCPU/wb2axip)/50 | Bus bridges and other odds and ends |
| 203 | 42 | 1 | 3 years ago | [ridecore](https://github.com/ridecore/ridecore)/51 | RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL. |
| 202 | 55 | 22 | 8 years ago | [fpga_nes](https://github.com/brianbennett/fpga_nes)/52 | FPGA-based Nintendo Entertainment System Emulator |
| 196 | 47 | 127 | 2 days ago | [basejump_stl](https://github.com/bespoke-silicon-group/basejump_stl)/53 | BaseJump STL: A Standard Template Library for SystemVerilog |
| 195 | 67 | 13 | 7 months ago | [Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA](https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA)/54 | Verilog Generator of Neural Net Digit Detector for FPGA |
| 195 | 75 | 3 | 7 days ago | [verilog-i2c](https://github.com/alexforencich/verilog-i2c)/55 | Verilog I2C interface for FPGA implementation |
| 190 | 71 | 4 | 5 months ago | [verilog-uart](https://github.com/alexforencich/verilog-uart)/56 | Verilog UART |
| 186 | 69 | 3 | 3 years ago | [CNN-FPGA](https://github.com/QShen3/CNN-FPGA)/57 | 使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用 |
| 185 | 67 | 1 | 1 year, 6 months ago | [AccDNN](https://github.com/IBM/AccDNN)/58 | A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration. |
| 183 | 180 | 1 | 9 months ago | [fpga](https://github.com/EttusResearch/fpga)/59 | The USRP™ Hardware Driver FPGA Repository |
| 180 | 67 | 1 | 4 years ago | [sdram-controller](https://github.com/stffrdhrn/sdram-controller)/60 | Verilog SDRAM memory controller  |
| 178 | 29 | 6 | 2 years ago | [TinyFPGA-B-Series](https://github.com/tinyfpga/TinyFPGA-B-Series)/61 | Open source design files for the TinyFPGA B-Series boards.   |
| 173 | 85 | 0 | 4 months ago | [Kryon](https://github.com/becomequantum/Kryon)/62 | FPGA,Verilog,Python |
| 171 | 61 | 2 | a month ago | [sha256](https://github.com/secworks/sha256)/63 | Hardware implementation of the SHA-256 cryptographic hash function |
| 171 | 8 | 1 | 2 years ago | [fpga-chip8](https://github.com/pwmarcz/fpga-chip8)/64 | CHIP-8 console on FPGA |
| 167 | 22 | 0 | 7 years ago | [ez8](https://github.com/zhemao/ez8)/65 | The Easy 8-bit Processor |
| 162 | 60 | 0 | 25 days ago | [Verilog-Practice](https://github.com/xiaop1/Verilog-Practice)/66 | HDLBits website practices & solutions |
| 161 | 10 | 0 | 1 year, 8 months ago | [fpg1](https://github.com/hrvach/fpg1)/67 | PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console. |
| 160 | 42 | 6 | a month ago | [icesugar](https://github.com/wuxx/icesugar)/68 | iCESugar FPGA Board (base on iCE40UP5k) |
| 160 | 68 | 3 | a month ago | [SCALE-MAMBA](https://github.com/KULeuven-COSIC/SCALE-MAMBA)/69 | Repository for the SCALE-MAMBA MPC system |
| 157 | 27 | 1 | 6 days ago | [ice40-playground](https://github.com/smunaut/ice40-playground)/70 | Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker) |
| 154 | 54 | 2 | a month ago | [e203_hbirdv2](https://github.com/riscv-mcu/e203_hbirdv2)/71 | The Ultra-Low Power RISC-V Core |
| 153 | 77 | 0 | a month ago | [aes](https://github.com/secworks/aes)/72 | Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys. |
| 147 | 81 | 5 | 5 months ago | [openofdm](https://github.com/jhshi/openofdm)/73 | Sythesizable, modular Verilog implementation of 802.11 OFDM decoder. |
| 147 | 27 | 0 | 2 years ago | [SimpleVOut](https://github.com/cliffordwolf/SimpleVOut)/74 | A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals |
| 141 | 36 | 4 | 8 months ago | [nandland](https://github.com/nandland/nandland)/75 | All code found on nandland is here.  underconstruction.gif |
| 138 | 37 | 0 | 5 months ago | [wbuart32](https://github.com/ZipCPU/wbuart32)/76 | A simple, basic, formally verified UART controller |
| 137 | 27 | 6 | 2 years ago | [DisplayPort_Verilog](https://github.com/hamsternz/DisplayPort_Verilog)/77 | A Verilog implementation of DisplayPort protocol for FPGAs |
| 137 | 29 | 4 | 1 year, 8 months ago | [FPGA-peripherals](https://github.com/FPGAwars/FPGA-peripherals)/78 | :seedling: :snowflake: Collection of open-source peripherals in Verilog |
| 137 | 45 | 5 | 1 year, 11 months ago | [Tang_E203_Mini](https://github.com/Lichee-Pi/Tang_E203_Mini)/79 | LicheeTang 蜂鸟E203 Core |
| 136 | 45 | 22 | 1 year, 8 months ago | [open-register-design-tool](https://github.com/Juniper/open-register-design-tool)/80 | Tool to generate register RTL, models, and docs using SystemRDL or JSpec input |
| 135 | 71 | 3 | 4 years ago | [FPGA_Based_CNN](https://github.com/mtmd/FPGA_Based_CNN)/81 | FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform. |
| 130 | 40 | 0 | 7 years ago | [milkymist](https://github.com/m-labs/milkymist)/82 | SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU |
| 129 | 45 | 1 | 9 months ago | [schoolMIPS](https://github.com/MIPSfpga/schoolMIPS)/83 | CPU microarchitecture, step by step |
| 122 | 42 | 4 | 7 years ago | [fpganes](https://github.com/strigeus/fpganes)/84 | NES in Verilog |
| 121 | 24 | 3 | 1 year, 8 months ago | [raven-picorv32](https://github.com/efabless/raven-picorv32)/85 | Silicon-validated SoC implementation of the PicoSoc/PicoRV32 |
| 121 | 38 | 0 | 2 years ago | [Single_instruction_cycle_OpenMIPS](https://github.com/zach0zhang/Single_instruction_cycle_OpenMIPS)/86 | 通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器 |
| 120 | 39 | 0 | 1 year, 3 months ago | [RePlAce](https://github.com/The-OpenROAD-Project/RePlAce)/87 | RePlAce global placement tool |
| 119 | 31 | 0 | 5 hours ago | [livehd](https://github.com/masc-ucsc/livehd)/88 | Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation |
| 118 | 83 | 4 | 8 years ago | [uvm_axi](https://github.com/funningboy/uvm_axi)/89 | uvm AXI BFM(bus functional model) |
| 118 | 31 | 1 | 9 months ago | [iceGDROM](https://github.com/zeldin/iceGDROM)/90 | An FPGA based GDROM emulator for the Sega Dreamcast |
| 117 | 12 | 0 | 3 years ago | [vm80a](https://github.com/1801BM1/vm80a)/91 | i8080 precise replica in Verilog, based on reverse engineering of real die |
| 116 | 79 | 14 | 2 years ago | [orpsoc-cores](https://github.com/openrisc/orpsoc-cores)/92 | Core description files for FuseSoC |
| 115 | 16 | 6 | 4 months ago | [DreamcastHDMI](https://github.com/chriz2600/DreamcastHDMI)/93 | Dreamcast HDMI |
| 113 | 23 | 3 | 9 months ago | [a2o](https://github.com/openpower-cores/a2o)/94 | None |
| 113 | 18 | 5 | 11 days ago | [twitchcore](https://github.com/geohot/twitchcore)/95 | It's a core. Made on Twitch. |
| 112 | 75 | 5 | 3 years ago | [Hardware-CNN](https://github.com/alan4186/Hardware-CNN)/96 | A convolutional neural network implemented in hardware (verilog) |
| 110 | 23 | 1 | 1 year, 6 months ago | [usbcorev](https://github.com/avakar/usbcorev)/97 | A full-speed device-side USB peripheral core written in Verilog. |
| 109 | 23 | 0 | 4 years ago | [archexp](https://github.com/zhanghai/archexp)/98 | 浙江大学计算机体系结构课程实验 |
| 107 | 30 | 13 | 3 months ago | [Cores-SweRVolf](https://github.com/chipsalliance/Cores-SweRVolf)/99 | FuseSoC-based SoC for SweRV EH1 |
| 106 | 31 | 0 | 3 years ago | [mriscv](https://github.com/onchipuis/mriscv)/100 | A 32-bit Microcontroller featuring a RISC-V core |
| 105 | 47 | 1 | 8 years ago | [fft-dit-fpga](https://github.com/benreynwar/fft-dit-fpga)/101 | Verilog module for calculation of FFT. |
| 103 | 7 | 2 | a month ago | [icestation-32](https://github.com/dan-rodrigues/icestation-32)/102 | Compact FPGA game console |
| 103 | 16 | 3 | 5 months ago | [panologic-g2](https://github.com/tomverbeure/panologic-g2)/103 | Pano Logic G2 Reverse Engineering Project |
| 102 | 12 | 5 | a month ago | [usb3_pipe](https://github.com/enjoy-digital/usb3_pipe)/104 | USB3 PIPE interface for Xilinx 7-Series / Lattice ECP5 |
| 102 | 12 | 3 | 2 months ago | [n64rgb](https://github.com/borti4938/n64rgb)/105 | Everything around N64 and RGB |
| 102 | 15 | 1 | 3 months ago | [cpu11](https://github.com/1801BM1/cpu11)/106 | Revengineered ancient PDP-11 CPUs, originals and clones |
| 100 | 47 | 57 | a day ago | [fomu-workshop](https://github.com/im-tomu/fomu-workshop)/107 | Support files for participating in a Fomu workshop |
| 99 | 33 | 48 | 11 days ago | [symbiflow-examples](https://github.com/SymbiFlow/symbiflow-examples)/108 | Example designs showing different ways to use SymbiFlow toolchains. |
| 99 | 24 | 0 | 1 year, 7 months ago | [mips32-cpu](https://github.com/Trinkle23897/mips32-cpu)/109 | 奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用） |
| 99 | 80 | 0 | 3 years ago | [FPGA-CNN](https://github.com/dem123456789/FPGA-CNN)/110 | FPGA implementation of Cellular Neural Network (CNN) |
| 99 | 67 | 1 | 5 years ago | [or1200](https://github.com/openrisc/or1200)/111 | OpenRISC 1200 implementation |
| 97 | 17 | 1 | 6 years ago | [oldland-cpu](https://github.com/jamieiles/oldland-cpu)/112 | Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools |
| 96 | 19 | 5 | 1 year, 8 days ago | [tinyfpga_bx_usbserial](https://github.com/davidthings/tinyfpga_bx_usbserial)/113 | USB Serial on the TinyFPGA BX |
| 95 | 8 | 0 | 10 months ago | [vgasim](https://github.com/ZipCPU/vgasim)/114 | A Video display simulator |
| 95 | 10 | 1 | 1 year, 21 days ago | [lpc_sniffer_tpm](https://github.com/denandz/lpc_sniffer_tpm)/115 | A low pin count sniffer for ICEStick - targeting TPM chips |
| 95 | 29 | 1 | 4 years ago | [kamikaze](https://github.com/rgwan/kamikaze)/116 | Light-weight RISC-V RV32IMC microcontroller core. |
| 95 | 10 | 1 | 1 year, 2 months ago | [antikernel](https://github.com/azonenberg/antikernel)/117 | The Antikernel operating system project |
| 95 | 12 | 58 | 2 years ago | [spatial-lang](https://github.com/stanford-ppl/spatial-lang)/118 | Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language" |
| 94 | 17 | 1 | 1 year, 3 months ago | [display_controller](https://github.com/projf/display_controller)/119 | FPGA display controller with support for VGA, DVI, and HDMI. |
| 93 | 37 | 9 | 1 year, 7 months ago | [Tang_FPGA_Examples](https://github.com/Lichee-Pi/Tang_FPGA_Examples)/120 | LicheeTang FPGA Examples |
| 92 | 6 | 0 | 24 days ago | [fedar-f1-rv64im](https://github.com/eminfedar/fedar-f1-rv64im)/121 | 5-Stage Pipelined RV64IM RISC-V CPU design in Verilog. |
| 92 | 36 | 33 | a month ago | [ao486_MiSTer](https://github.com/MiSTer-devel/ao486_MiSTer)/122 | ao486 port for MiSTer |
| 91 | 34 | 0 | a month ago | [ivtest](https://github.com/steveicarus/ivtest)/123 | Regression test suite for Icarus Verilog. |
| 91 | 100 | 24 | a month ago | [caravel](https://github.com/efabless/caravel)/124 | Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space. |
| 90 | 29 | 0 | 1 year, 6 months ago | [NaiveMIPS-HDL](https://github.com/z4yx/NaiveMIPS-HDL)/125 | Naïve MIPS32 SoC implementation |
| 90 | 9 | 3 | a day ago | [jt12](https://github.com/jotego/jt12)/126 | FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10) |
| 89 | 36 | 8 | 2 years ago | [mipsfpga-plus](https://github.com/MIPSfpga/mipsfpga-plus)/127 | MIPSfpga+ allows loading programs via UART and has a switchable clock |
| 89 | 25 | 3 | 13 days ago | [icebreaker-verilog-examples](https://github.com/icebreaker-fpga/icebreaker-verilog-examples)/128 | This repository contains small example designs that can be used with the open source icestorm flow. |
| 88 | 17 | 2 | 2 months ago | [Toooba](https://github.com/bluespec/Toooba)/129 | RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT |
| 88 | 31 | 2 | 10 months ago | [apple-one](https://github.com/alangarf/apple-one)/130 | An attempt at a small Verilog implementation of the original Apple 1 on an FPGA |
| 87 | 18 | 4 | 6 years ago | [NeoGeoHDMI](https://github.com/charcole/NeoGeoHDMI)/131 | Verilog project that takes the digital video and audio from a Neo Geo MVS before going through the DACs and outputs the signals over HDMI |
| 87 | 9 | 0 | 2 years ago | [NeoGeoFPGA-sim](https://github.com/neogeodev/NeoGeoFPGA-sim)/132 | Simulation only cartridge NeoGeo hardware definition |
| 86 | 11 | 0 | 4 years ago | [PonyLink](https://github.com/cliffordwolf/PonyLink)/133 | A single-wire bi-directional chip-to-chip interface for FPGAs |
| 85 | 29 | 1 | 8 years ago | [Xilinx-Serial-Miner](https://github.com/teknohog/Xilinx-Serial-Miner)/134 | Bitcoin miner for Xilinx FPGAs |
| 85 | 39 | 4 | 4 months ago | [vsdflow](https://github.com/kunalg123/vsdflow)/135 | VSDFLOW  is  an  automated  solution  to  programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW  is  completely  build  using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic. |
| 85 | 20 | 0 | 11 months ago | [openarty](https://github.com/ZipCPU/openarty)/136 | An Open Source configuration of the Arty platform |
| 84 | 8 | 0 | 3 years ago | [iCE40](https://github.com/mcmayer/iCE40)/137 | Lattice iCE40 FPGA experiments - Work in progress |
| 83 | 6 | 2 | 14 days ago | [vt52-fpga](https://github.com/AndresNavarro82/vt52-fpga)/138 | None |
| 82 | 29 | 36 | 3 months ago | [Minimig-AGA_MiSTer](https://github.com/MiSTer-devel/Minimig-AGA_MiSTer)/139 | None |
| 82 | 16 | 1 | 2 months ago | [ice40_ultraplus_examples](https://github.com/damdoy/ice40_ultraplus_examples)/140 | Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation |
| 81 | 27 | 0 | 6 years ago | [cpu](https://github.com/ejrh/cpu)/141 | A very primitive but hopefully self-educational CPU in Verilog |
| 81 | 47 | 34 | a month ago | [Genesis_MiSTer](https://github.com/MiSTer-devel/Genesis_MiSTer)/142 | Sega Genesis for MiSTer |
| 81 | 12 | 3 | 4 years ago | [fpgaboy](https://github.com/trun/fpgaboy)/143 | Implementation Nintendo's GameBoy console on an FPGA |
| 81 | 25 | 0 | 6 years ago | [lm32](https://github.com/m-labs/lm32)/144 | LatticeMico32 soft processor |
| 81 | 53 | 4 | 6 years ago | [DSLogic-hdl](https://github.com/DreamSourceLab/DSLogic-hdl)/145 | An open source FPGA design for DSLogic |
| 80 | 8 | 1 | 10 years ago | [Homotopy](https://github.com/andrejbauer/Homotopy)/146 | Homotopy theory in Coq. |
| 80 | 22 | 15 | 3 years ago | [c65gs](https://github.com/gardners/c65gs)/147 | FPGA-based C64 Accelerator / C65 like computer |
| 80 | 21 | 7 | 1 year, 1 month ago | [ice40_examples](https://github.com/nesl/ice40_examples)/148 | Public examples of ICE40 HX8K examples using Icestorm |
| 79 | 13 | 0 | 1 year, 4 months ago | [agc_simulation](https://github.com/virtualagc/agc_simulation)/149 | Verilog simulation files for a replica of the Apollo Guidance Computer |
| 79 | 20 | 1 | 1 year, 8 months ago | [MobileNet-in-FPGA](https://github.com/ZFTurbo/MobileNet-in-FPGA)/150 | Generator of verilog description for FPGA MobileNet implementation |
| 78 | 44 | 3 | 8 years ago | [Icarus](https://github.com/ngzhang/Icarus)/151 | DUAL Spartan6 Development Platform |
| 76 | 19 | 1 | 19 days ago | [aib-phy-hardware](https://github.com/chipsalliance/aib-phy-hardware)/152 | Advanced Interface Bus (AIB) die-to-die hardware open source |
| 74 | 29 | 71 | 3 months ago | [bsg_manycore](https://github.com/bespoke-silicon-group/bsg_manycore)/153 | Tile based architecture designed for computing efficiency, scalability and generality |
| 73 | 11 | 0 | 5 years ago | [cpus-caddr](https://github.com/lisper/cpus-caddr)/154 | FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs |
| 73 | 18 | 5 | 1 year, 10 months ago | [Reindeer](https://github.com/PulseRain/Reindeer)/155 | PulseRain Reindeer - RISCV RV32I[M] Soft CPU |
| 72 | 13 | 2 | 1 year, 10 months ago | [MIPS-pipeline-processor](https://github.com/mhyousefi/MIPS-pipeline-processor)/156 | A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding |
| 72 | 31 | 10 | 7 months ago | [c5soc_opencl](https://github.com/thinkoco/c5soc_opencl)/157 | DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on. |
| 72 | 40 | 0 | 8 years ago | [uart](https://github.com/jamieiles/uart)/158 | Verilog UART |
| 72 | 27 | 0 | 2 years ago | [PASC](https://github.com/jbush001/PASC)/159 | Parallel Array of Simple Cores. Multicore processor. |
| 71 | 6 | 1 | 8 months ago | [core_jpeg](https://github.com/ultraembedded/core_jpeg)/160 | High throughput JPEG decoder in Verilog for FPGA |
| 71 | 9 | 5 | 7 days ago | [VGChips](https://github.com/furrtek/VGChips)/161 | Video Game custom chips reverse-engineered from silicon |
| 71 | 40 | 31 | a month ago | [NeoGeo_MiSTer](https://github.com/MiSTer-devel/NeoGeo_MiSTer)/162 | NeoGeo for MiSTer |
| 70 | 19 | 1 | 2 months ago | [dspfilters](https://github.com/ZipCPU/dspfilters)/163 | A collection of demonstration digital filters |
| 70 | 27 | 1 | 3 years ago | [clacc](https://github.com/taoyilee/clacc)/164 | Deep Learning Accelerator (Convolution Neural Networks) |
| 69 | 19 | 2 | 2 years ago | [ZAP](https://github.com/krevanth/ZAP)/165 | ZAP is a pipelined ARMv4T architecture compatible processor with cache and MMU. |
| 69 | 9 | 8 | 2 months ago | [xcrypto](https://github.com/scarv/xcrypto)/166 | XCrypto: a cryptographic ISE for RISC-V |
| 69 | 12 | 0 | 2 months ago | [Colorlight-FPGA-Projects](https://github.com/wuxx/Colorlight-FPGA-Projects)/167 | current focus on Colorlight i5 series module |
| 68 | 29 | 1 | 3 years ago | [verilog-lfsr](https://github.com/alexforencich/verilog-lfsr)/168 | Fully parametrizable combinatorial parallel LFSR/CRC module |
| 67 | 7 | 6 | 17 hours ago | [jt_gng](https://github.com/jotego/jt_gng)/169 | CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter, Vulgus and The Speed Rumbler. |
| 67 | 2 | 0 | a month ago | [riskow](https://github.com/racerxdl/riskow)/170 | Learning how to make a RISC-V  |
| 65 | 33 | 0 | 3 months ago | [cdbus_ip](https://github.com/dukelec/cdbus_ip)/171 | CDBUS Protocol and the IP Core for FPGA users |
| 65 | 16 | 1 | 3 years ago | [RISC-V-CPU](https://github.com/Evensgn/RISC-V-CPU)/172 | RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL. |
| 65 | 12 | 0 | 2 years ago | [toygpu](https://github.com/matt-kimball/toygpu)/173 | A simple GPU on a TinyFPGA BX |
| 65 | 23 | 2 | a month ago | [Haasoscope](https://github.com/drandyhaas/Haasoscope)/174 | Docs, design, firmware, and software for the Haasoscope |
| 64 | 33 | 1 | 2 years ago | [zynq-axis](https://github.com/bmartini/zynq-axis)/175 | Hardware, Linux Driver and Library for the Zynq AXI DMA interface  |
| 64 | 22 | 1 | 3 years ago | [SoftMC](https://github.com/CMU-SAFARI/SoftMC)/176 | SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf> |
| 63 | 24 | 0 | 3 months ago | [DetectHumanFaces](https://github.com/WalkerLau/DetectHumanFaces)/177 | Real time face detection based on Arm Cortex-M3 DesignStart and FPGA |
| 63 | 26 | 2 | 2 years ago | [VidorFPGA](https://github.com/vidor-libraries/VidorFPGA)/178 | repository for Vidor FPGA IP blocks and projects |
| 62 | 14 | 3 | 9 years ago | [ao68000](https://github.com/alfikpl/ao68000)/179 | The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor. |
| 62 | 8 | 0 | 4 years ago | [FPGA-TX](https://github.com/dawsonjon/FPGA-TX)/180 | FPGA based transmitter |
| 62 | 53 | 5 | 3 years ago | [Convolutional-Neural-Network](https://github.com/AniketBadhan/Convolutional-Neural-Network)/181 | Implementation of CNN using Verilog |
| 62 | 12 | 0 | 2 years ago | [MARLANN](https://github.com/SymbioticEDA/MARLANN)/182 | Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks |
| 61 | 30 | 3 | 6 months ago | [SD-card-controller](https://github.com/mczerski/SD-card-controller)/183 | WISHBONE SD Card Controller IP Core |
| 61 | 36 | 3 | 4 days ago | [blinky](https://github.com/fusesoc/blinky)/184 | Example LED blinking project for your FPGA dev board of choice |
| 60 | 12 | 1 | 7 months ago | [mc6809](https://github.com/cavnex/mc6809)/185 | Cycle-Accurate MC6809/E implementation, Verilog |
| 59 | 9 | 1 | 1 year, 8 months ago | [Riscy-SoC](https://github.com/AleksandarKostovic/Riscy-SoC)/186 | Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog |
| 59 | 32 | 0 | 2 months ago | [cdpga](https://github.com/dukelec/cdpga)/187 | FPGA core boards / evaluation boards based on CDCTL hardware |
| 59 | 30 | 0 | 2 months ago | [async_fifo](https://github.com/dpretet/async_fifo)/188 | A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog |
| 59 | 14 | 0 | 2 years ago | [riscv](https://github.com/ataradov/riscv)/189 | Verilog implementation of a RISC-V core |
| 58 | 18 | 2 | 1 year, 3 months ago | [h265-encoder-rtl](https://github.com/openasic-org/h265-encoder-rtl)/190 | None |
| 58 | 5 | 0 | 7 months ago | [rt](https://github.com/tomverbeure/rt)/191 | A Full Hardware Real-Time Ray-Tracer |
| 58 | 23 | 2 | 1 year, 8 months ago | [daisho](https://github.com/enjoy-digital/daisho)/192 | Test of the USB3 IP Core from Daisho on a Xilinx device |
| 57 | 49 | 1 | 8 months ago | [Practical-UVM-Step-By-Step](https://github.com/Practical-UVM-Step-By-Step/Practical-UVM-Step-By-Step)/193 | This is the main repository for all the examples for the book Practical UVM |
| 57 | 35 | 20 | 18 days ago | [Gameboy_MiSTer](https://github.com/MiSTer-devel/Gameboy_MiSTer)/194 | Gameboy for MiSTer |
| 57 | 13 | 0 | 2 years ago | [hyperram](https://github.com/blackmesalabs/hyperram)/195 | Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC |
| 57 | 26 | 0 | 2 years ago | [mnist_fpga](https://github.com/papcjy/mnist_fpga)/196 | using xilinx xc6slx45 to implement mnist net |
| 56 | 30 | 8 | 4 years ago | [nysa-sata](https://github.com/CospanDesign/nysa-sata)/197 | None |
| 55 | 29 | 2 | 11 months ago | [cnn_hardware_acclerator_for_fpga](https://github.com/sumanth-kalluri/cnn_hardware_acclerator_for_fpga)/198 | This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs |
| 55 | 28 | 5 | a month ago | [libsystemctlm-soc](https://github.com/Xilinx/libsystemctlm-soc)/199 | SystemC/TLM-2.0 Co-simulation framework |
| 55 | 18 | 0 | 6 years ago | [Verilog-caches](https://github.com/airin711/Verilog-caches)/200 | Various caches written in Verilog-HDL |
| 55 | 22 | 2 | 10 months ago | [core_ddr3_controller](https://github.com/ultraembedded/core_ddr3_controller)/201 | A DDR3 memory controller in Verilog for various FPGAs |
| 55 | 16 | 0 | 1 year, 1 month ago | [hardenedlinux_profiles](https://github.com/hardenedlinux/hardenedlinux_profiles)/202 | It contains hardenedlinux community documentation. |
| 54 | 11 | 1 | a month ago | [up5k](https://github.com/osresearch/up5k)/203 | Upduino v2 with the ice40 up5k FPGA demos |
| 53 | 3 | 0 | 5 months ago | [wbscope](https://github.com/ZipCPU/wbscope)/204 | A wishbone controlled scope for FPGA's |
| 53 | 12 | 1 | 5 months ago | [sdspi](https://github.com/ZipCPU/sdspi)/205 | SD-Card controller, using a SPI interface that is (optionally) shared |
| 53 | 14 | 0 | 5 years ago | [fpga-md5-cracker](https://github.com/John-Leitch/fpga-md5-cracker)/206 | A 64-stage pipelined MD5 implementation written in verliog.  Runs reliably on a DE0-Nano at 100mhz, computing 100 million hashes per second. |
| 53 | 20 | 13 | 1 year, 9 months ago | [alpha-release](https://github.com/The-OpenROAD-Project/alpha-release)/207 | Builds, flow and designs for the alpha release |
| 53 | 4 | 1 | 6 months ago | [xenowing](https://github.com/xenowing/xenowing)/208 | "What comes next? Super Mario 128? Actually, that's what I want to do." |
| 52 | 25 | 0 | 10 months ago | [timetoexplore](https://github.com/WillGreen/timetoexplore)/209 | Source code to accompany https://timetoexplore.net |
| 52 | 22 | 1 | a month ago | [opencpi](https://github.com/opencpi/opencpi)/210 | Open Component Portability Infrastructure |
| 52 | 17 | 0 | 7 years ago | [verilog_fixed_point_math_library](https://github.com/freecores/verilog_fixed_point_math_library)/211 | Fixed Point Math Library for Verilog |
| 52 | 20 | 0 | 8 months ago | [SM3_core](https://github.com/ljgibbslf/SM3_core)/212 | None |
| 52 | 2 | 0 | 2 years ago | [soc](https://github.com/combinatorylogic/soc)/213 | An experimental System-on-Chip with a custom compiler toolchain. |
| 52 | 31 | 35 | 5 years ago | [minimig-mist](https://github.com/rkrajnc/minimig-mist)/214 | Minimig for the MiST board |
| 52 | 6 | 2 | 1 year, 7 months ago | [ay-3-8910_reverse_engineered](https://github.com/lvd2/ay-3-8910_reverse_engineered)/215 | The reverse-engineered AY-3-8910 chip. Transistor-level schematics, verilog model and a testbench with tools, that can render register dump files into .flac soundtrack. |
| 51 | 7 | 0 | 2 years ago | [up5k_basic](https://github.com/emeb/up5k_basic)/216 | A small 6502 system with MS BASIC in ROM |
| 51 | 5 | 1 | 1 year, 5 months ago | [flickerfixer](https://github.com/niklasekstrom/flickerfixer)/217 | An open source flicker fixer for Amiga 500/2000 |
| 51 | 17 | 1 | 1 year, 4 months ago | [aib-phy-hardware](https://github.com/intel/aib-phy-hardware)/218 | None |
| 51 | 7 | 13 | 2 years ago | [Neogeo_MiSTer_old](https://github.com/furrtek/Neogeo_MiSTer_old)/219 | SNK NeoGeo core for the MiSTer platform |
| 51 | 10 | 4 | 8 months ago | [amiga_replacement_project](https://github.com/nonarkitten/amiga_replacement_project)/220 | This is an attempt to make clean Verilog sources for each chip on the Amiga. |
| 51 | 16 | 2 | 2 years ago | [Verilog-Projects](https://github.com/nxbyte/Verilog-Projects)/221 | This repository contains source code for past labs and projects involving FPGA and Verilog based designs |
| 51 | 12 | 1 | 1 year, 20 days ago | [challenges-2020](https://github.com/pwn2winctf/challenges-2020)/222 | Pwn2Win 2020 Challenges |
| 51 | 18 | 3 | 9 years ago | [ORGFXSoC](https://github.com/maidenone/ORGFXSoC)/223 | An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU) |
| 50 | 23 | 1 | 3 years ago | [TOE](https://github.com/hpb-project/TOE)/224 | TCP Offload Engine  |
| 50 | 19 | 0 | 3 years ago | [MIPS](https://github.com/valar1234/MIPS)/225 | A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache. |
| 50 | 14 | 0 | 2 years ago | [VexRiscvSoftcoreContest2018](https://github.com/SpinalHDL/VexRiscvSoftcoreContest2018)/226 | None |
| 49 | 26 | 3 | 4 years ago | [digital-servo](https://github.com/nist-ionstorage/digital-servo)/227 | NIST digital servo: an FPGA based fast digital feedback controller |
| 49 | 11 | 0 | 1 year, 6 months ago | [icebreaker-workshop](https://github.com/icebreaker-fpga/icebreaker-workshop)/228 | iCEBreaker Workshop |
| 49 | 6 | 47 | 9 months ago | [rigel](https://github.com/jameshegarty/rigel)/229 | Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra. |
| 48 | 22 | 0 | 1 year, 8 months ago | [R8051](https://github.com/risclite/R8051)/230 |  8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core. |
| 48 | 38 | 0 | 6 years ago | [IPCORE](https://github.com/aquaxis/IPCORE)/231 | None |
| 48 | 10 | 0 | 8 months ago | [screen-pong](https://github.com/juanmard/screen-pong)/232 | Pong game in a FPGA. |
| 48 | 11 | 0 | 11 months ago | [XilinxUnisimLibrary](https://github.com/Xilinx/XilinxUnisimLibrary)/233 | None |
| 48 | 34 | 1 | 5 years ago | [mips32r1_xum](https://github.com/grantae/mips32r1_xum)/234 | A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This is a bare-metal CPU with no virtual memory. (Old University of Utah XUM archive) |
| 48 | 3 | 1 | 1 year, 3 months ago | [gameboy-fpga-cartridge](https://github.com/ghidraninja/gameboy-fpga-cartridge)/235 | None |
| 47 | 3 | 0 | 3 years ago | [collection-iPxs](https://github.com/sergicuen/collection-iPxs)/236 | Icestudio Pixel Stream collection |
| 47 | 3 | 1 | 4 years ago | [21FX](https://github.com/defparam/21FX)/237 | A bootloader for the SNES console |
| 47 | 8 | 1 | 1 year, 7 months ago | [panologic](https://github.com/tomverbeure/panologic)/238 | PanoLogic Zero Client G1 reverse engineering info |
| 47 | 10 | 3 | a month ago | [OpenAmiga500FastRamExpansion](https://github.com/SukkoPera/OpenAmiga500FastRamExpansion)/239 | 4/8 MB Fast RAM Expansion for the Commodore Amiga 500 |
| 46 | 22 | 25 | 2 months ago | [MegaCD_MiSTer](https://github.com/MiSTer-devel/MegaCD_MiSTer)/240 | Mega CD for MiSTer |
| 46 | 26 | 2 | 7 years ago | [beagle](https://github.com/bikerglen/beagle)/241 | BeagleBone HW, SW, & FPGA Development |
| 46 | 6 | 1 | 3 years ago | [lpc_sniffer](https://github.com/lynxis/lpc_sniffer)/242 | a low pin count sniffer for icestick |
| 46 | 13 | 1 | 1 year, 2 months ago | [fpga-sdft](https://github.com/mattvenn/fpga-sdft)/243 | sliding DFT for FPGA, targetting Lattice ICE40 1k |
| 46 | 4 | 0 | a month ago | [vdatp](https://github.com/danfoisy/vdatp)/244 | Volumetric Display using an Acoustically Trapped Particle |
| 46 | 26 | 2 | 1 year, 11 months ago | [verilog-cam](https://github.com/alexforencich/verilog-cam)/245 | Verilog Content Addressable Memory Module |
| 45 | 7 | 15 | 4 months ago | [hrm-cpu](https://github.com/adumont/hrm-cpu)/246 | Human Resource Machine - CPU Design #HRM |
| 45 | 26 | 1 | 4 years ago | [h.265_encoder](https://github.com/Bearzeng/h.265_encoder)/247 | None |
| 45 | 38 | 0 | 1 year, 7 months ago | [AMBA_AXI_AHB_APB](https://github.com/adki/AMBA_AXI_AHB_APB)/248 | AMBA bus lecture material |
| 45 | 20 | 5 | 7 days ago | [corescore](https://github.com/olofk/corescore)/249 | CoreScore |
| 45 | 16 | 2 | 3 years ago | [chiphack](https://github.com/embecosm/chiphack)/250 | Repository and Wiki for Chip Hack events. |
| 45 | 13 | 0 | 3 years ago | [caribou](https://github.com/fpgasystems/caribou)/251 | Caribou: Distributed Smart Storage built with FPGAs |
| 45 | 17 | 0 | 2 years ago | [BUAA_CO](https://github.com/aptx1231/BUAA_CO)/252 | 2017级北航计算机学院计算机组成原理课程设计(MIPS CPU) |
| 44 | 36 | 1 | 2 years ago | [AlteraDE2Labs_Verilog](https://github.com/BenBergman/AlteraDE2Labs_Verilog)/253 | My solutions to Alteras example labs |
| 44 | 20 | 0 | 2 years ago | [NPU_on_FPGA](https://github.com/cxdzyq1110/NPU_on_FPGA)/254 | 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。 |
| 44 | 14 | 0 | 4 years ago | [yarvi](https://github.com/tommythorn/yarvi)/255 | Yet Another RISC-V Implementation |
| 44 | 28 | 1 | 2 years ago | [GNSS_Firehose](https://github.com/pmonta/GNSS_Firehose)/256 | Wideband front-end digitizer for GPS, GLONASS, Galileo, BeiDou |
| 43 | 6 | 0 | 4 years ago | [MAM65C02-Processor-Core](https://github.com/MorrisMA/MAM65C02-Processor-Core)/257 | Microprogrammed 65C02-compatible FPGA Processor Core (Verilog-2001) |
| 43 | 17 | 0 | 8 years ago | [Multiplier16X16](https://github.com/wuzeyou/Multiplier16X16)/258 | Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder |
| 43 | 13 | 1 | 15 days ago | [sha3](https://github.com/ucb-bar/sha3)/259 | None |
| 43 | 9 | 4 | 7 months ago | [ice-chips-verilog](https://github.com/TimRudy/ice-chips-verilog)/260 | IceChips is a library of all common discrete logic devices in Verilog |
| 43 | 5 | 1 | 1 year, 10 months ago | [engine-V](https://github.com/micro-FPGA/engine-V)/261 | SoftCPU/SoC engine-V |
| 43 | 11 | 2 | 12 days ago | [benchmarks](https://github.com/lsils/benchmarks)/262 | EPFL logic synthesis benchmarks |
| 43 | 6 | 1 | 10 months ago | [iua](https://github.com/smunaut/iua)/263 | ice40 USB Analyzer |
| 43 | 14 | 0 | 4 years ago | [sds7102](https://github.com/wingel/sds7102)/264 | A port of Linux to the OWON SDS7102 scope |
| 42 | 32 | 1 | 2 years ago | [ethernet_10ge_mac_SV_UVM_tb](https://github.com/andres-mancera/ethernet_10ge_mac_SV_UVM_tb)/265 | SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core |
| 42 | 24 | 3 | a month ago | [vortex](https://github.com/vortexgpgpu/vortex)/266 | None |
| 42 | 16 | 0 | 1 year, 1 month ago | [max1000-tutorial](https://github.com/vpecanins/max1000-tutorial)/267 | Tutorial and example projects for the Arrow MAX1000 FPGA board |
| 42 | 12 | 1 | 2 years ago | [Speech256](https://github.com/trcwm/Speech256)/268 | An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10. |
| 42 | 17 | 1 | 3 years ago | [ARM7](https://github.com/chsasank/ARM7)/269 | Implemetation of pipelined ARM7TDMI processor in Verilog |
| 42 | 27 | 3 | 3 years ago | [prog_fpgas](https://github.com/simonmonk/prog_fpgas)/270 | The repository for the Verilog code examples and ISE projects that accompany the book Programming FPGAs: Getting Started with Verilog. |
| 42 | 14 | 0 | 5 months ago | [dpll](https://github.com/ZipCPU/dpll)/271 | A collection of phase locked loop (PLL) related projects |
| 42 | 30 | 3 | 5 years ago | [bch_verilog](https://github.com/russdill/bch_verilog)/272 | Verilog based BCH encoder/decoder |
| 41 | 9 | 0 | 2 years ago | [ctf](https://github.com/q3k/ctf)/273 | Stuff from CTF contests |
| 41 | 30 | 0 | 5 years ago | [mojo-base-project](https://github.com/embmicro/mojo-base-project)/274 | This is the base project for the Mojo. It should be used as the starting point for all projects. |
| 41 | 10 | 3 | 6 days ago | [act](https://github.com/asyncvlsi/act)/275 | ACT hardware description language and core tools. |
| 41 | 7 | 0 | 2 years ago | [fpga-odysseus](https://github.com/ulx3s/fpga-odysseus)/276 |  FPGA Odysseus with ULX3S |
| 41 | 8 | 0 | a day ago | [Fuxi](https://github.com/MaxXSoft/Fuxi)/277 | Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3. |
| 40 | 10 | 0 | 3 years ago | [mips-cpu](https://github.com/sxtyzhangzk/mips-cpu)/278 | A MIPS CPU implemented in Verilog |
| 40 | 9 | 0 | 11 months ago | [moxie-cores](https://github.com/atgreen/moxie-cores)/279 | Moxie-compatible core repository |
| 40 | 14 | 6 | 2 years ago | [BeagleWire](https://github.com/pmezydlo/BeagleWire)/280 | This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017 |
| 40 | 7 | 0 | a month ago | [icesugar-pro](https://github.com/wuxx/icesugar-pro)/281 | iCESugar series FPGA dev board |
| 40 | 7 | 1 | 6 months ago | [basic-ecp5-pcb](https://github.com/mattvenn/basic-ecp5-pcb)/282 | None |
| 40 | 5 | 0 | a month ago | [UltraMIPS_NSCSCC](https://github.com/SocialistDalao/UltraMIPS_NSCSCC)/283 | UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral. |
| 40 | 9 | 1 | 3 years ago | [BAR-Tender](https://github.com/defparam/BAR-Tender)/284 | An FPGA I/O Device which services physical memory reads/writes via UMDF2 driver |
| 40 | 13 | 0 | 1 year, 6 months ago | [drec-fpga-intro](https://github.com/viktor-prutyanov/drec-fpga-intro)/285 | Materials for "Introduction to FPGA and Verilog" at MIPT DREC |
| 39 | 12 | 0 | 2 years ago | [DIY_OpenMIPS](https://github.com/GundamBox/DIY_OpenMIPS)/286 | 實作《自己動手寫CPU》書上的程式碼 |
| 39 | 15 | 50 | 7 months ago | [tapasco](https://github.com/esa-tu-darmstadt/tapasco)/287 | The Task Parallel System Composer (TaPaSCo) |
| 39 | 8 | 2 | 4 years ago | [ACC](https://github.com/Obijuan/ACC)/288 | Apollo CPU Core in Verilog. For learning and having fun with open FPGA |
| 39 | 8 | 2 | 2 years ago | [cnnhwpe](https://github.com/chenhaoc/cnnhwpe)/289 | None |
| 39 | 4 | 0 | 2 years ago | [tiny_usb_examples](https://github.com/lawrie/tiny_usb_examples)/290 | Using the TinyFPGA BX USB code in user designs |
| 39 | 42 | 2 | 11 hours ago | [oc-accel](https://github.com/OpenCAPI/oc-accel)/291 | OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology |
| 39 | 12 | 0 | 10 months ago | [first-fpga-pcb](https://github.com/mattvenn/first-fpga-pcb)/292 | FPGA dev board based on Lattice iCE40 8k |
| 39 | 6 | 1 | 3 days ago | [GottaGoFastRAM](https://github.com/LIV2/GottaGoFastRAM)/293 | 8MB Autoconfig FastRAM for Amiga 500/1000/2000/CDTV |
| 38 | 6 | 0 | 1 year, 2 months ago | [MIPS48PipelineCPU](https://github.com/ljlin/MIPS48PipelineCPU)/294 | 5 stage pipelined MIPS-32 processor |
| 38 | 16 | 0 | 1 year, 8 months ago | [ethmac](https://github.com/freecores/ethmac)/295 | Ethernet MAC 10/100 Mbps |
| 38 | 11 | 0 | 2 years ago | [HyperBUS](https://github.com/gtjennings1/HyperBUS)/296 | A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs |
| 38 | 11 | 3 | 2 hours ago | [SOFA](https://github.com/lnis-uofu/SOFA)/297 | SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA |
| 38 | 15 | 3 | 3 months ago | [verilog-math](https://github.com/dawsonjon/verilog-math)/298 | Mathematical Functions in Verilog |
| 38 | 29 | 3 | 7 years ago | [cordic](https://github.com/cebarnes/cordic)/299 | An implementation of the CORDIC algorithm in Verilog. |
| 37 | 17 | 1 | 17 years ago | [8051](https://github.com/freecores/8051)/300 | 8051 core |
| 37 | 22 | 1 | 8 years ago | [Atalanta](https://github.com/hsluoyz/Atalanta)/301 | Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University. |
| 37 | 4 | 0 | 3 years ago | [Computer-Architecture-Task-2](https://github.com/lmxyy/Computer-Architecture-Task-2)/302 | Riscv32 CPU Project |
| 37 | 14 | 0 | 3 years ago | [robot-arm-v01](https://github.com/bikerglen/robot-arm-v01)/303 | None |
| 37 | 5 | 2 | 4 years ago | [Frix](https://github.com/archlabo/Frix)/304 | IBM PC Compatible SoC for a commercially available FPGA board |
| 37 | 27 | 0 | 9 years ago | [DDR2_Controller](https://github.com/adibis/DDR2_Controller)/305 | DDR2 memory controller written in Verilog |
| 36 | 1 | 1 | 4 months ago | [spokefpga](https://github.com/davidthings/spokefpga)/306 | FPGA Tools and Library |
| 36 | 9 | 0 | 9 years ago | [dcpu16](https://github.com/sybreon/dcpu16)/307 | Pipelined DCPU-16 Verilog Implementation |
| 36 | 4 | 0 | 3 years ago | [RISC-processor](https://github.com/suyashmahar/RISC-processor)/308 | Simple single cycle RISC processor written in Verilog  |
| 36 | 20 | 0 | 2 years ago | [huaweicloud-fpga](https://github.com/huaweicloud/huaweicloud-fpga)/309 | The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server. |
| 36 | 20 | 1 | 2 years ago | [OV7670-Verilog](https://github.com/westonb/OV7670-Verilog)/310 | Verilog modules required to get the OV7670 camera working |
| 35 | 0 | 0 | 2 years ago | [comparchitecture](https://github.com/vladostan/comparchitecture)/311 | Verilog and MIPS simple programs |
| 35 | 2 | 0 | 3 years ago | [vga_to_ascii](https://github.com/zephray/vga_to_ascii)/312 | Realtime VGA to ASCII Art converter |
| 35 | 13 | 0 | 5 years ago | [yosys-bigsim](https://github.com/YosysHQ/yosys-bigsim)/313 | A collection of big designs to run post-synthesis simulations with yosys |
| 35 | 9 | 1 | 5 years ago | [oc_jpegencode](https://github.com/chiggs/oc_jpegencode)/314 | Fork of OpenCores jpegencode with Cocotb testbench |
| 35 | 15 | 3 | 5 years ago | [FPU](https://github.com/danshanley/FPU)/315 | IEEE 754 floating point unit in Verilog |
| 35 | 13 | 0 | 4 years ago | [ECE1373_2016_hft_on_fpga](https://github.com/mustafabbas/ECE1373_2016_hft_on_fpga)/316 | High Frequency Trading using Vivado HLS |
| 35 | 8 | 2 | 3 months ago | [iceZ0mb1e](https://github.com/abnoname/iceZ0mb1e)/317 | FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC |
| 35 | 15 | 1 | 6 years ago | [minimig-de1](https://github.com/rkrajnc/minimig-de1)/318 | Minimig for the DE1 board |
| 35 | 13 | 0 | 1 year, 18 days ago | [neuralNetwork](https://github.com/vipinkmenon/neuralNetwork)/319 | None |
| 34 | 2 | 0 | 4 months ago | [fpga_pio](https://github.com/lawrie/fpga_pio)/320 | An attempt to recreate the RP2040 PIO in an FPGA |
| 34 | 12 | 41 | 28 days ago | [zx-evo](https://github.com/tslabs/zx-evo)/321 | TS-Configuration for ZX Spectrum clone named ZX-Evolution |
| 34 | 16 | 1 | 5 years ago | [nfmac10g](https://github.com/forconesi/nfmac10g)/322 | Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC |
| 34 | 5 | 3 | 9 days ago | [fpga_support_plug](https://github.com/Bestduan/fpga_support_plug)/323 | 在vscode上的fpga开发插件 |
| 34 | 11 | 0 | 8 months ago | [trng](https://github.com/secworks/trng)/324 | True Random Number Generator core implemented in Verilog. |
| 34 | 31 | 5 | a day ago | [OpenROAD-flow-scripts](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts)/325 | None |
| 34 | 7 | 0 | 4 months ago | [EDN8-PRO](https://github.com/krikzz/EDN8-PRO)/326 | EverDrive N8 PRO dev sources |
| 33 | 16 | 0 | 6 years ago | [verilog-utils](https://github.com/shuckc/verilog-utils)/327 | native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches |
| 33 | 7 | 5 | 5 months ago | [74xx-liberty](https://github.com/Ravenslofty/74xx-liberty)/328 | None |
| 33 | 2 | 0 | 5 years ago | [HaSKI](https://github.com/wyager/HaSKI)/329 | Cλash/Haskell FPGA-based SKI calculus evaluator |
| 33 | 29 | 7 | 2 years ago | [spi-slave](https://github.com/nandland/spi-slave)/330 | SPI Slave for FPGA in Verilog and VHDL |
| 33 | 6 | 0 | 10 months ago | [core_dvi_framebuffer](https://github.com/ultraembedded/core_dvi_framebuffer)/331 | Minimal DVI / HDMI Framebuffer |
| 33 | 21 | 0 | 8 months ago | [thinpad_top](https://github.com/thu-cs-lab/thinpad_top)/332 | Project template for Artix-7 based Thinpad board |
| 33 | 6 | 0 | 4 years ago | [wiki](https://github.com/tmatsuya/wiki)/333 | None |
| 32 | 13 | 1 | 9 years ago | [vSPI](https://github.com/mjlyons/vSPI)/334 | Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter |
| 32 | 15 | 1 | 2 years ago | [FPGA-Accelerator-for-AES-LeNet-VGG16](https://github.com/zhan6841/FPGA-Accelerator-for-AES-LeNet-VGG16)/335 | FPGA/AES/LeNet/VGG16 |
| 32 | 2 | 0 | 9 months ago | [sdram-controller](https://github.com/hdl-util/sdram-controller)/336 | Generic FPGA SDRAM controller, originally made for AS4C4M16SA |
| 32 | 13 | 4 | 1 year, 1 month ago | [i3c-slave-design](https://github.com/NXP/i3c-slave-design)/337 | MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices. |
| 32 | 11 | 0 | 1 year, 11 months ago | [csirx](https://github.com/stevenbell/csirx)/338 | Open-source CSI-2 receiver for Xilinx UltraScale parts  |
| 32 | 14 | 0 | 2 years ago | [8-bits-RISC-CPU-Verilog](https://github.com/liuqidev/8-bits-RISC-CPU-Verilog)/339 | Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。 |
| 32 | 2 | 0 | 6 years ago | [gb](https://github.com/geky/gb)/340 | The Original Nintendo Gameboy in Verilog |
| 32 | 11 | 0 | 1 year, 1 month ago | [LUTNet](https://github.com/awai54st/LUTNet)/341 | None |
| 32 | 13 | 0 | 8 years ago | [fpganes](https://github.com/jpwright/fpganes)/342 | FPGA-based AI for Super Mario Bros. Designed for an Altera DE2 |
| 32 | 13 | 0 | 1 year, 2 months ago | [MIPS-Processor](https://github.com/neelkshah/MIPS-Processor)/343 | 5-stage pipelined 32-bit MIPS microprocessor in Verilog |
| 32 | 13 | 1 | 2 years ago | [ARM-LEGv8](https://github.com/nxbyte/ARM-LEGv8)/344 | Verilog Implementation of an ARM LEGv8 CPU |
| 31 | 24 | 4 | 3 months ago | [Menu_MiSTer](https://github.com/MiSTer-devel/Menu_MiSTer)/345 | None |
| 31 | 8 | 0 | 1 year, 10 months ago | [tiny-tpu](https://github.com/cameronshinn/tiny-tpu)/346 | Small-scale Tensor Processing Unit built on an FPGA |
| 31 | 6 | 0 | 3 years ago | [OpenFPGA](https://github.com/haojunliu/OpenFPGA)/347 | OpenFPGA |
| 31 | 21 | 1 | 3 years ago | [fpga_design](https://github.com/jiaowushuang/fpga_design)/348 | 这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统 |
| 31 | 17 | 0 | 9 years ago | [verilog-sha256](https://github.com/rnz/verilog-sha256)/349 | Implementation of the SHA256 Algorithm in Verilog |
| 31 | 3 | 3 | 1 year, 1 month ago | [observer](https://github.com/olofk/observer)/350 | None |
| 31 | 5 | 0 | 5 months ago | [sdr](https://github.com/ZipCPU/sdr)/351 | A basic Soft(Gate)ware Defined Radio architecture |
| 31 | 19 | 1 | 2 years ago | [GnuRadar](https://github.com/rseal/GnuRadar)/352 | Open-source software defined radar based on the USRP 1 hardware. |
| 31 | 3 | 6 | 4 months ago | [QuokkaEvaluation](https://github.com/EvgenyMuryshkin/QuokkaEvaluation)/353 | Example projects for Quokka FPGA toolkit |
| 31 | 19 | 7 | 11 days ago | [Template_MiSTer](https://github.com/MiSTer-devel/Template_MiSTer)/354 | Template with latest framework for MiSTer |
| 31 | 11 | 0 | a month ago | [sha1](https://github.com/secworks/sha1)/355 | Verilog implementation of the SHA-1 cryptgraphic hash function |
| 31 | 2 | 1 | 2 years ago | [icebreaker-candy](https://github.com/kbob/icebreaker-candy)/356 | Eye candy from an iCEBreaker FPGA and a 64×64 LED panel |
| 31 | 24 | 0 | 3 years ago | [Examples-in-book-write-your-own-cpu](https://github.com/Z-Y00/Examples-in-book-write-your-own-cpu)/357 | 《自己动手写CPU》一书附带的文件   |
| 30 | 14 | 0 | 3 years ago | [eddr3](https://github.com/Elphel/eddr3)/358 | mirror of https://git.elphel.com/Elphel/eddr3 |
| 30 | 9 | 0 | 6 years ago | [vj-uart](https://github.com/binary-logic/vj-uart)/359 | Virtual JTAG UART for Altera Devices |
| 30 | 13 | 3 | 3 years ago | [Processor-UVM-Verification](https://github.com/gupta409/Processor-UVM-Verification)/360 | System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment |
| 30 | 5 | 2 | 1 year, 5 months ago | [datc_robust_design_flow](https://github.com/jinwookjungs/datc_robust_design_flow)/361 | DATC Robust Design Flow. |
| 30 | 4 | 0 | 13 days ago | [snark-barker-mca](https://github.com/schlae/snark-barker-mca)/362 | A Sound Blaster compatible sound card for Micro Channel bus computers |
| 30 | 11 | 0 | 1 year, 4 months ago | [SIGMA](https://github.com/georgia-tech-synergy-lab/SIGMA)/363 | RTL implementation of Flex-DPE. |
| 30 | 8 | 39 | 2 months ago | [mantle](https://github.com/phanrahan/mantle)/364 | mantle library |
| 30 | 13 | 1 | 1 year, 7 months ago | [Open_RegModel](https://github.com/zhajio1988/Open_RegModel)/365 | :hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL. |
| 30 | 13 | 2 | 3 years ago | [CNN_VGG19_verilog](https://github.com/romulus0914/CNN_VGG19_verilog)/366 | Convolution Neural Network of vgg19 model in verilog |
| 30 | 10 | 0 | a month ago | [MangoMIPS32](https://github.com/RickyTino/MangoMIPS32)/367 | A softcore microprocessor of MIPS32 architecture. |
| 29 | 4 | 1 | 8 months ago | [zbasic](https://github.com/ZipCPU/zbasic)/368 | A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems |
| 29 | 2 | 0 | 2 years ago | [riscv-megaproject](https://github.com/rongcuid/riscv-megaproject)/369 | A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones |
| 29 | 9 | 4 | 1 year, 4 months ago | [A500-8MB-FastRAM](https://github.com/kr239/A500-8MB-FastRAM)/370 | 8MB FastRAM Board for the Amiga 500 & Amiga 500+ |
| 29 | 50 | 1 | a month ago | [iob-soc](https://github.com/IObundle/iob-soc)/371 | RISC-V System on Chip Template Based on the picorv32 Processor |
| 29 | 8 | 0 | 10 months ago | [RDF-2019](https://github.com/ieee-ceda-datc/RDF-2019)/372 | DATC RDF |
| 29 | 6 | 0 | 9 months ago | [Solutions-to-HDLbits-Verilog-sets](https://github.com/jeremy-shi/Solutions-to-HDLbits-Verilog-sets)/373 | Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).  |
| 29 | 13 | 2 | 11 years ago | [round_robin_arbiter](https://github.com/freecores/round_robin_arbiter)/374 | round robin arbiter |
| 29 | 34 | 0 | 7 years ago | [FPGA_image_processing](https://github.com/suntodai/FPGA_image_processing)/375 | Image capture, image filtering and image display (VGA) : picture in picture, edge detection, gray image and smooth image |
| 29 | 18 | 0 | 2 years ago | [x393](https://github.com/Elphel/x393)/376 | mirror of https://git.elphel.com/Elphel/x393 |
| 29 | 12 | 1 | 1 year, 4 months ago | [Tang-Nano-examples](https://github.com/sipeed/Tang-Nano-examples)/377 | Tang-Nano-examples |
| 29 | 4 | 1 | 21 days ago | [A500_ACCEL_RAM_IDE-Rev-2](https://github.com/PR77/A500_ACCEL_RAM_IDE-Rev-2)/378 | Improved design attempt for Amiga 500 in socket 68000 Accelerator, FastRAM and IDE Interface  |
| 29 | 7 | 2 | 2 years ago | [iCEstick-UART-Demo](https://github.com/cyrozap/iCEstick-UART-Demo)/379 | This is a simple UART echo test for the iCEstick Evaluation Kit |
| 29 | 3 | 1 | 4 years ago | [RISCV_Piccolo_v1](https://github.com/rsnikhil/RISCV_Piccolo_v1)/380 | Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore). |
| 29 | 17 | 0 | 2 years ago | [de10nano_vgaHdmi_chip](https://github.com/nhasbun/de10nano_vgaHdmi_chip)/381 | Test for video output using the ADV7513 chip on a de10 nano board |
| 29 | 8 | 0 | 13 hours ago | [jtframe](https://github.com/jotego/jtframe)/382 | Common framework for MiST(er), SiDi, ZX-UNO/DOS and Unamiga core development. With special focus on arcade cores. |
| 29 | 5 | 0 | 1 year, 4 months ago | [icestick-glitcher](https://github.com/SySS-Research/icestick-glitcher)/383 | Simple voltage glitcher implementation for the Lattice iCEstick Evaluation Kit |
| 29 | 3 | 0 | 7 years ago | [CPU32](https://github.com/kazunori279/CPU32)/384 | Tiny MIPS for Terasic DE0 |
| 28 | 9 | 0 | 8 years ago | [lsasim](https://github.com/dwelch67/lsasim)/385 | Educational load/store instruction set architecture processor simulator |
| 28 | 3 | 0 | 3 years ago | [s6soc](https://github.com/ZipCPU/s6soc)/386 | CMod-S6 SoC |
| 28 | 12 | 2 | 26 days ago | [xfcp](https://github.com/alexforencich/xfcp)/387 | Extensible FPGA control platform |
| 28 | 13 | 1 | 3 years ago | [openmsp430](https://github.com/olgirard/openmsp430)/388 | The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. |
| 28 | 12 | 0 | 5 years ago | [stx_cookbook](https://github.com/thomasrussellmurphy/stx_cookbook)/389 | Altera Advanced Synthesis Cookbook 11.0 |
| 28 | 5 | 0 | 7 days ago | [SiDi-FPGA](https://github.com/ManuFerHi/SiDi-FPGA)/390 | SiDi FPGA for retro systems. |
| 28 | 7 | 5 | 6 months ago | [icestick-lpc-tpm-sniffer](https://github.com/SySS-Research/icestick-lpc-tpm-sniffer)/391 | FPGA-based LPC bus sniffing tool for Lattice iCEstick Evaluation Kit |
| 28 | 16 | 2 | 8 months ago | [ARM9-compatible-soft-CPU-core](https://github.com/risclite/ARM9-compatible-soft-CPU-core)/392 | This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz.  It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file.  This IP core is very compact. It is one .v file and has only less 1800 lines. |
| 28 | 22 | 0 | 8 years ago | [opensketch](https://github.com/harvard-cns/opensketch)/393 | simulation and netfpga code |
| 28 | 1 | 0 | 1 year, 5 months ago | [cisco-hwic-3g-cdma](https://github.com/tomverbeure/cisco-hwic-3g-cdma)/394 | Reverse Engineering of the Cisco HWIC-3G-CDMA PCB |
| 27 | 15 | 0 | 4 years ago | [HitchHike](https://github.com/pengyuzhang/HitchHike)/395 | None |
| 27 | 21 | 0 | 4 years ago | [fast](https://github.com/FAST-Switch/fast)/396 | FAST |
| 27 | 17 | 2 | 4 years ago | [Hardware-Implementation-of-AES-Verilog](https://github.com/pnvamshi/Hardware-Implementation-of-AES-Verilog)/397 | Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog |
| 27 | 5 | 1 | 2 years ago | [Lichee-Tang](https://github.com/piotr-go/Lichee-Tang)/398 | Lichee Tang FPGA board examples |
| 27 | 9 | 2 | 2 years ago | [Posit-HDL-Arithmetic](https://github.com/manish-kj/Posit-HDL-Arithmetic)/399 | Universal number Posit HDL Arithmetic Architecture generator |
| 27 | 7 | 0 | 7 years ago | [LVDS-7-to-1-Serializer](https://github.com/racerxdl/LVDS-7-to-1-Serializer)/400 | An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens. |
| 27 | 4 | 1 | 4 months ago | [vga-clock](https://github.com/mattvenn/vga-clock)/401 | None |
| 27 | 13 | 0 | 1 year, 7 months ago | [spi_mem_programmer](https://github.com/sergachev/spi_mem_programmer)/402 | Small (Q)SPI flash memory programmer in Verilog |
| 27 | 18 | 0 | 9 years ago | [tdc-core](https://github.com/m-labs/tdc-core)/403 | A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs |
| 27 | 10 | 0 | 3 years ago | [Spartan-Mini-NES](https://github.com/jonthomasson/Spartan-Mini-NES)/404 | An FPGA based handheld NES system built around the Spartan 6 and the Spartan Mini development board. |
| 27 | 5 | 3 | 2 years ago | [v-regex](https://github.com/shellbear/v-regex)/405 |  A simple regex library for V |
| 27 | 22 | 0 | 5 years ago | [AES-FPGA](https://github.com/mematrix/AES-FPGA)/406 | AES加密解密算法的Verilog实现 |
| 27 | 31 | 0 | 4 months ago | [jtag_vpi](https://github.com/fjullien/jtag_vpi)/407 | TCP/IP controlled VPI JTAG Interface. |
| 27 | 7 | 0 | 8 months ago | [avr](https://github.com/aman-goel/avr)/408 | Reads a state transition system and performs property checking |
| 27 | 16 | 0 | 8 years ago | [rfid-verilog](https://github.com/wisp/rfid-verilog)/409 | RFID tag and tester in Verilog |
| 27 | 9 | 0 | 2 years ago | [Open-FPGA](https://github.com/NingHeChuan/Open-FPGA)/410 | Devotes to open source FPGA |
| 26 | 8 | 0 | 6 months ago | [myslides](https://github.com/Obijuan/myslides)/411 | Collection of my presentations |
| 26 | 5 | 0 | 3 months ago | [verilog-65C02](https://github.com/Arlet/verilog-65C02)/412 | 65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface |
| 26 | 13 | 0 | 5 years ago | [FPGA_Ultrasound](https://github.com/waynezv/FPGA_Ultrasound)/413 |  CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system. |
| 26 | 2 | 4 | 1 year, 8 months ago | [quark](https://github.com/drom/quark)/414 | Stack CPU :construction: Work In Progress :construction: |
| 26 | 5 | 0 | 1 year, 1 month ago | [HDMI-to-FPGA-to-APA102-Pixels](https://github.com/hydronics2/HDMI-to-FPGA-to-APA102-Pixels)/415 | Final Project written in Lucid (verilog) for the Mojo FPGA development board. Reads pixels from HDMI and sends pixel data to 22,000 APA102 LEDs over SPI. |
| 26 | 17 | 5 | 2 years ago | [ODIN](https://github.com/ChFrenkel/ODIN)/416 | ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation. |
| 26 | 16 | 1 | 4 years ago | [Propeller_1_Design](https://github.com/parallaxinc/Propeller_1_Design)/417 | Propeller 1 design and example files to be run on FPGA boards. |
| 26 | 15 | 0 | a month ago | [Video-and-Image-Processing-Design-Using-FPGAs](https://github.com/cuongtvee/Video-and-Image-Processing-Design-Using-FPGAs)/418 | Video and Image Processing |
| 26 | 6 | 0 | 7 months ago | [jt49](https://github.com/jotego/jt49)/419 | Verilog clone of YM2149 |
| 26 | 15 | 20 | 4 years ago | [RetroCade_Synth](https://github.com/GadgetFactory/RetroCade_Synth)/420 | RetroCade Synth - C64 SID, YM2149, and POKEY audio chips with MIDI interface.  |
| 26 | 9 | 3 | 4 years ago | [Nitro-Parts-lib-Xilinx](https://github.com/dirjud/Nitro-Parts-lib-Xilinx)/421 | This is mainly a simulation library of xilinx primitives that are verilator compatible. |
| 26 | 8 | 0 | 1 year, 9 months ago | [core_audio](https://github.com/ultraembedded/core_audio)/422 | Audio controller (I2S, SPDIF, DAC) |
| 26 | 5 | 0 | 2 years ago | [snes_dejitter](https://github.com/marqs85/snes_dejitter)/423 | NES/SNES 240p de-jitter mod |
| 25 | 6 | 0 | a month ago | [fftdemo](https://github.com/ZipCPU/fftdemo)/424 | A demonstration showing how several components can be compsed to build a simulated spectrogram |
| 25 | 17 | 0 | 6 years ago | [yafpgatetris](https://github.com/johan92/yafpgatetris)/425 | Yet Another Tetris on FPGA Implementation |
| 25 | 14 | 0 | 10 years ago | [dma_axi](https://github.com/freecores/dma_axi)/426 | AXI DMA 32 / 64 bits |
| 25 | 8 | 1 | 2 months ago | [riscv-soc-cores](https://github.com/open-design/riscv-soc-cores)/427 | None |
| 25 | 26 | 2 | 1 year, 9 months ago | [block-nvdla-sifive](https://github.com/sifive/block-nvdla-sifive)/428 | None |
| 25 | 8 | 1 | 2 years ago | [Basic-SIMD-Processor-Verilog-Tutorial](https://github.com/zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial)/429 | Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit. |
| 25 | 16 | 1 | 1 year, 1 month ago | [fifo](https://github.com/olofk/fifo)/430 | Generic FIFO implementation with optional FWFT |
| 25 | 12 | 0 | 11 years ago | [jpegencode](https://github.com/freecores/jpegencode)/431 | JPEG Encoder Verilog |
| 25 | 4 | 0 | 7 months ago | [VirtualTap](https://github.com/furrtek/VirtualTap)/432 | Mod kit for the Virtual Boy to make it output VGA or RGB video |
| 25 | 15 | 0 | 10 years ago | [sparc64soc](https://github.com/freecores/sparc64soc)/433 | OpenSPARC-based SoC |
| 25 | 8 | 0 | 11 years ago | [osdvu](https://github.com/cyrozap/osdvu)/434 | None |
| 25 | 3 | 0 | 10 months ago | [nintendo-switch-i2s-to-spdif](https://github.com/puhitaku/nintendo-switch-i2s-to-spdif)/435 | I2S to S/PDIF conversion on SiPeed Tang Nano (GOWIN GW1N-LV1) which aims to convert Nintendo Switch's internal I2S signal. |
| 25 | 9 | 0 | 4 years ago | [book-examples](https://github.com/embmicro/book-examples)/436 | None |
| 25 | 14 | 1 | 5 months ago | [FAST9-Accelerator](https://github.com/ISKU/FAST9-Accelerator)/437 | FAST-9 Accelerator for Corner Detection |
| 25 | 5 | 1 | 6 years ago | [Y86-CPU](https://github.com/Archstacker/Y86-CPU)/438 | A pipeline CPU in Verilog for the Y86 instruction set. |
| 25 | 3 | 0 | 1 year, 1 month ago | [HW-Syn-Lab](https://github.com/tongplw/HW-Syn-Lab)/439 | ⚙Hardware Synthesis Laboratory Using Verilog |
| 25 | 9 | 0 | 5 months ago | [qspiflash](https://github.com/ZipCPU/qspiflash)/440 | A set of Wishbone Controlled SPI Flash Controllers |
| 25 | 13 | 1 | 7 years ago | [ddk-fpga](https://github.com/ddk/ddk-fpga)/441 | FPGA HDL Sources. |
| 25 | 11 | 0 | a month ago | [chacha](https://github.com/secworks/chacha)/442 | Verilog 2001 implementation of the ChaCha stream cipher. |
| 24 | 6 | 0 | 7 years ago | [aoOCS](https://github.com/alfikpl/aoOCS)/443 | The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.  |
| 24 | 10 | 1 | 1 year, 11 months ago | [HDL-Bits-Solutions](https://github.com/viduraakalanka/HDL-Bits-Solutions)/444 | This is a repository containing solutions to the problem statements given in HDL Bits website. |
| 24 | 10 | 1 | 4 years ago | [ocpi](https://github.com/ShepardSiegel/ocpi)/445 | Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo! |
| 24 | 10 | 0 | 9 years ago | [Pong](https://github.com/bogini/Pong)/446 | Pong game on an FPGA in Verilog. |
| 24 | 4 | 2 | 4 months ago | [ThymesisFlow](https://github.com/OpenCAPI/ThymesisFlow)/447 | Memory Disaggregation on POWER9 with OpenCAPI |
| 24 | 6 | 0 | 1 year, 7 months ago | [hackaday_supercon_2019_logic_noise_FPGA_workshop](https://github.com/hexagon5un/hackaday_supercon_2019_logic_noise_FPGA_workshop)/448 | Hackaday Supercon 2019 Logic Noise Badge Workshop |
| 24 | 11 | 1 | 7 months ago | [ARM_Cortex-M3](https://github.com/Qirun/ARM_Cortex-M3)/449 | 该项目依据全国大学生集成电路创新创业大赛“ARM杯”赛题要求，在FPGA上搭建Cortex-M3软核、图像协处理器，并通过OV5640摄像头采集车牌图像，实现对车牌的识别与结果显示。项目基于Altera DE1 FPGA搭载Cortex-M3软核，依据AHB-Lite总线协议，将LCD1602、RAM、图像协处理器等外设挂载至Cortex-M3。视频采集端，设计写FiFo模块、SDRAM存储与输出、读FiFo模块、灰度处理模块、二值化、VGA显示等模块。最终将400位宽的结果数据（对应20张车牌）存储在RAM中，输出至AHB总线，由Cortex-M3调用并显示识别结果。 |
| 24 | 10 | 2 | 2 years ago | [Parser-Verilog](https://github.com/OpenTimer/Parser-Verilog)/450 | A Standalone Structural Verilog Parser |
| 24 | 20 | 7 | 6 years ago | [MM](https://github.com/Canaan-Creative/MM)/451 | Miner Manager |
| 24 | 16 | 0 | 1 year, 6 months ago | [TPU-Tensor-Processing-Unit](https://github.com/leo47007/TPU-Tensor-Processing-Unit)/452 | IC implementation of TPU |
| 24 | 11 | 0 | 2 years ago | [workshops](https://github.com/FPGAwars/workshops)/453 | :snowflake: :star2: Workshops with Icestudio and the IceZUM Alhambra board |
| 24 | 9 | 16 | a day ago | [DFFRAM](https://github.com/Cloud-V/DFFRAM)/454 | Standard Cell Library based Memory Compiler using DFF cells |
| 24 | 13 | 0 | 4 years ago | [peridot](https://github.com/osafune/peridot)/455 | 'PERIDOT' - Simple & Compact FPGA board |
| 24 | 20 | 0 | 13 years ago | [xge_mac](https://github.com/freecores/xge_mac)/456 | Ethernet 10GE MAC |
| 24 | 3 | 3 | 2 years ago | [time-sleuth](https://github.com/chriz2600/time-sleuth)/457 | Time Sleuth - Open Source Lag Tester |
| 24 | 8 | 0 | 1 year, 6 months ago | [Uranus](https://github.com/ustb-owl/Uranus)/458 | Uranus MIPS processor by MaxXing & USTB NSCSCC team |
| 24 | 9 | 0 | 2 years ago | [verilog-mini-demo](https://github.com/ic7x24/verilog-mini-demo)/459 | Verilog极简教程 |
| 23 | 5 | 0 | 3 years ago | [bapi-rv32i](https://github.com/rgwan/bapi-rv32i)/460 | A extremely size-optimized RV32I soft processor for FPGA. |
| 23 | 22 | 1 | 1 year, 8 months ago | [LimeSDR-PCIe_GW](https://github.com/myriadrf/LimeSDR-PCIe_GW)/461 | Altera Cyclone IV FPGA project for the PCIe LimeSDR board  |
| 23 | 7 | 0 | 9 years ago | [aemb](https://github.com/aeste/aemb)/462 | Multi-threaded 32-bit embedded core family. |
| 23 | 11 | 0 | 3 months ago | [Icarus_Verilog](https://github.com/SinghCoder/Icarus_Verilog)/463 | This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum |
| 23 | 15 | 0 | 3 years ago | [H264](https://github.com/aiminickwong/H264)/464 | H264视频解码verilog实现 |
| 23 | 3 | 0 | 1 year, 1 month ago | [EDSAC](https://github.com/hrvach/EDSAC)/465 | FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope |
| 23 | 5 | 0 | 7 months ago | [litex_vexriscv_smp](https://github.com/enjoy-digital/litex_vexriscv_smp)/466 | Test with LiteX and VexRiscv SMP |
| 23 | 2 | 0 | 6 months ago | [PCI2Nano-PCB](https://github.com/defparam/PCI2Nano-PCB)/467 | An FPGA/PCI Device Reference Platform |
| 23 | 15 | 0 | 2 years ago | [Open-CryptoNight-ASIC](https://github.com/altASIC/Open-CryptoNight-ASIC)/468 | Open source hardware implementation of classic CryptoNight |
| 22 | 11 | 0 | 7 months ago | [verilog-osx](https://github.com/kehribar/verilog-osx)/469 | Barerbones OSX based Verilog simulation toolchain. |
| 22 | 2 | 0 | 5 years ago | [literate-broccoli](https://github.com/ueliem/literate-broccoli)/470 | An open source FPGA architecture |
| 22 | 0 | 0 | 6 months ago | [cxxrtl_eval](https://github.com/tomverbeure/cxxrtl_eval)/471 | Experiments with Yosys cxxrtl backend |
| 22 | 14 | 0 | 4 years ago | [FFT_Verilog](https://github.com/DexWen/FFT_Verilog)/472 | FFT implement by verilog_测试验证已通过 |
| 22 | 14 | 0 | 6 months ago | [vsdmixedsignalflow](https://github.com/praharshapm/vsdmixedsignalflow)/473 | This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools. |
| 22 | 3 | 0 | 2 years ago | [thunderclap-fpga-arria10](https://github.com/thunderclap-io/thunderclap-fpga-arria10)/474 | Thunderclap hardware for Intel Arria 10 FPGA |
| 22 | 12 | 0 | 4 years ago | [SVM-Gaussian-Classification-FPGA](https://github.com/arpanvyas/SVM-Gaussian-Classification-FPGA)/475 | SVM Gaussian Classifier of 30x30 greyscale image on Verilog |
| 22 | 4 | 1 | 3 years ago | [Verilog-VGA-game](https://github.com/Wujh1995/Verilog-VGA-game)/476 | A simple game written in Verilog HDL language and display on the VGA screen. |
| 22 | 11 | 0 | 9 months ago | [Booth_Multipliers](https://github.com/MorrisMA/Booth_Multipliers)/477 | Parameterized Booth Multiplier in Verilog 2001 |
| 22 | 17 | 1 | 5 years ago | [Nitro-Parts-lib-SPI](https://github.com/dirjud/Nitro-Parts-lib-SPI)/478 | Verilog SPI master and slave |
| 22 | 12 | 0 | 4 years ago | [ee260_lab](https://github.com/sheldonucr/ee260_lab)/479 | EE 260 Winter 2017: Advanced VLSI Design |
| 22 | 8 | 1 | 1 year, 4 months ago | [SDR-Micron](https://github.com/Dfinitski/SDR-Micron)/480 | SDR Micron USB receiver |
| 22 | 15 | 1 | 3 years ago | [nysa-verilog](https://github.com/CospanDesign/nysa-verilog)/481 | Verilog Repository for GIT |
| 22 | 9 | 1 | 5 years ago | [mipscpu](https://github.com/patc15/mipscpu)/482 | Fully pipelined MIPS CPU in Verilog/SystemVerilog with advanced branch prediction, register renaming, and value prediction |
| 22 | 6 | 0 | 2 years ago | [MIPS-Verilog](https://github.com/silverfoxy/MIPS-Verilog)/483 | MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board. |
| 22 | 8 | 0 | 9 years ago | [tinycpu](https://github.com/fallen/tinycpu)/484 | Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes. |
| 22 | 7 | 1 | 10 days ago | [VGA1306](https://github.com/uXeBoy/VGA1306)/485 | VGA1306 (VGA-out for DIY Arduboys implemented on an FPGA!) |
| 22 | 6 | 0 | 1 year, 11 days ago | [iverilog-tutorial](https://github.com/albertxie/iverilog-tutorial)/486 | Quickstart guide on Icarus Verilog. |
| 22 | 12 | 0 | 1 year, 1 month ago | [verilog-arbiter](https://github.com/bmartini/verilog-arbiter)/487 | A look ahead, round-robing parametrized arbiter written in Verilog. |
| 22 | 7 | 0 | 8 years ago | [usb-de2-fpga](https://github.com/mzakharo/usb-de2-fpga)/488 | Hardware interface for USB controller on DE2 FPGA Platform |
| 22 | 16 | 1 | 3 years ago | [Design-and-Verification-of-LDPC-Decoder](https://github.com/biren15/Design-and-Verification-of-LDPC-Decoder)/489 | - Designed the LDPC decoder in the Matlab using the min-sum approach.  - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix.  - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab. |
| 22 | 0 | 3 | 2 days ago | [MiSTery](https://github.com/gyurco/MiSTery)/490 | Atari ST/STe core for MiST |
| 21 | 4 | 0 | 9 years ago | [pdfparser](https://github.com/andreasdotorg/pdfparser)/491 | None |
| 21 | 8 | 1 | 3 years ago | [arty-glitcher](https://github.com/toothlessco/arty-glitcher)/492 | FPGA-based glitcher for the Digilent Arty FPGA development board. |
| 21 | 5 | 1 | 20 days ago | [HPS2FPGAmapping](https://github.com/robseb/HPS2FPGAmapping)/493 |  SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V) |
| 21 | 13 | 0 | 1 year, 11 months ago | [Ethernet-design-verilog](https://github.com/maxs-well/Ethernet-design-verilog)/494 | Gigabit Ethernet UDP communication driver |
| 21 | 6 | 1 | a month ago | [cpc_ram_expansion](https://github.com/revaldinho/cpc_ram_expansion)/495 | A series of Amstrad CPC PCBs including a backplane, ROM and 512K and 1MByte RAM expansions. |
| 21 | 11 | 1 | 6 years ago | [neural-hardware](https://github.com/shaneleonard/neural-hardware)/496 | Verilog library for implementing neural networks. |
| 21 | 2 | 0 | 11 months ago | [EI332](https://github.com/zengkaipeng/EI332)/497 | SJTU EI332 CPU完整实验代码及报告 |
| 21 | 2 | 0 | 22 days ago | [ZYNQ-NVDLA](https://github.com/LeiWang1999/ZYNQ-NVDLA)/498 | My Final year Project for Bachelor Degree. NVDLA implementation on FPGA. |
| 21 | 22 | 0 | 3 years ago | [SIMD-architecture](https://github.com/MatrixAINetwork/SIMD-architecture)/499 | Overall multi-core SIMD microarchitecture |
| 21 | 7 | 0 | a month ago | [Fixed-Floating-Point-Adder-Multiplier](https://github.com/suoglu/Fixed-Floating-Point-Adder-Multiplier)/500 | 16-bit Adder Multiplier hardware on Digilent Basys 3 |
| 21 | 9 | 0 | 2 years ago | [riscv_soc](https://github.com/ultraembedded/riscv_soc)/501 | Basic RISC-V Test SoC |
| 21 | 2 | 0 | 5 months ago | [PCI2Nano-RTL](https://github.com/defparam/PCI2Nano-RTL)/502 | An open source FPGA PCI core & 8250-Compatible PCI UART core |
| 21 | 6 | 0 | 13 days ago | [xschem_sky130](https://github.com/StefanSchippers/xschem_sky130)/503 | XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.  |
| 21 | 16 | 2 | 3 years ago | [up5k-demos](https://github.com/daveshah1/up5k-demos)/504 | ice40 UltraPlus demos |
| 21 | 7 | 3 | 1 year, 2 months ago | [UPduino-v2.1](https://github.com/tinyvision-ai-inc/UPduino-v2.1)/505 | UPduino |
| 21 | 4 | 0 | 2 years ago | [USB](https://github.com/pbing/USB)/506 | FPGA USB 1.1 Low-Speed Implementation |
| 21 | 2 | 11 | a month ago | [circuitgraph](https://github.com/circuitgraph/circuitgraph)/507 | Tools for working with circuits as graphs in python |
| 21 | 4 | 0 | 5 months ago | [interpolation](https://github.com/ZipCPU/interpolation)/508 | Digital Interpolation Techniques Applied to Digital Signal Processing |
| 21 | 8 | 2 | 2 months ago | [MacPlus_MiSTer](https://github.com/MiSTer-devel/MacPlus_MiSTer)/509 | Macintosh Plus for MiSTer |
| 21 | 18 | 2 | 6 years ago | [CAN-Bus-Controller](https://github.com/Tommydag/CAN-Bus-Controller)/510 | An CAN bus Controller implemented in Verilog |
| 21 | 12 | 0 | 7 years ago | [MIPS-Processor-in-Verilog](https://github.com/Caskman/MIPS-Processor-in-Verilog)/511 | Processor repo |
| 21 | 7 | 0 | 1 year, 10 months ago | [PACoGen](https://github.com/manish-kj/PACoGen)/512 | PACoGen: Posit Arithmetic Core Generator |
| 21 | 10 | 0 | 5 years ago | [CPU](https://github.com/ruanshihai/CPU)/513 | Verilog实现的简单五级流水线CPU，开发平台：Nexys3 |
| 21 | 3 | 1 | 2 years ago | [fpga-virtual-graf](https://github.com/mattvenn/fpga-virtual-graf)/514 | None |
| 21 | 14 | 1 | 6 years ago | [8051](https://github.com/lajanugen/8051)/515 | FPGA implementation of the 8051 Microcontroller (Verilog) |
| 20 | 10 | 2 | 15 years ago | [can](https://github.com/freecores/can)/516 | CAN Protocol Controller |
| 20 | 2 | 2 | 9 months ago | [OpenSERDES](https://github.com/SparcLab/OpenSERDES)/517 | Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology. |
| 20 | 4 | 2 | 2 years ago | [recon](https://github.com/jefflieu/recon)/518 | The RECON project creates library for Nios II Microcontroller System and Tool chain. The library includes a collection of hardware configurations and Arduino-style software APIs. |
| 20 | 10 | 12 | 11 months ago | [nanorv32](https://github.com/rbarzic/nanorv32)/519 | A small 32-bit implementation of the RISC-V architecture |
| 20 | 8 | 0 | 3 years ago | [LeNet_RTL](https://github.com/yztong/LeNet_RTL)/520 | An LeNet RTL implement onto FPGA |
| 20 | 2 | 0 | 1 year, 1 month ago | [Colorlight-5A-75B](https://github.com/kholia/Colorlight-5A-75B)/521 | Notes for Colorlight-5A-75B. |
| 20 | 13 | 0 | 10 years ago | [dma_ahb](https://github.com/freecores/dma_ahb)/522 | AHB DMA 32 / 64 bits |
| 20 | 13 | 0 | 3 years ago | [usb2_dev](https://github.com/www-asics-ws/usb2_dev)/523 | USB 2.0 Device IP Core |
| 20 | 11 | 0 | 8 years ago | [ovs-hw](https://github.com/sora/ovs-hw)/524 | An open source hardware engine for Open vSwitch on FPGA |
| 20 | 4 | 0 | 2 years ago | [fpga-examples](https://github.com/sehugg/fpga-examples)/525 | FPGA examples for 8bitworkshop.com |
| 20 | 23 | 3 | 2 months ago | [ZX-Spectrum_MISTer](https://github.com/MiSTer-devel/ZX-Spectrum_MISTer)/526 | None |
| 20 | 2 | 0 | 2 years ago | [gameduino-fpga-mods](https://github.com/toivoh/gameduino-fpga-mods)/527 | Mods of the FPGA code from @jamesbowman's Gameduino file repository |
| 20 | 4 | 0 | 6 months ago | [Async-Karin](https://github.com/Mario-Hero/Async-Karin)/528 | Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board. |
| 20 | 2 | 0 | 2 years ago | [enigmaFPGA](https://github.com/mmicko/enigmaFPGA)/529 | Enigma in FPGA |
| 20 | 5 | 0 | 2 years ago | [redpid](https://github.com/quartiq/redpid)/530 | migen + misoc + redpitaya = digital servo |
| 20 | 7 | 1 | 6 years ago | [azpr_cpu](https://github.com/zhangly/azpr_cpu)/531 | 用Altera FPGA芯片自制CPU |
| 20 | 7 | 0 | 6 days ago | [Vision-FPGA-SoM](https://github.com/tinyvision-ai-inc/Vision-FPGA-SoM)/532 | tinyVision.ai Vision & Sensor FPGA System on Module |
| 20 | 19 | 3 | 3 years ago | [Cosmos-OpenSSD](https://github.com/Cosmos-OpenSSD/Cosmos-OpenSSD)/533 | None |
| 20 | 18 | 2 | 8 months ago | [blake2](https://github.com/secworks/blake2)/534 | Hardware implementation of the blake2 hash function |
| 20 | 7 | 1 | 6 years ago | [ws2812-verilog](https://github.com/dhrosa/ws2812-verilog)/535 | This is a Verilog module to interface with WS2812-based LED strips. |
| 20 | 2 | 0 | 6 years ago | [BCOpenMIPS](https://github.com/binderclip/BCOpenMIPS)/536 | 跟着《自己动手写 CPU》书上写的 OpenMIPS CPU。 |
| 20 | 5 | 0 | 2 months ago | [ctfs](https://github.com/5unKn0wn/ctfs)/537 | ctfs write-up |
| 20 | 1 | 0 | 1 year, 6 months ago | [BusPirateUltraHDL](https://github.com/DangerousPrototypes/BusPirateUltraHDL)/538 | Verilog for the Bus Pirate Ultra FPGA |
| 20 | 7 | 2 | 2 years ago | [buffets](https://github.com/cwfletcher/buffets)/539 | Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration. |
| 20 | 6 | 0 | 1 year, 2 months ago | [Computer-Experiment-on-the-principle-of-computer-composition](https://github.com/hjs557523/Computer-Experiment-on-the-principle-of-computer-composition)/540 | 杭电计算机学院-《计算机组成原理》上机实验代码工程文件 |
| 20 | 18 | 10 | 1 year, 1 month ago | [UHD-Fairwaves](https://github.com/fairwaves/UHD-Fairwaves)/541 | Fairwaves version of the UHD drivers, tweaked to support Fairwaves UmTRX.  |
| 20 | 6 | 0 | 4 years ago | [Yoshis-Nightmare](https://github.com/jconenna/Yoshis-Nightmare)/542 | FPGA Based Platformer Video Game |
| 20 | 6 | 0 | 1 year, 18 days ago | [picorv32_Xilinx](https://github.com/cjhonlyone/picorv32_Xilinx)/543 | A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz  |
| 20 | 19 | 0 | 7 years ago | [RSA4096](https://github.com/fatestudio/RSA4096)/544 | 4096bit RSA project, with verilog code, python test code, etc |
| 20 | 14 | 0 | 1 year, 1 month ago | [x393_sata](https://github.com/Elphel/x393_sata)/545 | mirror of https://git.elphel.com/Elphel/x393_sata |
| 20 | 3 | 3 | a day ago | [OpenCGRA](https://github.com/pnnl/OpenCGRA)/546 | OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs. |
| 20 | 15 | 1 | 9 months ago | [NandFlashController](https://github.com/cjhonlyone/NandFlashController)/547 | AXI Interface Nand Flash Controller (Sync mode) |
| 20 | 13 | 1 | 1 year, 1 month ago | [Pepino](https://github.com/Saanlima/Pepino)/548 | None |
| 20 | 5 | 0 | 3 months ago | [Bluster](https://github.com/LIV2/Bluster)/549 | CPLD Replacement for A2000 Buster |
| 20 | 12 | 0 | 4 years ago | [4-way-set-associative-cache-verilog](https://github.com/rajshadow/4-way-set-associative-cache-verilog)/550 | Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy |
| 20 | 5 | 0 | 2 months ago | [Pet2001_Nexys3](https://github.com/skibo/Pet2001_Nexys3)/551 | A Commodore PET in an FPGA. |
| 20 | 1 | 0 | 5 months ago | [MIPS54SP-Lifesaver](https://github.com/4x10msv/MIPS54SP-Lifesaver)/552 | None |
| 20 | 17 | 0 | 6 years ago | [Open-Source-Network-on-Chip-Router-RTL](https://github.com/anan-cn/Open-Source-Network-on-Chip-Router-RTL)/553 | None |
| 20 | 4 | 0 | 20 days ago | [notary](https://github.com/anishathalye/notary)/554 | Notary: A Device for Secure Transaction Approval 📟 |
| 19 | 15 | 0 | a month ago | [sha512](https://github.com/secworks/sha512)/555 | Verilog implementation of the SHA-512 hash function. |
| 19 | 6 | 1 | 3 years ago | [UPDuino-OV7670-Camera](https://github.com/gtjennings1/UPDuino-OV7670-Camera)/556 | Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module |
| 19 | 14 | 1 | 7 years ago | [turbo8051](https://github.com/freecores/turbo8051)/557 | turbo 8051 |
| 19 | 7 | 0 | 8 years ago | [riscv-invicta](https://github.com/qmn/riscv-invicta)/558 | A simple RISC-V core, described with Verilog |
| 19 | 3 | 2 | 2 months ago | [StereoCensus](https://github.com/slongfield/StereoCensus)/559 | Verilog Implementation of the Census Transform Stereo Vision algorithm |
| 19 | 8 | 0 | 5 years ago | [Make-FPGA](https://github.com/tritechpw/Make-FPGA)/560 | Repository of Verilog code for Make:FPGA book Chapters 2 & 3. |
| 19 | 14 | 0 | 2 years ago | [face_detect_open](https://github.com/lulinchen/face_detect_open)/561 | A Voila-Jones face detector hardware implementation |
| 19 | 5 | 9 | 9 years ago | [hdl_devel](https://github.com/casper-astro/hdl_devel)/562 | A new CASPER toolflow based on an HDL primitives library |
| 19 | 9 | 0 | 1 year, 1 month ago | [00_Image_Rotate](https://github.com/WayneGong/00_Image_Rotate)/563 | 视频旋转（2019FPGA大赛） |
| 19 | 7 | 1 | 8 years ago | [fpgaminer-vanitygen](https://github.com/fpgaminer/fpgaminer-vanitygen)/564 | Open Source Bitcoin Vanity Address Generation on FPGAs |
| 19 | 2 | 0 | 1 year, 2 months ago | [dbgbus](https://github.com/ZipCPU/dbgbus)/565 | A collection of debugging busses developed and presented at zipcpu.com |
| 19 | 3 | 0 | 9 months ago | [serv_soc](https://github.com/DaveBerkeley/serv_soc)/566 | SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash. |
| 19 | 2 | 0 | 2 years ago | [verifla](https://github.com/wd5gnr/verifla)/567 | Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm |
| 19 | 8 | 0 | 5 years ago | [CoCo3FPGA](https://github.com/richard42/CoCo3FPGA)/568 | FPGA implementation of the TRS-80 Color Computer 3 in Verilog, by Gary Becker et al. |
| 19 | 9 | 0 | 13 days ago | [uart](https://github.com/ben-marshall/uart)/569 | A simple implementation of a UART modem in Verilog. |
| 19 | 11 | 0 | 2 years ago | [trainwreck](https://github.com/aswaterman/trainwreck)/570 | Original RISC-V 1.0 implementation.  Not supported. |
| 19 | 6 | 0 | 1 year, 7 months ago | [tinyfpga_examples](https://github.com/lawrie/tinyfpga_examples)/571 | Verilog example programs for TinyFPGA |
| 19 | 16 | 0 | 3 months ago | [computer-organization-lab](https://github.com/Jed-Z/computer-organization-lab)/572 | 中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU |
| 19 | 31 | 0 | 3 years ago | [sata3_host_controller](https://github.com/CoreyChen922/sata3_host_controller)/573 | It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface. |
| 19 | 2 | 1 | 5 years ago | [icestick-vga-test](https://github.com/SubProto/icestick-vga-test)/574 | Test of ICEstick PLL usage with Yosys/Arachne-PNR/Icetools |
| 19 | 8 | 3 | 2 years ago | [s7_mini_fpga](https://github.com/blackmesalabs/s7_mini_fpga)/575 | Example designs for the Spartan7 "S7 Mini" FPGA board |
| 19 | 13 | 1 | 1 year, 5 months ago | [matrix-creator-fpga](https://github.com/matrix-io/matrix-creator-fpga)/576 | Reference HDL code for the MATRIX Creator's Spartan 6 FPGA |
| 19 | 10 | 2 | 2 years ago | [Zeus](https://github.com/GeraltShi/Zeus)/577 | NVDLA small config implementation on Zynq ZCU104 (evaluation) |
| 19 | 5 | 0 | 1 year, 1 month ago | [bitcoin_mining](https://github.com/kmod/bitcoin_mining)/578 | Simple test fpga bitcoin miner |
| 19 | 6 | 0 | 14 days ago | [jelly](https://github.com/ryuz/jelly)/579 | Original FPGA platform |
| 19 | 5 | 0 | 4 months ago | [srgh-matrix-trinity](https://github.com/kooscode/srgh-matrix-trinity)/580 | XBOX 360 advanced glitching - Reverse Engineered using a logic analyzer. |
| 19 | 2 | 0 | 6 months ago | [caravel_fpga250](https://github.com/ucb-cs250/caravel_fpga250)/581 | FPGA250 aboard the eFabless Caravel |
| 19 | 13 | 0 | 1 year, 7 months ago | [RISC-V-32I](https://github.com/Lyncien/RISC-V-32I)/582 | 体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器 |
| 19 | 6 | 0 | 2 years ago | [arm_vhdl](https://github.com/sergeykhbr/arm_vhdl)/583 | Portable FPGA project based on the ARM DesignStart bundle with ARM Cortex-M3 processor |
| 19 | 12 | 0 | 2 months ago | [evoapproxlib](https://github.com/ehw-fit/evoapproxlib)/584 | Library of approximate arithmetic circuits |
| 19 | 2 | 0 | 4 years ago | [RiverRaidFPGA](https://github.com/ef-end-y/RiverRaidFPGA)/585 | River Raid game on FPGA |
| 19 | 13 | 1 | 1 year, 9 months ago | [gemac](https://github.com/aquaxis/gemac)/586 | Gigabit MAC + UDP/TCP/IP offload Engine |
| 19 | 4 | 0 | 3 months ago | [CPU_start_from_0](https://github.com/luyufan498/CPU_start_from_0)/587 | 从零开始设计一个CPU   (Verilog) |
| 18 | 4 | 0 | 9 years ago | [verilog-vga-controller](https://github.com/mstump/verilog-vga-controller)/588 | A very simple VGA controller written in verilog |
| 18 | 4 | 0 | 2 months ago | [k1801](https://github.com/1801BM1/k1801)/589 | 1801 series ULA reverse engineering |
| 18 | 6 | 0 | 1 year, 1 month ago | [core_soc](https://github.com/ultraembedded/core_soc)/590 | Basic Peripheral SoC (SPI, GPIO, Timer, UART) |
| 18 | 3 | 4 | 2 years ago | [fLaCPGA](https://github.com/xavieran/fLaCPGA)/591 | Implementation of fLaC encoder/decoder for FPGA |
| 18 | 1 | 0 | 2 months ago | [biggateboy](https://github.com/racerxdl/biggateboy)/592 | WIP Big FPGA Gameboy |
| 18 | 7 | 0 | Unknown | [DSP-RTL-Lib](https://github.com/ahmedshahein/DSP-RTL-Lib)/593 | RTL Verilog library for various DSP modules |
| 18 | 1 | 0 | Unknown | [VerilogCommon](https://github.com/hedgeberg/VerilogCommon)/594 | A repo of basic Verilog/SystemVerilog modules useful in other circuits.  |
| 18 | 7 | 0 | 3 years ago | [Verilog_Calculator_Matrix_Multiplication](https://github.com/pontazaricardo/Verilog_Calculator_Matrix_Multiplication)/595 | This is a simple project that shows how to multiply two 3x3 matrixes in Verilog. |
| 18 | 20 | 0 | Unknown | [risc-v-core](https://github.com/shivanishah269/risc-v-core)/596 | This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover |
| 18 | 0 | 0 | 3 years ago | [sdaccel_chisel_integration](https://github.com/necst/sdaccel_chisel_integration)/597 | Chisel Project for Integrating RTL code into SDAccel |
| 18 | 0 | 0 | 1 year, 8 months ago | [risc-v](https://github.com/Cra2yPierr0t/risc-v)/598 | RISC-VのCPU作った |
| 18 | 1 | 0 | Unknown | [8bit-computer](https://github.com/lightcode/8bit-computer)/599 | Simple 8-bit computer build in Verilog |
| 18 | 4 | 0 | 4 years ago | [MesaBusProtocol](https://github.com/blackmesalabs/MesaBusProtocol)/600 | Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces |
| 18 | 1 | 0 | Unknown | [spi_tb](https://github.com/cr1901/spi_tb)/601 | CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys |
| 18 | 10 | 0 | Unknown | [DDLM](https://github.com/RomeoMe5/DDLM)/602 | Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула) |
| 18 | 8 | 0 | Unknown | [INSIDER-System](https://github.com/zainryan/INSIDER-System)/603 | An FPGA-based full-stack in-storage computing system.  |
| 18 | 5 | 0 | 6 months ago | [wb_intercon](https://github.com/olofk/wb_intercon)/604 | Wishbone interconnect utilities |
| 18 | 0 | 2 | 2 years ago | [HDL-deflate](https://github.com/tomtor/HDL-deflate)/605 | FPGA implementation of deflate (de)compress RFC 1950/1951 |
| 18 | 12 | 0 | 4 years ago | [polyphase_filter_prj](https://github.com/HeLiangHIT/polyphase_filter_prj)/606 | 软件无线电课设：多相滤波器的原理、实现及其应用，从采样率变换、多相滤波器结构到信道化收发机应用都有matlab介绍和FPGA仿真结果，含答辩PPT、学习笔记和个人总结。 |
| 18 | 17 | 1 | 9 years ago | [MIPS-in-Verilog](https://github.com/alok-upadhyay/MIPS-in-Verilog)/607 | An implementation of MIPS single cycle datapath in Verilog.  |
| 18 | 8 | 0 | 4 years ago | [Centaur](https://github.com/fpgasystems/Centaur)/608 | Centaur, a framework for hybrid CPU-FPGA databases |
| 18 | 0 | 0 | 1 year, 1 month ago | [Life_MiSTer](https://github.com/hrvach/Life_MiSTer)/609 | Conway's Game of Life in FPGA |
| 18 | 13 | 0 | 5 months ago | [DSX_KCXG](https://github.com/25thengineer/DSX_KCXG)/610 | 个人资料，合肥工业大学宣城校区2019年-2020年第二学期（大三下学期），与物联网工程专业的课程有关资料，含课件、实验报告、课设报告等 |
| 18 | 11 | 0 | 5 years ago | [ethernet_10ge_mac_SV_tb](https://github.com/andres-mancera/ethernet_10ge_mac_SV_tb)/611 | SystemVerilog testbench for an Ethernet 10GE MAC core |
| 18 | 7 | 0 | 10 years ago | [video_stream_scaler](https://github.com/freecores/video_stream_scaler)/612 | Video Stream Scaler |
| 18 | 1 | 0 | 3 years ago | [UART2NAND](https://github.com/hedgeberg/UART2NAND)/613 | Interface for exposing raw NAND i/o over UART to enable pc-side modification. |
| 18 | 5 | 0 | 1 year, 6 months ago | [Digital_Front_End_Verilog](https://github.com/NingHeChuan/Digital_Front_End_Verilog)/614 | None |
| 18 | 6 | 0 | 1 year, 9 days ago | [USTC-ComputerArchitecture-2020S](https://github.com/yuxguo/USTC-ComputerArchitecture-2020S)/615 | Code for "Computer Architecture" in 2020 Spring. |
| 17 | 1 | 0 | 3 years ago | [fpga-sram](https://github.com/mattvenn/fpga-sram)/616 | mystorm sram test |
| 17 | 5 | 1 | 5 years ago | [mips](https://github.com/HaleLu/mips)/617 | Mips处理器仿真设计 |
| 17 | 10 | 2 | 9 months ago | [KWS-SoC](https://github.com/IA-C-Lab-Fudan/KWS-SoC)/618 | This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform. |
| 17 | 7 | 0 | 1 year, 21 days ago | [fpga-bpf](https://github.com/UofT-HPRC/fpga-bpf)/619 | A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark |
| 17 | 6 | 1 | 4 years ago | [iir-bandstop-filter](https://github.com/amoudgl/iir-bandstop-filter)/620 | Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic |
| 17 | 0 | 0 | 6 months ago | [ucisc](https://github.com/grokthis/ucisc)/621 | None |
| 17 | 5 | 0 | 5 years ago | [orgexp](https://github.com/zhanghai/orgexp)/622 | Computer Organization Experiment, Shi Qingsong, Zhejiang University. |
| 17 | 4 | 2 | 5 years ago | [icestickPWM](https://github.com/wd5gnr/icestickPWM)/623 | Simple USB to PWM Peripheral using Lattice iCEStick (Hackaday demo) |
| 17 | 14 | 0 | 7 months ago | [vsdstdcelldesign](https://github.com/nickson-jose/vsdstdcelldesign)/624 | This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow. |
| 17 | 0 | 0 | 7 months ago | [SmolDVI](https://github.com/Wren6991/SmolDVI)/625 | Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs |
| 17 | 11 | 0 | 7 months ago | [verilog-starter-tutorials](https://github.com/ashishrana160796/verilog-starter-tutorials)/626 | Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts. |
| 17 | 5 | 1 | 3 years ago | [anlogic-picorv32](https://github.com/AnlogicInfo/anlogic-picorv32)/627 | Optimized picorv32 core for anlogic FPGA |
| 17 | 6 | 0 | 2 years ago | [OV7670_NEXYS4_Verilog](https://github.com/jonlwowski012/OV7670_NEXYS4_Verilog)/628 | This code is used to connect the OV7670 Camera to a NEXYS4 and then display the image on a monitor in Verilog |
| 17 | 15 | 1 | 1 year, 10 months ago | [FPGA_CryptoNight_V7](https://github.com/lulinchen/FPGA_CryptoNight_V7)/629 | FPGA CryptoNight V7 Minner |
| 17 | 1 | 0 | 6 months ago | [ics-adpcm](https://github.com/dan-rodrigues/ics-adpcm)/630 | Programmable multichannel ADPCM decoder for FPGA |
| 17 | 2 | 0 | 5 years ago | [QuickSilverNEO](https://github.com/HeavyPixels/QuickSilverNEO)/631 | None |
| 17 | 6 | 0 | 4 years ago | [computer-systems-ucas](https://github.com/sailordiary/computer-systems-ucas)/632 | 中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session |
| 17 | 0 | 0 | 5 months ago | [Hardware_Design](https://github.com/barryZZJ/Hardware_Design)/633 | None |
| 17 | 16 | 1 | 4 months ago | [apio-examples](https://github.com/FPGAwars/apio-examples)/634 | :seedling: Apio examples |
| 17 | 8 | 0 | 1 year, 23 days ago | [usb2sniffer](https://github.com/ultraembedded/usb2sniffer)/635 | USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware) |
| 17 | 4 | 0 | 9 years ago | [amber_samples](https://github.com/dwelch67/amber_samples)/636 | None |
| 17 | 9 | 0 | 3 years ago | [posture_recognition_CNN](https://github.com/cxdzyq1110/posture_recognition_CNN)/637 | To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different responses to all kinds of human's postures. But the process is very difficult as well, because usually it is very slow and power-consuming, and requires a very large memory space. Here we focus on real-time posture recognition, and try to make the machine "know" what posture we make. The posture recognition system is consisted of DE10-Nano SoC FPGA Kit, a camera, and an HDMI monitor. SoC FPGA captures video streams from the camera, recognizes human postures with a CNN model, and finally shows the original video and classification result (standing, walking, waving, etc.) via HDMI interface. |
| 17 | 6 | 2 | 3 months ago | [Simulator_CPU](https://github.com/ayzk/Simulator_CPU)/638 | Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog |
| 17 | 2 | 0 | 3 months ago | [hello-verilog](https://github.com/milochen0418/hello-verilog)/639 | Hello Verilog by Mac + VSCode  |
| 17 | 5 | 1 | 7 months ago | [OpenPhySyn](https://github.com/scale-lab/OpenPhySyn)/640 | EDA physical synthesis optimization kit |
| 17 | 3 | 30 | 14 days ago | [TART](https://github.com/tmolteno/TART)/641 | Transient Array Radio Telescope |
| 17 | 4 | 7 | 5 years ago | [vector06cc](https://github.com/svofski/vector06cc)/642 | Вектор-06ц в ПЛИС / Vector-06c in FPGA |
| 17 | 9 | 0 | 5 years ago | [2-way-Set-Associative-Cache-Controller](https://github.com/prasadp4009/2-way-Set-Associative-Cache-Controller)/643 | Synthesizable and Parameterized Cache Controller in Verilog |
| 17 | 6 | 0 | 2 years ago | [tinyfpga-bx-game-soc](https://github.com/gundy/tinyfpga-bx-game-soc)/644 | A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games |
| 17 | 2 | 0 | 7 months ago | [ws2812-core](https://github.com/mattvenn/ws2812-core)/645 | verilog core for ws2812 leds |
| 17 | 11 | 0 | 2 years ago | [FPGA-SM3-HASH](https://github.com/raymondrc/FPGA-SM3-HASH)/646 | Description of Chinese SM3 Hash algorithm with Verilog HDL |
| 16 | 2 | 0 | 4 years ago | [PitchShifter](https://github.com/jmt329/PitchShifter)/647 | Change the pitch of your voice in real-time! |
| 16 | 7 | 1 | 1 year, 4 months ago | [tonic](https://github.com/minmit/tonic)/648 | A Programmable Hardware Architecture for Network Transport Logic |
| 16 | 1 | 0 | 19 days ago | [Home-Brew-Computer](https://github.com/gpthimble/Home-Brew-Computer)/649 | SystemOT, yet another home brew cpu. |
| 16 | 0 | 0 | 3 years ago | [mera400f](https://github.com/jakubfi/mera400f)/650 | MERA-400 in an FPGA |
| 16 | 7 | 0 | 5 years ago | [PCIE_AXI_BRIDGE](https://github.com/SanjayRai/PCIE_AXI_BRIDGE)/651 | Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices |
| 16 | 2 | 0 | 27 days ago | [difuzz-rtl](https://github.com/compsec-snu/difuzz-rtl)/652 | None |
| 16 | 5 | 0 | 5 years ago | [cpus-pdp8](https://github.com/lisper/cpus-pdp8)/653 | FPGA based PDP-8/i clone in verilog.  Includes several TSS/8 sources and utiltities to build from source |
| 16 | 9 | 0 | 5 years ago | [Hardware_circular_buffer_controller](https://github.com/wtiandong/Hardware_circular_buffer_controller)/654 | This is a circular buffer controller used in FPGA. |
| 16 | 6 | 0 | 4 years ago | [icestick](https://github.com/wd5gnr/icestick)/655 | Simple demo for Lattice iCEstick board as seen on Hackaday |
| 16 | 6 | 5 | 4 years ago | [polaris](https://github.com/KestrelComputer/polaris)/656 | RISC-V RV64IS-compatible processor for the Kestrel-3 |
| 16 | 13 | 0 | 4 years ago | [FreeAHB](https://github.com/krevanth/FreeAHB)/657 | AHB Master |
| 16 | 22 | 1 | 3 years ago | [moneroasic](https://github.com/stremovsky/moneroasic)/658 | Cryptonight Monero Verilog code for ASIC |
| 16 | 4 | 0 | 1 year, 7 months ago | [RePLIA](https://github.com/WarwickEPR/RePLIA)/659 | FPGA Based lock in amplifier |
| 16 | 2 | 0 | 6 years ago | [WitnessProtection](https://github.com/feiranchen/WitnessProtection)/660 | in FPGA |
| 16 | 1 | 0 | a month ago | [enxor-logic-analyzer](https://github.com/lekgolo167/enxor-logic-analyzer)/661 | FPGA Logic Analyzer and GUI |
| 16 | 11 | 0 | 1 year, 1 month ago | [DA_PUF_Library](https://github.com/scluconn/DA_PUF_Library)/662 | Defense/Attack PUF Library (DA PUF Library) |
| 16 | 14 | 0 | 7 years ago | [logi-pong-chu-examples](https://github.com/fpga-logi/logi-pong-chu-examples)/663 | example code for the logi-boards from pong chu HDL book |
| 16 | 4 | 0 | 1 year, 2 months ago | [CNNAF-CNN-Accelerator](https://github.com/eda-lab/CNNAF-CNN-Accelerator)/664 | CNN-Accelerator based on FPGA developed by verilog HDL.  |
| 16 | 6 | 0 | a month ago | [core_usb_cdc](https://github.com/ultraembedded/core_usb_cdc)/665 | Basic USB-CDC device core (Verilog) |
| 16 | 6 | 0 | 5 years ago | [nes_mappers](https://github.com/ClusterM/nes_mappers)/666 | NES mappers |
| 16 | 12 | 13 | 11 months ago | [sancus-core](https://github.com/sancus-tee/sancus-core)/667 | Minimal OpenMSP430 hardware extensions for isolation and attestation |
| 16 | 6 | 0 | 9 days ago | [MIDI-Stepper-Synth-V2](https://github.com/jzkmath/MIDI-Stepper-Synth-V2)/668 | Virginia Tech AMP Lab Version of the MIDI Stepper Synth. Uses FPGA and 32 Stepper Motors. |
| 16 | 10 | 1 | 5 years ago | [AHB_Bus_Matrix](https://github.com/Lianghao-Yuan/AHB_Bus_Matrix)/669 | None |
| 16 | 14 | 1 | 4 years ago | [fpga-nn](https://github.com/roboticslab-uc3m/fpga-nn)/670 | NN on FPGA |
| 16 | 3 | 2 | 2 months ago | [OpenIRV](https://github.com/OVGN/OpenIRV)/671 | Open-source thermal camera project |
| 16 | 0 | 0 | 11 months ago | [ulx3s_examples](https://github.com/lawrie/ulx3s_examples)/672 | Example Verilog code for Ulx3s |
| 16 | 7 | 0 | 1 year, 8 months ago | [nica](https://github.com/acsl-technion/nica)/673 | An infrastructure for inline acceleration of network applications |
| 16 | 10 | 0 | a month ago | [vivado-ip-cores](https://github.com/CospanDesign/vivado-ip-cores)/674 | IP Cores that can be used within Vivado |
| 16 | 14 | 0 | 2 years ago | [gameduino](https://github.com/Godzil/gameduino)/675 | My own version of the @JamesBowman's Gameduino file repository |
| 16 | 1 | 0 | 3 days ago | [no2muacm](https://github.com/no2fpga/no2muacm)/676 | Drop In USB CDC ACM core for iCE40 FPGA |
| 16 | 6 | 1 | 1 year, 6 months ago | [ZBC---The-Zero-Board-Computer](https://github.com/donnaware/ZBC---The-Zero-Board-Computer)/677 | Based heavily on zet.aluzina.org and Terasic DE0 |
| 16 | 4 | 0 | 6 years ago | [magukara](https://github.com/Murailab-arch/magukara)/678 | FPGA-based open-source network tester |
| 16 | 15 | 0 | 3 years ago | [FPGA_SM4](https://github.com/raymondrc/FPGA_SM4)/679 | FPGA implementation of Chinese SM4 encryption algorithm. |
| 16 | 4 | 1 | 9 hours ago | [saxonsoc-ulx3s-bin](https://github.com/lawrie/saxonsoc-ulx3s-bin)/680 | The binaries for SaxonSoc Linux and other configurations |
| 16 | 3 | 0 | 8 months ago | [3DORGB](https://github.com/citrus3000psi/3DORGB)/681 | RGB Project for most 3DO consoles. |
| 16 | 13 | 1 | 4 years ago | [lisnoc](https://github.com/TUM-LIS/lisnoc)/682 | LIS Network-on-Chip Implementation |
| 16 | 5 | 0 | 7 years ago | [FPGA_Stereo_Depth_Map](https://github.com/jamesrivas/FPGA_Stereo_Depth_Map)/683 | None |
| 16 | 3 | 5 | 11 months ago | [MiSTer-Arcade-SEGASYS1](https://github.com/MrX-8B/MiSTer-Arcade-SEGASYS1)/684 | FPGA implementation of SEGA SYSTEM 1 arcade board |
| 16 | 1 | 0 | 11 months ago | [mips-cpu](https://github.com/skyzh/mips-cpu)/685 | 💻 A 5-stage pipeline MIPS CPU implementation in Verilog. |
| 16 | 2 | 1 | 7 months ago | [raiden](https://github.com/IBM/raiden)/686 | Raiden project |
| 16 | 9 | 0 | 3 years ago | [Curso-Electronica-Digital-para-makers-con-FPGAs-Libres](https://github.com/Obijuan/Curso-Electronica-Digital-para-makers-con-FPGAs-Libres)/687 | Curso de 35h sobre el diseño de sistemas digitales usando FPGAs libres, orientado para makers |
| 16 | 3 | 0 | 5 years ago | [verilog_tutorials_BB](https://github.com/peepo/verilog_tutorials_BB)/688 | verilog tutorials for iCE40HX8K Breakout Board |
| 16 | 1 | 0 | 1 year, 11 months ago | [Merlin](https://github.com/origintfj/Merlin)/689 | RISC-V RV32I[C] CPU (Apache-2.0) - Merlin |
| 16 | 2 | 0 | 4 years ago | [Hardware-Accelerated-SNN](https://github.com/arpanvyas/Hardware-Accelerated-SNN)/690 | Architecture for Spiking Neural Network |
| 15 | 1 | 0 | 10 years ago | [Oberwolfach-explorations](https://github.com/peterlefanulumsdaine/Oberwolfach-explorations)/691 | collaboration on work in progress |
| 15 | 11 | 0 | 1 year, 5 months ago | [matrix-voice-fpga](https://github.com/matrix-io/matrix-voice-fpga)/692 | HDL code for the MATRIX Voice's Spartan 6 FPGA http://voice.matrix.one |
| 15 | 0 | 0 | 1 year, 7 months ago | [FPGAGameBoy](https://github.com/Chockichoc/FPGAGameBoy)/693 | an implementation of the GameBoy in Verilog |
| 15 | 0 | 0 | 3 months ago | [my_hdmi_device](https://github.com/splinedrive/my_hdmi_device)/694 | New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser! |
| 15 | 1 | 0 | 3 years ago | [UPduino-Mecrisp-Ice-15kB](https://github.com/igor-m/UPduino-Mecrisp-Ice-15kB)/695 | Mecrisp-Ice Forth running on 16bit j1a processor (iCE40UP5k based UPduino board) with full 15kB of bram and 48bit Floating Point Library. |
| 15 | 0 | 1 | a month ago | [Deep-DarkFantasy](https://github.com/b1f6c1c4/Deep-DarkFantasy)/696 | Global Dark Mode for ALL apps on ANY platforms. |
| 15 | 8 | 8 | 4 years ago | [pars](https://github.com/subutai-attic/pars)/697 | None |
| 15 | 4 | 0 | 1 year, 8 months ago | [fpga_image_processing](https://github.com/damdoy/fpga_image_processing)/698 | IP operations in verilog (simulation and implementation on ice40) |
| 16 | 4 | 1 | 4 years ago | [handwriting-recognition-using-neural-networks-on-FPGA-final-year-project](https://github.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project)/699 | None |
| 15 | 9 | 2 | 4 months ago | [MemTest_MiSTer](https://github.com/MiSTer-devel/MemTest_MiSTer)/700 | None |
| 15 | 15 | 19 | a day ago | [yosys-symbiflow-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins)/701 | Plugins for Yosys developed as part of the SymbiFlow project. |
| 15 | 5 | 2 | 6 years ago | [Modular-Exponentiation](https://github.com/lajanugen/Modular-Exponentiation)/702 | Verilog Implementation of modular exponentiation using Montgomery multiplication |
| 15 | 8 | 0 | 3 years ago | [JPEG-Decoder](https://github.com/jdocampom/JPEG-Decoder)/703 | Verilog Code for a JPEG Decoder |
| 15 | 8 | 0 | 12 years ago | [verilog_cordic_core](https://github.com/freecores/verilog_cordic_core)/704 | configurable cordic core in verilog |
| 15 | 12 | 1 | 2 years ago | [Viterbi-Decoder-in-Verilog](https://github.com/jfoshea/Viterbi-Decoder-in-Verilog)/705 | An efficient implementation of the Viterbi decoding algorithm in Verilog |
| 15 | 12 | 0 | 3 years ago | [NoC-Verilog](https://github.com/bakhshalipour/NoC-Verilog)/706 | A verilog implementation for Network-on-Chip |
| 15 | 8 | 0 | 3 years ago | [FFTVisualizer](https://github.com/Goshik92/FFTVisualizer)/707 | This project demonstrates DSP capabilities of Terasic DE2-115 |
| 15 | 6 | 4 | 1 year, 9 months ago | [yosys-bench](https://github.com/YosysHQ/yosys-bench)/708 | Benchmarks for Yosys development |
| 15 | 5 | 0 | 2 years ago | [Flappy-Bird](https://github.com/BlusLiu/Flappy-Bird)/709 | FPGA program :VGA-GAME |
| 15 | 7 | 0 | 2 years ago | [Computer-Organization-and-Architecture-LAB](https://github.com/vedic-partap/Computer-Organization-and-Architecture-LAB)/710 | Solution to COA LAB Assgn, IIT Kharagpur |
| 15 | 1 | 0 | 4 months ago | [verilog](https://github.com/HarmonInstruments/verilog)/711 | None |
| 15 | 0 | 0 | 1 year, 7 months ago | [wbfmtx](https://github.com/ZipCPU/wbfmtx)/712 | A wishbone controlled FM transmitter hack |
| 15 | 10 | 0 | 2 years ago | [Verilog-FIR](https://github.com/Grootzz/Verilog-FIR)/713 | FIR implemention with Verilog |
| 15 | 14 | 1 | 11 years ago | [dvb_s2_ldpc_decoder](https://github.com/freecores/dvb_s2_ldpc_decoder)/714 | DVB-S2 LDPC Decoder |
| 15 | 5 | 1 | 1 year, 6 months ago | [RISC-V-CPU](https://github.com/jasonlin316/RISC-V-CPU)/715 | A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology. |
| 15 | 2 | 0 | 3 years ago | [NeuralHDL](https://github.com/andywag/NeuralHDL)/716 | None |
| 15 | 6 | 1 | 5 years ago | [dnn-sim](https://github.com/tayler-hetherington/dnn-sim)/717 | None |
| 15 | 10 | 0 | 4 years ago | [heterosim](https://github.com/RCSL-HKUST/heterosim)/718 | HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design space exploration is enabled by a wide range of system configurations. A complete simulation flow with compiler support is provided so that a full system simulation can be performed with various performance metrics returned. |
| 15 | 6 | 0 | 3 years ago | [Autonomous-Drone-Design](https://github.com/ISKU/Autonomous-Drone-Design)/719 | Design real-time image processing, object recognition and PID control for Autonomous Drone. |
| 15 | 3 | 1 | 6 years ago | [descrypt-ztex-bruteforcer](https://github.com/Gifts/descrypt-ztex-bruteforcer)/720 | descrypt-ztex-bruteforcer |
| 15 | 1 | 0 | 3 years ago | [iCEstick-hacks](https://github.com/r4d10n/iCEstick-hacks)/721 | iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter |
| 15 | 10 | 1 | 6 years ago | [i2s](https://github.com/skristiansson/i2s)/722 | i2s core, with support for both transmit and receive |
| 15 | 3 | 0 | 4 years ago | [OpenMIPS](https://github.com/muzilinxi90/OpenMIPS)/723 | OpenMIPS——《自己动手写CPU》处理器部分 |
| 15 | 9 | 0 | 6 months ago | [Reindeer_Step](https://github.com/PulseRain/Reindeer_Step)/724 | Reindeer Soft CPU for Step CYC10 FPGA board |
| 15 | 6 | 0 | 5 months ago | [fpga-ml-accelerator](https://github.com/thedatabusdotio/fpga-ml-accelerator)/725 | This repository hosts the code for an FPGA based accelerator for convolutional neural networks  |
| 15 | 10 | 0 | 2 years ago | [RISC-Processor](https://github.com/jbush001/RISC-Processor)/726 | 32-bit RISC processor |
| 15 | 3 | 1 | 1 year, 9 months ago | [net2axis](https://github.com/lucasbrasilino/net2axis)/727 | Verilog network module. Models network traffic from pcap to AXI-Stream |
| 15 | 5 | 0 | 9 years ago | [openmsp430](https://github.com/dlitz/openmsp430)/728 | openMSP430 CPU core (from OpenCores) |
| 15 | 8 | 0 | 3 years ago | [SHA256Hasher](https://github.com/Goshik92/SHA256Hasher)/729 | SHA-256 IP core for ZedBoard (Zynq SoC) |
| 15 | 4 | 2 | Unknown | [mipi-demo](https://github.com/hdl-util/mipi-demo)/730 | MIPI CSI-2 + MIPI CCS Demo |
| 15 | 4 | 0 | a month ago | [arrowzip](https://github.com/ZipCPU/arrowzip)/731 | A ZipCPU based demonstration of the MAX1000 FPGA board |
| 15 | 3 | 0 | 4 years ago | [fpga-synth](https://github.com/UA3MQJ/fpga-synth)/732 | FPGA based modular synth. |
| 15 | 5 | 0 | Unknown | [fpga-spartan6](https://github.com/ucb-bar/fpga-spartan6)/733 | Support for zScale on Spartan6 FPGAs |
| 14 | 2 | 1 | 1 year, 8 months ago | [galaksija](https://github.com/emard/galaksija)/734 | Galaksija computer for FPGA |
| 14 | 2 | 1 | 3 years ago | [mikrobus-upduino](https://github.com/mmicko/mikrobus-upduino)/735 | Dual MikroBUS board for Upduino 2 FPGA |
| 14 | 22 | 2 | 3 years ago | [FPGA-Keccak-Miner](https://github.com/0x2fed/FPGA-Keccak-Miner)/736 | None |
| 14 | 5 | 1 | 1 year, 5 months ago | [max2-audio-dac](https://github.com/dilshan/max2-audio-dac)/737 | 24-bit Stereo Audio DAC for Raspberry Pi |
| 14 | 13 | 0 | Unknown | [fpga-sdk-prj](https://github.com/syntacore/fpga-sdk-prj)/738 | FPGA-based SDK projects for SCRx cores |
| 14 | 7 | 0 | Unknown | [steel-core](https://github.com/rafaelcalcada/steel-core)/739 | Steel is a RISC-V processor core that implements the RV32I and Zicsr instruction sets of the RISC-V specifications. |
| 14 | 11 | 1 | 2 years ago | [zuma-fpga](https://github.com/adbrant/zuma-fpga)/740 | Fine Grain FPGA Overlay Architecture and Tools |
| 14 | 0 | 0 | 3 years ago | [iPxs-Text](https://github.com/juanmard/iPxs-Text)/741 | Text for a iPxs-Collection. |
| 14 | 9 | 0 | 4 months ago | [FPGA_DevKit_HX1006A](https://github.com/eda-lab/FPGA_DevKit_HX1006A)/742 | None |
| 14 | 8 | 7 | 4 months ago | [Archie_MiSTer](https://github.com/MiSTer-devel/Archie_MiSTer)/743 | Acorn Archimedes for MiSTer |
| 14 | 4 | 0 | Unknown | [ASIC-FPGA-tetris](https://github.com/tinylic/ASIC-FPGA-tetris)/744 | a FPGA implementation for tetris game. |
| 14 | 3 | 1 | 4 years ago | [Menu_MIST](https://github.com/sorgelig/Menu_MIST)/745 | Dummy FPGA core to display menu at startup |
| 14 | 2 | 0 | 1 year, 9 months ago | [systolic-array-matrix-multiplier](https://github.com/wzc810049078/systolic-array-matrix-multiplier)/746 | A systolic array matrix multiplier  |
| 14 | 14 | 1 | Unknown | [ASIC](https://github.com/vlsi1217/ASIC)/747 | EE 287 2012 Fall |
| 14 | 1 | 0 | a month ago | [jtopl](https://github.com/jotego/jtopl)/748 | Verilog module compatible with Yamaha OPL chips |
| 14 | 4 | 0 | 5 years ago | [Computer-Architecture](https://github.com/nblintao/Computer-Architecture)/749 | A pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and cache. |
| 14 | 2 | 1 | 2 years ago | [Conways-Game-of-Life-with-Vlang](https://github.com/fuyutarow/Conways-Game-of-Life-with-Vlang)/750 |  Conway's life game in V |
| 14 | 9 | 2 | Unknown | [freepdk-45nm](https://github.com/mflowgen/freepdk-45nm)/751 | ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen |
| 14 | 8 | 0 | Unknown | [ring_network-based-multicore-](https://github.com/zhaishaomin/ring_network-based-multicore-)/752 | 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency |
| 14 | 3 | 0 | 2 years ago | [Ada-PicoRV32-example](https://github.com/Fabien-Chouteau/Ada-PicoRV32-example)/753 | Example of Ada code running on the PicoRV32 RISC-V CPU for FPGA |
| 14 | 4 | 0 | 10 years ago | [opengg](https://github.com/lzw545/opengg)/754 | OpenGL-like graphics pipeline on a Xilinx FPGA |
| 14 | 2 | 1 | Unknown | [chad](https://github.com/bradleyeckert/chad)/755 | A self-hosting Forth for J1-style CPUs |
| 14 | 7 | 0 | 3 years ago | [pciebench-netfpga](https://github.com/pcie-bench/pciebench-netfpga)/756 |  pcie-bench code for NetFPGA/VCU709 cards  |
| 14 | 13 | 1 | Unknown | [OpenHPSDR-Firmware](https://github.com/TAPR/OpenHPSDR-Firmware)/757 | This is the verilog code for the various FPGA in the OpenHPSDR Radios |
| 14 | 5 | 4 | Unknown | [VossII](https://github.com/TeamVoss/VossII)/758 | The source code to the Voss II Hardware Verification Suite |
| 14 | 10 | 4 | 4 months ago | [Arcade-GnG_MiSTer](https://github.com/MiSTer-devel/Arcade-GnG_MiSTer)/759 | Arcade Ghosts'n Goblins for MiSTer |
| 14 | 7 | 0 | Unknown | [Atari7800_MiSTer](https://github.com/Kitrinx/Atari7800_MiSTer)/760 | Atari 7800 for MiSTer |
| 14 | 4 | 1 | Unknown | [fpga-wpa-psk-bruteforcer](https://github.com/davidgfnet/fpga-wpa-psk-bruteforcer)/761 | WPA-PSK cracking for FPGA devices |
| 14 | 4 | 7 | 3 years ago | [liquid-router](https://github.com/subutai-attic/liquid-router)/762 | The Subutai™ Router open hardware project sources. |
| 14 | 2 | 4 | 1 year, 4 months ago | [fluent10g](https://github.com/aoeldemann/fluent10g)/763 | Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet |
| 14 | 2 | 0 | 1 year, 2 months ago | [Nu6509](https://github.com/go4retro/Nu6509)/764 | Emulate a 6509 with a 6502 |
| 14 | 10 | 1 | 5 years ago | [BD3_FPGA](https://github.com/whc2uestc/BD3_FPGA)/765 | 新一代北斗卫星导航监测接收机的FPGA实现 |
| 14 | 3 | 0 | a month ago | [icozip](https://github.com/ZipCPU/icozip)/766 | A ZipCPU demonstration port for the icoboard |
| 14 | 6 | 2 | 5 years ago | [idea](https://github.com/warclab/idea)/767 | iDEA FPGA Soft Processor |
| 14 | 6 | 0 | 1 year, 3 months ago | [verilog](https://github.com/dslu7733/verilog)/768 | None |
| 14 | 4 | 0 | 1 year, 10 months ago | [cdsAsync](https://github.com/ucdrstdenis/cdsAsync)/769 | cdsAsync: An Asynchronous VLSI Toolset & Schematic Library  |
| 14 | 13 | 1 | Unknown | [FPGA_rtime_HDR_video](https://github.com/sh-vlad/FPGA_rtime_HDR_video)/770 | We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.  |
| 14 | 11 | 0 | Unknown | [32-bit-MIPS-Processor](https://github.com/sevvalmehder/32-bit-MIPS-Processor)/771 | A 32-bit MIPS processor used Altera Quartus II with Verilog. |
| 14 | 7 | 0 | Unknown | [vp_awsfpga](https://github.com/nvdla/vp_awsfpga)/772 | Virtual Platform for AWS FPGA support |
| 14 | 3 | 1 | 1 year, 9 months ago | [TMR](https://github.com/ThalesGroup/TMR)/773 | Triple Modular Redundancy  |
| 14 | 4 | 0 | 3 years ago | [crap-o-scope](https://github.com/mattvenn/crap-o-scope)/774 | crap-o-scope scope implementation for icestick |
| 14 | 4 | 0 | 1 year, 10 months ago | [yoloRISC](https://github.com/gsomlo/yoloRISC)/775 | A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga |
| 14 | 9 | 0 | 2 years ago | [Convolution-using-systolic-arrays](https://github.com/ac-optimus/Convolution-using-systolic-arrays)/776 | None |
| 14 | 0 | 0 | Unknown | [RISCV-CPU](https://github.com/kzoacn/RISCV-CPU)/777 | SJTU Computer Architecture(1) Hw |
| 14 | 10 | 0 | Unknown | [AXI_BFM](https://github.com/ptracton/AXI_BFM)/778 | AXI4 BFM in Verilog |
| 14 | 4 | 0 | 2 months ago | [OPDB](https://github.com/PrincetonUniversity/OPDB)/779 | OpenPiton Design Benchmark |
| 14 | 5 | 0 | Unknown | [Nexys-4-DDR-Ethernet-Mac](https://github.com/chasep255/Nexys-4-DDR-Ethernet-Mac)/780 | Ethernet MAC for the Digilent Nexys 4 DDR FPGA. |
| 14 | 2 | 0 | 1 year, 5 months ago | [ice40_8bitworkshop](https://github.com/n24bass/ice40_8bitworkshop)/781 |  "Designing Video Game Hardware in Verilog" in  iCE40HX8K Breakout Board. |
| 14 | 6 | 0 | 1 year, 12 days ago | [Azure-SDR](https://github.com/Elrori/Azure-SDR)/782 | SW SDR |
| 14 | 9 | 0 | 6 years ago | [NetFPGA-10G-UPB-OpenFlow](https://github.com/pc2/NetFPGA-10G-UPB-OpenFlow)/783 | An OpenFlow implementation for the NetFPGA-10G card |
| 14 | 6 | 0 | Unknown | [digital_lab](https://github.com/KorotkiyEugene/digital_lab)/784 | Laboratory works for digital electronics course in Kyiv Polytechnic Institute, Department of Design of Electronic Digital Equipment, Electronics faculty |
| 14 | 10 | 0 | Unknown | [FPGA-Mnist](https://github.com/Johnny-Zou/FPGA-Mnist)/785 | Hand written number classification done in hardware (De1-SoC board) using neural networks |
| 14 | 1 | 0 | a month ago | [arty-videocap](https://github.com/ikanoano/arty-videocap)/786 | Repeat and capture the video signal with Digilent Arty-A7 and a video extender board. |
| 14 | 9 | 0 | Unknown | [sha3](https://github.com/secworks/sha3)/787 | FIPS 202 compliant SHA-3 core in Verilog |
| 14 | 12 | 0 | 3 years ago | [riscvv](https://github.com/panweitao/riscvv)/788 | an open source uvm verification platform for e200 (riscv) |
| 14 | 2 | 1 | Unknown | [ethpipe](https://github.com/sora/ethpipe)/789 | EtherPIPE: an Ethernet character device for packet processing |
| 14 | 3 | 0 | 6 months ago | [NeoChips](https://github.com/neogeodev/NeoChips)/790 | Replacement "chips" for NeoGeo systems |
| 14 | 6 | 0 | 1 year, 10 months ago | [Delta-sigma-ADC-verilog](https://github.com/Elrori/Delta-sigma-ADC-verilog)/791 | Delta-sigma ADC,PDM audio FPGA Implementation |
| 14 | 3 | 0 | 3 months ago | [riscv-core](https://github.com/ombhilare999/riscv-core)/792 | A customized RISCV core made using verilog |
| 13 | 4 | 0 | Unknown | [80211scrambler](https://github.com/travisgoodspeed/80211scrambler)/793 | Tools for working with the 802.11B scrambler when writing Packet-in-Packet exploits. |
| 13 | 11 | 0 | Unknown | [wb_sdram_ctrl](https://github.com/skristiansson/wb_sdram_ctrl)/794 | SDRAM controller with multiple wishbone slave ports |
| 13 | 0 | 1 | 10 months ago | [TurboMaster](https://github.com/go4retro/TurboMaster)/795 | Reverse Engineering of the Schnedler Systems 4MHz TurboMaster accelerator cartridge for the Commodore 64 |
| 13 | 4 | 0 | 6 years ago | [ShootingGame-FPGA](https://github.com/Lyukx/ShootingGame-FPGA)/796 | Using verilog-HDL, xilinx-ISE and nexys-iii. A shooting game based on VGA and ps/2 keyboard. |
| 13 | 12 | 4 | Unknown | [DE1-SoC-Sound](https://github.com/bsteinsbo/DE1-SoC-Sound)/797 | None |
| 13 | 0 | 0 | Unknown | [fpga_tv](https://github.com/mcleod-ideafix/fpga_tv)/798 | Some crazy experiments about using a FPGA to transmit a TV signal old-style |
| 13 | 2 | 0 | 3 months ago | [bitmips2019](https://github.com/Silverster98/bitmips2019)/799 | None |
| 13 | 4 | 0 | 1 year, 4 months ago | [Jaguar_MiSTer_new](https://github.com/ElectronAsh/Jaguar_MiSTer_new)/800 | None |
| 13 | 2 | 0 | 6 years ago | [parallel-processor-design](https://github.com/sdasgup3/parallel-processor-design)/801 | Super scalar Processor design  |
| 13 | 4 | 1 | 5 years ago | [dyract](https://github.com/warclab/dyract)/802 | DyRACT Open Source Repository |
| 13 | 6 | 0 | 5 years ago | [mips32r1_core](https://github.com/grantae/mips32r1_core)/803 | A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. |
| 13 | 8 | 0 | 5 years ago | [verilog-tetris](https://github.com/rfotino/verilog-tetris)/804 | A Verilog implementation of the popular video game Tetris. |
| 13 | 3 | 2 | 4 years ago | [hardcaml-riscv](https://github.com/ujamjar/hardcaml-riscv)/805 | RISC-V instruction set CPUs in HardCaml |
| 13 | 4 | 0 | 30 days ago | [no2bootloader](https://github.com/no2fpga/no2bootloader)/806 | USB DFU bootloader gateware / firmware for FPGAs |
| 13 | 2 | 0 | 2 years ago | [pinky8bitcpu](https://github.com/ikotler/pinky8bitcpu)/807 | Pinky (8-bit CPU) written in Verilog and an Assembler written in Python 3 |
| 13 | 4 | 1 | a month ago | [subservient](https://github.com/olofk/subservient)/808 | Small SERV-based SoC primarily for OpenMPW tapeout |
| 13 | 3 | 0 | 5 years ago | [FPGA](https://github.com/JeremyJiWZ/FPGA)/809 | computer hardware system including ps2/vga with tank war game in verilog and mips |
| 13 | 6 | 0 | 1 year, 9 months ago | [fpga-gpu](https://github.com/charliehorse55/fpga-gpu)/810 | A basic GPU for altera FPGAs |
| 13 | 9 | 0 | 2 years ago | [AD9361_TX_MSK](https://github.com/Grootzz/AD9361_TX_MSK)/811 | A project demonstrate how to config ad9361 to TX mode and how to transmit MSK |
| 13 | 5 | 6 | 16 days ago | [shapool-core](https://github.com/jkiv/shapool-core)/812 | FPGA core for SHA256d mining targeting Lattice iCE40 devices. |
| 13 | 8 | 0 | 3 years ago | [TinyFPGA-SoC](https://github.com/tinyfpga/TinyFPGA-SoC)/813 | Opensource building blocks for TinyFPGA microcontrollers and retro computers. |
| 13 | 11 | 0 | 8 years ago | [4way-cache](https://github.com/xdesigns/4way-cache)/814 | Verilog cache implementation of 4-way FIFO 16k Cache |
| 13 | 2 | 0 | 2 years ago | [CNN-Based-FPGA](https://github.com/fanbinqi/CNN-Based-FPGA)/815 | CNN implementation based FPGA |
| 13 | 5 | 0 | 2 years ago | [openzcore](https://github.com/lokisz/openzcore)/816 | powerpc processor prototype and an example of semiconductor startup biz plan |
| 13 | 9 | 1 | 9 years ago | [mips_16](https://github.com/freecores/mips_16)/817 | Educational 16-bit MIPS Processor |
| 13 | 11 | 1 | 4 years ago | [Radix-2-FFT](https://github.com/vinamarora8/Radix-2-FFT)/818 | Verilog code for a circuit implementation of Radix-2 FFT |
| 13 | 9 | 0 | 1 year, 11 months ago | [verilog-divider](https://github.com/risclite/verilog-divider)/819 | a super-simple pipelined verilog divider. flexible to define stages |
| 13 | 1 | 3 | 3 years ago | [oram](https://github.com/ascend-secure-processor/oram)/820 | Hardware implementation of ORAM |
| 13 | 12 | 1 | 2 years ago | [digital-design-lab-manual](https://github.com/MIPSfpga/digital-design-lab-manual)/821 | Digital Design Labs |
| 13 | 4 | 0 | 3 months ago | [ssith-aws-fpga](https://github.com/acceleratedtech/ssith-aws-fpga)/822 | Host software for running SSITH processors on AWS F1 FPGAs |
| 13 | 2 | 1 | 11 years ago | [soc-lm32](https://github.com/jbornschein/soc-lm32)/823 | Open source/hardware SoC plattform based on the lattice mico 32 softcore |
| 13 | 7 | 0 | 3 months ago | [64-bit-Universal-Floating-Point-ISA-Compute-Engine](https://github.com/jerry-D/64-bit-Universal-Floating-Point-ISA-Compute-Engine)/824 | RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine |
| 13 | 2 | 0 | 10 months ago | [de10-nano-riscv](https://github.com/thinkoco/de10-nano-riscv)/825 | A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano |
| 13 | 4 | 7 | 8 months ago | [scarv-cpu](https://github.com/scarv/scarv-cpu)/826 | SCARV: a side-channel hardened RISC-V platform |
| 13 | 1 | 0 | 6 years ago | [VerilogCogs](https://github.com/Cognoscan/VerilogCogs)/827 | Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun. |
| 13 | 14 | 4 | 4 years ago | [test_jpeg](https://github.com/cfelton/test_jpeg)/828 | This is a myhdl test environment for the open-cores jpeg_encoder. |
| 13 | 7 | 0 | 17 years ago | [jtag](https://github.com/freecores/jtag)/829 | JTAG Test Access Port (TAP) |
| 13 | 9 | 0 | 5 years ago | [Verilog-Single-Cycle-Processor](https://github.com/hxing9974/Verilog-Single-Cycle-Processor)/830 | Verilog |
| 13 | 5 | 0 | 1 year, 1 month ago | [aes](https://github.com/ahegazy/aes)/831 | Advanced encryption standard implementation in verilog. |
| 13 | 0 | 0 | 4 years ago | [fpga_csgo](https://github.com/SmartHypercube/fpga_csgo)/832 | Counter Strike: Global Offensive FPGA Version (LOL) |
| 13 | 6 | 0 | 2 months ago | [M65C02A](https://github.com/MorrisMA/M65C02A)/833 | Enhanced 6502/65C02 Microprogrammed FPGA Processor Core (Verilog-2001) |
| 13 | 2 | 1 | 1 year, 6 months ago | [SNKVerilog](https://github.com/neogeodev/SNKVerilog)/834 | Verilog definitions of custom SNK chips, for repairs and preservation. |
| 13 | 11 | 5 | 4 months ago | [rp_lock-in_pid](https://github.com/marceluda/rp_lock-in_pid)/835 | Lock-in and PID application for RedPitaya enviroment |
| 13 | 13 | 1 | 3 years ago | [c64-dodgypla](https://github.com/desaster/c64-dodgypla)/836 | Commodore 64 PLA replacement |
| 13 | 0 | 0 | 11 months ago | [fomu-vga](https://github.com/mntmn/fomu-vga)/837 | None |
| 13 | 4 | 0 | 10 months ago | [SortingNetwork](https://github.com/john9636/SortingNetwork)/838 | Implement a bitonic sorting network on FPGA |
| 13 | 5 | 4 | 14 hours ago | [jtdd](https://github.com/jotego/jtdd)/839 | Double Dragon FPGA core |
| 13 | 4 | 0 | 2 years ago | [MIPS-Architecture-CPU-design](https://github.com/KurohaneNioko/MIPS-Architecture-CPU-design)/840 | BUAA SCSE - Computer Organization - Pipeline CPU design |
| 13 | 1 | 1 | 9 months ago | [INT_FP_MAC](https://github.com/erihsu/INT_FP_MAC)/841 | INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed. |
| 13 | 8 | 2 | 8 months ago | [elec50010-2020-verilog-lab](https://github.com/m8pple/elec50010-2020-verilog-lab)/842 | Verilog lab material for ELEC50010 class |
| 13 | 2 | 2 | 1 year, 8 months ago | [upduino](https://github.com/tomverbeure/upduino)/843 | None |
| 13 | 4 | 0 | 1 year, 1 month ago | [riscv_sbc](https://github.com/ultraembedded/riscv_sbc)/844 | A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board. |
| 13 | 6 | 0 | 2 years ago | [up5k_vga](https://github.com/emeb/up5k_vga)/845 | A complete 65C02 computer with VGA output on a Lattice Ultra Plus FPGA |
| 13 | 65 | 14 | 9 days ago | [caravel_user_project](https://github.com/efabless/caravel_user_project)/846 | https://caravel-user-project.readthedocs.io |
| 13 | 9 | 0 | 2 years ago | [fpga-tutorial](https://github.com/pwmarcz/fpga-tutorial)/847 | FPGA tutorial |
| 12 | 11 | 0 | 9 years ago | [wimax_ofdm](https://github.com/jmesmon/wimax_ofdm)/848 | Partial Verilog implimentation of a WiMAX OFDM Phy |
| 12 | 3 | 0 | 3 years ago | [ipxactexamplelib](https://github.com/kactus2/ipxactexamplelib)/849 | Contains examples to start with Kactus2. |
| 12 | 0 | 0 | 1 year, 4 months ago | [eecs151](https://github.com/ry/eecs151)/850 | http://inst.eecs.berkeley.edu/~eecs151/fa19/ |
| 12 | 11 | 0 | 5 years ago | [Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM](https://github.com/AmeerAbdelhadi/Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM)/851 | Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM) |
| 12 | 7 | 1 | 1 year, 11 months ago | [ComputerArchitectureLab](https://github.com/Summer-Summer/ComputerArchitectureLab)/852 | This repository is used to release the Labs of Computer Architecture Course from USTC |
| 12 | 7 | 0 | 1 year, 10 months ago | [verilog-doc](https://github.com/Explainaur/verilog-doc)/853 | All About HDL |
| 12 | 2 | 0 | 2 years ago | [cpld-6502](https://github.com/Arlet/cpld-6502)/854 | 6502 CPU in 4 small CPLDs |
| 12 | 6 | 1 | 1 year, 1 month ago | [Low-Cost-and-Programmable-CRC](https://github.com/FPGA-Networking/Low-Cost-and-Programmable-CRC)/855 | Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA" |
| 12 | 3 | 0 | 3 years ago | [bladerf-dvbs2](https://github.com/mattzgto/bladerf-dvbs2)/856 | 16-APSK DVB-S2 Transmitter for BladeRF |
| 12 | 9 | 1 | 3 years ago | [HLS_Legup](https://github.com/wincle626/HLS_Legup)/857 | None |
| 12 | 6 | 0 | 4 years ago | [Rocket-Chip](https://github.com/riscveval/Rocket-Chip)/858 | None |
| 12 | 3 | 0 | 2 years ago | [fpga_1943](https://github.com/fredrequin/fpga_1943)/859 | Verilog re-implementation of the famous CAPCOM arcade game |
| 12 | 8 | 0 | 3 years ago | [fpga-hdl](https://github.com/jeras/fpga-hdl)/860 | A set of small Verilog projects, to simulate and implement on FPGA development boards |
| 12 | 12 | 0 | 1 year, 9 months ago | [Pmod-I2S2](https://github.com/Digilent/Pmod-I2S2)/861 | None |
| 12 | 3 | 0 | 2 years ago | [xulalx25soc](https://github.com/ZipCPU/xulalx25soc)/862 | A System on a Chip Implementation for the XuLA2-LX25 board |
| 12 | 7 | 0 | 3 years ago | [CPU](https://github.com/txstate-pcarch-blue/CPU)/863 | CS3339 Computer Architecture class project - 5 stage MIPS-like processor with forwarding, hazard control, no exception handling. |
| 12 | 4 | 0 | 8 years ago | [mcs-4](https://github.com/freecores/mcs-4)/864 | 4004 CPU and MCS-4 family chips |
| 12 | 2 | 0 | 4 months ago | [DVP_to_UDP](https://github.com/KoroB14/DVP_to_UDP)/865 | Uncompressed video uver UDP using 1000BASE-T Ethernet on Cyclone IV FPGA |
| 12 | 1 | 0 | 7 years ago | [milkymist-mmu](https://github.com/fallen/milkymist-mmu)/866 | Milkymist MMU project |
| 12 | 3 | 0 | 3 years ago | [bextdep](https://github.com/cliffordwolf/bextdep)/867 | Reference Hardware Implementations of Bit Extract/Deposit Instructions |
| 12 | 5 | 0 | 2 years ago | [BareBonesCortexM0](https://github.com/siorpaes/BareBonesCortexM0)/868 | Extremely basic CortexM0 SoC based on ARM DesignStart Eval |
| 12 | 1 | 0 | 26 days ago | [xyloni](https://github.com/Efinix-Inc/xyloni)/869 | This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board. |
| 12 | 3 | 0 | 4 months ago | [Nexys-4-DDR-Keyboard](https://github.com/Digilent/Nexys-4-DDR-Keyboard)/870 | None |
| 12 | 5 | 0 | 4 years ago | [riffa2](https://github.com/promach/riffa2)/871 | Full duplex version of https://github.com/KastnerRG/riffa/issues/30 |
| 12 | 3 | 2 | 6 months ago | [SoC_Automation](https://github.com/habibagamal/SoC_Automation)/872 | SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.  |
| 12 | 1 | 0 | 9 years ago | [bfcpu2](https://github.com/whitequark/bfcpu2)/873 | A pipelined brainfuck softcore in Verilog |
| 12 | 4 | 1 | 5 years ago | [ICEd](https://github.com/AnttiLukats/ICEd)/874 | Open Hardware for Open Source FPGA Toolchain |
| 12 | 0 | 0 | 5 years ago | [yosys-ice-experiments](https://github.com/laanwj/yosys-ice-experiments)/875 | Experiments for iCEstick evaluation board with iCE40HX-1k FPGA - using open source toolchain |
| 12 | 4 | 0 | 2 years ago | [digital-design](https://github.com/defano/digital-design)/876 | An introduction to integrated circuit design with Verilog and the Papilio Pro development board. |
| 12 | 7 | 7 | 5 years ago | [pifo-hardware](https://github.com/programmable-scheduling/pifo-hardware)/877 | None |
| 12 | 6 | 0 | 1 year, 11 months ago | [Zynq-7000-DPU-TRD](https://github.com/sumilao/Zynq-7000-DPU-TRD)/878 | Zynq-7000 DPU TRD |
| 12 | 4 | 0 | 9 years ago | [oc-i2c](https://github.com/trondd/oc-i2c)/879 | I2C controller core from Opencores.org |
| 12 | 6 | 0 | 4 years ago | [gng](https://github.com/liuguangxi/gng)/880 | Gaussian noise generator Verilog IP core |
| 12 | 4 | 0 | 6 years ago | [radio-86rk-wxeda](https://github.com/andykarpov/radio-86rk-wxeda)/881 | Port of the original radio-86rk_SDRAM Altera DE1 code to the WXEDA board |
| 12 | 2 | 0 | 5 years ago | [consolite-hardware](https://github.com/rfotino/consolite-hardware)/882 | A hardware implementation of the Consolite game console written in Verilog. |
| 12 | 2 | 4 | 1 year, 11 months ago | [pumpkin](https://github.com/pobu-arch/pumpkin)/883 | None |
| 12 | 0 | 0 | 2 years ago | [ulx3s-foss-blinky](https://github.com/q3k/ulx3s-foss-blinky)/884 | A template project for the ULX3S ECP5 FPGA board using only Open Source Software |
| 12 | 9 | 5 | 4 months ago | [Amstrad_MiSTer](https://github.com/MiSTer-devel/Amstrad_MiSTer)/885 | Amstrad CPC 6128 for MiSTer |
| 12 | 3 | 0 | 24 days ago | [core_dbg_bridge](https://github.com/ultraembedded/core_dbg_bridge)/886 | UART -> AXI Bridge |
| 12 | 1 | 1 | 1 year, 11 months ago | [Electronic-competition](https://github.com/qiaoxu123/Electronic-competition)/887 | 全国大学生电子设计大赛往年赛题--仪器仪表类练习 |
| 12 | 11 | 0 | 2 years ago | [CurriculumDesign-PrinciplesOfComputerOrganization](https://github.com/junglehust/CurriculumDesign-PrinciplesOfComputerOrganization)/888 | 华中科技大学计算机15级计算机组成原理课程设计，分别用logisim和Verilog实现简单CPU |
| 12 | 6 | 2 | 5 years ago | [Pano-Logic-Zero-Client-G2-FPGA-Demo](https://github.com/cyrozap/Pano-Logic-Zero-Client-G2-FPGA-Demo)/889 | Constraints file and Verilog demo code for the Pano Logic Zero Client G2 |
| 12 | 9 | 0 | 8 years ago | [VP2motion](https://github.com/sevikkk/VP2motion)/890 | FPGA based motion controller for RepRap style 3D printers |
| 12 | 3 | 6 | 1 year, 8 months ago | [loam](https://github.com/phanrahan/loam)/891 | Loam system models |
| 12 | 4 | 0 | 3 years ago | [DSITx](https://github.com/MightyDevices/DSITx)/892 | FPGA implementation of DSITx (single lane) used in conjunction with ipod nano 7th gen display |
| 12 | 6 | 0 | 1 year, 8 months ago | [SparkRoad-FPGA](https://github.com/verimake-team/SparkRoad-FPGA)/893 | None |
| 12 | 1 | 0 | 7 years ago | [next186_soc_pc](https://github.com/tmatsuya/next186_soc_pc)/894 | Next186 SoC PC |
| 12 | 0 | 1 | 2 years ago | [gameboy-sound-chip](https://github.com/aselker/gameboy-sound-chip)/895 | None |
| 12 | 14 | 0 | 8 years ago | [axi-bfm](https://github.com/sjaeckel/axi-bfm)/896 | git clone of http://code.google.com/p/axi-bfm/ |
| 12 | 5 | 0 | 6 years ago | [Simple-32bit-ALU-Design](https://github.com/bobmshannon/Simple-32bit-ALU-Design)/897 | A simple, working, 32-bit ALU design. |
| 12 | 8 | 0 | 3 months ago | [FPGA_NTP_SERVER](https://github.com/Netnod/FPGA_NTP_SERVER)/898 | None |
| 12 | 7 | 0 | 4 years ago | [mriscv_vivado](https://github.com/onchipuis/mriscv_vivado)/899 | A 32-bit Microcontroller for NEXYS4-DDR fpga based on mriscv. |
| 12 | 1 | 0 | 2 years ago | [sky-machine](https://github.com/overlogged/sky-machine)/900 | An untyped lambda calculus machine designed in FPGA. |
| 12 | 1 | 0 | 1 year, 5 months ago | [DVGHV](https://github.com/cpantel/DVGHV)/901 | Designing Video Game Hardware in Verilog |
| 12 | 22 | 0 | 26 days ago | [CE202-LC-Lab-Manual](https://github.com/aut-ce/CE202-LC-Lab-Manual)/902 | Manual and Template Sources of Logic Circuit Laboratory  (Verilog Templates) |
| 12 | 0 | 1 | 2 months ago | [plaid-bib-cpld](https://github.com/schlae/plaid-bib-cpld)/903 | A replica of the Ad Lib MCA sound card, now with a CPLD instead of the bus interface chip |
| 12 | 11 | 1 | 5 years ago | [i2c-master](https://github.com/joelagnel/i2c-master)/904 | An i2c master controller implemented in Verilog |
| 12 | 0 | 0 | 6 years ago | [tetris-verilog](https://github.com/jeremycw/tetris-verilog)/905 | Verilog Tetris |
| 12 | 1 | 0 | 7 years ago | [nand2tetris-vhdl](https://github.com/kzzch/nand2tetris-vhdl)/906 | nand2tetris files converted to VHDL so I can simulate them on an FPGA |
| 12 | 4 | 0 | 3 years ago | [FPGA-video-decoder](https://github.com/aekanman/FPGA-video-decoder)/907 |  :space_invader: Design and implementation of a video decoder on an Altera Cyclone V FPGA board. |
| 12 | 3 | 1 | 8 years ago | [uart_dpi](https://github.com/rdiez/uart_dpi)/908 | DPI module for UART-based console interaction with Verilator simulations |
| 12 | 10 | 0 | 3 years ago | [nitro-parts-lib-mipi](https://github.com/BrooksEE/nitro-parts-lib-mipi)/909 | RTL for mipi serialize and deserialize |
| 11 | 8 | 0 | 4 years ago | [axi-ddr3](https://github.com/kdurant/axi-ddr3)/910 | 学习AXI接口，以及xilinx DDR3 IP使用 |
| 11 | 0 | 0 | 2 years ago | [ice-risc](https://github.com/Icenowy/ice-risc)/911 | RISC CPU by Icenowy |
| 11 | 0 | 0 | 4 months ago | [lemoncore](https://github.com/nmoroze/lemoncore)/912 | Simple RISC-V processor for FPGAs :lemon: :robot: |
| 11 | 5 | 0 | 11 months ago | [8bit_MicroComputer_Verilog](https://github.com/TheSUPERCD/8bit_MicroComputer_Verilog)/913 | This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This was developed for the Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad. |
| 11 | 3 | 0 | 2 months ago | [SpGEMM](https://github.com/sfu-arch/SpGEMM)/914 | None |
| 11 | 3 | 0 | 8 years ago | [Midi_SynthFpga](https://github.com/Thomasb81/Midi_SynthFpga)/915 | Sound synthetizer with an fpga |
| 11 | 6 | 0 | 6 years ago | [parallella-fpga-tutorials](https://github.com/yanidubin/parallella-fpga-tutorials)/916 | A place to store the code for FPGA tutorial projects I have written for the Parallella [http://parallellagram.org] |
| 11 | 3 | 0 | 2 years ago | [hilotof](https://github.com/daveshah1/hilotof)/917 | HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs |
| 11 | 4 | 1 | 4 months ago | [rodinia](https://github.com/pablomarx/rodinia)/918 | AGM bitstream utilities and decoded files from Supra |
| 11 | 3 | 1 | 10 months ago | [getting-started-with-verilog](https://github.com/aklsh/getting-started-with-verilog)/919 | Verilog modules for beginners |
| 11 | 0 | 1 | 3 years ago | [miniatom](https://github.com/janrinze/miniatom)/920 | Acorn Atom in minimal configuration for iCE40 HX8K board and ICOboard |
| 11 | 0 | 0 | 1 year, 26 days ago | [MiSTer-Arcade-DigDug](https://github.com/MrX-8B/MiSTer-Arcade-DigDug)/921 | FPGA implementation of DigDug arcade game |
| 11 | 3 | 0 | 5 months ago | [qemu-hdl-cosim](https://github.com/RSPwFPGAs/qemu-hdl-cosim)/922 | VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs |
| 11 | 8 | 0 | 6 years ago | [Multiported-RAM](https://github.com/AmeerAbdelhadi/Multiported-RAM)/923 | Modular Multi-ported SRAM-based Memory |
| 11 | 12 | 0 | 3 years ago | [single-cycle-CPU](https://github.com/Liu-YT/single-cycle-CPU)/924 | 单周期CPU设计与实现 |
| 11 | 8 | 0 | 6 years ago | [uart](https://github.com/stffrdhrn/uart)/925 | Verilog uart receiver and transmitter modules for De0 Nano |
| 11 | 6 | 0 | 4 years ago | [Example-Codes-for-Snorkeling-in-Verilog-Bay](https://github.com/ipcoregarfield/Example-Codes-for-Snorkeling-in-Verilog-Bay)/926 | Example Codes for Snorkeling in Verilog Bay |
| 11 | 0 | 0 | 8 months ago | [ctf-writeups](https://github.com/braindead/ctf-writeups)/927 | My CTF writeups |
| 11 | 0 | 0 | 2 years ago | [Virtual-Console](https://github.com/davewoo999/Virtual-Console)/928 | work in progress of a xterm-256color terminal |
| 11 | 1 | 1 | 1 year, 5 months ago | [tang-nano-lcd](https://github.com/dotcypress/tang-nano-lcd)/929 | Sipeed Tang Nano playground |
| 11 | 4 | 0 | 5 years ago | [NCL_sandbox](https://github.com/karlfant/NCL_sandbox)/930 | Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determined design in a familiar context. The tools used are Icarus verilog and gtkwave. |
| 11 | 14 | 0 | 3 years ago | [OFDM_802_11](https://github.com/phthinh/OFDM_802_11)/931 | None |
| 11 | 3 | 0 | 8 years ago | [ov](https://github.com/tmbinc/ov)/932 | None |
| 11 | 8 | 0 | 9 years ago | [Verilog-Pac-Man](https://github.com/idanw/Verilog-Pac-Man)/933 | Verilog implementation of Pac-Man made for a class's final project |
| 11 | 3 | 0 | 1 year, 6 months ago | [panog1_opl3](https://github.com/skiphansen/panog1_opl3)/934 | A port of the OPL3 to the Panologic G1 thin client |
| 11 | 10 | 0 | 3 years ago | [Mustang](https://github.com/PulseRain/Mustang)/935 | Top level of PulseRain M10 RTL design |
| 11 | 0 | 0 | 4 years ago | [fpga_nes](https://github.com/irwinz321/fpga_nes)/936 | Recreating an NES in verilog |
| 11 | 13 | 0 | 5 years ago | [Asynchronous-FIFO](https://github.com/JonathanJing/Asynchronous-FIFO)/937 | Asynchronous fifo in verilog |
| 11 | 3 | 1 | a day ago | [gateware](https://github.com/betrusted-io/gateware)/938 | IP submodules, formatted for easier CI integration |
| 11 | 7 | 0 | 6 years ago | [Verilog-SPI-Master](https://github.com/andrade824/Verilog-SPI-Master)/939 | A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen |
| 11 | 12 | 0 | 7 months ago | [FT245_interface](https://github.com/6thimage/FT245_interface)/940 | Verilog module to communicate with the FT245 interface of an FTDI FT2232H |
| 11 | 4 | 3 | 7 years ago | [ahci_mpi](https://github.com/linuxbest/ahci_mpi)/941 | an sata controller using smallest resource. |
| 11 | 5 | 0 | 3 months ago | [32-Verilog-Mini-Projects](https://github.com/sudhamshu091/32-Verilog-Mini-Projects)/942 | Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM |
| 11 | 3 | 0 | 3 years ago | [FPGAMAG18](https://github.com/aquaxis/FPGAMAG18)/943 | FPGA Magazine No.18 - RISC-V |
| 11 | 1 | 0 | 22 hours ago | [BubbleDrive8](https://github.com/ika-musume/BubbleDrive8)/944 | Konami Bubble System Bubble Memory Cartridge FBM-#101 Emulator |
| 11 | 3 | 0 | 10 years ago | [crunchy](https://github.com/tmbinc/crunchy)/945 | Distributed FPGA Number Crunching for the Masses |
| 11 | 6 | 1 | 4 years ago | [dvi_lvds](https://github.com/julbouln/dvi_lvds)/946 | DVI to LVDS Verilog converter |
| 11 | 11 | 5 | 3 years ago | [papiGB](https://github.com/diegovalverde/papiGB)/947 | Game Boy Classic fully functional FPGA implementation from scratch |
| 11 | 7 | 0 | 3 years ago | [bbcpu](https://github.com/google/bbcpu)/948 | None |
| 11 | 1 | 0 | 7 months ago | [Verilog-Playground](https://github.com/rob-ng15/Verilog-Playground)/949 | Verilog Experiment Area |
| 11 | 0 | 0 | 3 months ago | [sub-25-ns-nasdaq-itch-fpga-parser](https://github.com/mbattyani/sub-25-ns-nasdaq-itch-fpga-parser)/950 | None |
| 11 | 5 | 0 | 1 year, 7 months ago | [aq_mipi_csi2rx_ultrascaleplus](https://github.com/aquaxis/aq_mipi_csi2rx_ultrascaleplus)/951 | None |
| 11 | 3 | 1 | 1 year, 1 day ago | [core_usb_uart](https://github.com/ultraembedded/core_usb_uart)/952 | USB serial device (CDC-ACM) |
| 11 | 176 | 0 | 4 years ago | [ece4750-tut4-verilog](https://github.com/cornell-ece4750/ece4750-tut4-verilog)/953 | ECE 4750 Tutorial 4: Verilog Hardware Description Language |
| 11 | 1 | 0 | 6 years ago | [v.vga.font8x16](https://github.com/MParygin/v.vga.font8x16)/954 | Verilog VGA font generator 8 by 16 pixels |
| 11 | 5 | 0 | 4 years ago | [Single-Cycle-CPU](https://github.com/AlexZhang267/Single-Cycle-CPU)/955 | None |
| 11 | 3 | 0 | 5 months ago | [rtcclock](https://github.com/ZipCPU/rtcclock)/956 | A Real Time Clock core for FPGA's |
| 11 | 7 | 0 | Unknown | [Zedboard-OLED](https://github.com/Digilent/Zedboard-OLED)/957 | None |
| 11 | 3 | 0 | 5 years ago | [ECG-feature-extraction-using-DWT](https://github.com/dwaipayanBiswas/ECG-feature-extraction-using-DWT)/958 | Haar wavelet based Discrete wavelet transform for ECG feature extraction in Verilog |
| 11 | 4 | 8 | 2 years ago | [automatic-chainsaw](https://github.com/disaderp/automatic-chainsaw)/959 | A custom 16-bit computer |
| 11 | 1 | 0 | 11 months ago | [RISC-V](https://github.com/VenciFreeman/RISC-V)/960 | A simple RISC-V CPU written in Verilog. |
| 11 | 2 | 0 | 1 year, 6 months ago | [bfcpu](https://github.com/Icenowy/bfcpu)/961 | A simple CPU that runs Br**nf*ck code. |
| 11 | 3 | 0 | 1 year, 11 months ago | [HDLBits_Practice_verilog](https://github.com/M-HHH/HDLBits_Practice_verilog)/962 | This is a practice of verilog coding  |
| 11 | 5 | 0 | Unknown | [core_usb_bridge](https://github.com/ultraembedded/core_usb_bridge)/963 | USB -> AXI Debug Bridge |
| 11 | 5 | 0 | 9 years ago | [Open-Source-System-on-Chip-Experiment](https://github.com/progranism/Open-Source-System-on-Chip-Experiment)/964 | Just experimenting with Open Source SoCs on my Altera dev kit. |
| 11 | 7 | 1 | 9 years ago | [md5_core](https://github.com/stass/md5_core)/965 | MD5 core in verilog |
| 11 | 2 | 0 | 1 year, 5 months ago | [color3](https://github.com/tomverbeure/color3)/966 | Information about eeColor Color3 HDMI FPGA board |
| 11 | 1 | 0 | 1 year, 6 months ago | [ZC-RISCV-CORE](https://github.com/wzc810049078/ZC-RISCV-CORE)/967 | ZC RISCV CORE |
| 11 | 9 | 0 | 6 years ago | [Verilog-I2C-Slave](https://github.com/AdriaanSwan/Verilog-I2C-Slave)/968 | Verilog I2C Slave |
| 11 | 4 | 0 | 6 months ago | [Image-Classification-using-CNN-on-FPGA](https://github.com/padhi499/Image-Classification-using-CNN-on-FPGA)/969 | Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN. |
| 11 | 5 | 0 | Unknown | [numatolib](https://github.com/jblang/numatolib)/970 | Demo Library for Numato FPGA Boards |
| 11 | 3 | 2 | Unknown | [TDC](https://github.com/RuiMachado39/TDC)/971 | Verilog implementation of a tapped delay line TDC |
| 11 | 1 | 0 | 1 year, 5 months ago | [RISCV-CPU](https://github.com/wu-qing-157/RISCV-CPU)/972 | A Homework for Computer Architecture at SJTU |
| 11 | 0 | 0 | Unknown | [zevios](https://github.com/icf3/zevios)/973 | original 8bit CPU of ICF3-Z |
| 11 | 8 | 1 | Unknown | [apbi2c](https://github.com/freecores/apbi2c)/974 | APB to I2C |
| 11 | 3 | 0 | 3 months ago | [hdmi-demo](https://github.com/hdl-util/hdmi-demo)/975 | Demo of hdmi on Arduino MKR Vidor 4000 at 720p with VGA-compatible text mode and sound |
| 11 | 9 | 1 | 4 years ago | [PUF-lab](https://github.com/eriksargent/PUF-lab)/976 | FPGA implementation of a physical unclonable function for authentication |
| 11 | 2 | 0 | Unknown | [PH-Experiment](https://github.com/Fassial/PH-Experiment)/977 | 大二上学期--计算机组成与设计(PH)--实验 |
| 11 | 4 | 0 | 2 years ago | [FPGAWhack](https://github.com/jbush001/FPGAWhack)/978 | Video Effects on VGA |
| 11 | 10 | 2 | 3 years ago | [Verilog-Snippets](https://github.com/deepvyas/Verilog-Snippets)/979 | Verilog Snippets for partial fulfilment of CS-F342 Computer Architecture,BITS Pilani |
| 11 | 8 | 0 | 4 years ago | [ice40-stm32-sdram](https://github.com/knielsen/ice40-stm32-sdram)/980 | Test code to talk from STM32 MCU over FSMC to SDRAM on ICE40 FPGA |
| 11 | 8 | 0 | 1 year, 11 months ago | [A-Single-Path-Delay-32-Point-FFT-Processor](https://github.com/jasonlin316/A-Single-Path-Delay-32-Point-FFT-Processor)/981 | A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76. |
| 11 | 13 | 0 | 3 years ago | [PulseRain_FP51_MCU](https://github.com/PulseRain/PulseRain_FP51_MCU)/982 | PulseRain FP51 MCU, with peripherals |
| 11 | 2 | 0 | Unknown | [ddec](https://github.com/zhelnio/ddec)/983 | Digital Design Express Course |
| 11 | 4 | 0 | Unknown | [orpsoc](https://github.com/lgeek/orpsoc)/984 | [abandoned fork] OpenRISC Reference Platform SoC |
| 11 | 0 | 0 | Unknown | [JagNetlists](https://github.com/Torlus/JagNetlists)/985 | Atari Jaguar netlists compiler |
| 11 | 4 | 1 | Unknown | [n64rgb](https://github.com/mrehkopf/n64rgb)/986 | Alternative configuration for CPLD style N64 RGB mods to produce crisper image in 240p/288p modes |
| 11 | 9 | 0 | Unknown | [ft232h-core](https://github.com/xiedidan/ft232h-core)/987 | None |
| 11 | 3 | 1 | Unknown | [led_matrix_tinyfpga_a2](https://github.com/attie/led_matrix_tinyfpga_a2)/988 | Driving an LED Matrix with a TinyFPGA |
| 11 | 5 | 0 | Unknown | [usb1_device](https://github.com/www-asics-ws/usb1_device)/989 | USB 1.1 Device IP Core |
| 11 | 1 | 0 | 3 years ago | [mips-cpu](https://github.com/synxlin/mips-cpu)/990 | The Verilog implementation of five-stage-pipelined MIPS CPU (Classic RISC pipeline) |
| 11 | 1 | 0 | Unknown | [FPGAOL-Examples](https://github.com/fandahao17/FPGAOL-Examples)/991 | Example programs for FPGAOL |
| 11 | 1 | 0 | 2 months ago | [xor_vga_fpga](https://github.com/mattvenn/xor_vga_fpga)/992 | playing with XOR video patterns on an FPGA |
| 11 | 5 | 0 | 6 years ago | [md5cracker](https://github.com/zhemao/md5cracker)/993 | A Hardware MD5 Cracker for the Cyclone V SoC |
| 11 | 0 | 0 | 3 years ago | [brainf__k_CPU](https://github.com/moizumi99/brainf__k_CPU)/994 | A CPU that executes brainf**k language. Can be synthesized on FPGA |
| 11 | 2 | 0 | 1 year, 3 months ago | [wbpmic](https://github.com/ZipCPU/wbpmic)/995 | Wishbone controller for a MEMs microphone |
| 11 | 2 | 0 | 1 year, 11 months ago | [100DayFPGA](https://github.com/abhishek-kakkar/100DayFPGA)/996 | Scratchpad repository for the 100-day FPGA challenge |
| 11 | 7 | 0 | Unknown | [Verilog-Adders](https://github.com/mongrelgem/Verilog-Adders)/997 | Implementing Different Adder Structures in Verilog |
| 11 | 7 | 0 | 1 year, 2 months ago | [DRUM](https://github.com/scale-lab/DRUM)/998 | The Verilog source code for DRUM approximate multiplier.  |
| 11 | 7 | 0 | 8 months ago | [Chisel-FFT](https://github.com/IA-C-Lab-Fudan/Chisel-FFT)/999 | FFT wrriten in Chisel |
| 10 | 11 | 17 | 9 years ago | [G729_CODE](https://github.com/nickrobinson/G729_CODE)/1000 | G.729 Encoder |