Microchip Technology Inc. ATSAMA5D27 1.0 No description available. CA5 r0p1 little false false 4 false 32 32 0x20 read-write 0x00000000 0xFFFFFFFF DDR_RAM 0x20900000 0x2000000 CSR 0xF0000000 0xfffffff ACC Analog Comparator Controller 0xF804A000 0x0 0x8 registers 0xE4 0x8 registers CR Control Register 0x0 0x20 write-only SWRST Software Reset [0:0] read-write MR Mode Register 0x4 0x20 read-write ACEN Analog Comparator Enable [8:8] read-write true DIS Analog comparator disabled. 0 EN Analog comparator enabled. 1 INV Invert Comparator Output [12:12] read-write true DIS Analog comparator output is directly processed. 0 EN Analog comparator output is inverted prior to being processed. 1 WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 4277059 WPSR Write Protection Status Register 0xE8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write ADC Analog-to-Digital Converter 0xFC030000 0x0 0x1C registers 0x20 0x28 registers 0x4C 0x8 registers 0x94 0x4 registers 0xB0 0x14 registers 0xD4 0xC registers 0xE4 0x8 registers ACR Analog Control Register 0x94 0x20 read-write PENDETSENS Pen Detection Sensitivity [1:0] read-write 0 3 IBCTL ADC Bias Current Control [9:8] read-write 0 3 CDR Channel Data Register 0x50 0x20 read-only DATA Converted Data [13:0] read-write 0 16383 CECR Channel Error Correction Register 0xD8 0x20 read-write ECORR0 Error Correction Enable for channel 0 [0:0] read-write ECORR1 Error Correction Enable for channel 1 [1:1] read-write ECORR2 Error Correction Enable for channel 2 [2:2] read-write ECORR3 Error Correction Enable for channel 3 [3:3] read-write ECORR4 Error Correction Enable for channel 4 [4:4] read-write ECORR5 Error Correction Enable for channel 5 [5:5] read-write ECORR6 Error Correction Enable for channel 6 [6:6] read-write ECORR7 Error Correction Enable for channel 7 [7:7] read-write ECORR8 Error Correction Enable for channel 8 [8:8] read-write ECORR9 Error Correction Enable for channel 9 [9:9] read-write ECORR10 Error Correction Enable for channel 10 [10:10] read-write ECORR11 Error Correction Enable for channel 11 [11:11] read-write CHDR Channel Disable Register 0x14 0x20 write-only CH0 Channel 0 Disable [0:0] read-write CH1 Channel 1 Disable [1:1] read-write CH2 Channel 2 Disable [2:2] read-write CH3 Channel 3 Disable [3:3] read-write CH4 Channel 4 Disable [4:4] read-write CH5 Channel 5 Disable [5:5] read-write CH6 Channel 6 Disable [6:6] read-write CH7 Channel 7 Disable [7:7] read-write CH8 Channel 8 Disable [8:8] read-write CH9 Channel 9 Disable [9:9] read-write CH10 Channel 10 Disable [10:10] read-write CH11 Channel 11 Disable [11:11] read-write CHER Channel Enable Register 0x10 0x20 write-only CH0 Channel 0 Enable [0:0] read-write CH1 Channel 1 Enable [1:1] read-write CH2 Channel 2 Enable [2:2] read-write CH3 Channel 3 Enable [3:3] read-write CH4 Channel 4 Enable [4:4] read-write CH5 Channel 5 Enable [5:5] read-write CH6 Channel 6 Enable [6:6] read-write CH7 Channel 7 Enable [7:7] read-write CH8 Channel 8 Enable [8:8] read-write CH9 Channel 9 Enable [9:9] read-write CH10 Channel 10 Enable [10:10] read-write CH11 Channel 11 Enable [11:11] read-write CHSR Channel Status Register 0x18 0x20 read-only CH0 Channel 0 Status [0:0] read-write CH1 Channel 1 Status [1:1] read-write CH2 Channel 2 Status [2:2] read-write CH3 Channel 3 Status [3:3] read-write CH4 Channel 4 Status [4:4] read-write CH5 Channel 5 Status [5:5] read-write CH6 Channel 6 Status [6:6] read-write CH7 Channel 7 Status [7:7] read-write CH8 Channel 8 Status [8:8] read-write CH9 Channel 9 Status [9:9] read-write CH10 Channel 10 Status [10:10] read-write CH11 Channel 11 Status [11:11] read-write COR Channel Offset Register 0x4C 0x20 read-write DIFF0 Differential Inputs for Channel 0 [16:16] read-write DIFF1 Differential Inputs for Channel 1 [17:17] read-write DIFF2 Differential Inputs for Channel 2 [18:18] read-write DIFF3 Differential Inputs for Channel 3 [19:19] read-write DIFF4 Differential Inputs for Channel 4 [20:20] read-write DIFF5 Differential Inputs for Channel 5 [21:21] read-write DIFF6 Differential Inputs for Channel 6 [22:22] read-write DIFF7 Differential Inputs for Channel 7 [23:23] read-write DIFF8 Differential Inputs for Channel 8 [24:24] read-write DIFF9 Differential Inputs for Channel 9 [25:25] read-write DIFF10 Differential Inputs for Channel 10 [26:26] read-write DIFF11 Differential Inputs for Channel 11 [27:27] read-write CR Control Register 0x0 0x20 write-only SWRST Software Reset [0:0] read-write START Start Conversion [1:1] read-write TSCALIB Touchscreen Calibration [2:2] read-write CMPRST Comparison Restart [4:4] read-write CVR Correction Values Register 0xD4 0x20 read-write OFFSETCORR Offset Correction [15:0] read-write 0 65535 GAINCORR Gain Correction [31:16] read-write 0 65535 CWR Compare Window Register 0x44 0x20 read-write LOWTHRES Low Threshold [13:0] read-write 0 16383 HIGHTHRES High Threshold [29:16] read-write 0 16383 EMR Extended Mode Register 0x40 0x20 read-write CMPMODE Comparison Mode [1:0] read-write true LOW When the converted data is lower than the low threshold of the window, generates the COMPE flag in ADC_ISR or, in Partial Wakeup mode, defines the conditions to exit system from Wait mode. 0 HIGH When the converted data is higher than the high threshold of the window, generates the COMPE flag in ADC_ISR or, in Partial Wakeup mode, defines the conditions to exit system from Wait mode. 1 IN When the converted data is in the comparison window, generates the COMPE flag in ADC_ISR or, in Partial Wakeup mode, defines the conditions to exit system from Wait mode. 2 OUT When the converted data is out of the comparison window, generates the COMPE flag in ADC_ISR or, in Partial Wakeup mode, defines the conditions to exit system from Wait mode. 3 CMPTYPE Comparison Type [2:2] read-write true FLAG_ONLY Any conversion is performed and comparison function drives the COMPE flag. 0 START_CONDITION Comparison conditions must be met to start the storage of all conversions until the CMPRST bit is set. 1 CMPSEL Comparison Selected Channel [7:4] read-write 0 15 CMPALL Compare All Channels [9:9] read-write CMPFILTER Compare Event Filtering [13:12] read-write 0 3 OSR Over Sampling Rate [17:16] read-write true NO_AVERAGE No averaging. ADC sample rate is maximum. 0 OSR4 1-bit enhanced resolution by averaging. ADC sample rate divided by 4. 1 OSR16 2-bit enhanced resolution by averaging. ADC sample rate divided by 16. 2 ASTE Averaging on Single Trigger Event [20:20] read-write true MULTI_TRIG_AVERAGE The average requests several trigger events. 0 SINGLE_TRIG_AVERAGE The average requests only one trigger event. 1 SRCCLK External Clock Selection [21:21] read-write true PERIPH_CLK The peripheral clock is the source for the ADC prescaler. 0 GCLK GCLK is the source clock for the ADC prescaler, thus the ADC clock can be independent of the core/peripheral clock. 1 TAG Tag of ADC_LCDR [24:24] read-write SIGNMODE Sign Mode [26:25] read-write true SE_UNSG_DF_SIGN Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. 0 SE_SIGN_DF_UNSG Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. 1 ALL_UNSIGNED All channels: Unsigned conversions. 2 ALL_SIGNED All channels: Signed conversions. 3 ADCMODE ADC Running Mode [29:28] read-write true NORMAL Normal mode of operation. 0 OFFSET_ERROR Offset Error mode to measure the offset error. See Table 7-6. 1 GAIN_ERROR_HIGH Gain Error mode to measure the gain error. See Table 7-6. 2 GAIN_ERROR_LOW Gain Error mode to measure the gain error. See Table 7-6. 3 IDR Interrupt Disable Register 0x28 0x20 write-only EOC0 End of Conversion Interrupt Disable 0 [0:0] read-write EOC1 End of Conversion Interrupt Disable 1 [1:1] read-write EOC2 End of Conversion Interrupt Disable 2 [2:2] read-write EOC3 End of Conversion Interrupt Disable 3 [3:3] read-write EOC4 End of Conversion Interrupt Disable 4 [4:4] read-write EOC5 End of Conversion Interrupt Disable 5 [5:5] read-write EOC6 End of Conversion Interrupt Disable 6 [6:6] read-write EOC7 End of Conversion Interrupt Disable 7 [7:7] read-write EOC8 End of Conversion Interrupt Disable 8 [8:8] read-write EOC9 End of Conversion Interrupt Disable 9 [9:9] read-write EOC10 End of Conversion Interrupt Disable 10 [10:10] read-write EOC11 End of Conversion Interrupt Disable 11 [11:11] read-write LCCHG Last Channel Change Interrupt Disable [19:19] read-write XRDY Touchscreen Measure XPOS Ready Interrupt Disable [20:20] read-write YRDY Touchscreen Measure YPOS Ready Interrupt Disable [21:21] read-write PRDY Touchscreen Measure Pressure Ready Interrupt Disable [22:22] read-write DRDY Data Ready Interrupt Disable [24:24] read-write GOVRE General Overrun Error Interrupt Disable [25:25] read-write COMPE Comparison Event Interrupt Disable [26:26] read-write PEN Pen Contact Interrupt Disable [29:29] read-write NOPEN No Pen Contact Interrupt Disable [30:30] read-write IER Interrupt Enable Register 0x24 0x20 write-only EOC0 End of Conversion Interrupt Enable 0 [0:0] read-write EOC1 End of Conversion Interrupt Enable 1 [1:1] read-write EOC2 End of Conversion Interrupt Enable 2 [2:2] read-write EOC3 End of Conversion Interrupt Enable 3 [3:3] read-write EOC4 End of Conversion Interrupt Enable 4 [4:4] read-write EOC5 End of Conversion Interrupt Enable 5 [5:5] read-write EOC6 End of Conversion Interrupt Enable 6 [6:6] read-write EOC7 End of Conversion Interrupt Enable 7 [7:7] read-write EOC8 End of Conversion Interrupt Enable 8 [8:8] read-write EOC9 End of Conversion Interrupt Enable 9 [9:9] read-write EOC10 End of Conversion Interrupt Enable 10 [10:10] read-write EOC11 End of Conversion Interrupt Enable 11 [11:11] read-write LCCHG Last Channel Change Interrupt Enable [19:19] read-write XRDY Touchscreen Measure XPOS Ready Interrupt Enable [20:20] read-write YRDY Touchscreen Measure YPOS Ready Interrupt Enable [21:21] read-write PRDY Touchscreen Measure Pressure Ready Interrupt Enable [22:22] read-write DRDY Data Ready Interrupt Enable [24:24] read-write GOVRE General Overrun Error Interrupt Enable [25:25] read-write COMPE Comparison Event Interrupt Enable [26:26] read-write PEN Pen Contact Interrupt Enable [29:29] read-write NOPEN No Pen Contact Interrupt Enable [30:30] read-write IMR Interrupt Mask Register 0x2C 0x20 read-only EOC0 End of Conversion Interrupt Mask 0 [0:0] read-write EOC1 End of Conversion Interrupt Mask 1 [1:1] read-write EOC2 End of Conversion Interrupt Mask 2 [2:2] read-write EOC3 End of Conversion Interrupt Mask 3 [3:3] read-write EOC4 End of Conversion Interrupt Mask 4 [4:4] read-write EOC5 End of Conversion Interrupt Mask 5 [5:5] read-write EOC6 End of Conversion Interrupt Mask 6 [6:6] read-write EOC7 End of Conversion Interrupt Mask 7 [7:7] read-write EOC8 End of Conversion Interrupt Mask 8 [8:8] read-write EOC9 End of Conversion Interrupt Mask 9 [9:9] read-write EOC10 End of Conversion Interrupt Mask 10 [10:10] read-write EOC11 End of Conversion Interrupt Mask 11 [11:11] read-write LCCHG Last Channel Change Interrupt Disable [19:19] read-write XRDY Touchscreen Measure XPOS Ready Interrupt Mask [20:20] read-write YRDY Touchscreen Measure YPOS Ready Interrupt Mask [21:21] read-write PRDY Touchscreen Measure Pressure Ready Interrupt Mask [22:22] read-write DRDY Data Ready Interrupt Mask [24:24] read-write GOVRE General Overrun Error Interrupt Mask [25:25] read-write COMPE Comparison Event Interrupt Mask [26:26] read-write PEN Pen Contact Interrupt Mask [29:29] read-write NOPEN No Pen Contact Interrupt Mask [30:30] read-write ISR Interrupt Status Register 0x30 0x20 read-only EOC0 End of Conversion 0 (automatically set / cleared) [0:0] read-write EOC1 End of Conversion 1 (automatically set / cleared) [1:1] read-write EOC2 End of Conversion 2 (automatically set / cleared) [2:2] read-write EOC3 End of Conversion 3 (automatically set / cleared) [3:3] read-write EOC4 End of Conversion 4 (automatically set / cleared) [4:4] read-write EOC5 End of Conversion 5 (automatically set / cleared) [5:5] read-write EOC6 End of Conversion 6 (automatically set / cleared) [6:6] read-write EOC7 End of Conversion 7 (automatically set / cleared) [7:7] read-write EOC8 End of Conversion 8 (automatically set / cleared) [8:8] read-write EOC9 End of Conversion 9 (automatically set / cleared) [9:9] read-write EOC10 End of Conversion 10 (automatically set / cleared) [10:10] read-write EOC11 End of Conversion 11 (automatically set / cleared) [11:11] read-write LCCHG Last Channel Change (cleared on read) [19:19] read-write XRDY Touchscreen XPOS Measure Ready (cleared on read) [20:20] read-write YRDY Touchscreen YPOS Measure Ready (cleared on read) [21:21] read-write PRDY Touchscreen Pressure Measure Ready (cleared on read) [22:22] read-write DRDY Data Ready (automatically set / cleared) [24:24] read-write GOVRE General Overrun Error (cleared on read) [25:25] read-write COMPE Comparison Event (cleared on read) [26:26] read-write PEN Pen contact (cleared on read) [29:29] read-write NOPEN No Pen Contact (cleared on read) [30:30] read-write PENS Pen Detect Status [31:31] read-write LCCWR Last Channel Compare Window Register 0x38 0x20 read-write LOWTHRES Low Threshold [11:0] read-write 0 4095 HIGHTHRES High Threshold [27:16] read-write 0 4095 LCDR Last Converted Data Register 0x20 0x20 read-only LDATA Last Data Converted [15:0] read-write 0 65535 CHNBOSR Channel Number in Oversampling Mode [28:24] read-write 0 31 LCTMR Last Channel Trigger Mode Register 0x34 0x20 read-write DUALTRIG Dual Trigger ON [0:0] read-write CMPMOD Last Channel Comparison Mode [5:4] read-write true LOW Generates the LCCHG flag in ADC_ISR when the converted data is lower than the low threshold of the window. 0 HIGH Generates the LCCHG flag in ADC_ISR when the converted data is higher than the high threshold of the window. 1 IN Generates the LCCHG flag in ADC_ISR when the converted data is in the comparison window. 2 OUT Generates the LCCHG flag in ADC_ISR when the converted data is out of the comparison window. 3 MR Mode Register 0x4 0x20 read-write TRGSEL Trigger Selection [3:1] read-write true ADC_TRIG0 ADTRG 0 ADC_TRIG1 TIOA0 1 ADC_TRIG2 TIOA1 2 ADC_TRIG3 TIOA2 3 ADC_TRIG4 PWM event line 0 4 ADC_TRIG5 PWM event line 1 5 ADC_TRIG6 TIOA3 6 ADC_TRIG7 RTCOUT0 7 SLEEP Sleep Mode [5:5] read-write true NORMAL Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions. 0 SLEEP Sleep Mode: The wakeup time can be modified by programming the FWUP bit. 1 FWUP Fast Wakeup [6:6] read-write true OFF If SLEEP is 1, then both ADC core and reference voltage circuitry are OFF between conversions 0 ON If SLEEP is 1, then Fast Wakeup Sleep mode: The voltage reference is ON between conversions and ADC core is OFF 1 PRESCAL Prescaler Rate Selection [15:8] read-write 0 255 STARTUP Startup Time [19:16] read-write true SUT0 0 periods of ADCCLK 0 SUT8 8 periods of ADCCLK 1 SUT16 16 periods of ADCCLK 2 SUT24 24 periods of ADCCLK 3 SUT64 64 periods of ADCCLK 4 SUT80 80 periods of ADCCLK 5 SUT96 96 periods of ADCCLK 6 SUT112 112 periods of ADCCLK 7 SUT512 512 periods of ADCCLK 8 SUT576 576 periods of ADCCLK 9 SUT640 640 periods of ADCCLK 10 SUT704 704 periods of ADCCLK 11 SUT768 768 periods of ADCCLK 12 SUT832 832 periods of ADCCLK 13 SUT896 896 periods of ADCCLK 14 SUT960 960 periods of ADCCLK 15 ANACH Analog Change [23:23] read-write true NONE No analog change on channel switching: DIFF0 is used for all channels. 0 ALLOWED Allows different analog settings for each channel. See ADC Channel Offset RegisterChannel Configuration Register. 1 TRACKTIM Tracking Time [27:24] read-write 0 15 TRANSFER Transfer Time [29:28] read-write 0 3 MAXSPEED Maximum Sampling Rate Enable in Freerun Mode [30:30] read-write USEQ Use Sequence Enable [31:31] read-write true NUM_ORDER Normal mode: The controller converts channels in a simple numeric order depending only on the channel index. 0 REG_ORDER User Sequence mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert the same channel several times. 1 OVER Overrun Status Register 0x3C 0x20 read-only OVRE0 Overrun Error 0 [0:0] read-write OVRE1 Overrun Error 1 [1:1] read-write OVRE2 Overrun Error 2 [2:2] read-write OVRE3 Overrun Error 3 [3:3] read-write OVRE4 Overrun Error 4 [4:4] read-write OVRE5 Overrun Error 5 [5:5] read-write OVRE6 Overrun Error 6 [6:6] read-write OVRE7 Overrun Error 7 [7:7] read-write OVRE8 Overrun Error 8 [8:8] read-write OVRE9 Overrun Error 9 [9:9] read-write OVRE10 Overrun Error 10 [10:10] read-write OVRE11 Overrun Error 11 [11:11] read-write PRESSR Touchscreen Pressure Register 0xBC 0x20 read-only Z1 Data of Z1 Measurement [11:0] read-write 0 4095 Z2 Data of Z2 Measurement [27:16] read-write 0 4095 SEQR1 Channel Sequence Register 1 0x8 0x20 read-write USCH1 User Sequence Number 1 [3:0] read-write 0 15 USCH2 User Sequence Number 2 [7:4] read-write 0 15 USCH3 User Sequence Number 3 [11:8] read-write 0 15 USCH4 User Sequence Number 4 [15:12] read-write 0 15 USCH5 User Sequence Number 5 [19:16] read-write 0 15 USCH6 User Sequence Number 6 [23:20] read-write 0 15 USCH7 User Sequence Number 7 [27:24] read-write 0 15 USCH8 User Sequence Number 8 [31:28] read-write 0 15 SEQR2 Channel Sequence Register 2 0xC 0x20 read-write USCH9 User Sequence Number 9 [3:0] read-write 0 15 USCH10 User Sequence Number 10 [7:4] read-write 0 15 USCH11 User Sequence Number 11 [11:8] read-write 0 15 TRGR Trigger Register 0xC0 0x20 read-write TRGMOD Trigger Mode [2:0] read-write true NO_TRIGGER No trigger, only software trigger can start conversions 0 EXT_TRIG_RISE External trigger rising edge 1 EXT_TRIG_FALL External trigger falling edge 2 EXT_TRIG_ANY External trigger any edge 3 PEN_TRIG Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touchscreen only mode) 4 PERIOD_TRIG ADC internal periodic trigger (see field TRGPER) 5 CONTINUOUS Continuous mode 6 TRGPER Trigger Period [31:16] read-write 0 65535 TSCVR Touchscreen Correction Values Register 0xDC 0x20 read-write TSOFFSETCORR Touchscreen Offset Correction [15:0] read-write 0 65535 TSGAINCORR Touchscreen Gain Correction [31:16] read-write 0 65535 TSMR Touchscreen Mode Register 0xB0 0x20 read-write TSMODE Touchscreen Mode [1:0] read-write true NONE No Touchscreen 0 _4_WIRE_NO_PM 4-wire Touchscreen without pressure measurement 1 _4_WIRE 4-wire Touchscreen with pressure measurement 2 _5_WIRE 5-wire Touchscreen 3 TSAV Touchscreen Average [5:4] read-write true NO_FILTER No Filtering. Only one ADC conversion per measure 0 AVG2CONV Averages 2 ADC conversions 1 AVG4CONV Averages 4 ADC conversions 2 AVG8CONV Averages 8 ADC conversions 3 TSFREQ Touchscreen Frequency [11:8] read-write 0 15 TSSCTIM Touchscreen Switches Closure Time [19:16] read-write 0 15 NOTSDMA No TouchScreen DMA [22:22] read-write PENDET Pen Contact Detection Enable [24:24] read-write PENDBC Pen Detect Debouncing Period [31:28] read-write 0 15 WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 4277315 WPSR Write Protection Status Register 0xE8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [23:8] read-write 0 65535 XPOSR Touchscreen X Position Register 0xB4 0x20 read-only XPOS X Position [11:0] read-write 0 4095 XSCALE Scale of XPOS [27:16] read-write 0 4095 YPOSR Touchscreen Y Position Register 0xB8 0x20 read-only YPOS Y Position [11:0] read-write 0 4095 YSCALE Scale of YPOS [27:16] read-write 0 4095 AES Advanced Encryption Standard 0xF002C000 0x0 0x8 registers 0x10 0x14 registers 0x40 0x4 registers 0x50 0x4 registers 0x60 0x4 registers 0x70 0xC registers 0x88 0x4 registers 0x98 0x8 registers 0xB0 0x8 registers 0xC0 0x4 registers 0xD0 0x4 registers AADLENR Additional Authenticated Data Length Register 0x70 0x20 read-write AADLEN Additional Authenticated Data Length [31:0] read-write 0 4294967295 ALPHAR Alpha Word Register 0xD0 0x20 write-only ALPHA Alpha Word x [31:0] read-write 0 4294967295 BCNT Byte Counter Register 0xB4 0x20 read-write BCNT Auto Padding Byte Counter [31:0] read-write 0 4294967295 CLENR Plaintext/Ciphertext Length Register 0x74 0x20 read-write CLEN Plaintext/Ciphertext Length [31:0] read-write 0 4294967295 CR Control Register 0x0 0x20 write-only START Start Processing [0:0] read-write SWRST Software Reset [8:8] read-write CTRR GCM Encryption Counter Value Register 0x98 0x20 read-only CTR GCM Encryption Counter [31:0] read-write 0 4294967295 EMR Extended Mode Register 0xB0 0x20 read-write APEN Auto Padding Enable [0:0] read-write APM Auto Padding Mode [1:1] read-write PLIPEN Protocol Layer Improved Performance Enable [4:4] read-write PLIPD Protocol Layer Improved Performance Decipher [5:5] read-write PADLEN Auto Padding Length [15:8] read-write 0 255 NHEAD IPSEC Next Header [23:16] read-write 0 255 GCMHR GCM H Word Register 0x9C 0x20 read-write H GCM H Word x [31:0] read-write 0 4294967295 GHASHR GCM Intermediate Hash Word Register 0x78 0x20 read-write GHASH Intermediate GCM Hash Word x [31:0] read-write 0 4294967295 IDATAR Input Data Register 0x40 0x20 write-only IDATA Input Data Word [31:0] read-write 0 4294967295 IDR Interrupt Disable Register 0x14 0x20 write-only DATRDY Data Ready Interrupt Disable [0:0] read-write URAD Unspecified Register Access Detection Interrupt Disable [8:8] read-write TAGRDY GCM Tag Ready Interrupt Disable [16:16] read-write EOPAD End of Padding Interrupt Disable [17:17] read-write PLENERR Padding Length Error Interrupt Disable [18:18] read-write IER Interrupt Enable Register 0x10 0x20 write-only DATRDY Data Ready Interrupt Enable [0:0] read-write URAD Unspecified Register Access Detection Interrupt Enable [8:8] read-write TAGRDY GCM Tag Ready Interrupt Enable [16:16] read-write EOPAD End of Padding Interrupt Enable [17:17] read-write PLENERR Padding Length Error Interrupt Enable [18:18] read-write IMR Interrupt Mask Register 0x18 0x20 read-only DATRDY Data Ready Interrupt Mask [0:0] read-write URAD Unspecified Register Access Detection Interrupt Mask [8:8] read-write TAGRDY GCM Tag Ready Interrupt Mask [16:16] read-write EOPAD End of Padding Interrupt Mask [17:17] read-write PLENERR Padding Length Error Interrupt Mask [18:18] read-write ISR Interrupt Status Register 0x1C 0x20 read-only DATRDY Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) [0:0] read-write URAD Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) [8:8] read-write URAT Unspecified Register Access (cleared by writing SWRST in AES_CR) [15:12] read-write true IDR_WR_PROCESSING Input Data register written during the data processing when SMOD = 2 mode. 0 ODR_RD_PROCESSING Output Data register read during the data processing. 1 MR_WR_PROCESSING Mode register written during the data processing. 2 ODR_RD_SUBKGEN Output Data register read during the sub-keys generation. 3 MR_WR_SUBKGEN Mode register written during the sub-keys generation. 4 WOR_RD_ACCESS Write-only register read access. 5 TAGRDY GCM Tag Ready [16:16] read-write EOPAD End of Padding [17:17] read-write PLENERR Padding Length Error [18:18] read-write IVR Initialization Vector Register 0x60 0x20 write-only IV Initialization Vector [31:0] read-write 0 4294967295 KEYWR Key Word Register 0x20 0x20 write-only KEYW Key Word [31:0] read-write 0 4294967295 MR Mode Register 0x4 0x20 read-write CIPHER Processing Mode [0:0] read-write GTAGEN GCM Automatic Tag Generation Enable [1:1] read-write DUALBUFF Dual Input Buffer [3:3] read-write true INACTIVE AES_IDATARx cannot be written during processing of previous block. 0 ACTIVE AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. 1 PROCDLY Processing Delay [7:4] read-write 0 15 SMOD Start Mode [9:8] read-write true MANUAL_START Manual Mode 0 AUTO_START Auto Mode 1 IDATAR0_START AES_IDATAR0 access only Auto Mode (DMA) 2 KEYSIZE Key Size [11:10] read-write true AES128 AES Key Size is 128 bits 0 AES192 AES Key Size is 192 bits 1 AES256 AES Key Size is 256 bits 2 OPMOD Operating Mode [14:12] read-write true ECB ECB: Electronic Codebook mode 0 CBC CBC: Cipher Block Chaining mode 1 OFB OFB: Output Feedback mode 2 CFB CFB: Cipher Feedback mode 3 CTR CTR: Counter mode (16-bit internal counter) 4 GCM GCM: Galois/Counter mode 5 XTS XTS: XEX-based tweaked-codebook mode 6 LOD Last Output Data Mode [15:15] read-write CFBS Cipher Feedback Data Size [18:16] read-write true SIZE_128BIT 128-bit 0 SIZE_64BIT 64-bit 1 SIZE_32BIT 32-bit 2 SIZE_16BIT 16-bit 3 SIZE_8BIT 8-bit 4 CKEY Key [23:20] read-write true PASSWD This field must be written with 0xE the first time AES_MR is programmed. For subsequent programming of AES_MR, any value can be written, including that of 0xE.Always reads as 0. 14 ODATAR Output Data Register 0x50 0x20 read-only ODATA Output Data [31:0] read-write 0 4294967295 TAGR GCM Authentication Tag Word Register 0x88 0x20 read-only TAG GCM Authentication Tag x [31:0] read-write 0 4294967295 TWR Tweak Word Register 0xC0 0x20 read-write TWEAK Tweak Word x [31:0] read-write 0 4294967295 AESB Advanced Encryption Standard Bridge 0xF001C000 0x0 0x8 registers 0x10 0x14 registers 0x40 0x4 registers 0x50 0x4 registers 0x60 0x4 registers CR Control Register 0x0 0x20 write-only START Start Processing [0:0] read-write SWRST Software Reset [8:8] read-write IDATAR Input Data Register 0x40 0x20 write-only IDATA Input Data Word [31:0] read-write 0 4294967295 IDR Interrupt Disable Register 0x14 0x20 write-only DATRDY Data Ready Interrupt Disable [0:0] read-write URAD Unspecified Register Access Detection Interrupt Disable [8:8] read-write IER Interrupt Enable Register 0x10 0x20 write-only DATRDY Data Ready Interrupt Enable [0:0] read-write URAD Unspecified Register Access Detection Interrupt Enable [8:8] read-write IMR Interrupt Mask Register 0x18 0x20 read-only DATRDY Data Ready Interrupt Mask [0:0] read-write URAD Unspecified Register Access Detection Interrupt Mask [8:8] read-write ISR Interrupt Status Register 0x1C 0x20 read-only DATRDY Data Ready [0:0] read-write URAD Unspecified Register Access Detection Status [8:8] read-write URAT Unspecified Register Access [15:12] read-write true IDR_WR_PROCESSING Input Data Register written during the data processing when SMOD = 0x2 mode 0 ODR_RD_PROCESSING Output Data Register read during the data processing 1 MR_WR_PROCESSING Mode Register written during the data processing 2 ODR_RD_SUBKGEN Output Data Register read during the sub-keys generation 3 MR_WR_SUBKGEN Mode Register written during the sub-keys generation 4 WOR_RD_ACCESS Write-only register read access 5 IVR Initialization Vector Register 0x60 0x20 write-only IV Initialization Vector [31:0] read-write 0 4294967295 KEYWR Key Word Register 0x20 0x20 write-only KEYW Key Word [31:0] read-write 0 4294967295 MR Mode Register 0x4 0x20 read-write CIPHER Processing Mode [0:0] read-write AAHB Automatic Bridge Mode [2:2] read-write DUALBUFF Dual Input Buffer [3:3] read-write true INACTIVE AESB_IDATARx cannot be written during processing of previous block. 0 ACTIVE AESB_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. 1 PROCDLY Processing Delay [7:4] read-write 0 15 SMOD Start Mode [9:8] read-write true MANUAL_START Manual mode 0 AUTO_START Auto mode 1 IDATAR0_START AESB_IDATAR0 access only Auto mode 2 OPMOD Operating Mode [14:12] read-write true ECB Electronic Code Book mode 0 CBC Cipher Block Chaining mode 1 CTR Counter mode (16-bit internal counter) 4 LOD Last Output Data Mode [15:15] read-write CKEY Key [23:20] read-write true PASSWD This field must be written with 0xE the first time that AESB_MR is programmed. For subsequent programming of the AESB_MR register, any value can be written, including that of 0xE.Always reads as 0. 14 ODATAR Output Data Register 0x50 0x20 read-only ODATA Output Data [31:0] read-write 0 4294967295 AIC Advanced Interrupt Controller 0xFC020000 0x0 0xC registers 0x10 0xC registers 0x20 0x30 registers 0x6C 0x4 registers 0xE4 0x8 registers CISR Core Interrupt Status Register 0x34 0x20 read-only NFIQ NFIQ Status [0:0] read-write NIRQ NIRQ Status [1:1] read-write DCR Debug Control Register 0x6C 0x20 read-write PROT Protection Mode [0:0] read-write GMSK General Interrupt Mask [1:1] read-write EOICR End of Interrupt Command Register 0x38 0x20 write-only ENDIT Interrupt Processing Complete Command [0:0] read-write FVR FIQ Vector Register 0x14 0x20 read-only FIQV FIQ Vector Register [31:0] read-write 0 4294967295 ICCR Interrupt Clear Command Register 0x48 0x20 write-only INTCLR Interrupt Clear [0:0] read-write IDCR Interrupt Disable Command Register 0x44 0x20 write-only INTD Interrupt Disable [0:0] read-write IECR Interrupt Enable Command Register 0x40 0x20 write-only INTEN Interrupt Enable [0:0] read-write IMR Interrupt Mask Register 0x30 0x20 read-only INTM Interrupt Mask [0:0] read-write IPR0 Interrupt Pending Register 0 0x20 0x20 read-only FIQ Interrupt Pending [0:0] read-write PID1 Interrupt Pending [1:1] read-write PID2 Interrupt Pending [2:2] read-write PID3 Interrupt Pending [3:3] read-write PID4 Interrupt Pending [4:4] read-write PID5 Interrupt Pending [5:5] read-write PID6 Interrupt Pending [6:6] read-write PID7 Interrupt Pending [7:7] read-write PID8 Interrupt Pending [8:8] read-write PID9 Interrupt Pending [9:9] read-write PID10 Interrupt Pending [10:10] read-write PID11 Interrupt Pending [11:11] read-write PID12 Interrupt Pending [12:12] read-write PID13 Interrupt Pending [13:13] read-write PID14 Interrupt Pending [14:14] read-write PID15 Interrupt Pending [15:15] read-write PID16 Interrupt Pending [16:16] read-write PID17 Interrupt Pending [17:17] read-write PID18 Interrupt Pending [18:18] read-write PID19 Interrupt Pending [19:19] read-write PID20 Interrupt Pending [20:20] read-write PID21 Interrupt Pending [21:21] read-write PID22 Interrupt Pending [22:22] read-write PID23 Interrupt Pending [23:23] read-write PID24 Interrupt Pending [24:24] read-write PID25 Interrupt Pending [25:25] read-write PID26 Interrupt Pending [26:26] read-write PID27 Interrupt Pending [27:27] read-write PID28 Interrupt Pending [28:28] read-write PID29 Interrupt Pending [29:29] read-write PID30 Interrupt Pending [30:30] read-write PID31 Interrupt Pending [31:31] read-write IPR1 Interrupt Pending Register 1 0x24 0x20 read-only PID32 Interrupt Pending [0:0] read-write PID33 Interrupt Pending [1:1] read-write PID34 Interrupt Pending [2:2] read-write PID35 Interrupt Pending [3:3] read-write PID36 Interrupt Pending [4:4] read-write PID37 Interrupt Pending [5:5] read-write PID38 Interrupt Pending [6:6] read-write PID39 Interrupt Pending [7:7] read-write PID40 Interrupt Pending [8:8] read-write PID41 Interrupt Pending [9:9] read-write PID42 Interrupt Pending [10:10] read-write PID43 Interrupt Pending [11:11] read-write PID44 Interrupt Pending [12:12] read-write PID45 Interrupt Pending [13:13] read-write PID46 Interrupt Pending [14:14] read-write PID47 Interrupt Pending [15:15] read-write PID48 Interrupt Pending [16:16] read-write PID49 Interrupt Pending [17:17] read-write PID50 Interrupt Pending [18:18] read-write PID51 Interrupt Pending [19:19] read-write PID52 Interrupt Pending [20:20] read-write PID53 Interrupt Pending [21:21] read-write PID54 Interrupt Pending [22:22] read-write PID55 Interrupt Pending [23:23] read-write PID56 Interrupt Pending [24:24] read-write PID57 Interrupt Pending [25:25] read-write PID58 Interrupt Pending [26:26] read-write PID59 Interrupt Pending [27:27] read-write PID60 Interrupt Pending [28:28] read-write PID61 Interrupt Pending [29:29] read-write PID62 Interrupt Pending [30:30] read-write PID63 Interrupt Pending [31:31] read-write IPR2 Interrupt Pending Register 2 0x28 0x20 read-only PID64 Interrupt Pending [0:0] read-write PID65 Interrupt Pending [1:1] read-write PID66 Interrupt Pending [2:2] read-write PID67 Interrupt Pending [3:3] read-write PID68 Interrupt Pending [4:4] read-write PID69 Interrupt Pending [5:5] read-write PID70 Interrupt Pending [6:6] read-write PID71 Interrupt Pending [7:7] read-write PID72 Interrupt Pending [8:8] read-write PID73 Interrupt Pending [9:9] read-write SYS Interrupt Pending [10:10] read-write PID75 Interrupt Pending [11:11] read-write PID76 Interrupt Pending [12:12] read-write PID77 Interrupt Pending [13:13] read-write PID78 Interrupt Pending [14:14] read-write PID79 Interrupt Pending [15:15] read-write PID80 Interrupt Pending [16:16] read-write PID81 Interrupt Pending [17:17] read-write PID82 Interrupt Pending [18:18] read-write PID83 Interrupt Pending [19:19] read-write PID84 Interrupt Pending [20:20] read-write PID85 Interrupt Pending [21:21] read-write PID86 Interrupt Pending [22:22] read-write PID87 Interrupt Pending [23:23] read-write PID88 Interrupt Pending [24:24] read-write PID89 Interrupt Pending [25:25] read-write PID90 Interrupt Pending [26:26] read-write PID91 Interrupt Pending [27:27] read-write PID92 Interrupt Pending [28:28] read-write PID93 Interrupt Pending [29:29] read-write PID94 Interrupt Pending [30:30] read-write PID95 Interrupt Pending [31:31] read-write IPR3 Interrupt Pending Register 3 0x2C 0x20 read-only PID96 Interrupt Pending [0:0] read-write PID97 Interrupt Pending [1:1] read-write PID98 Interrupt Pending [2:2] read-write PID99 Interrupt Pending [3:3] read-write PID100 Interrupt Pending [4:4] read-write PID101 Interrupt Pending [5:5] read-write PID102 Interrupt Pending [6:6] read-write PID103 Interrupt Pending [7:7] read-write PID104 Interrupt Pending [8:8] read-write PID105 Interrupt Pending [9:9] read-write PID106 Interrupt Pending [10:10] read-write PID107 Interrupt Pending [11:11] read-write PID108 Interrupt Pending [12:12] read-write PID109 Interrupt Pending [13:13] read-write PID110 Interrupt Pending [14:14] read-write PID111 Interrupt Pending [15:15] read-write PID112 Interrupt Pending [16:16] read-write PID113 Interrupt Pending [17:17] read-write PID114 Interrupt Pending [18:18] read-write PID115 Interrupt Pending [19:19] read-write PID116 Interrupt Pending [20:20] read-write PID117 Interrupt Pending [21:21] read-write PID118 Interrupt Pending [22:22] read-write PID119 Interrupt Pending [23:23] read-write PID120 Interrupt Pending [24:24] read-write PID121 Interrupt Pending [25:25] read-write PID122 Interrupt Pending [26:26] read-write PID123 Interrupt Pending [27:27] read-write PID124 Interrupt Pending [28:28] read-write PID125 Interrupt Pending [29:29] read-write PID126 Interrupt Pending [30:30] read-write PID127 Interrupt Pending [31:31] read-write ISCR Interrupt Set Command Register 0x4C 0x20 write-only INTSET Interrupt Set [0:0] read-write ISR Interrupt Status Register 0x18 0x20 read-only IRQID Current Interrupt Identifier [6:0] read-write 0 127 IVR Interrupt Vector Register 0x10 0x20 read-only IRQV Interrupt Vector Register [31:0] read-write 0 4294967295 SMR Source Mode Register 0x4 0x20 read-write PRIORITY Priority Level [2:0] read-write true MINIMUM Minimum priority 0 VERY_LOW Very low priority 1 LOW Low priority 2 MEDIUM_LOW Medium priority 3 MEDIUM_HIGH Medium-high priority 4 HIGH High priority 5 VERY_HIGH Very high priority 6 MAXIMUM Maximum priority 7 SRCTYPE Interrupt Source Type [6:5] read-write true INT_LEVEL_SENSITIVE High-level sensitive for internal source. Low-level sensitive for external source 0 EXT_NEGATIVE_EDGE Negative-edge triggered for external source 1 EXT_HIGH_LEVEL High-level sensitive for internal source. High-level sensitive for external source 2 EXT_POSITIVE_EDGE Positive-edge triggered for external source 3 SPU Spurious Interrupt Vector Register 0x3C 0x20 read-write SIVR Spurious Interrupt Vector Register [31:0] read-write 0 4294967295 SSR Source Select Register 0x0 0x20 read-write INTSEL Interrupt Line Selection [6:0] read-write 0 127 SVR Source Vector Register 0x8 0x20 read-write VECTOR Source Vector [31:0] read-write 0 4294967295 WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 4278595 WPSR Write Protection Status Register 0xE8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [23:8] read-write 0 65535 AXIMX AXI Matrix 0x00600000 0x0 0x4 registers AXIMX_REMAP AXI Matrix Remap Register 0x0 0x20 write-only REMAP0 Remap State 0 [0:0] read-write CHIPID Chip Identifier 0xFC069000 0x0 0x8 registers CIDR Chip ID Register 0x0 0x20 read-only VERSION Version of the Device [4:0] read-write 0 31 EPROC Embedded Processor [7:5] read-write true SAMx7 Cortex-M7 0 ARM946ES ARM946ES 1 ARM7TDMI ARM7TDMI 2 CM3 Cortex-M3 3 ARM920T ARM920T 4 ARM926EJS ARM926EJS 5 CA5 Cortex-A5 6 CM4 Cortex-M4 7 NVPSIZ Nonvolatile Program Memory Size [11:8] read-write true NONE None 0 _8K 8 Kbytes 1 _16K 16 Kbytes 2 _32K 32 Kbytes 3 _64K 64 Kbytes 5 _128K 128 Kbytes 7 _160K 160 Kbytes 8 _256K 256 Kbytes 9 _512K 512 Kbytes 10 _1024K 1024 Kbytes 12 _2048K 2048 Kbytes 14 NVPSIZ2 Second Nonvolatile Program Memory Size [15:12] read-write true NONE None 0 _8K 8 Kbytes 1 _16K 16 Kbytes 2 _32K 32 Kbytes 3 _64K 64 Kbytes 5 _128K 128 Kbytes 7 _256K 256 Kbytes 9 _512K 512 Kbytes 10 _1024K 1024 Kbytes 12 _2048K 2048 Kbytes 14 SRAMSIZ Internal SRAM Size [19:16] read-write true _48K 48 Kbytes 0 _192K 192 Kbytes 1 _384K 384 Kbytes 2 _6K 6 Kbytes 3 _24K 24 Kbytes 4 _4K 4 Kbytes 5 _80K 80 Kbytes 6 _160K 160 Kbytes 7 _8K 8 Kbytes 8 _16K 16 Kbytes 9 _32K 32 Kbytes 10 _64K 64 Kbytes 11 _128K 128 Kbytes 12 _256K 256 Kbytes 13 _96K 96 Kbytes 14 _512K 512 Kbytes 15 ARCH Architecture Identifier [27:20] read-write true SAMA5 SAMA5 165 NVPTYP Nonvolatile Program Memory Type [30:28] read-write true ROM ROM 0 ROMLESS ROMless or on-chip Flash 1 FLASH Embedded Flash Memory 2 ROM_FLASH ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size 3 SRAM SRAM emulating ROM 4 EXT Extension Flag [31:31] read-write EXID Chip ID Extension Register 0x4 0x20 read-only EXID Chip ID Extension [31:0] read-write 0 4294967295 CLASSD Audio Class D Amplifier (CLASSD) 0xFC048000 0x0 0x24 registers 0xE4 0x4 registers CR Control Register 0x0 0x20 write-only SWRST Software Reset [0:0] read-write IDR Interrupt Disable Register 0x18 0x20 write-only DATRDY Data Ready [0:0] read-write IER Interrupt Enable Register 0x14 0x20 write-only DATRDY Data Ready [0:0] read-write IMR Interrupt Mask Register 0x1C 0x20 read-write DATRDY Data Ready [0:0] read-write INTPMR Interpolator Mode Register 0x8 0x20 read-write ATTL Left Channel Attenuation [6:0] read-write 0 127 ATTR Right Channel Attenuation [14:8] read-write 0 127 DSPCLKFREQ DSP Clock Frequency [16:16] read-write true _12M288 DSP Clock (DSPCLK) is 12.288 MHz. 0 _11M2896 DSP Clock (DSPCLK) is 11.2896 MHz. 1 DEEMP Enable De-emphasis Filter [18:18] read-write true DISABLED De-emphasis filter is disabled. 0 ENABLED De-emphasis filter is enabled. 1 SWAP Swap Left and Right Channels [19:19] read-write true LEFT_ON_LSB Left channel is on CLASSD_THR[15:0], right channel is on CLASSD_THR[31:16]. 0 RIGHT_ON_LSB Right channel is on CLASSD_THR[15:0], left channel is on CLASSD_THR[31:16]. 1 FRAME CLASSD Incoming Data Sampling Frequency [22:20] read-write true FRAME_8K 8 kHz 0 FRAME_16K 16 kHz 1 FRAME_32K 32 kHz 2 FRAME_48K 48 kHz 3 FRAME_96K 96 kHz 4 FRAME_22K 22.05 kHz 5 FRAME_44K 44.1 kHz 6 FRAME_88K 88.2 kHz 7 EQCFG Equalization Selection [27:24] read-write true FLAT Flat Response 0 BBOOST12 Bass boost +12 dB 1 BBOOST6 Bass boost +6 dB 2 BCUT12 Bass cut -12 dB 3 BCUT6 Bass cut -6 dB 4 MBOOST3 Medium boost +3 dB 5 MBOOST8 Medium boost +8 dB 6 MCUT3 Medium cut -3 dB 7 MCUT8 Medium cut -8 dB 8 TBOOST12 Treble boost +12 dB 9 TBOOST6 Treble boost +6 dB 10 TCUT12 Treble cut -12 dB 11 TCUT6 Treble cut -6 dB 12 MONO Mono Signal [28:28] read-write true DISABLED The signal is sent stereo to the left and right channels. 0 ENABLED The same signal is sent on both left and right channels. The sent signal is defined by the MONOMODE field value. 1 MONOMODE Mono Mode Selection [30:29] read-write true MONOMIX (left + right) / 2 is sent on both channels 0 MONOSAT (left + right) is sent to both channels. If the sum is too high, the result is saturated. 1 MONOLEFT THR[15:0] is sent on both left and right channels 2 MONORIGHT THR[31:16] is sent on both left and right channels 3 INTSR Interpolator Status Register 0xC 0x20 read-only CFGERR Configuration Error [0:0] read-write ISR Interrupt Status Register 0x20 0x20 read-only DATRDY Data Ready [0:0] read-write MR Mode Register 0x4 0x20 read-write LEN Left Channel Enable [0:0] read-write LMUTE Left Channel Mute [1:1] read-write REN Right Channel Enable [4:4] read-write RMUTE Right Channel Mute [5:5] read-write PWMTYP PWM Modulation Type [8:8] read-write NON_OVERLAP Non-Overlapping Enable [16:16] read-write NOVRVAL Non-Overlapping Value [21:20] read-write true _5NS Non-overlapping time is 5 ns 0 _10NS Non-overlapping time is 10 ns 1 _15NS Non-overlapping time is 15 ns 2 _20NS Non-overlapping time is 20 ns 3 THR Transmit Holding Register 0x10 0x20 read-write LDATA Left Channel Data [15:0] read-write 0 65535 RDATA Right Channel Data [31:16] read-write 0 65535 WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 4410436 FLEXCOM0 Flexible Serial Communication 0xF8034000 0x0 0x4 registers 0x10 0x4 registers 0x20 0x4 registers 0x200 0x2C registers 0x240 0x8 registers 0x24C 0x14 registers 0x290 0x4 registers 0x2A0 0x18 registers 0x2E4 0x8 registers 0x400 0x20 registers 0x430 0x4 registers 0x440 0xC registers 0x4E4 0x8 registers 0x600 0x14 registers 0x620 0x1C registers 0x640 0x8 registers 0x64C 0xC registers 0x660 0x10 registers 0x6D0 0x4 registers 0x6E4 0x8 registers MR FLEXCOM Mode Register 0x0 0x20 read-write OPMODE FLEXCOM Operating Mode [1:0] read-write true NO_COM No communication 0 USART All UART related protocols are selected (RS232, RS485, IrDA, ISO7816, LIN,)SPI/TWI related registers are not accessible and have no impact on IOs. 1 SPI SPI operating mode is selected.USART/TWI related registers are not accessible and have no impact on IOs. 2 TWI All TWI related protocols are selected (TWI, SMBus).USART/SPI related registers are not accessible and have no impact on IOs. 3 RHR FLEXCOM Receive Holding Register 0x10 0x20 read-only RXDATA Receive Data [15:0] read-write 0 65535 SPI_CMPR SPI Comparison Register 0x448 0x20 read-write VAL1 First Comparison Value for Received Character [15:0] read-write 0 65535 VAL2 Second Comparison Value for Received Character [31:16] read-write 0 65535 SPI_CR SPI Control Register 0x400 0x20 write-only SPIEN SPI Enable [0:0] read-write SPIDIS SPI Disable [1:1] read-write SWRST SPI Software Reset [7:7] read-write REQCLR Request to Clear the Comparison Trigger [12:12] read-write TXFCLR Transmit FIFO Clear [16:16] read-write RXFCLR Receive FIFO Clear [17:17] read-write LASTXFER Last Transfer [24:24] read-write FIFOEN FIFO Enable [30:30] read-write FIFODIS FIFO Disable [31:31] read-write SPI_CSR SPI Chip Select Register 0x430 0x20 read-write CPOL Clock Polarity [0:0] read-write NCPHA Clock Phase [1:1] read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) [2:2] read-write CSAAT Chip Select Active After Transfer [3:3] read-write BITS Bits Per Transfer [7:4] read-write true 8_BIT 8 bits for transfer 0 9_BIT 9 bits for transfer 1 10_BIT 10 bits for transfer 2 11_BIT 11 bits for transfer 3 12_BIT 12 bits for transfer 4 13_BIT 13 bits for transfer 5 14_BIT 14 bits for transfer 6 15_BIT 15 bits for transfer 7 16_BIT 16 bits for transfer 8 SCBR Serial Clock Bit Rate [15:8] read-write 0 255 DLYBS Delay Before SPCK [23:16] read-write 0 255 DLYBCT Delay Between Consecutive Transfers [31:24] read-write 0 255 SPI_FLR SPI FIFO Level Register 0x444 0x20 read-only TXFL Transmit FIFO Level [5:0] read-write 0 63 RXFL Receive FIFO Level [21:16] read-write 0 63 SPI_FMR SPI FIFO Mode Register 0x440 0x20 read-write TXRDYM Transmit Data Register Empty Mode [1:0] read-write true ONE_DATA TDRE will be at level '1' when at least one data can be written in the Transmit FIFO. 0 TWO_DATA TDRE will be at level '1' when at least two data can be written in the Transmit FIFO.Cannot be used if FLEX_SPI_MR.PS =1. 1 RXRDYM Receive Data Register Full Mode [5:4] read-write true ONE_DATA RDRF will be at level '1' when at least one unread data is in the Receive FIFO. 0 TWO_DATA RDRF will be at level '1' when at least two unread data are in the Receive FIFO.Cannot be used if FLEX_SPI_MR.PS =1. 1 FOUR_DATA RDRF will be at level '1' when at least four unread data are in the Receive FIFO.Cannot be used when FLEX_SPI_CSRx.BITS is greater than 0, or if FLEX_SPI_MR.MSTR =1, or if FLEX_SPI_MR.PS =1. 2 TXFTHRES Transmit FIFO Threshold [21:16] read-write 0 63 RXFTHRES Receive FIFO Threshold [29:24] read-write 0 63 SPI_IDR SPI Interrupt Disable Register 0x418 0x20 write-only RDRF Receive Data Register Full Interrupt Disable [0:0] read-write TDRE SPI Transmit Data Register Empty Interrupt Disable [1:1] read-write MODF Mode Fault Error Interrupt Disable [2:2] read-write OVRES Overrun Error Interrupt Disable [3:3] read-write NSSR NSS Rising Interrupt Disable [8:8] read-write TXEMPTY Transmission Registers Empty Disable [9:9] read-write UNDES Underrun Error Interrupt Disable [10:10] read-write CMP Comparison Interrupt Disable [11:11] read-write TXFEF TXFEF Interrupt Disable [24:24] read-write TXFFF TXFFF Interrupt Disable [25:25] read-write TXFTHF TXFTHF Interrupt Disable [26:26] read-write RXFEF RXFEF Interrupt Disable [27:27] read-write RXFFF RXFFF Interrupt Disable [28:28] read-write RXFTHF RXFTHF Interrupt Disable [29:29] read-write TXFPTEF TXFPTEF Interrupt Disable [30:30] read-write RXFPTEF RXFPTEF Interrupt Disable [31:31] read-write SPI_IER SPI Interrupt Enable Register 0x414 0x20 write-only RDRF Receive Data Register Full Interrupt Enable [0:0] read-write TDRE SPI Transmit Data Register Empty Interrupt Enable [1:1] read-write MODF Mode Fault Error Interrupt Enable [2:2] read-write OVRES Overrun Error Interrupt Enable [3:3] read-write NSSR NSS Rising Interrupt Enable [8:8] read-write TXEMPTY Transmission Registers Empty Enable [9:9] read-write UNDES Underrun Error Interrupt Enable [10:10] read-write CMP Comparison Interrupt Enable [11:11] read-write TXFEF TXFEF Interrupt Enable [24:24] read-write TXFFF TXFFF Interrupt Enable [25:25] read-write TXFTHF TXFTHF Interrupt Enable [26:26] read-write RXFEF RXFEF Interrupt Enable [27:27] read-write RXFFF RXFFF Interrupt Enable [28:28] read-write RXFTHF RXFTHF Interrupt Enable [29:29] read-write TXFPTEF TXFPTEF Interrupt Enable [30:30] read-write RXFPTEF RXFPTEF Interrupt Enable [31:31] read-write SPI_IMR SPI Interrupt Mask Register 0x41C 0x20 read-only RDRF Receive Data Register Full Interrupt Mask [0:0] read-write TDRE SPI Transmit Data Register Empty Interrupt Mask [1:1] read-write MODF Mode Fault Error Interrupt Mask [2:2] read-write OVRES Overrun Error Interrupt Mask [3:3] read-write NSSR NSS Rising Interrupt Mask [8:8] read-write TXEMPTY Transmission Registers Empty Mask [9:9] read-write UNDES Underrun Error Interrupt Mask [10:10] read-write CMP Comparison Interrupt Mask [11:11] read-write TXFEF TXFEF Interrupt Mask [24:24] read-write TXFFF TXFFF Interrupt Mask [25:25] read-write TXFTHF TXFTHF Interrupt Mask [26:26] read-write RXFEF RXFEF Interrupt Mask [27:27] read-write RXFFF RXFFF Interrupt Mask [28:28] read-write RXFTHF RXFTHF Interrupt Mask [29:29] read-write TXFPTEF TXFPTEF Interrupt Mask [30:30] read-write RXFPTEF RXFPTEF Interrupt Mask [31:31] read-write SPI_MR SPI Mode Register 0x404 0x20 read-write MSTR Master/Slave Mode [0:0] read-write PS Peripheral Select [1:1] read-write PCSDEC Chip Select Decode [2:2] read-write BRSRCCLK Bit Rate Source Clock [3:3] read-write true PERIPH_CLK The peripheral clock is the source clock for the bit rate generation. 0 GCLK GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock. 1 MODFDIS Mode Fault Detection [4:4] read-write WDRBT Wait Data Read Before Transfer [5:5] read-write LLB Local Loopback Enable [7:7] read-write LBHPC Last Bit Half Period Compatibility [8:8] read-write CMPMODE Comparison Mode [12:12] read-write true FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception of all incoming characters until REQCLR is set. 1 PCS Peripheral Chip Select [17:16] read-write 0 3 DLYBCS Delay Between Chip Selects [31:24] read-write 0 255 SPI_RDR SPI Receive Data Register 0x408 0x20 read-only RD Receive Data [15:0] read-write 0 65535 RD16_0 Receive Data [15:0] read-write 0 65535 RD8_0 Receive Data [7:0] read-write 0 255 RD8_1 Receive Data [15:8] read-write 0 255 PCS Peripheral Chip Select [19:16] read-write 0 15 RD16_1 Receive Data [31:16] read-write 0 65535 RD8_2 Receive Data [23:16] read-write 0 255 RD8_3 Receive Data [31:24] read-write 0 255 SPI_SR SPI Status Register 0x410 0x20 read-only RDRF Receive Data Register Full (cleared by reading FLEX_SPI_RDR) [0:0] read-write TDRE Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR) [1:1] read-write MODF Mode Fault Error (cleared on read) [2:2] read-write OVRES Overrun Error Status (cleared on read) [3:3] read-write NSSR NSS Rising (cleared on read) [8:8] read-write TXEMPTY Transmission Registers Empty (cleared by writing FLEX_SPI_TDR) [9:9] read-write UNDES Underrun Error Status (Slave mode only) (cleared on read) [10:10] read-write CMP Comparison Status (cleared on read) [11:11] read-write SPIENS SPI Enable Status [16:16] read-write TXFEF Transmit FIFO Empty Flag (cleared on read) [24:24] read-write TXFFF Transmit FIFO Full Flag (cleared on read) [25:25] read-write TXFTHF Transmit FIFO Threshold Flag (cleared on read) [26:26] read-write RXFEF Receive FIFO Empty Flag [27:27] read-write RXFFF Receive FIFO Full Flag [28:28] read-write RXFTHF Receive FIFO Threshold Flag [29:29] read-write TXFPTEF Transmit FIFO Pointer Error Flag [30:30] read-write RXFPTEF Receive FIFO Pointer Error Flag [31:31] read-write SPI_TDR SPI Transmit Data Register 0x40C 0x20 write-only TD Transmit Data [15:0] read-write 0 65535 TD0 Transmit Data [15:0] read-write 0 65535 PCS Peripheral Chip Select [19:16] read-write 0 15 TD1 Transmit Data [31:16] read-write 0 65535 LASTXFER Last Transfer [24:24] read-write SPI_WPMR SPI Write Protection Mode Register 0x4E4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0 5460041 SPI_WPSR SPI Write Protection Status Register 0x4E8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [15:8] read-write 0 255 THR FLEXCOM Transmit Holding Register 0x20 0x20 read-write TXDATA Transmit Data [15:0] read-write 0 65535 TWI_ACR TWI Alternative Command Register 0x640 0x20 read-write DATAL Data Length [7:0] read-write 0 255 DIR Transfer Direction [8:8] read-write PEC PEC Request (SMBus Mode only) [9:9] read-write NDATAL Next Data Length [23:16] read-write 0 255 NDIR Next Transfer Direction [24:24] read-write NPEC Next PEC Request (SMBus Mode only) [25:25] read-write TWI_CR TWI Control Register 0x600 0x20 write-only START Send a START Condition [0:0] read-write STOP Send a STOP Condition [1:1] read-write MSEN TWI Master Mode Enabled [2:2] read-write MSDIS TWI Master Mode Disabled [3:3] read-write SVEN TWI Slave Mode Enabled [4:4] read-write SVDIS TWI Slave Mode Disabled [5:5] read-write QUICK SMBus Quick Command [6:6] read-write SWRST Software Reset [7:7] read-write HSEN TWI High-Speed Mode Enabled [8:8] read-write HSDIS TWI High-Speed Mode Disabled [9:9] read-write SMBEN SMBus Mode Enabled [10:10] read-write SMBDIS SMBus Mode Disabled [11:11] read-write PECEN Packet Error Checking Enable [12:12] read-write PECDIS Packet Error Checking Disable [13:13] read-write PECRQ PEC Request [14:14] read-write CLEAR Bus CLEAR Command [15:15] read-write ACMEN Alternative Command Mode Enable [16:16] read-write ACMDIS Alternative Command Mode Disable [17:17] read-write THRCLR Transmit Holding Register Clear [24:24] read-write TXFCLR Transmit FIFO Clear [24:24] read-write RXFCLR Receive FIFO Clear [25:25] read-write LOCKCLR Lock Clear [26:26] read-write TXFLCLR Transmit FIFO Lock CLEAR [26:26] read-write FIFOEN FIFO Enable [28:28] read-write FIFODIS FIFO Disable [29:29] read-write TWI_CWGR TWI Clock Waveform Generator Register 0x610 0x20 read-write CLDIV Clock Low Divider [7:0] read-write 0 255 CHDIV Clock High Divider [15:8] read-write 0 255 CKDIV Clock Divider [18:16] read-write 0 7 BRSRCCLK Bit Rate Source Clock [20:20] read-write true PERIPH_CLK The peripheral clock is the source clock for the bit rate generation. 0 GCLK GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock. 1 HOLD TWD Hold Time Versus TWCK Falling [28:24] read-write 0 31 TWI_DR TWI Debug Register 0x6D0 0x20 read-only SWEN SleepWalking Enable [0:0] read-write CLKRQ Clock Request [1:1] read-write SWMATCH SleepWalking Match [2:2] read-write TRP Transfer Pending [3:3] read-write TWI_FIDR TWI FIFO Interrupt Disable Register 0x668 0x20 write-only TXFEF TXFEF Interrupt Disable [0:0] read-write TXFFF TXFFF Interrupt Disable [1:1] read-write TXFTHF TXFTHF Interrupt Disable [2:2] read-write RXFEF RXFEF Interrupt Disable [3:3] read-write RXFFF RXFFF Interrupt Disable [4:4] read-write RXFTHF RXFTHF Interrupt Disable [5:5] read-write TXFPTEF TXFPTEF Interrupt Disable [6:6] read-write RXFPTEF RXFPTEF Interrupt Disable [7:7] read-write TWI_FIER TWI FIFO Interrupt Enable Register 0x664 0x20 write-only TXFEF TXFEF Interrupt Enable [0:0] read-write TXFFF TXFFF Interrupt Enable [1:1] read-write TXFTHF TXFTHF Interrupt Enable [2:2] read-write RXFEF RXFEF Interrupt Enable [3:3] read-write RXFFF RXFFF Interrupt Enable [4:4] read-write RXFTHF RXFTHF Interrupt Enable [5:5] read-write TXFPTEF TXFPTEF Interrupt Enable [6:6] read-write RXFPTEF RXFPTEF Interrupt Enable [7:7] read-write TWI_FILTR TWI Filter Register 0x644 0x20 read-write FILT RX Digital Filter [0:0] read-write PADFEN PAD Filter Enable [1:1] read-write PADFCFG PAD Filter Config [2:2] read-write THRES Digital Filter Threshold [10:8] read-write 0 7 TWI_FIMR TWI FIFO Interrupt Mask Register 0x66C 0x20 read-only TXFEF TXFEF Interrupt Mask [0:0] read-write TXFFF TXFFF Interrupt Mask [1:1] read-write TXFTHF TXFTHF Interrupt Mask [2:2] read-write RXFEF RXFEF Interrupt Mask [3:3] read-write RXFFF RXFFF Interrupt Mask [4:4] read-write RXFTHF RXFTHF Interrupt Mask [5:5] read-write TXFPTEF TXFPTEF Interrupt Mask [6:6] read-write RXFPTEF RXFPTEF Interrupt Mask [7:7] read-write TWI_FLR TWI FIFO Level Register 0x654 0x20 read-only TXFL Transmit FIFO Level [5:0] read-write 0 63 RXFL Receive FIFO Level [21:16] read-write 0 63 TWI_FMR TWI FIFO Mode Register 0x650 0x20 read-write TXRDYM Transmitter Ready Mode [1:0] read-write true ONE_DATA TXRDY will be at level '1' when at least one data can be written in the Transmit FIFO 0 TWO_DATA TXRDY will be at level '1' when at least two data can be written in the Transmit FIFO 1 FOUR_DATA TXRDY will be at level '1' when at least four data can be written in the Transmit FIFO 2 RXRDYM Receiver Ready Mode [5:4] read-write true ONE_DATA RXRDY will be at level '1' when at least one unread data is in the Receive FIFO 0 TWO_DATA RXRDY will be at level '1' when at least two unread data are in the Receive FIFO 1 FOUR_DATA RXRDY will be at level '1' when at least four unread data are in the Receive FIFO 2 TXFTHRES Transmit FIFO Threshold [21:16] read-write 0 63 RXFTHRES Receive FIFO Threshold [29:24] read-write 0 63 TWI_FSR TWI FIFO Status Register 0x660 0x20 read-only TXFEF Transmit FIFO Empty Flag (cleared on read) [0:0] read-write TXFFF Transmit FIFO Full Flag (cleared on read) [1:1] read-write TXFTHF Transmit FIFO Threshold Flag (cleared on read) [2:2] read-write RXFEF Receive FIFO Empty Flag [3:3] read-write RXFFF Receive FIFO Full Flag [4:4] read-write RXFTHF Receive FIFO Threshold Flag [5:5] read-write TXFPTEF Transmit FIFO Pointer Error Flag [6:6] read-write RXFPTEF Receive FIFO Pointer Error Flag [7:7] read-write TWI_IADR TWI Internal Address Register 0x60C 0x20 read-write IADR Internal Address [23:0] read-write 0 16777215 TWI_IDR TWI Interrupt Disable Register 0x628 0x20 write-only TXCOMP Transmission Completed Interrupt Disable [0:0] read-write RXRDY Receive Holding Register Ready Interrupt Disable [1:1] read-write TXRDY Transmit Holding Register Ready Interrupt Disable [2:2] read-write SVACC Slave Access Interrupt Disable [4:4] read-write GACC General Call Access Interrupt Disable [5:5] read-write OVRE Overrun Error Interrupt Disable [6:6] read-write UNRE Underrun Error Interrupt Disable [7:7] read-write NACK Not Acknowledge Interrupt Disable [8:8] read-write ARBLST Arbitration Lost Interrupt Disable [9:9] read-write SCL_WS Clock Wait State Interrupt Disable [10:10] read-write EOSACC End Of Slave Access Interrupt Disable [11:11] read-write ENDRX End of Receive Buffer Interrupt Disable [12:12] read-write ENDTX End of Transmit Buffer Interrupt Disable [13:13] read-write RXBUFF Receive Buffer Full Interrupt Disable [14:14] read-write TXBUFE Transmit Buffer Empty Interrupt Disable [15:15] read-write MCACK Master Code Acknowledge Interrupt Disable [16:16] read-write TOUT Timeout Error Interrupt Disable [18:18] read-write PECERR PEC Error Interrupt Disable [19:19] read-write SMBDAM SMBus Default Address Match Interrupt Disable [20:20] read-write SMBHHM SMBus Host Header Address Match Interrupt Disable [21:21] read-write TWI_IER TWI Interrupt Enable Register 0x624 0x20 write-only TXCOMP Transmission Completed Interrupt Enable [0:0] read-write RXRDY Receive Holding Register Ready Interrupt Enable [1:1] read-write TXRDY Transmit Holding Register Ready Interrupt Enable [2:2] read-write SVACC Slave Access Interrupt Enable [4:4] read-write GACC General Call Access Interrupt Enable [5:5] read-write OVRE Overrun Error Interrupt Enable [6:6] read-write UNRE Underrun Error Interrupt Enable [7:7] read-write NACK Not Acknowledge Interrupt Enable [8:8] read-write ARBLST Arbitration Lost Interrupt Enable [9:9] read-write SCL_WS Clock Wait State Interrupt Enable [10:10] read-write EOSACC End Of Slave Access Interrupt Enable [11:11] read-write ENDRX End of Receive Buffer Interrupt Enable [12:12] read-write ENDTX End of Transmit Buffer Interrupt Enable [13:13] read-write RXBUFF Receive Buffer Full Interrupt Enable [14:14] read-write TXBUFE Transmit Buffer Empty Interrupt Enable [15:15] read-write MCACK Master Code Acknowledge Interrupt Enable [16:16] read-write TOUT Timeout Error Interrupt Enable [18:18] read-write PECERR PEC Error Interrupt Enable [19:19] read-write SMBDAM SMBus Default Address Match Interrupt Enable [20:20] read-write SMBHHM SMBus Host Header Address Match Interrupt Enable [21:21] read-write TWI_IMR TWI Interrupt Mask Register 0x62C 0x20 read-only TXCOMP Transmission Completed Interrupt Mask [0:0] read-write RXRDY Receive Holding Register Ready Interrupt Mask [1:1] read-write TXRDY Transmit Holding Register Ready Interrupt Mask [2:2] read-write SVACC Slave Access Interrupt Mask [4:4] read-write GACC General Call Access Interrupt Mask [5:5] read-write OVRE Overrun Error Interrupt Mask [6:6] read-write UNRE Underrun Error Interrupt Mask [7:7] read-write NACK Not Acknowledge Interrupt Mask [8:8] read-write ARBLST Arbitration Lost Interrupt Mask [9:9] read-write SCL_WS Clock Wait State Interrupt Mask [10:10] read-write EOSACC End Of Slave Access Interrupt Mask [11:11] read-write ENDRX End of Receive Buffer Interrupt Mask [12:12] read-write ENDTX End of Transmit Buffer Interrupt Mask [13:13] read-write RXBUFF Receive Buffer Full Interrupt Mask [14:14] read-write TXBUFE Transmit Buffer Empty Interrupt Mask [15:15] read-write MCACK Master Code Acknowledge Interrupt Mask [16:16] read-write TOUT Timeout Error Interrupt Mask [18:18] read-write PECERR PEC Error Interrupt Mask [19:19] read-write SMBDAM SMBus Default Address Match Interrupt Mask [20:20] read-write SMBHHM SMBus Host Header Address Match Interrupt Mask [21:21] read-write TWI_MMR TWI Master Mode Register 0x604 0x20 read-write IADRSZ Internal Device Address Size [9:8] read-write true NONE No internal device address 0 1_BYTE One-byte internal device address 1 2_BYTE Two-byte internal device address 2 3_BYTE Three-byte internal device address 3 MREAD Master Read Direction [12:12] read-write DADR Device Address [22:16] read-write 0 127 TWI_RHR TWI Receive Holding Register 0x630 0x20 read-only RXDATA Master or Slave Receive Holding Data [7:0] read-write 0 255 RXDATA0 Master or Slave Receive Holding Data 0 [7:0] read-write 0 255 RXDATA1 Master or Slave Receive Holding Data 1 [15:8] read-write 0 255 RXDATA2 Master or Slave Receive Holding Data 2 [23:16] read-write 0 255 RXDATA3 Master or Slave Receive Holding Data 3 [31:24] read-write 0 255 TWI_SMBTR TWI SMBus Timing Register 0x638 0x20 read-write PRESC SMBus Clock Prescaler [3:0] read-write 0 15 TLOWS Slave Clock Stretch Maximum Cycles [15:8] read-write 0 255 TLOWM Master Clock Stretch Maximum Cycles [23:16] read-write 0 255 THMAX Clock High Maximum Cycles [31:24] read-write 0 255 TWI_SMR TWI Slave Mode Register 0x608 0x20 read-write NACKEN Slave Receiver Data Phase NACK Enable [0:0] read-write SMDA SMBus Default Address [2:2] read-write SMHH SMBus Host Header [3:3] read-write SCLWSDIS Clock Wait State Disable [6:6] read-write MASK Slave Address Mask [14:8] read-write 0 127 SADR Slave Address [22:16] read-write 0 127 SADR1EN Slave Address 1 Enable [28:28] read-write SADR2EN Slave Address 2 Enable [29:29] read-write SADR3EN Slave Address 3 Enable [30:30] read-write DATAMEN Data Matching Enable [31:31] read-write TWI_SR TWI Status Register 0x620 0x20 read-only TXCOMP Transmission Completed (cleared by writing FLEX_TWI_THR) [0:0] read-write RXRDY Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR) [1:1] read-write TXRDY Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR) [2:2] read-write SVREAD Slave Read [3:3] read-write SVACC Slave Access [4:4] read-write GACC General Call Access (cleared on read) [5:5] read-write OVRE Overrun Error (cleared on read) [6:6] read-write UNRE Underrun Error (cleared on read) [7:7] read-write NACK Not Acknowledged (cleared on read) [8:8] read-write ARBLST Arbitration Lost (cleared on read) [9:9] read-write SCLWS Clock Wait State [10:10] read-write EOSACC End Of Slave Access (cleared on read) [11:11] read-write MCACK Master Code Acknowledge (cleared on read) [16:16] read-write TOUT Timeout Error (cleared on read) [18:18] read-write PECERR PEC Error (cleared on read) [19:19] read-write SMBDAM SMBus Default Address Match (cleared on read) [20:20] read-write SMBHHM SMBus Host Header Address Match (cleared on read) [21:21] read-write LOCK TWI Lock Due to Frame Errors [23:23] read-write TXFLOCK Transmit FIFO Lock [23:23] read-write SCL SCL Line Value [24:24] read-write SDA SDA Line Value [25:25] read-write TWI_SWMR TWI SleepWalking Matching Register 0x64C 0x20 read-write SADR1 Slave Address 1 [6:0] read-write 0 127 SADR2 Slave Address 2 [14:8] read-write 0 127 SADR3 Slave Address 3 [22:16] read-write 0 127 DATAM Data Match [31:24] read-write 0 255 TWI_THR TWI Transmit Holding Register 0x634 0x20 write-only TXDATA Master or Slave Transmit Holding Data [7:0] read-write 0 255 TXDATA0 Master or Slave Transmit Holding Data 0 [7:0] read-write 0 255 TXDATA1 Master or Slave Transmit Holding Data 1 [15:8] read-write 0 255 TXDATA2 Master or Slave Transmit Holding Data 2 [23:16] read-write 0 255 TXDATA3 Master or Slave Transmit Holding Data 3 [31:24] read-write 0 255 TWI_WPMR TWI Write Protection Mode Register 0x6E4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0 5527369 TWI_WPSR TWI Write Protection Status Register 0x6E8 0x20 read-only WPVS Write Protect Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [31:8] read-write 0 16777215 US_BRGR USART Baud Rate Generator Register 0x220 0x20 read-write CD Clock Divider [15:0] read-write 0 65535 FP Fractional Part [18:16] read-write 0 7 US_CMPR USART Comparison Register 0x290 0x20 read-write VAL1 First Comparison Value for Received Character [8:0] read-write 0 511 CMPMODE Comparison Mode [12:12] read-write true FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity [14:14] read-write VAL2 Second Comparison Value for Received Character [24:16] read-write 0 511 US_CR USART Control Register 0x200 0x20 write-only RSTRX Reset Receiver [2:2] read-write RSTTX Reset Transmitter [3:3] read-write RXEN Receiver Enable [4:4] read-write RXDIS Receiver Disable [5:5] read-write TXEN Transmitter Enable [6:6] read-write TXDIS Transmitter Disable [7:7] read-write RSTSTA Reset Status Bits [8:8] read-write STTBRK Start Break [9:9] read-write STPBRK Stop Break [10:10] read-write STTTO Clear TIMEOUT Flag and Start Timeout After Next Character Received [11:11] read-write SENDA Send Address [12:12] read-write RSTIT Reset Iterations [13:13] read-write RSTNACK Reset Non Acknowledge [14:14] read-write RETTO Start Timeout Immediately [15:15] read-write FCS Force SPI Chip Select [18:18] read-write RTSEN Request to Send Enable [18:18] read-write RCS Release SPI Chip Select [19:19] read-write RTSDIS Request to Send Disable [19:19] read-write LINABT Abort LIN Transmission [20:20] read-write LINWKUP Send LIN Wakeup Signal [21:21] read-write TXFCLR Transmit FIFO Clear [24:24] read-write RXFCLR Receive FIFO Clear [25:25] read-write TXFLCLR Transmit FIFO Lock CLEAR [26:26] read-write REQCLR Request to Clear the Comparison Trigger [28:28] read-write FIFOEN FIFO Enable [30:30] read-write FIFODIS FIFO Disable [31:31] read-write US_CSR USART Channel Status Register 0x214 0x20 read-only RXRDY Receiver Ready (cleared by reading FLEX_US_RHR) [0:0] read-write TXRDY Transmitter Ready (cleared by writing FLEX_US_THR) [1:1] read-write RXBRK Break Received/End of Break [2:2] read-write OVRE Overrun Error [5:5] read-write FRAME Framing Error [6:6] read-write PARE Parity Error [7:7] read-write TIMEOUT Receiver Timeout [8:8] read-write TXEMPTY Transmitter Empty (cleared by writing FLEX_US_THR) [9:9] read-write ITER Max Number of Repetitions Reached [10:10] read-write UNRE Underrun Error [10:10] read-write LINBK LIN Break Sent or LIN Break Received [13:13] read-write NACK Non Acknowledge Interrupt [13:13] read-write LINID LIN Identifier Sent or LIN Identifier Received [14:14] read-write LINTC LIN Transfer Completed [15:15] read-write CTSIC Clear to Send Input Change Flag [19:19] read-write NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) [19:19] read-write CMP Comparison Match [22:22] read-write CTS Image of CTS Input [23:23] read-write LINBLS LIN Bus Line Status [23:23] read-write NSS NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) [23:23] read-write MANE Manchester Error [24:24] read-write LINBE LIN Bit Error [25:25] read-write LINISFE LIN Inconsistent Synch Field Error [26:26] read-write LINIPE LIN Identifier Parity Error [27:27] read-write LINCE LIN Checksum Error [28:28] read-write LINSNRE LIN Slave Not Responding Error [29:29] read-write LINSTE LIN Synch Tolerance Error [30:30] read-write LINHTE LIN Header Timeout Error [31:31] read-write US_FESR USART FIFO Event Status Register 0x2B4 0x20 read-only TXFEF Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit) [0:0] read-write TXFFF Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit) [1:1] read-write TXFTHF Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit) [2:2] read-write RXFEF Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit) [3:3] read-write RXFFF Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit) [4:4] read-write RXFTHF Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit) [5:5] read-write TXFPTEF Transmit FIFO Pointer Error Flag [6:6] read-write RXFPTEF Receive FIFO Pointer Error Flag [7:7] read-write TXFLOCK Transmit FIFO Lock [8:8] read-write RXFTHF2 Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit) [9:9] read-write US_FIDI USART FI DI Ratio Register 0x240 0x20 read-write FI_DI_RATIO FI Over DI Ratio Value [15:0] read-write 0 65535 US_FIDR USART FIFO Interrupt Disable Register 0x2AC 0x20 write-only TXFEF TXFEF Interrupt Disable [0:0] read-write TXFFF TXFFF Interrupt Disable [1:1] read-write TXFTHF TXFTHF Interrupt Disable [2:2] read-write RXFEF RXFEF Interrupt Disable [3:3] read-write RXFFF RXFFF Interrupt Disable [4:4] read-write RXFTHF RXFTHF Interrupt Disable [5:5] read-write TXFPTEF TXFPTEF Interrupt Disable [6:6] read-write RXFPTEF RXFPTEF Interrupt Disable [7:7] read-write RXFTHF2 RXFTHF2 Interrupt Disable [9:9] read-write US_FIER USART FIFO Interrupt Enable Register 0x2A8 0x20 write-only TXFEF TXFEF Interrupt Enable [0:0] read-write TXFFF TXFFF Interrupt Enable [1:1] read-write TXFTHF TXFTHF Interrupt Enable [2:2] read-write RXFEF RXFEF Interrupt Enable [3:3] read-write RXFFF RXFFF Interrupt Enable [4:4] read-write RXFTHF RXFTHF Interrupt Enable [5:5] read-write TXFPTEF TXFPTEF Interrupt Enable [6:6] read-write RXFPTEF RXFPTEF Interrupt Enable [7:7] read-write RXFTHF2 RXFTHF2 Interrupt Enable [9:9] read-write US_FIMR USART FIFO Interrupt Mask Register 0x2B0 0x20 read-only TXFEF TXFEF Interrupt Mask [0:0] read-write TXFFF TXFFF Interrupt Mask [1:1] read-write TXFTHF TXFTHF Interrupt Mask [2:2] read-write RXFEF RXFEF Interrupt Mask [3:3] read-write RXFFF RXFFF Interrupt Mask [4:4] read-write RXFTHF RXFTHF Interrupt Mask [5:5] read-write TXFPTEF TXFPTEF Interrupt Mask [6:6] read-write RXFPTEF RXFPTEF Interrupt Mask [7:7] read-write RXFTHF2 RXFTHF2 Interrupt Mask [9:9] read-write US_FLR USART FIFO Level Register 0x2A4 0x20 read-only TXFL Transmit FIFO Level [5:0] read-write 0 63 RXFL Receive FIFO Level [21:16] read-write 0 63 US_FMR USART FIFO Mode Register 0x2A0 0x20 read-write TXRDYM Transmitter Ready Mode [1:0] read-write true ONE_DATA TXRDY will be at level '1' when at least one data can be written in the Transmit FIFO 0 TWO_DATA TXRDY will be at level '1' when at least two data can be written in the Transmit FIFO 1 FOUR_DATA TXRDY will be at level '1' when at least four data can be written in the Transmit FIFO 2 RXRDYM Receiver Ready Mode [5:4] read-write true ONE_DATA RXRDY will be at level '1' when at least one unread data is in the Receive FIFO 0 TWO_DATA RXRDY will be at level '1' when at least two unread data are in the Receive FIFO 1 FOUR_DATA RXRDY will be at level '1' when at least four unread data are in the Receive FIFO 2 FRTSC FIFO RTS Pin Control enable (Hardware Handshaking mode only) [7:7] read-write TXFTHRES Transmit FIFO Threshold [13:8] read-write 0 63 RXFTHRES Receive FIFO Threshold [21:16] read-write 0 63 RXFTHRES2 Receive FIFO Threshold 2 [29:24] read-write 0 63 US_IDR USART Interrupt Disable Register 0x20C 0x20 write-only RXRDY RXRDY Interrupt Disable [0:0] read-write TXRDY TXRDY Interrupt Disable [1:1] read-write RXBRK Receiver Break Interrupt Disable [2:2] read-write OVRE Overrun Error Interrupt Disable [5:5] read-write FRAME Framing Error Interrupt Disable [6:6] read-write PARE Parity Error Interrupt Disable [7:7] read-write TIMEOUT Timeout Interrupt Disable [8:8] read-write TXEMPTY TXEMPTY Interrupt Disable [9:9] read-write ITER Max Number of Repetitions Reached Interrupt Disable [10:10] read-write UNRE SPI Underrun Error Interrupt Disable [10:10] read-write LINBK LIN Break Sent or LIN Break Received Interrupt Disable [13:13] read-write NACK Non Acknowledge Interrupt Disable [13:13] read-write LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable [14:14] read-write LINTC LIN Transfer Completed Interrupt Disable [15:15] read-write CTSIC Clear to Send Input Change Interrupt Disable [19:19] read-write NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event [19:19] read-write CMP Comparison Interrupt Disable [22:22] read-write MANE Manchester Error Interrupt Disable [24:24] read-write LINBE LIN Bus Error Interrupt Disable [25:25] read-write LINISFE LIN Inconsistent Synch Field Error Interrupt Disable [26:26] read-write LINIPE LIN Identifier Parity Interrupt Disable [27:27] read-write LINCE LIN Checksum Error Interrupt Disable [28:28] read-write LINSNRE LIN Slave Not Responding Error Interrupt Disable [29:29] read-write LINSTE LIN Synch Tolerance Error Interrupt Disable [30:30] read-write LINHTE LIN Header Timeout Error Interrupt Disable [31:31] read-write US_IER USART Interrupt Enable Register 0x208 0x20 write-only RXRDY RXRDY Interrupt Enable [0:0] read-write TXRDY TXRDY Interrupt Enable [1:1] read-write RXBRK Receiver Break Interrupt Enable [2:2] read-write OVRE Overrun Error Interrupt Enable [5:5] read-write FRAME Framing Error Interrupt Enable [6:6] read-write PARE Parity Error Interrupt Enable [7:7] read-write TIMEOUT Timeout Interrupt Enable [8:8] read-write TXEMPTY TXEMPTY Interrupt Enable [9:9] read-write ITER Max number of Repetitions Reached Interrupt Enable [10:10] read-write UNRE SPI Underrun Error Interrupt Enable [10:10] read-write LINBK LIN Break Sent or LIN Break Received Interrupt Enable [13:13] read-write NACK Non Acknowledge Interrupt Enable [13:13] read-write LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable [14:14] read-write LINTC LIN Transfer Completed Interrupt Enable [15:15] read-write CTSIC Clear to Send Input Change Interrupt Enable [19:19] read-write NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event [19:19] read-write CMP Comparison Interrupt Enable [22:22] read-write MANE Manchester Error Interrupt Enable [24:24] read-write LINBE LIN Bus Error Interrupt Enable [25:25] read-write LINISFE LIN Inconsistent Synch Field Error Interrupt Enable [26:26] read-write LINIPE LIN Identifier Parity Interrupt Enable [27:27] read-write LINCE LIN Checksum Error Interrupt Enable [28:28] read-write LINSNRE LIN Slave Not Responding Error Interrupt Enable [29:29] read-write LINSTE LIN Synch Tolerance Error Interrupt Enable [30:30] read-write LINHTE LIN Header Timeout Error Interrupt Enable [31:31] read-write US_IF USART IrDA Filter Register 0x24C 0x20 read-write IRDA_FILTER IrDA Filter [7:0] read-write 0 255 US_IMR USART Interrupt Mask Register 0x210 0x20 read-only RXRDY RXRDY Interrupt Mask [0:0] read-write TXRDY TXRDY Interrupt Mask [1:1] read-write RXBRK Receiver Break Interrupt Mask [2:2] read-write OVRE Overrun Error Interrupt Mask [5:5] read-write FRAME Framing Error Interrupt Mask [6:6] read-write PARE Parity Error Interrupt Mask [7:7] read-write TIMEOUT Timeout Interrupt Mask [8:8] read-write TXEMPTY TXEMPTY Interrupt Mask [9:9] read-write ITER Max Number of Repetitions Reached Interrupt Mask [10:10] read-write UNRE SPI Underrun Error Interrupt Mask [10:10] read-write LINBK LIN Break Sent or LIN Break Received Interrupt Mask [13:13] read-write NACK Non Acknowledge Interrupt Mask [13:13] read-write LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask [14:14] read-write LINTC LIN Transfer Completed Interrupt Mask [15:15] read-write CTSIC Clear to Send Input Change Interrupt Mask [19:19] read-write NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event [19:19] read-write CMP Comparison Interrupt Mask [22:22] read-write MANE Manchester Error Interrupt Mask [24:24] read-write LINBE LIN Bus Error Interrupt Mask [25:25] read-write LINISFE LIN Inconsistent Synch Field Error Interrupt Mask [26:26] read-write LINIPE LIN Identifier Parity Interrupt Mask [27:27] read-write LINCE LIN Checksum Error Interrupt Mask [28:28] read-write LINSNRE LIN Slave Not Responding Error Interrupt Mask [29:29] read-write LINSTE LIN Synch Tolerance Error Interrupt Mask [30:30] read-write LINHTE LIN Header Timeout Error Interrupt Mask [31:31] read-write US_LINBRR USART LIN Baud Rate Register 0x25C 0x20 read-only LINCD Clock Divider after Synchronization [15:0] read-write 0 65535 LINFP Fractional Part after Synchronization [18:16] read-write 0 7 US_LINIR USART LIN Identifier Register 0x258 0x20 read-write IDCHR Identifier Character [7:0] read-write 0 255 US_LINMR USART LIN Mode Register 0x254 0x20 read-write NACT LIN Node Action [1:0] read-write true PUBLISH The USART transmits the response. 0 SUBSCRIBE The USART receives the response. 1 IGNORE The USART does not transmit and does not receive the response. 2 PARDIS Parity Disable [2:2] read-write CHKDIS Checksum Disable [3:3] read-write CHKTYP Checksum Type [4:4] read-write DLM Data Length Mode [5:5] read-write FSDIS Frame Slot Mode Disable [6:6] read-write WKUPTYP Wakeup Signal Type [7:7] read-write DLC Data Length Control [15:8] read-write 0 255 PDCM DMAC Mode [16:16] read-write SYNCDIS Synchronization Disable [17:17] read-write US_MAN USART Manchester Configuration Register 0x250 0x20 read-write TX_PL Transmitter Preamble Length [3:0] read-write 0 15 TX_PP Transmitter Preamble Pattern [9:8] read-write true ALL_ONE The preamble is composed of '1's 0 ALL_ZERO The preamble is composed of '0's 1 ZERO_ONE The preamble is composed of '01's 2 ONE_ZERO The preamble is composed of '10's 3 TX_MPOL Transmitter Manchester Polarity [12:12] read-write RX_PL Receiver Preamble Length [19:16] read-write 0 15 RX_PP Receiver Preamble Pattern detected [25:24] read-write true ALL_ONE The preamble is composed of '1's 0 ALL_ZERO The preamble is composed of '0's 1 ZERO_ONE The preamble is composed of '01's 2 ONE_ZERO The preamble is composed of '10's 3 RX_MPOL Receiver Manchester Polarity [28:28] read-write ONE Must Be Set to 1 [29:29] read-write DRIFT Drift Compensation [30:30] read-write RXIDLEV Receiver Idle Value [31:31] read-write US_MR USART Mode Register 0x204 0x20 read-write USART_MODE USART Mode of Operation [3:0] read-write true SPI_MASTER SPI master 14 SPI_SLAVE SPI slave 15 USCLKS Clock Selection [5:4] read-write true MCK Peripheral clock is selected 0 DIV Peripheral clock Divided (DIV= 8) is selected 1 GCLK A PMC generic clock is selected 2 SCK External pin SCK is selected 3 CHRL Character Length [7:6] read-write true 8_BIT Character length is 8 bits 3 CPHA SPI Clock Phase [8:8] read-write SYNC Synchronous Mode Select [8:8] read-write PAR Parity Type [11:9] read-write true EVEN Even parity 0 ODD Odd parity 1 SPACE Parity forced to 0 (Space) 2 MARK Parity forced to 1 (Mark) 3 NO No parity 4 MULTIDROP Multidrop mode 6 NBSTOP Number of Stop Bits [13:12] read-write true 1_BIT 1 stop bit 0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 1 2_BIT 2 stop bits 2 CHMODE Channel Mode [15:14] read-write true NORMAL Normal mode 0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 3 CPOL SPI Clock Polarity [16:16] read-write MSBF Bit Order [16:16] read-write MODE9 9-bit Character Length [17:17] read-write CLKO Clock Output Select [18:18] read-write OVER Oversampling Mode [19:19] read-write INACK Inhibit Non Acknowledge [20:20] read-write WRDBT Wait Read Data Before Transfer [20:20] read-write DSNACK Disable Successive NACK [21:21] read-write VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter [22:22] read-write INVDATA Inverted Data [23:23] read-write MAX_ITERATION Maximum Number of Automatic Iteration [26:24] read-write 0 7 FILTER Receive Line Filter [28:28] read-write MAN Manchester Encoder/Decoder Enable [29:29] read-write MODSYNC Manchester Synchronization Mode [30:30] read-write ONEBIT Start Frame Delimiter Selector [31:31] read-write US_NER USART Number of Errors Register 0x244 0x20 read-only NB_ERRORS Number of Errors [7:0] read-write 0 255 US_RHR USART Receive Holding Register 0x218 0x20 read-only RXCHR Received Character [8:0] read-write 0 511 RXCHR0 Received Character [7:0] read-write 0 255 RXCHR1 Received Character [15:8] read-write 0 255 RXSYNH Received Sync [15:15] read-write RXCHR2 Received Character [23:16] read-write 0 255 RXCHR3 Received Character [31:24] read-write 0 255 US_RTOR USART Receiver Timeout Register 0x224 0x20 read-write TO Timeout Value [16:0] read-write 0 131071 US_THR USART Transmit Holding Register 0x21C 0x20 write-only TXCHR Character to be Transmitted [8:0] read-write 0 511 TXCHR0 Character to be Transmitted [7:0] read-write 0 255 TXCHR1 Character to be Transmitted [15:8] read-write 0 255 TXSYNH Sync Field to be Transmitted [15:15] read-write TXCHR2 Character to be Transmitted [23:16] read-write 0 255 TXCHR3 Character to be Transmitted [31:24] read-write 0 255 US_TTGR USART Transmitter Timeguard Register 0x228 0x20 read-write TG Timeguard Value [7:0] read-write 0 255 US_WPMR USART Write Protection Mode Register 0x2E4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of bit WPEN. Always reads as 0. 5591873 US_WPSR USART Write Protection Status Register 0x2E8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [23:8] read-write 0 65535 FLEXCOM1 Flexible Serial Communication 0xF8038000 FLEXCOM2 Flexible Serial Communication 0xFC010000 FLEXCOM3 Flexible Serial Communication 0xFC014000 FLEXCOM4 Flexible Serial Communication 0xFC018000 GMAC Gigabit Ethernet MAC 0xF8008000 0x0 0x4C registers 0x80 0x8 registers 0xA8 0x28 registers 0xDC 0x1C registers 0x100 0xB4 registers 0x1BC 0x8 registers 0x1D0 0x30 registers 0x270 0x10 registers 0x400 0x4 registers 0x440 0x4 registers 0x480 0x4 registers 0x4A0 0x4 registers 0x4BC 0xC registers 0x500 0x4 registers 0x540 0x4 registers 0x600 0x4 registers 0x620 0x4 registers 0x640 0x4 registers 0x6E0 0x4 registers AE Alignment Errors Register 0x19C 0x20 read-only AER Alignment Errors [9:0] read-write 0 1023 BCFR Broadcast Frames Received Register 0x15C 0x20 read-only BFRX Broadcast Frames Received without Error [31:0] read-write 0 4294967295 BCFT Broadcast Frames Transmitted Register 0x10C 0x20 read-only BFTX Broadcast Frames Transmitted without Error [31:0] read-write 0 4294967295 BFR64 64 Byte Frames Received Register 0x168 0x20 read-only NFRX 64 Byte Frames Received without Error [31:0] read-write 0 4294967295 BFT64 64 Byte Frames Transmitted Register 0x118 0x20 read-only NFTX 64 Byte Frames Transmitted without Error [31:0] read-write 0 4294967295 CBSCR Credit-Based Shaping Control Register 0x4BC 0x20 read-write QBE Queue B CBS Enable [0:0] read-write QAE Queue A CBS Enable [1:1] read-write CBSISQA Credit-Based Shaping IdleSlope Register for Queue A 0x4C0 0x20 read-write IS IdleSlope [31:0] read-write 0 4294967295 CBSISQB Credit-Based Shaping IdleSlope Register for Queue B 0x4C4 0x20 read-write IS IdleSlope [31:0] read-write 0 4294967295 CSE Carrier Sense Errors Register 0x14C 0x20 read-only CSR Carrier Sense Error [9:0] read-write 0 1023 DCFGR DMA Configuration Register 0x10 0x20 read-write FBLDO Fixed Burst Length for DMA Data Operations: [4:0] read-write true SINGLE 00001: Always use SINGLE AHB bursts 1 INCR4 001xx: Attempt to use INCR4 AHB bursts (Default) 4 INCR8 01xxx: Attempt to use INCR8 AHB bursts 8 INCR16 1xxxx: Attempt to use INCR16 AHB bursts 16 ESMA Endian Swap Mode Enable for Management Descriptor Accesses [6:6] read-write ESPA Endian Swap Mode Enable for Packet Data Accesses [7:7] read-write RXBMS Receiver Packet Buffer Memory Size Select [9:8] read-write true EIGHTH 4/8 Kbyte Memory Size 0 QUARTER 4/4 Kbytes Memory Size 1 HALF 4/2 Kbytes Memory Size 2 FULL 4 Kbytes Memory Size 3 TXPBMS Transmitter Packet Buffer Memory Size Select [10:10] read-write TXCOEN Transmitter Checksum Generation Offload Enable [11:11] read-write DRBS DMA Receive Buffer Size [23:16] read-write 0 255 DDRP DMA Discard Receive Packets [24:24] read-write DTF Deferred Transmission Frames Register 0x148 0x20 read-only DEFT Deferred Transmission [17:0] read-write 0 262143 EC Excessive Collisions Register 0x140 0x20 read-only XCOL Excessive Collisions [9:0] read-write 0 1023 EFRN PTP Event Frame Received Nanoseconds Register 0x1EC 0x20 read-only RUD Register Update [29:0] read-write 0 1073741823 EFRSH PTP Event Frame Received Seconds High Register 0xEC 0x20 read-only RUD Register Update [15:0] read-write 0 65535 EFRSL PTP Event Frame Received Seconds Low Register 0x1E8 0x20 read-only RUD Register Update [31:0] read-write 0 4294967295 EFTN PTP Event Frame Transmitted Nanoseconds Register 0x1E4 0x20 read-only RUD Register Update [29:0] read-write 0 1073741823 EFTSH PTP Event Frame Transmitted Seconds High Register 0xE8 0x20 read-only RUD Register Update [15:0] read-write 0 65535 EFTSL PTP Event Frame Transmitted Seconds Low Register 0x1E0 0x20 read-only RUD Register Update [31:0] read-write 0 4294967295 FCSE Frame Check Sequence Errors Register 0x190 0x20 read-only FCKR Frame Check Sequence Errors [9:0] read-write 0 1023 FR Frames Received Register 0x158 0x20 read-only FRX Frames Received without Error [31:0] read-write 0 4294967295 FT Frames Transmitted Register 0x108 0x20 read-only FTX Frames Transmitted without Error [31:0] read-write 0 4294967295 GTBFT1518 Greater Than 1518 Byte Frames Transmitted Register 0x130 0x20 read-only NFTX Greater than 1518 Byte Frames Transmitted without Error [31:0] read-write 0 4294967295 HRB Hash Register Bottom 0x80 0x20 read-write ADDR Hash Address [31:0] read-write 0 4294967295 HRT Hash Register Top 0x84 0x20 read-write ADDR Hash Address [31:0] read-write 0 4294967295 IDR Interrupt Disable Register 0x2C 0x20 write-only MFS Management Frame Sent [0:0] read-write RCOMP Receive Complete [1:1] read-write RXUBR RX Used Bit Read [2:2] read-write TXUBR TX Used Bit Read [3:3] read-write TUR Transmit Underrun [4:4] read-write RLEX Retry Limit Exceeded or Late Collision [5:5] read-write TFC Transmit Frame Corruption Due to AHB Error [6:6] read-write TCOMP Transmit Complete [7:7] read-write ROVR Receive Overrun [10:10] read-write HRESP HRESP Not OK [11:11] read-write PFNZ Pause Frame with Non-zero Pause Quantum Received [12:12] read-write PTZ Pause Time Zero [13:13] read-write PFTR Pause Frame Transmitted [14:14] read-write EXINT External Interrupt [15:15] read-write DRQFR PTP Delay Request Frame Received [18:18] read-write SFR PTP Sync Frame Received [19:19] read-write DRQFT PTP Delay Request Frame Transmitted [20:20] read-write SFT PTP Sync Frame Transmitted [21:21] read-write PDRQFR PDelay Request Frame Received [22:22] read-write PDRSFR PDelay Response Frame Received [23:23] read-write PDRQFT PDelay Request Frame Transmitted [24:24] read-write PDRSFT PDelay Response Frame Transmitted [25:25] read-write SRI TSU Seconds Register Increment [26:26] read-write RXLPISBC Enable RX LPI Indication [27:27] read-write WOL Wake On LAN [28:28] read-write TSUTIMCOMP TSU Timer Comparison [29:29] read-write IDRPQ Interrupt Disable Register Priority Queue (1..2) 0x620 0x20 write-only RCOMP Receive Complete [1:1] read-write RXUBR RX Used Bit Read [2:2] read-write RLEX Retry Limit Exceeded or Late Collision [5:5] read-write TFC Transmit Frame Corruption Due to AHB Error [6:6] read-write TCOMP Transmit Complete [7:7] read-write ROVR Receive Overrun [10:10] read-write HRESP HRESP Not OK [11:11] read-write IER Interrupt Enable Register 0x28 0x20 write-only MFS Management Frame Sent [0:0] read-write RCOMP Receive Complete [1:1] read-write RXUBR RX Used Bit Read [2:2] read-write TXUBR TX Used Bit Read [3:3] read-write TUR Transmit Underrun [4:4] read-write RLEX Retry Limit Exceeded or Late Collision [5:5] read-write TFC Transmit Frame Corruption Due to AHB Error [6:6] read-write TCOMP Transmit Complete [7:7] read-write ROVR Receive Overrun [10:10] read-write HRESP HRESP Not OK [11:11] read-write PFNZ Pause Frame with Non-zero Pause Quantum Received [12:12] read-write PTZ Pause Time Zero [13:13] read-write PFTR Pause Frame Transmitted [14:14] read-write EXINT External Interrupt [15:15] read-write DRQFR PTP Delay Request Frame Received [18:18] read-write SFR PTP Sync Frame Received [19:19] read-write DRQFT PTP Delay Request Frame Transmitted [20:20] read-write SFT PTP Sync Frame Transmitted [21:21] read-write PDRQFR PDelay Request Frame Received [22:22] read-write PDRSFR PDelay Response Frame Received [23:23] read-write PDRQFT PDelay Request Frame Transmitted [24:24] read-write PDRSFT PDelay Response Frame Transmitted [25:25] read-write SRI TSU Seconds Register Increment [26:26] read-write RXLPISBC Enable RX LPI Indication [27:27] read-write WOL Wake On LAN [28:28] read-write TSUTIMCOMP TSU Timer Comparison [29:29] read-write IERPQ Interrupt Enable Register Priority Queue (1..2) 0x600 0x20 write-only RCOMP Receive Complete [1:1] read-write RXUBR RX Used Bit Read [2:2] read-write RLEX Retry Limit Exceeded or Late Collision [5:5] read-write TFC Transmit Frame Corruption Due to AHB Error [6:6] read-write TCOMP Transmit Complete [7:7] read-write ROVR Receive Overrun [10:10] read-write HRESP HRESP Not OK [11:11] read-write IHCE IP Header Checksum Errors Register 0x1A8 0x20 read-only HCKER IP Header Checksum Errors [7:0] read-write 0 255 IMR Interrupt Mask Register 0x30 0x20 read-write MFS Management Frame Sent [0:0] read-write RCOMP Receive Complete [1:1] read-write RXUBR RX Used Bit Read [2:2] read-write TXUBR TX Used Bit Read [3:3] read-write TUR Transmit Underrun [4:4] read-write RLEX Retry Limit Exceeded [5:5] read-write TFC Transmit Frame Corruption Due to AHB Error [6:6] read-write TCOMP Transmit Complete [7:7] read-write ROVR Receive Overrun [10:10] read-write HRESP HRESP Not OK [11:11] read-write PFNZ Pause Frame with Non-zero Pause Quantum Received [12:12] read-write PTZ Pause Time Zero [13:13] read-write PFTR Pause Frame Transmitted [14:14] read-write EXINT External Interrupt [15:15] read-write DRQFR PTP Delay Request Frame Received [18:18] read-write SFR PTP Sync Frame Received [19:19] read-write DRQFT PTP Delay Request Frame Transmitted [20:20] read-write SFT PTP Sync Frame Transmitted [21:21] read-write PDRQFR PDelay Request Frame Received [22:22] read-write PDRSFR PDelay Response Frame Received [23:23] read-write PDRQFT PDelay Request Frame Transmitted [24:24] read-write PDRSFT PDelay Response Frame Transmitted [25:25] read-write SRI TSU Seconds Register Increment [26:26] read-write RXLPISBC Enable RX LPI Indication [27:27] read-write WOL Wake On LAN [28:28] read-write TSUTIMCOMP TSU Timer Comparison [29:29] read-write IMRPQ Interrupt Mask Register Priority Queue (1..2) 0x640 0x20 read-write RCOMP Receive Complete [1:1] read-write RXUBR RX Used Bit Read [2:2] read-write RLEX Retry Limit Exceeded or Late Collision [5:5] read-write AHB AHB Error [6:6] read-write TCOMP Transmit Complete [7:7] read-write ROVR Receive Overrun [10:10] read-write HRESP HRESP Not OK [11:11] read-write IPGS IPG Stretch Register 0xBC 0x20 read-write FL Frame Length [15:0] read-write 0 65535 ISR Interrupt Status Register 0x24 0x20 read-only MFS Management Frame Sent [0:0] read-write RCOMP Receive Complete [1:1] read-write RXUBR RX Used Bit Read [2:2] read-write TXUBR TX Used Bit Read [3:3] read-write TUR Transmit Underrun [4:4] read-write RLEX Retry Limit Exceeded [5:5] read-write TFC Transmit Frame Corruption Due to AHB Error [6:6] read-write TCOMP Transmit Complete [7:7] read-write ROVR Receive Overrun [10:10] read-write HRESP HRESP Not OK [11:11] read-write PFNZ Pause Frame with Non-zero Pause Quantum Received [12:12] read-write PTZ Pause Time Zero [13:13] read-write PFTR Pause Frame Transmitted [14:14] read-write DRQFR PTP Delay Request Frame Received [18:18] read-write SFR PTP Sync Frame Received [19:19] read-write DRQFT PTP Delay Request Frame Transmitted [20:20] read-write SFT PTP Sync Frame Transmitted [21:21] read-write PDRQFR PDelay Request Frame Received [22:22] read-write PDRSFR PDelay Response Frame Received [23:23] read-write PDRQFT PDelay Request Frame Transmitted [24:24] read-write PDRSFT PDelay Response Frame Transmitted [25:25] read-write SRI TSU Seconds Register Increment [26:26] read-write RXLPISBC Receive LPI indication Status Bit Change [27:27] read-write WOL Wake On LAN [28:28] read-write TSUTIMCOMP TSU Timer Comparison [29:29] read-write ISRPQ Interrupt Status Register Priority Queue (1..2) 0x400 0x20 read-only RCOMP Receive Complete [1:1] read-write RXUBR RX Used Bit Read [2:2] read-write RLEX Retry Limit Exceeded or Late Collision [5:5] read-write TFC Transmit Frame Corruption Due to AHB Error [6:6] read-write TCOMP Transmit Complete [7:7] read-write ROVR Receive Overrun [10:10] read-write HRESP HRESP Not OK [11:11] read-write JR Jabbers Received Register 0x18C 0x20 read-only JRX Jabbers Received [9:0] read-write 0 1023 LC Late Collisions Register 0x144 0x20 read-only LCOL Late Collisions [9:0] read-write 0 1023 LFFE Length Field Frame Errors Register 0x194 0x20 read-only LFER Length Field Frame Errors [9:0] read-write 0 1023 MAN PHY Maintenance Register 0x34 0x20 read-write DATA PHY Data [15:0] read-write 0 65535 WTN Write Ten [17:16] read-write 0 3 REGA Register Address [22:18] read-write 0 31 PHYA PHY Address [27:23] read-write 0 31 OP Operation [29:28] read-write 0 3 CLTTO Clause 22 Operation [30:30] read-write WZO Write ZERO [31:31] read-write MCF Multiple Collision Frames Register 0x13C 0x20 read-only MCOL Multiple Collision [17:0] read-write 0 262143 MFR Multicast Frames Received Register 0x160 0x20 read-only MFRX Multicast Frames Received without Error [31:0] read-write 0 4294967295 MFT Multicast Frames Transmitted Register 0x110 0x20 read-only MFTX Multicast Frames Transmitted without Error [31:0] read-write 0 4294967295 NCFGR Network Configuration Register 0x4 0x20 read-write SPD Speed [0:0] read-write FD Full Duplex [1:1] read-write DNVLAN Discard Non-VLAN FRAMES [2:2] read-write JFRAME Jumbo Frame Size [3:3] read-write CAF Copy All Frames [4:4] read-write NBC No Broadcast [5:5] read-write MTIHEN Multicast Hash Enable [6:6] read-write UNIHEN Unicast Hash Enable [7:7] read-write MAXFS 1536 Maximum Frame Size [8:8] read-write RTY Retry Test [12:12] read-write PEN Pause Enable [13:13] read-write RXBUFO Receive Buffer Offset [15:14] read-write 0 3 LFERD Length Field Error Frame Discard [16:16] read-write RFCS Remove FCS [17:17] read-write CLK MDC CLock Division [20:18] read-write true MCK_8 MCK divided by 8 (MCK up to 20 MHz) 0 MCK_16 MCK divided by 16 (MCK up to 40 MHz) 1 MCK_32 MCK divided by 32 (MCK up to 80 MHz) 2 MCK_48 MCK divided by 48 (MCK up to 120 MHz) 3 MCK_64 MCK divided by 64 (MCK up to 160 MHz) 4 MCK_96 MCK divided by 96 (MCK up to 240 MHz) 5 DBW Data Bus Width [22:21] read-write 0 3 DCPF Disable Copy of Pause Frames [23:23] read-write RXCOEN Receive Checksum Offload Enable [24:24] read-write EFRHD Enable Frames Received in Half Duplex [25:25] read-write IRXFCS Ignore RX FCS [26:26] read-write IPGSEN IP Stretch Enable [28:28] read-write RXBP Receive Bad Preamble [29:29] read-write IRXER Ignore IPG GRXER [30:30] read-write NCR Network Control Register 0x0 0x20 read-write LBL Loop Back Local [1:1] read-write RXEN Receive Enable [2:2] read-write TXEN Transmit Enable [3:3] read-write MPE Management Port Enable [4:4] read-write CLRSTAT Clear Statistics Registers [5:5] read-write INCSTAT Increment Statistics Registers [6:6] read-write WESTAT Write Enable for Statistics Registers [7:7] read-write BP Back pressure [8:8] read-write TSTART Start Transmission [9:9] read-write THALT Transmit Halt [10:10] read-write TXPF Transmit Pause Frame [11:11] read-write TXZQPF Transmit Zero Quantum Pause Frame [12:12] read-write SRTSM Store Receive Timestamp to Memory [15:15] read-write ENPBPR Enable PFC Priority-based Pause Reception [16:16] read-write TXPBPF Transmit PFC Priority-based Pause Frame [17:17] read-write FNP Flush Next Packet [18:18] read-write TXLPIEN Enable LPI Transmission [19:19] read-write NSC 1588 Timer Nanosecond Comparison Register 0xDC 0x20 read-write NANOSEC 1588 Timer Nanosecond Comparison Value [21:0] read-write 0 4194303 NSR Network Status Register 0x8 0x20 read-only MDIO MDIO Input Status [1:1] read-write IDLE PHY Management Logic Idle [2:2] read-write RXLPIS LPI Indication [7:7] read-write OFR Oversize Frames Received Register 0x188 0x20 read-only OFRX Oversized Frames Received [9:0] read-write 0 1023 ORHI Octets Received High Received Register 0x154 0x20 read-only RXO Received Octets [15:0] read-write 0 65535 ORLO Octets Received Low Received Register 0x150 0x20 read-only RXO Received Octets [31:0] read-write 0 4294967295 OTHI Octets Transmitted High Register 0x104 0x20 read-only TXO Transmitted Octets [15:0] read-write 0 65535 OTLO Octets Transmitted Low Register 0x100 0x20 read-only TXO Transmitted Octets [31:0] read-write 0 4294967295 PEFRN PTP Peer Event Frame Received Nanoseconds Register 0x1FC 0x20 read-only RUD Register Update [29:0] read-write 0 1073741823 PEFRSH PTP Peer Event Frame Received Seconds High Register 0xF4 0x20 read-only RUD Register Update [15:0] read-write 0 65535 PEFRSL PTP Peer Event Frame Received Seconds Low Register 0x1F8 0x20 read-only RUD Register Update [31:0] read-write 0 4294967295 PEFTN PTP Peer Event Frame Transmitted Nanoseconds Register 0x1F4 0x20 read-only RUD Register Update [29:0] read-write 0 1073741823 PEFTSH PTP Peer Event Frame Transmitted Seconds High Register 0xF0 0x20 read-only RUD Register Update [15:0] read-write 0 65535 PEFTSL PTP Peer Event Frame Transmitted Seconds Low Register 0x1F0 0x20 read-only RUD Register Update [31:0] read-write 0 4294967295 PFR Pause Frames Received Register 0x164 0x20 read-only PFRX Pause Frames Received Register [15:0] read-write 0 65535 PFT Pause Frames Transmitted Register 0x114 0x20 read-only PFTX Pause Frames Transmitted Register [15:0] read-write 0 65535 RBQB Receive Buffer Queue Base Address Register 0x18 0x20 read-write ADDR Receive Buffer Queue Base Address [31:2] read-write 0 1073741823 RBQBAPQ Receive Buffer Queue Base Address Register Priority Queue (1..2) 0x480 0x20 read-write RXBQBA Receive Buffer Queue Base Address [31:2] read-write 0 1073741823 RBSRPQ Receive Buffer Size Register Priority Queue (1..2) 0x4A0 0x20 read-write RBS Receive Buffer Size [15:0] read-write 0 65535 RJFML RX Jumbo Frame Max Length Register 0x48 0x20 read-write FML Frame Max Length [13:0] read-write 0 16383 ROE Receive Overrun Register 0x1A4 0x20 read-only RXOVR Receive Overruns [9:0] read-write 0 1023 RPQ Received Pause Quantum Register 0x38 0x20 read-only RPQ Received Pause Quantum [15:0] read-write 0 65535 RPSF RX Partial Store and Forward Register 0x44 0x20 read-write RPB1ADR Receive Partial Store and Forward Address [11:0] read-write 0 4095 ENRXP Enable RX Partial Store and Forward Operation [31:31] read-write RRE Receive Resource Errors Register 0x1A0 0x20 read-only RXRER Receive Resource Errors [17:0] read-write 0 262143 RSE Receive Symbol Errors Register 0x198 0x20 read-only RXSE Receive Symbol Errors [9:0] read-write 0 1023 RSR Receive Status Register 0x20 0x20 read-write BNA Buffer Not Available [0:0] read-write REC Frame Received [1:1] read-write RXOVR Receive Overrun [2:2] read-write HNO HRESP Not OK [3:3] read-write RXLPI Received LPI Transitions 0x270 0x20 read-only COUNT Count of RX LPI transitions (cleared on read) [15:0] read-write 0 65535 RXLPITIME Received LPI Time 0x274 0x20 read-only LPITIME Time in LPI (cleared on read) [23:0] read-write 0 16777215 SAMB1 Specific Address 1 Mask Bottom Register 0xC8 0x20 read-write ADDR Specific Address 1 Mask [31:0] read-write 0 4294967295 SAMT1 Specific Address 1 Mask Top Register 0xCC 0x20 read-write ADDR Specific Address 1 Mask [15:0] read-write 0 65535 SCF Single Collision Frames Register 0x138 0x20 read-only SCOL Single Collision [17:0] read-write 0 262143 SCH 1588 Timer Second Comparison High Register 0xE4 0x20 read-write SEC 1588 Timer Second Comparison Value [15:0] read-write 0 65535 SCL 1588 Timer Second Comparison Low Register 0xE0 0x20 read-write SEC 1588 Timer Second Comparison Value [31:0] read-write 0 4294967295 ST1RPQ Screening Type 1 Register Priority Queue 0x500 0x20 read-write QNB Queue Number (0-2) [2:0] read-write 0 7 DSTCM Differentiated Services or Traffic Class Match [11:4] read-write 0 255 UDPM UDP Port Match [27:12] read-write 0 65535 DSTCE Differentiated Services or Traffic Class Match Enable [28:28] read-write UDPE UDP Port Match Enable [29:29] read-write ST2ER Screening Type 2 Ethertype Register 0x6E0 0x20 read-write COMPVAL Ethertype Compare Value [15:0] read-write 0 65535 ST2RPQ Screening Type 2 Register Priority Queue 0x540 0x20 read-write QNB Queue Number (0-2) [2:0] read-write 0 7 VLANP VLAN Priority [6:4] read-write 0 7 VLANE VLAN Enable [8:8] read-write I2ETH Index of Screening Type 2 EtherType register x [11:9] read-write 0 7 ETHE EtherType Enable [12:12] read-write COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x [17:13] read-write 0 31 COMPAE Compare A Enable [18:18] read-write COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x [23:19] read-write 0 31 COMPBE Compare B Enable [24:24] read-write COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x [29:25] read-write 0 31 COMPCE Compare C Enable [30:30] read-write SVLAN Stacked VLAN Register 0xC0 0x20 read-write VLAN_TYPE User Defined VLAN_TYPE Field [15:0] read-write 0 65535 ESVLAN Enable Stacked VLAN Processing Mode [31:31] read-write TA 1588 Timer Adjust Register 0x1D8 0x20 write-only ITDT Increment/Decrement [29:0] read-write 0 1073741823 ADJ Adjust 1588 Timer [31:31] read-write TBFR1023 512 to 1023 Byte Frames Received Register 0x178 0x20 read-only NFRX 512 to 1023 Byte Frames Received without Error [31:0] read-write 0 4294967295 TBFR127 65 to 127 Byte Frames Received Register 0x16C 0x20 read-only NFRX 65 to 127 Byte Frames Received without Error [31:0] read-write 0 4294967295 TBFR1518 1024 to 1518 Byte Frames Received Register 0x17C 0x20 read-only NFRX 1024 to 1518 Byte Frames Received without Error [31:0] read-write 0 4294967295 TBFR255 128 to 255 Byte Frames Received Register 0x170 0x20 read-only NFRX 128 to 255 Byte Frames Received without Error [31:0] read-write 0 4294967295 TBFR511 256 to 511 Byte Frames Received Register 0x174 0x20 read-only NFRX 256 to 511 Byte Frames Received without Error [31:0] read-write 0 4294967295 TBFT1023 512 to 1023 Byte Frames Transmitted Register 0x128 0x20 read-only NFTX 512 to 1023 Byte Frames Transmitted without Error [31:0] read-write 0 4294967295 TBFT127 65 to 127 Byte Frames Transmitted Register 0x11C 0x20 read-only NFTX 65 to 127 Byte Frames Transmitted without Error [31:0] read-write 0 4294967295 TBFT1518 1024 to 1518 Byte Frames Transmitted Register 0x12C 0x20 read-only NFTX 1024 to 1518 Byte Frames Transmitted without Error [31:0] read-write 0 4294967295 TBFT255 128 to 255 Byte Frames Transmitted Register 0x120 0x20 read-only NFTX 128 to 255 Byte Frames Transmitted without Error [31:0] read-write 0 4294967295 TBFT511 256 to 511 Byte Frames Transmitted Register 0x124 0x20 read-only NFTX 256 to 511 Byte Frames Transmitted without Error [31:0] read-write 0 4294967295 TBQB Transmit Buffer Queue Base Address Register 0x1C 0x20 read-write ADDR Transmit Buffer Queue Base Address [31:2] read-write 0 1073741823 TBQBAPQ Transmit Buffer Queue Base Address Register Priority Queue (1..2) 0x440 0x20 read-write TXBQBA Transmit Buffer Queue Base Address [31:2] read-write 0 1073741823 TCE TCP Checksum Errors Register 0x1AC 0x20 read-only TCKER TCP Checksum Errors [7:0] read-write 0 255 TI 1588 Timer Increment Register 0x1DC 0x20 read-write CNS Count Nanoseconds [7:0] read-write 0 255 ACNS Alternative Count Nanoseconds [15:8] read-write 0 255 NIT Number of Increments [23:16] read-write 0 255 TIDM1 Type ID Match 1 Register 0xA8 0x20 read-write TID Type ID Match 1 [15:0] read-write 0 65535 ENID1 Enable Copying of TID Matched Frames [31:31] read-write TIDM2 Type ID Match 2 Register 0xAC 0x20 read-write TID Type ID Match 2 [15:0] read-write 0 65535 ENID2 Enable Copying of TID Matched Frames [31:31] read-write TIDM3 Type ID Match 3 Register 0xB0 0x20 read-write TID Type ID Match 3 [15:0] read-write 0 65535 ENID3 Enable Copying of TID Matched Frames [31:31] read-write TIDM4 Type ID Match 4 Register 0xB4 0x20 read-write TID Type ID Match 4 [15:0] read-write 0 65535 ENID4 Enable Copying of TID Matched Frames [31:31] read-write TISUBN 1588 Timer Increment Sub-nanoseconds Register 0x1BC 0x20 read-write LSBTIR Lower Significant Bits of Timer Increment Register [15:0] read-write 0 65535 TMXBFR 1519 to Maximum Byte Frames Received Register 0x180 0x20 read-only NFRX 1519 to Maximum Byte Frames Received without Error [31:0] read-write 0 4294967295 TN 1588 Timer Nanoseconds Register 0x1D4 0x20 read-write TNS Timer Count in Nanoseconds [29:0] read-write 0 1073741823 TPFCP Transmit PFC Pause Register 0xC4 0x20 read-write PEV Priority Enable Vector [7:0] read-write 0 255 PQ Pause Quantum [15:8] read-write 0 255 TPQ Transmit Pause Quantum Register 0x3C 0x20 read-write TPQ Transmit Pause Quantum [15:0] read-write 0 65535 TPSF TX Partial Store and Forward Register 0x40 0x20 read-write TPB1ADR Transmit Partial Store and Forward Address [11:0] read-write 0 4095 ENTXP Enable TX Partial Store and Forward Operation [31:31] read-write TSH 1588 Timer Seconds High Register 0x1C0 0x20 read-write TCS Timer Count in Seconds [15:0] read-write 0 65535 TSL 1588 Timer Seconds Low Register 0x1D0 0x20 read-write TCS Timer Count in Seconds [31:0] read-write 0 4294967295 TSR Transmit Status Register 0x14 0x20 read-write UBR Used Bit Read [0:0] read-write COL Collision Occurred [1:1] read-write RLE Retry Limit Exceeded [2:2] read-write TXGO Transmit Go [3:3] read-write TFC Transmit Frame Corruption Due to AHB Error [4:4] read-write TXCOMP Transmit Complete [5:5] read-write HRESP HRESP Not OK [8:8] read-write TUR Transmit Underruns Register 0x134 0x20 read-only TXUNR Transmit Underruns [9:0] read-write 0 1023 TXLPI Transmit LPI Transitions 0x278 0x20 read-only COUNT Count of LPI transitions (cleared on read) [15:0] read-write 0 65535 TXLPITIME Transmit LPI Time 0x27C 0x20 read-only LPITIME Time in LPI (cleared on read) [23:0] read-write 0 16777215 UCE UDP Checksum Errors Register 0x1B0 0x20 read-only UCKER UDP Checksum Errors [7:0] read-write 0 255 UFR Undersize Frames Received Register 0x184 0x20 read-only UFRX Undersize Frames Received [9:0] read-write 0 1023 UR User Register 0xC 0x20 read-write RMII Reduced MII Mode [0:0] read-write WOL Wake on LAN Register 0xB8 0x20 read-write IP ARP Request IP Address [15:0] read-write 0 65535 MAG Magic Packet Event Enable [16:16] read-write ARP ARP Request IP Address [17:17] read-write SA1 Specific Address Register 1 Event Enable [18:18] read-write MTI Multicast Hash Event Enable [19:19] read-write I2SC0 Inter-IC Sound Controller 0xF8050000 0x0 0x28 registers CR Control Register 0x0 0x20 write-only RXEN Receiver Enable [0:0] read-write RXDIS Receiver Disable [1:1] read-write CKEN Clocks Enable [2:2] read-write CKDIS Clocks Disable [3:3] read-write TXEN Transmitter Enable [4:4] read-write TXDIS Transmitter Disable [5:5] read-write SWRST Software Reset [7:7] read-write IDR Interrupt Disable Register 0x18 0x20 write-only RXRDY Receiver Ready Interrupt Disable [1:1] read-write RXOR Receiver Overrun Interrupt Disable [2:2] read-write TXRDY Transmit Ready Interrupt Disable [5:5] read-write TXUR Transmit Underflow Interrupt Disable [6:6] read-write IER Interrupt Enable Register 0x14 0x20 write-only RXRDY Receiver Ready Interrupt Enable [1:1] read-write RXOR Receiver Overrun Interrupt Enable [2:2] read-write TXRDY Transmit Ready Interrupt Enable [5:5] read-write TXUR Transmit Underflow Interrupt Enable [6:6] read-write IMR Interrupt Mask Register 0x1C 0x20 read-only RXRDY Receiver Ready Interrupt Disable [1:1] read-write RXOR Receiver Overrun Interrupt Disable [2:2] read-write TXRDY Transmit Ready Interrupt Disable [5:5] read-write TXUR Transmit Underflow Interrupt Disable [6:6] read-write MR Mode Register 0x4 0x20 read-write MODE Inter-IC Sound Controller Mode [0:0] read-write true SLAVE I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization. 0 MASTER Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set. 1 DATALENGTH Data Word Length [4:2] read-write true _32_BITS Data length is set to 32 bits 0 _24_BITS Data length is set to 24 bits 1 _20_BITS Data length is set to 20 bits 2 _18_BITS Data length is set to 18 bits 3 _16_BITS Data length is set to 16 bits 4 _16_BITS_COMPACT Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. 5 _8_BITS Data length is set to 8 bits 6 _8_BITS_COMPACT Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. 7 FORMAT Data Format [7:6] read-write true I2S I2S format, stereo with I2SC_WS low for left channel, and MSB of sample starting one I2SC_CK period after I2SC_WS edge 0 LJ Left-justified format, stereo with I2SC_WS high for left channel, and MSB of sample starting on I2SC_WS edge 1 RXMONO Receive Mono [8:8] read-write RXLOOP Loopback Test Mode [10:10] read-write TXMONO Transmit Mono [12:12] read-write TXSAME Transmit Data when Underrun [14:14] read-write IMCKDIV Selected Clock to I2SC Master Clock Ratio [21:16] read-write 0 63 IMCKFS Master Clock to fs Ratio [29:24] read-write true M2SF32 Sample frequency ratio set to 32 0 M2SF64 Sample frequency ratio set to 64 1 M2SF96 Sample frequency ratio set to 96 2 M2SF128 Sample frequency ratio set to 128 3 M2SF192 Sample frequency ratio set to 192 5 M2SF256 Sample frequency ratio set to 256 7 M2SF384 Sample frequency ratio set to 384 11 M2SF512 Sample frequency ratio set to 512 15 M2SF768 Sample frequency ratio set to 768 23 M2SF1024 Sample frequency ratio set to 1024 31 M2SF1536 Sample frequency ratio set to 1536 47 M2SF2048 Sample frequency ratio set to 2048 63 IMCKMODE Master Clock Mode [30:30] read-write IWS I2SC_WS Slot Width [31:31] read-write RHR Receiver Holding Register 0x20 0x20 read-only RHR Receiver Holding Register [31:0] read-write 0 4294967295 SCR Status Clear Register 0xC 0x20 write-only RXOR Receive Overrun Status Clear [2:2] read-write TXUR Transmit Underrun Status Clear [6:6] read-write RXORCH Receive Overrun Per Channel Status Clear [9:8] read-write 0 3 TXURCH Transmit Underrun Per Channel Status Clear [21:20] read-write 0 3 SR Status Register 0x8 0x20 read-only RXEN Receiver Enabled [0:0] read-write RXRDY Receive Ready [1:1] read-write RXOR Receive Overrun [2:2] read-write TXEN Transmitter Enabled [4:4] read-write TXRDY Transmit Ready [5:5] read-write TXUR Transmit Underrun [6:6] read-write RXORCH Receive Overrun Channel [9:8] read-write 0 3 TXURCH Transmit Underrun Channel [21:20] read-write 0 3 SSR Status Set Register 0x10 0x20 write-only RXOR Receive Overrun Status Set [2:2] read-write TXUR Transmit Underrun Status Set [6:6] read-write RXORCH Receive Overrun Per Channel Status Set [9:8] read-write 0 3 TXURCH Transmit Underrun Per Channel Status Set [21:20] read-write 0 3 THR Transmitter Holding Register 0x24 0x20 write-only THR Transmitter Holding Register [31:0] read-write 0 4294967295 I2SC1 Inter-IC Sound Controller 0xFC04C000 ICM Integrity Check Monitor 0xF8040000 0x0 0xC registers 0x10 0x14 registers 0x30 0xC registers CFG Configuration Register 0x0 0x20 read-write WBDIS Write Back Disable [0:0] read-write EOMDIS End of Monitoring Disable [1:1] read-write SLBDIS Secondary List Branching Disable [2:2] read-write BBC Bus Burden Control [7:4] read-write 0 15 ASCD Automatic Switch To Compare Digest [8:8] read-write DUALBUFF Dual Input Buffer [9:9] read-write UIHASH User Initial Hash Value [12:12] read-write UALGO User SHA Algorithm [15:13] read-write true SHA1 SHA1 algorithm processed 0 SHA256 SHA256 algorithm processed 1 SHA224 SHA224 algorithm processed 4 HAPROT Region Hash Area Protection [21:16] read-write 0 63 DAPROT Region Descriptor Area Protection [29:24] read-write 0 63 CTRL Control Register 0x4 0x20 write-only ENABLE ICM Enable [0:0] read-write DISABLE ICM Disable Register [1:1] read-write SWRST Software Reset [2:2] read-write REHASH Recompute Internal Hash [7:4] read-write 0 15 RMDIS Region Monitoring Disable [11:8] read-write 0 15 RMEN Region Monitoring Enable [15:12] read-write 0 15 DSCR Region Descriptor Area Start Address Register 0x30 0x20 read-write DASA Descriptor Area Start Address [31:6] read-write 0 67108863 HASH Region Hash Area Start Address Register 0x34 0x20 read-write HASA Hash Area Start Address [31:7] read-write 0 33554431 IDR Interrupt Disable Register 0x14 0x20 write-only RHC Region Hash Completed Interrupt Disable [3:0] read-write 0 15 RDM Region Digest Mismatch Interrupt Disable [7:4] read-write 0 15 RBE Region Bus Error Interrupt Disable [11:8] read-write 0 15 RWC Region Wrap Condition Detected Interrupt Disable [15:12] read-write 0 15 REC Region End bit Condition detected Interrupt Disable [19:16] read-write 0 15 RSU Region Status Updated Interrupt Disable [23:20] read-write 0 15 URAD Undefined Register Access Detection Interrupt Disable [24:24] read-write IER Interrupt Enable Register 0x10 0x20 write-only RHC Region Hash Completed Interrupt Enable [3:0] read-write 0 15 RDM Region Digest Mismatch Interrupt Enable [7:4] read-write 0 15 RBE Region Bus Error Interrupt Enable [11:8] read-write 0 15 RWC Region Wrap Condition detected Interrupt Enable [15:12] read-write 0 15 REC Region End bit Condition Detected Interrupt Enable [19:16] read-write 0 15 RSU Region Status Updated Interrupt Disable [23:20] read-write 0 15 URAD Undefined Register Access Detection Interrupt Enable [24:24] read-write IMR Interrupt Mask Register 0x18 0x20 read-only RHC Region Hash Completed Interrupt Mask [3:0] read-write 0 15 RDM Region Digest Mismatch Interrupt Mask [7:4] read-write 0 15 RBE Region Bus Error Interrupt Mask [11:8] read-write 0 15 RWC Region Wrap Condition Detected Interrupt Mask [15:12] read-write 0 15 REC Region End bit Condition Detected Interrupt Mask [19:16] read-write 0 15 RSU Region Status Updated Interrupt Mask [23:20] read-write 0 15 URAD Undefined Register Access Detection Interrupt Mask [24:24] read-write ISR Interrupt Status Register 0x1C 0x20 read-only RHC Region Hash Completed [3:0] read-write 0 15 RDM Region Digest Mismatch [7:4] read-write 0 15 RBE Region Bus Error [11:8] read-write 0 15 RWC Region Wrap Condition Detected [15:12] read-write 0 15 REC Region End Bit Condition Detected [19:16] read-write 0 15 RSU Region Status Updated Detected [23:20] read-write 0 15 URAD Undefined Register Access Detection Status [24:24] read-write SR Status Register 0x8 0x20 read-only ENABLE ICM Enable Register [0:0] read-write RAWRMDIS Region Monitoring Disabled Raw Status [11:8] read-write 0 15 RMDIS Region Monitoring Disabled Status [15:12] read-write 0 15 UASR Undefined Access Status Register 0x20 0x20 read-only URAT Undefined Register Access Trace [2:0] read-write true UNSPEC_STRUCT_MEMBER Unspecified structure member set to one detected when the descriptor is loaded. 0 ICM_CFG_MODIFIED ICM_CFG modified during active monitoring. 1 ICM_DSCR_MODIFIED ICM_DSCR modified during active monitoring. 2 ICM_HASH_MODIFIED ICM_HASH modified during active monitoring 3 READ_ACCESS Write-only register read access 4 UIHVAL User Initial Hash Value 0 Register 0x38 0x20 write-only VAL Initial Hash Value [31:0] read-write 0 4294967295 ISC Image Sensor Controller 0xF0008000 0x0 0x38 registers 0x58 0x44 registers 0x198 0x4 registers 0x298 0x4 registers 0x398 0x44 registers 0x3E0 0xC registers 0x410 0x4 registers CBC_BRIGHT Contrast and Brightness, Brightness Register 0x3BC 0x20 read-write BRIGHT Brightness Control (signed 11 bits 1:10:0) [10:0] read-write 0 2047 CBC_CFG Contrast and Brightness Configuration Register 0x3B8 0x20 read-write CCIR CCIR656 Stream Enable [0:0] read-write CCIRMODE CCIR656 Byte Ordering [2:1] read-write true CBY Byte ordering Cb0, Y0, Cr0, Y1 0 CRY Byte ordering Cr0, Y0, Cb0, Y1 1 YCB Byte ordering Y0, Cb0, Y1, Cr0 2 YCR Byte ordering Y0, Cr0, Y1, Cb0 3 CBC_CONTRAST Contrast and Brightness, Contrast Register 0x3C0 0x20 read-write CONTRAST Contrast (unsigned 12 bits 0:4:8) [11:0] read-write 0 4095 CBC_CTRL Contrast and Brightness Control Register 0x3B4 0x20 read-write ENABLE Contrast and Brightness Control Enable [0:0] read-write CC_BB_OB Color Correction BB OB Register 0x90 0x20 read-write BBGAIN Blue Gain for Blue Component (signed 12 bits, 1:3:8) [11:0] read-write 0 4095 BOFST Blue Component Offset (signed 13 bits, 1:12:0) [28:16] read-write 0 8191 CC_BR_BG Color Correction BR BG Register 0x8C 0x20 read-write BRGAIN Red Gain for Blue Component (signed 12 bits, 1:3:8) [11:0] read-write 0 4095 BGGAIN Green Gain for Blue Component (signed 12 bits, 1:3:8) [27:16] read-write 0 4095 CC_CTRL Color Correction Control Register 0x78 0x20 read-write ENABLE Color Correction Enable [0:0] read-write CC_GB_OG Color Correction GB OG Register 0x88 0x20 read-write GBGAIN Blue Gain for Green Component (signed 12 bits, 1:3:8) [11:0] read-write 0 4095 ROFST Green Component Offset (signed 13 bits, 1:12:0) [28:16] read-write 0 8191 CC_GR_GG Color Correction GR GG Register 0x84 0x20 read-write GRGAIN Red Gain for Green Component (signed 12 bits, 1:3:8) [11:0] read-write 0 4095 GGGAIN Green Gain for Green Component (signed 12 bits, 1:3:8) [27:16] read-write 0 4095 CC_RB_OR Color Correction RB OR Register 0x80 0x20 read-write RBGAIN Blue Gain for Red Component (signed 12 bits, 1:3:8) [11:0] read-write 0 4095 ROFST Red Component Offset (signed 13 bits, 1:12:0) [28:16] read-write 0 8191 CC_RR_RG Color Correction RR RG Register 0x7C 0x20 read-write RRGAIN Red Gain for Red Component (signed 12 bits, 1:3:8) [11:0] read-write 0 4095 RGGAIN Green Gain for Red Component (signed 12 bits, 1:3:8) [27:16] read-write 0 4095 CFA_CFG Color Filter Array Configuration Register 0x74 0x20 read-write BAYCFG Color Filter Array Pattern [1:0] read-write true GRGR Starting row configuration is G R G R (red row) 0 RGRG Starting row configuration is R G R G (red row 1 GBGB Starting row configuration is G B G B (blue row) 2 BGBG Starting row configuration is B G B G (blue row) 3 EITPOL Edge Interpolation [4:4] read-write CFA_CTRL Color Filter Array Control Register 0x70 0x20 read-write ENABLE Color Filter Array Interpolation Enable [0:0] read-write CLKCFG Clock Configuration Register 0x24 0x20 read-write ICDIV ISP Clock Divider [7:0] read-write 0 255 ICSEL ISP Clock Selection [8:8] read-write MCDIV Master Clock Divider [23:16] read-write 0 255 MCSEL Master Clock Reference Clock Selection [25:24] read-write 0 3 CLKDIS Clock Disable Register 0x1C 0x20 write-only ICDIS ISP Clock Disable [0:0] read-write MCDIS Master Clock Disable [1:1] read-write ICSWRST ISP Clock Software Reset [8:8] read-write MCSWRST Master Clock Software Reset [9:9] read-write CLKEN Clock Enable Register 0x18 0x20 write-only ICEN ISP Clock Enable [0:0] read-write MCEN Master Clock Enable [1:1] read-write CLKSR Clock Status Register 0x20 0x20 read-only ICSR ISP Clock Status Register [0:0] read-write MCSR Master Clock Status Register [1:1] read-write SIP Synchronization In Progress [31:31] read-write CSC_CBB_OCB Color Space Conversion CBB OCB Register 0x3A8 0x20 read-write CBBGAIN Blue Gain for Blue Chrominance (signed 12 bits 1:3:8) [11:0] read-write 0 4095 CBOFST Blue Chrominance Offset (signed 11 bits 1:10:0) [26:16] read-write 0 2047 CSC_CBR_CBG Color Space Conversion CBR CBG Register 0x3A4 0x20 read-write CBRGAIN Red Gain for Blue Chrominance (signed 12 bits, 1:3:8) [11:0] read-write 0 4095 CBGGAIN Green Gain for Blue Chrominance (signed 12 bits 1:3:8) [27:16] read-write 0 4095 CSC_CRB_OCR Color Space Conversion CRB OCR Register 0x3B0 0x20 read-write CRBGAIN Blue Gain for Red Chrominance (signed 12 bits 1:3:8) [11:0] read-write 0 4095 CROFST Red Chrominance Offset (signed 11 bits 1:10:0) [26:16] read-write 0 2047 CSC_CRR_CRG Color Space Conversion CRR CRG Register 0x3AC 0x20 read-write CRRGAIN Red Gain for Red Chrominance (signed 12 bits 1:3:8) [11:0] read-write 0 4095 CRGGAIN Green Gain for Red Chrominance (signed 12 bits 1:3:8) [27:16] read-write 0 4095 CSC_CTRL Color Space Conversion Control Register 0x398 0x20 read-write ENABLE RGB to YCbCr Color Space Conversion Enable [0:0] read-write CSC_YB_OY Color Space Conversion YB, OY Register 0x3A0 0x20 read-write YBGAIN Blue Gain for Luminance Component (12 bits signed 1:3:8) [11:0] read-write 0 4095 YOFST Luminance Offset (11 bits signed 1:10:0) [26:16] read-write 0 2047 CSC_YR_YG Color Space Conversion YR, YG Register 0x39C 0x20 read-write YRGAIN Reg Gain for Luminance (signed 12 bits 1:3:8) [11:0] read-write 0 4095 YGGAIN Green Gain for Luminance (signed 12 bits 1:3:8) [27:16] read-write 0 4095 CTRLDIS Control Disable Register 0x4 0x20 write-only DISABLE Capture Disable [0:0] read-write SWRST Software Reset [8:8] read-write CTRLEN Control Enable Register 0x0 0x20 write-only CAPTURE Capture Input Stream Command [0:0] read-write UPPRO Update Profile [1:1] read-write HISREQ Histogram Request [2:2] read-write HISCLR Histogram Clear [3:3] read-write CTRLSR Control Status Register 0x8 0x20 read-only CAPTURE Capture pending [0:0] read-write UPPRO Profile Update Pending [1:1] read-write HISREQ Histogram Request Pending [2:2] read-write FIELD Field Status (only relevant when the video stream is interlaced) [4:4] read-write SIP Synchronization In Progress [31:31] read-write DCFG DMA Configuration Register 0x3E0 0x20 read-write IMODE DMA Input Mode Selection [2:0] read-write true PACKED8 8 bits, single channel packed 0 PACKED16 16 bits, single channel packed 1 PACKED32 32 bits, single channel packed 2 YC422SP 32 bits, dual channel 3 YC422P 32 bits, triple channel 4 YC420SP 32 bits, dual channel 5 YC420P 32 bits, triple channel 6 YMBSIZE DMA Memory Burst Size Y channel [5:4] read-write true SINGLE DMA single access 0 BEATS4 4-beat burst access 1 BEATS8 8-beat burst access 2 BEATS16 16-beat burst access 3 CMBSIZE DMA Memory Burst Size C channel [9:8] read-write true SINGLE DMA single access 0 BEATS4 4-beat burst access 1 BEATS8 8-beat burst access 2 BEATS16 16-beat burst access 3 DCTRL DMA Control Register 0x3E4 0x20 read-write DE Descriptor Enable [0:0] read-write DVIEW Descriptor View [2:1] read-write true PACKED Address {0} Stride {0} are updated 0 SEMIPLANAR Address {0,1} Stride {0,1} are updated 1 PLANAR Address {0,1,2} Stride {0,1,2} are updated 2 IE Interrupt Enable [4:4] read-write WB Write Back Operation Enable [5:5] read-write FIELD Value of Captured Frame Field Signal(1)(2) [6:6] read-write DONE Descriptor Processing Status(2) [7:7] read-write DNDA DMA Descriptor Address Register 0x3E8 0x20 read-write NDA Next Descriptor Address Register [31:2] read-write 0 1073741823 GAM_BENTRY Gamma Correction Blue Entry 0x98 0x20 read-write BSLOPE Blue Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6) [9:0] read-write 0 1023 BCONSTANT Blue Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0) [25:16] read-write 0 1023 GAM_CTRL Gamma Correction Control Register 0x94 0x20 read-write ENABLE Gamma Correction Enable [0:0] read-write BENABLE Gamma Correction Enable for B Channel [1:1] read-write GENABLE Gamma Correction Enable for G Channel [2:2] read-write RENABLE Gamma Correction Enable for R Channel [3:3] read-write GAM_GENTRY Gamma Correction Green Entry 0x198 0x20 read-write GSLOPE Green Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6) [9:0] read-write 0 1023 GCONSTANT Green Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0) [25:16] read-write 0 1023 GAM_RENTRY Gamma Correction Red Entry 0x298 0x20 read-write RSLOPE Red Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6) [9:0] read-write 0 1023 RCONSTANT Red Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0) [25:16] read-write 0 1023 HIS_CFG Histogram Configuration Register 0x3D8 0x20 read-write MODE Histogram Operating Mode [2:0] read-write true Gr Gr sampling 0 R R sampling 1 Gb Gb sampling 2 B B sampling 3 Y Luminance-only mode 4 RAW Raw sampling 5 YCCIR656 Luminance only with CCIR656 10-bit or 8-bit mode 6 BAYSEL Bayer Color Component Selection [5:4] read-write true GRGR Starting row configuration is G R G R (red row) 0 RGRG Starting row configuration is R G R G (red row) 1 GBGB Starting row configuration is G B G B (blue row 2 BGBG Starting row configuration is B G B G (blue row) 3 RAR Histogram Reset After Read [8:8] read-write HIS_CTRL Histogram Control Register 0x3D4 0x20 read-write ENABLE Histogram Sub Module Enable [0:0] read-write HIS_ENTRY Histogram Entry 0x410 0x20 read-only COUNT Entry Counter [19:0] read-write 0 1048575 INTDIS Interrupt Disable Register 0x2C 0x20 write-only VD Vertical Synchronization Detection Interrupt Disable [0:0] read-write HD Horizontal Synchronization Detection Interrupt Disable [1:1] read-write SWRST Software Reset Completed Interrupt Disable [4:4] read-write DIS Disable Completed Interrupt Disable [5:5] read-write DDONE DMA Done Interrupt Disable [8:8] read-write LDONE DMA List Done Interrupt Disable [9:9] read-write HISDONE Histogram Completed Interrupt Disable [12:12] read-write HISCLR Histogram Clear Interrupt Disable [13:13] read-write WERR Write Channel Error Interrupt Disable [16:16] read-write RERR Read Channel Error Interrupt Disable [20:20] read-write VFPOV Vertical Front Porch Overflow Interrupt Disable [24:24] read-write DAOV Data Overflow Interrupt Disable [25:25] read-write VDTO Vertical Synchronization Timeout Interrupt Disable [26:26] read-write HDTO Horizontal Synchronization Timeout Interrupt Disable [27:27] read-write CCIRERR CCIR Decoder Error Interrupt Disable [28:28] read-write INTEN Interrupt Enable Register 0x28 0x20 write-only VD Vertical Synchronization Detection Interrupt Enable [0:0] read-write HD Horizontal Synchronization Detection Interrupt Enable [1:1] read-write SWRST Software Reset Completed Interrupt Enable [4:4] read-write DIS Disable Completed Interrupt Enable [5:5] read-write DDONE DMA Done Interrupt Enable [8:8] read-write LDONE DMA List Done Interrupt Enable [9:9] read-write HISDONE Histogram Completed Interrupt Enable [12:12] read-write HISCLR Histogram Clear Interrupt Enable [13:13] read-write WERR Write Channel Error Interrupt Enable [16:16] read-write RERR Read Channel Error Interrupt Enable [20:20] read-write VFPOV Vertical Front Porch Overflow Interrupt Enable [24:24] read-write DAOV Data Overflow Interrupt Enable [25:25] read-write VDTO Vertical Synchronization Timeout Interrupt Enable [26:26] read-write HDTO Horizontal Synchronization Timeout Interrupt Enable [27:27] read-write CCIRERR CCIR Decoder Error Interrupt Enable [28:28] read-write INTMASK Interrupt Mask Register 0x30 0x20 read-only VD Vertical Synchronization Detection Interrupt Mask [0:0] read-write HD Horizontal Synchronization Detection Interrupt Mask [1:1] read-write SWRST Software Reset Completed Interrupt Mask [4:4] read-write DIS Disable Completed Interrupt Mask [5:5] read-write DDONE DMA Done Interrupt Mask [8:8] read-write LDONE DMA List Done Interrupt Mask [9:9] read-write HISDONE Histogram Completed Interrupt Mask [12:12] read-write HISCLR Histogram Clear Interrupt Mask [13:13] read-write WERR Write Channel Error Interrupt Mask [16:16] read-write RERR Read Channel Error Interrupt Mask [20:20] read-write VFPOV Vertical Front Porch Overflow Interrupt Mask [24:24] read-write DAOV Data Overflow Interrupt Mask [25:25] read-write VDTO Vertical Synchronization Timeout Interrupt Mask [26:26] read-write HDTO Horizontal Synchronization Timeout Interrupt Mask [27:27] read-write CCIRERR CCIR Decoder Error Interrupt Mask [28:28] read-write INTSR Interrupt Status Register 0x34 0x20 read-only VD Vertical Synchronization Detected Interrupt [0:0] read-write HD Horizontal Synchronization Detected Interrupt [1:1] read-write SWRST Software Reset Completed Interrupt [4:4] read-write DIS Disable Completed Interrupt [5:5] read-write DDONE DMA Done Interrupt [8:8] read-write LDONE DMA List Done Interrupt [9:9] read-write HISDONE Histogram Completed Interrupt [12:12] read-write HISCLR Histogram Clear Interrupt [13:13] read-write WERR Write Channel Error Interrupt [16:16] read-write WERRID Write Channel Error Identifier [18:17] read-write true CH0 An error occurred for Channel 0 (RAW/RGB/Y) 0 CH1 An error occurred for Channel 1 (CbCr/Cb) 1 CH2 An error occurred for Channel 2 (Cr) 2 WB Write back channel error 3 RERR Read Channel Error Interrupt [20:20] read-write VFPOV Vertical Front Porch Overflow Interrupt [24:24] read-write DAOV Data Overflow Interrupt [25:25] read-write VDTO Vertical Synchronization Timeout Interrupt [26:26] read-write HDTO Horizontal Synchronization Timeout Interrupt [27:27] read-write CCIRERR CCIR Decoder Error Interrupt [28:28] read-write PFE_CFG0 Parallel Front End Configuration 0 Register 0xC 0x20 read-write HPOL Horizontal Synchronization Polarity [0:0] read-write VPOL Vertical Synchronization Polarity [1:1] read-write PPOL Pixel Clock Polarity [2:2] read-write FPOL Field Polarity [3:3] read-write MODE Parallel Front End Mode [6:4] read-write true PROGRESSIVE Video source is progressive. 0 DF_TOP Video source is interlaced, two fields are captured starting with top field. 1 DF_BOTTOM Video source is interlaced, two fields are captured starting with bottom field. 2 DF_IMMEDIATE Video source is interlaced, two fields are captured immediately. 3 SF_TOP Video source is interlaced, one field is captured starting with the top field. 4 SF_BOTTOM Video source is interlaced, one field is captured starting with the bottom field. 5 SF_IMMEDIATE Video source is interlaced, one field is captured starting immediately. 6 CONT Continuous Acquisition [7:7] read-write GATED Gated input clock [8:8] read-write CCIR656 CCIR656 input mode [9:9] read-write CCIR_CRC CCIR656 CRC Decoder [10:10] read-write CCIR10_8N CCIR 10 bits or 8 bits [11:11] read-write COLEN Column Cropping Enable [12:12] read-write ROWEN Row Cropping Enable [13:13] read-write SKIPCNT Frame Skipping Counter [23:16] read-write 0 255 CCIR_REP CCIR Replication [27:27] read-write BPS Bits Per Sample [30:28] read-write true TWELVE 12-bit input 0 ELEVEN 11-bit input 1 TEN 10-bit input 2 NINE 9-bit input 3 EIGHT 8-bit input 4 REP Up Multiply with Replication [31:31] read-write PFE_CFG1 Parallel Front End Configuration 1 Register 0x10 0x20 read-write COLMIN Column Minimum Limit [15:0] read-write 0 65535 COLMAX Column Maximum Limit [31:16] read-write 0 65535 PFE_CFG2 Parallel Front End Configuration 2 Register 0x14 0x20 read-write ROWMIN Row Minimum Limit [15:0] read-write 0 65535 ROWMAX Row Maximum Limit [31:16] read-write 0 65535 RLP_CFG Rounding, Limiting and Packing Configuration Register 0x3D0 0x20 read-write MODE Rounding, Limiting and Packing Mode [3:0] read-write true DAT8 8-bit data 0 DAT9 9-bit data 1 DAT10 10-bit data 2 DAT11 11-bit data 3 DAT12 12-bit data 4 DATY8 8-bit luminance only 5 DATY10 10-bit luminance only 6 ARGB444 12-bit RGB+4-bit Alpha (MSB) 7 ARGB555 15-bit RGB+1-bit Alpha (MSB) 8 RGB565 16-bit RGB 9 ARGB32 24-bits RGB mode+8-bit Alpha 10 YYCC YCbCr mode (full range, [0-255]) 11 YYCC_LIMITED YCbCr mode (limited range) 12 ALPHA Alpha Value for Alpha-enabled RGB Mode [15:8] read-write 0 255 SUB420_CTRL Subsampling 4:2:2 to 4:2:0 Control Register 0x3CC 0x20 read-write ENABLE 4:2:2 to 4:2:0 Vertical Subsampling Filter Enable (Center Aligned) [0:0] read-write FILTER Interlaced or Progressive Chrominance Filter [4:4] read-write SUB422_CFG Subsampling 4:4:4 to 4:2:2 Configuration Register 0x3C8 0x20 read-write CCIR CCIR656 Input Stream [0:0] read-write CCIRMODE CCIR656 Byte Ordering [2:1] read-write true CBY Byte ordering Cb0, Y0, Cr0, Y1 0 CRY Byte ordering Cr0, Y0, Cb0, Y1 1 YCB Byte ordering Y0, Cb0, Y1, Cr0 2 YCR Byte ordering Y0, Cr0, Y1, Cb0 3 FILTER Low Pass Filter Selection [5:4] read-write true FILT0CO Cosited, {1} 0 FILT1CE Centered {1, 1} 1 FILT2CO Cosited {1,2,1} 2 FILT3CE Centered {1, 3, 3, 1} 3 SUB422_CTRL Subsampling 4:4:4 to 4:2:2 Control Register 0x3C4 0x20 read-write ENABLE 4:4:4 to 4:2:2 Chrominance Horizontal Subsampling Filter Enable [0:0] read-write WB_CFG White Balance Configuration Register 0x5C 0x20 read-write BAYCFG White Balance Bayer Configuration (Pixel Color Pattern) [1:0] read-write true GRGR Starting Row configuration is G R G R (Red Row) 0 RGRG Starting Row configuration is R G R G (Red Row) 1 GBGB Starting Row configuration is G B G B (Blue Row) 2 BGBG Starting Row configuration is B G B G (Blue Row) 3 WB_CTRL White Balance Control Register 0x58 0x20 read-write ENABLE White Balance Enable [0:0] read-write WB_G_BGB White Balance Gain for B, GB Register 0x6C 0x20 read-write BGAIN Blue Component Gain (unsigned 13 bits, 0:4:9) [12:0] read-write 0 8191 GBGAIN Green Component (Blue row) Gain (unsigned 13 bits, 0:4:9) [28:16] read-write 0 8191 WB_G_RGR White Balance Gain for R, GR Register 0x68 0x20 read-write RGAIN Red Component Gain (unsigned 13 bits, 0:4:9) [12:0] read-write 0 8191 GRGAIN Green Component (Red row) Gain (unsigned 13 bits, 0:4:9) [28:16] read-write 0 8191 WB_O_BGB White Balance Offset for B, GB Register 0x64 0x20 read-write BOFST Offset Blue Component (signed 13 bits, 1:12:0) [12:0] read-write 0 8191 GBOFST Offset Green Component for Blue Row (signed 13 bits, 1:12:0) [28:16] read-write 0 8191 WB_O_RGR White Balance Offset for R, GR Register 0x60 0x20 read-write ROFST Offset Red Component (signed 13 bits 1:12:0) [12:0] read-write 0 8191 GROFST Offset Green Component for Red Row (signed 13 bits 1:12:0) [28:16] read-write 0 8191 L2CC L2 Cache Controller 0x00A00000 0x0 0x8 registers 0x100 0x10 registers 0x200 0x24 registers 0x730 0x4 registers 0x770 0x4 registers 0x77C 0x4 registers 0x7B0 0x4 registers 0x7B8 0x8 registers 0x7F0 0x4 registers 0x7F8 0x8 registers 0x900 0x8 registers 0xF40 0x4 registers 0xF60 0x4 registers 0xF80 0x4 registers ACR Auxiliary Control Register 0x104 0x20 read-write HPSO High Priority for SO and Dev Reads Enable [10:10] read-write SBDLE Store Buffer Device Limitation Enable [11:11] read-write EXCC Exclusive Cache Configuration [12:12] read-write SAIE Shared Attribute Invalidate Enable [13:13] read-write ASS Associativity [16:16] read-write WAYSIZE Way Size [19:17] read-write true _16KB_WAY 16-Kbyte way set associative 1 EMBEN Event Monitor Bus Enable [20:20] read-write PEN Parity Enable [21:21] read-write SAOEN Shared Attribute Override Enable [22:22] read-write FWA Force Write Allocate [24:23] read-write 0 3 CRPOL Cache Replacement Policy [25:25] read-write NSLEN Non-Secure Lockdown Enable [26:26] read-write NSIAC Non-Secure Interrupt Access Control [27:27] read-write DPEN Data Prefetch Enable [28:28] read-write IPEN Instruction Prefetch Enable [29:29] read-write CIIR Clean Invalidate Index Register 0x7F8 0x20 read-write C Cache Synchronization Status [0:0] read-write IDX Index Number [13:5] read-write 0 511 WAY Way Number [30:28] read-write 0 7 CIPALR Clean Invalidate Physical Address Line Register 0x7F0 0x20 read-write C Cache Synchronization Status [0:0] read-write IDX Index Number [13:5] read-write 0 511 TAG Tag Number [31:14] read-write 0 262143 CIR Clean Index Register 0x7B8 0x20 read-write C Cache Synchronization Status [0:0] read-write IDX Index number [13:5] read-write 0 511 WAY Way number [30:28] read-write 0 7 CIWR Clean Invalidate Way Register 0x7FC 0x20 read-write WAY0 Clean Invalidate Way Number 0 [0:0] read-write WAY1 Clean Invalidate Way Number 1 [1:1] read-write WAY2 Clean Invalidate Way Number 2 [2:2] read-write WAY3 Clean Invalidate Way Number 3 [3:3] read-write WAY4 Clean Invalidate Way Number 4 [4:4] read-write WAY5 Clean Invalidate Way Number 5 [5:5] read-write WAY6 Clean Invalidate Way Number 6 [6:6] read-write WAY7 Clean Invalidate Way Number 7 [7:7] read-write CPALR Clean Physical Address Line Register 0x7B0 0x20 read-write C Cache Synchronization Status [0:0] read-write IDX Index number [13:5] read-write 0 511 TAG Tag number [31:14] read-write 0 262143 CR Control Register 0x100 0x20 read-write L2CEN L2 Cache Enable [0:0] read-write CSR Cache Synchronization Register 0x730 0x20 read-write C Cache Synchronization Status [0:0] read-write CWR Clean Way Register 0x7BC 0x20 read-write WAY0 Clean Way Number 0 [0:0] read-write WAY1 Clean Way Number 1 [1:1] read-write WAY2 Clean Way Number 2 [2:2] read-write WAY3 Clean Way Number 3 [3:3] read-write WAY4 Clean Way Number 4 [4:4] read-write WAY5 Clean Way Number 5 [5:5] read-write WAY6 Clean Way Number 6 [6:6] read-write WAY7 Clean Way Number 7 [7:7] read-write DCR Debug Control Register 0xF40 0x20 read-write DCL Disable Cache Linefill [0:0] read-write DWB Disable Write-back, Force Write-through [1:1] read-write SPNIDEN SPNIDEN Value [2:2] read-write DLKR Data Lockdown Register 0x900 0x20 read-write DLK0 Data Lockdown in Way Number 0 [0:0] read-write DLK1 Data Lockdown in Way Number 1 [1:1] read-write DLK2 Data Lockdown in Way Number 2 [2:2] read-write DLK3 Data Lockdown in Way Number 3 [3:3] read-write DLK4 Data Lockdown in Way Number 4 [4:4] read-write DLK5 Data Lockdown in Way Number 5 [5:5] read-write DLK6 Data Lockdown in Way Number 6 [6:6] read-write DLK7 Data Lockdown in Way Number 7 [7:7] read-write DRCR Data RAM Control Register 0x10C 0x20 read-write DSETLAT Setup Latency [2:0] read-write 0 7 DRDLAT Read Access Latency [6:4] read-write 0 7 DWRLAT Write Access Latency [10:8] read-write 0 7 ECFGR0 Event Counter 0 Configuration Register 0x208 0x20 read-write EIGEN Event Counter Interrupt Generation [1:0] read-write true INT_DIS Disables (default) 0 INT_EN_INCR Enables with Increment condition 1 INT_EN_OVER Enables with Overflow condition 2 INT_GEN_DIS Disables Interrupt generation 3 ESRC Event Counter Source [5:2] read-write true CNT_DIS Counter Disabled 0 SRC_CO Source is CO 1 SRC_DRHIT Source is DRHIT 2 SRC_DRREQ Source is DRREQ 3 SRC_DWHIT Source is DWHIT 4 SRC_DWREQ Source is DWREQ 5 SRC_DWTREQ Source is DWTREQ 6 SRC_IRHIT Source is IRHIT 7 SRC_IRREQ Source is IRREQ 8 SRC_WA Source is WA 9 SRC_IPFALLOC Source is IPFALLOC 10 SRC_EPFHIT Source is EPFHIT 11 SRC_EPFALLOC Source is EPFALLOC 12 SRC_SRRCVD Source is SRRCVD 13 SRC_SRCONF Source is SRCONF 14 SRC_EPFRCVD Source is EPFRCVD 15 ECFGR1 Event Counter 1 Configuration Register 0x204 0x20 read-write EIGEN Event Counter Interrupt Generation [1:0] read-write true INT_DIS Disables (default) 0 INT_EN_INCR Enables with Increment condition 1 INT_EN_OVER Enables with Overflow condition 2 INT_GEN_DIS Disables Interrupt generation 3 ESRC Event Counter Source [5:2] read-write true CNT_DIS Counter Disabled 0 SRC_CO Source is CO 1 SRC_DRHIT Source is DRHIT 2 SRC_DRREQ Source is DRREQ 3 SRC_DWHIT Source is DWHIT 4 SRC_DWREQ Source is DWREQ 5 SRC_DWTREQ Source is DWTREQ 6 SRC_IRHIT Source is IRHIT 7 SRC_IRREQ Source is IRREQ 8 SRC_WA Source is WA 9 SRC_IPFALLOC Source is IPFALLOC 10 SRC_EPFHIT Source is EPFHIT 11 SRC_EPFALLOC Source is EPFALLOC 12 SRC_SRRCVD Source is SRRCVD 13 SRC_SRCONF Source is SRCONF 14 SRC_EPFRCVD Source is EPFRCVD 15 ECR Event Counter Control Register 0x200 0x20 read-write EVCEN Event Counter Enable [0:0] read-write EVC0RST Event Counter 0 Reset [1:1] read-write EVC1RST Event Counter 1 Reset [2:2] read-write EVR0 Event Counter 0 Value Register 0x210 0x20 read-write VALUE Event Counter Value [31:0] read-write 0 4294967295 EVR1 Event Counter 1 Value Register 0x20C 0x20 read-write VALUE Event Counter Value [31:0] read-write 0 4294967295 ICR Interrupt Clear Register 0x220 0x20 read-write ECNTR Event Counter 1/0 Overflow Increment [0:0] read-write PARRT Parity Error on L2 Tag RAM, Read [1:1] read-write PARRD Parity Error on L2 Data RAM, Read [2:2] read-write ERRWT Error on L2 Tag RAM, Write [3:3] read-write ERRWD Error on L2 Data RAM, Write [4:4] read-write ERRRT Error on L2 Tag RAM, Read [5:5] read-write ERRRD Error on L2 Data RAM, Read [6:6] read-write SLVERR SLVERR from L3 memory [7:7] read-write DECERR DECERR from L3 memory [8:8] read-write IDR Cache ID Register 0x0 0x20 read-only ID Cache Controller ID [31:0] read-write 0 4294967295 ILKR Instruction Lockdown Register 0x904 0x20 read-write ILK0 Instruction Lockdown in Way Number 0 [0:0] read-write ILK1 Instruction Lockdown in Way Number 1 [1:1] read-write ILK2 Instruction Lockdown in Way Number 2 [2:2] read-write ILK3 Instruction Lockdown in Way Number 3 [3:3] read-write ILK4 Instruction Lockdown in Way Number 4 [4:4] read-write ILK5 Instruction Lockdown in Way Number 5 [5:5] read-write ILK6 Instruction Lockdown in Way Number 6 [6:6] read-write ILK7 Instruction Lockdown in Way Number 7 [7:7] read-write IMR Interrupt Mask Register 0x214 0x20 read-write ECNTR Event Counter 1/0 Overflow Increment [0:0] read-write PARRT Parity Error on L2 Tag RAM, Read [1:1] read-write PARRD Parity Error on L2 Data RAM, Read [2:2] read-write ERRWT Error on L2 Tag RAM, Write [3:3] read-write ERRWD Error on L2 Data RAM, Write [4:4] read-write ERRRT Error on L2 Tag RAM, Read [5:5] read-write ERRRD Error on L2 Data RAM, Read [6:6] read-write SLVERR SLVERR from L3 Memory [7:7] read-write DECERR DECERR from L3 Memory [8:8] read-write IPALR Invalidate Physical Address Line Register 0x770 0x20 read-write C Cache Synchronization Status [0:0] read-write IDX Index Number [13:5] read-write 0 511 TAG Tag Number [31:14] read-write 0 262143 IWR Invalidate Way Register 0x77C 0x20 read-write WAY0 Invalidate Way Number 0 [0:0] read-write WAY1 Invalidate Way Number 1 [1:1] read-write WAY2 Invalidate Way Number 2 [2:2] read-write WAY3 Invalidate Way Number 3 [3:3] read-write WAY4 Invalidate Way Number 4 [4:4] read-write WAY5 Invalidate Way Number 5 [5:5] read-write WAY6 Invalidate Way Number 6 [6:6] read-write WAY7 Invalidate Way Number 7 [7:7] read-write MISR Masked Interrupt Status Register 0x218 0x20 read-only ECNTR Event Counter 1/0 Overflow Increment [0:0] read-write PARRT Parity Error on L2 Tag RAM, Read [1:1] read-write PARRD Parity Error on L2 Data RAM, Read [2:2] read-write ERRWT Error on L2 Tag RAM, Write [3:3] read-write ERRWD Error on L2 Data RAM, Write [4:4] read-write ERRRT Error on L2 Tag RAM, Read [5:5] read-write ERRRD Error on L2 Data RAM, Read [6:6] read-write SLVERR SLVERR from L3 memory [7:7] read-write DECERR DECERR from L3 memory [8:8] read-write PCR Prefetch Control Register 0xF60 0x20 read-write OFFSET Prefetch Offset [4:0] read-write 0 31 NSIDEN Not Same ID on Exclusive Sequence Enable [21:21] read-write IDLEN INCR Double Linefill Enable [23:23] read-write PDEN Prefetch Drop Enable [24:24] read-write DLFWRDIS Double Linefill on WRAP Read Disable [27:27] read-write DATPEN Data Prefetch Enable [28:28] read-write INSPEN Instruction Prefetch Enable [29:29] read-write DLEN Double Linefill Enable [30:30] read-write POWCR Power Control Register 0xF80 0x20 read-write STBYEN Standby Mode Enable [0:0] read-write DCKGATEN Dynamic Clock Gating Enable [1:1] read-write RISR Raw Interrupt Status Register 0x21C 0x20 read-only ECNTR Event Counter 1/0 Overflow Increment [0:0] read-write PARRT Parity Error on L2 Tag RAM, Read [1:1] read-write PARRD Parity Error on L2 Data RAM, Read [2:2] read-write ERRWT Error on L2 Tag RAM, Write [3:3] read-write ERRWD Error on L2 Data RAM, Write [4:4] read-write ERRRT Error on L2 Tag RAM, Read [5:5] read-write ERRRD Error on L2 Data RAM, Read [6:6] read-write SLVERR SLVERR from L3 memory [7:7] read-write DECERR DECERR from L3 memory [8:8] read-write TRCR Tag RAM Control Register 0x108 0x20 read-write TSETLAT Setup Latency [2:0] read-write 0 7 TRDLAT Read Access Latency [6:4] read-write 0 7 TWRLAT Write Access Latency [10:8] read-write 0 7 TYPR Cache Type Register 0x4 0x20 read-only IL2ASS Instruction L2 Cache Associativity [6:6] read-write IL2WSIZE Instruction L2 Cache Way Size [10:8] read-write 0 7 DL2ASS Data L2 Cache Associativity [18:18] read-write DL2WSIZE Data L2 Cache Way Size [22:20] read-write 0 7 LCDC LCD Controller 0xF0000000 0x0 0x1C registers 0x20 0x68 registers 0x140 0x54 registers 0x240 0x54 registers 0x340 0xF4 registers 0x540 0x44 registers 0x600 0x4 registers 0xA00 0x4 registers 0xE00 0x4 registers 0x1200 0x4 registers ATTR LCD Controller Attribute Register 0x3C 0x20 write-only BASE Base Layer Update Attribute [0:0] read-write OVR1 Overlay 1 Update Attribute [1:1] read-write OVR2 Overlay 2 Update Attribute [2:2] read-write HEO High-End Overlay Update Attribute [3:3] read-write PP Post-Processing Update Attribute [5:5] read-write BASEA2Q Base Layer Update Add To Queue [8:8] read-write OVR1A2Q Overlay 1 Update Add To Queue [9:9] read-write OVR2A2Q Overlay 2 Update Add to Queue [10:10] read-write HEOA2Q High-End Overlay Update Add To Queue [11:11] read-write PPA2Q Post-Processing Update Add To Queue [13:13] read-write BASEADDR Base DMA Address Register 0x60 0x20 read-write ADDR DMA Transfer Start Address [31:0] read-write 0 4294967295 BASECFG0 Base Layer Configuration Register 0 0x6C 0x20 read-write SIF Source Interface [0:0] read-write BLEN AHB Burst Length [5:4] read-write true AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 0 AHB_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 DLBO Defined Length Burst Only For Channel Bus Transaction [8:8] read-write BASECFG1 Base Layer Configuration Register 1 0x70 0x20 read-write CLUTEN Color Lookup Table Mode Enable [0:0] read-write RGBMODE RGB Mode Input Selection [7:4] read-write true _12BPP_RGB_444 12 bpp RGB 444 0 _16BPP_ARGB_4444 16 bpp ARGB 4444 1 _16BPP_RGBA_4444 16 bpp RGBA 4444 2 _16BPP_RGB_565 16 bpp RGB 565 3 _16BPP_TRGB_1555 16 bpp TRGB 1555 4 _18BPP_RGB_666 18 bpp RGB 666 5 _18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 6 _19BPP_TRGB_1666 19 bpp TRGB 1666 7 _19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 8 _24BPP_RGB_888 24 bpp RGB 888 9 _24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 10 _25BPP_TRGB_1888 25 bpp TRGB 1888 11 _32BPP_ARGB_8888 32 bpp ARGB 8888 12 _32BPP_RGBA_8888 32 bpp RGBA 8888 13 CLUTMODE Color Lookup Table Mode Input Selection [9:8] read-write true CLUT_1BPP Color Lookup Table mode set to 1 bit per pixel 0 CLUT_2BPP Color Lookup Table mode set to 2 bits per pixel 1 CLUT_4BPP Color Lookup Table mode set to 4 bits per pixel 2 CLUT_8BPP Color Lookup Table mode set to 8 bits per pixel 3 BASECFG2 Base Layer Configuration Register 2 0x74 0x20 read-write XSTRIDE Horizontal Stride [31:0] read-write 0 4294967295 BASECFG3 Base Layer Configuration Register 3 0x78 0x20 read-write BDEF Blue Default [7:0] read-write 0 255 GDEF Green Default [15:8] read-write 0 255 RDEF Red Default [23:16] read-write 0 255 BASECFG4 Base Layer Configuration Register 4 0x7C 0x20 read-write DMA Use DMA Data Path [8:8] read-write REP Use Replication logic to expand RGB color to 24 bits [9:9] read-write DISCEN Discard Area Enable [11:11] read-write BASECFG5 Base Layer Configuration Register 5 0x80 0x20 read-write DISCXPOS Discard Area Horizontal Coordinate [10:0] read-write 0 2047 DISCYPOS Discard Area Vertical Coordinate [26:16] read-write 0 2047 BASECFG6 Base Layer Configuration Register 6 0x84 0x20 read-write DISCXSIZE Discard Area Horizontal Size [10:0] read-write 0 2047 DISCYSIZE Discard Area Vertical Size [26:16] read-write 0 2047 BASECHDR Base Layer Channel Disable Register 0x44 0x20 write-only CHDIS Channel Disable [0:0] read-write CHRST Channel Reset [8:8] read-write BASECHER Base Layer Channel Enable Register 0x40 0x20 write-only CHEN Channel Enable [0:0] read-write UPDATEEN Update Overlay Attributes Enable [1:1] read-write A2QEN Add To Queue Enable [2:2] read-write BASECHSR Base Layer Channel Status Register 0x48 0x20 read-only CHSR Channel Status [0:0] read-write UPDATESR Update Overlay Attributes In Progress Status [1:1] read-write A2QSR Add To Queue Status [2:2] read-write BASECLUT Base CLUT Register 0x600 0x20 read-write BCLUT Blue Color Entry [7:0] read-write 0 255 GCLUT Green Color Entry [15:8] read-write 0 255 RCLUT Red Color Entry [23:16] read-write 0 255 BASECTRL Base DMA Control Register 0x64 0x20 read-write DFETCH Transfer Descriptor Fetch Enable [0:0] read-write LFETCH Lookup Table Fetch Enable [1:1] read-write DMAIEN End of DMA Transfer Interrupt Enable [2:2] read-write DSCRIEN Descriptor Loaded Interrupt Enable [3:3] read-write ADDIEN Add Head Descriptor to Queue Interrupt Enable [4:4] read-write DONEIEN End of List Interrupt Enable [5:5] read-write BASEHEAD Base DMA Head Register 0x5C 0x20 read-write HEAD DMA Head Pointer [31:2] read-write 0 1073741823 BASEIDR Base Layer Interrupt Disabled Register 0x50 0x20 write-only DMA End of DMA Transfer Interrupt Disable [2:2] read-write DSCR Descriptor Loaded Interrupt Disable [3:3] read-write ADD Head Descriptor Loaded Interrupt Disable [4:4] read-write DONE End of List Interrupt Disable [5:5] read-write OVR Overflow Interrupt Disable [6:6] read-write BASEIER Base Layer Interrupt Enable Register 0x4C 0x20 write-only DMA End of DMA Transfer Interrupt Enable [2:2] read-write DSCR Descriptor Loaded Interrupt Enable [3:3] read-write ADD Head Descriptor Loaded Interrupt Enable [4:4] read-write DONE End of List Interrupt Enable [5:5] read-write OVR Overflow Interrupt Enable [6:6] read-write BASEIMR Base Layer Interrupt Mask Register 0x54 0x20 read-only DMA End of DMA Transfer Interrupt Mask [2:2] read-write DSCR Descriptor Loaded Interrupt Mask [3:3] read-write ADD Head Descriptor Loaded Interrupt Mask [4:4] read-write DONE End of List Interrupt Mask [5:5] read-write OVR Overflow Interrupt Mask [6:6] read-write BASEISR Base Layer Interrupt Status Register 0x58 0x20 read-only DMA End of DMA Transfer [2:2] read-write DSCR DMA Descriptor Loaded [3:3] read-write ADD Head Descriptor Loaded [4:4] read-write DONE End of List Detected [5:5] read-write OVR Overflow Detected [6:6] read-write BASENEXT Base DMA Next Register 0x68 0x20 read-write NEXT DMA Descriptor Next Address [31:0] read-write 0 4294967295 HEOADDR High-End Overlay DMA Address Register 0x360 0x20 read-write ADDR DMA Transfer Start Address [31:0] read-write 0 4294967295 HEOCFG0 High-End Overlay Configuration Register 0 0x38C 0x20 read-write SIF Source Interface [0:0] read-write BLEN AHB Burst Length [5:4] read-write true AHB_BLEN_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 0 AHB_BLEN_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_BLEN_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_BLEN_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 BLENUV AHB Burst Length for U-V Channel [7:6] read-write true AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 0 AHB_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 DLBO Defined Length Burst Only For Channel Bus Transaction [8:8] read-write ROTDIS Hardware Rotation Optimization Disable [12:12] read-write LOCKDIS Hardware Rotation Lock Disable [13:13] read-write HEOCFG1 High-End Overlay Configuration Register 1 0x390 0x20 read-write CLUTEN Color Lookup Table Mode Enable [0:0] read-write YUVEN YUV Color Space Enable [1:1] read-write RGBMODE RGB Mode Input Selection [7:4] read-write true _12BPP_RGB_444 12 bpp RGB 444 0 _16BPP_ARGB_4444 16 bpp ARGB 4444 1 _16BPP_RGBA_4444 16 bpp RGBA 4444 2 _16BPP_RGB_565 16 bpp RGB 565 3 _16BPP_TRGB_1555 16 bpp TRGB 1555 4 _18BPP_RGB_666 18 bpp RGB 666 5 _18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 6 _19BPP_TRGB_1666 19 bpp TRGB 1666 7 _19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 8 _24BPP_RGB_888 24 bpp RGB 888 9 _24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 10 _25BPP_TRGB_1888 25 bpp TRGB 1888 11 _32BPP_ARGB_8888 32 bpp ARGB 8888 12 _32BPP_RGBA_8888 32 bpp RGBA 8888 13 CLUTMODE Color Lookup Table Mode Input Selection [9:8] read-write true CLUT_1BPP Color Lookup Table mode set to 1 bit per pixel 0 CLUT_2BPP Color Lookup Table mode set to 2 bits per pixel 1 CLUT_4BPP Color Lookup Table mode set to 4 bits per pixel 2 CLUT_8BPP Color Lookup Table mode set to 8 bits per pixel 3 YUVMODE YUV Mode Input Selection [15:12] read-write 0 15 YUV422ROT YUV 4:2:2 Rotation [16:16] read-write YUV422SWP YUV 4:2:2 Swap [17:17] read-write DSCALEOPT Down Scaling Bandwidth Optimization [20:20] read-write HEOCFG10 High-End Overlay Configuration Register 10 0x3B4 0x20 read-write BKEY Blue Color Component Chroma Key [7:0] read-write 0 255 GKEY Green Color Component Chroma Key [15:8] read-write 0 255 RKEY Red Color Component Chroma Key [23:16] read-write 0 255 HEOCFG11 High-End Overlay Configuration Register 11 0x3B8 0x20 read-write BMASK Blue Color Component Chroma Key Mask [7:0] read-write 0 255 GMASK Green Color Component Chroma Key Mask [15:8] read-write 0 255 RMASK Red Color Component Chroma Key Mask [23:16] read-write 0 255 HEOCFG12 High-End Overlay Configuration Register 12 0x3BC 0x20 read-write CRKEY Blender Chroma Key Enable [0:0] read-write INV Blender Inverted Blender Output Enable [1:1] read-write ITER2BL Blender Iterated Color Enable [2:2] read-write ITER Blender Use Iterated Color [3:3] read-write REVALPHA Blender Reverse Alpha [4:4] read-write GAEN Blender Global Alpha Enable [5:5] read-write LAEN Blender Local Alpha Enable [6:6] read-write OVR Blender Overlay Layer Enable [7:7] read-write DMA Blender DMA Layer Enable [8:8] read-write REP Use Replication logic to expand RGB color to 24 bits [9:9] read-write DSTKEY Destination Chroma Keying [10:10] read-write VIDPRI Video Priority [12:12] read-write GA Blender Global Alpha [23:16] read-write 0 255 HEOCFG13 High-End Overlay Configuration Register 13 0x3C0 0x20 read-write XFACTOR Horizontal Scaling Factor [13:0] read-write 0 16383 YFACTOR Vertical Scaling Factor [29:16] read-write 0 16383 SCALEN Hardware Scaler Enable [31:31] read-write HEOCFG14 High-End Overlay Configuration Register 14 0x3C4 0x20 read-write CSCRY Color Space Conversion Y coefficient for Red Component 1:2:7 format [9:0] read-write 0 1023 CSCRU Color Space Conversion U coefficient for Red Component 1:2:7 format [19:10] read-write 0 1023 CSCRV Color Space Conversion V coefficient for Red Component 1:2:7 format [29:20] read-write 0 1023 CSCYOFF Color Space Conversion Offset [30:30] read-write HEOCFG15 High-End Overlay Configuration Register 15 0x3C8 0x20 read-write CSCGY Color Space Conversion Y coefficient for Green Component 1:2:7 format [9:0] read-write 0 1023 CSCGU Color Space Conversion U coefficient for Green Component 1:2:7 format [19:10] read-write 0 1023 CSCGV Color Space Conversion V coefficient for Green Component 1:2:7 format [29:20] read-write 0 1023 CSCUOFF Color Space Conversion Offset [30:30] read-write HEOCFG16 High-End Overlay Configuration Register 16 0x3CC 0x20 read-write CSCBY Color Space Conversion Y coefficient for Blue Component 1:2:7 format [9:0] read-write 0 1023 CSCBU Color Space Conversion U coefficient for Blue Component 1:2:7 format [19:10] read-write 0 1023 CSCBV Color Space Conversion V coefficient for Blue Component 1:2:7 format [29:20] read-write 0 1023 CSCVOFF Color Space Conversion Offset [30:30] read-write HEOCFG17 High-End Overlay Configuration Register 17 0x3D0 0x20 read-write XPHI0COEFF0 Horizontal Coefficient for phase 0 tap 0 [7:0] read-write 0 255 XPHI0COEFF1 Horizontal Coefficient for phase 0 tap 1 [15:8] read-write 0 255 XPHI0COEFF2 Horizontal Coefficient for phase 0 tap 2 [23:16] read-write 0 255 XPHI0COEFF3 Horizontal Coefficient for phase 0 tap 3 [31:24] read-write 0 255 HEOCFG18 High-End Overlay Configuration Register 18 0x3D4 0x20 read-write XPHI0COEFF4 Horizontal Coefficient for phase 0 tap 4 [7:0] read-write 0 255 HEOCFG19 High-End Overlay Configuration Register 19 0x3D8 0x20 read-write XPHI1COEFF0 Horizontal Coefficient for phase 1 tap 0 [7:0] read-write 0 255 XPHI1COEFF1 Horizontal Coefficient for phase 1 tap 1 [15:8] read-write 0 255 XPHI1COEFF2 Horizontal Coefficient for phase 1 tap 2 [23:16] read-write 0 255 XPHI1COEFF3 Horizontal Coefficient for phase 1 tap 3 [31:24] read-write 0 255 HEOCFG2 High-End Overlay Configuration Register 2 0x394 0x20 read-write XPOS Horizontal Window Position [10:0] read-write 0 2047 YPOS Vertical Window Position [26:16] read-write 0 2047 HEOCFG20 High-End Overlay Configuration Register 20 0x3DC 0x20 read-write XPHI1COEFF4 Horizontal Coefficient for phase 1 tap 4 [7:0] read-write 0 255 HEOCFG21 High-End Overlay Configuration Register 21 0x3E0 0x20 read-write XPHI2COEFF0 Horizontal Coefficient for phase 2 tap 0 [7:0] read-write 0 255 XPHI2COEFF1 Horizontal Coefficient for phase 2 tap 1 [15:8] read-write 0 255 XPHI2COEFF2 Horizontal Coefficient for phase 2 tap 2 [23:16] read-write 0 255 XPHI2COEFF3 Horizontal Coefficient for phase 2 tap 3 [31:24] read-write 0 255 HEOCFG22 High-End Overlay Configuration Register 22 0x3E4 0x20 read-write XPHI2COEFF4 Horizontal Coefficient for phase 2 tap 4 [7:0] read-write 0 255 HEOCFG23 High-End Overlay Configuration Register 23 0x3E8 0x20 read-write XPHI3COEFF0 Horizontal Coefficient for phase 3 tap 0 [7:0] read-write 0 255 XPHI3COEFF1 Horizontal Coefficient for phase 3 tap 1 [15:8] read-write 0 255 XPHI3COEFF2 Horizontal Coefficient for phase 3 tap 2 [23:16] read-write 0 255 XPHI3COEFF3 Horizontal Coefficient for phase 3 tap 3 [31:24] read-write 0 255 HEOCFG24 High-End Overlay Configuration Register 24 0x3EC 0x20 read-write XPHI3COEFF4 Horizontal Coefficient for phase 3 tap 4 [7:0] read-write 0 255 HEOCFG25 High-End Overlay Configuration Register 25 0x3F0 0x20 read-write XPHI4COEFF0 Horizontal Coefficient for phase 4 tap 0 [7:0] read-write 0 255 XPHI4COEFF1 Horizontal Coefficient for phase 4 tap 1 [15:8] read-write 0 255 XPHI4COEFF2 Horizontal Coefficient for phase 4 tap 2 [23:16] read-write 0 255 XPHI4COEFF3 Horizontal Coefficient for phase 4 tap 3 [31:24] read-write 0 255 HEOCFG26 High-End Overlay Configuration Register 26 0x3F4 0x20 read-write XPHI4COEFF4 Horizontal Coefficient for phase 4 tap 4 [7:0] read-write 0 255 HEOCFG27 High-End Overlay Configuration Register 27 0x3F8 0x20 read-write XPHI5COEFF0 Horizontal Coefficient for phase 5 tap 0 [7:0] read-write 0 255 XPHI5COEFF1 Horizontal Coefficient for phase 5 tap 1 [15:8] read-write 0 255 XPHI5COEFF2 Horizontal Coefficient for phase 5 tap 2 [23:16] read-write 0 255 XPHI5COEFF3 Horizontal Coefficient for phase 5 tap 3 [31:24] read-write 0 255 HEOCFG28 High-End Overlay Configuration Register 28 0x3FC 0x20 read-write XPHI5COEFF4 Horizontal Coefficient for phase 5 tap 4 [7:0] read-write 0 255 HEOCFG29 High-End Overlay Configuration Register 29 0x400 0x20 read-write XPHI6COEFF0 Horizontal Coefficient for phase 6 tap 0 [7:0] read-write 0 255 XPHI6COEFF1 Horizontal Coefficient for phase 6 tap 1 [15:8] read-write 0 255 XPHI6COEFF2 Horizontal Coefficient for phase 6 tap 2 [23:16] read-write 0 255 XPHI6COEFF3 Horizontal Coefficient for phase 6 tap 3 [31:24] read-write 0 255 HEOCFG3 High-End Overlay Configuration Register 3 0x398 0x20 read-write XSIZE Horizontal Window Size [10:0] read-write 0 2047 YSIZE Vertical Window Size [26:16] read-write 0 2047 HEOCFG30 High-End Overlay Configuration Register 30 0x404 0x20 read-write XPHI6COEFF4 Horizontal Coefficient for phase 6 tap 4 [7:0] read-write 0 255 HEOCFG31 High-End Overlay Configuration Register 31 0x408 0x20 read-write XPHI7COEFF0 Horizontal Coefficient for phase 7 tap 0 [7:0] read-write 0 255 XPHI7COEFF1 Horizontal Coefficient for phase 7 tap 1 [15:8] read-write 0 255 XPHI7COEFF2 Horizontal Coefficient for phase 7 tap 2 [23:16] read-write 0 255 XPHI7COEFF3 Horizontal Coefficient for phase 7 tap 3 [31:24] read-write 0 255 HEOCFG32 High-End Overlay Configuration Register 32 0x40C 0x20 read-write XPHI7COEFF4 Horizontal Coefficient for phase 7 tap 4 [7:0] read-write 0 255 HEOCFG33 High-End Overlay Configuration Register 33 0x410 0x20 read-write YPHI0COEFF0 Vertical Coefficient for phase 0 tap 0 [7:0] read-write 0 255 YPHI0COEFF1 Vertical Coefficient for phase 0 tap 1 [15:8] read-write 0 255 YPHI0COEFF2 Vertical Coefficient for phase 0 tap 2 [23:16] read-write 0 255 HEOCFG34 High-End Overlay Configuration Register 34 0x414 0x20 read-write YPHI1COEFF0 Vertical Coefficient for phase 1 tap 0 [7:0] read-write 0 255 YPHI1COEFF1 Vertical Coefficient for phase 1 tap 1 [15:8] read-write 0 255 YPHI1COEFF2 Vertical Coefficient for phase 1 tap 2 [23:16] read-write 0 255 HEOCFG35 High-End Overlay Configuration Register 35 0x418 0x20 read-write YPHI2COEFF0 Vertical Coefficient for phase 2 tap 0 [7:0] read-write 0 255 YPHI2COEFF1 Vertical Coefficient for phase 2 tap 1 [15:8] read-write 0 255 YPHI2COEFF2 Vertical Coefficient for phase 2 tap 2 [23:16] read-write 0 255 HEOCFG36 High-End Overlay Configuration Register 36 0x41C 0x20 read-write YPHI3COEFF0 Vertical Coefficient for phase 3 tap 0 [7:0] read-write 0 255 YPHI3COEFF1 Vertical Coefficient for phase 3 tap 1 [15:8] read-write 0 255 YPHI3COEFF2 Vertical Coefficient for phase 3 tap 2 [23:16] read-write 0 255 HEOCFG37 High-End Overlay Configuration Register 37 0x420 0x20 read-write YPHI4COEFF0 Vertical Coefficient for phase 4 tap 0 [7:0] read-write 0 255 YPHI4COEFF1 Vertical Coefficient for phase 4 tap 1 [15:8] read-write 0 255 YPHI4COEFF2 Vertical Coefficient for phase 4 tap 2 [23:16] read-write 0 255 HEOCFG38 High-End Overlay Configuration Register 38 0x424 0x20 read-write YPHI5COEFF0 Vertical Coefficient for phase 5 tap 0 [7:0] read-write 0 255 YPHI5COEFF1 Vertical Coefficient for phase 5 tap 1 [15:8] read-write 0 255 YPHI5COEFF2 Vertical Coefficient for phase 5 tap 2 [23:16] read-write 0 255 HEOCFG39 High-End Overlay Configuration Register 39 0x428 0x20 read-write YPHI6COEFF0 Vertical Coefficient for phase 6 tap 0 [7:0] read-write 0 255 YPHI6COEFF1 Vertical Coefficient for phase 6 tap 1 [15:8] read-write 0 255 YPHI6COEFF2 Vertical Coefficient for phase 6 tap 2 [23:16] read-write 0 255 HEOCFG4 High-End Overlay Configuration Register 4 0x39C 0x20 read-write XMEMSIZE Horizontal image Size in Memory [10:0] read-write 0 2047 YMEMSIZE Vertical image Size in Memory [26:16] read-write 0 2047 HEOCFG40 High-End Overlay Configuration Register 40 0x42C 0x20 read-write YPHI7COEFF0 Vertical Coefficient for phase 7 tap 0 [7:0] read-write 0 255 YPHI7COEFF1 Vertical Coefficient for phase 7 tap 1 [15:8] read-write 0 255 YPHI7COEFF2 Vertical Coefficient for phase 7 tap 2 [23:16] read-write 0 255 HEOCFG41 High-End Overlay Configuration Register 41 0x430 0x20 read-write XPHIDEF Horizontal Filter Phase Offset [2:0] read-write 0 7 YPHIDEF Vertical Filter Phase Offset [18:16] read-write 0 7 HEOCFG5 High-End Overlay Configuration Register 5 0x3A0 0x20 read-write XSTRIDE Horizontal Stride [31:0] read-write 0 4294967295 HEOCFG6 High-End Overlay Configuration Register 6 0x3A4 0x20 read-write PSTRIDE Pixel Stride [31:0] read-write 0 4294967295 HEOCFG7 High-End Overlay Configuration Register 7 0x3A8 0x20 read-write UVXSTRIDE UV Horizontal Stride [31:0] read-write 0 4294967295 HEOCFG8 High-End Overlay Configuration Register 8 0x3AC 0x20 read-write UVPSTRIDE UV Pixel Stride [31:0] read-write 0 4294967295 HEOCFG9 High-End Overlay Configuration Register 9 0x3B0 0x20 read-write BDEF Blue Default [7:0] read-write 0 255 GDEF Green Default [15:8] read-write 0 255 RDEF Red Default [23:16] read-write 0 255 HEOCHDR High-End Overlay Channel Disable Register 0x344 0x20 write-only CHDIS Channel Disable [0:0] read-write CHRST Channel Reset [8:8] read-write HEOCHER High-End Overlay Channel Enable Register 0x340 0x20 write-only CHEN Channel Enable [0:0] read-write UPDATEEN Update Overlay Attributes Enable [1:1] read-write A2QEN Add To Queue Enable [2:2] read-write HEOCHSR High-End Overlay Channel Status Register 0x348 0x20 read-only CHSR Channel Status [0:0] read-write UPDATESR Update Overlay Attributes In Progress Status [1:1] read-write A2QSR Add To Queue Status [2:2] read-write HEOCLUT High-End Overlay CLUT Register 0x1200 0x20 read-write BCLUT Blue Color Entry [7:0] read-write 0 255 GCLUT Green Color Entry [15:8] read-write 0 255 RCLUT Red Color Entry [23:16] read-write 0 255 ACLUT Alpha Color Entry [31:24] read-write 0 255 HEOCTRL High-End Overlay DMA Control Register 0x364 0x20 read-write DFETCH Transfer Descriptor Fetch Enable [0:0] read-write LFETCH Lookup Table Fetch Enable [1:1] read-write DMAIEN End of DMA Transfer Interrupt Enable [2:2] read-write DSCRIEN Descriptor Loaded Interrupt Enable [3:3] read-write ADDIEN Add Head Descriptor to Queue Interrupt Enable [4:4] read-write DONEIEN End of List Interrupt Enable [5:5] read-write HEOHEAD High-End Overlay DMA Head Register 0x35C 0x20 read-write HEAD DMA Head Pointer [31:2] read-write 0 1073741823 HEOIDR High-End Overlay Interrupt Disable Register 0x350 0x20 write-only DMA End of DMA Transfer Interrupt Disable [2:2] read-write DSCR Descriptor Loaded Interrupt Disable [3:3] read-write ADD Head Descriptor Loaded Interrupt Disable [4:4] read-write DONE End of List Interrupt Disable [5:5] read-write OVR Overflow Interrupt Disable [6:6] read-write UDMA End of DMA Transfer for U or UV Chrominance Component Interrupt Disable [10:10] read-write UDSCR Descriptor Loaded for U or UV Chrominance Component Interrupt Disable [11:11] read-write UADD Head Descriptor Loaded for U or UV Chrominance Component Interrupt Disable [12:12] read-write UDONE End of List Interrupt for U or UV Chrominance Component Disable [13:13] read-write UOVR Overflow Interrupt for U or UV Chrominance Component Disable [14:14] read-write VDMA End of DMA Transfer for V Chrominance Component Interrupt Disable [18:18] read-write VDSCR Descriptor Loaded for V Chrominance Component Interrupt Disable [19:19] read-write VADD Head Descriptor Loaded for V Chrominance Component Interrupt Disable [20:20] read-write VDONE End of List for V Chrominance Component Interrupt Disable [21:21] read-write VOVR Overflow for V Chrominance Component Interrupt Disable [22:22] read-write HEOIER High-End Overlay Interrupt Enable Register 0x34C 0x20 write-only DMA End of DMA Transfer Interrupt Enable [2:2] read-write DSCR Descriptor Loaded Interrupt Enable [3:3] read-write ADD Head Descriptor Loaded Interrupt Enable [4:4] read-write DONE End of List Interrupt Enable [5:5] read-write OVR Overflow Interrupt Enable [6:6] read-write UDMA End of DMA Transfer for U or UV Chrominance Interrupt Enable [10:10] read-write UDSCR Descriptor Loaded for U or UV Chrominance Interrupt Enable [11:11] read-write UADD Head Descriptor Loaded for U or UV Chrominance Interrupt Enable [12:12] read-write UDONE End of List for U or UV Chrominance Interrupt Enable [13:13] read-write UOVR Overflow for U or UV Chrominance Interrupt Enable [14:14] read-write VDMA End of DMA for V Chrominance Transfer Interrupt Enable [18:18] read-write VDSCR Descriptor Loaded for V Chrominance Interrupt Enable [19:19] read-write VADD Head Descriptor Loaded for V Chrominance Interrupt Enable [20:20] read-write VDONE End of List for V Chrominance Interrupt Enable [21:21] read-write VOVR Overflow for V Chrominance Interrupt Enable [22:22] read-write HEOIMR High-End Overlay Interrupt Mask Register 0x354 0x20 read-only DMA End of DMA Transfer Interrupt Mask [2:2] read-write DSCR Descriptor Loaded Interrupt Mask [3:3] read-write ADD Head Descriptor Loaded Interrupt Mask [4:4] read-write DONE End of List Interrupt Mask [5:5] read-write OVR Overflow Interrupt Mask [6:6] read-write UDMA End of DMA Transfer for U or UV Chrominance Component Interrupt Mask [10:10] read-write UDSCR Descriptor Loaded for U or UV Chrominance Component Interrupt Mask [11:11] read-write UADD Head Descriptor Loaded for U or UV Chrominance Component Mask [12:12] read-write UDONE End of List for U or UV Chrominance Component Mask [13:13] read-write UOVR Overflow for U Chrominance Interrupt Mask [14:14] read-write VDMA End of DMA Transfer for V Chrominance Component Interrupt Mask [18:18] read-write VDSCR Descriptor Loaded for V Chrominance Component Interrupt Mask [19:19] read-write VADD Head Descriptor Loaded for V Chrominance Component Mask [20:20] read-write VDONE End of List for V Chrominance Component Mask [21:21] read-write VOVR Overflow for V Chrominance Interrupt Mask [22:22] read-write HEOISR High-End Overlay Interrupt Status Register 0x358 0x20 read-only DMA End of DMA Transfer [2:2] read-write DSCR DMA Descriptor Loaded [3:3] read-write ADD Head Descriptor Loaded [4:4] read-write DONE End of List Detected [5:5] read-write OVR Overflow Detected [6:6] read-write UDMA End of DMA Transfer for U Component [10:10] read-write UDSCR DMA Descriptor Loaded for U Component [11:11] read-write UADD Head Descriptor Loaded for U Component [12:12] read-write UDONE End of List Detected for U Component [13:13] read-write UOVR Overflow Detected for U Component [14:14] read-write VDMA End of DMA Transfer for V Component [18:18] read-write VDSCR DMA Descriptor Loaded for V Component [19:19] read-write VADD Head Descriptor Loaded for V Component [20:20] read-write VDONE End of List Detected for V Component [21:21] read-write VOVR Overflow Detected for V Component [22:22] read-write HEONEXT High-End Overlay DMA Next Register 0x368 0x20 read-write NEXT DMA Descriptor Next Address [31:0] read-write 0 4294967295 HEOUADDR High-End Overlay U-UV DMA Address Register 0x370 0x20 read-write UADDR DMA Transfer Start Address for U or UV Chrominance [31:0] read-write 0 4294967295 HEOUCTRL High-End Overlay U-UV DMA Control Register 0x374 0x20 read-write UDFETCH Transfer Descriptor Fetch Enable [0:0] read-write UDMAIEN End of DMA Transfer Interrupt Enable [2:2] read-write UDSCRIEN Descriptor Loaded Interrupt Enable [3:3] read-write UADDIEN Add Head Descriptor to Queue Interrupt Enable [4:4] read-write UDONEIEN End of List Interrupt Enable [5:5] read-write HEOUHEAD High-End Overlay U-UV DMA Head Register 0x36C 0x20 read-write UHEAD DMA Head Pointer [31:0] read-write 0 4294967295 HEOUNEXT High-End Overlay U-UV DMA Next Register 0x378 0x20 read-write UNEXT DMA Descriptor Next Address [31:0] read-write 0 4294967295 HEOVADDR High-End Overlay V DMA Address Register 0x380 0x20 read-write VADDR DMA Transfer Start Address for V Chrominance [31:0] read-write 0 4294967295 HEOVCTRL High-End Overlay V DMA Control Register 0x384 0x20 read-write VDFETCH Transfer Descriptor Fetch Enable [0:0] read-write VDMAIEN End of DMA Transfer Interrupt Enable [2:2] read-write VDSCRIEN Descriptor Loaded Interrupt Enable [3:3] read-write VADDIEN Add Head Descriptor to Queue Interrupt Enable [4:4] read-write VDONEIEN End of List Interrupt Enable [5:5] read-write HEOVHEAD High-End Overlay V DMA Head Register 0x37C 0x20 read-write VHEAD DMA Head Pointer [31:0] read-write 0 4294967295 HEOVNEXT High-End Overlay V DMA Next Register 0x388 0x20 read-write VNEXT DMA Descriptor Next Address [31:0] read-write 0 4294967295 LCDCFG0 LCD Controller Configuration Register 0 0x0 0x20 read-write CLKPOL LCD Controller Clock Polarity [0:0] read-write CLKSEL LCD Controller Clock Source Selection [2:2] read-write CLKPWMSEL LCD Controller PWM Clock Source Selection [3:3] read-write CGDISBASE Clock Gating Disable Control for the Base Layer [8:8] read-write CGDISOVR1 Clock Gating Disable Control for the Overlay 1 Layer [9:9] read-write CGDISOVR2 Clock Gating Disable Control for the Overlay 2 Layer [10:10] read-write CGDISHEO Clock Gating Disable Control for the High-End Overlay [11:11] read-write CGDISPP Clock Gating Disable Control for the Post Processing Layer [13:13] read-write CLKDIV LCD Controller Clock Divider [23:16] read-write 0 255 LCDCFG1 LCD Controller Configuration Register 1 0x4 0x20 read-write HSPW Horizontal Synchronization Pulse Width [9:0] read-write 0 1023 VSPW Vertical Synchronization Pulse Width [25:16] read-write 0 1023 LCDCFG2 LCD Controller Configuration Register 2 0x8 0x20 read-write VFPW Vertical Front Porch Width [9:0] read-write 0 1023 VBPW Vertical Back Porch Width [25:16] read-write 0 1023 LCDCFG3 LCD Controller Configuration Register 3 0xC 0x20 read-write HFPW Horizontal Front Porch Width [9:0] read-write 0 1023 HBPW Horizontal Back Porch Width [25:16] read-write 0 1023 LCDCFG4 LCD Controller Configuration Register 4 0x10 0x20 read-write PPL Number of Pixels Per Line [10:0] read-write 0 2047 RPF Number of Active Row Per Frame [26:16] read-write 0 2047 LCDCFG5 LCD Controller Configuration Register 5 0x14 0x20 read-write HSPOL Horizontal Synchronization Pulse Polarity [0:0] read-write VSPOL Vertical Synchronization Pulse Polarity [1:1] read-write VSPDLYS Vertical Synchronization Pulse Start [2:2] read-write VSPDLYE Vertical Synchronization Pulse End [3:3] read-write DISPPOL Display Signal Polarity [4:4] read-write DITHER LCD Controller Dithering [6:6] read-write DISPDLY LCD Controller Display Power Signal Synchronization [7:7] read-write MODE LCD Controller Output Mode [9:8] read-write true OUTPUT_12BPP LCD Output mode is set to 12 bits per pixel 0 OUTPUT_16BPP LCD Output mode is set to 16 bits per pixel 1 OUTPUT_18BPP LCD Output mode is set to 18 bits per pixel 2 OUTPUT_24BPP LCD Output mode is set to 24 bits per pixel 3 PP Post Processing Enable [10:10] read-write VSPSU LCD Controller Vertical synchronization Pulse Setup Configuration [12:12] read-write VSPHO LCD Controller Vertical synchronization Pulse Hold Configuration [13:13] read-write GUARDTIME LCD DISPLAY Guard Time [23:16] read-write 0 255 LCDCFG6 LCD Controller Configuration Register 6 0x18 0x20 read-write PWMPS PWM Clock Prescaler [2:0] read-write true DIV_1 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK 0 DIV_2 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/2 1 DIV_4 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/4 2 DIV_8 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/8 3 DIV_16 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/16 4 DIV_32 The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/32 5 DIV_64 The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/64 6 PWMPOL LCD Controller PWM Signal Polarity [4:4] read-write PWMCVAL LCD Controller PWM Compare Value [15:8] read-write 0 255 LCDDIS LCD Controller Disable Register 0x24 0x20 write-only CLKDIS LCD Controller Pixel Clock Disable [0:0] read-write SYNCDIS LCD Controller Horizontal and Vertical Synchronization Disable [1:1] read-write DISPDIS LCD Controller DISP Signal Disable [2:2] read-write PWMDIS LCD Controller Pulse Width Modulation Disable [3:3] read-write CLKRST LCD Controller Clock Reset [8:8] read-write SYNCRST LCD Controller Horizontal and Vertical Synchronization Reset [9:9] read-write DISPRST LCD Controller DISP Signal Reset [10:10] read-write PWMRST LCD Controller PWM Reset [11:11] read-write LCDEN LCD Controller Enable Register 0x20 0x20 write-only CLKEN LCD Controller Pixel Clock Enable [0:0] read-write SYNCEN LCD Controller Horizontal and Vertical Synchronization Enable [1:1] read-write DISPEN LCD Controller DISP Signal Enable [2:2] read-write PWMEN LCD Controller Pulse Width Modulation Enable [3:3] read-write LCDIDR LCD Controller Interrupt Disable Register 0x30 0x20 write-only SOFID Start of Frame Interrupt Disable [0:0] read-write DISID LCD Disable Interrupt Disable [1:1] read-write DISPID Powerup/Powerdown Sequence Terminated Interrupt Disable [2:2] read-write FIFOERRID Output FIFO Error Interrupt Disable [4:4] read-write BASEID Base Layer Interrupt Disable [8:8] read-write OVR1ID Overlay 1 Interrupt Disable [9:9] read-write OVR2ID Overlay 2 Interrupt Disable [10:10] read-write HEOID High-End Overlay Interrupt Disable [11:11] read-write PPID Post Processing Interrupt Disable [13:13] read-write LCDIER LCD Controller Interrupt Enable Register 0x2C 0x20 write-only SOFIE Start of Frame Interrupt Enable [0:0] read-write DISIE LCD Disable Interrupt Enable [1:1] read-write DISPIE Powerup/Powerdown Sequence Terminated Interrupt Enable [2:2] read-write FIFOERRIE Output FIFO Error Interrupt Enable [4:4] read-write BASEIE Base Layer Interrupt Enable [8:8] read-write OVR1IE Overlay 1 Interrupt Enable [9:9] read-write OVR2IE Overlay 2 Interrupt Enable [10:10] read-write HEOIE High-End Overlay Interrupt Enable [11:11] read-write PPIE Post Processing Interrupt Enable [13:13] read-write LCDIMR LCD Controller Interrupt Mask Register 0x34 0x20 read-only SOFIM Start of Frame Interrupt Mask [0:0] read-write DISIM LCD Disable Interrupt Mask [1:1] read-write DISPIM Powerup/Powerdown Sequence Terminated Interrupt Mask [2:2] read-write FIFOERRIM Output FIFO Error Interrupt Mask [4:4] read-write BASEIM Base Layer Interrupt Mask [8:8] read-write OVR1IM Overlay 1 Interrupt Mask [9:9] read-write OVR2IM Overlay 2 Interrupt Mask [10:10] read-write HEOIM High-End Overlay Interrupt Mask [11:11] read-write PPIM Post Processing Interrupt Mask [13:13] read-write LCDISR LCD Controller Interrupt Status Register 0x38 0x20 read-only SOF Start of Frame Interrupt Status [0:0] read-write DIS LCD Disable Interrupt Status [1:1] read-write DISP Powerup/Powerdown Sequence Terminated Interrupt Status [2:2] read-write FIFOERR Output FIFO Error [4:4] read-write BASE Base Layer Raw Interrupt Status [8:8] read-write OVR1 Overlay 1 Raw Interrupt Status [9:9] read-write OVR2 Overlay 2 Raw Interrupt Status [10:10] read-write HEO High-End Overlay Raw Interrupt Status [11:11] read-write PP Post Processing Raw Interrupt Status [13:13] read-write LCDSR LCD Controller Status Register 0x28 0x20 read-only CLKSTS Clock Status [0:0] read-write LCDSTS LCD Controller Synchronization status [1:1] read-write DISPSTS LCD Controller DISP Signal Status [2:2] read-write PWMSTS LCD Controller PWM Signal Status [3:3] read-write SIPSTS Synchronization In Progress [4:4] read-write OVR1ADDR Overlay 1 DMA Address Register 0x160 0x20 read-write ADDR DMA Transfer Overlay 1 Address [31:0] read-write 0 4294967295 OVR1CFG0 Overlay 1 Configuration Register 0 0x16C 0x20 read-write SIF Source Interface [0:0] read-write BLEN AHB Burst Length [5:4] read-write true AHB_BLEN_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 0 AHB_BLEN_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_BLEN_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_BLEN_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 DLBO Defined Length Burst Only for Channel Bus Transaction [8:8] read-write ROTDIS Hardware Rotation Optimization Disable [12:12] read-write LOCKDIS Hardware Rotation Lock Disable [13:13] read-write OVR1CFG1 Overlay 1 Configuration Register 1 0x170 0x20 read-write CLUTEN Color Lookup Table Mode Enable [0:0] read-write RGBMODE RGB Mode Input Selection [7:4] read-write true _12BPP_RGB_444 12 bpp RGB 444 0 _16BPP_ARGB_4444 16 bpp ARGB 4444 1 _16BPP_RGBA_4444 16 bpp RGBA 4444 2 _16BPP_RGB_565 16 bpp RGB 565 3 _16BPP_TRGB_1555 16 bpp TRGB 1555 4 _18BPP_RGB_666 18 bpp RGB 666 5 _18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 6 _19BPP_TRGB_1666 19 bpp TRGB 1666 7 _19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 8 _24BPP_RGB_888 24 bpp RGB 888 9 _24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 10 _25BPP_TRGB_1888 25 bpp TRGB 1888 11 _32BPP_ARGB_8888 32 bpp ARGB 8888 12 _32BPP_RGBA_8888 32 bpp RGBA 8888 13 CLUTMODE Color Lookup Table Mode Input Selection [9:8] read-write true CLUT_1BPP Color Lookup Table mode set to 1 bit per pixel 0 CLUT_2BPP Color Lookup Table mode set to 2 bits per pixel 1 CLUT_4BPP Color Lookup Table mode set to 4 bits per pixel 2 CLUT_8BPP Color Lookup Table mode set to 8 bits per pixel 3 OVR1CFG2 Overlay 1 Configuration Register 2 0x174 0x20 read-write XPOS Horizontal Window Position [10:0] read-write 0 2047 YPOS Vertical Window Position [26:16] read-write 0 2047 OVR1CFG3 Overlay 1 Configuration Register 3 0x178 0x20 read-write XSIZE Horizontal Window Size [10:0] read-write 0 2047 YSIZE Vertical Window Size [26:16] read-write 0 2047 OVR1CFG4 Overlay 1 Configuration Register 4 0x17C 0x20 read-write XSTRIDE Horizontal Stride [31:0] read-write 0 4294967295 OVR1CFG5 Overlay 1 Configuration Register 5 0x180 0x20 read-write PSTRIDE Pixel Stride [31:0] read-write 0 4294967295 OVR1CFG6 Overlay 1 Configuration Register 6 0x184 0x20 read-write BDEF Blue Default [7:0] read-write 0 255 GDEF Green Default [15:8] read-write 0 255 RDEF Red Default [23:16] read-write 0 255 OVR1CFG7 Overlay 1 Configuration Register 7 0x188 0x20 read-write BKEY Blue Color Component Chroma Key [7:0] read-write 0 255 GKEY Green Color Component Chroma Key [15:8] read-write 0 255 RKEY Red Color Component Chroma Key [23:16] read-write 0 255 OVR1CFG8 Overlay 1 Configuration Register 8 0x18C 0x20 read-write BMASK Blue Color Component Chroma Key Mask [7:0] read-write 0 255 GMASK Green Color Component Chroma Key Mask [15:8] read-write 0 255 RMASK Red Color Component Chroma Key Mask [23:16] read-write 0 255 OVR1CFG9 Overlay 1 Configuration Register 9 0x190 0x20 read-write CRKEY Blender Chroma Key Enable [0:0] read-write INV Blender Inverted Blender Output Enable [1:1] read-write ITER2BL Blender Iterated Color Enable [2:2] read-write ITER Blender Use Iterated Color [3:3] read-write REVALPHA Blender Reverse Alpha [4:4] read-write GAEN Blender Global Alpha Enable [5:5] read-write LAEN Blender Local Alpha Enable [6:6] read-write OVR Blender Overlay Layer Enable [7:7] read-write DMA Blender DMA Layer Enable [8:8] read-write REP Use Replication logic to expand RGB color to 24 bits [9:9] read-write DSTKEY Destination Chroma Keying [10:10] read-write GA Blender Global Alpha [23:16] read-write 0 255 OVR1CHDR Overlay 1 Channel Disable Register 0x144 0x20 write-only CHDIS Channel Disable [0:0] read-write CHRST Channel Reset [8:8] read-write OVR1CHER Overlay 1 Channel Enable Register 0x140 0x20 write-only CHEN Channel Enable [0:0] read-write UPDATEEN Update Overlay Attributes Enable [1:1] read-write A2QEN Add To Queue Enable [2:2] read-write OVR1CHSR Overlay 1 Channel Status Register 0x148 0x20 read-only CHSR Channel Status [0:0] read-write UPDATESR Update Overlay Attributes In Progress Status [1:1] read-write A2QSR Add To Queue Status [2:2] read-write OVR1CLUT Overlay 1 CLUT Register 0xA00 0x20 read-write BCLUT Blue Color Entry [7:0] read-write 0 255 GCLUT Green Color Entry [15:8] read-write 0 255 RCLUT Red Color Entry [23:16] read-write 0 255 ACLUT Alpha Color Entry [31:24] read-write 0 255 OVR1CTRL Overlay 1 DMA Control Register 0x164 0x20 read-write DFETCH Transfer Descriptor Fetch Enable [0:0] read-write LFETCH Lookup Table Fetch Enable [1:1] read-write DMAIEN End of DMA Transfer Interrupt Enable [2:2] read-write DSCRIEN Descriptor Loaded Interrupt Enable [3:3] read-write ADDIEN Add Head Descriptor to Queue Interrupt Enable [4:4] read-write DONEIEN End of List Interrupt Enable [5:5] read-write OVR1HEAD Overlay 1 DMA Head Register 0x15C 0x20 read-write HEAD DMA Head Pointer [31:2] read-write 0 1073741823 OVR1IDR Overlay 1 Interrupt Disable Register 0x150 0x20 write-only DMA End of DMA Transfer Interrupt Disable [2:2] read-write DSCR Descriptor Loaded Interrupt Disable [3:3] read-write ADD Head Descriptor Loaded Interrupt Disable [4:4] read-write DONE End of List Interrupt Disable [5:5] read-write OVR Overflow Interrupt Disable [6:6] read-write OVR1IER Overlay 1 Interrupt Enable Register 0x14C 0x20 write-only DMA End of DMA Transfer Interrupt Enable [2:2] read-write DSCR Descriptor Loaded Interrupt Enable [3:3] read-write ADD Head Descriptor Loaded Interrupt Enable [4:4] read-write DONE End of List Interrupt Enable [5:5] read-write OVR Overflow Interrupt Enable [6:6] read-write OVR1IMR Overlay 1 Interrupt Mask Register 0x154 0x20 read-only DMA End of DMA Transfer Interrupt Mask [2:2] read-write DSCR Descriptor Loaded Interrupt Mask [3:3] read-write ADD Head Descriptor Loaded Interrupt Mask [4:4] read-write DONE End of List Interrupt Mask [5:5] read-write OVR Overflow Interrupt Mask [6:6] read-write OVR1ISR Overlay 1 Interrupt Status Register 0x158 0x20 read-only DMA End of DMA Transfer [2:2] read-write DSCR DMA Descriptor Loaded [3:3] read-write ADD Head Descriptor Loaded [4:4] read-write DONE End of List Detected [5:5] read-write OVR Overflow Detected [6:6] read-write OVR1NEXT Overlay 1 DMA Next Register 0x168 0x20 read-write NEXT DMA Descriptor Next Address [31:0] read-write 0 4294967295 OVR2ADDR Overlay 2 DMA Address Register 0x260 0x20 read-write ADDR DMA Transfer Overlay 2 Address [31:0] read-write 0 4294967295 OVR2CFG0 Overlay 2 Configuration Register 0 0x26C 0x20 read-write BLEN AHB Burst Length [5:4] read-write true AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 0 AHB_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 DLBO Defined Length Burst Only For Channel Bus Transaction [8:8] read-write ROTDIS Hardware Rotation Optimization Disable [12:12] read-write LOCKDIS Hardware Rotation Lock Disable [13:13] read-write OVR2CFG1 Overlay 2 Configuration Register 1 0x270 0x20 read-write CLUTEN Color Lookup Table Mode Enable [0:0] read-write RGBMODE RGB Mode Input Selection [7:4] read-write true _12BPP_RGB_444 12 bpp RGB 444 0 _16BPP_ARGB_4444 16 bpp ARGB 4444 1 _16BPP_RGBA_4444 16 bpp RGBA 4444 2 _16BPP_RGB_565 16 bpp RGB 565 3 _16BPP_TRGB_1555 16 bpp TRGB 1555 4 _18BPP_RGB_666 18 bpp RGB 666 5 _18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 6 _19BPP_TRGB_1666 19 bpp TRGB 1666 7 _19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 8 _24BPP_RGB_888 24 bpp RGB 888 9 _24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 10 _25BPP_TRGB_1888 25 bpp TRGB 1888 11 _32BPP_ARGB_8888 32 bpp ARGB 8888 12 _32BPP_RGBA_8888 32 bpp RGBA 8888 13 CLUTMODE Color Lookup Table Mode Input Selection [9:8] read-write true CLUT_1BPP Color Lookup Table mode set to 1 bit per pixel 0 CLUT_2BPP Color Lookup Table mode set to 2 bits per pixel 1 CLUT_4BPP Color Lookup Table mode set to 4 bits per pixel 2 CLUT_8BPP Color Lookup Table mode set to 8 bits per pixel 3 OVR2CFG2 Overlay 2 Configuration Register 2 0x274 0x20 read-write XPOS Horizontal Window Position [10:0] read-write 0 2047 YPOS Vertical Window Position [26:16] read-write 0 2047 OVR2CFG3 Overlay 2 Configuration Register 3 0x278 0x20 read-write XSIZE Horizontal Window Size [10:0] read-write 0 2047 YSIZE Vertical Window Size [26:16] read-write 0 2047 OVR2CFG4 Overlay 2 Configuration Register 4 0x27C 0x20 read-write XSTRIDE Horizontal Stride [31:0] read-write 0 4294967295 OVR2CFG5 Overlay 2 Configuration Register 5 0x280 0x20 read-write PSTRIDE Pixel Stride [31:0] read-write 0 4294967295 OVR2CFG6 Overlay 2 Configuration Register 6 0x284 0x20 read-write BDEF Blue Default [7:0] read-write 0 255 GDEF Green Default [15:8] read-write 0 255 RDEF Red Default [23:16] read-write 0 255 OVR2CFG7 Overlay 2 Configuration Register 7 0x288 0x20 read-write BKEY Blue Color Component Chroma Key [7:0] read-write 0 255 GKEY Green Color Component Chroma Key [15:8] read-write 0 255 RKEY Red Color Component Chroma Key [23:16] read-write 0 255 OVR2CFG8 Overlay 2 Configuration Register 8 0x28C 0x20 read-write BMASK Blue Color Component Chroma Key Mask [7:0] read-write 0 255 GMASK Green Color Component Chroma Key Mask [15:8] read-write 0 255 RMASK Red Color Component Chroma Key Mask [23:16] read-write 0 255 OVR2CFG9 Overlay 2 Configuration Register 9 0x290 0x20 read-write CRKEY Blender Chroma Key Enable [0:0] read-write INV Blender Inverted Blender Output Enable [1:1] read-write ITER2BL Blender Iterated Color Enable [2:2] read-write ITER Blender Use Iterated Color [3:3] read-write REVALPHA Blender Reverse Alpha [4:4] read-write GAEN Blender Global Alpha Enable [5:5] read-write LAEN Blender Local Alpha Enable [6:6] read-write OVR Blender Overlay Layer Enable [7:7] read-write DMA Blender DMA Layer Enable [8:8] read-write REP Use Replication logic to expand RGB color to 24 bits [9:9] read-write DSTKEY Destination Chroma Keying [10:10] read-write GA Blender Global Alpha [23:16] read-write 0 255 OVR2CHDR Overlay 2 Channel Disable Register 0x244 0x20 write-only CHDIS Channel Disable [0:0] read-write CHRST Channel Reset [8:8] read-write OVR2CHER Overlay 2 Channel Enable Register 0x240 0x20 write-only CHEN Channel Enable [0:0] read-write UPDATEEN Update Overlay Attributes Enable [1:1] read-write A2QEN Add To Queue Enable [2:2] read-write OVR2CHSR Overlay 2 Channel Status Register 0x248 0x20 read-only CHSR Channel Status [0:0] read-write UPDATESR Update Overlay Attributes In Progress Status [1:1] read-write A2QSR Add To Queue Status [2:2] read-write OVR2CLUT Overlay 2 CLUT Register 0xE00 0x20 read-write BCLUT Blue Color Entry [7:0] read-write 0 255 GCLUT Green Color Entry [15:8] read-write 0 255 RCLUT Red Color Entry [23:16] read-write 0 255 ACLUT Alpha Color Entry [31:24] read-write 0 255 OVR2CTRL Overlay 2 DMA Control Register 0x264 0x20 read-write DFETCH Transfer Descriptor Fetch Enable [0:0] read-write LFETCH Lookup Table Fetch Enable [1:1] read-write DMAIEN End of DMA Transfer Interrupt Enable [2:2] read-write DSCRIEN Descriptor Loaded Interrupt Enable [3:3] read-write ADDIEN Add Head Descriptor to Queue Interrupt Enable [4:4] read-write DONEIEN End of List Interrupt Enable [5:5] read-write OVR2HEAD Overlay 2 DMA Head Register 0x25C 0x20 read-write HEAD DMA Head Pointer [31:2] read-write 0 1073741823 OVR2IDR Overlay 2 Interrupt Disable Register 0x250 0x20 write-only DMA End of DMA Transfer Interrupt Disable [2:2] read-write DSCR Descriptor Loaded Interrupt Disable [3:3] read-write ADD Head Descriptor Loaded Interrupt Disable [4:4] read-write DONE End of List Interrupt Disable [5:5] read-write OVR Overflow Interrupt Disable [6:6] read-write OVR2IER Overlay 2 Interrupt Enable Register 0x24C 0x20 write-only DMA End of DMA Transfer Interrupt Enable [2:2] read-write DSCR Descriptor Loaded Interrupt Enable [3:3] read-write ADD Head Descriptor Loaded Interrupt Enable [4:4] read-write DONE End of List Interrupt Enable [5:5] read-write OVR Overflow Interrupt Enable [6:6] read-write OVR2IMR Overlay 2 Interrupt Mask Register 0x254 0x20 read-only DMA End of DMA Transfer Interrupt Mask [2:2] read-write DSCR Descriptor Loaded Interrupt Mask [3:3] read-write ADD Head Descriptor Loaded Interrupt Mask [4:4] read-write DONE End of List Interrupt Mask [5:5] read-write OVR Overflow Interrupt Mask [6:6] read-write OVR2ISR Overlay 2 Interrupt Status Register 0x258 0x20 read-only DMA End of DMA Transfer [2:2] read-write DSCR DMA Descriptor Loaded [3:3] read-write ADD Head Descriptor Loaded [4:4] read-write DONE End of List Detected [5:5] read-write OVR Overflow Detected [6:6] read-write OVR2NEXT Overlay 2 DMA Next Register 0x268 0x20 read-write NEXT DMA Descriptor Next Address [31:0] read-write 0 4294967295 PPADDR Post Processing Address Register 0x560 0x20 read-write ADDR DMA Transfer Start Address [31:0] read-write 0 4294967295 PPCFG0 Post Processing Configuration Register 0 0x56C 0x20 read-write SIF Source Interface [0:0] read-write BLEN AHB Burst Length [5:4] read-write 0 3 DLBO Defined Length Burst Only For Channel Bus Transaction [8:8] read-write PPCFG1 Post Processing Configuration Register 1 0x570 0x20 read-write PPMODE Post Processing Output Format Selection [2:0] read-write true PPMODE_RGB_16BPP RGB 16 bpp 0 PPMODE_RGB_24BPP_PACKED RGB 24 bpp PACKED 1 PPMODE_RGB_24BPP_UNPACKED RGB 24 bpp UNPACKED 2 PPMODE_YCBCR_422_MODE0 YCbCr 422 16 bpp (Mode 0) 3 PPMODE_YCBCR_422_MODE1 YCbCr 422 16 bpp (Mode 1) 4 PPMODE_YCBCR_422_MODE2 YCbCr 422 16 bpp (Mode 2) 5 PPMODE_YCBCR_422_MODE3 YCbCr 422 16 bpp (Mode 3) 6 ITUBT601 Color Space Conversion Luminance [4:4] read-write PPCFG2 Post Processing Configuration Register 2 0x574 0x20 read-write XSTRIDE Horizontal Stride [31:0] read-write 0 4294967295 PPCFG3 Post Processing Configuration Register 3 0x578 0x20 read-write CSCYR Color Space Conversion R coefficient for Luminance component, signed format, step set to 1/1024 [9:0] read-write 0 1023 CSCYG Color Space Conversion G coefficient for Luminance component, signed format, step set to 1/512 [19:10] read-write 0 1023 CSCYB Color Space Conversion B coefficient for Luminance component, signed format, step set to 1/1024 [29:20] read-write 0 1023 CSCYOFF Color Space Conversion Luminance Offset [30:30] read-write PPCFG4 Post Processing Configuration Register 4 0x57C 0x20 read-write CSCUR Color Space Conversion R coefficient for Chrominance B component, signed format. (step 1/1024) [9:0] read-write 0 1023 CSCUG Color Space Conversion G coefficient for Chrominance B component, signed format. (step 1/512) [19:10] read-write 0 1023 CSCUB Color Space Conversion B coefficient for Chrominance B component, signed format. (step 1/512) [29:20] read-write 0 1023 CSCUOFF Color Space Conversion Chrominance B Offset [30:30] read-write PPCFG5 Post Processing Configuration Register 5 0x580 0x20 read-write CSCVR Color Space Conversion R coefficient for Chrominance R component, signed format. (step 1/1024) [9:0] read-write 0 1023 CSCVG Color Space Conversion G coefficient for Chrominance R component, signed format. (step 1/512) [19:10] read-write 0 1023 CSCVB Color Space Conversion B coefficient for Chrominance R component, signed format. (step 1/1024) [29:20] read-write 0 1023 CSCVOFF Color Space Conversion Chrominance R Offset [30:30] read-write PPCHDR Post Processing Channel Disable Register 0x544 0x20 write-only CHDIS Channel Disable [0:0] read-write CHRST Channel Reset [8:8] read-write PPCHER Post Processing Channel Enable Register 0x540 0x20 write-only CHEN Channel Enable [0:0] read-write UPDATEEN Update Overlay Attributes Enable [1:1] read-write A2QEN Add To Queue Enable [2:2] read-write PPCHSR Post Processing Channel Status Register 0x548 0x20 read-only CHSR Channel Status [0:0] read-write UPDATESR Update Overlay Attributes In Progress Status [1:1] read-write A2QSR Add To Queue Status [2:2] read-write PPCTRL Post Processing Control Register 0x564 0x20 read-write DFETCH Transfer Descriptor Fetch Enable [0:0] read-write DMAIEN End of DMA Transfer Interrupt Enable [2:2] read-write DSCRIEN Descriptor Loaded Interrupt Enable [3:3] read-write ADDIEN Add Head Descriptor to Queue Interrupt Enable [4:4] read-write DONEIEN End of List Interrupt Enable [5:5] read-write PPHEAD Post Processing Head Register 0x55C 0x20 read-write HEAD DMA Head Pointer [31:2] read-write 0 1073741823 PPIDR Post Processing Interrupt Disable Register 0x550 0x20 write-only DMA End of DMA Transfer Interrupt Disable [2:2] read-write DSCR Descriptor Loaded Interrupt Disable [3:3] read-write ADD Head Descriptor Loaded Interrupt Disable [4:4] read-write DONE End of List Interrupt Disable [5:5] read-write PPIER Post Processing Interrupt Enable Register 0x54C 0x20 write-only DMA End of DMA Transfer Interrupt Enable [2:2] read-write DSCR Descriptor Loaded Interrupt Enable [3:3] read-write ADD Head Descriptor Loaded Interrupt Enable [4:4] read-write DONE End of List Interrupt Enable [5:5] read-write PPIMR Post Processing Interrupt Mask Register 0x554 0x20 read-only DMA End of DMA Transfer Interrupt Mask [2:2] read-write DSCR Descriptor Loaded Interrupt Mask [3:3] read-write ADD Head Descriptor Loaded Interrupt Mask [4:4] read-write DONE End of List Interrupt Mask [5:5] read-write PPISR Post Processing Interrupt Status Register 0x558 0x20 read-only DMA End of DMA Transfer [2:2] read-write DSCR DMA Descriptor Loaded [3:3] read-write ADD Head Descriptor Loaded [4:4] read-write DONE End of List Detected [5:5] read-write PPNEXT Post Processing Next Register 0x568 0x20 read-write NEXT DMA Descriptor Next Address [31:0] read-write 0 4294967295 MATRIX0 AHB Bus Matrix 0xF0018000 0x0 0x4 registers 0x40 0x4 registers 0x150 0x14 registers 0x1E4 0x8 registers 0x200 0x4 registers 0x240 0x4 registers 0x284 0x4 registers 0x2C0 0x4 registers MCFG Master Configuration Register 0x0 0x20 read-write ULBT Undefined Length Burst Type [2:0] read-write true UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence. 1 _4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats. 2 _8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats. 3 _16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats. 4 _32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats. 5 _64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats. 6 _128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 7 MEAR Master 0 Error Address Register 0x160 0x20 read-only ERRADD Master Error Address [31:0] read-write 0 4294967295 MEIDR Master Error Interrupt Disable Register 0x154 0x20 write-only MERR0 Master 0 Access Error [0:0] read-write MERR1 Master 1 Access Error [1:1] read-write MERR2 Master 2 Access Error [2:2] read-write MERR3 Master 3 Access Error [3:3] read-write MERR4 Master 4 Access Error [4:4] read-write MERR5 Master 5 Access Error [5:5] read-write MERR6 Master 6 Access Error [6:6] read-write MERR7 Master 7 Access Error [7:7] read-write MERR8 Master 8 Access Error [8:8] read-write MERR9 Master 9 Access Error [9:9] read-write MERR10 Master 10 Access Error [10:10] read-write MERR11 Master 11 Access Error [11:11] read-write MEIER Master Error Interrupt Enable Register 0x150 0x20 write-only MERR0 Master 0 Access Error [0:0] read-write MERR1 Master 1 Access Error [1:1] read-write MERR2 Master 2 Access Error [2:2] read-write MERR3 Master 3 Access Error [3:3] read-write MERR4 Master 4 Access Error [4:4] read-write MERR5 Master 5 Access Error [5:5] read-write MERR6 Master 6 Access Error [6:6] read-write MERR7 Master 7 Access Error [7:7] read-write MERR8 Master 8 Access Error [8:8] read-write MERR9 Master 9 Access Error [9:9] read-write MERR10 Master 10 Access Error [10:10] read-write MERR11 Master 11 Access Error [11:11] read-write MEIMR Master Error Interrupt Mask Register 0x158 0x20 read-only MERR0 Master 0 Access Error [0:0] read-write MERR1 Master 1 Access Error [1:1] read-write MERR2 Master 2 Access Error [2:2] read-write MERR3 Master 3 Access Error [3:3] read-write MERR4 Master 4 Access Error [4:4] read-write MERR5 Master 5 Access Error [5:5] read-write MERR6 Master 6 Access Error [6:6] read-write MERR7 Master 7 Access Error [7:7] read-write MERR8 Master 8 Access Error [8:8] read-write MERR9 Master 9 Access Error [9:9] read-write MERR10 Master 10 Access Error [10:10] read-write MERR11 Master 11 Access Error [11:11] read-write MESR Master Error Status Register 0x15C 0x20 read-only MERR0 Master 0 Access Error [0:0] read-write MERR1 Master 1 Access Error [1:1] read-write MERR2 Master 2 Access Error [2:2] read-write MERR3 Master 3 Access Error [3:3] read-write MERR4 Master 4 Access Error [4:4] read-write MERR5 Master 5 Access Error [5:5] read-write MERR6 Master 6 Access Error [6:6] read-write MERR7 Master 7 Access Error [7:7] read-write MERR8 Master 8 Access Error [8:8] read-write MERR9 Master 9 Access Error [9:9] read-write MERR10 Master 10 Access Error [10:10] read-write MERR11 Master 11 Access Error [11:11] read-write SASSR Security Areas Split Slave 0 Register 0x240 0x20 read-write SASPLIT0 Security Areas Split for HSELx Security Region [3:0] read-write 0 15 SASPLIT1 Security Areas Split for HSELx Security Region [7:4] read-write 0 15 SASPLIT2 Security Areas Split for HSELx Security Region [11:8] read-write 0 15 SASPLIT3 Security Areas Split for HSELx Security Region [15:12] read-write 0 15 SASPLIT4 Security Areas Split for HSELx Security Region [19:16] read-write 0 15 SASPLIT5 Security Areas Split for HSELx Security Region [23:20] read-write 0 15 SASPLIT6 Security Areas Split for HSELx Security Region [27:24] read-write 0 15 SASPLIT7 Security Areas Split for HSELx Security Region [31:28] read-write 0 15 SCFG Slave Configuration Register 0x40 0x20 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters [8:0] read-write 0 511 DEFMSTR_TYPE Default Master Type [17:16] read-write true NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 2 FIXED_DEFMSTR Fixed Default Master [21:18] read-write 0 15 SPSELR Security Peripheral Select 1 Register 0x2C0 0x20 read-write NSECP0 Non-secured Peripheral [0:0] read-write NSECP1 Non-secured Peripheral [1:1] read-write NSECP2 Non-secured Peripheral [2:2] read-write NSECP3 Non-secured Peripheral [3:3] read-write NSECP4 Non-secured Peripheral [4:4] read-write NSECP5 Non-secured Peripheral [5:5] read-write NSECP6 Non-secured Peripheral [6:6] read-write NSECP7 Non-secured Peripheral [7:7] read-write NSECP8 Non-secured Peripheral [8:8] read-write NSECP9 Non-secured Peripheral [9:9] read-write NSECP10 Non-secured Peripheral [10:10] read-write NSECP11 Non-secured Peripheral [11:11] read-write NSECP12 Non-secured Peripheral [12:12] read-write NSECP13 Non-secured Peripheral [13:13] read-write NSECP14 Non-secured Peripheral [14:14] read-write NSECP15 Non-secured Peripheral [15:15] read-write NSECP16 Non-secured Peripheral [16:16] read-write NSECP17 Non-secured Peripheral [17:17] read-write NSECP18 Non-secured Peripheral [18:18] read-write NSECP19 Non-secured Peripheral [19:19] read-write NSECP20 Non-secured Peripheral [20:20] read-write NSECP21 Non-secured Peripheral [21:21] read-write NSECP22 Non-secured Peripheral [22:22] read-write NSECP23 Non-secured Peripheral [23:23] read-write NSECP24 Non-secured Peripheral [24:24] read-write NSECP25 Non-secured Peripheral [25:25] read-write NSECP26 Non-secured Peripheral [26:26] read-write NSECP27 Non-secured Peripheral [27:27] read-write NSECP28 Non-secured Peripheral [28:28] read-write NSECP29 Non-secured Peripheral [29:29] read-write NSECP30 Non-secured Peripheral [30:30] read-write NSECP31 Non-secured Peripheral [31:31] read-write SRTSR Security Region Top Slave 1 Register 0x284 0x20 read-write SRTOP0 HSELx Security Region Top [3:0] read-write 0 15 SRTOP1 HSELx Security Region Top [7:4] read-write 0 15 SRTOP2 HSELx Security Region Top [11:8] read-write 0 15 SRTOP3 HSELx Security Region Top [15:12] read-write 0 15 SRTOP4 HSELx Security Region Top [19:16] read-write 0 15 SRTOP5 HSELx Security Region Top [23:20] read-write 0 15 SRTOP6 HSELx Security Region Top [27:24] read-write 0 15 SRTOP7 HSELx Security Region Top [31:28] read-write 0 15 SSR Security Slave 0 Register 0x200 0x20 read-write LANSECH0 Low Area Non-secured in HSELx Security Region [0:0] read-write LANSECH1 Low Area Non-secured in HSELx Security Region [1:1] read-write LANSECH2 Low Area Non-secured in HSELx Security Region [2:2] read-write LANSECH3 Low Area Non-secured in HSELx Security Region [3:3] read-write LANSECH4 Low Area Non-secured in HSELx Security Region [4:4] read-write LANSECH5 Low Area Non-secured in HSELx Security Region [5:5] read-write LANSECH6 Low Area Non-secured in HSELx Security Region [6:6] read-write LANSECH7 Low Area Non-secured in HSELx Security Region [7:7] read-write RDNSECH0 Read Non-secured for HSELx Security Region [8:8] read-write RDNSECH1 Read Non-secured for HSELx Security Region [9:9] read-write RDNSECH2 Read Non-secured for HSELx Security Region [10:10] read-write RDNSECH3 Read Non-secured for HSELx Security Region [11:11] read-write RDNSECH4 Read Non-secured for HSELx Security Region [12:12] read-write RDNSECH5 Read Non-secured for HSELx Security Region [13:13] read-write RDNSECH6 Read Non-secured for HSELx Security Region [14:14] read-write RDNSECH7 Read Non-secured for HSELx Security Region [15:15] read-write WRNSECH0 Write Non-secured for HSELx Security Region [16:16] read-write WRNSECH1 Write Non-secured for HSELx Security Region [17:17] read-write WRNSECH2 Write Non-secured for HSELx Security Region [18:18] read-write WRNSECH3 Write Non-secured for HSELx Security Region [19:19] read-write WRNSECH4 Write Non-secured for HSELx Security Region [20:20] read-write WRNSECH5 Write Non-secured for HSELx Security Region [21:21] read-write WRNSECH6 Write Non-secured for HSELx Security Region [22:22] read-write WRNSECH7 Write Non-secured for HSELx Security Region [23:23] read-write WPMR Write Protection Mode Register 0x1E4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key (Write-only) [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5062996 WPSR Write Protection Status Register 0x1E8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [23:8] read-write 0 65535 MATRIX1 AHB Bus Matrix 0xFC03C000 MCAN0 Controller Area Network 0xF8054000 0x0 0x30 registers 0x40 0xC registers 0x50 0x10 registers 0x80 0xC registers 0x90 0x58 registers 0xF0 0xC registers CCCR CC Control Register 0x18 0x20 read-write INIT Initialization (read/write) [0:0] read-write true DISABLED Normal operation. 0 ENABLED Initialization is started. 1 CCE Configuration Change Enable (read/write, write protection) [1:1] read-write true PROTECTED The processor has no write access to the protected configuration registers. 0 CONFIGURABLE The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). 1 ASM Restricted Operation Mode (read/write, write protection against '1') [2:2] read-write true NORMAL Normal CAN operation. 0 RESTRICTED Restricted Operation mode active. 1 CSA Clock Stop Acknowledge (read-only) [3:3] read-write CSR Clock Stop Request (read/write) [4:4] read-write true NO_CLOCK_STOP No clock stop is requested. 0 CLOCK_STOP Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. 1 MON Bus Monitoring Mode (read/write, write protection against '1') [5:5] read-write true DISABLED Bus Monitoring mode is disabled. 0 ENABLED Bus Monitoring mode is enabled. 1 DAR Disable Automatic Retransmission (read/write, write protection) [6:6] read-write true AUTO_RETX Automatic retransmission of messages not transmitted successfully enabled. 0 NO_AUTO_RETX Automatic retransmission disabled. 1 TEST Test Mode Enable (read/write, write protection against '1') [7:7] read-write true DISABLED Normal operation, MCAN_TEST register holds reset values. 0 ENABLED Test mode, write access to MCAN_TEST register enabled. 1 FDOE CAN FD Operation Enable (read/write, write protection) [8:8] read-write true DISABLED FD operation disabled. 0 ENABLED FD operation enabled. 1 BRSE Bit Rate Switching Enable (read/write, write protection) [9:9] read-write true DISABLED Bit rate switching for transmissions disabled. 0 ENABLED Bit rate switching for transmissions enabled. 1 PXHD Protocol Exception Event Handling (read/write, write protection) [12:12] read-write EFBI Edge Filtering during Bus Integration (read/write, write protection) [13:13] read-write TXP Transmit Pause (read/write, write protection) [14:14] read-write CREL Core Release Register 0x0 0x20 read-only DAY Timestamp Day [7:0] read-write 0 255 MON Timestamp Month [15:8] read-write 0 255 YEAR Timestamp Year [19:16] read-write 0 15 SUBSTEP Sub-step of Core Release [23:20] read-write 0 15 STEP Step of Core Release [27:24] read-write 0 15 REL Core Release [31:28] read-write 0 15 CUST Customer Register 0x8 0x20 read-write CSV Customer-specific Value [31:0] read-write 0 4294967295 DBTP Data Bit Timing and Prescaler Register 0xC 0x20 read-write DSJW Data (Re) Synchronization Jump Width [2:0] read-write 0 7 DTSEG2 Data Time Segment After Sample Point [7:4] read-write 0 15 DTSEG1 Data Time Segment Before Sample Point [12:8] read-write 0 31 DBRP Data Bit Rate Prescaler [20:16] read-write 0 31 TDC Transmitter Delay Compensation [23:23] read-write true DISABLED Transmitter Delay Compensation disabled. 0 ENABLED Transmitter Delay Compensation enabled. 1 ECR Error Counter Register 0x40 0x20 read-only TEC Transmit Error Counter [7:0] read-write 0 255 REC Receive Error Counter [14:8] read-write 0 127 RP Receive Error Passive [15:15] read-write CEL CAN Error Logging (cleared on read) [23:16] read-write 0 255 ENDN Endian Register 0x4 0x20 read-only ETV Endianness Test Value [31:0] read-write 0 4294967295 GFC Global Filter Configuration Register 0x80 0x20 read-write RRFE Reject Remote Frames Extended [0:0] read-write true FILTER Filter remote frames with 29-bit extended IDs. 0 REJECT Reject all remote frames with 29-bit extended IDs. 1 RRFS Reject Remote Frames Standard [1:1] read-write true FILTER Filter remote frames with 11-bit standard IDs. 0 REJECT Reject all remote frames with 11-bit standard IDs. 1 ANFE Accept Non-matching Frames Extended [3:2] read-write true RX_FIFO_0 Accept in Rx FIFO 0 0 RX_FIFO_1 Accept in Rx FIFO 1 1 ANFS Accept Non-matching Frames Standard [5:4] read-write true RX_FIFO_0 Accept in Rx FIFO 0 0 RX_FIFO_1 Accept in Rx FIFO 1 1 HPMS High Priority Message Status Register 0x94 0x20 read-only BIDX Buffer Index [5:0] read-write 0 63 MSI Message Storage Indicator [7:6] read-write true NO_FIFO_SEL No FIFO selected. 0 LOST FIFO message lost. 1 FIFO_0 Message stored in FIFO 0. 2 FIFO_1 Message stored in FIFO 1. 3 FIDX Filter Index [14:8] read-write 0 127 FLST Filter List [15:15] read-write IE Interrupt Enable Register 0x54 0x20 read-write RF0NE Receive FIFO 0 New Message Interrupt Enable [0:0] read-write RF0WE Receive FIFO 0 Watermark Reached Interrupt Enable [1:1] read-write RF0FE Receive FIFO 0 Full Interrupt Enable [2:2] read-write RF0LE Receive FIFO 0 Message Lost Interrupt Enable [3:3] read-write RF1NE Receive FIFO 1 New Message Interrupt Enable [4:4] read-write RF1WE Receive FIFO 1 Watermark Reached Interrupt Enable [5:5] read-write RF1FE Receive FIFO 1 Full Interrupt Enable [6:6] read-write RF1LE Receive FIFO 1 Message Lost Interrupt Enable [7:7] read-write HPME High Priority Message Interrupt Enable [8:8] read-write TCE Transmission Completed Interrupt Enable [9:9] read-write TCFE Transmission Cancellation Finished Interrupt Enable [10:10] read-write TFEE Tx FIFO Empty Interrupt Enable [11:11] read-write TEFNE Tx Event FIFO New Entry Interrupt Enable [12:12] read-write TEFWE Tx Event FIFO Watermark Reached Interrupt Enable [13:13] read-write TEFFE Tx Event FIFO Full Interrupt Enable [14:14] read-write TEFLE Tx Event FIFO Event Lost Interrupt Enable [15:15] read-write TSWE Timestamp Wraparound Interrupt Enable [16:16] read-write MRAFE Message RAM Access Failure Interrupt Enable [17:17] read-write TOOE Timeout Occurred Interrupt Enable [18:18] read-write DRXE Message stored to Dedicated Receive Buffer Interrupt Enable [19:19] read-write BECE Bit Error Corrected Interrupt Enable [20:20] read-write BEUE Bit Error Uncorrected Interrupt Enable [21:21] read-write ELOE Error Logging Overflow Interrupt Enable [22:22] read-write EPE Error Passive Interrupt Enable [23:23] read-write EWE Warning Status Interrupt Enable [24:24] read-write BOE Bus_Off Status Interrupt Enable [25:25] read-write WDIE Watchdog Interrupt Enable [26:26] read-write PEAE Protocol Error in Arbitration Phase Enable [27:27] read-write PEDE Protocol Error in Data Phase Enable [28:28] read-write ARAE Access to Reserved Address Enable [29:29] read-write ILE Interrupt Line Enable Register 0x5C 0x20 read-write EINT0 Enable Interrupt Line 0 [0:0] read-write EINT1 Enable Interrupt Line 1 [1:1] read-write ILS Interrupt Line Select Register 0x58 0x20 read-write RF0NL Receive FIFO 0 New Message Interrupt Line [0:0] read-write RF0WL Receive FIFO 0 Watermark Reached Interrupt Line [1:1] read-write RF0FL Receive FIFO 0 Full Interrupt Line [2:2] read-write RF0LL Receive FIFO 0 Message Lost Interrupt Line [3:3] read-write RF1NL Receive FIFO 1 New Message Interrupt Line [4:4] read-write RF1WL Receive FIFO 1 Watermark Reached Interrupt Line [5:5] read-write RF1FL Receive FIFO 1 Full Interrupt Line [6:6] read-write RF1LL Receive FIFO 1 Message Lost Interrupt Line [7:7] read-write HPML High Priority Message Interrupt Line [8:8] read-write TCL Transmission Completed Interrupt Line [9:9] read-write TCFL Transmission Cancellation Finished Interrupt Line [10:10] read-write TFEL Tx FIFO Empty Interrupt Line [11:11] read-write TEFNL Tx Event FIFO New Entry Interrupt Line [12:12] read-write TEFWL Tx Event FIFO Watermark Reached Interrupt Line [13:13] read-write TEFFL Tx Event FIFO Full Interrupt Line [14:14] read-write TEFLL Tx Event FIFO Event Lost Interrupt Line [15:15] read-write TSWL Timestamp Wraparound Interrupt Line [16:16] read-write MRAFL Message RAM Access Failure Interrupt Line [17:17] read-write TOOL Timeout Occurred Interrupt Line [18:18] read-write DRXL Message stored to Dedicated Receive Buffer Interrupt Line [19:19] read-write BECL Bit Error Corrected Interrupt Line [20:20] read-write BEUL Bit Error Uncorrected Interrupt Line [21:21] read-write ELOL Error Logging Overflow Interrupt Line [22:22] read-write EPL Error Passive Interrupt Line [23:23] read-write EWL Warning Status Interrupt Line [24:24] read-write BOL Bus_Off Status Interrupt Line [25:25] read-write WDIL Watchdog Interrupt Line [26:26] read-write PEAL Protocol Error in Arbitration Phase Line [27:27] read-write PEDL Protocol Error in Data Phase Line [28:28] read-write ARAL Access to Reserved Address Line [29:29] read-write IR Interrupt Register 0x50 0x20 read-write RF0N Receive FIFO 0 New Message [0:0] read-write RF0W Receive FIFO 0 Watermark Reached [1:1] read-write RF0F Receive FIFO 0 Full [2:2] read-write RF0L Receive FIFO 0 Message Lost [3:3] read-write RF1N Receive FIFO 1 New Message [4:4] read-write RF1W Receive FIFO 1 Watermark Reached [5:5] read-write RF1F Receive FIFO 1 Full [6:6] read-write RF1L Receive FIFO 1 Message Lost [7:7] read-write HPM High Priority Message [8:8] read-write TC Transmission Completed [9:9] read-write TCF Transmission Cancellation Finished [10:10] read-write TFE Tx FIFO Empty [11:11] read-write TEFN Tx Event FIFO New Entry [12:12] read-write TEFW Tx Event FIFO Watermark Reached [13:13] read-write TEFF Tx Event FIFO Full [14:14] read-write TEFL Tx Event FIFO Element Lost [15:15] read-write TSW Timestamp Wraparound [16:16] read-write MRAF Message RAM Access Failure [17:17] read-write TOO Timeout Occurred [18:18] read-write DRX Message stored to Dedicated Receive Buffer [19:19] read-write BEC Bit Error Corrected [20:20] read-write BEU Bit Error Uncorrected [21:21] read-write ELO Error Logging Overflow [22:22] read-write EP Error Passive [23:23] read-write EW Warning Status [24:24] read-write BO Bus_Off Status [25:25] read-write WDI Watchdog Interrupt [26:26] read-write PEA Protocol Error in Arbitration Phase [27:27] read-write PED Protocol Error in Data Phase [28:28] read-write ARA Access to Reserved Address [29:29] read-write NBTP Nominal Bit Timing and Prescaler Register 0x1C 0x20 read-write NTSEG2 Nominal Time Segment After Sample Point [6:0] read-write 0 127 NTSEG1 Nominal Time Segment Before Sample Point [15:8] read-write 0 255 NBRP Nominal Bit Rate Prescaler [24:16] read-write 0 511 NSJW Nominal (Re) Synchronization Jump Width [31:25] read-write 0 127 NDAT1 New Data 1 Register 0x98 0x20 read-write ND0 New Data [0:0] read-write ND1 New Data [1:1] read-write ND2 New Data [2:2] read-write ND3 New Data [3:3] read-write ND4 New Data [4:4] read-write ND5 New Data [5:5] read-write ND6 New Data [6:6] read-write ND7 New Data [7:7] read-write ND8 New Data [8:8] read-write ND9 New Data [9:9] read-write ND10 New Data [10:10] read-write ND11 New Data [11:11] read-write ND12 New Data [12:12] read-write ND13 New Data [13:13] read-write ND14 New Data [14:14] read-write ND15 New Data [15:15] read-write ND16 New Data [16:16] read-write ND17 New Data [17:17] read-write ND18 New Data [18:18] read-write ND19 New Data [19:19] read-write ND20 New Data [20:20] read-write ND21 New Data [21:21] read-write ND22 New Data [22:22] read-write ND23 New Data [23:23] read-write ND24 New Data [24:24] read-write ND25 New Data [25:25] read-write ND26 New Data [26:26] read-write ND27 New Data [27:27] read-write ND28 New Data [28:28] read-write ND29 New Data [29:29] read-write ND30 New Data [30:30] read-write ND31 New Data [31:31] read-write NDAT2 New Data 2 Register 0x9C 0x20 read-write ND32 New Data [0:0] read-write ND33 New Data [1:1] read-write ND34 New Data [2:2] read-write ND35 New Data [3:3] read-write ND36 New Data [4:4] read-write ND37 New Data [5:5] read-write ND38 New Data [6:6] read-write ND39 New Data [7:7] read-write ND40 New Data [8:8] read-write ND41 New Data [9:9] read-write ND42 New Data [10:10] read-write ND43 New Data [11:11] read-write ND44 New Data [12:12] read-write ND45 New Data [13:13] read-write ND46 New Data [14:14] read-write ND47 New Data [15:15] read-write ND48 New Data [16:16] read-write ND49 New Data [17:17] read-write ND50 New Data [18:18] read-write ND51 New Data [19:19] read-write ND52 New Data [20:20] read-write ND53 New Data [21:21] read-write ND54 New Data [22:22] read-write ND55 New Data [23:23] read-write ND56 New Data [24:24] read-write ND57 New Data [25:25] read-write ND58 New Data [26:26] read-write ND59 New Data [27:27] read-write ND60 New Data [28:28] read-write ND61 New Data [29:29] read-write ND62 New Data [30:30] read-write ND63 New Data [31:31] read-write PSR Protocol Status Register 0x44 0x20 read-only LEC Last Error Code (set to 111 on read) [2:0] read-write true NO_ERROR No error occurred since LEC has been reset by successful reception or transmission. 0 STUFF_ERROR More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 1 FORM_ERROR A fixed format part of a received frame has the wrong format. 2 ACK_ERROR The message transmitted by the MCAN was not acknowledged by another node. 3 BIT1_ERROR During transmission of a message (with the exception of the arbitration field), the device tried to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 4 BIT0_ERROR During transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device tried to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 5 CRC_ERROR The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match the CRC calculated from the received data. 6 NO_CHANGE Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. 7 ACT Activity [4:3] read-write true SYNCHRONIZING Node is synchronizing on CAN communication 0 IDLE Node is neither receiver nor transmitter 1 RECEIVER Node is operating as receiver 2 TRANSMITTER Node is operating as transmitter 3 EP Error Passive [5:5] read-write EW Warning Status [6:6] read-write BO Bus_Off Status [7:7] read-write DLEC Data Phase Last Error Code (set to 111 on read) [10:8] read-write 0 7 RESI ESI Flag of Last Received CAN FD Message (cleared on read) [11:11] read-write RBRS BRS Flag of Last Received CAN FD Message (cleared on read) [12:12] read-write RFDF Received a CAN FD Message (cleared on read) [13:13] read-write PXE Protocol Exception Event (cleared on read) [14:14] read-write TDCV Transmitter Delay Compensation Value [22:16] read-write 0 127 RWD RAM Watchdog Register 0x14 0x20 read-write WDC Watchdog Configuration (read/write) [7:0] read-write 0 255 WDV Watchdog Value (read-only) [15:8] read-write 0 255 RXBC Receive Rx Buffer Configuration Register 0xAC 0x20 read-write RBSA Receive Buffer Start Address [15:2] read-write 0 16383 RXESC Receive Buffer / FIFO Element Size Configuration Register 0xBC 0x20 read-write F0DS Receive FIFO 0 Data Field Size [2:0] read-write true _8_BYTE 8-byte data field 0 _12_BYTE 12-byte data field 1 _16_BYTE 16-byte data field 2 _20_BYTE 20-byte data field 3 _24_BYTE 24-byte data field 4 _32_BYTE 32-byte data field 5 _48_BYTE 48-byte data field 6 _64_BYTE 64-byte data field 7 F1DS Receive FIFO 1 Data Field Size [6:4] read-write true _8_BYTE 8-byte data field 0 _12_BYTE 12-byte data field 1 _16_BYTE 16-byte data field 2 _20_BYTE 20-byte data field 3 _24_BYTE 24-byte data field 4 _32_BYTE 32-byte data field 5 _48_BYTE 48-byte data field 6 _64_BYTE 64-byte data field 7 RBDS Receive Buffer Data Field Size [10:8] read-write true _8_BYTE 8-byte data field 0 _12_BYTE 12-byte data field 1 _16_BYTE 16-byte data field 2 _20_BYTE 20-byte data field 3 _24_BYTE 24-byte data field 4 _32_BYTE 32-byte data field 5 _48_BYTE 48-byte data field 6 _64_BYTE 64-byte data field 7 RXF0A Receive FIFO 0 Acknowledge Register 0xA8 0x20 read-write F0AI Receive FIFO 0 Acknowledge Index [5:0] read-write 0 63 RXF0C Receive FIFO 0 Configuration Register 0xA0 0x20 read-write F0SA Receive FIFO 0 Start Address [15:2] read-write 0 16383 F0S Receive FIFO 0 Start Address [22:16] read-write 0 127 F0WM Receive FIFO 0 Watermark [30:24] read-write 0 127 F0OM FIFO 0 Operation Mode [31:31] read-write RXF0S Receive FIFO 0 Status Register 0xA4 0x20 read-only F0FL Receive FIFO 0 Fill Level [6:0] read-write 0 127 F0GI Receive FIFO 0 Get Index [13:8] read-write 0 63 F0PI Receive FIFO 0 Put Index [21:16] read-write 0 63 F0F Receive FIFO 0 Fill Level [24:24] read-write RF0L Receive FIFO 0 Message Lost [25:25] read-write RXF1A Receive FIFO 1 Acknowledge Register 0xB8 0x20 read-write F1AI Receive FIFO 1 Acknowledge Index [5:0] read-write 0 63 RXF1C Receive FIFO 1 Configuration Register 0xB0 0x20 read-write F1SA Receive FIFO 1 Start Address [15:2] read-write 0 16383 F1S Receive FIFO 1 Start Address [22:16] read-write 0 127 F1WM Receive FIFO 1 Watermark [30:24] read-write 0 127 F1OM FIFO 1 Operation Mode [31:31] read-write RXF1S Receive FIFO 1 Status Register 0xB4 0x20 read-only F1FL Receive FIFO 1 Fill Level [6:0] read-write 0 127 F1GI Receive FIFO 1 Get Index [13:8] read-write 0 63 F1PI Receive FIFO 1 Put Index [21:16] read-write 0 63 F1F Receive FIFO 1 Fill Level [24:24] read-write RF1L Receive FIFO 1 Message Lost [25:25] read-write DMS Debug Message Status [31:30] read-write true IDLE Idle state, wait for reception of debug messages, DMA request is cleared. 0 MSG_A Debug message A received. 1 MSG_AB Debug messages A, B received. 2 MSG_ABC Debug messages A, B, C received, DMA request is set. 3 SIDFC Standard ID Filter Configuration Register 0x84 0x20 read-write FLSSA Filter List Standard Start Address [15:2] read-write 0 16383 LSS List Size Standard [23:16] read-write 0 255 TDCR Transmit Delay Compensation Register 0x48 0x20 read-write TDCF Transmitter Delay Compensation Filter [6:0] read-write 0 127 TDCO Transmitter Delay Compensation Offset [14:8] read-write 0 127 TEST Test Register 0x10 0x20 read-write LBCK Loop Back Mode (read/write) [4:4] read-write true DISABLED Reset value. Loop Back mode is disabled. 0 ENABLED Loop Back mode is enabled (see Section 6.1.9). 1 TX Control of Transmit Pin (read/write) [6:5] read-write true RESET Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. 0 SAMPLE_POINT_MONITORING Sample Point can be monitored at pin CANTX. 1 DOMINANT Dominant ('0') level at pin CANTX. 2 RECESSIVE Recessive ('1') at pin CANTX. 3 RX Receive Pin (read-only) [7:7] read-write TOCC Timeout Counter Configuration Register 0x28 0x20 read-write ETOC Enable Timeout Counter [0:0] read-write true NO_TIMEOUT Timeout Counter disabled. 0 TOS_CONTROLLED Timeout Counter enabled. 1 TOS Timeout Select [2:1] read-write true CONTINUOUS Continuous operation 0 TX_EV_TIMEOUT Timeout controlled by Tx Event FIFO 1 RX0_EV_TIMEOUT Timeout controlled by Receive FIFO 0 2 RX1_EV_TIMEOUT Timeout controlled by Receive FIFO 1 3 TOP Timeout Period [31:16] read-write 0 65535 TOCV Timeout Counter Value Register 0x2C 0x20 read-write TOC Timeout Counter (cleared on write) [15:0] read-write 0 65535 TSCC Timestamp Counter Configuration Register 0x20 0x20 read-write TSS Timestamp Select [1:0] read-write true ALWAYS_0 Timestamp counter value always 0x0000 0 TCP_INC Timestamp counter value incremented according to TCP 1 EXT_TIMESTAMP External timestamp counter value used 2 TCP Timestamp Counter Prescaler [19:16] read-write 0 15 TSCV Timestamp Counter Value Register 0x24 0x20 read-write TSC Timestamp Counter (cleared on write) [15:0] read-write 0 65535 TXBAR Transmit Buffer Add Request Register 0xD0 0x20 read-write AR0 Add Request for Transmit Buffer 0 [0:0] read-write AR1 Add Request for Transmit Buffer 1 [1:1] read-write AR2 Add Request for Transmit Buffer 2 [2:2] read-write AR3 Add Request for Transmit Buffer 3 [3:3] read-write AR4 Add Request for Transmit Buffer 4 [4:4] read-write AR5 Add Request for Transmit Buffer 5 [5:5] read-write AR6 Add Request for Transmit Buffer 6 [6:6] read-write AR7 Add Request for Transmit Buffer 7 [7:7] read-write AR8 Add Request for Transmit Buffer 8 [8:8] read-write AR9 Add Request for Transmit Buffer 9 [9:9] read-write AR10 Add Request for Transmit Buffer 10 [10:10] read-write AR11 Add Request for Transmit Buffer 11 [11:11] read-write AR12 Add Request for Transmit Buffer 12 [12:12] read-write AR13 Add Request for Transmit Buffer 13 [13:13] read-write AR14 Add Request for Transmit Buffer 14 [14:14] read-write AR15 Add Request for Transmit Buffer 15 [15:15] read-write AR16 Add Request for Transmit Buffer 16 [16:16] read-write AR17 Add Request for Transmit Buffer 17 [17:17] read-write AR18 Add Request for Transmit Buffer 18 [18:18] read-write AR19 Add Request for Transmit Buffer 19 [19:19] read-write AR20 Add Request for Transmit Buffer 20 [20:20] read-write AR21 Add Request for Transmit Buffer 21 [21:21] read-write AR22 Add Request for Transmit Buffer 22 [22:22] read-write AR23 Add Request for Transmit Buffer 23 [23:23] read-write AR24 Add Request for Transmit Buffer 24 [24:24] read-write AR25 Add Request for Transmit Buffer 25 [25:25] read-write AR26 Add Request for Transmit Buffer 26 [26:26] read-write AR27 Add Request for Transmit Buffer 27 [27:27] read-write AR28 Add Request for Transmit Buffer 28 [28:28] read-write AR29 Add Request for Transmit Buffer 29 [29:29] read-write AR30 Add Request for Transmit Buffer 30 [30:30] read-write AR31 Add Request for Transmit Buffer 31 [31:31] read-write TXBC Transmit Buffer Configuration Register 0xC0 0x20 read-write TBSA Tx Buffers Start Address [15:2] read-write 0 16383 NDTB Number of Dedicated Transmit Buffers [21:16] read-write 0 63 TFQS Transmit FIFO/Queue Size [29:24] read-write 0 63 TFQM Tx FIFO/Queue Mode [30:30] read-write TXBCF Transmit Buffer Cancellation Finished Register 0xDC 0x20 read-only CF0 Cancellation Finished for Transmit Buffer 0 [0:0] read-write CF1 Cancellation Finished for Transmit Buffer 1 [1:1] read-write CF2 Cancellation Finished for Transmit Buffer 2 [2:2] read-write CF3 Cancellation Finished for Transmit Buffer 3 [3:3] read-write CF4 Cancellation Finished for Transmit Buffer 4 [4:4] read-write CF5 Cancellation Finished for Transmit Buffer 5 [5:5] read-write CF6 Cancellation Finished for Transmit Buffer 6 [6:6] read-write CF7 Cancellation Finished for Transmit Buffer 7 [7:7] read-write CF8 Cancellation Finished for Transmit Buffer 8 [8:8] read-write CF9 Cancellation Finished for Transmit Buffer 9 [9:9] read-write CF10 Cancellation Finished for Transmit Buffer 10 [10:10] read-write CF11 Cancellation Finished for Transmit Buffer 11 [11:11] read-write CF12 Cancellation Finished for Transmit Buffer 12 [12:12] read-write CF13 Cancellation Finished for Transmit Buffer 13 [13:13] read-write CF14 Cancellation Finished for Transmit Buffer 14 [14:14] read-write CF15 Cancellation Finished for Transmit Buffer 15 [15:15] read-write CF16 Cancellation Finished for Transmit Buffer 16 [16:16] read-write CF17 Cancellation Finished for Transmit Buffer 17 [17:17] read-write CF18 Cancellation Finished for Transmit Buffer 18 [18:18] read-write CF19 Cancellation Finished for Transmit Buffer 19 [19:19] read-write CF20 Cancellation Finished for Transmit Buffer 20 [20:20] read-write CF21 Cancellation Finished for Transmit Buffer 21 [21:21] read-write CF22 Cancellation Finished for Transmit Buffer 22 [22:22] read-write CF23 Cancellation Finished for Transmit Buffer 23 [23:23] read-write CF24 Cancellation Finished for Transmit Buffer 24 [24:24] read-write CF25 Cancellation Finished for Transmit Buffer 25 [25:25] read-write CF26 Cancellation Finished for Transmit Buffer 26 [26:26] read-write CF27 Cancellation Finished for Transmit Buffer 27 [27:27] read-write CF28 Cancellation Finished for Transmit Buffer 28 [28:28] read-write CF29 Cancellation Finished for Transmit Buffer 29 [29:29] read-write CF30 Cancellation Finished for Transmit Buffer 30 [30:30] read-write CF31 Cancellation Finished for Transmit Buffer 31 [31:31] read-write TXBCIE Transmit Buffer Cancellation Finished Interrupt Enable Register 0xE4 0x20 read-write CFIE0 Cancellation Finished Interrupt Enable for Transmit Buffer 0 [0:0] read-write CFIE1 Cancellation Finished Interrupt Enable for Transmit Buffer 1 [1:1] read-write CFIE2 Cancellation Finished Interrupt Enable for Transmit Buffer 2 [2:2] read-write CFIE3 Cancellation Finished Interrupt Enable for Transmit Buffer 3 [3:3] read-write CFIE4 Cancellation Finished Interrupt Enable for Transmit Buffer 4 [4:4] read-write CFIE5 Cancellation Finished Interrupt Enable for Transmit Buffer 5 [5:5] read-write CFIE6 Cancellation Finished Interrupt Enable for Transmit Buffer 6 [6:6] read-write CFIE7 Cancellation Finished Interrupt Enable for Transmit Buffer 7 [7:7] read-write CFIE8 Cancellation Finished Interrupt Enable for Transmit Buffer 8 [8:8] read-write CFIE9 Cancellation Finished Interrupt Enable for Transmit Buffer 9 [9:9] read-write CFIE10 Cancellation Finished Interrupt Enable for Transmit Buffer 10 [10:10] read-write CFIE11 Cancellation Finished Interrupt Enable for Transmit Buffer 11 [11:11] read-write CFIE12 Cancellation Finished Interrupt Enable for Transmit Buffer 12 [12:12] read-write CFIE13 Cancellation Finished Interrupt Enable for Transmit Buffer 13 [13:13] read-write CFIE14 Cancellation Finished Interrupt Enable for Transmit Buffer 14 [14:14] read-write CFIE15 Cancellation Finished Interrupt Enable for Transmit Buffer 15 [15:15] read-write CFIE16 Cancellation Finished Interrupt Enable for Transmit Buffer 16 [16:16] read-write CFIE17 Cancellation Finished Interrupt Enable for Transmit Buffer 17 [17:17] read-write CFIE18 Cancellation Finished Interrupt Enable for Transmit Buffer 18 [18:18] read-write CFIE19 Cancellation Finished Interrupt Enable for Transmit Buffer 19 [19:19] read-write CFIE20 Cancellation Finished Interrupt Enable for Transmit Buffer 20 [20:20] read-write CFIE21 Cancellation Finished Interrupt Enable for Transmit Buffer 21 [21:21] read-write CFIE22 Cancellation Finished Interrupt Enable for Transmit Buffer 22 [22:22] read-write CFIE23 Cancellation Finished Interrupt Enable for Transmit Buffer 23 [23:23] read-write CFIE24 Cancellation Finished Interrupt Enable for Transmit Buffer 24 [24:24] read-write CFIE25 Cancellation Finished Interrupt Enable for Transmit Buffer 25 [25:25] read-write CFIE26 Cancellation Finished Interrupt Enable for Transmit Buffer 26 [26:26] read-write CFIE27 Cancellation Finished Interrupt Enable for Transmit Buffer 27 [27:27] read-write CFIE28 Cancellation Finished Interrupt Enable for Transmit Buffer 28 [28:28] read-write CFIE29 Cancellation Finished Interrupt Enable for Transmit Buffer 29 [29:29] read-write CFIE30 Cancellation Finished Interrupt Enable for Transmit Buffer 30 [30:30] read-write CFIE31 Cancellation Finished Interrupt Enable for Transmit Buffer 31 [31:31] read-write TXBCR Transmit Buffer Cancellation Request Register 0xD4 0x20 read-write CR0 Cancellation Request for Transmit Buffer 0 [0:0] read-write CR1 Cancellation Request for Transmit Buffer 1 [1:1] read-write CR2 Cancellation Request for Transmit Buffer 2 [2:2] read-write CR3 Cancellation Request for Transmit Buffer 3 [3:3] read-write CR4 Cancellation Request for Transmit Buffer 4 [4:4] read-write CR5 Cancellation Request for Transmit Buffer 5 [5:5] read-write CR6 Cancellation Request for Transmit Buffer 6 [6:6] read-write CR7 Cancellation Request for Transmit Buffer 7 [7:7] read-write CR8 Cancellation Request for Transmit Buffer 8 [8:8] read-write CR9 Cancellation Request for Transmit Buffer 9 [9:9] read-write CR10 Cancellation Request for Transmit Buffer 10 [10:10] read-write CR11 Cancellation Request for Transmit Buffer 11 [11:11] read-write CR12 Cancellation Request for Transmit Buffer 12 [12:12] read-write CR13 Cancellation Request for Transmit Buffer 13 [13:13] read-write CR14 Cancellation Request for Transmit Buffer 14 [14:14] read-write CR15 Cancellation Request for Transmit Buffer 15 [15:15] read-write CR16 Cancellation Request for Transmit Buffer 16 [16:16] read-write CR17 Cancellation Request for Transmit Buffer 17 [17:17] read-write CR18 Cancellation Request for Transmit Buffer 18 [18:18] read-write CR19 Cancellation Request for Transmit Buffer 19 [19:19] read-write CR20 Cancellation Request for Transmit Buffer 20 [20:20] read-write CR21 Cancellation Request for Transmit Buffer 21 [21:21] read-write CR22 Cancellation Request for Transmit Buffer 22 [22:22] read-write CR23 Cancellation Request for Transmit Buffer 23 [23:23] read-write CR24 Cancellation Request for Transmit Buffer 24 [24:24] read-write CR25 Cancellation Request for Transmit Buffer 25 [25:25] read-write CR26 Cancellation Request for Transmit Buffer 26 [26:26] read-write CR27 Cancellation Request for Transmit Buffer 27 [27:27] read-write CR28 Cancellation Request for Transmit Buffer 28 [28:28] read-write CR29 Cancellation Request for Transmit Buffer 29 [29:29] read-write CR30 Cancellation Request for Transmit Buffer 30 [30:30] read-write CR31 Cancellation Request for Transmit Buffer 31 [31:31] read-write TXBRP Transmit Buffer Request Pending Register 0xCC 0x20 read-only TRP0 Transmission Request Pending for Buffer 0 [0:0] read-write TRP1 Transmission Request Pending for Buffer 1 [1:1] read-write TRP2 Transmission Request Pending for Buffer 2 [2:2] read-write TRP3 Transmission Request Pending for Buffer 3 [3:3] read-write TRP4 Transmission Request Pending for Buffer 4 [4:4] read-write TRP5 Transmission Request Pending for Buffer 5 [5:5] read-write TRP6 Transmission Request Pending for Buffer 6 [6:6] read-write TRP7 Transmission Request Pending for Buffer 7 [7:7] read-write TRP8 Transmission Request Pending for Buffer 8 [8:8] read-write TRP9 Transmission Request Pending for Buffer 9 [9:9] read-write TRP10 Transmission Request Pending for Buffer 10 [10:10] read-write TRP11 Transmission Request Pending for Buffer 11 [11:11] read-write TRP12 Transmission Request Pending for Buffer 12 [12:12] read-write TRP13 Transmission Request Pending for Buffer 13 [13:13] read-write TRP14 Transmission Request Pending for Buffer 14 [14:14] read-write TRP15 Transmission Request Pending for Buffer 15 [15:15] read-write TRP16 Transmission Request Pending for Buffer 16 [16:16] read-write TRP17 Transmission Request Pending for Buffer 17 [17:17] read-write TRP18 Transmission Request Pending for Buffer 18 [18:18] read-write TRP19 Transmission Request Pending for Buffer 19 [19:19] read-write TRP20 Transmission Request Pending for Buffer 20 [20:20] read-write TRP21 Transmission Request Pending for Buffer 21 [21:21] read-write TRP22 Transmission Request Pending for Buffer 22 [22:22] read-write TRP23 Transmission Request Pending for Buffer 23 [23:23] read-write TRP24 Transmission Request Pending for Buffer 24 [24:24] read-write TRP25 Transmission Request Pending for Buffer 25 [25:25] read-write TRP26 Transmission Request Pending for Buffer 26 [26:26] read-write TRP27 Transmission Request Pending for Buffer 27 [27:27] read-write TRP28 Transmission Request Pending for Buffer 28 [28:28] read-write TRP29 Transmission Request Pending for Buffer 29 [29:29] read-write TRP30 Transmission Request Pending for Buffer 30 [30:30] read-write TRP31 Transmission Request Pending for Buffer 31 [31:31] read-write TXBTIE Transmit Buffer Transmission Interrupt Enable Register 0xE0 0x20 read-write TIE0 Transmission Interrupt Enable for Buffer 0 [0:0] read-write TIE1 Transmission Interrupt Enable for Buffer 1 [1:1] read-write TIE2 Transmission Interrupt Enable for Buffer 2 [2:2] read-write TIE3 Transmission Interrupt Enable for Buffer 3 [3:3] read-write TIE4 Transmission Interrupt Enable for Buffer 4 [4:4] read-write TIE5 Transmission Interrupt Enable for Buffer 5 [5:5] read-write TIE6 Transmission Interrupt Enable for Buffer 6 [6:6] read-write TIE7 Transmission Interrupt Enable for Buffer 7 [7:7] read-write TIE8 Transmission Interrupt Enable for Buffer 8 [8:8] read-write TIE9 Transmission Interrupt Enable for Buffer 9 [9:9] read-write TIE10 Transmission Interrupt Enable for Buffer 10 [10:10] read-write TIE11 Transmission Interrupt Enable for Buffer 11 [11:11] read-write TIE12 Transmission Interrupt Enable for Buffer 12 [12:12] read-write TIE13 Transmission Interrupt Enable for Buffer 13 [13:13] read-write TIE14 Transmission Interrupt Enable for Buffer 14 [14:14] read-write TIE15 Transmission Interrupt Enable for Buffer 15 [15:15] read-write TIE16 Transmission Interrupt Enable for Buffer 16 [16:16] read-write TIE17 Transmission Interrupt Enable for Buffer 17 [17:17] read-write TIE18 Transmission Interrupt Enable for Buffer 18 [18:18] read-write TIE19 Transmission Interrupt Enable for Buffer 19 [19:19] read-write TIE20 Transmission Interrupt Enable for Buffer 20 [20:20] read-write TIE21 Transmission Interrupt Enable for Buffer 21 [21:21] read-write TIE22 Transmission Interrupt Enable for Buffer 22 [22:22] read-write TIE23 Transmission Interrupt Enable for Buffer 23 [23:23] read-write TIE24 Transmission Interrupt Enable for Buffer 24 [24:24] read-write TIE25 Transmission Interrupt Enable for Buffer 25 [25:25] read-write TIE26 Transmission Interrupt Enable for Buffer 26 [26:26] read-write TIE27 Transmission Interrupt Enable for Buffer 27 [27:27] read-write TIE28 Transmission Interrupt Enable for Buffer 28 [28:28] read-write TIE29 Transmission Interrupt Enable for Buffer 29 [29:29] read-write TIE30 Transmission Interrupt Enable for Buffer 30 [30:30] read-write TIE31 Transmission Interrupt Enable for Buffer 31 [31:31] read-write TXBTO Transmit Buffer Transmission Occurred Register 0xD8 0x20 read-only TO0 Transmission Occurred for Buffer 0 [0:0] read-write TO1 Transmission Occurred for Buffer 1 [1:1] read-write TO2 Transmission Occurred for Buffer 2 [2:2] read-write TO3 Transmission Occurred for Buffer 3 [3:3] read-write TO4 Transmission Occurred for Buffer 4 [4:4] read-write TO5 Transmission Occurred for Buffer 5 [5:5] read-write TO6 Transmission Occurred for Buffer 6 [6:6] read-write TO7 Transmission Occurred for Buffer 7 [7:7] read-write TO8 Transmission Occurred for Buffer 8 [8:8] read-write TO9 Transmission Occurred for Buffer 9 [9:9] read-write TO10 Transmission Occurred for Buffer 10 [10:10] read-write TO11 Transmission Occurred for Buffer 11 [11:11] read-write TO12 Transmission Occurred for Buffer 12 [12:12] read-write TO13 Transmission Occurred for Buffer 13 [13:13] read-write TO14 Transmission Occurred for Buffer 14 [14:14] read-write TO15 Transmission Occurred for Buffer 15 [15:15] read-write TO16 Transmission Occurred for Buffer 16 [16:16] read-write TO17 Transmission Occurred for Buffer 17 [17:17] read-write TO18 Transmission Occurred for Buffer 18 [18:18] read-write TO19 Transmission Occurred for Buffer 19 [19:19] read-write TO20 Transmission Occurred for Buffer 20 [20:20] read-write TO21 Transmission Occurred for Buffer 21 [21:21] read-write TO22 Transmission Occurred for Buffer 22 [22:22] read-write TO23 Transmission Occurred for Buffer 23 [23:23] read-write TO24 Transmission Occurred for Buffer 24 [24:24] read-write TO25 Transmission Occurred for Buffer 25 [25:25] read-write TO26 Transmission Occurred for Buffer 26 [26:26] read-write TO27 Transmission Occurred for Buffer 27 [27:27] read-write TO28 Transmission Occurred for Buffer 28 [28:28] read-write TO29 Transmission Occurred for Buffer 29 [29:29] read-write TO30 Transmission Occurred for Buffer 30 [30:30] read-write TO31 Transmission Occurred for Buffer 31 [31:31] read-write TXEFA Transmit Event FIFO Acknowledge Register 0xF8 0x20 read-write EFAI Event FIFO Acknowledge Index [4:0] read-write 0 31 TXEFC Transmit Event FIFO Configuration Register 0xF0 0x20 read-write EFSA Event FIFO Start Address [15:2] read-write 0 16383 EFS Event FIFO Size [21:16] read-write 0 63 EFWM Event FIFO Watermark [29:24] read-write 0 63 TXEFS Transmit Event FIFO Status Register 0xF4 0x20 read-only EFFL Event FIFO Fill Level [5:0] read-write 0 63 EFGI Event FIFO Get Index [12:8] read-write 0 31 EFPI Event FIFO Put Index [20:16] read-write 0 31 EFF Event FIFO Full [24:24] read-write TEFL Tx Event FIFO Element Lost [25:25] read-write TXESC Transmit Buffer Element Size Configuration Register 0xC8 0x20 read-write TBDS Tx Buffer Data Field Size [2:0] read-write true _8_BYTE 8-byte data field 0 _12_BYTE 12-byte data field 1 _16_BYTE 16-byte data field 2 _20_BYTE 20-byte data field 3 _24_BYTE 24-byte data field 4 _32_BYTE 32-byte data field 5 _48_BYTE 48- byte data field 6 _64_BYTE 64-byte data field 7 TXFQS Transmit FIFO/Queue Status Register 0xC4 0x20 read-only TFFL Tx FIFO Free Level [5:0] read-write 0 63 TFGI Tx FIFO Get Index [12:8] read-write 0 31 TFQPI Tx FIFO/Queue Put Index [20:16] read-write 0 31 TFQF Tx FIFO/Queue Full [21:21] read-write XIDAM Extended ID AND Mask Register 0x90 0x20 read-write EIDM Extended ID Mask [28:0] read-write 0 536870911 XIDFC Extended ID Filter Configuration Register 0x88 0x20 read-write FLESA Filter List Extended Start Address [15:2] read-write 0 16383 LSE List Size Extended [22:16] read-write 0 127 MCAN1 Controller Area Network 0xFC050000 MPDDRC AHB Multiport DDR-SDRAM Controller 0xF000C000 0x0 0x18 registers 0x1C 0x8 registers 0x28 0x7C registers 0xE4 0x8 registers BDW_PORT_0123 Current/Maximum Bandwidth Port 0-1-2-3 Register 0x54 0x20 read-only BDW_P0 Current/Maximum Bandwidth from Port 0-1-2-3 [6:0] read-write 0 127 BDW_P1 Current/Maximum Bandwidth from Port 0-1-2-3 [14:8] read-write 0 127 BDW_P2 Current/Maximum Bandwidth from Port 0-1-2-3 [22:16] read-write 0 127 BDW_P3 Current/Maximum Bandwidth from Port 0-1-2-3 [30:24] read-write 0 127 BDW_PORT_4567 Current/Maximum Bandwidth Port 4-5-6-7 Register 0x58 0x20 read-only BDW_P4 Current/Maximum Bandwidth from Port 4-5-6-7 [6:0] read-write 0 127 BDW_P5 Current/Maximum Bandwidth from Port 4-5-6-7 [14:8] read-write 0 127 BDW_P6 Current/Maximum Bandwidth from Port 4-5-6-7 [22:16] read-write 0 127 BDW_P7 Current/Maximum Bandwidth from Port 4-5-6-7 [30:24] read-write 0 127 CONF_ARBITER Configuration Arbiter Register 0x44 0x20 read-write ARB Type of Arbitration [1:0] read-write true ROUND Round Robin 0 NB_REQUEST Request Policy 1 BANDWIDTH Bandwidth Policy 2 BDW_MAX_CUR Bandwidth Max or Current [3:3] read-write RQ_WD_P0 Request or Word from Port X [8:8] read-write RQ_WD_P1 Request or Word from Port X [9:9] read-write RQ_WD_P2 Request or Word from Port X [10:10] read-write RQ_WD_P3 Request or Word from Port X [11:11] read-write RQ_WD_P4 Request or Word from Port X [12:12] read-write RQ_WD_P5 Request or Word from Port X [13:13] read-write RQ_WD_P6 Request or Word from Port X [14:14] read-write RQ_WD_P7 Request or Word from Port X [15:15] read-write MA_PR_P0 Master or Software Provide Information [16:16] read-write MA_PR_P1 Master or Software Provide Information [17:17] read-write MA_PR_P2 Master or Software Provide Information [18:18] read-write MA_PR_P3 Master or Software Provide Information [19:19] read-write MA_PR_P4 Master or Software Provide Information [20:20] read-write MA_PR_P5 Master or Software Provide Information [21:21] read-write MA_PR_P6 Master or Software Provide Information [22:22] read-write MA_PR_P7 Master or Software Provide Information [23:23] read-write BDW_BURST_P0 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X [24:24] read-write BDW_BURST_P1 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X [25:25] read-write BDW_BURST_P2 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X [26:26] read-write BDW_BURST_P3 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X [27:27] read-write BDW_BURST_P4 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X [28:28] read-write BDW_BURST_P5 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X [29:29] read-write BDW_BURST_P6 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X [30:30] read-write BDW_BURST_P7 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X [31:31] read-write CR Configuration Register 0x8 0x20 read-write NC Number of Column Bits [1:0] read-write true DDR9_MDDR8_COL_BITS 9 bits to define the column number, up to 512 columns, for DDR2-SDRAM/DDR3-SDRAM/LPDDR2-SDRAM/LPDDR3-SDRAM 8 bits to define the column number, up to 256 columns, for LPDDR1-SDRAM 0 DDR10_MDDR9_COL_BITS 10 bits to define the column number, up to 1024 columns, for DDR2-SDRAM/DDR3-SDRAM/LPDDR2-SDRAM/LPDDR3-SDRAM 9 bits to define the column number, up to 512 columns, for LPDDR1-SDRAM 1 DDR11_MDDR10_COL_BITS 11 bits to define the column number, up to 2048 columns, for DDR2-SDRAM/DDR3-SDRAM/LPDDR2-SDRAM/LPDDR3-SDRAM 10 bits to define the column number, up to 1024 columns, for LPDDR1-SDRAM 2 DDR12_MDDR11_COL_BITS 12 bits to define the column number, up to 4096 columns, for DDR2-SDRAM/DDR3-SDRAM/LPDDR2-SDRAM/LPDDR3-SDRAM 11 bits to define the column number, up to 2048 columns, for LPDDR1-SDRAM 3 NR Number of Row Bits [3:2] read-write true _11_ROW_BITS 11 bits to define the row number, up to 2048 rows 0 _12_ROW_BITS 12 bits to define the row number, up to 4096 rows 1 _13_ROW_BITS 13 bits to define the row number, up to 8192 rows 2 _14_ROW_BITS 14 bits to define the row number, up to 16384 rows 3 CAS CAS Latency [6:4] read-write true DDR_CAS2 LPDDR1 CAS Latency 2 2 DDR_CAS3 LPDDR3/DDR2/LPDDR2/LPDDR1 CAS Latency 3 3 DDR_CAS5 DDR3 CAS Latency 5 5 DDR_CAS6 DDR3LPDDR3 CAS Latency 6 6 DLL Reset DLL [7:7] read-write true RESET_DISABLED Disable DLL reset 0 RESET_ENABLED Enable DLL reset 1 DIC_DS Output Driver Impedance Control (Drive Strength) [8:8] read-write true DDR2_NORMALSTRENGTH_DDR3_RZQ6 Normal drive strength (DDR2) - RZQ/6 (40 [NOM], DDR3) 0 DDR2_WEAKSTRENGTH_DDR3_RZQ7 Weak drive strength (DDR2) - RZQ/7 (34 [NOM], DDR3) 1 DIS_DLL DISABLE DLL [9:9] read-write ZQ ZQ Calibration [11:10] read-write true INIT Calibration command after initialization 0 LONG Long calibration 1 SHORT Short calibration 2 RESET ZQ Reset 3 OCD Off-chip Driver [14:12] read-write true DDR2_EXITCALIB Exit from OCD Calibration mode and maintain settings 0 DDR2_DEFAULT_CALIB OCD calibration default 7 DQMS Mask Data is Shared [16:16] read-write true NOT_SHARED DQM is not shared with another controller 0 SHARED DQM is shared with another controller 1 ENRDM Enable Read Measure [17:17] read-write true OFF DQS/DDR_DATA phase error correction is disabled 0 ON DQS/DDR_DATA phase error correction is enabled 1 LC_LPDDR1 Low-cost Low-power DDR1 [19:19] read-write true NOT_2_BANKS Any type of memory devices except of low cost, low density Low Power DDR1. 0 _2_BANKS_LPDDR1 Low-cost and low-density low-power DDR1. These devices have a density of 32 Mbits and are organized as two internal banks. To use this feature, the user has to define the type of memory and the data bus width (see Section 8.8 "MPDDRC Memory Device Register").The 16-bit memory device is organized as 2 banks, 9 columns and 11 rows.The 32-bit memory device is organized as 2 banks, 8 columns and 11 rows.It is impossible to use two 16-bit memory devices (2 x 32 Mbits) for creating one 32-bit memory device (64 Mbits). In this case, it is recommended to use one 32-bit memory device which embeds four internal banks. 1 NB Number of Banks [20:20] read-write true _4_BANKS 4-bank memory devices 0 _8_BANKS 8 banks. Only possible when using the DDR2-SDRAM and low-power DDR2-SDRAM and DDR3-SDRAM and low-power DDR3-SDRAM devices. 1 NDQS Not DQS [21:21] read-write true ENABLED Not DQS is enabled 0 DISABLED Not DQS is disabled 1 DECOD Type of Decoding [22:22] read-write true SEQUENTIAL Method for address mapping where banks alternate at each last DDR-SDRAM page of the current bank. 0 INTERLEAVED Method for address mapping where banks alternate at each DDR-SDRAM end of page of the current bank. 1 UNAL Support Unaligned Access [23:23] read-write true UNSUPPORTED Unaligned access is not supported. 0 SUPPORTED Unaligned access is supported. 1 IO_CALIBR I/O Calibration Register 0x34 0x20 read-write RDIV Resistor Divider, Output Driver Impedance [2:0] read-write true RZQ_34 LPDDR2 serial impedance line = 34.3 ohms,DDR2/LPDDR1 serial impedance line: Not applicable 1 RZQ_40_RZQ_38_RZQ_37_RZQ_35 LPDDR2 serial impedance line = 40 ohms,LPDDR3 serial impedance line = 38 ohms,DDR3 serial impedance line = 37 ohms,DDR2/LPDDR1 serial impedance line = 35 ohms 2 RZQ_48_RZQ_46_RZQ_44_RZQ_43 LPDDR2 serial impedance line = 48 ohms,LPDDR3 serial impedance line = 46 ohms,DDR3 serial impedance line = 44 ohms,DDR2/LPDDR1 serial impedance line = 43 ohms 3 RZQ_60_RZQ_57_RZQ_55_RZQ_52 LPDDR2 serial impedance line = 60 ohms,LPDDR3 serial impedance line = 57 ohms,DDR3 serial impedance line = 55 ohms,DDR2/LPDDR1 serial impedance line = 52 ohms 4 RZQ_80_RZQ_77_RZQ_73_RZQ_70 LPDDR2 serial impedance line = 80 ohms,LPDDR3 serial impedance line = 77 ohms,DDR3 serial impedance line = 73 ohms,DDR2/LPDDR1 serial impedance line = 70 ohms 6 RZQ_120_RZQ_115_RZQ_110_RZQ_105 LPDDR2 serial impedance line = 120 ohms,LPDDR3 serial impedance line = 115 ohms,DDR3 serial impedance line = 110 ohms,DDR2/LPDDR1 serial impedance line = 105 ohms 7 EN_CALIB Enable Calibration [4:4] read-write true DISABLE_CALIBRATION Calibration is disabled. 0 ENABLE_CALIBRATION Calibration is enabled. 1 TZQIO IO Calibration [14:8] read-write 0 127 CALCODEP Number of Transistor P (read-only) [19:16] read-write 0 15 CALCODEN Number of Transistor N (read-only) [23:20] read-write 0 15 LPDDR23_LPR Low-power DDR2 Low-power DDR3 Low-power Register 0x28 0x20 read-write BK_MASK_PASR Bank Mask Bit/PASR [7:0] read-write 0 255 SEG_MASK Segment Mask Bit [23:8] read-write 0 65535 DS Drive Strength [27:24] read-write true DS_34_3 34.3 ohm typical 1 DS_40 40 ohm typical (default) 2 DS_48 48 ohm typical 3 DS_60 60 ohm typical 4 DS_80 80 ohm typical 6 DS_120 120 ohm typical 7 LPDDR2_LPDDR3_DDR3_CAL_MR4 Low-power DDR2 Low-power DDR3 and DDR3 Calibration and MR4 Register 0x2C 0x20 read-write COUNT_CAL LPDDR2 LPDDR3 and DDR3 Calibration Timer Count [15:0] read-write 0 65535 MR4_READ Mode Register 4 Read Interval [31:16] read-write 0 65535 LPDDR2_LPDDR3_DDR3_TIM_CAL Low-power DDR2 Low-power DDR3 and DDR3 Timing Calibration Register 0x30 0x20 read-write ZQCS ZQ Calibration Short [7:0] read-write 0 255 RZQI Built-in Self-Test for RZQ Information (read-only) [17:16] read-write true RZQ_NOT_SUPPORTED RZQ self test not supported 0 ZQ_VDDCA_FLOAT The ZQ pin can be connected to VDDCA or left floating. 1 ZQ_SHORTED_GROUND The ZQ pin can be shorted to ground. 2 ZQ_SELF_TEST_OK ZQ pin self test complete; no error condition detected 3 LPR Low-Power Register 0x1C 0x20 read-write LPCB Low-power Command Bit [1:0] read-write true NOLOWPOWER Low-power feature is inhibited. No Powerdown, Self-refresh and Deep power modes are issued to the DDR-SDRAM device. 0 SELFREFRESH The MPDDRC issues a self-refresh command to the DDR-SDRAM device, the clock(s) is/are deactivated and the CKE signal is set low. The DDR-SDRAM device leaves the Self-refresh mode when accessed and reenters it after the access. 1 POWERDOWN The MPDDRC issues a Powerdown command to the DDR-SDRAM device after each access, the CKE signal is set low. The DDR-SDRAM device leaves the Powerdown mode when accessed and reenters it after the access. 2 DEEPPOWERDOWN The MPDDRC issues a Deep Powerdown command to the low-power DDR-SDRAM device. 3 CLK_FR Clock Frozen Command Bit [2:2] read-write true DISABLED Clock(s) is/are not frozen. 0 ENABLED Clock(s) is/are frozen. 1 LPDDR2_LPDDR3_PWOFF LPDDR2 - LPDDR3 Power Off Bit [3:3] read-write true DISABLED No power-off sequence applied to LPDDR2/LPDDR3. 0 ENABLED A power-off sequence is applied to the LPDDR2/LPDDR3 device. CKE is forced low. 1 PASR Partial Array Self-refresh [6:4] read-write 0 7 DS Drive Strength [10:8] read-write true DS_FULL Full drive strength 0 DS_HALF Half drive strength 1 DS_QUARTER Quarter drive strength 2 DS_OCTANT Octant drive strength 3 TIMEOUT Time Between Last Transfer and Low-Power Mode [13:12] read-write true NONE SDRAM Low-power mode is activated immediately after the end of the last transfer. 0 DELAY_64_CLK SDRAM Low-power mode is activated 64 clock cycles after the end of the last transfer. 1 DELAY_128_CLK SDRAM Low-power mode is activated 128 clock cycles after the end of the last transfer. 2 APDE Active Power Down Exit Time [16:16] read-write true DDR2_FAST_EXIT Fast Exit from Power Down. DDR2-SDRAM and DDR3-SDRAM devices only. 0 DDR2_SLOW_EXIT Slow Exit from Power Down. DDR2-SDRAM and DDR3-SDRAM devices only. 1 UPD_MR Update Load Mode Register and Extended Mode Register [21:20] read-write true NO_UPDATE Update of Load Mode and Extended Mode registers is disabled. 0 UPDATE_SHAREDBUS MPDDRC shares an external bus. Automatic update is done during a refresh command and a pending read or write access in the SDRAM device. 1 UPDATE_NOSHAREDBUS MPDDRC does not share an external bus. Automatic update is done before entering Self-refresh mode. 2 CHG_FRQ Change Clock Frequency During Self-refresh Mode [24:24] read-write SELF_DONE Self-refresh is done (read-only) [25:25] read-write MADDR0 Monitor Address High/Low Port 0 Register 0x64 0x20 read-write ADDR_LOW_PORT0 Address Low on Port x [x = 0..7] [15:0] read-write 0 65535 ADDR_HIGH_PORT0 Address High on Port x [x = 0..7] [31:16] read-write 0 65535 MADDR1 Monitor Address High/Low Port 1 Register 0x68 0x20 read-write ADDR_LOW_PORT1 Address Low on Port x [x = 0..7] [15:0] read-write 0 65535 ADDR_HIGH_PORT1 Address High on Port x [x = 0..7] [31:16] read-write 0 65535 MADDR2 Monitor Address High/Low Port 2 Register 0x6C 0x20 read-write ADDR_LOW_PORT2 Address Low on Port x [x = 0..7] [15:0] read-write 0 65535 ADDR_HIGH_PORT2 Address High on Port x [x = 0..7] [31:16] read-write 0 65535 MADDR3 Monitor Address High/Low Port 3 Register 0x70 0x20 read-write ADDR_LOW_PORT3 Address Low on Port x [x = 0..7] [15:0] read-write 0 65535 ADDR_HIGH_PORT3 Address High on Port x [x = 0..7] [31:16] read-write 0 65535 MADDR4 Monitor Address High/Low Port 4 Register 0x74 0x20 read-write ADDR_LOW_PORT4 Address Low on Port x [x = 0..7] [15:0] read-write 0 65535 ADDR_HIGH_PORT4 Address High on Port x [x = 0..7] [31:16] read-write 0 65535 MADDR5 Monitor Address High/Low Port 5 Register 0x78 0x20 read-write ADDR_LOW_PORT5 Address Low on Port x [x = 0..7] [15:0] read-write 0 65535 ADDR_HIGH_PORT5 Address High on Port x [x = 0..7] [31:16] read-write 0 65535 MADDR6 Monitor Address High/Low Port 6 Register 0x7C 0x20 read-write ADDR_LOW_PORT6 Address Low on Port x [x = 0..7] [15:0] read-write 0 65535 ADDR_HIGH_PORT6 Address High on Port x [x = 0..7] [31:16] read-write 0 65535 MADDR7 Monitor Address High/Low Port 7 Register 0x80 0x20 read-write ADDR_LOW_PORT7 Address Low on Port x [x = 0..7] [15:0] read-write 0 65535 ADDR_HIGH_PORT7 Address High on Port x [x = 0..7] [31:16] read-write 0 65535 MCFGR Monitor Configuration Register 0x60 0x20 read-write EN_MONI Enable Monitor [0:0] read-write SOFT_RESET Soft Reset [1:1] read-write RUN Control Monitor [4:4] read-write READ_WRITE Read/Write Access [9:8] read-write true TRIG_RD_WR Read and Write accesses are triggered. 0 TRIG_WR Only Write accesses are triggered. 1 TRIG_RD Only Read accesses are triggered. 2 REFR_CALIB Refresh Calibration [10:10] read-write INFO Information Type [12:11] read-write true MAX_WAIT Information concerning the transfer with the longest waiting time 0 NB_TRANSFERS Number of transfers on the port 1 TOTAL_LATENCY Total latency on the port 2 MD Memory Device Register 0x20 0x20 read-write MD Memory Device [2:0] read-write true LPDDR_SDRAM Low-power DDR1-SDRAM 3 DDR3_SDRAM DDR3-SDRAM 4 LPDDR3_SDRAM Low-power DDR3-SDRAM 5 DDR2_SDRAM DDR2-SDRAM 6 LPDDR2_SDRAM Low-power DDR2-SDRAM 7 DBW Data Bus Width [4:4] read-write true DBW_32_BITS Data bus width is 32 bits 0 DBW_16_BITS Data bus width is 16 bits. 1 WL Write Latency (read-only) [6:6] read-write true WL_SETA Write Latency Set A 0 WL_SETB Write Latency Set B 1 RL3 Read Latency 3 Option Support (read-only) [7:7] read-write true RL3_SUPPORT Read latency of 3 is supported 0 RL3_NOT_SUPPORTED Read latency 0f 3 is not supported 1 MANU_ID Manufacturer Identification (read-only) [15:8] read-write 0 255 REV_ID Revision Identification (read-only) [23:16] read-write 0 255 TYPE DRAM Architecture (read-only) [25:24] read-write true S4_SDRAM 4n prefetch architecture 0 S2_SDRAM 2n prefetch architecture 1 NVM Non-volatile device 2 S8_SDRAM 8n prefetch architecture 3 DENSITY Density of Memory (read-only) [29:26] read-write true DENSITY_64MBITS The device density is 64 Mbits. 0 DENSITY_128MBITS The device density is 128 Mbits. 1 DENSITY_256MBITS The device density is 256 Mbits. 2 DENSITY_512MBITS The device density is 512 Mbits. 3 DENSITY_1GBITS The device density is 1 Gbit. 4 DENSITY_2GBITS The device density is 2 Gbits. 5 DENSITY_4GBITS The device density is 4 Gbits. 6 DENSITY_8GBITS The device density is 8 Gbits. 7 DENSITY_16GBITS The device density is 16 Gbits. 8 DENSITY_32GBITS The device density is 32 Gbits. 9 IO_WIDTH Width of Memory (read-only) [31:30] read-write true WIDTH_32 The data bus width is 32 bits. 0 WIDTH_16 The data bus width is 16 bits. 1 WIDTH_8 The data bus width is 8 bits. 2 NOT_USED - 3 MINFO0 Monitor Information Port 0 Register 0x84 0x20 read-only MAX_PORT0_WAITING Address High on Port x [x = 0..7] [15:0] read-write 0 65535 P0_NB_TRANSFERS Number of Transfers on Port x [x = 0..7] [31:0] read-write 0 4294967295 P0_TOTAL_LATENCY Total Latency on Port x [x = 0..7] [31:0] read-write 0 4294967295 BURST Type of Burst on Port x [x = 0..7] [18:16] read-write true SINGLE Single transfer 0 INCR Incrementing burst of unspecified length 1 WRAP4 4-beat wrapping burst 2 INCR4 4-beat incrementing burst 3 WRAP8 8-beat wrapping burst 4 INCR8 8-beat incrementing burst 5 WRAP16 16-beat wrapping burst 6 INCR16 16-beat incrementing burst 7 SIZE Transfer Size on Port x [x = 0..7] [22:20] read-write true _8BITS Byte transfer 0 _16BITS Halfword transfer 1 _32BITS Word transfer 2 _64BITS Dword transfer 3 READ_WRITE Read or Write Access on Port x [x = 0..7] [24:24] read-write MINFO1 Monitor Information Port 1 Register 0x88 0x20 read-only MAX_PORT1_WAITING Address High on Port x [x = 0..7] [15:0] read-write 0 65535 P1_NB_TRANSFERS Number of Transfers on Port x [x = 0..7] [31:0] read-write 0 4294967295 P1_TOTAL_LATENCY Total Latency on Port x [x = 0..7] [31:0] read-write 0 4294967295 BURST Type of Burst on Port x [x = 0..7] [18:16] read-write true SINGLE Single transfer 0 INCR Incrementing burst of unspecified length 1 WRAP4 4-beat wrapping burst 2 INCR4 4-beat incrementing burst 3 WRAP8 8-beat wrapping burst 4 INCR8 8-beat incrementing burst 5 WRAP16 16-beat wrapping burst 6 INCR16 16-beat incrementing burst 7 SIZE Transfer Size on Port x [x = 0..7] [22:20] read-write true _8BITS Byte transfer 0 _16BITS Halfword transfer 1 _32BITS Word transfer 2 _64BITS Dword transfer 3 READ_WRITE Read or Write Access on Port x [x = 0..7] [24:24] read-write MINFO2 Monitor Information Port 2 Register 0x8C 0x20 read-only MAX_PORT2_WAITING Address High on Port x [x = 0..7] [15:0] read-write 0 65535 P2_NB_TRANSFERS Number of Transfers on Port x [x = 0..7] [31:0] read-write 0 4294967295 P2_TOTAL_LATENCY Total Latency on Port x [x = 0..7] [31:0] read-write 0 4294967295 BURST Type of Burst on Port x [x = 0..7] [18:16] read-write true SINGLE Single transfer 0 INCR Incrementing burst of unspecified length 1 WRAP4 4-beat wrapping burst 2 INCR4 4-beat incrementing burst 3 WRAP8 8-beat wrapping burst 4 INCR8 8-beat incrementing burst 5 WRAP16 16-beat wrapping burst 6 INCR16 16-beat incrementing burst 7 SIZE Transfer Size on Port x [x = 0..7] [22:20] read-write true _8BITS Byte transfer 0 _16BITS Halfword transfer 1 _32BITS Word transfer 2 _64BITS Dword transfer 3 READ_WRITE Read or Write Access on Port x [x = 0..7] [24:24] read-write MINFO3 Monitor Information Port 3 Register 0x90 0x20 read-only MAX_PORT3_WAITING Address High on Port x [x = 0..7] [15:0] read-write 0 65535 P3_NB_TRANSFERS Number of Transfers on Port x [x = 0..7] [31:0] read-write 0 4294967295 P3_TOTAL_LATENCY Total Latency on Port x [x = 0..7] [31:0] read-write 0 4294967295 BURST Type of Burst on Port x [x = 0..7] [18:16] read-write true SINGLE Single transfer 0 INCR Incrementing burst of unspecified length 1 WRAP4 4-beat wrapping burst 2 INCR4 4-beat incrementing burst 3 WRAP8 8-beat wrapping burst 4 INCR8 8-beat incrementing burst 5 WRAP16 16-beat wrapping burst 6 INCR16 16-beat incrementing burst 7 SIZE Transfer Size on Port x [x = 0..7] [22:20] read-write true _8BITS Byte transfer 0 _16BITS Halfword transfer 1 _32BITS Word transfer 2 _64BITS Dword transfer 3 READ_WRITE Read or Write Access on Port x [x = 0..7] [24:24] read-write MINFO4 Monitor Information Port 4 Register 0x94 0x20 read-only MAX_PORT4_WAITING Address High on Port x [x = 0..7] [15:0] read-write 0 65535 P4_NB_TRANSFERS Number of Transfers on Port x [x = 0..7] [31:0] read-write 0 4294967295 P4_TOTAL_LATENCY Total Latency on Port x [x = 0..7] [31:0] read-write 0 4294967295 BURST Type of Burst on Port x [x = 0..7] [18:16] read-write true SINGLE Single transfer 0 INCR Incrementing burst of unspecified length 1 WRAP4 4-beat wrapping burst 2 INCR4 4-beat incrementing burst 3 WRAP8 8-beat wrapping burst 4 INCR8 8-beat incrementing burst 5 WRAP16 16-beat wrapping burst 6 INCR16 16-beat incrementing burst 7 SIZE Transfer Size on Port x [x = 0..7] [22:20] read-write true _8BITS Byte transfer 0 _16BITS Halfword transfer 1 _32BITS Word transfer 2 _64BITS Dword transfer 3 READ_WRITE Read or Write Access on Port x [x = 0..7] [24:24] read-write MINFO5 Monitor Information Port 5 Register 0x98 0x20 read-only MAX_PORT5_WAITING Address High on Port x [x = 0..7] [15:0] read-write 0 65535 P5_NB_TRANSFERS Number of Transfers on Port x [x = 0..7] [31:0] read-write 0 4294967295 P5_TOTAL_LATENCY Total Latency on Port x [x = 0..7] [31:0] read-write 0 4294967295 BURST Type of Burst on Port x [x = 0..7] [18:16] read-write true SINGLE Single transfer 0 INCR Incrementing burst of unspecified length 1 WRAP4 4-beat wrapping burst 2 INCR4 4-beat incrementing burst 3 WRAP8 8-beat wrapping burst 4 INCR8 8-beat incrementing burst 5 WRAP16 16-beat wrapping burst 6 INCR16 16-beat incrementing burst 7 SIZE Transfer Size on Port x [x = 0..7] [22:20] read-write true _8BITS Byte transfer 0 _16BITS Halfword transfer 1 _32BITS Word transfer 2 _64BITS Dword transfer 3 READ_WRITE Read or Write Access on Port x [x = 0..7] [24:24] read-write MINFO6 Monitor Information Port 6 Register 0x9C 0x20 read-only MAX_PORT6_WAITING Address High on Port x [x = 0..7] [15:0] read-write 0 65535 P6_NB_TRANSFERS Number of Transfers on Port x [x = 0..7] [31:0] read-write 0 4294967295 P6_TOTAL_LATENCY Total Latency on Port x [x = 0..7] [31:0] read-write 0 4294967295 BURST Type of Burst on Port x [x = 0..7] [18:16] read-write true SINGLE Single transfer 0 INCR Incrementing burst of unspecified length 1 WRAP4 4-beat wrapping burst 2 INCR4 4-beat incrementing burst 3 WRAP8 8-beat wrapping burst 4 INCR8 8-beat incrementing burst 5 WRAP16 16-beat wrapping burst 6 INCR16 16-beat incrementing burst 7 SIZE Transfer Size on Port x [x = 0..7] [22:20] read-write true _8BITS Byte transfer 0 _16BITS Halfword transfer 1 _32BITS Word transfer 2 _64BITS Dword transfer 3 READ_WRITE Read or Write Access on Port x [x = 0..7] [24:24] read-write MINFO7 Monitor Information Port 7 Register 0xA0 0x20 read-only MAX_PORT7_WAITING Address High on Port x [x = 0..7] [15:0] read-write 0 65535 P7_NB_TRANSFERS Number of Transfers on Port x [x = 0..7] [31:0] read-write 0 4294967295 P7_TOTAL_LATENCY Total Latency on Port x [x = 0..7] [31:0] read-write 0 4294967295 BURST Type of Burst on Port x [x = 0..7] [18:16] read-write true SINGLE Single transfer 0 INCR Incrementing burst of unspecified length 1 WRAP4 4-beat wrapping burst 2 INCR4 4-beat incrementing burst 3 WRAP8 8-beat wrapping burst 4 INCR8 8-beat incrementing burst 5 WRAP16 16-beat wrapping burst 6 INCR16 16-beat incrementing burst 7 SIZE Transfer Size on Port x [x = 0..7] [22:20] read-write true _8BITS Byte transfer 0 _16BITS Halfword transfer 1 _32BITS Word transfer 2 _64BITS Dword transfer 3 READ_WRITE Read or Write Access on Port x [x = 0..7] [24:24] read-write MR Mode Register 0x0 0x20 read-write MODE MPDDRC Command Mode [2:0] read-write true NORMAL_CMD Normal Mode. Any access to the MPDDRC is decoded normally. To activate this mode, the command must be followed by a write to the DDR-SDRAM. 0 NOP_CMD The MPDDRC issues a NOP command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. 1 PRCGALL_CMD The MPDDRC issues the All Banks Precharge command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. 2 LMR_CMD The MPDDRC issues a Load Mode Register command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. 3 RFSH_CMD The MPDDRC issues an Autorefresh command when the DDR-SDRAM device is accessed regardless of the cycle. Previously, an All Banks Precharge command must be issued. To activate this mode, the command must be followed by a write to the DDR-SDRAM. 4 EXT_LMR_CMD The MPDDRC issues an Extended Load Mode Register command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. The write in the DDR-SDRAM must be done in the appropriate bank. 5 DEEP_CALIB_MD Deep Power mode: Access to Deep Powerdown modeCalibration command: to calibrate RTT and RON values for the Process Voltage Temperature (PVT) (DDR3-SDRAM device) 6 LPDDR2_LPDDR3_CMD The MPDDRC issues an LPDDR2/LPDDR3 Mode Register command when the device is accessed regardless of the cycle. To activate this mode, the Mode Register command must be followed by a write to the low-power DDR2-SDRAM or to the low-power DDR3-SDRAM. 7 DAI Device Autoinitialization Status (read-only) [4:4] read-write true DAI_COMPLETE DAI complete 0 DAI_IN_PROGESSS DAI still in progress 1 MRS Mode Register Select LPDDR2/LPDDR3 [15:8] read-write 0 255 OCMS OCMS Register 0x38 0x20 read-write SCR_EN Scrambling Enable [0:0] read-write OCMS_KEY1 OCMS KEY1 Register 0x3C 0x20 write-only KEY1 Off-chip Memory Scrambling (OCMS) Key Part 1 [31:0] read-write 0 4294967295 OCMS_KEY2 OCMS KEY2 Register 0x40 0x20 write-only KEY2 Off-chip Memory Scrambling (OCMS) Key Part 2 [31:0] read-write 0 4294967295 RD_DATA_PATH Read Data Path Register 0x5C 0x20 read-write SHIFT_SAMPLING Shift Sampling Point of Data [1:0] read-write true NO_SHIFT Initial sampling point. 0 SHIFT_ONE_CYCLE Sampling point is shifted by one cycle. 1 SHIFT_TWO_CYCLES Sampling point is shifted by two cycles. 2 SHIFT_THREE_CYCLES Sampling point is shifted by three cycles, unique for LPDDR2 and DDR3 and LPDDR3.Not applicable for DDR2 and LPDDR1 devices. 3 REQ_PORT_0123 Request Port 0-1-2-3 Register 0x4C 0x20 read-write NRQ_NWD_BDW_P0 Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 [7:0] read-write 0 255 NRQ_NWD_BDW_P1 Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 [15:8] read-write 0 255 NRQ_NWD_BDW_P2 Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 [23:16] read-write 0 255 NRQ_NWD_BDW_P3 Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 [31:24] read-write 0 255 REQ_PORT_4567 Request Port 4-5-6-7 Register 0x50 0x20 read-write NRQ_NWD_BDW_P4 Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 [7:0] read-write 0 255 NRQ_NWD_BDW_P5 Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 [15:8] read-write 0 255 NRQ_NWD_BDW_P6 Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 [23:16] read-write 0 255 NRQ_NWD_BDW_P7 Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 [31:24] read-write 0 255 RTR Refresh Timer Register 0x4 0x20 read-write COUNT MPDDRC Refresh Timer Count [11:0] read-write 0 4095 ADJ_REF Adjust Refresh Rate [16:16] read-write REF_PB Refresh Per Bank [17:17] read-write MR4_VALUE Content of MR4 Register (read-only) [22:20] read-write 0 7 TIMEOUT Timeout Register 0x48 0x20 read-write TIMEOUT_P0 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 [3:0] read-write 0 15 TIMEOUT_P1 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 [7:4] read-write 0 15 TIMEOUT_P2 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 [11:8] read-write 0 15 TIMEOUT_P3 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 [15:12] read-write 0 15 TIMEOUT_P4 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 [19:16] read-write 0 15 TIMEOUT_P5 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 [23:20] read-write 0 15 TIMEOUT_P6 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 [27:24] read-write 0 15 TIMEOUT_P7 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 [31:28] read-write 0 15 TPR0 Timing Parameter 0 Register 0xC 0x20 read-write TRAS Active to Precharge Delay [3:0] read-write 0 15 TRCD Row to Column Delay [7:4] read-write 0 15 TWR Write Recovery Delay [11:8] read-write 0 15 TRC Row Cycle Delay [15:12] read-write 0 15 TRP Row Precharge Delay [19:16] read-write 0 15 TRRD Active BankA to Active BankB [23:20] read-write 0 15 TWTR Internal Write to Read Delay [27:24] read-write 0 15 TMRD Load Mode Register Command to Activate or Refresh Command [31:28] read-write 0 15 TPR1 Timing Parameter 1 Register 0x10 0x20 read-write TRFC Row Cycle Delay [6:0] read-write 0 127 TXSNR Exit Self-refresh Delay to Non-Read Command [15:8] read-write 0 255 TXSRD Exit Self-refresh Delay to Read Command [23:16] read-write 0 255 TXP Exit Powerdown Delay to First Command [27:24] read-write 0 15 TPR2 Timing Parameter 2 Register 0x14 0x20 read-write TXARD Exit Active Power Down Delay to Read Command in Mode "Fast Exit" [3:0] read-write 0 15 TXARDS Exit Active Power Down Delay to Read Command in Mode "Slow Exit" [7:4] read-write 0 15 TRPA Row Precharge All Delay [11:8] read-write 0 15 TRTP Read to Precharge [14:12] read-write 0 7 TFAW Four Active Windows [19:16] read-write 0 15 WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 4473938 WPSR Write Protection Status Register 0xE8 0x20 read-only WPVS Write Protection Enable [0:0] read-write WPVSRC Write Protection Violation Source [23:8] read-write 0 65535 PDMIC Pulse Density Modulation Interface Controller 0xF8018000 0x0 0x8 registers 0x14 0x14 registers 0x58 0x8 registers 0xE4 0x8 registers CDR Converted Data Register 0x14 0x20 read-only DATA Data Converted [31:0] read-write 0 4294967295 CR Control Register 0x0 0x20 read-write SWRST Software Reset [0:0] read-write ENPDM Enable PDM [4:4] read-write DSPR0 DSP Configuration Register 0 0x58 0x20 read-write HPFBYP High-Pass Filter Bypass [1:1] read-write SINBYP SINCC Filter Bypass [2:2] read-write SIZE Data Size [3:3] read-write OSR Global Oversampling Ratio [6:4] read-write true _128 Global Oversampling ratio is 128 (SINC filter oversampling ratio is 64) 0 _64 Global Oversampling ratio is 64 (SINC filter oversampling ratio is 32) 1 SCALE Data Scale [11:8] read-write 0 15 SHIFT Data Shift [15:12] read-write 0 15 DSPR1 DSP Configuration Register 1 0x5C 0x20 read-write DGAIN Gain Correction [14:0] read-write 0 32767 OFFSET Offset Correction [31:16] read-write 0 65535 IDR Interrupt Disable Register 0x1C 0x20 write-only DRDY Data Ready Interrupt Disable [24:24] read-write OVRE General Overrun Error Interrupt Disable [25:25] read-write IER Interrupt Enable Register 0x18 0x20 write-only DRDY Data Ready Interrupt Enable [24:24] read-write OVRE Overrun Error Interrupt Enable [25:25] read-write IMR Interrupt Mask Register 0x20 0x20 read-only DRDY Data Ready Interrupt Mask [24:24] read-write OVRE General Overrun Error Interrupt Mask [25:25] read-write ISR Interrupt Status Register 0x24 0x20 read-only FIFOCNT FIFO Count [23:16] read-write 0 255 DRDY Data Ready (cleared by reading PDMIC_CDR) [24:24] read-write OVRE Overrun Error (cleared on read) [25:25] read-write MR Mode Register 0x4 0x20 read-write CLKS Clock Source Selection [4:4] read-write PRESCAL Prescaler Rate Selection [14:8] read-write 0 127 WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 4277315 WPSR Write Protection Status Register 0xE8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [23:8] read-write 0 65535 PIO Parallel Input/Output Controller. 0xFC038000 0x0 0x1000 registers PIO_WPMR PIO Write Protection Mode Register. 0x5E0 0x20 write-only WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 5261647 PIO_WPSR Write Protection Status Register. 0x5E4 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [23:8] read-write 0 65535 PIO_MSKR0 PIO Mask Register. 0x000 MSK0 Selects the I/O line 0 to be configured when writing the PIO Configuration Register. 0 1 MSK1 Selects the I/O line 1 to be configured when writing the PIO Configuration Register. 1 1 MSK2 Selects the I/O line 2 to be configured when writing the PIO Configuration Register. 2 1 MSK3 Selects the I/O line 3 to be configured when writing the PIO Configuration Register. 3 1 MSK4 Selects the I/O line 4 to be configured when writing the PIO Configuration Register. 4 1 MSK5 Selects the I/O line 5 to be configured when writing the PIO Configuration Register. 5 1 MSK6 Selects the I/O line 6 to be configured when writing the PIO Configuration Register. 6 1 MSK7 Selects the I/O line 7 to be configured when writing the PIO Configuration Register. 7 1 MSK8 Selects the I/O line 8 to be configured when writing the PIO Configuration Register. 8 1 MSK9 Selects the I/O line 9 to be configured when writing the PIO Configuration Register. 9 1 MSK10 Selects the I/O line 10 to be configured when writing the PIO Configuration Register. 10 1 MSK11 Selects the I/O line 11 to be configured when writing the PIO Configuration Register. 11 1 MSK12 Selects the I/O line 12 to be configured when writing the PIO Configuration Register. 12 1 MSK13 Selects the I/O line 13 to be configured when writing the PIO Configuration Register. 13 1 MSK14 Selects the I/O line 14 to be configured when writing the PIO Configuration Register. 14 1 MSK15 Selects the I/O line 15 to be configured when writing the PIO Configuration Register. 15 1 MSK16 Selects the I/O line 16 to be configured when writing the PIO Configuration Register. 16 1 MSK17 Selects the I/O line 17 to be configured when writing the PIO Configuration Register. 17 1 MSK18 Selects the I/O line 18 to be configured when writing the PIO Configuration Register. 18 1 MSK19 Selects the I/O line 19 to be configured when writing the PIO Configuration Register. 19 1 MSK20 Selects the I/O line 20 to be configured when writing the PIO Configuration Register. 20 1 MSK21 Selects the I/O line 21 to be configured when writing the PIO Configuration Register. 21 1 MSK22 Selects the I/O line 22 to be configured when writing the PIO Configuration Register. 22 1 MSK23 Selects the I/O line 23 to be configured when writing the PIO Configuration Register. 23 1 MSK24 Selects the I/O line 24 to be configured when writing the PIO Configuration Register. 24 1 MSK25 Selects the I/O line 25 to be configured when writing the PIO Configuration Register. 25 1 MSK26 Selects the I/O line 26 to be configured when writing the PIO Configuration Register. 26 1 MSK27 Selects the I/O line 27 to be configured when writing the PIO Configuration Register. 27 1 MSK28 Selects the I/O line 28 to be configured when writing the PIO Configuration Register. 28 1 MSK29 Selects the I/O line 29 to be configured when writing the PIO Configuration Register. 29 1 MSK30 Selects the I/O line 30 to be configured when writing the PIO Configuration Register. 30 1 PIO_MSKR1 PIO Mask Register. 0x040 MSK0 Selects the I/O line 0 to be configured when writing the PIO Configuration Register. 0 1 MSK1 Selects the I/O line 1 to be configured when writing the PIO Configuration Register. 1 1 MSK2 Selects the I/O line 2 to be configured when writing the PIO Configuration Register. 2 1 MSK3 Selects the I/O line 3 to be configured when writing the PIO Configuration Register. 3 1 MSK4 Selects the I/O line 4 to be configured when writing the PIO Configuration Register. 4 1 MSK5 Selects the I/O line 5 to be configured when writing the PIO Configuration Register. 5 1 MSK6 Selects the I/O line 6 to be configured when writing the PIO Configuration Register. 6 1 MSK7 Selects the I/O line 7 to be configured when writing the PIO Configuration Register. 7 1 MSK8 Selects the I/O line 8 to be configured when writing the PIO Configuration Register. 8 1 MSK9 Selects the I/O line 9 to be configured when writing the PIO Configuration Register. 9 1 MSK10 Selects the I/O line 10 to be configured when writing the PIO Configuration Register. 10 1 MSK11 Selects the I/O line 11 to be configured when writing the PIO Configuration Register. 11 1 MSK12 Selects the I/O line 12 to be configured when writing the PIO Configuration Register. 12 1 MSK13 Selects the I/O line 13 to be configured when writing the PIO Configuration Register. 13 1 MSK14 Selects the I/O line 14 to be configured when writing the PIO Configuration Register. 14 1 MSK15 Selects the I/O line 15 to be configured when writing the PIO Configuration Register. 15 1 MSK16 Selects the I/O line 16 to be configured when writing the PIO Configuration Register. 16 1 MSK17 Selects the I/O line 17 to be configured when writing the PIO Configuration Register. 17 1 MSK18 Selects the I/O line 18 to be configured when writing the PIO Configuration Register. 18 1 MSK19 Selects the I/O line 19 to be configured when writing the PIO Configuration Register. 19 1 MSK20 Selects the I/O line 20 to be configured when writing the PIO Configuration Register. 20 1 MSK21 Selects the I/O line 21 to be configured when writing the PIO Configuration Register. 21 1 MSK22 Selects the I/O line 22 to be configured when writing the PIO Configuration Register. 22 1 MSK23 Selects the I/O line 23 to be configured when writing the PIO Configuration Register. 23 1 MSK24 Selects the I/O line 24 to be configured when writing the PIO Configuration Register. 24 1 MSK25 Selects the I/O line 25 to be configured when writing the PIO Configuration Register. 25 1 MSK26 Selects the I/O line 26 to be configured when writing the PIO Configuration Register. 26 1 MSK27 Selects the I/O line 27 to be configured when writing the PIO Configuration Register. 27 1 MSK28 Selects the I/O line 28 to be configured when writing the PIO Configuration Register. 28 1 MSK29 Selects the I/O line 29 to be configured when writing the PIO Configuration Register. 29 1 MSK30 Selects the I/O line 30 to be configured when writing the PIO Configuration Register. 30 1 PIO_MSKR2 PIO Mask Register. 0x080 MSK0 Selects the I/O line 0 to be configured when writing the PIO Configuration Register. 0 1 MSK1 Selects the I/O line 1 to be configured when writing the PIO Configuration Register. 1 1 MSK2 Selects the I/O line 2 to be configured when writing the PIO Configuration Register. 2 1 MSK3 Selects the I/O line 3 to be configured when writing the PIO Configuration Register. 3 1 MSK4 Selects the I/O line 4 to be configured when writing the PIO Configuration Register. 4 1 MSK5 Selects the I/O line 5 to be configured when writing the PIO Configuration Register. 5 1 MSK6 Selects the I/O line 6 to be configured when writing the PIO Configuration Register. 6 1 MSK7 Selects the I/O line 7 to be configured when writing the PIO Configuration Register. 7 1 MSK8 Selects the I/O line 8 to be configured when writing the PIO Configuration Register. 8 1 MSK9 Selects the I/O line 9 to be configured when writing the PIO Configuration Register. 9 1 MSK10 Selects the I/O line 10 to be configured when writing the PIO Configuration Register. 10 1 MSK11 Selects the I/O line 11 to be configured when writing the PIO Configuration Register. 11 1 MSK12 Selects the I/O line 12 to be configured when writing the PIO Configuration Register. 12 1 MSK13 Selects the I/O line 13 to be configured when writing the PIO Configuration Register. 13 1 MSK14 Selects the I/O line 14 to be configured when writing the PIO Configuration Register. 14 1 MSK15 Selects the I/O line 15 to be configured when writing the PIO Configuration Register. 15 1 MSK16 Selects the I/O line 16 to be configured when writing the PIO Configuration Register. 16 1 MSK17 Selects the I/O line 17 to be configured when writing the PIO Configuration Register. 17 1 MSK18 Selects the I/O line 18 to be configured when writing the PIO Configuration Register. 18 1 MSK19 Selects the I/O line 19 to be configured when writing the PIO Configuration Register. 19 1 MSK20 Selects the I/O line 20 to be configured when writing the PIO Configuration Register. 20 1 MSK21 Selects the I/O line 21 to be configured when writing the PIO Configuration Register. 21 1 MSK22 Selects the I/O line 22 to be configured when writing the PIO Configuration Register. 22 1 MSK23 Selects the I/O line 23 to be configured when writing the PIO Configuration Register. 23 1 MSK24 Selects the I/O line 24 to be configured when writing the PIO Configuration Register. 24 1 MSK25 Selects the I/O line 25 to be configured when writing the PIO Configuration Register. 25 1 MSK26 Selects the I/O line 26 to be configured when writing the PIO Configuration Register. 26 1 MSK27 Selects the I/O line 27 to be configured when writing the PIO Configuration Register. 27 1 MSK28 Selects the I/O line 28 to be configured when writing the PIO Configuration Register. 28 1 MSK29 Selects the I/O line 29 to be configured when writing the PIO Configuration Register. 29 1 MSK30 Selects the I/O line 30 to be configured when writing the PIO Configuration Register. 30 1 PIO_MSKR3 PIO Mask Register. 0x0C0 MSK0 Selects the I/O line 0 to be configured when writing the PIO Configuration Register. 0 1 MSK1 Selects the I/O line 1 to be configured when writing the PIO Configuration Register. 1 1 MSK2 Selects the I/O line 2 to be configured when writing the PIO Configuration Register. 2 1 MSK3 Selects the I/O line 3 to be configured when writing the PIO Configuration Register. 3 1 MSK4 Selects the I/O line 4 to be configured when writing the PIO Configuration Register. 4 1 MSK5 Selects the I/O line 5 to be configured when writing the PIO Configuration Register. 5 1 MSK6 Selects the I/O line 6 to be configured when writing the PIO Configuration Register. 6 1 MSK7 Selects the I/O line 7 to be configured when writing the PIO Configuration Register. 7 1 MSK8 Selects the I/O line 8 to be configured when writing the PIO Configuration Register. 8 1 MSK9 Selects the I/O line 9 to be configured when writing the PIO Configuration Register. 9 1 MSK10 Selects the I/O line 10 to be configured when writing the PIO Configuration Register. 10 1 MSK11 Selects the I/O line 11 to be configured when writing the PIO Configuration Register. 11 1 MSK12 Selects the I/O line 12 to be configured when writing the PIO Configuration Register. 12 1 MSK13 Selects the I/O line 13 to be configured when writing the PIO Configuration Register. 13 1 MSK14 Selects the I/O line 14 to be configured when writing the PIO Configuration Register. 14 1 MSK15 Selects the I/O line 15 to be configured when writing the PIO Configuration Register. 15 1 MSK16 Selects the I/O line 16 to be configured when writing the PIO Configuration Register. 16 1 MSK17 Selects the I/O line 17 to be configured when writing the PIO Configuration Register. 17 1 MSK18 Selects the I/O line 18 to be configured when writing the PIO Configuration Register. 18 1 MSK19 Selects the I/O line 19 to be configured when writing the PIO Configuration Register. 19 1 MSK20 Selects the I/O line 20 to be configured when writing the PIO Configuration Register. 20 1 MSK21 Selects the I/O line 21 to be configured when writing the PIO Configuration Register. 21 1 MSK22 Selects the I/O line 22 to be configured when writing the PIO Configuration Register. 22 1 MSK23 Selects the I/O line 23 to be configured when writing the PIO Configuration Register. 23 1 MSK24 Selects the I/O line 24 to be configured when writing the PIO Configuration Register. 24 1 MSK25 Selects the I/O line 25 to be configured when writing the PIO Configuration Register. 25 1 MSK26 Selects the I/O line 26 to be configured when writing the PIO Configuration Register. 26 1 MSK27 Selects the I/O line 27 to be configured when writing the PIO Configuration Register. 27 1 MSK28 Selects the I/O line 28 to be configured when writing the PIO Configuration Register. 28 1 MSK29 Selects the I/O line 29 to be configured when writing the PIO Configuration Register. 29 1 MSK30 Selects the I/O line 30 to be configured when writing the PIO Configuration Register. 30 1 PIO_CFGR0 PIO Configuration Register. 0x004 0x20 read-write ICFS Interrupt Configuration Freeze Status. 30 1 read-only PCFS Physical Configuration Freeze Status. 29 1 read-only EVTSEL Event Selection. 24 3 EVTSEL read-write FALLING Event detection on input falling edge. 0 RISING Event detection on input rising edge. 1 BOTH Event detection on input both edge. 2 LOW Event detection on low level input. 3 HIGH Event detection on high level input. 4 DRVSTR Drive Strength. 16 2 DRVSTR read-write LO0 Low drive. 0 LO1 Low drive. 1 ME Medium drive. 2 HI Medium drive. 3 SCHMITT Schmitt Trigger. 15 1 SCHMITT read-write ENABLED Schmitt trigger is enabled for the selected I/O lines. 0 DISABLED Schmitt trigger is disabled for the selected I/O lines. 1 OPD Open Drain. 14 1 OPD read-write DISABLED Open drain is disabled for the selected I/O lines. 0 ENABLED Open drain is enabled for the selected I/O lines. 1 IFSCEN Input Filter Slow Clock Enable. 13 1 IFSCEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 IFEN Input Filter Enable. 12 1 IFEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 PDEN Pull-Down Enable. 10 1 PDEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 PUEN Pull-Up Enable. 9 1 PUEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 DIR Direction. 8 1 DIR read-write INPUT The selected I/O lines are pure inputs. 0 OUTPUT The selected I/O lines are enabled in output. 1 FUNC I/O Line Function. 0 3 FUNC read-write GPIO Selects GPIO mode for the selected I/O lines. 0 PERIPH_A Selects peripheral A for the selected I/O lines. 1 PERIPH_B Selects peripheral B for the selected I/O lines. 2 PERIPH_C Selects peripheral C for the selected I/O lines. 3 PERIPH_D Selects peripheral D for the selected I/O lines. 4 PERIPH_E Selects peripheral E for the selected I/O lines. 5 PERIPH_F Selects peripheral F for the selected I/O lines. 6 PIO_CFGR1 PIO Configuration Register. 0x044 0x20 read-write ICFS Interrupt Configuration Freeze Status. 30 1 read-only PCFS Physical Configuration Freeze Status. 29 1 read-only EVTSEL Event Selection. 24 3 EVTSEL read-write FALLING Event detection on input falling edge. 0 RISING Event detection on input rising edge. 1 BOTH Event detection on input both edge. 2 LOW Event detection on low level input. 3 HIGH Event detection on high level input. 4 DRVSTR Drive Strength. 16 2 DRVSTR read-write LO0 Low drive. 0 LO1 Low drive. 1 ME Medium drive. 2 HI Medium drive. 3 SCHMITT Schmitt Trigger. 15 1 SCHMITT read-write ENABLED Schmitt trigger is enabled for the selected I/O lines. 0 DISABLED Schmitt trigger is disabled for the selected I/O lines. 1 OPD Open Drain. 14 1 OPD read-write DISABLED Open drain is disabled for the selected I/O lines. 0 ENABLED Open drain is enabled for the selected I/O lines. 1 IFSCEN Input Filter Slow Clock Enable. 13 1 IFSCEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 IFEN Input Filter Enable. 12 1 IFEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 PDEN Pull-Down Enable. 10 1 PDEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 PUEN Pull-Up Enable. 9 1 PUEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 DIR Direction. 8 1 DIR read-write INPUT The selected I/O lines are pure inputs. 0 OUTPUT The selected I/O lines are enabled in output. 1 FUNC I/O Line Function. 0 3 FUNC read-write GPIO Selects GPIO mode for the selected I/O lines. 0 PERIPH_A Selects peripheral A for the selected I/O lines. 1 PERIPH_B Selects peripheral B for the selected I/O lines. 2 PERIPH_C Selects peripheral C for the selected I/O lines. 3 PERIPH_D Selects peripheral D for the selected I/O lines. 4 PERIPH_E Selects peripheral E for the selected I/O lines. 5 PERIPH_F Selects peripheral F for the selected I/O lines. 6 PIO_CFGR2 PIO Configuration Register. 0x084 0x20 read-write ICFS Interrupt Configuration Freeze Status. 30 1 read-only PCFS Physical Configuration Freeze Status. 29 1 read-only EVTSEL Event Selection. 24 3 EVTSEL read-write FALLING Event detection on input falling edge. 0 RISING Event detection on input rising edge. 1 BOTH Event detection on input both edge. 2 LOW Event detection on low level input. 3 HIGH Event detection on high level input. 4 DRVSTR Drive Strength. 16 2 DRVSTR read-write LO0 Low drive. 0 LO1 Low drive. 1 ME Medium drive. 2 HI Medium drive. 3 SCHMITT Schmitt Trigger. 15 1 SCHMITT read-write ENABLED Schmitt trigger is enabled for the selected I/O lines. 0 DISABLED Schmitt trigger is disabled for the selected I/O lines. 1 OPD Open Drain. 14 1 OPD read-write DISABLED Open drain is disabled for the selected I/O lines. 0 ENABLED Open drain is enabled for the selected I/O lines. 1 IFSCEN Input Filter Slow Clock Enable. 13 1 IFSCEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 IFEN Input Filter Enable. 12 1 IFEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 PDEN Pull-Down Enable. 10 1 PDEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 PUEN Pull-Up Enable. 9 1 PUEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 DIR Direction. 8 1 DIR read-write INPUT The selected I/O lines are pure inputs. 0 OUTPUT The selected I/O lines are enabled in output. 1 FUNC I/O Line Function. 0 3 FUNC read-write GPIO Selects GPIO mode for the selected I/O lines. 0 PERIPH_A Selects peripheral A for the selected I/O lines. 1 PERIPH_B Selects peripheral B for the selected I/O lines. 2 PERIPH_C Selects peripheral C for the selected I/O lines. 3 PERIPH_D Selects peripheral D for the selected I/O lines. 4 PERIPH_E Selects peripheral E for the selected I/O lines. 5 PERIPH_F Selects peripheral F for the selected I/O lines. 6 PIO_CFGR3 PIO Configuration Register. 0x0C4 0x20 read-write ICFS Interrupt Configuration Freeze Status. 30 1 read-only PCFS Physical Configuration Freeze Status. 29 1 read-only EVTSEL Event Selection. 24 3 EVTSEL read-write FALLING Event detection on input falling edge. 0 RISING Event detection on input rising edge. 1 BOTH Event detection on input both edge. 2 LOW Event detection on low level input. 3 HIGH Event detection on high level input. 4 DRVSTR Drive Strength. 16 2 DRVSTR read-write LO0 Low drive. 0 LO1 Low drive. 1 ME Medium drive. 2 HI Medium drive. 3 SCHMITT Schmitt Trigger. 15 1 SCHMITT read-write ENABLED Schmitt trigger is enabled for the selected I/O lines. 0 DISABLED Schmitt trigger is disabled for the selected I/O lines. 1 OPD Open Drain. 14 1 OPD read-write DISABLED Open drain is disabled for the selected I/O lines. 0 ENABLED Open drain is enabled for the selected I/O lines. 1 IFSCEN Input Filter Slow Clock Enable. 13 1 IFSCEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 IFEN Input Filter Enable. 12 1 IFEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 PDEN Pull-Down Enable. 10 1 PDEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 PUEN Pull-Up Enable. 9 1 PUEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 DIR Direction. 8 1 DIR read-write INPUT The selected I/O lines are pure inputs. 0 OUTPUT The selected I/O lines are enabled in output. 1 FUNC I/O Line Function. 0 3 FUNC read-write GPIO Selects GPIO mode for the selected I/O lines. 0 PERIPH_A Selects peripheral A for the selected I/O lines. 1 PERIPH_B Selects peripheral B for the selected I/O lines. 2 PERIPH_C Selects peripheral C for the selected I/O lines. 3 PERIPH_D Selects peripheral D for the selected I/O lines. 4 PERIPH_E Selects peripheral E for the selected I/O lines. 5 PERIPH_F Selects peripheral F for the selected I/O lines. 6 PIO_PDSR0 PIO Pin Data Status Register. 0x008 P0 The input data status of the I/O line 0. 0 1 P1 The input data status of the I/O line 1. 1 1 P2 The input data status of the I/O line 2. 2 1 P3 The input data status of the I/O line 3. 3 1 P4 The input data status of the I/O line 4. 4 1 P5 The input data status of the I/O line 5. 5 1 P6 The input data status of the I/O line 6. 6 1 P7 The input data status of the I/O line 7. 7 1 P8 The input data status of the I/O line 8. 8 1 P9 The input data status of the I/O line 9. 9 1 P10 The input data status of the I/O line 10. 10 1 P11 The input data status of the I/O line 11. 11 1 P12 The input data status of the I/O line 12. 12 1 P13 The input data status of the I/O line 13. 13 1 P14 The input data status of the I/O line 14. 14 1 P15 The input data status of the I/O line 15. 15 1 P16 The input data status of the I/O line 16. 16 1 P17 The input data status of the I/O line 17. 17 1 P18 The input data status of the I/O line 18. 18 1 P19 The input data status of the I/O line 19. 19 1 P20 The input data status of the I/O line 20. 20 1 P21 The input data status of the I/O line 21. 21 1 P22 The input data status of the I/O line 22. 22 1 P23 The input data status of the I/O line 23. 23 1 P24 The input data status of the I/O line 24. 24 1 P25 The input data status of the I/O line 25. 25 1 P26 The input data status of the I/O line 26. 26 1 P27 The input data status of the I/O line 27. 27 1 P28 The input data status of the I/O line 28. 28 1 P29 The input data status of the I/O line 29. 29 1 P30 The input data status of the I/O line 30. 30 1 P31 The input data status of the I/O line 31. 31 1 PIO_PDSR1 PIO Pin Data Status Register. 0x048 P0 The input data status of the I/O line 0. 0 1 P1 The input data status of the I/O line 1. 1 1 P2 The input data status of the I/O line 2. 2 1 P3 The input data status of the I/O line 3. 3 1 P4 The input data status of the I/O line 4. 4 1 P5 The input data status of the I/O line 5. 5 1 P6 The input data status of the I/O line 6. 6 1 P7 The input data status of the I/O line 7. 7 1 P8 The input data status of the I/O line 8. 8 1 P9 The input data status of the I/O line 9. 9 1 P10 The input data status of the I/O line 10. 10 1 P11 The input data status of the I/O line 11. 11 1 P12 The input data status of the I/O line 12. 12 1 P13 The input data status of the I/O line 13. 13 1 P14 The input data status of the I/O line 14. 14 1 P15 The input data status of the I/O line 15. 15 1 P16 The input data status of the I/O line 16. 16 1 P17 The input data status of the I/O line 17. 17 1 P18 The input data status of the I/O line 18. 18 1 P19 The input data status of the I/O line 19. 19 1 P20 The input data status of the I/O line 20. 20 1 P21 The input data status of the I/O line 21. 21 1 P22 The input data status of the I/O line 22. 22 1 P23 The input data status of the I/O line 23. 23 1 P24 The input data status of the I/O line 24. 24 1 P25 The input data status of the I/O line 25. 25 1 P26 The input data status of the I/O line 26. 26 1 P27 The input data status of the I/O line 27. 27 1 P28 The input data status of the I/O line 28. 28 1 P29 The input data status of the I/O line 29. 29 1 P30 The input data status of the I/O line 30. 30 1 P31 The input data status of the I/O line 31. 31 1 PIO_PDSR2 PIO Pin Data Status Register. 0x088 P0 The input data status of the I/O line 0. 0 1 P1 The input data status of the I/O line 1. 1 1 P2 The input data status of the I/O line 2. 2 1 P3 The input data status of the I/O line 3. 3 1 P4 The input data status of the I/O line 4. 4 1 P5 The input data status of the I/O line 5. 5 1 P6 The input data status of the I/O line 6. 6 1 P7 The input data status of the I/O line 7. 7 1 P8 The input data status of the I/O line 8. 8 1 P9 The input data status of the I/O line 9. 9 1 P10 The input data status of the I/O line 10. 10 1 P11 The input data status of the I/O line 11. 11 1 P12 The input data status of the I/O line 12. 12 1 P13 The input data status of the I/O line 13. 13 1 P14 The input data status of the I/O line 14. 14 1 P15 The input data status of the I/O line 15. 15 1 P16 The input data status of the I/O line 16. 16 1 P17 The input data status of the I/O line 17. 17 1 P18 The input data status of the I/O line 18. 18 1 P19 The input data status of the I/O line 19. 19 1 P20 The input data status of the I/O line 20. 20 1 P21 The input data status of the I/O line 21. 21 1 P22 The input data status of the I/O line 22. 22 1 P23 The input data status of the I/O line 23. 23 1 P24 The input data status of the I/O line 24. 24 1 P25 The input data status of the I/O line 25. 25 1 P26 The input data status of the I/O line 26. 26 1 P27 The input data status of the I/O line 27. 27 1 P28 The input data status of the I/O line 28. 28 1 P29 The input data status of the I/O line 29. 29 1 P30 The input data status of the I/O line 30. 30 1 P31 The input data status of the I/O line 31. 31 1 PIO_PDSR3 PIO Pin Data Status Register. 0x0C8 P0 The input data status of the I/O line 0. 0 1 P1 The input data status of the I/O line 1. 1 1 P2 The input data status of the I/O line 2. 2 1 P3 The input data status of the I/O line 3. 3 1 P4 The input data status of the I/O line 4. 4 1 P5 The input data status of the I/O line 5. 5 1 P6 The input data status of the I/O line 6. 6 1 P7 The input data status of the I/O line 7. 7 1 P8 The input data status of the I/O line 8. 8 1 P9 The input data status of the I/O line 9. 9 1 P10 The input data status of the I/O line 10. 10 1 P11 The input data status of the I/O line 11. 11 1 P12 The input data status of the I/O line 12. 12 1 P13 The input data status of the I/O line 13. 13 1 P14 The input data status of the I/O line 14. 14 1 P15 The input data status of the I/O line 15. 15 1 P16 The input data status of the I/O line 16. 16 1 P17 The input data status of the I/O line 17. 17 1 P18 The input data status of the I/O line 18. 18 1 P19 The input data status of the I/O line 19. 19 1 P20 The input data status of the I/O line 20. 20 1 P21 The input data status of the I/O line 21. 21 1 P22 The input data status of the I/O line 22. 22 1 P23 The input data status of the I/O line 23. 23 1 P24 The input data status of the I/O line 24. 24 1 P25 The input data status of the I/O line 25. 25 1 P26 The input data status of the I/O line 26. 26 1 P27 The input data status of the I/O line 27. 27 1 P28 The input data status of the I/O line 28. 28 1 P29 The input data status of the I/O line 29. 29 1 P30 The input data status of the I/O line 30. 30 1 P31 The input data status of the I/O line 31. 31 1 PIO_LOCKSR0 PIO Lock Status Register. 0x00C P0 The lock status status of the I/O line 0. 0 1 P1 The lock status status of the I/O line 1. 1 1 P2 The lock status status of the I/O line 2. 2 1 P3 The lock status status of the I/O line 3. 3 1 P4 The lock status status of the I/O line 4. 4 1 P5 The lock status status of the I/O line 5. 5 1 P6 The lock status status of the I/O line 6. 6 1 P7 The lock status status of the I/O line 7. 7 1 P8 The lock status status of the I/O line 8. 8 1 P9 The lock status status of the I/O line 9. 9 1 P10 The lock status status of the I/O line 10. 10 1 P11 The lock status status of the I/O line 11. 11 1 P12 The lock status status of the I/O line 12. 12 1 P13 The lock status status of the I/O line 13. 13 1 P14 The lock status status of the I/O line 14. 14 1 P15 The lock status status of the I/O line 15. 15 1 P16 The lock status status of the I/O line 16. 16 1 P17 The lock status status of the I/O line 17. 17 1 P18 The lock status status of the I/O line 18. 18 1 P19 The lock status status of the I/O line 19. 19 1 P20 The lock status status of the I/O line 20. 20 1 P21 The lock status status of the I/O line 21. 21 1 P22 The lock status status of the I/O line 22. 22 1 P23 The lock status status of the I/O line 23. 23 1 P24 The lock status status of the I/O line 24. 24 1 P25 The lock status status of the I/O line 25. 25 1 P26 The lock status status of the I/O line 26. 26 1 P27 The lock status status of the I/O line 27. 27 1 P28 The lock status status of the I/O line 28. 28 1 P29 The lock status status of the I/O line 29. 29 1 P30 The lock status status of the I/O line 30. 30 1 P31 The lock status status of the I/O line 31. 31 1 PIO_LOCKSR1 PIO Lock Status Register. 0x04C P0 The lock status status of the I/O line 0. 0 1 P1 The lock status status of the I/O line 1. 1 1 P2 The lock status status of the I/O line 2. 2 1 P3 The lock status status of the I/O line 3. 3 1 P4 The lock status status of the I/O line 4. 4 1 P5 The lock status status of the I/O line 5. 5 1 P6 The lock status status of the I/O line 6. 6 1 P7 The lock status status of the I/O line 7. 7 1 P8 The lock status status of the I/O line 8. 8 1 P9 The lock status status of the I/O line 9. 9 1 P10 The lock status status of the I/O line 10. 10 1 P11 The lock status status of the I/O line 11. 11 1 P12 The lock status status of the I/O line 12. 12 1 P13 The lock status status of the I/O line 13. 13 1 P14 The lock status status of the I/O line 14. 14 1 P15 The lock status status of the I/O line 15. 15 1 P16 The lock status status of the I/O line 16. 16 1 P17 The lock status status of the I/O line 17. 17 1 P18 The lock status status of the I/O line 18. 18 1 P19 The lock status status of the I/O line 19. 19 1 P20 The lock status status of the I/O line 20. 20 1 P21 The lock status status of the I/O line 21. 21 1 P22 The lock status status of the I/O line 22. 22 1 P23 The lock status status of the I/O line 23. 23 1 P24 The lock status status of the I/O line 24. 24 1 P25 The lock status status of the I/O line 25. 25 1 P26 The lock status status of the I/O line 26. 26 1 P27 The lock status status of the I/O line 27. 27 1 P28 The lock status status of the I/O line 28. 28 1 P29 The lock status status of the I/O line 29. 29 1 P30 The lock status status of the I/O line 30. 30 1 P31 The lock status status of the I/O line 31. 31 1 PIO_LOCKSR2 PIO Lock Status Register. 0x08C P0 The lock status status of the I/O line 0. 0 1 P1 The lock status status of the I/O line 1. 1 1 P2 The lock status status of the I/O line 2. 2 1 P3 The lock status status of the I/O line 3. 3 1 P4 The lock status status of the I/O line 4. 4 1 P5 The lock status status of the I/O line 5. 5 1 P6 The lock status status of the I/O line 6. 6 1 P7 The lock status status of the I/O line 7. 7 1 P8 The lock status status of the I/O line 8. 8 1 P9 The lock status status of the I/O line 9. 9 1 P10 The lock status status of the I/O line 10. 10 1 P11 The lock status status of the I/O line 11. 11 1 P12 The lock status status of the I/O line 12. 12 1 P13 The lock status status of the I/O line 13. 13 1 P14 The lock status status of the I/O line 14. 14 1 P15 The lock status status of the I/O line 15. 15 1 P16 The lock status status of the I/O line 16. 16 1 P17 The lock status status of the I/O line 17. 17 1 P18 The lock status status of the I/O line 18. 18 1 P19 The lock status status of the I/O line 19. 19 1 P20 The lock status status of the I/O line 20. 20 1 P21 The lock status status of the I/O line 21. 21 1 P22 The lock status status of the I/O line 22. 22 1 P23 The lock status status of the I/O line 23. 23 1 P24 The lock status status of the I/O line 24. 24 1 P25 The lock status status of the I/O line 25. 25 1 P26 The lock status status of the I/O line 26. 26 1 P27 The lock status status of the I/O line 27. 27 1 P28 The lock status status of the I/O line 28. 28 1 P29 The lock status status of the I/O line 29. 29 1 P30 The lock status status of the I/O line 30. 30 1 P31 The lock status status of the I/O line 31. 31 1 PIO_LOCKSR3 PIO Lock Status Register. 0x0CC P0 The lock status status of the I/O line 0. 0 1 P1 The lock status status of the I/O line 1. 1 1 P2 The lock status status of the I/O line 2. 2 1 P3 The lock status status of the I/O line 3. 3 1 P4 The lock status status of the I/O line 4. 4 1 P5 The lock status status of the I/O line 5. 5 1 P6 The lock status status of the I/O line 6. 6 1 P7 The lock status status of the I/O line 7. 7 1 P8 The lock status status of the I/O line 8. 8 1 P9 The lock status status of the I/O line 9. 9 1 P10 The lock status status of the I/O line 10. 10 1 P11 The lock status status of the I/O line 11. 11 1 P12 The lock status status of the I/O line 12. 12 1 P13 The lock status status of the I/O line 13. 13 1 P14 The lock status status of the I/O line 14. 14 1 P15 The lock status status of the I/O line 15. 15 1 P16 The lock status status of the I/O line 16. 16 1 P17 The lock status status of the I/O line 17. 17 1 P18 The lock status status of the I/O line 18. 18 1 P19 The lock status status of the I/O line 19. 19 1 P20 The lock status status of the I/O line 20. 20 1 P21 The lock status status of the I/O line 21. 21 1 P22 The lock status status of the I/O line 22. 22 1 P23 The lock status status of the I/O line 23. 23 1 P24 The lock status status of the I/O line 24. 24 1 P25 The lock status status of the I/O line 25. 25 1 P26 The lock status status of the I/O line 26. 26 1 P27 The lock status status of the I/O line 27. 27 1 P28 The lock status status of the I/O line 28. 28 1 P29 The lock status status of the I/O line 29. 29 1 P30 The lock status status of the I/O line 30. 30 1 P31 The lock status status of the I/O line 31. 31 1 PIO_SODR0 PIO Set Output Data Register 0x010 P0 Set the output data to be driven on the I/O line 0. 0 1 P1 Set the output data to be driven on the I/O line 1. 1 1 P2 Set the output data to be driven on the I/O line 2. 2 1 P3 Set the output data to be driven on the I/O line 3. 3 1 P4 Set the output data to be driven on the I/O line 4. 4 1 P5 Set the output data to be driven on the I/O line 5. 5 1 P6 Set the output data to be driven on the I/O line 6. 6 1 P7 Set the output data to be driven on the I/O line 7. 7 1 P8 Set the output data to be driven on the I/O line 8. 8 1 P9 Set the output data to be driven on the I/O line 9. 9 1 P10 Set the output data to be driven on the I/O line 10. 10 1 P11 Set the output data to be driven on the I/O line 11. 11 1 P12 Set the output data to be driven on the I/O line 12. 12 1 P13 Set the output data to be driven on the I/O line 13. 13 1 P14 Set the output data to be driven on the I/O line 14. 14 1 P15 Set the output data to be driven on the I/O line 15. 15 1 P16 Set the output data to be driven on the I/O line 16. 16 1 P17 Set the output data to be driven on the I/O line 17. 17 1 P18 Set the output data to be driven on the I/O line 18. 18 1 P19 Set the output data to be driven on the I/O line 19. 19 1 P20 Set the output data to be driven on the I/O line 20. 20 1 P21 Set the output data to be driven on the I/O line 21. 21 1 P22 Set the output data to be driven on the I/O line 22. 22 1 P23 Set the output data to be driven on the I/O line 23. 23 1 P24 Set the output data to be driven on the I/O line 24. 24 1 P25 Set the output data to be driven on the I/O line 25. 25 1 P26 Set the output data to be driven on the I/O line 26. 26 1 P27 Set the output data to be driven on the I/O line 27. 27 1 P28 Set the output data to be driven on the I/O line 28. 28 1 P29 Set the output data to be driven on the I/O line 29. 29 1 P30 Set the output data to be driven on the I/O line 30. 30 1 P31 Set the output data to be driven on the I/O line 31. 31 1 PIO_SODR1 PIO Set Output Data Register 0x050 P0 Set the output data to be driven on the I/O line 0. 0 1 P1 Set the output data to be driven on the I/O line 1. 1 1 P2 Set the output data to be driven on the I/O line 2. 2 1 P3 Set the output data to be driven on the I/O line 3. 3 1 P4 Set the output data to be driven on the I/O line 4. 4 1 P5 Set the output data to be driven on the I/O line 5. 5 1 P6 Set the output data to be driven on the I/O line 6. 6 1 P7 Set the output data to be driven on the I/O line 7. 7 1 P8 Set the output data to be driven on the I/O line 8. 8 1 P9 Set the output data to be driven on the I/O line 9. 9 1 P10 Set the output data to be driven on the I/O line 10. 10 1 P11 Set the output data to be driven on the I/O line 11. 11 1 P12 Set the output data to be driven on the I/O line 12. 12 1 P13 Set the output data to be driven on the I/O line 13. 13 1 P14 Set the output data to be driven on the I/O line 14. 14 1 P15 Set the output data to be driven on the I/O line 15. 15 1 P16 Set the output data to be driven on the I/O line 16. 16 1 P17 Set the output data to be driven on the I/O line 17. 17 1 P18 Set the output data to be driven on the I/O line 18. 18 1 P19 Set the output data to be driven on the I/O line 19. 19 1 P20 Set the output data to be driven on the I/O line 20. 20 1 P21 Set the output data to be driven on the I/O line 21. 21 1 P22 Set the output data to be driven on the I/O line 22. 22 1 P23 Set the output data to be driven on the I/O line 23. 23 1 P24 Set the output data to be driven on the I/O line 24. 24 1 P25 Set the output data to be driven on the I/O line 25. 25 1 P26 Set the output data to be driven on the I/O line 26. 26 1 P27 Set the output data to be driven on the I/O line 27. 27 1 P28 Set the output data to be driven on the I/O line 28. 28 1 P29 Set the output data to be driven on the I/O line 29. 29 1 P30 Set the output data to be driven on the I/O line 30. 30 1 P31 Set the output data to be driven on the I/O line 31. 31 1 PIO_SODR2 PIO Set Output Data Register 0x090 P0 Set the output data to be driven on the I/O line 0. 0 1 P1 Set the output data to be driven on the I/O line 1. 1 1 P2 Set the output data to be driven on the I/O line 2. 2 1 P3 Set the output data to be driven on the I/O line 3. 3 1 P4 Set the output data to be driven on the I/O line 4. 4 1 P5 Set the output data to be driven on the I/O line 5. 5 1 P6 Set the output data to be driven on the I/O line 6. 6 1 P7 Set the output data to be driven on the I/O line 7. 7 1 P8 Set the output data to be driven on the I/O line 8. 8 1 P9 Set the output data to be driven on the I/O line 9. 9 1 P10 Set the output data to be driven on the I/O line 10. 10 1 P11 Set the output data to be driven on the I/O line 11. 11 1 P12 Set the output data to be driven on the I/O line 12. 12 1 P13 Set the output data to be driven on the I/O line 13. 13 1 P14 Set the output data to be driven on the I/O line 14. 14 1 P15 Set the output data to be driven on the I/O line 15. 15 1 P16 Set the output data to be driven on the I/O line 16. 16 1 P17 Set the output data to be driven on the I/O line 17. 17 1 P18 Set the output data to be driven on the I/O line 18. 18 1 P19 Set the output data to be driven on the I/O line 19. 19 1 P20 Set the output data to be driven on the I/O line 20. 20 1 P21 Set the output data to be driven on the I/O line 21. 21 1 P22 Set the output data to be driven on the I/O line 22. 22 1 P23 Set the output data to be driven on the I/O line 23. 23 1 P24 Set the output data to be driven on the I/O line 24. 24 1 P25 Set the output data to be driven on the I/O line 25. 25 1 P26 Set the output data to be driven on the I/O line 26. 26 1 P27 Set the output data to be driven on the I/O line 27. 27 1 P28 Set the output data to be driven on the I/O line 28. 28 1 P29 Set the output data to be driven on the I/O line 29. 29 1 P30 Set the output data to be driven on the I/O line 30. 30 1 P31 Set the output data to be driven on the I/O line 31. 31 1 PIO_SODR3 PIO Set Output Data Register 0x0D0 P0 Set the output data to be driven on the I/O line 0. 0 1 P1 Set the output data to be driven on the I/O line 1. 1 1 P2 Set the output data to be driven on the I/O line 2. 2 1 P3 Set the output data to be driven on the I/O line 3. 3 1 P4 Set the output data to be driven on the I/O line 4. 4 1 P5 Set the output data to be driven on the I/O line 5. 5 1 P6 Set the output data to be driven on the I/O line 6. 6 1 P7 Set the output data to be driven on the I/O line 7. 7 1 P8 Set the output data to be driven on the I/O line 8. 8 1 P9 Set the output data to be driven on the I/O line 9. 9 1 P10 Set the output data to be driven on the I/O line 10. 10 1 P11 Set the output data to be driven on the I/O line 11. 11 1 P12 Set the output data to be driven on the I/O line 12. 12 1 P13 Set the output data to be driven on the I/O line 13. 13 1 P14 Set the output data to be driven on the I/O line 14. 14 1 P15 Set the output data to be driven on the I/O line 15. 15 1 P16 Set the output data to be driven on the I/O line 16. 16 1 P17 Set the output data to be driven on the I/O line 17. 17 1 P18 Set the output data to be driven on the I/O line 18. 18 1 P19 Set the output data to be driven on the I/O line 19. 19 1 P20 Set the output data to be driven on the I/O line 20. 20 1 P21 Set the output data to be driven on the I/O line 21. 21 1 P22 Set the output data to be driven on the I/O line 22. 22 1 P23 Set the output data to be driven on the I/O line 23. 23 1 P24 Set the output data to be driven on the I/O line 24. 24 1 P25 Set the output data to be driven on the I/O line 25. 25 1 P26 Set the output data to be driven on the I/O line 26. 26 1 P27 Set the output data to be driven on the I/O line 27. 27 1 P28 Set the output data to be driven on the I/O line 28. 28 1 P29 Set the output data to be driven on the I/O line 29. 29 1 P30 Set the output data to be driven on the I/O line 30. 30 1 P31 Set the output data to be driven on the I/O line 31. 31 1 PIO_CODR0 PIO Clear Output Data Register. 0x014 P0 Clear the output data to be driven on the I/O line 0. 0 1 P1 Clear the output data to be driven on the I/O line 1. 1 1 P2 Clear the output data to be driven on the I/O line 2. 2 1 P3 Clear the output data to be driven on the I/O line 3. 3 1 P4 Clear the output data to be driven on the I/O line 4. 4 1 P5 Clear the output data to be driven on the I/O line 5. 5 1 P6 Clear the output data to be driven on the I/O line 6. 6 1 P7 Clear the output data to be driven on the I/O line 7. 7 1 P8 Clear the output data to be driven on the I/O line 8. 8 1 P9 Clear the output data to be driven on the I/O line 9. 9 1 P10 Clear the output data to be driven on the I/O line 10. 10 1 P11 Clear the output data to be driven on the I/O line 11. 11 1 P12 Clear the output data to be driven on the I/O line 12. 12 1 P13 Clear the output data to be driven on the I/O line 13. 13 1 P14 Clear the output data to be driven on the I/O line 14. 14 1 P15 Clear the output data to be driven on the I/O line 15. 15 1 P16 Clear the output data to be driven on the I/O line 16. 16 1 P17 Clear the output data to be driven on the I/O line 17. 17 1 P18 Clear the output data to be driven on the I/O line 18. 18 1 P19 Clear the output data to be driven on the I/O line 19. 19 1 P20 Clear the output data to be driven on the I/O line 20. 20 1 P21 Clear the output data to be driven on the I/O line 21. 21 1 P22 Clear the output data to be driven on the I/O line 22. 22 1 P23 Clear the output data to be driven on the I/O line 23. 23 1 P24 Clear the output data to be driven on the I/O line 24. 24 1 P25 Clear the output data to be driven on the I/O line 25. 25 1 P26 Clear the output data to be driven on the I/O line 26. 26 1 P27 Clear the output data to be driven on the I/O line 27. 27 1 P28 Clear the output data to be driven on the I/O line 28. 28 1 P29 Clear the output data to be driven on the I/O line 29. 29 1 P30 Clear the output data to be driven on the I/O line 30. 30 1 P31 Clear the output data to be driven on the I/O line 31. 31 1 PIO_CODR1 PIO Clear Output Data Register. 0x054 P0 Clear the output data to be driven on the I/O line 0. 0 1 P1 Clear the output data to be driven on the I/O line 1. 1 1 P2 Clear the output data to be driven on the I/O line 2. 2 1 P3 Clear the output data to be driven on the I/O line 3. 3 1 P4 Clear the output data to be driven on the I/O line 4. 4 1 P5 Clear the output data to be driven on the I/O line 5. 5 1 P6 Clear the output data to be driven on the I/O line 6. 6 1 P7 Clear the output data to be driven on the I/O line 7. 7 1 P8 Clear the output data to be driven on the I/O line 8. 8 1 P9 Clear the output data to be driven on the I/O line 9. 9 1 P10 Clear the output data to be driven on the I/O line 10. 10 1 P11 Clear the output data to be driven on the I/O line 11. 11 1 P12 Clear the output data to be driven on the I/O line 12. 12 1 P13 Clear the output data to be driven on the I/O line 13. 13 1 P14 Clear the output data to be driven on the I/O line 14. 14 1 P15 Clear the output data to be driven on the I/O line 15. 15 1 P16 Clear the output data to be driven on the I/O line 16. 16 1 P17 Clear the output data to be driven on the I/O line 17. 17 1 P18 Clear the output data to be driven on the I/O line 18. 18 1 P19 Clear the output data to be driven on the I/O line 19. 19 1 P20 Clear the output data to be driven on the I/O line 20. 20 1 P21 Clear the output data to be driven on the I/O line 21. 21 1 P22 Clear the output data to be driven on the I/O line 22. 22 1 P23 Clear the output data to be driven on the I/O line 23. 23 1 P24 Clear the output data to be driven on the I/O line 24. 24 1 P25 Clear the output data to be driven on the I/O line 25. 25 1 P26 Clear the output data to be driven on the I/O line 26. 26 1 P27 Clear the output data to be driven on the I/O line 27. 27 1 P28 Clear the output data to be driven on the I/O line 28. 28 1 P29 Clear the output data to be driven on the I/O line 29. 29 1 P30 Clear the output data to be driven on the I/O line 30. 30 1 P31 Clear the output data to be driven on the I/O line 31. 31 1 PIO_CODR2 PIO Clear Output Data Register. 0x094 P0 Clear the output data to be driven on the I/O line 0. 0 1 P1 Clear the output data to be driven on the I/O line 1. 1 1 P2 Clear the output data to be driven on the I/O line 2. 2 1 P3 Clear the output data to be driven on the I/O line 3. 3 1 P4 Clear the output data to be driven on the I/O line 4. 4 1 P5 Clear the output data to be driven on the I/O line 5. 5 1 P6 Clear the output data to be driven on the I/O line 6. 6 1 P7 Clear the output data to be driven on the I/O line 7. 7 1 P8 Clear the output data to be driven on the I/O line 8. 8 1 P9 Clear the output data to be driven on the I/O line 9. 9 1 P10 Clear the output data to be driven on the I/O line 10. 10 1 P11 Clear the output data to be driven on the I/O line 11. 11 1 P12 Clear the output data to be driven on the I/O line 12. 12 1 P13 Clear the output data to be driven on the I/O line 13. 13 1 P14 Clear the output data to be driven on the I/O line 14. 14 1 P15 Clear the output data to be driven on the I/O line 15. 15 1 P16 Clear the output data to be driven on the I/O line 16. 16 1 P17 Clear the output data to be driven on the I/O line 17. 17 1 P18 Clear the output data to be driven on the I/O line 18. 18 1 P19 Clear the output data to be driven on the I/O line 19. 19 1 P20 Clear the output data to be driven on the I/O line 20. 20 1 P21 Clear the output data to be driven on the I/O line 21. 21 1 P22 Clear the output data to be driven on the I/O line 22. 22 1 P23 Clear the output data to be driven on the I/O line 23. 23 1 P24 Clear the output data to be driven on the I/O line 24. 24 1 P25 Clear the output data to be driven on the I/O line 25. 25 1 P26 Clear the output data to be driven on the I/O line 26. 26 1 P27 Clear the output data to be driven on the I/O line 27. 27 1 P28 Clear the output data to be driven on the I/O line 28. 28 1 P29 Clear the output data to be driven on the I/O line 29. 29 1 P30 Clear the output data to be driven on the I/O line 30. 30 1 P31 Clear the output data to be driven on the I/O line 31. 31 1 PIO_CODR3 PIO Clear Output Data Register. 0x0D4 P0 Clear the output data to be driven on the I/O line 0. 0 1 P1 Clear the output data to be driven on the I/O line 1. 1 1 P2 Clear the output data to be driven on the I/O line 2. 2 1 P3 Clear the output data to be driven on the I/O line 3. 3 1 P4 Clear the output data to be driven on the I/O line 4. 4 1 P5 Clear the output data to be driven on the I/O line 5. 5 1 P6 Clear the output data to be driven on the I/O line 6. 6 1 P7 Clear the output data to be driven on the I/O line 7. 7 1 P8 Clear the output data to be driven on the I/O line 8. 8 1 P9 Clear the output data to be driven on the I/O line 9. 9 1 P10 Clear the output data to be driven on the I/O line 10. 10 1 P11 Clear the output data to be driven on the I/O line 11. 11 1 P12 Clear the output data to be driven on the I/O line 12. 12 1 P13 Clear the output data to be driven on the I/O line 13. 13 1 P14 Clear the output data to be driven on the I/O line 14. 14 1 P15 Clear the output data to be driven on the I/O line 15. 15 1 P16 Clear the output data to be driven on the I/O line 16. 16 1 P17 Clear the output data to be driven on the I/O line 17. 17 1 P18 Clear the output data to be driven on the I/O line 18. 18 1 P19 Clear the output data to be driven on the I/O line 19. 19 1 P20 Clear the output data to be driven on the I/O line 20. 20 1 P21 Clear the output data to be driven on the I/O line 21. 21 1 P22 Clear the output data to be driven on the I/O line 22. 22 1 P23 Clear the output data to be driven on the I/O line 23. 23 1 P24 Clear the output data to be driven on the I/O line 24. 24 1 P25 Clear the output data to be driven on the I/O line 25. 25 1 P26 Clear the output data to be driven on the I/O line 26. 26 1 P27 Clear the output data to be driven on the I/O line 27. 27 1 P28 Clear the output data to be driven on the I/O line 28. 28 1 P29 Clear the output data to be driven on the I/O line 29. 29 1 P30 Clear the output data to be driven on the I/O line 30. 30 1 P31 Clear the output data to be driven on the I/O line 31. 31 1 PIO_ODSR0 PIO Output Data Status Register. 0x018 P0 The output data status to be driven on the I/O line 0. 0 1 P1 The output data status to be driven on the I/O line 1. 1 1 P2 The output data status to be driven on the I/O line 2. 2 1 P3 The output data status to be driven on the I/O line 3. 3 1 P4 The output data status to be driven on the I/O line 4. 4 1 P5 The output data status to be driven on the I/O line 5. 5 1 P6 The output data status to be driven on the I/O line 6. 6 1 P7 The output data status to be driven on the I/O line 7. 7 1 P8 The output data status to be driven on the I/O line 8. 8 1 P9 The output data status to be driven on the I/O line 9. 9 1 P10 The output data status to be driven on the I/O line 10. 10 1 P11 The output data status to be driven on the I/O line 11. 11 1 P12 The output data status to be driven on the I/O line 12. 12 1 P13 The output data status to be driven on the I/O line 13. 13 1 P14 The output data status to be driven on the I/O line 14. 14 1 P15 The output data status to be driven on the I/O line 15. 15 1 P16 The output data status to be driven on the I/O line 16. 16 1 P17 The output data status to be driven on the I/O line 17. 17 1 P18 The output data status to be driven on the I/O line 18. 18 1 P19 The output data status to be driven on the I/O line 19. 19 1 P20 The output data status to be driven on the I/O line 20. 20 1 P21 The output data status to be driven on the I/O line 21. 21 1 P22 The output data status to be driven on the I/O line 22. 22 1 P23 The output data status to be driven on the I/O line 23. 23 1 P24 The output data status to be driven on the I/O line 24. 24 1 P25 The output data status to be driven on the I/O line 25. 25 1 P26 The output data status to be driven on the I/O line 26. 26 1 P27 The output data status to be driven on the I/O line 27. 27 1 P28 The output data status to be driven on the I/O line 28. 28 1 P29 The output data status to be driven on the I/O line 29. 29 1 P30 The output data status to be driven on the I/O line 30. 30 1 P31 The output data status to be driven on the I/O line 31. 31 1 PIO_ODSR1 PIO Output Data Status Register. 0x058 P0 The output data status to be driven on the I/O line 0. 0 1 P1 The output data status to be driven on the I/O line 1. 1 1 P2 The output data status to be driven on the I/O line 2. 2 1 P3 The output data status to be driven on the I/O line 3. 3 1 P4 The output data status to be driven on the I/O line 4. 4 1 P5 The output data status to be driven on the I/O line 5. 5 1 P6 The output data status to be driven on the I/O line 6. 6 1 P7 The output data status to be driven on the I/O line 7. 7 1 P8 The output data status to be driven on the I/O line 8. 8 1 P9 The output data status to be driven on the I/O line 9. 9 1 P10 The output data status to be driven on the I/O line 10. 10 1 P11 The output data status to be driven on the I/O line 11. 11 1 P12 The output data status to be driven on the I/O line 12. 12 1 P13 The output data status to be driven on the I/O line 13. 13 1 P14 The output data status to be driven on the I/O line 14. 14 1 P15 The output data status to be driven on the I/O line 15. 15 1 P16 The output data status to be driven on the I/O line 16. 16 1 P17 The output data status to be driven on the I/O line 17. 17 1 P18 The output data status to be driven on the I/O line 18. 18 1 P19 The output data status to be driven on the I/O line 19. 19 1 P20 The output data status to be driven on the I/O line 20. 20 1 P21 The output data status to be driven on the I/O line 21. 21 1 P22 The output data status to be driven on the I/O line 22. 22 1 P23 The output data status to be driven on the I/O line 23. 23 1 P24 The output data status to be driven on the I/O line 24. 24 1 P25 The output data status to be driven on the I/O line 25. 25 1 P26 The output data status to be driven on the I/O line 26. 26 1 P27 The output data status to be driven on the I/O line 27. 27 1 P28 The output data status to be driven on the I/O line 28. 28 1 P29 The output data status to be driven on the I/O line 29. 29 1 P30 The output data status to be driven on the I/O line 30. 30 1 P31 The output data status to be driven on the I/O line 31. 31 1 PIO_ODSR2 PIO Output Data Status Register. 0x098 P0 The output data status to be driven on the I/O line 0. 0 1 P1 The output data status to be driven on the I/O line 1. 1 1 P2 The output data status to be driven on the I/O line 2. 2 1 P3 The output data status to be driven on the I/O line 3. 3 1 P4 The output data status to be driven on the I/O line 4. 4 1 P5 The output data status to be driven on the I/O line 5. 5 1 P6 The output data status to be driven on the I/O line 6. 6 1 P7 The output data status to be driven on the I/O line 7. 7 1 P8 The output data status to be driven on the I/O line 8. 8 1 P9 The output data status to be driven on the I/O line 9. 9 1 P10 The output data status to be driven on the I/O line 10. 10 1 P11 The output data status to be driven on the I/O line 11. 11 1 P12 The output data status to be driven on the I/O line 12. 12 1 P13 The output data status to be driven on the I/O line 13. 13 1 P14 The output data status to be driven on the I/O line 14. 14 1 P15 The output data status to be driven on the I/O line 15. 15 1 P16 The output data status to be driven on the I/O line 16. 16 1 P17 The output data status to be driven on the I/O line 17. 17 1 P18 The output data status to be driven on the I/O line 18. 18 1 P19 The output data status to be driven on the I/O line 19. 19 1 P20 The output data status to be driven on the I/O line 20. 20 1 P21 The output data status to be driven on the I/O line 21. 21 1 P22 The output data status to be driven on the I/O line 22. 22 1 P23 The output data status to be driven on the I/O line 23. 23 1 P24 The output data status to be driven on the I/O line 24. 24 1 P25 The output data status to be driven on the I/O line 25. 25 1 P26 The output data status to be driven on the I/O line 26. 26 1 P27 The output data status to be driven on the I/O line 27. 27 1 P28 The output data status to be driven on the I/O line 28. 28 1 P29 The output data status to be driven on the I/O line 29. 29 1 P30 The output data status to be driven on the I/O line 30. 30 1 P31 The output data status to be driven on the I/O line 31. 31 1 PIO_ODSR3 PIO Output Data Status Register. 0x0D8 P0 The output data status to be driven on the I/O line 0. 0 1 P1 The output data status to be driven on the I/O line 1. 1 1 P2 The output data status to be driven on the I/O line 2. 2 1 P3 The output data status to be driven on the I/O line 3. 3 1 P4 The output data status to be driven on the I/O line 4. 4 1 P5 The output data status to be driven on the I/O line 5. 5 1 P6 The output data status to be driven on the I/O line 6. 6 1 P7 The output data status to be driven on the I/O line 7. 7 1 P8 The output data status to be driven on the I/O line 8. 8 1 P9 The output data status to be driven on the I/O line 9. 9 1 P10 The output data status to be driven on the I/O line 10. 10 1 P11 The output data status to be driven on the I/O line 11. 11 1 P12 The output data status to be driven on the I/O line 12. 12 1 P13 The output data status to be driven on the I/O line 13. 13 1 P14 The output data status to be driven on the I/O line 14. 14 1 P15 The output data status to be driven on the I/O line 15. 15 1 P16 The output data status to be driven on the I/O line 16. 16 1 P17 The output data status to be driven on the I/O line 17. 17 1 P18 The output data status to be driven on the I/O line 18. 18 1 P19 The output data status to be driven on the I/O line 19. 19 1 P20 The output data status to be driven on the I/O line 20. 20 1 P21 The output data status to be driven on the I/O line 21. 21 1 P22 The output data status to be driven on the I/O line 22. 22 1 P23 The output data status to be driven on the I/O line 23. 23 1 P24 The output data status to be driven on the I/O line 24. 24 1 P25 The output data status to be driven on the I/O line 25. 25 1 P26 The output data status to be driven on the I/O line 26. 26 1 P27 The output data status to be driven on the I/O line 27. 27 1 P28 The output data status to be driven on the I/O line 28. 28 1 P29 The output data status to be driven on the I/O line 29. 29 1 P30 The output data status to be driven on the I/O line 30. 30 1 P31 The output data status to be driven on the I/O line 31. 31 1 PIO_IER0 PIO Interrupt Enable Register. 0x020 write-only P0 Enables the Input Change interrupt on the I/O line 0. 0 1 P1 Enables the Input Change interrupt on the I/O line 1. 1 1 P2 Enables the Input Change interrupt on the I/O line 2. 2 1 P3 Enables the Input Change interrupt on the I/O line 3. 3 1 P4 Enables the Input Change interrupt on the I/O line 4. 4 1 P5 Enables the Input Change interrupt on the I/O line 5. 5 1 P6 Enables the Input Change interrupt on the I/O line 6. 6 1 P7 Enables the Input Change interrupt on the I/O line 7. 7 1 P8 Enables the Input Change interrupt on the I/O line 8. 8 1 P9 Enables the Input Change interrupt on the I/O line 9. 9 1 P10 Enables the Input Change interrupt on the I/O line 10. 10 1 P11 Enables the Input Change interrupt on the I/O line 11. 11 1 P12 Enables the Input Change interrupt on the I/O line 12. 12 1 P13 Enables the Input Change interrupt on the I/O line 13. 13 1 P14 Enables the Input Change interrupt on the I/O line 14. 14 1 P15 Enables the Input Change interrupt on the I/O line 15. 15 1 P16 Enables the Input Change interrupt on the I/O line 16. 16 1 P17 Enables the Input Change interrupt on the I/O line 17. 17 1 P18 Enables the Input Change interrupt on the I/O line 18. 18 1 P19 Enables the Input Change interrupt on the I/O line 19. 19 1 P20 Enables the Input Change interrupt on the I/O line 20. 20 1 P21 Enables the Input Change interrupt on the I/O line 21. 21 1 P22 Enables the Input Change interrupt on the I/O line 22. 22 1 P23 Enables the Input Change interrupt on the I/O line 23. 23 1 P24 Enables the Input Change interrupt on the I/O line 24. 24 1 P25 Enables the Input Change interrupt on the I/O line 25. 25 1 P26 Enables the Input Change interrupt on the I/O line 26. 26 1 P27 Enables the Input Change interrupt on the I/O line 27. 27 1 P28 Enables the Input Change interrupt on the I/O line 28. 28 1 P29 Enables the Input Change interrupt on the I/O line 29. 29 1 P30 Enables the Input Change interrupt on the I/O line 30. 30 1 P31 Enables the Input Change interrupt on the I/O line 31. 31 1 PIO_IER1 PIO Interrupt Enable Register. 0x060 write-only P0 Enables the Input Change interrupt on the I/O line 0. 0 1 P1 Enables the Input Change interrupt on the I/O line 1. 1 1 P2 Enables the Input Change interrupt on the I/O line 2. 2 1 P3 Enables the Input Change interrupt on the I/O line 3. 3 1 P4 Enables the Input Change interrupt on the I/O line 4. 4 1 P5 Enables the Input Change interrupt on the I/O line 5. 5 1 P6 Enables the Input Change interrupt on the I/O line 6. 6 1 P7 Enables the Input Change interrupt on the I/O line 7. 7 1 P8 Enables the Input Change interrupt on the I/O line 8. 8 1 P9 Enables the Input Change interrupt on the I/O line 9. 9 1 P10 Enables the Input Change interrupt on the I/O line 10. 10 1 P11 Enables the Input Change interrupt on the I/O line 11. 11 1 P12 Enables the Input Change interrupt on the I/O line 12. 12 1 P13 Enables the Input Change interrupt on the I/O line 13. 13 1 P14 Enables the Input Change interrupt on the I/O line 14. 14 1 P15 Enables the Input Change interrupt on the I/O line 15. 15 1 P16 Enables the Input Change interrupt on the I/O line 16. 16 1 P17 Enables the Input Change interrupt on the I/O line 17. 17 1 P18 Enables the Input Change interrupt on the I/O line 18. 18 1 P19 Enables the Input Change interrupt on the I/O line 19. 19 1 P20 Enables the Input Change interrupt on the I/O line 20. 20 1 P21 Enables the Input Change interrupt on the I/O line 21. 21 1 P22 Enables the Input Change interrupt on the I/O line 22. 22 1 P23 Enables the Input Change interrupt on the I/O line 23. 23 1 P24 Enables the Input Change interrupt on the I/O line 24. 24 1 P25 Enables the Input Change interrupt on the I/O line 25. 25 1 P26 Enables the Input Change interrupt on the I/O line 26. 26 1 P27 Enables the Input Change interrupt on the I/O line 27. 27 1 P28 Enables the Input Change interrupt on the I/O line 28. 28 1 P29 Enables the Input Change interrupt on the I/O line 29. 29 1 P30 Enables the Input Change interrupt on the I/O line 30. 30 1 P31 Enables the Input Change interrupt on the I/O line 31. 31 1 PIO_IER2 PIO Interrupt Enable Register. 0x0A0 write-only P0 Enables the Input Change interrupt on the I/O line 0. 0 1 P1 Enables the Input Change interrupt on the I/O line 1. 1 1 P2 Enables the Input Change interrupt on the I/O line 2. 2 1 P3 Enables the Input Change interrupt on the I/O line 3. 3 1 P4 Enables the Input Change interrupt on the I/O line 4. 4 1 P5 Enables the Input Change interrupt on the I/O line 5. 5 1 P6 Enables the Input Change interrupt on the I/O line 6. 6 1 P7 Enables the Input Change interrupt on the I/O line 7. 7 1 P8 Enables the Input Change interrupt on the I/O line 8. 8 1 P9 Enables the Input Change interrupt on the I/O line 9. 9 1 P10 Enables the Input Change interrupt on the I/O line 10. 10 1 P11 Enables the Input Change interrupt on the I/O line 11. 11 1 P12 Enables the Input Change interrupt on the I/O line 12. 12 1 P13 Enables the Input Change interrupt on the I/O line 13. 13 1 P14 Enables the Input Change interrupt on the I/O line 14. 14 1 P15 Enables the Input Change interrupt on the I/O line 15. 15 1 P16 Enables the Input Change interrupt on the I/O line 16. 16 1 P17 Enables the Input Change interrupt on the I/O line 17. 17 1 P18 Enables the Input Change interrupt on the I/O line 18. 18 1 P19 Enables the Input Change interrupt on the I/O line 19. 19 1 P20 Enables the Input Change interrupt on the I/O line 20. 20 1 P21 Enables the Input Change interrupt on the I/O line 21. 21 1 P22 Enables the Input Change interrupt on the I/O line 22. 22 1 P23 Enables the Input Change interrupt on the I/O line 23. 23 1 P24 Enables the Input Change interrupt on the I/O line 24. 24 1 P25 Enables the Input Change interrupt on the I/O line 25. 25 1 P26 Enables the Input Change interrupt on the I/O line 26. 26 1 P27 Enables the Input Change interrupt on the I/O line 27. 27 1 P28 Enables the Input Change interrupt on the I/O line 28. 28 1 P29 Enables the Input Change interrupt on the I/O line 29. 29 1 P30 Enables the Input Change interrupt on the I/O line 30. 30 1 P31 Enables the Input Change interrupt on the I/O line 31. 31 1 PIO_IER3 PIO Interrupt Enable Register. 0x0E0 write-only P0 Enables the Input Change interrupt on the I/O line 0. 0 1 P1 Enables the Input Change interrupt on the I/O line 1. 1 1 P2 Enables the Input Change interrupt on the I/O line 2. 2 1 P3 Enables the Input Change interrupt on the I/O line 3. 3 1 P4 Enables the Input Change interrupt on the I/O line 4. 4 1 P5 Enables the Input Change interrupt on the I/O line 5. 5 1 P6 Enables the Input Change interrupt on the I/O line 6. 6 1 P7 Enables the Input Change interrupt on the I/O line 7. 7 1 P8 Enables the Input Change interrupt on the I/O line 8. 8 1 P9 Enables the Input Change interrupt on the I/O line 9. 9 1 P10 Enables the Input Change interrupt on the I/O line 10. 10 1 P11 Enables the Input Change interrupt on the I/O line 11. 11 1 P12 Enables the Input Change interrupt on the I/O line 12. 12 1 P13 Enables the Input Change interrupt on the I/O line 13. 13 1 P14 Enables the Input Change interrupt on the I/O line 14. 14 1 P15 Enables the Input Change interrupt on the I/O line 15. 15 1 P16 Enables the Input Change interrupt on the I/O line 16. 16 1 P17 Enables the Input Change interrupt on the I/O line 17. 17 1 P18 Enables the Input Change interrupt on the I/O line 18. 18 1 P19 Enables the Input Change interrupt on the I/O line 19. 19 1 P20 Enables the Input Change interrupt on the I/O line 20. 20 1 P21 Enables the Input Change interrupt on the I/O line 21. 21 1 P22 Enables the Input Change interrupt on the I/O line 22. 22 1 P23 Enables the Input Change interrupt on the I/O line 23. 23 1 P24 Enables the Input Change interrupt on the I/O line 24. 24 1 P25 Enables the Input Change interrupt on the I/O line 25. 25 1 P26 Enables the Input Change interrupt on the I/O line 26. 26 1 P27 Enables the Input Change interrupt on the I/O line 27. 27 1 P28 Enables the Input Change interrupt on the I/O line 28. 28 1 P29 Enables the Input Change interrupt on the I/O line 29. 29 1 P30 Enables the Input Change interrupt on the I/O line 30. 30 1 P31 Enables the Input Change interrupt on the I/O line 31. 31 1 PIO_IDR0 PIO Interrupt Disable Register. 0x024 write-only P0 Disables the Input Change interrupt on the I/O line 0. 0 1 P1 Disables the Input Change interrupt on the I/O line 1. 1 1 P2 Disables the Input Change interrupt on the I/O line 2. 2 1 P3 Disables the Input Change interrupt on the I/O line 3. 3 1 P4 Disables the Input Change interrupt on the I/O line 4. 4 1 P5 Disables the Input Change interrupt on the I/O line 5. 5 1 P6 Disables the Input Change interrupt on the I/O line 6. 6 1 P7 Disables the Input Change interrupt on the I/O line 7. 7 1 P8 Disables the Input Change interrupt on the I/O line 8. 8 1 P9 Disables the Input Change interrupt on the I/O line 9. 9 1 P10 Disables the Input Change interrupt on the I/O line 10. 10 1 P11 Disables the Input Change interrupt on the I/O line 11. 11 1 P12 Disables the Input Change interrupt on the I/O line 12. 12 1 P13 Disables the Input Change interrupt on the I/O line 13. 13 1 P14 Disables the Input Change interrupt on the I/O line 14. 14 1 P15 Disables the Input Change interrupt on the I/O line 15. 15 1 P16 Disables the Input Change interrupt on the I/O line 16. 16 1 P17 Disables the Input Change interrupt on the I/O line 17. 17 1 P18 Disables the Input Change interrupt on the I/O line 18. 18 1 P19 Disables the Input Change interrupt on the I/O line 19. 19 1 P20 Disables the Input Change interrupt on the I/O line 20. 20 1 P21 Disables the Input Change interrupt on the I/O line 21. 21 1 P22 Disables the Input Change interrupt on the I/O line 22. 22 1 P23 Disables the Input Change interrupt on the I/O line 23. 23 1 P24 Disables the Input Change interrupt on the I/O line 24. 24 1 P25 Disables the Input Change interrupt on the I/O line 25. 25 1 P26 Disables the Input Change interrupt on the I/O line 26. 26 1 P27 Disables the Input Change interrupt on the I/O line 27. 27 1 P28 Disables the Input Change interrupt on the I/O line 28. 28 1 P29 Disables the Input Change interrupt on the I/O line 29. 29 1 P30 Disables the Input Change interrupt on the I/O line 30. 30 1 P31 Disables the Input Change interrupt on the I/O line 31. 31 1 PIO_IDR1 PIO Interrupt Disable Register. 0x064 write-only P0 Disables the Input Change interrupt on the I/O line 0. 0 1 P1 Disables the Input Change interrupt on the I/O line 1. 1 1 P2 Disables the Input Change interrupt on the I/O line 2. 2 1 P3 Disables the Input Change interrupt on the I/O line 3. 3 1 P4 Disables the Input Change interrupt on the I/O line 4. 4 1 P5 Disables the Input Change interrupt on the I/O line 5. 5 1 P6 Disables the Input Change interrupt on the I/O line 6. 6 1 P7 Disables the Input Change interrupt on the I/O line 7. 7 1 P8 Disables the Input Change interrupt on the I/O line 8. 8 1 P9 Disables the Input Change interrupt on the I/O line 9. 9 1 P10 Disables the Input Change interrupt on the I/O line 10. 10 1 P11 Disables the Input Change interrupt on the I/O line 11. 11 1 P12 Disables the Input Change interrupt on the I/O line 12. 12 1 P13 Disables the Input Change interrupt on the I/O line 13. 13 1 P14 Disables the Input Change interrupt on the I/O line 14. 14 1 P15 Disables the Input Change interrupt on the I/O line 15. 15 1 P16 Disables the Input Change interrupt on the I/O line 16. 16 1 P17 Disables the Input Change interrupt on the I/O line 17. 17 1 P18 Disables the Input Change interrupt on the I/O line 18. 18 1 P19 Disables the Input Change interrupt on the I/O line 19. 19 1 P20 Disables the Input Change interrupt on the I/O line 20. 20 1 P21 Disables the Input Change interrupt on the I/O line 21. 21 1 P22 Disables the Input Change interrupt on the I/O line 22. 22 1 P23 Disables the Input Change interrupt on the I/O line 23. 23 1 P24 Disables the Input Change interrupt on the I/O line 24. 24 1 P25 Disables the Input Change interrupt on the I/O line 25. 25 1 P26 Disables the Input Change interrupt on the I/O line 26. 26 1 P27 Disables the Input Change interrupt on the I/O line 27. 27 1 P28 Disables the Input Change interrupt on the I/O line 28. 28 1 P29 Disables the Input Change interrupt on the I/O line 29. 29 1 P30 Disables the Input Change interrupt on the I/O line 30. 30 1 P31 Disables the Input Change interrupt on the I/O line 31. 31 1 PIO_IDR2 PIO Interrupt Disable Register. 0x0A4 write-only P0 Disables the Input Change interrupt on the I/O line 0. 0 1 P1 Disables the Input Change interrupt on the I/O line 1. 1 1 P2 Disables the Input Change interrupt on the I/O line 2. 2 1 P3 Disables the Input Change interrupt on the I/O line 3. 3 1 P4 Disables the Input Change interrupt on the I/O line 4. 4 1 P5 Disables the Input Change interrupt on the I/O line 5. 5 1 P6 Disables the Input Change interrupt on the I/O line 6. 6 1 P7 Disables the Input Change interrupt on the I/O line 7. 7 1 P8 Disables the Input Change interrupt on the I/O line 8. 8 1 P9 Disables the Input Change interrupt on the I/O line 9. 9 1 P10 Disables the Input Change interrupt on the I/O line 10. 10 1 P11 Disables the Input Change interrupt on the I/O line 11. 11 1 P12 Disables the Input Change interrupt on the I/O line 12. 12 1 P13 Disables the Input Change interrupt on the I/O line 13. 13 1 P14 Disables the Input Change interrupt on the I/O line 14. 14 1 P15 Disables the Input Change interrupt on the I/O line 15. 15 1 P16 Disables the Input Change interrupt on the I/O line 16. 16 1 P17 Disables the Input Change interrupt on the I/O line 17. 17 1 P18 Disables the Input Change interrupt on the I/O line 18. 18 1 P19 Disables the Input Change interrupt on the I/O line 19. 19 1 P20 Disables the Input Change interrupt on the I/O line 20. 20 1 P21 Disables the Input Change interrupt on the I/O line 21. 21 1 P22 Disables the Input Change interrupt on the I/O line 22. 22 1 P23 Disables the Input Change interrupt on the I/O line 23. 23 1 P24 Disables the Input Change interrupt on the I/O line 24. 24 1 P25 Disables the Input Change interrupt on the I/O line 25. 25 1 P26 Disables the Input Change interrupt on the I/O line 26. 26 1 P27 Disables the Input Change interrupt on the I/O line 27. 27 1 P28 Disables the Input Change interrupt on the I/O line 28. 28 1 P29 Disables the Input Change interrupt on the I/O line 29. 29 1 P30 Disables the Input Change interrupt on the I/O line 30. 30 1 P31 Disables the Input Change interrupt on the I/O line 31. 31 1 PIO_IDR3 PIO Interrupt Disable Register. 0x0E4 write-only P0 Disables the Input Change interrupt on the I/O line 0. 0 1 P1 Disables the Input Change interrupt on the I/O line 1. 1 1 P2 Disables the Input Change interrupt on the I/O line 2. 2 1 P3 Disables the Input Change interrupt on the I/O line 3. 3 1 P4 Disables the Input Change interrupt on the I/O line 4. 4 1 P5 Disables the Input Change interrupt on the I/O line 5. 5 1 P6 Disables the Input Change interrupt on the I/O line 6. 6 1 P7 Disables the Input Change interrupt on the I/O line 7. 7 1 P8 Disables the Input Change interrupt on the I/O line 8. 8 1 P9 Disables the Input Change interrupt on the I/O line 9. 9 1 P10 Disables the Input Change interrupt on the I/O line 10. 10 1 P11 Disables the Input Change interrupt on the I/O line 11. 11 1 P12 Disables the Input Change interrupt on the I/O line 12. 12 1 P13 Disables the Input Change interrupt on the I/O line 13. 13 1 P14 Disables the Input Change interrupt on the I/O line 14. 14 1 P15 Disables the Input Change interrupt on the I/O line 15. 15 1 P16 Disables the Input Change interrupt on the I/O line 16. 16 1 P17 Disables the Input Change interrupt on the I/O line 17. 17 1 P18 Disables the Input Change interrupt on the I/O line 18. 18 1 P19 Disables the Input Change interrupt on the I/O line 19. 19 1 P20 Disables the Input Change interrupt on the I/O line 20. 20 1 P21 Disables the Input Change interrupt on the I/O line 21. 21 1 P22 Disables the Input Change interrupt on the I/O line 22. 22 1 P23 Disables the Input Change interrupt on the I/O line 23. 23 1 P24 Disables the Input Change interrupt on the I/O line 24. 24 1 P25 Disables the Input Change interrupt on the I/O line 25. 25 1 P26 Disables the Input Change interrupt on the I/O line 26. 26 1 P27 Disables the Input Change interrupt on the I/O line 27. 27 1 P28 Disables the Input Change interrupt on the I/O line 28. 28 1 P29 Disables the Input Change interrupt on the I/O line 29. 29 1 P30 Disables the Input Change interrupt on the I/O line 30. 30 1 P31 Disables the Input Change interrupt on the I/O line 31. 31 1 PIO_IMR0 PIO Interrupt Mask Register. 0x028 read-only P0 Input Change interrupt mask on the I/O line 0. 0 1 P1 Input Change interrupt mask on the I/O line 1. 1 1 P2 Input Change interrupt mask on the I/O line 2. 2 1 P3 Input Change interrupt mask on the I/O line 3. 3 1 P4 Input Change interrupt mask on the I/O line 4. 4 1 P5 Input Change interrupt mask on the I/O line 5. 5 1 P6 Input Change interrupt mask on the I/O line 6. 6 1 P7 Input Change interrupt mask on the I/O line 7. 7 1 P8 Input Change interrupt mask on the I/O line 8. 8 1 P9 Input Change interrupt mask on the I/O line 9. 9 1 P10 Input Change interrupt mask on the I/O line 10. 10 1 P11 Input Change interrupt mask on the I/O line 11. 11 1 P12 Input Change interrupt mask on the I/O line 12. 12 1 P13 Input Change interrupt mask on the I/O line 13. 13 1 P14 Input Change interrupt mask on the I/O line 14. 14 1 P15 Input Change interrupt mask on the I/O line 15. 15 1 P16 Input Change interrupt mask on the I/O line 16. 16 1 P17 Input Change interrupt mask on the I/O line 17. 17 1 P18 Input Change interrupt mask on the I/O line 18. 18 1 P19 Input Change interrupt mask on the I/O line 19. 19 1 P20 Input Change interrupt mask on the I/O line 20. 20 1 P21 Input Change interrupt mask on the I/O line 21. 21 1 P22 Input Change interrupt mask on the I/O line 22. 22 1 P23 Input Change interrupt mask on the I/O line 23. 23 1 P24 Input Change interrupt mask on the I/O line 24. 24 1 P25 Input Change interrupt mask on the I/O line 25. 25 1 P26 Input Change interrupt mask on the I/O line 26. 26 1 P27 Input Change interrupt mask on the I/O line 27. 27 1 P28 Input Change interrupt mask on the I/O line 28. 28 1 P29 Input Change interrupt mask on the I/O line 29. 29 1 P30 Input Change interrupt mask on the I/O line 30. 30 1 P31 Input Change interrupt mask on the I/O line 31. 31 1 PIO_IMR1 PIO Interrupt Mask Register. 0x068 read-only P0 Input Change interrupt mask on the I/O line 0. 0 1 P1 Input Change interrupt mask on the I/O line 1. 1 1 P2 Input Change interrupt mask on the I/O line 2. 2 1 P3 Input Change interrupt mask on the I/O line 3. 3 1 P4 Input Change interrupt mask on the I/O line 4. 4 1 P5 Input Change interrupt mask on the I/O line 5. 5 1 P6 Input Change interrupt mask on the I/O line 6. 6 1 P7 Input Change interrupt mask on the I/O line 7. 7 1 P8 Input Change interrupt mask on the I/O line 8. 8 1 P9 Input Change interrupt mask on the I/O line 9. 9 1 P10 Input Change interrupt mask on the I/O line 10. 10 1 P11 Input Change interrupt mask on the I/O line 11. 11 1 P12 Input Change interrupt mask on the I/O line 12. 12 1 P13 Input Change interrupt mask on the I/O line 13. 13 1 P14 Input Change interrupt mask on the I/O line 14. 14 1 P15 Input Change interrupt mask on the I/O line 15. 15 1 P16 Input Change interrupt mask on the I/O line 16. 16 1 P17 Input Change interrupt mask on the I/O line 17. 17 1 P18 Input Change interrupt mask on the I/O line 18. 18 1 P19 Input Change interrupt mask on the I/O line 19. 19 1 P20 Input Change interrupt mask on the I/O line 20. 20 1 P21 Input Change interrupt mask on the I/O line 21. 21 1 P22 Input Change interrupt mask on the I/O line 22. 22 1 P23 Input Change interrupt mask on the I/O line 23. 23 1 P24 Input Change interrupt mask on the I/O line 24. 24 1 P25 Input Change interrupt mask on the I/O line 25. 25 1 P26 Input Change interrupt mask on the I/O line 26. 26 1 P27 Input Change interrupt mask on the I/O line 27. 27 1 P28 Input Change interrupt mask on the I/O line 28. 28 1 P29 Input Change interrupt mask on the I/O line 29. 29 1 P30 Input Change interrupt mask on the I/O line 30. 30 1 P31 Input Change interrupt mask on the I/O line 31. 31 1 PIO_IMR2 PIO Interrupt Mask Register. 0x0A8 read-only P0 Input Change interrupt mask on the I/O line 0. 0 1 P1 Input Change interrupt mask on the I/O line 1. 1 1 P2 Input Change interrupt mask on the I/O line 2. 2 1 P3 Input Change interrupt mask on the I/O line 3. 3 1 P4 Input Change interrupt mask on the I/O line 4. 4 1 P5 Input Change interrupt mask on the I/O line 5. 5 1 P6 Input Change interrupt mask on the I/O line 6. 6 1 P7 Input Change interrupt mask on the I/O line 7. 7 1 P8 Input Change interrupt mask on the I/O line 8. 8 1 P9 Input Change interrupt mask on the I/O line 9. 9 1 P10 Input Change interrupt mask on the I/O line 10. 10 1 P11 Input Change interrupt mask on the I/O line 11. 11 1 P12 Input Change interrupt mask on the I/O line 12. 12 1 P13 Input Change interrupt mask on the I/O line 13. 13 1 P14 Input Change interrupt mask on the I/O line 14. 14 1 P15 Input Change interrupt mask on the I/O line 15. 15 1 P16 Input Change interrupt mask on the I/O line 16. 16 1 P17 Input Change interrupt mask on the I/O line 17. 17 1 P18 Input Change interrupt mask on the I/O line 18. 18 1 P19 Input Change interrupt mask on the I/O line 19. 19 1 P20 Input Change interrupt mask on the I/O line 20. 20 1 P21 Input Change interrupt mask on the I/O line 21. 21 1 P22 Input Change interrupt mask on the I/O line 22. 22 1 P23 Input Change interrupt mask on the I/O line 23. 23 1 P24 Input Change interrupt mask on the I/O line 24. 24 1 P25 Input Change interrupt mask on the I/O line 25. 25 1 P26 Input Change interrupt mask on the I/O line 26. 26 1 P27 Input Change interrupt mask on the I/O line 27. 27 1 P28 Input Change interrupt mask on the I/O line 28. 28 1 P29 Input Change interrupt mask on the I/O line 29. 29 1 P30 Input Change interrupt mask on the I/O line 30. 30 1 P31 Input Change interrupt mask on the I/O line 31. 31 1 PIO_IMR3 PIO Interrupt Mask Register. 0x0E8 read-only P0 Input Change interrupt mask on the I/O line 0. 0 1 P1 Input Change interrupt mask on the I/O line 1. 1 1 P2 Input Change interrupt mask on the I/O line 2. 2 1 P3 Input Change interrupt mask on the I/O line 3. 3 1 P4 Input Change interrupt mask on the I/O line 4. 4 1 P5 Input Change interrupt mask on the I/O line 5. 5 1 P6 Input Change interrupt mask on the I/O line 6. 6 1 P7 Input Change interrupt mask on the I/O line 7. 7 1 P8 Input Change interrupt mask on the I/O line 8. 8 1 P9 Input Change interrupt mask on the I/O line 9. 9 1 P10 Input Change interrupt mask on the I/O line 10. 10 1 P11 Input Change interrupt mask on the I/O line 11. 11 1 P12 Input Change interrupt mask on the I/O line 12. 12 1 P13 Input Change interrupt mask on the I/O line 13. 13 1 P14 Input Change interrupt mask on the I/O line 14. 14 1 P15 Input Change interrupt mask on the I/O line 15. 15 1 P16 Input Change interrupt mask on the I/O line 16. 16 1 P17 Input Change interrupt mask on the I/O line 17. 17 1 P18 Input Change interrupt mask on the I/O line 18. 18 1 P19 Input Change interrupt mask on the I/O line 19. 19 1 P20 Input Change interrupt mask on the I/O line 20. 20 1 P21 Input Change interrupt mask on the I/O line 21. 21 1 P22 Input Change interrupt mask on the I/O line 22. 22 1 P23 Input Change interrupt mask on the I/O line 23. 23 1 P24 Input Change interrupt mask on the I/O line 24. 24 1 P25 Input Change interrupt mask on the I/O line 25. 25 1 P26 Input Change interrupt mask on the I/O line 26. 26 1 P27 Input Change interrupt mask on the I/O line 27. 27 1 P28 Input Change interrupt mask on the I/O line 28. 28 1 P29 Input Change interrupt mask on the I/O line 29. 29 1 P30 Input Change interrupt mask on the I/O line 30. 30 1 P31 Input Change interrupt mask on the I/O line 31. 31 1 PIO_ISR0 PIO Interrupt Status Register 0x02C read-only P0 Input Change interrupt status on the I/O line 0. 0 1 P1 Input Change interrupt status on the I/O line 1. 1 1 P2 Input Change interrupt status on the I/O line 2. 2 1 P3 Input Change interrupt status on the I/O line 3. 3 1 P4 Input Change interrupt status on the I/O line 4. 4 1 P5 Input Change interrupt status on the I/O line 5. 5 1 P6 Input Change interrupt status on the I/O line 6. 6 1 P7 Input Change interrupt status on the I/O line 7. 7 1 P8 Input Change interrupt status on the I/O line 8. 8 1 P9 Input Change interrupt status on the I/O line 9. 9 1 P10 Input Change interrupt status on the I/O line 10. 10 1 P11 Input Change interrupt status on the I/O line 11. 11 1 P12 Input Change interrupt status on the I/O line 12. 12 1 P13 Input Change interrupt status on the I/O line 13. 13 1 P14 Input Change interrupt status on the I/O line 14. 14 1 P15 Input Change interrupt status on the I/O line 15. 15 1 P16 Input Change interrupt status on the I/O line 16. 16 1 P17 Input Change interrupt status on the I/O line 17. 17 1 P18 Input Change interrupt status on the I/O line 18. 18 1 P19 Input Change interrupt status on the I/O line 19. 19 1 P20 Input Change interrupt status on the I/O line 20. 20 1 P21 Input Change interrupt status on the I/O line 21. 21 1 P22 Input Change interrupt status on the I/O line 22. 22 1 P23 Input Change interrupt status on the I/O line 23. 23 1 P24 Input Change interrupt status on the I/O line 24. 24 1 P25 Input Change interrupt status on the I/O line 25. 25 1 P26 Input Change interrupt status on the I/O line 26. 26 1 P27 Input Change interrupt status on the I/O line 27. 27 1 P28 Input Change interrupt status on the I/O line 28. 28 1 P29 Input Change interrupt status on the I/O line 29. 29 1 P30 Input Change interrupt status on the I/O line 30. 30 1 P31 Input Change interrupt status on the I/O line 31. 31 1 PIO_ISR1 PIO Interrupt Status Register 0x06C read-only P0 Input Change interrupt status on the I/O line 0. 0 1 P1 Input Change interrupt status on the I/O line 1. 1 1 P2 Input Change interrupt status on the I/O line 2. 2 1 P3 Input Change interrupt status on the I/O line 3. 3 1 P4 Input Change interrupt status on the I/O line 4. 4 1 P5 Input Change interrupt status on the I/O line 5. 5 1 P6 Input Change interrupt status on the I/O line 6. 6 1 P7 Input Change interrupt status on the I/O line 7. 7 1 P8 Input Change interrupt status on the I/O line 8. 8 1 P9 Input Change interrupt status on the I/O line 9. 9 1 P10 Input Change interrupt status on the I/O line 10. 10 1 P11 Input Change interrupt status on the I/O line 11. 11 1 P12 Input Change interrupt status on the I/O line 12. 12 1 P13 Input Change interrupt status on the I/O line 13. 13 1 P14 Input Change interrupt status on the I/O line 14. 14 1 P15 Input Change interrupt status on the I/O line 15. 15 1 P16 Input Change interrupt status on the I/O line 16. 16 1 P17 Input Change interrupt status on the I/O line 17. 17 1 P18 Input Change interrupt status on the I/O line 18. 18 1 P19 Input Change interrupt status on the I/O line 19. 19 1 P20 Input Change interrupt status on the I/O line 20. 20 1 P21 Input Change interrupt status on the I/O line 21. 21 1 P22 Input Change interrupt status on the I/O line 22. 22 1 P23 Input Change interrupt status on the I/O line 23. 23 1 P24 Input Change interrupt status on the I/O line 24. 24 1 P25 Input Change interrupt status on the I/O line 25. 25 1 P26 Input Change interrupt status on the I/O line 26. 26 1 P27 Input Change interrupt status on the I/O line 27. 27 1 P28 Input Change interrupt status on the I/O line 28. 28 1 P29 Input Change interrupt status on the I/O line 29. 29 1 P30 Input Change interrupt status on the I/O line 30. 30 1 P31 Input Change interrupt status on the I/O line 31. 31 1 PIO_ISR2 PIO Interrupt Status Register 0x0AC read-only P0 Input Change interrupt status on the I/O line 0. 0 1 P1 Input Change interrupt status on the I/O line 1. 1 1 P2 Input Change interrupt status on the I/O line 2. 2 1 P3 Input Change interrupt status on the I/O line 3. 3 1 P4 Input Change interrupt status on the I/O line 4. 4 1 P5 Input Change interrupt status on the I/O line 5. 5 1 P6 Input Change interrupt status on the I/O line 6. 6 1 P7 Input Change interrupt status on the I/O line 7. 7 1 P8 Input Change interrupt status on the I/O line 8. 8 1 P9 Input Change interrupt status on the I/O line 9. 9 1 P10 Input Change interrupt status on the I/O line 10. 10 1 P11 Input Change interrupt status on the I/O line 11. 11 1 P12 Input Change interrupt status on the I/O line 12. 12 1 P13 Input Change interrupt status on the I/O line 13. 13 1 P14 Input Change interrupt status on the I/O line 14. 14 1 P15 Input Change interrupt status on the I/O line 15. 15 1 P16 Input Change interrupt status on the I/O line 16. 16 1 P17 Input Change interrupt status on the I/O line 17. 17 1 P18 Input Change interrupt status on the I/O line 18. 18 1 P19 Input Change interrupt status on the I/O line 19. 19 1 P20 Input Change interrupt status on the I/O line 20. 20 1 P21 Input Change interrupt status on the I/O line 21. 21 1 P22 Input Change interrupt status on the I/O line 22. 22 1 P23 Input Change interrupt status on the I/O line 23. 23 1 P24 Input Change interrupt status on the I/O line 24. 24 1 P25 Input Change interrupt status on the I/O line 25. 25 1 P26 Input Change interrupt status on the I/O line 26. 26 1 P27 Input Change interrupt status on the I/O line 27. 27 1 P28 Input Change interrupt status on the I/O line 28. 28 1 P29 Input Change interrupt status on the I/O line 29. 29 1 P30 Input Change interrupt status on the I/O line 30. 30 1 P31 Input Change interrupt status on the I/O line 31. 31 1 PIO_ISR3 PIO Interrupt Status Register 0x0EC read-only P0 Input Change interrupt status on the I/O line 0. 0 1 P1 Input Change interrupt status on the I/O line 1. 1 1 P2 Input Change interrupt status on the I/O line 2. 2 1 P3 Input Change interrupt status on the I/O line 3. 3 1 P4 Input Change interrupt status on the I/O line 4. 4 1 P5 Input Change interrupt status on the I/O line 5. 5 1 P6 Input Change interrupt status on the I/O line 6. 6 1 P7 Input Change interrupt status on the I/O line 7. 7 1 P8 Input Change interrupt status on the I/O line 8. 8 1 P9 Input Change interrupt status on the I/O line 9. 9 1 P10 Input Change interrupt status on the I/O line 10. 10 1 P11 Input Change interrupt status on the I/O line 11. 11 1 P12 Input Change interrupt status on the I/O line 12. 12 1 P13 Input Change interrupt status on the I/O line 13. 13 1 P14 Input Change interrupt status on the I/O line 14. 14 1 P15 Input Change interrupt status on the I/O line 15. 15 1 P16 Input Change interrupt status on the I/O line 16. 16 1 P17 Input Change interrupt status on the I/O line 17. 17 1 P18 Input Change interrupt status on the I/O line 18. 18 1 P19 Input Change interrupt status on the I/O line 19. 19 1 P20 Input Change interrupt status on the I/O line 20. 20 1 P21 Input Change interrupt status on the I/O line 21. 21 1 P22 Input Change interrupt status on the I/O line 22. 22 1 P23 Input Change interrupt status on the I/O line 23. 23 1 P24 Input Change interrupt status on the I/O line 24. 24 1 P25 Input Change interrupt status on the I/O line 25. 25 1 P26 Input Change interrupt status on the I/O line 26. 26 1 P27 Input Change interrupt status on the I/O line 27. 27 1 P28 Input Change interrupt status on the I/O line 28. 28 1 P29 Input Change interrupt status on the I/O line 29. 29 1 P30 Input Change interrupt status on the I/O line 30. 30 1 P31 Input Change interrupt status on the I/O line 31. 31 1 PIO_IOFR0 PIO Freeze Configuration Register. 0x03C write-only FRZKEY Freeze Key. 8 24 FRZKEY read-write PASSWD Freeze key. 0x494F46 FINT Freeze Interrupt Configuration. 1 1 FINT read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): IFEN, IFSCEN and EVTSEL. 1 FPHY Freeze Physical Configuration. 0 1 FPHY read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): FUNC, DIR, PUEN, PDEN, OPD, SCHMITT and DRVSTR. 1 PIO_IOFR1 PIO Freeze Configuration Register. 0x07C write-only FRZKEY Freeze Key. 8 24 FRZKEY read-write PASSWD Freeze key. 0x494F46 FINT Freeze Interrupt Configuration. 1 1 FINT read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): IFEN, IFSCEN and EVTSEL. 1 FPHY Freeze Physical Configuration. 0 1 FPHY read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): FUNC, DIR, PUEN, PDEN, OPD, SCHMITT and DRVSTR. 1 PIO_IOFR2 PIO Freeze Configuration Register. 0x0BC write-only FRZKEY Freeze Key. 8 24 FRZKEY read-write PASSWD Freeze key. 0x494F46 FINT Freeze Interrupt Configuration. 1 1 FINT read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): IFEN, IFSCEN and EVTSEL. 1 FPHY Freeze Physical Configuration. 0 1 FPHY read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): FUNC, DIR, PUEN, PDEN, OPD, SCHMITT and DRVSTR. 1 PIO_IOFR3 PIO Freeze Configuration Register. 0x0FC write-only FRZKEY Freeze Key. 8 24 FRZKEY read-write PASSWD Freeze key. 0x494F46 FINT Freeze Interrupt Configuration. 1 1 FINT read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): IFEN, IFSCEN and EVTSEL. 1 FPHY Freeze Physical Configuration. 0 1 FPHY read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): FUNC, DIR, PUEN, PDEN, OPD, SCHMITT and DRVSTR. 1 PIT Periodic Interval Timer 0xF8048030 0x0 0x10 registers MR Mode Register 0x0 0x20 read-write PIV Periodic Interval Value [19:0] read-write 0 1048575 PITEN Period Interval Timer Enabled [24:24] read-write PITIEN Periodic Interval Timer Interrupt Enable [25:25] read-write PIIR Periodic Interval Image Register 0xC 0x20 read-only CPIV Current Periodic Interval Value [19:0] read-write 0 1048575 PICNT Periodic Interval Counter [31:20] read-write 0 4095 PIVR Periodic Interval Value Register 0x8 0x20 read-only CPIV Current Periodic Interval Value [19:0] read-write 0 1048575 PICNT Periodic Interval Counter [31:20] read-write 0 4095 SR Status Register 0x4 0x20 read-only PITS Periodic Interval Timer Status [0:0] read-write PMC Power Management Controller 0xF0014000 0x0 0xC registers 0x10 0x1C registers 0x30 0x4 registers 0x38 0x4 registers 0x40 0x4 registers 0x60 0x1C registers 0x80 0x4 registers 0xE4 0x8 registers 0x100 0x24 registers 0x134 0x20 registers CKGR_MCFR Main Clock Frequency Register 0x24 0x20 read-write MAINF Main Clock Frequency [15:0] read-write 0 65535 MAINFRDY Main Clock Frequency Measure Ready [16:16] read-write RCMEAS RC Oscillator Frequency Measure (write-only) [20:20] read-write CCSS Counter Clock Source Selection [24:24] read-write CKGR_MOR Main Oscillator Register 0x20 0x20 read-write MOSCXTEN 8 to 24 MHz Crystal Oscillator Enable [0:0] read-write MOSCXTBY 8 to 24 MHz Crystal Oscillator Bypass [1:1] read-write WAITMODE Wait Mode Command (Write-only) [2:2] read-write MOSCRCEN 12 MHz RC Oscillator Enable [3:3] read-write ONE Must Be Set to 1 [5:5] read-write MOSCXTST 8 to 24 MHz Crystal Oscillator Startup Time [15:8] read-write 0 255 KEY Password [23:16] read-write true PASSWD Writing any other value in this field aborts the write operation. 55 MOSCSEL Main Clock Oscillator Selection [24:24] read-write CFDEN Clock Failure Detector Enable [25:25] read-write CKGR_PLLAR PLLA Register 0x28 0x20 read-write DIVA Divider A [0:0] read-write PLLACOUNT PLLA Counter [13:8] read-write 0 63 OUTA PLLA Clock Frequency Range [17:14] read-write 0 15 MULA PLLA Multiplier [24:18] read-write 0 127 ONE Must Be Set to 1 [29:29] read-write CKGR_UCKR UTMI Clock Register 0x1C 0x20 read-write UPLLEN UTMI PLL Enable [16:16] read-write UPLLCOUNT UTMI PLL Startup Time [23:20] read-write 0 15 BIASEN UTMI BIAS Enable [24:24] read-write BIASCOUNT UTMI BIAS Startup Time [31:28] read-write 0 15 PMC_AUDIO_PLL0 Audio PLL Register 0 0x14C 0x20 read-write PLLEN PLL Enable [0:0] read-write PADEN Pad Clock Enable [1:1] read-write PMCEN PMC Clock Enable [2:2] read-write RESETN Audio PLL Reset [3:3] read-write PLLFLT PLL Loop Filter Selection [7:4] read-write 0 15 ND Loop Divider Ratio [14:8] read-write 0 127 QDPMC Output Divider Ratio for PMC Clock [22:16] read-write 0 127 DCO_FILTER Digitally Controlled Oscillator Filter Selection [27:24] read-write 0 15 DCO_GAIN Digitally Controlled Oscillator Gain Selection [29:28] read-write 0 3 PMC_AUDIO_PLL1 Audio PLL Register 1 0x150 0x20 read-write FRACR Fractional Loop Divider Setting [21:0] read-write 0 4194303 DIV Divider Value [25:24] read-write true DIV2 Divide by 2 2 DIV3 Divide by 3 3 QDAUDIO Output Divider Ratio for Pad Clock [30:26] read-write 0 31 PMC_FOCR Fault Output Clear Register 0x78 0x20 write-only FOCLR Fault Output Clear [0:0] read-write PMC_FSMR Fast Startup Mode Register 0x70 0x20 read-write FSTT0 Fast Startup from WKUP Pin Enable [0:0] read-write FSTT1 Fast Startup from Security Module Enable [1:1] read-write FSTT2 Fast Startup from PIOBU0-7 Input Enable [2:2] read-write FSTT3 Fast Startup from PIOBU0-7 Input Enable [3:3] read-write FSTT4 Fast Startup from PIOBU0-7 Input Enable [4:4] read-write FSTT5 Fast Startup from PIOBU0-7 Input Enable [5:5] read-write FSTT6 Fast Startup from PIOBU0-7 Input Enable [6:6] read-write FSTT7 Fast Startup from PIOBU0-7 Input Enable [7:7] read-write FSTT8 Fast Startup from PIOBU0-7 Input Enable [8:8] read-write FSTT9 Fast Startup from PIOBU0-7 Input Enable [9:9] read-write FSTT10 Fast Start-up from GMAC Wake-up On LAN Enable [10:10] read-write RTCAL Fast Startup from RTC Alarm Enable [17:17] read-write USBAL Fast Startup from USB Resume Enable [18:18] read-write SDMMC_CD Fast Startup from SDMMC Card Detect Enable [19:19] read-write LPM Low-power Mode [20:20] read-write RXLP_MCE Fast Startup from Backup UART Receive Match Condition Enable [24:24] read-write ACC_CE Fast Startup from Analog Comparator Controller Comparison Enable [25:25] read-write PMC_FSPR Fast Startup Polarity Register 0x74 0x20 read-write FSTP0 WKUP Pin Polarity for Fast Startup [0:0] read-write FSTP1 Security Module Polarity for Fast Startup [1:1] read-write FSTP2 PIOBU0-7 Pin Polarity for Fast Startup [2:2] read-write FSTP3 PIOBU0-7 Pin Polarity for Fast Startup [3:3] read-write FSTP4 PIOBU0-7 Pin Polarity for Fast Startup [4:4] read-write FSTP5 PIOBU0-7 Pin Polarity for Fast Startup [5:5] read-write FSTP6 PIOBU0-7 Pin Polarity for Fast Startup [6:6] read-write FSTP7 PIOBU0-7 Pin Polarity for Fast Startup [7:7] read-write FSTP8 PIOBU0-7 Pin Polarity for Fast Startup [8:8] read-write FSTP9 PIOBU0-7 Pin Polarity for Fast Startup [9:9] read-write FSTP10 GMAC Wake-up On LAN Polarity for Fast Start-up [10:10] read-write PMC_IDR Interrupt Disable Register 0x64 0x20 write-only MOSCXTS 8 to 24 MHz Crystal Oscillator Status Interrupt Disable [0:0] read-write LOCKA PLLA Lock Interrupt Disable [1:1] read-write MCKRDY Master Clock Ready Interrupt Disable [3:3] read-write LOCKU UTMI PLL Lock Interrupt Enable [6:6] read-write PCKRDY0 Programmable Clock Ready 0 Interrupt Disable [8:8] read-write PCKRDY1 Programmable Clock Ready 1 Interrupt Disable [9:9] read-write PCKRDY2 Programmable Clock Ready 2 Interrupt Disable [10:10] read-write MOSCSELS Main Oscillator Clock Source Selection Status Interrupt Disable [16:16] read-write MOSCRCS 12 MHz RC Oscillator Status Interrupt Disable [17:17] read-write CFDEV Clock Failure Detector Event Interrupt Disable [18:18] read-write PMC_IER Interrupt Enable Register 0x60 0x20 write-only MOSCXTS 8 to 24 MHz Crystal Oscillator Status Interrupt Enable [0:0] read-write LOCKA PLLA Lock Interrupt Enable [1:1] read-write MCKRDY Master Clock Ready Interrupt Enable [3:3] read-write LOCKU UTMI PLL Lock Interrupt Enable [6:6] read-write PCKRDY0 Programmable Clock Ready 0 Interrupt Enable [8:8] read-write PCKRDY1 Programmable Clock Ready 1 Interrupt Enable [9:9] read-write PCKRDY2 Programmable Clock Ready 2 Interrupt Enable [10:10] read-write MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Enable [16:16] read-write MOSCRCS 12 MHz RC Oscillator Status Interrupt Enable [17:17] read-write CFDEV Clock Failure Detector Event Interrupt Enable [18:18] read-write PMC_IMR Interrupt Mask Register 0x6C 0x20 read-only MOSCXTS 8 to 24 MHz Crystal Oscillator Status Interrupt Mask [0:0] read-write LOCKA PLLA Lock Interrupt Mask [1:1] read-write MCKRDY Master Clock Ready Interrupt Mask [3:3] read-write PCKRDY0 Programmable Clock Ready 0 Interrupt Mask [8:8] read-write PCKRDY1 Programmable Clock Ready 1 Interrupt Mask [9:9] read-write PCKRDY2 Programmable Clock Ready 2 Interrupt Mask [10:10] read-write MOSCSELS Main Oscillator Clock Source Selection Status Interrupt Mask [16:16] read-write MOSCRCS 12 MHz RC Oscillator Status Interrupt Mask [17:17] read-write CFDEV Clock Failure Detector Event Interrupt Mask [18:18] read-write PMC_MCKR Master Clock Register 0x30 0x20 read-write CSS Master/Processor Clock Source Selection [1:0] read-write true SLOW_CLK Slow clock is selected 0 MAIN_CLK Main clock is selected 1 PLLA_CLK PLLACK is selected 2 UPLL_CLK UPLL Clock is selected 3 PRES Master/Processor Clock Prescaler [6:4] read-write true CLOCK Selected clock 0 CLOCK_DIV2 Selected clock divided by 2 1 CLOCK_DIV4 Selected clock divided by 4 2 CLOCK_DIV8 Selected clock divided by 8 3 CLOCK_DIV16 Selected clock divided by 16 4 CLOCK_DIV32 Selected clock divided by 32 5 CLOCK_DIV64 Selected clock divided by 64 6 MDIV Master Clock Division [9:8] read-write true EQ_PCK Master Clock is Prescaler Output Clock divided by 1.Warning: DDRCK is not available. 0 PCK_DIV2 Master Clock is Prescaler Output Clock divided by 2. DDRCK is equal to MCK. 1 PCK_DIV4 Master Clock is Prescaler Output Clock divided by 4. DDRCK is equal to MCK. 2 PCK_DIV3 Master Clock is Prescaler Output Clock divided by 3. DDRCK is equal to MCK. 3 PLLADIV2 PLLA Divisor by 2 [12:12] read-write H32MXDIV AHB 32-bit Matrix Divisor [24:24] read-write true H32MXDIV1 The AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix frequency. It is possible only if the AHB 64-bit Matrix frequency does not exceed 83 MHz. 0 H32MXDIV2 The AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix frequency divided by 2. 1 PMC_OCR Oscillator Calibration Register 0x110 0x20 read-write CAL 12 MHz RC Oscillator Calibration Bits [6:0] read-write 0 127 SEL Selection of RC Oscillator Calibration Bits [7:7] read-write PMC_PCDR0 Peripheral Clock Disable Register 0 0x14 0x20 write-only PID2 Peripheral Clock 2 Disable [2:2] read-write PID3 Peripheral Clock 3 Disable [3:3] read-write PID4 Peripheral Clock 4 Disable [4:4] read-write PID5 Peripheral Clock 5 Disable [5:5] read-write PID6 Peripheral Clock 6 Disable [6:6] read-write PID7 Peripheral Clock 7 Disable [7:7] read-write PID8 Peripheral Clock 8 Disable [8:8] read-write PID9 Peripheral Clock 9 Disable [9:9] read-write PID10 Peripheral Clock 10 Disable [10:10] read-write PID11 Peripheral Clock 11 Disable [11:11] read-write PID12 Peripheral Clock 12 Disable [12:12] read-write PID13 Peripheral Clock 13 Disable [13:13] read-write PID14 Peripheral Clock 14 Disable [14:14] read-write PID15 Peripheral Clock 15 Disable [15:15] read-write PID16 Peripheral Clock 16 Disable [16:16] read-write PID17 Peripheral Clock 17 Disable [17:17] read-write PID18 Peripheral Clock 18 Disable [18:18] read-write PID19 Peripheral Clock 19 Disable [19:19] read-write PID20 Peripheral Clock 20 Disable [20:20] read-write PID21 Peripheral Clock 21 Disable [21:21] read-write PID22 Peripheral Clock 22 Disable [22:22] read-write PID23 Peripheral Clock 23 Disable [23:23] read-write PID24 Peripheral Clock 24 Disable [24:24] read-write PID25 Peripheral Clock 25 Disable [25:25] read-write PID26 Peripheral Clock 26 Disable [26:26] read-write PID27 Peripheral Clock 27 Disable [27:27] read-write PID28 Peripheral Clock 28 Disable [28:28] read-write PID29 Peripheral Clock 29 Disable [29:29] read-write PID30 Peripheral Clock 30 Disable [30:30] read-write PID31 Peripheral Clock 31 Disable [31:31] read-write PMC_PCDR1 Peripheral Clock Disable Register 1 0x104 0x20 write-only PID32 Peripheral Clock 32 Disable [0:0] read-write PID33 Peripheral Clock 33 Disable [1:1] read-write PID34 Peripheral Clock 34 Disable [2:2] read-write PID35 Peripheral Clock 35 Disable [3:3] read-write PID36 Peripheral Clock 36 Disable [4:4] read-write PID37 Peripheral Clock 37 Disable [5:5] read-write PID38 Peripheral Clock 38 Disable [6:6] read-write PID39 Peripheral Clock 39 Disable [7:7] read-write PID40 Peripheral Clock 40 Disable [8:8] read-write PID41 Peripheral Clock 41 Disable [9:9] read-write PID42 Peripheral Clock 42 Disable [10:10] read-write PID43 Peripheral Clock 43 Disable [11:11] read-write PID44 Peripheral Clock 44 Disable [12:12] read-write PID45 Peripheral Clock 45 Disable [13:13] read-write PID46 Peripheral Clock 46 Disable [14:14] read-write PID47 Peripheral Clock 47 Disable [15:15] read-write PID48 Peripheral Clock 48 Disable [16:16] read-write PID49 Peripheral Clock 49 Disable [17:17] read-write PID50 Peripheral Clock 50 Disable [18:18] read-write PID51 Peripheral Clock 51 Disable [19:19] read-write PID52 Peripheral Clock 52 Disable [20:20] read-write PID53 Peripheral Clock 53 Disable [21:21] read-write PID54 Peripheral Clock 54 Disable [22:22] read-write PID55 Peripheral Clock 55 Disable [23:23] read-write PID56 Peripheral Clock 56 Disable [24:24] read-write PID57 Peripheral Clock 57 Disable [25:25] read-write PID58 Peripheral Clock 58 Disable [26:26] read-write PID59 Peripheral Clock 59 Disable [27:27] read-write PID60 Peripheral Clock 60 Disable [28:28] read-write PID61 Peripheral Clock 61 Disable [29:29] read-write PID62 Peripheral Clock 62 Disable [30:30] read-write PID63 Peripheral Clock 63 Disable [31:31] read-write PMC_PCER0 Peripheral Clock Enable Register 0 0x10 0x20 write-only PID2 Peripheral Clock 2 Enable [2:2] read-write PID3 Peripheral Clock 3 Enable [3:3] read-write PID4 Peripheral Clock 4 Enable [4:4] read-write PID5 Peripheral Clock 5 Enable [5:5] read-write PID6 Peripheral Clock 6 Enable [6:6] read-write PID7 Peripheral Clock 7 Enable [7:7] read-write PID8 Peripheral Clock 8 Enable [8:8] read-write PID9 Peripheral Clock 9 Enable [9:9] read-write PID10 Peripheral Clock 10 Enable [10:10] read-write PID11 Peripheral Clock 11 Enable [11:11] read-write PID12 Peripheral Clock 12 Enable [12:12] read-write PID13 Peripheral Clock 13 Enable [13:13] read-write PID14 Peripheral Clock 14 Enable [14:14] read-write PID15 Peripheral Clock 15 Enable [15:15] read-write PID16 Peripheral Clock 16 Enable [16:16] read-write PID17 Peripheral Clock 17 Enable [17:17] read-write PID18 Peripheral Clock 18 Enable [18:18] read-write PID19 Peripheral Clock 19 Enable [19:19] read-write PID20 Peripheral Clock 20 Enable [20:20] read-write PID21 Peripheral Clock 21 Enable [21:21] read-write PID22 Peripheral Clock 22 Enable [22:22] read-write PID23 Peripheral Clock 23 Enable [23:23] read-write PID24 Peripheral Clock 24 Enable [24:24] read-write PID25 Peripheral Clock 25 Enable [25:25] read-write PID26 Peripheral Clock 26 Enable [26:26] read-write PID27 Peripheral Clock 27 Enable [27:27] read-write PID28 Peripheral Clock 28 Enable [28:28] read-write PID29 Peripheral Clock 29 Enable [29:29] read-write PID30 Peripheral Clock 30 Enable [30:30] read-write PID31 Peripheral Clock 31 Enable [31:31] read-write PMC_PCER1 Peripheral Clock Enable Register 1 0x100 0x20 write-only PID32 Peripheral Clock 32 Enable [0:0] read-write PID33 Peripheral Clock 33 Enable [1:1] read-write PID34 Peripheral Clock 34 Enable [2:2] read-write PID35 Peripheral Clock 35 Enable [3:3] read-write PID36 Peripheral Clock 36 Enable [4:4] read-write PID37 Peripheral Clock 37 Enable [5:5] read-write PID38 Peripheral Clock 38 Enable [6:6] read-write PID39 Peripheral Clock 39 Enable [7:7] read-write PID40 Peripheral Clock 40 Enable [8:8] read-write PID41 Peripheral Clock 41 Enable [9:9] read-write PID42 Peripheral Clock 42 Enable [10:10] read-write PID43 Peripheral Clock 43 Enable [11:11] read-write PID44 Peripheral Clock 44 Enable [12:12] read-write PID45 Peripheral Clock 45 Enable [13:13] read-write PID46 Peripheral Clock 46 Enable [14:14] read-write PID47 Peripheral Clock 47 Enable [15:15] read-write PID48 Peripheral Clock 48 Enable [16:16] read-write PID49 Peripheral Clock 49 Enable [17:17] read-write PID50 Peripheral Clock 50 Enable [18:18] read-write PID51 Peripheral Clock 51 Enable [19:19] read-write PID52 Peripheral Clock 52 Enable [20:20] read-write PID53 Peripheral Clock 53 Enable [21:21] read-write PID54 Peripheral Clock 54 Enable [22:22] read-write PID55 Peripheral Clock 55 Enable [23:23] read-write PID56 Peripheral Clock 56 Enable [24:24] read-write PID57 Peripheral Clock 57 Enable [25:25] read-write PID58 Peripheral Clock 58 Enable [26:26] read-write PID59 Peripheral Clock 59 Enable [27:27] read-write PID60 Peripheral Clock 60 Enable [28:28] read-write PID61 Peripheral Clock 61 Enable [29:29] read-write PID62 Peripheral Clock 62 Enable [30:30] read-write PID63 Peripheral Clock 63 Enable [31:31] read-write PMC_PCK Programmable Clock 0 Register 0x40 0x20 read-write CSS Master Clock Source Selection [2:0] read-write true SLOW_CLK Slow clock is selected 0 MAIN_CLK Main clock is selected 1 PLLA_CLK PLLACK is selected 2 UPLL_CLK UPLL Clock is selected 3 MCK_CLK Master Clock is selected 4 AUDIO_CLK Audio PLL clock is selected 5 PRES Programmable Clock Prescaler [11:4] read-write 0 255 PMC_PCR Peripheral Control Register 0x10C 0x20 read-write PID Peripheral ID [6:0] read-write 0 127 GCKCSS Generic Clock Source Selection [10:8] read-write true SLOW_CLK Slow clock is selected 0 MAIN_CLK Main clock is selected 1 PLLA_CLK PLLACK is selected 2 UPLL_CLK UPLL Clock is selected 3 MCK_CLK Master Clock is selected 4 AUDIO_CLK Audio PLL clock is selected 5 CMD Command [12:12] read-write GCKDIV Generic Clock Division Ratio [27:20] read-write 0 255 EN Enable [28:28] read-write GCKEN Generic Clock Enable [29:29] read-write PMC_PCSR0 Peripheral Clock Status Register 0 0x18 0x20 read-only PID2 Peripheral Clock 2 Status [2:2] read-write PID3 Peripheral Clock 3 Status [3:3] read-write PID4 Peripheral Clock 4 Status [4:4] read-write PID5 Peripheral Clock 5 Status [5:5] read-write PID6 Peripheral Clock 6 Status [6:6] read-write PID7 Peripheral Clock 7 Status [7:7] read-write PID8 Peripheral Clock 8 Status [8:8] read-write PID9 Peripheral Clock 9 Status [9:9] read-write PID10 Peripheral Clock 10 Status [10:10] read-write PID11 Peripheral Clock 11 Status [11:11] read-write PID12 Peripheral Clock 12 Status [12:12] read-write PID13 Peripheral Clock 13 Status [13:13] read-write PID14 Peripheral Clock 14 Status [14:14] read-write PID15 Peripheral Clock 15 Status [15:15] read-write PID16 Peripheral Clock 16 Status [16:16] read-write PID17 Peripheral Clock 17 Status [17:17] read-write PID18 Peripheral Clock 18 Status [18:18] read-write PID19 Peripheral Clock 19 Status [19:19] read-write PID20 Peripheral Clock 20 Status [20:20] read-write PID21 Peripheral Clock 21 Status [21:21] read-write PID22 Peripheral Clock 22 Status [22:22] read-write PID23 Peripheral Clock 23 Status [23:23] read-write PID24 Peripheral Clock 24 Status [24:24] read-write PID25 Peripheral Clock 25 Status [25:25] read-write PID26 Peripheral Clock 26 Status [26:26] read-write PID27 Peripheral Clock 27 Status [27:27] read-write PID28 Peripheral Clock 28 Status [28:28] read-write PID29 Peripheral Clock 29 Status [29:29] read-write PID30 Peripheral Clock 30 Status [30:30] read-write PID31 Peripheral Clock 31 Status [31:31] read-write PMC_PCSR1 Peripheral Clock Status Register 1 0x108 0x20 read-only PID32 Peripheral Clock 32 Status [0:0] read-write PID33 Peripheral Clock 33 Status [1:1] read-write PID34 Peripheral Clock 34 Status [2:2] read-write PID35 Peripheral Clock 35 Status [3:3] read-write PID36 Peripheral Clock 36 Status [4:4] read-write PID37 Peripheral Clock 37 Status [5:5] read-write PID38 Peripheral Clock 38 Status [6:6] read-write PID39 Peripheral Clock 39 Status [7:7] read-write PID40 Peripheral Clock 40 Status [8:8] read-write PID41 Peripheral Clock 41 Status [9:9] read-write PID42 Peripheral Clock 42 Status [10:10] read-write PID43 Peripheral Clock 43 Status [11:11] read-write PID44 Peripheral Clock 44 Status [12:12] read-write PID45 Peripheral Clock 45 Status [13:13] read-write PID46 Peripheral Clock 46 Status [14:14] read-write PID47 Peripheral Clock 47 Status [15:15] read-write PID48 Peripheral Clock 48 Status [16:16] read-write PID49 Peripheral Clock 49 Status [17:17] read-write PID50 Peripheral Clock 50 Status [18:18] read-write PID51 Peripheral Clock 51 Status [19:19] read-write PID52 Peripheral Clock 52 Status [20:20] read-write PID53 Peripheral Clock 53 Status [21:21] read-write PID54 Peripheral Clock 54 Status [22:22] read-write PID55 Peripheral Clock 55 Status [23:23] read-write PID56 Peripheral Clock 56 Status [24:24] read-write PID57 Peripheral Clock 57 Status [25:25] read-write PID58 Peripheral Clock 58 Status [26:26] read-write PID59 Peripheral Clock 59 Status [27:27] read-write PID60 Peripheral Clock 60 Status [28:28] read-write PID61 Peripheral Clock 61 Status [29:29] read-write PID62 Peripheral Clock 62 Status [30:30] read-write PID63 Peripheral Clock 63 Status [31:31] read-write PMC_PLLICPR PLL Charge Pump Current Register 0x80 0x20 read-write ICP_PLLA Charge Pump Current [1:0] read-write 0 3 ICP_PLLU Charge Pump Current PLL UTMI [17:16] read-write 0 3 IVCO_PLLU Voltage Control Output Current PLL UTMI [25:24] read-write 0 3 PMC_SCDR System Clock Disable Register 0x4 0x20 write-only PCK Processor Clock Disable [0:0] read-write DDRCK DDR Clock Disable [2:2] read-write LCDCK MCK2x Clock Disable [3:3] read-write UHP USB Host OHCI Clock Disable [6:6] read-write UDP USB Device Clock Enable [7:7] read-write PCK0 Programmable Clock 0 Output Disable [8:8] read-write PCK1 Programmable Clock 1 Output Disable [9:9] read-write PCK2 Programmable Clock 2 Output Disable [10:10] read-write ISCCK ISC Clock Disable [18:18] read-write PMC_SCER System Clock Enable Register 0x0 0x20 write-only DDRCK DDR Clock Enable [2:2] read-write LCDCK MCK2x Clock Enable [3:3] read-write UHP USB Host OHCI Clocks Enable [6:6] read-write UDP USB Device Clock Enable [7:7] read-write PCK0 Programmable Clock 0 Output Enable [8:8] read-write PCK1 Programmable Clock 1 Output Enable [9:9] read-write PCK2 Programmable Clock 2 Output Enable [10:10] read-write ISCCK ISC Clock Enable [18:18] read-write PMC_SCSR System Clock Status Register 0x8 0x20 read-only PCK Processor Clock Status [0:0] read-write DDRCK DDR Clock Status [2:2] read-write LCDCK MCK2x Clock Status [3:3] read-write UHP USB Host Port Clock Status [6:6] read-write UDP USB Device Port Clock Status [7:7] read-write PCK0 Programmable Clock 0 Output Status [8:8] read-write PCK1 Programmable Clock 1 Output Status [9:9] read-write PCK2 Programmable Clock 2 Output Status [10:10] read-write ISCCK ISC Clock Status [18:18] read-write PMC_SLPWKCR SleepWalking Control Register 0x148 0x20 read-write PID Peripheral ID [6:0] read-write 0 127 CMD Command [12:12] read-write ASR Activity Status Register [16:16] read-write SLPWKSR SleepWalking Status Register [28:28] read-write PMC_SLPWK_AIPR SleepWalking Activity In Progress Register 0x144 0x20 read-only AIP Activity In Progress [0:0] read-write PMC_SLPWK_ASR0 SleepWalking Activity Status Register 0 0x120 0x20 read-only PID19 Peripheral 19 Activity Status [19:19] read-write PID20 Peripheral 20 Activity Status [20:20] read-write PID21 Peripheral 21 Activity Status [21:21] read-write PID22 Peripheral 22 Activity Status [22:22] read-write PID23 Peripheral 23 Activity Status [23:23] read-write PID24 Peripheral 24 Activity Status [24:24] read-write PID25 Peripheral 25 Activity Status [25:25] read-write PID26 Peripheral 26 Activity Status [26:26] read-write PID27 Peripheral 27 Activity Status [27:27] read-write PID28 Peripheral 28 Activity Status [28:28] read-write PID29 Peripheral 29 Activity Status [29:29] read-write PID30 Peripheral 30 Activity Status [30:30] read-write PMC_SLPWK_ASR1 SleepWalking Activity Status Register 1 0x140 0x20 read-only PID33 Peripheral 33 Activity Status [1:1] read-write PID34 Peripheral 34 Activity Status [2:2] read-write PID40 Peripheral 40 Activity Status [8:8] read-write PMC_SLPWK_DR0 SleepWalking Disable Register 0 0x118 0x20 write-only PID19 Peripheral 19 SleepWalking Disable [19:19] read-write PID20 Peripheral 20 SleepWalking Disable [20:20] read-write PID21 Peripheral 21 SleepWalking Disable [21:21] read-write PID22 Peripheral 22 SleepWalking Disable [22:22] read-write PID23 Peripheral 23 SleepWalking Disable [23:23] read-write PID24 Peripheral 24 SleepWalking Disable [24:24] read-write PID25 Peripheral 25 SleepWalking Disable [25:25] read-write PID26 Peripheral 26 SleepWalking Disable [26:26] read-write PID27 Peripheral 27 SleepWalking Disable [27:27] read-write PID28 Peripheral 28 SleepWalking Disable [28:28] read-write PID29 Peripheral 29 SleepWalking Disable [29:29] read-write PID30 Peripheral 30 SleepWalking Disable [30:30] read-write PMC_SLPWK_DR1 SleepWalking Disable Register 1 0x138 0x20 write-only PID33 Peripheral 33 SleepWalking Disable [1:1] read-write PID34 Peripheral 34 SleepWalking Disable [2:2] read-write PID40 Peripheral 40 SleepWalking Disable [8:8] read-write PMC_SLPWK_ER0 SleepWalking Enable Register 0 0x114 0x20 write-only PID19 Peripheral 19 SleepWalking Enable [19:19] read-write PID20 Peripheral 20 SleepWalking Enable [20:20] read-write PID21 Peripheral 21 SleepWalking Enable [21:21] read-write PID22 Peripheral 22 SleepWalking Enable [22:22] read-write PID23 Peripheral 23 SleepWalking Enable [23:23] read-write PID24 Peripheral 24 SleepWalking Enable [24:24] read-write PID25 Peripheral 25 SleepWalking Enable [25:25] read-write PID26 Peripheral 26 SleepWalking Enable [26:26] read-write PID27 Peripheral 27 SleepWalking Enable [27:27] read-write PID28 Peripheral 28 SleepWalking Enable [28:28] read-write PID29 Peripheral 29 SleepWalking Enable [29:29] read-write PID30 Peripheral 30 SleepWalking Enable [30:30] read-write PMC_SLPWK_ER1 SleepWalking Enable Register 1 0x134 0x20 write-only PID33 Peripheral 33 SleepWalking Enable [1:1] read-write PID34 Peripheral 34 SleepWalking Enable [2:2] read-write PID40 Peripheral 40 SleepWalking Enable [8:8] read-write PMC_SLPWK_SR0 SleepWalking Status Register 0 0x11C 0x20 read-only PID19 Peripheral 19 SleepWalking Status [19:19] read-write PID20 Peripheral 20 SleepWalking Status [20:20] read-write PID21 Peripheral 21 SleepWalking Status [21:21] read-write PID22 Peripheral 22 SleepWalking Status [22:22] read-write PID23 Peripheral 23 SleepWalking Status [23:23] read-write PID24 Peripheral 24 SleepWalking Status [24:24] read-write PID25 Peripheral 25 SleepWalking Status [25:25] read-write PID26 Peripheral 26 SleepWalking Status [26:26] read-write PID27 Peripheral 27 SleepWalking Status [27:27] read-write PID28 Peripheral 28 SleepWalking Status [28:28] read-write PID29 Peripheral 29 SleepWalking Status [29:29] read-write PID30 Peripheral 30 SleepWalking Status [30:30] read-write PMC_SLPWK_SR1 SleepWalking Status Register 1 0x13C 0x20 read-only PID33 Peripheral 33 SleepWalking Status [1:1] read-write PID34 Peripheral 34 SleepWalking Status [2:2] read-write PID40 Peripheral 40 SleepWalking Status [8:8] read-write PMC_SR Status Register 0x68 0x20 read-only MOSCXTS 8 to 24 MHz Crystal Oscillator Status [0:0] read-write LOCKA PLLA Lock Status [1:1] read-write MCKRDY Master Clock Status [3:3] read-write LOCKU UPLL Clock Status [6:6] read-write OSCSELS Slow Clock Oscillator Selection [7:7] read-write PCKRDY0 Programmable Clock Ready Status [8:8] read-write PCKRDY1 Programmable Clock Ready Status [9:9] read-write PCKRDY2 Programmable Clock Ready Status [10:10] read-write MOSCSELS Main Oscillator Selection Status [16:16] read-write MOSCRCS 12 MHz RC Oscillator Status [17:17] read-write CFDEV Clock Failure Detector Event [18:18] read-write CFDS Clock Failure Detector Status [19:19] read-write FOS Clock Failure Detector Fault Output Status [20:20] read-write APLLCKRDY Audio PLL Lock Status [22:22] read-write GCKRDY Generic Clock Status [24:24] read-write PMC_USB USB Clock Register 0x38 0x20 read-write USBS USB OHCI Input Clock Selection [0:0] read-write USBDIV Divider for USB OHCI Clock [11:8] read-write 0 15 PMC_WPMR Write ProtectIon Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5262659 PMC_WPSR Write Protection Status Register 0xE8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [23:8] read-write 0 65535 PTC Peripheral Touch Controller 0xFC060028 0x0 0x1 registers 0x8 0x1 registers 0xD 0x1 registers CMD PTC Command Register 0x0 0x8 write-only CMD Host Command [3:0] read-write true NO_ACTION - 0 STOP Waits for ongoing execution to complete, then stops. 1 REST Stops and resets 2 ABORT Stops without waiting for ongoing execution to complete. 4 RUN Starts execution (from stopped state) 5 IED PTC Enable Register 0xD 0x8 write-only IER0 IER0 [4:4] read-write IER1 IER1 [5:5] read-write IER2 IER2 [6:6] read-write IER3 IER3 [7:7] read-write ISR PTC Interrupt Status Register 0x8 0x8 read-write NOTIFY0 Notification to the Firmware [0:0] read-write IRQ0 IRQ0 [4:4] read-write IRQ1 IRQ1 [5:5] read-write IRQ2 IRQ2 [6:6] read-write IRQ3 IRQ3 [7:7] read-write PWM Pulse Width Modulation Controller 0xF802C000 0x0 0x70 registers 0x7C 0x4 registers 0xA0 0x8 registers 0xB0 0x4 registers 0xC0 0x4 registers 0xE4 0x8 registers 0x400 0x4 registers 0x420 0x4 registers 0x42C 0x10 registers 0x440 0x4 registers 0x460 0x4 registers CLK PWM Clock Register 0x0 0x20 read-write DIVA CLKA Divide Factor [7:0] read-write true CLKA_POFF CLKA clock is turned off 0 PREA CLKA clock is clock selected by PREA 1 PREA CLKA Source Clock Selection [11:8] read-write true CLK Peripheral clock 0 CLK_DIV2 Peripheral clock/2 1 CLK_DIV4 Peripheral clock/4 2 CLK_DIV8 Peripheral clock/8 3 CLK_DIV16 Peripheral clock/16 4 CLK_DIV32 Peripheral clock/32 5 CLK_DIV64 Peripheral clock/64 6 CLK_DIV128 Peripheral clock/128 7 CLK_DIV256 Peripheral clock/256 8 CLK_DIV512 Peripheral clock/512 9 CLK_DIV1024 Peripheral clock/1024 10 DIVB CLKB Divide Factor [23:16] read-write true CLKB_POFF CLKB clock is turned off 0 PREB CLKB clock is clock selected by PREB 1 PREB CLKB Source Clock Selection [27:24] read-write true CLK Peripheral clock 0 CLK_DIV2 Peripheral clock/2 1 CLK_DIV4 Peripheral clock/4 2 CLK_DIV8 Peripheral clock/8 3 CLK_DIV16 Peripheral clock/16 4 CLK_DIV32 Peripheral clock/32 5 CLK_DIV64 Peripheral clock/64 6 CLK_DIV128 Peripheral clock/128 7 CLK_DIV256 Peripheral clock/256 8 CLK_DIV512 Peripheral clock/512 9 CLK_DIV1024 Peripheral clock/1024 10 CMUPD0 PWM Channel Mode Update Register (ch_num = 0) 0x400 0x20 write-only CPOLUP Channel Polarity Update [9:9] read-write CPOLINVUP Channel Polarity Inversion Update [13:13] read-write CMUPD1 PWM Channel Mode Update Register (ch_num = 1) 0x420 0x20 write-only CPOLUP Channel Polarity Update [9:9] read-write CPOLINVUP Channel Polarity Inversion Update [13:13] read-write CMUPD2 PWM Channel Mode Update Register (ch_num = 2) 0x440 0x20 write-only CPOLUP Channel Polarity Update [9:9] read-write CPOLINVUP Channel Polarity Inversion Update [13:13] read-write CMUPD3 PWM Channel Mode Update Register (ch_num = 3) 0x460 0x20 write-only CPOLUP Channel Polarity Update [9:9] read-write CPOLINVUP Channel Polarity Inversion Update [13:13] read-write DIS PWM Disable Register 0x8 0x20 write-only CHID0 Channel ID [0:0] read-write CHID1 Channel ID [1:1] read-write CHID2 Channel ID [2:2] read-write CHID3 Channel ID [3:3] read-write DMAR PWM DMA Register 0x24 0x20 write-only DMADUTY Duty-Cycle Holding Register for DMA Access [23:0] read-write 0 16777215 ELMR PWM Event Line 0 Mode Register 0x7C 0x20 read-write CSEL0 Comparison 0 Selection [0:0] read-write CSEL1 Comparison 1 Selection [1:1] read-write CSEL2 Comparison 2 Selection [2:2] read-write CSEL3 Comparison 3 Selection [3:3] read-write CSEL4 Comparison 4 Selection [4:4] read-write CSEL5 Comparison 5 Selection [5:5] read-write CSEL6 Comparison 6 Selection [6:6] read-write CSEL7 Comparison 7 Selection [7:7] read-write ENA PWM Enable Register 0x4 0x20 write-only CHID0 Channel ID [0:0] read-write CHID1 Channel ID [1:1] read-write CHID2 Channel ID [2:2] read-write CHID3 Channel ID [3:3] read-write ETRG1 PWM External Trigger Register 1 0x42C 0x20 read-write MAXCNT Maximum Counter value [23:0] read-write 0 16777215 TRGMODE External Trigger Mode [25:24] read-write true OFF External trigger is not enabled. 0 MODE1 External PWM Reset Mode 1 MODE2 External PWM Start Mode 2 MODE3 Cycle-by-cycle Duty Mode 3 TRGEDGE Edge Selection [28:28] read-write true FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input [29:29] read-write TRGSRC Trigger Source [30:30] read-write RFEN Recoverable Fault Enable [31:31] read-write ETRG2 PWM External Trigger Register 2 0x434 0x20 read-write MAXCNT Maximum Counter value [23:0] read-write 0 16777215 TRGMODE External Trigger Mode [25:24] read-write true OFF External trigger is not enabled. 0 MODE1 External PWM Reset Mode 1 MODE2 External PWM Start Mode 2 MODE3 Cycle-by-cycle Duty Mode 3 TRGEDGE Edge Selection [28:28] read-write true FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input [29:29] read-write TRGSRC Trigger Source [30:30] read-write RFEN Recoverable Fault Enable [31:31] read-write FCR PWM Fault Clear Register 0x64 0x20 write-only FCLR Fault Clear [7:0] read-write 0 255 FMR PWM Fault Mode Register 0x5C 0x20 read-write FPOL Fault Polarity [7:0] read-write 0 255 FMOD Fault Activation Mode [15:8] read-write 0 255 FFIL Fault Filtering [23:16] read-write 0 255 FPE PWM Fault Protection Enable Register 0x6C 0x20 read-write FPE0 Fault Protection Enable for channel 0 [7:0] read-write 0 255 FPE1 Fault Protection Enable for channel 1 [15:8] read-write 0 255 FPE2 Fault Protection Enable for channel 2 [23:16] read-write 0 255 FPE3 Fault Protection Enable for channel 3 [31:24] read-write 0 255 FPV1 PWM Fault Protection Value Register 1 0x68 0x20 read-write FPVH0 Fault Protection Value for PWMH output on channel 0 [0:0] read-write FPVH1 Fault Protection Value for PWMH output on channel 1 [1:1] read-write FPVH2 Fault Protection Value for PWMH output on channel 2 [2:2] read-write FPVH3 Fault Protection Value for PWMH output on channel 3 [3:3] read-write FPVL0 Fault Protection Value for PWML output on channel 0 [16:16] read-write FPVL1 Fault Protection Value for PWML output on channel 1 [17:17] read-write FPVL2 Fault Protection Value for PWML output on channel 2 [18:18] read-write FPVL3 Fault Protection Value for PWML output on channel 3 [19:19] read-write FPV2 PWM Fault Protection Value 2 Register 0xC0 0x20 read-write FPZH0 Fault Protection to Hi-Z for PWMH output on channel 0 [0:0] read-write FPZH1 Fault Protection to Hi-Z for PWMH output on channel 1 [1:1] read-write FPZH2 Fault Protection to Hi-Z for PWMH output on channel 2 [2:2] read-write FPZH3 Fault Protection to Hi-Z for PWMH output on channel 3 [3:3] read-write FPZL0 Fault Protection to Hi-Z for PWML output on channel 0 [16:16] read-write FPZL1 Fault Protection to Hi-Z for PWML output on channel 1 [17:17] read-write FPZL2 Fault Protection to Hi-Z for PWML output on channel 2 [18:18] read-write FPZL3 Fault Protection to Hi-Z for PWML output on channel 3 [19:19] read-write FSR PWM Fault Status Register 0x60 0x20 read-only FIV Fault Input Value [7:0] read-write 0 255 FS Fault Status [15:8] read-write 0 255 IDR1 PWM Interrupt Disable Register 1 0x14 0x20 write-only CHID0 Counter Event on Channel 0 Interrupt Disable [0:0] read-write CHID1 Counter Event on Channel 1 Interrupt Disable [1:1] read-write CHID2 Counter Event on Channel 2 Interrupt Disable [2:2] read-write CHID3 Counter Event on Channel 3 Interrupt Disable [3:3] read-write FCHID0 Fault Protection Trigger on Channel 0 Interrupt Disable [16:16] read-write FCHID1 Fault Protection Trigger on Channel 1 Interrupt Disable [17:17] read-write FCHID2 Fault Protection Trigger on Channel 2 Interrupt Disable [18:18] read-write FCHID3 Fault Protection Trigger on Channel 3 Interrupt Disable [19:19] read-write IDR2 PWM Interrupt Disable Register 2 0x38 0x20 write-only WRDY Write Ready for Synchronous Channels Update Interrupt Disable [0:0] read-write UNRE Synchronous Channels Update Underrun Error Interrupt Disable [3:3] read-write CMPM0 Comparison 0 Match Interrupt Disable [8:8] read-write CMPM1 Comparison 1 Match Interrupt Disable [9:9] read-write CMPM2 Comparison 2 Match Interrupt Disable [10:10] read-write CMPM3 Comparison 3 Match Interrupt Disable [11:11] read-write CMPM4 Comparison 4 Match Interrupt Disable [12:12] read-write CMPM5 Comparison 5 Match Interrupt Disable [13:13] read-write CMPM6 Comparison 6 Match Interrupt Disable [14:14] read-write CMPM7 Comparison 7 Match Interrupt Disable [15:15] read-write CMPU0 Comparison 0 Update Interrupt Disable [16:16] read-write CMPU1 Comparison 1 Update Interrupt Disable [17:17] read-write CMPU2 Comparison 2 Update Interrupt Disable [18:18] read-write CMPU3 Comparison 3 Update Interrupt Disable [19:19] read-write CMPU4 Comparison 4 Update Interrupt Disable [20:20] read-write CMPU5 Comparison 5 Update Interrupt Disable [21:21] read-write CMPU6 Comparison 6 Update Interrupt Disable [22:22] read-write CMPU7 Comparison 7 Update Interrupt Disable [23:23] read-write IER1 PWM Interrupt Enable Register 1 0x10 0x20 write-only CHID0 Counter Event on Channel 0 Interrupt Enable [0:0] read-write CHID1 Counter Event on Channel 1 Interrupt Enable [1:1] read-write CHID2 Counter Event on Channel 2 Interrupt Enable [2:2] read-write CHID3 Counter Event on Channel 3 Interrupt Enable [3:3] read-write FCHID0 Fault Protection Trigger on Channel 0 Interrupt Enable [16:16] read-write FCHID1 Fault Protection Trigger on Channel 1 Interrupt Enable [17:17] read-write FCHID2 Fault Protection Trigger on Channel 2 Interrupt Enable [18:18] read-write FCHID3 Fault Protection Trigger on Channel 3 Interrupt Enable [19:19] read-write IER2 PWM Interrupt Enable Register 2 0x34 0x20 write-only WRDY Write Ready for Synchronous Channels Update Interrupt Enable [0:0] read-write UNRE Synchronous Channels Update Underrun Error Interrupt Enable [3:3] read-write CMPM0 Comparison 0 Match Interrupt Enable [8:8] read-write CMPM1 Comparison 1 Match Interrupt Enable [9:9] read-write CMPM2 Comparison 2 Match Interrupt Enable [10:10] read-write CMPM3 Comparison 3 Match Interrupt Enable [11:11] read-write CMPM4 Comparison 4 Match Interrupt Enable [12:12] read-write CMPM5 Comparison 5 Match Interrupt Enable [13:13] read-write CMPM6 Comparison 6 Match Interrupt Enable [14:14] read-write CMPM7 Comparison 7 Match Interrupt Enable [15:15] read-write CMPU0 Comparison 0 Update Interrupt Enable [16:16] read-write CMPU1 Comparison 1 Update Interrupt Enable [17:17] read-write CMPU2 Comparison 2 Update Interrupt Enable [18:18] read-write CMPU3 Comparison 3 Update Interrupt Enable [19:19] read-write CMPU4 Comparison 4 Update Interrupt Enable [20:20] read-write CMPU5 Comparison 5 Update Interrupt Enable [21:21] read-write CMPU6 Comparison 6 Update Interrupt Enable [22:22] read-write CMPU7 Comparison 7 Update Interrupt Enable [23:23] read-write IMR1 PWM Interrupt Mask Register 1 0x18 0x20 read-only CHID0 Counter Event on Channel 0 Interrupt Mask [0:0] read-write CHID1 Counter Event on Channel 1 Interrupt Mask [1:1] read-write CHID2 Counter Event on Channel 2 Interrupt Mask [2:2] read-write CHID3 Counter Event on Channel 3 Interrupt Mask [3:3] read-write FCHID0 Fault Protection Trigger on Channel 0 Interrupt Mask [16:16] read-write FCHID1 Fault Protection Trigger on Channel 1 Interrupt Mask [17:17] read-write FCHID2 Fault Protection Trigger on Channel 2 Interrupt Mask [18:18] read-write FCHID3 Fault Protection Trigger on Channel 3 Interrupt Mask [19:19] read-write IMR2 PWM Interrupt Mask Register 2 0x3C 0x20 read-only WRDY Write Ready for Synchronous Channels Update Interrupt Mask [0:0] read-write UNRE Synchronous Channels Update Underrun Error Interrupt Mask [3:3] read-write CMPM0 Comparison 0 Match Interrupt Mask [8:8] read-write CMPM1 Comparison 1 Match Interrupt Mask [9:9] read-write CMPM2 Comparison 2 Match Interrupt Mask [10:10] read-write CMPM3 Comparison 3 Match Interrupt Mask [11:11] read-write CMPM4 Comparison 4 Match Interrupt Mask [12:12] read-write CMPM5 Comparison 5 Match Interrupt Mask [13:13] read-write CMPM6 Comparison 6 Match Interrupt Mask [14:14] read-write CMPM7 Comparison 7 Match Interrupt Mask [15:15] read-write CMPU0 Comparison 0 Update Interrupt Mask [16:16] read-write CMPU1 Comparison 1 Update Interrupt Mask [17:17] read-write CMPU2 Comparison 2 Update Interrupt Mask [18:18] read-write CMPU3 Comparison 3 Update Interrupt Mask [19:19] read-write CMPU4 Comparison 4 Update Interrupt Mask [20:20] read-write CMPU5 Comparison 5 Update Interrupt Mask [21:21] read-write CMPU6 Comparison 6 Update Interrupt Mask [22:22] read-write CMPU7 Comparison 7 Update Interrupt Mask [23:23] read-write ISR1 PWM Interrupt Status Register 1 0x1C 0x20 read-only CHID0 Counter Event on Channel 0 [0:0] read-write CHID1 Counter Event on Channel 1 [1:1] read-write CHID2 Counter Event on Channel 2 [2:2] read-write CHID3 Counter Event on Channel 3 [3:3] read-write FCHID0 Fault Protection Trigger on Channel 0 [16:16] read-write FCHID1 Fault Protection Trigger on Channel 1 [17:17] read-write FCHID2 Fault Protection Trigger on Channel 2 [18:18] read-write FCHID3 Fault Protection Trigger on Channel 3 [19:19] read-write ISR2 PWM Interrupt Status Register 2 0x40 0x20 read-only WRDY Write Ready for Synchronous Channels Update [0:0] read-write UNRE Synchronous Channels Update Underrun Error [3:3] read-write CMPM0 Comparison 0 Match [8:8] read-write CMPM1 Comparison 1 Match [9:9] read-write CMPM2 Comparison 2 Match [10:10] read-write CMPM3 Comparison 3 Match [11:11] read-write CMPM4 Comparison 4 Match [12:12] read-write CMPM5 Comparison 5 Match [13:13] read-write CMPM6 Comparison 6 Match [14:14] read-write CMPM7 Comparison 7 Match [15:15] read-write CMPU0 Comparison 0 Update [16:16] read-write CMPU1 Comparison 1 Update [17:17] read-write CMPU2 Comparison 2 Update [18:18] read-write CMPU3 Comparison 3 Update [19:19] read-write CMPU4 Comparison 4 Update [20:20] read-write CMPU5 Comparison 5 Update [21:21] read-write CMPU6 Comparison 6 Update [22:22] read-write CMPU7 Comparison 7 Update [23:23] read-write LEBR1 PWM Leading-Edge Blanking Register 1 0x430 0x20 read-write LEBDELAY Leading-Edge Blanking Delay for TRGINx [6:0] read-write 0 127 PWMLFEN PWML Falling Edge Enable [16:16] read-write PWMLREN PWML Rising Edge Enable [17:17] read-write PWMHFEN PWMH Falling Edge Enable [18:18] read-write PWMHREN PWMH Rising Edge Enable [19:19] read-write LEBR2 PWM Leading-Edge Blanking Register 2 0x438 0x20 read-write LEBDELAY Leading-Edge Blanking Delay for TRGINx [6:0] read-write 0 127 PWMLFEN PWML Falling Edge Enable [16:16] read-write PWMLREN PWML Rising Edge Enable [17:17] read-write PWMHFEN PWMH Falling Edge Enable [18:18] read-write PWMHREN PWMH Rising Edge Enable [19:19] read-write OOV PWM Output Override Value Register 0x44 0x20 read-write OOVH0 Output Override Value for PWMH output of the channel 0 [0:0] read-write OOVH1 Output Override Value for PWMH output of the channel 1 [1:1] read-write OOVH2 Output Override Value for PWMH output of the channel 2 [2:2] read-write OOVH3 Output Override Value for PWMH output of the channel 3 [3:3] read-write OOVL0 Output Override Value for PWML output of the channel 0 [16:16] read-write OOVL1 Output Override Value for PWML output of the channel 1 [17:17] read-write OOVL2 Output Override Value for PWML output of the channel 2 [18:18] read-write OOVL3 Output Override Value for PWML output of the channel 3 [19:19] read-write OS PWM Output Selection Register 0x48 0x20 read-write OSH0 Output Selection for PWMH output of the channel 0 [0:0] read-write OSH1 Output Selection for PWMH output of the channel 1 [1:1] read-write OSH2 Output Selection for PWMH output of the channel 2 [2:2] read-write OSH3 Output Selection for PWMH output of the channel 3 [3:3] read-write OSL0 Output Selection for PWML output of the channel 0 [16:16] read-write OSL1 Output Selection for PWML output of the channel 1 [17:17] read-write OSL2 Output Selection for PWML output of the channel 2 [18:18] read-write OSL3 Output Selection for PWML output of the channel 3 [19:19] read-write OSC PWM Output Selection Clear Register 0x50 0x20 write-only OSCH0 Output Selection Clear for PWMH output of the channel 0 [0:0] read-write OSCH1 Output Selection Clear for PWMH output of the channel 1 [1:1] read-write OSCH2 Output Selection Clear for PWMH output of the channel 2 [2:2] read-write OSCH3 Output Selection Clear for PWMH output of the channel 3 [3:3] read-write OSCL0 Output Selection Clear for PWML output of the channel 0 [16:16] read-write OSCL1 Output Selection Clear for PWML output of the channel 1 [17:17] read-write OSCL2 Output Selection Clear for PWML output of the channel 2 [18:18] read-write OSCL3 Output Selection Clear for PWML output of the channel 3 [19:19] read-write OSCUPD PWM Output Selection Clear Update Register 0x58 0x20 write-only OSCUPH0 Output Selection Clear for PWMH output of the channel 0 [0:0] read-write OSCUPH1 Output Selection Clear for PWMH output of the channel 1 [1:1] read-write OSCUPH2 Output Selection Clear for PWMH output of the channel 2 [2:2] read-write OSCUPH3 Output Selection Clear for PWMH output of the channel 3 [3:3] read-write OSCUPL0 Output Selection Clear for PWML output of the channel 0 [16:16] read-write OSCUPL1 Output Selection Clear for PWML output of the channel 1 [17:17] read-write OSCUPL2 Output Selection Clear for PWML output of the channel 2 [18:18] read-write OSCUPL3 Output Selection Clear for PWML output of the channel 3 [19:19] read-write OSS PWM Output Selection Set Register 0x4C 0x20 write-only OSSH0 Output Selection Set for PWMH output of the channel 0 [0:0] read-write OSSH1 Output Selection Set for PWMH output of the channel 1 [1:1] read-write OSSH2 Output Selection Set for PWMH output of the channel 2 [2:2] read-write OSSH3 Output Selection Set for PWMH output of the channel 3 [3:3] read-write OSSL0 Output Selection Set for PWML output of the channel 0 [16:16] read-write OSSL1 Output Selection Set for PWML output of the channel 1 [17:17] read-write OSSL2 Output Selection Set for PWML output of the channel 2 [18:18] read-write OSSL3 Output Selection Set for PWML output of the channel 3 [19:19] read-write OSSUPD PWM Output Selection Set Update Register 0x54 0x20 write-only OSSUPH0 Output Selection Set for PWMH output of the channel 0 [0:0] read-write OSSUPH1 Output Selection Set for PWMH output of the channel 1 [1:1] read-write OSSUPH2 Output Selection Set for PWMH output of the channel 2 [2:2] read-write OSSUPH3 Output Selection Set for PWMH output of the channel 3 [3:3] read-write OSSUPL0 Output Selection Set for PWML output of the channel 0 [16:16] read-write OSSUPL1 Output Selection Set for PWML output of the channel 1 [17:17] read-write OSSUPL2 Output Selection Set for PWML output of the channel 2 [18:18] read-write OSSUPL3 Output Selection Set for PWML output of the channel 3 [19:19] read-write SCM PWM Sync Channels Mode Register 0x20 0x20 read-write SYNC0 Synchronous Channel 0 [0:0] read-write SYNC1 Synchronous Channel 1 [1:1] read-write SYNC2 Synchronous Channel 2 [2:2] read-write SYNC3 Synchronous Channel 3 [3:3] read-write UPDM Synchronous Channels Update Mode [17:16] read-write true MODE0 Manual write of double buffer registers and manual update of synchronous channels 0 MODE1 Manual write of double buffer registers and automatic update of synchronous channels 1 MODE2 Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels 2 PTRM DMA Controller Transfer Request Mode [20:20] read-write PTRCS DMA Controller Transfer Request Comparison Selection [23:21] read-write 0 7 SCUC PWM Sync Channels Update Control Register 0x28 0x20 read-write UPDULOCK Synchronous Channels Update Unlock [0:0] read-write SCUP PWM Sync Channels Update Period Register 0x2C 0x20 read-write UPR Update Period [3:0] read-write 0 15 UPRCNT Update Period Counter [7:4] read-write 0 15 SCUPUPD PWM Sync Channels Update Period Update Register 0x30 0x20 write-only UPRUPD Update Period Update [3:0] read-write 0 15 SMMR PWM Stepper Motor Mode Register 0xB0 0x20 read-write GCEN0 Gray Count Enable [0:0] read-write GCEN1 Gray Count Enable [1:1] read-write DOWN0 Down Count [16:16] read-write DOWN1 Down Count [17:17] read-write SR PWM Status Register 0xC 0x20 read-only CHID0 Channel ID [0:0] read-write CHID1 Channel ID [1:1] read-write CHID2 Channel ID [2:2] read-write CHID3 Channel ID [3:3] read-write SSPR PWM Spread Spectrum Register 0xA0 0x20 read-write SPRD Spread Spectrum Limit Value [23:0] read-write 0 16777215 SPRDM Spread Spectrum Counter Mode [24:24] read-write SSPUP PWM Spread Spectrum Update Register 0xA4 0x20 write-only SPRDUP Spread Spectrum Limit Value Update [23:0] read-write 0 16777215 WPCR PWM Write Protection Control Register 0xE4 0x20 write-only WPCMD Write Protection Command [1:0] read-write true DISABLE_SW_PROT Disables the software write protection of the register groups of which the bit WPRGx is at '1'. 0 ENABLE_SW_PROT Enables the software write protection of the register groups of which the bit WPRGx is at '1'. 1 ENABLE_HW_PROT Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. 2 WPRG0 Write Protection Register Group 0 [2:2] read-write WPRG1 Write Protection Register Group 1 [3:3] read-write WPRG2 Write Protection Register Group 2 [4:4] read-write WPRG3 Write Protection Register Group 3 [5:5] read-write WPRG4 Write Protection Register Group 4 [6:6] read-write WPRG5 Write Protection Register Group 5 [7:7] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 5265229 WPSR PWM Write Protection Status Register 0xE8 0x20 read-only WPSWS0 Write Protect SW Status [0:0] read-write WPSWS1 Write Protect SW Status [1:1] read-write WPSWS2 Write Protect SW Status [2:2] read-write WPSWS3 Write Protect SW Status [3:3] read-write WPSWS4 Write Protect SW Status [4:4] read-write WPSWS5 Write Protect SW Status [5:5] read-write WPVS Write Protect Violation Status [7:7] read-write WPHWS0 Write Protect HW Status [8:8] read-write WPHWS1 Write Protect HW Status [9:9] read-write WPHWS2 Write Protect HW Status [10:10] read-write WPHWS3 Write Protect HW Status [11:11] read-write WPHWS4 Write Protect HW Status [12:12] read-write WPHWS5 Write Protect HW Status [13:13] read-write WPVSRC Write Protect Violation Source [31:16] read-write 0 65535 QSPI0 Quad Serial Peripheral Interface 0xF0020000 0x0 0x24 registers 0x30 0xC registers 0x40 0x8 registers 0xE4 0x8 registers CR Control Register 0x0 0x20 write-only QSPIEN QSPI Enable [0:0] read-write QSPIDIS QSPI Disable [1:1] read-write SWRST QSPI Software Reset [7:7] read-write LASTXFER Last Transfer [24:24] read-write IAR Instruction Address Register 0x30 0x20 read-write ADDR Address [31:0] read-write 0 4294967295 ICR Instruction Code Register 0x34 0x20 read-write INST Instruction Code [7:0] read-write 0 255 OPT Option Code [23:16] read-write 0 255 IDR Interrupt Disable Register 0x18 0x20 write-only RDRF Receive Data Register Full Interrupt Disable [0:0] read-write TDRE Transmit Data Register Empty Interrupt Disable [1:1] read-write TXEMPTY Transmission Registers Empty Disable [2:2] read-write OVRES Overrun Error Interrupt Disable [3:3] read-write CSR Chip Select Rise Interrupt Disable [8:8] read-write CSS Chip Select Status Interrupt Disable [9:9] read-write INSTRE Instruction End Interrupt Disable [10:10] read-write IER Interrupt Enable Register 0x14 0x20 write-only RDRF Receive Data Register Full Interrupt Enable [0:0] read-write TDRE Transmit Data Register Empty Interrupt Enable [1:1] read-write TXEMPTY Transmission Registers Empty Enable [2:2] read-write OVRES Overrun Error Interrupt Enable [3:3] read-write CSR Chip Select Rise Interrupt Enable [8:8] read-write CSS Chip Select Status Interrupt Enable [9:9] read-write INSTRE Instruction End Interrupt Enable [10:10] read-write IFR Instruction Frame Register 0x38 0x20 read-write WIDTH Width of Instruction Code, Address, Option Code and Data [2:0] read-write true SINGLE_BIT_SPI Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI 0 DUAL_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI 1 QUAD_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI 2 DUAL_IO Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI 3 QUAD_IO Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI 4 DUAL_CMD Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI 5 QUAD_CMD Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI 6 INSTEN Instruction Enable [4:4] read-write ADDREN Address Enable [5:5] read-write OPTEN Option Enable [6:6] read-write DATAEN Data Enable [7:7] read-write OPTL Option Code Length [9:8] read-write true OPTION_1BIT The option code is 1 bit long. 0 OPTION_2BIT The option code is 2 bits long. 1 OPTION_4BIT The option code is 4 bits long. 2 OPTION_8BIT The option code is 8 bits long. 3 ADDRL Address Length [10:10] read-write true _24_BIT The address is 24 bits long. 0 _32_BIT The address is 32 bits long. 1 TFRTYP Data Transfer Type [13:12] read-write true TRSFR_READ Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. 0 TRSFR_READ_MEMORY Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. 1 TRSFR_WRITE Write transfer into the serial memory.Scrambling is not performed. 2 TRSFR_WRITE_MEMORY Write data transfer into the serial memory.If enabled, scrambling is performed. 3 CRM Continuous Read Mode [14:14] read-write true DISABLED Continuous Read mode is disabled. 0 ENABLED Continuous Read mode is enabled. 1 NBDUM Number Of Dummy Cycles [20:16] read-write 0 31 IMR Interrupt Mask Register 0x1C 0x20 read-only RDRF Receive Data Register Full Interrupt Mask [0:0] read-write TDRE Transmit Data Register Empty Interrupt Mask [1:1] read-write TXEMPTY Transmission Registers Empty Mask [2:2] read-write OVRES Overrun Error Interrupt Mask [3:3] read-write CSR Chip Select Rise Interrupt Mask [8:8] read-write CSS Chip Select Status Interrupt Mask [9:9] read-write INSTRE Instruction End Interrupt Mask [10:10] read-write MR Mode Register 0x4 0x20 read-write SMM Serial Memory Mode [0:0] read-write true SPI The QSPI is in SPI mode. 0 MEMORY The QSPI is in Serial Memory mode. 1 LLB Local Loopback Enable [1:1] read-write true DISABLED Local loopback path disabled. 0 ENABLED Local loopback path enabled. 1 WDRBT Wait Data Read Before Transfer [2:2] read-write true DISABLED No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. 0 ENABLED In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. 1 SMRM Serial Memory Register Mode [3:3] read-write CSMODE Chip Select Mode [5:4] read-write true NOT_RELOADED The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. 0 LASTXFER The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. 1 SYSTEMATICALLY The chip select is deasserted systematically after each transfer. 2 NBBITS Number Of Bits Per Transfer [11:8] read-write true _8_BIT 8 bits for transfer 0 _16_BIT 16 bits for transfer 8 PHYCR Physical Interface Clock Ratio [14:14] read-write true RATIO_1_1 The physical interface clock is at the same speed as the QSPI controller clock. 0 RATIO_1_2 The physical interface clock is twice as fast as the QSPI controller clock. 1 DLYBCT Delay Between Consecutive Transfers [23:16] read-write 0 255 DLYCS Minimum Inactive QCS Delay [31:24] read-write 0 255 RDR Receive Data Register 0x8 0x20 read-only RD Receive Data [15:0] read-write 0 65535 SCR Serial Clock Register 0x20 0x20 read-write CPOL Clock Polarity [0:0] read-write CPHA Clock Phase [1:1] read-write SCBR Serial Clock Baud Rate [15:8] read-write 0 255 DLYBS Delay Before QSCK [23:16] read-write 0 255 SKR Scrambling Key Register 0x44 0x20 write-only USRK User Scrambling Key [31:0] read-write 0 4294967295 SMR Scrambling Mode Register 0x40 0x20 read-write SCREN Scrambling/Unscrambling Enable [0:0] read-write true DISABLED The scrambling/unscrambling is disabled. 0 ENABLED The scrambling/unscrambling is enabled. 1 RVDIS Scrambling/Unscrambling Random Value Disable [1:1] read-write SR Status Register 0x10 0x20 read-only RDRF Receive Data Register Full (cleared by reading QSPI_RDR) [0:0] read-write TDRE Transmit Data Register Empty (cleared by writing QSPI_TDR) [1:1] read-write TXEMPTY Transmission Registers Empty (cleared by writing QSPI_TDR) [2:2] read-write OVRES Overrun Error Status (cleared on read) [3:3] read-write CSR Chip Select Rise (cleared on read) [8:8] read-write CSS Chip Select Status [9:9] read-write INSTRE Instruction End Status (cleared on read) [10:10] read-write QSPIENS QSPI Enable Status [24:24] read-write TDR Transmit Data Register 0xC 0x20 write-only TD Transmit Data [15:0] read-write 0 65535 WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 5329744 WPSR Write Protection Status Register 0xE8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [15:8] read-write 0 255 QSPI1 Quad Serial Peripheral Interface 0xF0024000 RSTC Reset Controller 0xF8048000 0x0 0xC registers CR Control Register 0x0 0x20 write-only PROCRST Processor Reset [0:0] read-write KEY Write Access Password [31:24] read-write true PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 165 MR Mode Register 0x8 0x20 read-write URSTEN User Reset Enable [0:0] read-write URSTIEN User Reset Interrupt Enable [4:4] read-write KEY Write Access Password [31:24] read-write true PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 165 SR Status Register 0x4 0x20 read-only URSTS User Reset Status [0:0] read-write RSTTYP Reset Type [10:8] read-write true GENERAL_RST Both VDDCORE and VDDBU rising 0 WKUP_RST VDDCORE rising 1 WDT_RST Watchdog fault occurred 2 SOFT_RST Processor reset required by the software 3 USER_RST NRST pin detected low 4 NRSTL NRST Pin Level [16:16] read-write SRCMP Software Reset Command in Progress [17:17] read-write RTC Real-time Clock 0xF80480B0 0x0 0x30 registers CALALR Calendar Alarm Register 0x14 0x20 read-write UTCEN UTC Alarm Enable [0:0] read-write MONTH Month Alarm [20:16] read-write 0 31 MTHEN Month Alarm Enable [23:23] read-write DATE Date Alarm [29:24] read-write 0 63 DATEEN Date Alarm Enable [31:31] read-write CALR Calendar Register 0xC 0x20 read-write CENT Current Century [6:0] read-write 0 127 YEAR Current Year [15:8] read-write 0 255 MONTH Current Month [20:16] read-write 0 31 DAY Current Day in Current Week [23:21] read-write 0 7 DATE Current Day in Current Month [29:24] read-write 0 63 CR Control Register 0x0 0x20 read-write UPDTIM Update Request Time Register [0:0] read-write UPDCAL Update Request Calendar Register [1:1] read-write TIMEVSEL Time Event Selection [9:8] read-write true MINUTE Minute change 0 HOUR Hour change 1 MIDNIGHT Every day at midnight 2 NOON Every day at noon 3 CALEVSEL Calendar Event Selection [17:16] read-write true WEEK Week change (every Monday at time 00:00:00) 0 MONTH Month change (every 01 of each month at time 00:00:00) 1 YEAR Year change (every January 1 at time 00:00:00) 2 IDR Interrupt Disable Register 0x24 0x20 write-only ACKDIS Acknowledge Update Interrupt Disable [0:0] read-write ALRDIS Alarm Interrupt Disable [1:1] read-write SECDIS Second Event Interrupt Disable [2:2] read-write TIMDIS Time Event Interrupt Disable [3:3] read-write CALDIS Calendar Event Interrupt Disable [4:4] read-write TDERRDIS Time and/or Date Error Interrupt Disable [5:5] read-write IER Interrupt Enable Register 0x20 0x20 write-only ACKEN Acknowledge Update Interrupt Enable [0:0] read-write ALREN Alarm Interrupt Enable [1:1] read-write SECEN Second Event Interrupt Enable [2:2] read-write TIMEN Time Event Interrupt Enable [3:3] read-write CALEN Calendar Event Interrupt Enable [4:4] read-write TDERREN Time and/or Date Error Interrupt Enable [5:5] read-write IMR Interrupt Mask Register 0x28 0x20 read-only ACK Acknowledge Update Interrupt Mask [0:0] read-write ALR Alarm Interrupt Mask [1:1] read-write SEC Second Event Interrupt Mask [2:2] read-write TIM Time Event Interrupt Mask [3:3] read-write CAL Calendar Event Interrupt Mask [4:4] read-write TDERR Time and/or Date Error Mask [5:5] read-write MR Mode Register 0x4 0x20 read-write HRMOD 12-/24-hour Mode [0:0] read-write PERSIAN PERSIAN Calendar [1:1] read-write UTC UTC Time Format [2:2] read-write NEGPPM NEGative PPM Correction [4:4] read-write CORRECTION Slow Clock Correction [14:8] read-write 0 127 HIGHPPM HIGH PPM Correction [15:15] read-write OUT0 All ADC Channel Trigger Event Source Selection [18:16] read-write true NO_WAVE No waveform, stuck at '0' 0 FREQ1HZ 1 Hz square wave 1 FREQ32HZ 32 Hz square wave 2 FREQ64HZ 64 Hz square wave 3 FREQ512HZ 512 Hz square wave 4 ALARM_TOGGLE Output toggles when alarm flag rises 5 ALARM_FLAG Output is a copy of the alarm flag 6 PROG_PULSE Duty cycle programmable pulse 7 OUT1 ADC Last Channel Trigger Event Source Selection [22:20] read-write true NO_WAVE No waveform, stuck at '0' 0 FREQ1HZ 1 Hz square wave 1 FREQ32HZ 32 Hz square wave 2 FREQ64HZ 64 Hz square wave 3 FREQ512HZ 512 Hz square wave 4 ALARM_TOGGLE Output toggles when alarm flag rises 5 ALARM_FLAG Output is a copy of the alarm flag 6 PROG_PULSE Duty cycle programmable pulse 7 THIGH High Duration of the Output Pulse [26:24] read-write true H_31MS 31.2 ms 0 H_16MS 15.6 ms 1 H_4MS 3.91 ms 2 H_976US 976 us 3 H_488US 488 us 4 H_122US 122 us 5 H_30US 30.5 us 6 H_15US 15.2 us 7 TPERIOD Period of the Output Pulse [29:28] read-write true P_1S 1 second 0 P_500MS 500 ms 1 P_250MS 250 ms 2 P_125MS 125 ms 3 SCCR Status Clear Command Register 0x1C 0x20 write-only ACKCLR Acknowledge Clear [0:0] read-write ALRCLR Alarm Clear [1:1] read-write SECCLR Second Clear [2:2] read-write TIMCLR Time Clear [3:3] read-write CALCLR Calendar Clear [4:4] read-write TDERRCLR Time and/or Date Free Running Error Clear [5:5] read-write SR Status Register 0x18 0x20 read-only ACKUPD Acknowledge for Update [0:0] read-write true FREERUN Time and calendar registers cannot be updated. 0 UPDATE Time and calendar registers can be updated. 1 ALARM Alarm Flag [1:1] read-write true NO_ALARMEVENT No alarm matching condition occurred. 0 ALARMEVENT An alarm matching condition has occurred. 1 SEC Second Event [2:2] read-write true NO_SECEVENT No second event has occurred since the last clear. 0 SECEVENT At least one second event has occurred since the last clear. 1 TIMEV Time Event [3:3] read-write true NO_TIMEVENT No time event has occurred since the last clear. 0 TIMEVENT At least one time event has occurred since the last clear. 1 CALEV Calendar Event [4:4] read-write true NO_CALEVENT No calendar event has occurred since the last clear. 0 CALEVENT At least one calendar event has occurred since the last clear. 1 TDERR Time and/or Date Free Running Error [5:5] read-write true CORRECT The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). 0 ERR_TIMEDATE The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. 1 TIMALR Time Alarm Register 0x10 0x20 read-write SEC Second Alarm [6:0] read-write 0 127 UTC_TIME UTC_TIME Alarm [31:0] read-write 0 4294967295 SECEN Second Alarm Enable [7:7] read-write MIN Minute Alarm [14:8] read-write 0 127 MINEN Minute Alarm Enable [15:15] read-write HOUR Hour Alarm [21:16] read-write 0 63 AMPM AM/PM Indicator [22:22] read-write HOUREN Hour Alarm Enable [23:23] read-write TIMR Time Register 0x8 0x20 read-write SEC Current Second [6:0] read-write 0 127 UTC_TIME Current UTC Time [31:0] read-write 0 4294967295 MIN Current Minute [14:8] read-write 0 127 HOUR Current Hour [21:16] read-write 0 63 AMPM Ante Meridiem Post Meridiem Indicator [22:22] read-write VER Valid Entry Register 0x2C 0x20 read-only NVTIM Non-valid Time [0:0] read-write NVCAL Non-valid Calendar [1:1] read-write NVTIMALR Non-valid Time Alarm [2:2] read-write NVCALALR Non-valid Calendar Alarm [3:3] read-write RXLP Low Power Asynchronous Receiver 0xF8049000 0x0 0x8 registers 0x18 0x4 registers 0x20 0x8 registers 0xE4 0x4 registers BRGR Baud Rate Generator Register 0x20 0x20 read-write CD Clock Divisor [1:0] read-write 0 3 CMPR Comparison Register 0x24 0x20 read-write VAL1 First Comparison Value for Received Character [7:0] read-write 0 255 VAL2 Second Comparison Value for Received Character [23:16] read-write 0 255 CR Control Register 0x0 0x20 write-only RSTRX Reset Receiver [2:2] read-write RXEN Receiver Enable [4:4] read-write RXDIS Receiver Disable [5:5] read-write MR Mode Register 0x4 0x20 read-write FILTER Receiver Digital Filter [4:4] read-write true DISABLED RXLP does not filter the receive line. 0 ENABLED RXLP filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type [11:9] read-write true EVEN Even Parity 0 ODD Odd Parity 1 SPACE Parity forced to 0 2 MARK Parity forced to 1 3 NO No parity 4 RHR Receive Holding Register 0x18 0x20 read-only RXCHR Received Character [7:0] read-write 0 255 WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 5396556 SAIC Advanced Interrupt Controller 0xF803C000 0x0 0xC registers 0x10 0xC registers 0x20 0x30 registers 0x6C 0x4 registers 0xE4 0x8 registers CISR Core Interrupt Status Register 0x34 0x20 read-only NFIQ NFIQ Status [0:0] read-write NIRQ NIRQ Status [1:1] read-write DCR Debug Control Register 0x6C 0x20 read-write PROT Protection Mode [0:0] read-write GMSK General Interrupt Mask [1:1] read-write EOICR End of Interrupt Command Register 0x38 0x20 write-only ENDIT Interrupt Processing Complete Command [0:0] read-write FVR FIQ Vector Register 0x14 0x20 read-only FIQV FIQ Vector Register [31:0] read-write 0 4294967295 ICCR Interrupt Clear Command Register 0x48 0x20 write-only INTCLR Interrupt Clear [0:0] read-write IDCR Interrupt Disable Command Register 0x44 0x20 write-only INTD Interrupt Disable [0:0] read-write IECR Interrupt Enable Command Register 0x40 0x20 write-only INTEN Interrupt Enable [0:0] read-write IMR Interrupt Mask Register 0x30 0x20 read-only INTM Interrupt Mask [0:0] read-write IPR0 Interrupt Pending Register 0 0x20 0x20 read-only FIQ Interrupt Pending [0:0] read-write PID1 Interrupt Pending [1:1] read-write PID2 Interrupt Pending [2:2] read-write PID3 Interrupt Pending [3:3] read-write PID4 Interrupt Pending [4:4] read-write PID5 Interrupt Pending [5:5] read-write PID6 Interrupt Pending [6:6] read-write PID7 Interrupt Pending [7:7] read-write PID8 Interrupt Pending [8:8] read-write PID9 Interrupt Pending [9:9] read-write PID10 Interrupt Pending [10:10] read-write PID11 Interrupt Pending [11:11] read-write PID12 Interrupt Pending [12:12] read-write PID13 Interrupt Pending [13:13] read-write PID14 Interrupt Pending [14:14] read-write PID15 Interrupt Pending [15:15] read-write PID16 Interrupt Pending [16:16] read-write PID17 Interrupt Pending [17:17] read-write PID18 Interrupt Pending [18:18] read-write PID19 Interrupt Pending [19:19] read-write PID20 Interrupt Pending [20:20] read-write PID21 Interrupt Pending [21:21] read-write PID22 Interrupt Pending [22:22] read-write PID23 Interrupt Pending [23:23] read-write PID24 Interrupt Pending [24:24] read-write PID25 Interrupt Pending [25:25] read-write PID26 Interrupt Pending [26:26] read-write PID27 Interrupt Pending [27:27] read-write PID28 Interrupt Pending [28:28] read-write PID29 Interrupt Pending [29:29] read-write PID30 Interrupt Pending [30:30] read-write PID31 Interrupt Pending [31:31] read-write IPR1 Interrupt Pending Register 1 0x24 0x20 read-only PID32 Interrupt Pending [0:0] read-write PID33 Interrupt Pending [1:1] read-write PID34 Interrupt Pending [2:2] read-write PID35 Interrupt Pending [3:3] read-write PID36 Interrupt Pending [4:4] read-write PID37 Interrupt Pending [5:5] read-write PID38 Interrupt Pending [6:6] read-write PID39 Interrupt Pending [7:7] read-write PID40 Interrupt Pending [8:8] read-write PID41 Interrupt Pending [9:9] read-write PID42 Interrupt Pending [10:10] read-write PID43 Interrupt Pending [11:11] read-write PID44 Interrupt Pending [12:12] read-write PID45 Interrupt Pending [13:13] read-write PID46 Interrupt Pending [14:14] read-write PID47 Interrupt Pending [15:15] read-write PID48 Interrupt Pending [16:16] read-write PID49 Interrupt Pending [17:17] read-write PID50 Interrupt Pending [18:18] read-write PID51 Interrupt Pending [19:19] read-write PID52 Interrupt Pending [20:20] read-write PID53 Interrupt Pending [21:21] read-write PID54 Interrupt Pending [22:22] read-write PID55 Interrupt Pending [23:23] read-write PID56 Interrupt Pending [24:24] read-write PID57 Interrupt Pending [25:25] read-write PID58 Interrupt Pending [26:26] read-write PID59 Interrupt Pending [27:27] read-write PID60 Interrupt Pending [28:28] read-write PID61 Interrupt Pending [29:29] read-write PID62 Interrupt Pending [30:30] read-write PID63 Interrupt Pending [31:31] read-write IPR2 Interrupt Pending Register 2 0x28 0x20 read-only PID64 Interrupt Pending [0:0] read-write PID65 Interrupt Pending [1:1] read-write PID66 Interrupt Pending [2:2] read-write PID67 Interrupt Pending [3:3] read-write PID68 Interrupt Pending [4:4] read-write PID69 Interrupt Pending [5:5] read-write PID70 Interrupt Pending [6:6] read-write PID71 Interrupt Pending [7:7] read-write PID72 Interrupt Pending [8:8] read-write PID73 Interrupt Pending [9:9] read-write SYS Interrupt Pending [10:10] read-write PID75 Interrupt Pending [11:11] read-write PID76 Interrupt Pending [12:12] read-write PID77 Interrupt Pending [13:13] read-write PID78 Interrupt Pending [14:14] read-write PID79 Interrupt Pending [15:15] read-write PID80 Interrupt Pending [16:16] read-write PID81 Interrupt Pending [17:17] read-write PID82 Interrupt Pending [18:18] read-write PID83 Interrupt Pending [19:19] read-write PID84 Interrupt Pending [20:20] read-write PID85 Interrupt Pending [21:21] read-write PID86 Interrupt Pending [22:22] read-write PID87 Interrupt Pending [23:23] read-write PID88 Interrupt Pending [24:24] read-write PID89 Interrupt Pending [25:25] read-write PID90 Interrupt Pending [26:26] read-write PID91 Interrupt Pending [27:27] read-write PID92 Interrupt Pending [28:28] read-write PID93 Interrupt Pending [29:29] read-write PID94 Interrupt Pending [30:30] read-write PID95 Interrupt Pending [31:31] read-write IPR3 Interrupt Pending Register 3 0x2C 0x20 read-only PID96 Interrupt Pending [0:0] read-write PID97 Interrupt Pending [1:1] read-write PID98 Interrupt Pending [2:2] read-write PID99 Interrupt Pending [3:3] read-write PID100 Interrupt Pending [4:4] read-write PID101 Interrupt Pending [5:5] read-write PID102 Interrupt Pending [6:6] read-write PID103 Interrupt Pending [7:7] read-write PID104 Interrupt Pending [8:8] read-write PID105 Interrupt Pending [9:9] read-write PID106 Interrupt Pending [10:10] read-write PID107 Interrupt Pending [11:11] read-write PID108 Interrupt Pending [12:12] read-write PID109 Interrupt Pending [13:13] read-write PID110 Interrupt Pending [14:14] read-write PID111 Interrupt Pending [15:15] read-write PID112 Interrupt Pending [16:16] read-write PID113 Interrupt Pending [17:17] read-write PID114 Interrupt Pending [18:18] read-write PID115 Interrupt Pending [19:19] read-write PID116 Interrupt Pending [20:20] read-write PID117 Interrupt Pending [21:21] read-write PID118 Interrupt Pending [22:22] read-write PID119 Interrupt Pending [23:23] read-write PID120 Interrupt Pending [24:24] read-write PID121 Interrupt Pending [25:25] read-write PID122 Interrupt Pending [26:26] read-write PID123 Interrupt Pending [27:27] read-write PID124 Interrupt Pending [28:28] read-write PID125 Interrupt Pending [29:29] read-write PID126 Interrupt Pending [30:30] read-write PID127 Interrupt Pending [31:31] read-write ISCR Interrupt Set Command Register 0x4C 0x20 write-only INTSET Interrupt Set [0:0] read-write ISR Interrupt Status Register 0x18 0x20 read-only IRQID Current Interrupt Identifier [6:0] read-write 0 127 IVR Interrupt Vector Register 0x10 0x20 read-only IRQV Interrupt Vector Register [31:0] read-write 0 4294967295 SMR Source Mode Register 0x4 0x20 read-write PRIORITY Priority Level [2:0] read-write true MINIMUM Minimum priority 0 VERY_LOW Very low priority 1 LOW Low priority 2 MEDIUM_LOW Medium priority 3 MEDIUM_HIGH Medium-high priority 4 HIGH High priority 5 VERY_HIGH Very high priority 6 MAXIMUM Maximum priority 7 SRCTYPE Interrupt Source Type [6:5] read-write true INT_LEVEL_SENSITIVE High-level sensitive for internal source. Low-level sensitive for external source 0 EXT_NEGATIVE_EDGE Negative-edge triggered for external source 1 EXT_HIGH_LEVEL High-level sensitive for internal source. High-level sensitive for external source 2 EXT_POSITIVE_EDGE Positive-edge triggered for external source 3 SPU Spurious Interrupt Vector Register 0x3C 0x20 read-write SIVR Spurious Interrupt Vector Register [31:0] read-write 0 4294967295 SSR Source Select Register 0x0 0x20 read-write INTSEL Interrupt Line Selection [6:0] read-write 0 127 SVR Source Vector Register 0x8 0x20 read-write VECTOR Source Vector [31:0] read-write 0 4294967295 WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 4278595 WPSR Write Protection Status Register 0xE8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [23:8] read-write 0 65535 SCKC Slow Clock Controller 0xF8048050 0x0 0x4 registers SCKC_CR Slow Clock Controller Configuration Register 0x0 0x20 read-write OSCSEL Slow Clock Selector [3:3] read-write true RC Slow clock is the embedded 64 kHz (typical) RC oscillator. 0 XTAL Slow clock is the 32.768 kHz crystal oscillator. 1 SDMMC0 Secure Digital MultiMedia Card Controller 0xA0000000 0x0 0x14 registers 0x20 0x2C registers 0x50 0x5 registers 0x58 0x4 registers 0x60 0x2 registers 0xFC 0x4 registers 0x200 0x6 registers 0x208 0xA registers 0x214 0x6 registers 0x21C 0x2 registers 0x220 0x4 registers 0x230 0x4 registers 0x240 0x4 registers ACESR Auto CMD Error Status Register 0x3C 0x10 read-only ACMD12NE Auto CMD12 Not Executed [0:0] read-write ACMDTEO Auto CMD Timeout Error [1:1] read-write ACMDCRC Auto CMD CRC Error [2:2] read-write ACMDEND Auto CMD End Bit Error [3:3] read-write ACMDIDX Auto CMD Index Error [4:4] read-write CMDNI Command Not Issued by Auto CMD12 Error [7:7] read-write ACR AHB Control Register 0x208 0x20 read-write BMAX AHB Maximum Burst [1:0] read-write true INCR16 The maximum burst size is INCR16. 0 INCR8 The maximum burst size is INCR8. 1 INCR4 The maximum burst size is INCR4. 2 SINGLE Only SINGLE transfers are performed. 3 AESR ADMA Error Status Register 0x54 0x8 read-only ERRST ADMA Error State [1:0] read-write 0 3 LMIS ADMA Length Mismatch Error [2:2] read-write APSR Additional Present State Register 0x200 0x20 read-only HDATLL DAT[7:4] High Line Level [3:0] read-write 0 15 ARG1R Argument 1 Register 0x8 0x20 read-write ARG1 Argument 1 [31:0] read-write 0 4294967295 ASAR0 ADMA System Address Register 0 0x58 0x20 read-write ADMASA ADMA System Address [31:0] read-write 0 4294967295 BCR Block Count Register 0x6 0x10 read-write BLKCNT Block Count for Current Transfer [15:0] read-write 0 65535 BDPR Buffer Data Port Register 0x20 0x20 read-write BUFDATA Buffer Data [31:0] read-write 0 4294967295 BGCR Block Gap Control Register 0x2A 0x8 read-write STPBGR Stop At Block Gap Request [0:0] read-write CONTR Continue Request [1:1] read-write RWCTRL Read Wait Control [2:2] read-write INTBG Interrupt at Block Gap [3:3] read-write true DISABLED Interrupt detection disabled. 0 ENABLED Interrupt detection enabled. 1 BSR Block Size Register 0x4 0x10 read-write BLKSIZE Transfer Block Size [9:0] read-write 0 1023 BOUNDARY SDMA Buffer Boundary [14:12] read-write true _4K 4-Kbyte boundary 0 _8K 8-Kbyte boundary 1 _16K 16-Kbyte boundary 2 _32K 32-Kbyte boundary 3 _64K 64-Kbyte boundary 4 _128K 128-Kbyte boundary 5 _256k 256-Kbyte boundary 6 _512K 512-Kbyte boundary 7 CA0R Capabilities 0 Register 0x40 0x20 read-only TEOCLKF Timeout Clock Frequency [5:0] read-write 0 63 TEOCLKU Timeout Clock Unit [7:7] read-write BASECLKF Base Clock Frequency [15:8] read-write 0 255 MAXBLKL Max Block Length [17:16] read-write true _512 512 bytes 0 _1024 1024 bytes 1 _2048 2048 bytes 2 ED8SUP 8-Bit Support for Embedded Device [18:18] read-write ADMA2SUP ADMA2 Support [19:19] read-write HSSUP High Speed Support [21:21] read-write SDMASUP SDMA Support [22:22] read-write SRSUP Suspend/Resume Support [23:23] read-write V33VSUP Voltage Support 3.3V [24:24] read-write V30VSUP Voltage Support 3.0V [25:25] read-write V18VSUP Voltage Support 1.8V [26:26] read-write SB64SUP 64-Bit System Bus Support [28:28] read-write ASINTSUP Asynchronous Interrupt Support [29:29] read-write SLTYPE Slot Type [31:30] read-write 0 3 CA1R Capabilities 1 Register 0x44 0x20 read-write SDR50SUP SDR50 Support [0:0] read-write SDR104SUP SDR104 Support [1:1] read-write DDR50SUP DDR50 Support [2:2] read-write DRVASUP Driver Type A Support [4:4] read-write DRVCSUP Driver Type C Support [5:5] read-write DRVDSUP Driver Type D Support [6:6] read-write TCNTRT Timer Count For Retuning [11:8] read-write 0 15 TSDR50 Use Tuning for SDR50 [13:13] read-write RTMOD Retuning Modes [15:14] read-write true MODE1 Timer 0 MODE2 Timer and Retuning Request 1 MODE3 Auto Retuning (for transfer) Timer and Retuning Request 2 CLKMULT Clock Multiplier [23:16] read-write 0 255 CACR Capabilities Control Register 0x230 0x20 read-write CAPWREN Capabilities Write Enable [0:0] read-write KEY Key [15:8] read-write 0 255 CALCR Calibration Control Register 0x240 0x20 read-write EN PADs Calibration Enable [0:0] read-write ALWYSON Calibration Analog Always ON [4:4] read-write TUNDIS Calibration During Tuning Disabled [5:5] read-write CNTVAL Calibration Counter Value [15:8] read-write 0 255 CALN Calibration N Status [19:16] read-write 0 15 CALP Calibration P Status [27:24] read-write 0 15 CC2R Clock Control 2 Register 0x20C 0x20 read-write FSDCLKD Force SDCLK Disabled [0:0] read-write CCR Clock Control Register 0x2C 0x10 read-write INTCLKEN Internal Clock Enable [0:0] read-write INTCLKS Internal Clock Stable [1:1] read-write SDCLKEN SD Clock Enable [2:2] read-write CLKGSEL Clock Generator Select [5:5] read-write USDCLKFSEL Upper Bits of SDCLK Frequency Select [7:6] read-write 0 3 SDCLKFSEL SDCLK Frequency Select [15:8] read-write 0 255 CR Command Register 0xE 0x10 read-write RESPTYP Response Type [1:0] read-write true NORESP No Response 0 RL136 Response Length 136 1 RL48 Response Length 48 2 RL48BUSY Response Length 48 with Busy 3 CMDCCEN Command CRC Check Enable [3:3] read-write true DISABLED The Command CRC Check is disabled. 0 ENABLED The Command CRC Check is enabled. 1 CMDICEN Command Index Check Enable [4:4] read-write true DISABLED The Command Index Check is disabled. 0 ENABLED The Command Index Check is enabled. 1 DPSEL Data Present Select [5:5] read-write CMDTYP Command Type [7:6] read-write true NORMAL Other commands 0 SUSPEND CMD52 to write "Bus Suspend" in the Card Common Control Registers (CCCR) (for SDIO only) 1 RESUME CMD52 to write "Function Select" in the Card Common Control Registers (CCCR) (for SDIO only) 2 ABORT CMD12, CMD52 to write "I/O Abort" in the Card Common Control Registers (CCCR) (for SDIO only) 3 CMDIDX Command Index [13:8] read-write 0 63 EISIER Error Interrupt Signal Enable Register 0x3A 0x10 read-write CMDTEO Command Timeout Error Signal Enable [0:0] read-write true MASKED No interrupt is generated when the CMDTEO status rises in SDMMC_EISTR. 0 ENABLED An interrupt is generated when the CMDTEO status rises in SDMMC_EISTR. 1 CMDCRC Command CRC Error Signal Enable [1:1] read-write true MASKED No interrupt is generated when the CDMCRC status rises in SDMMC_EISTR. 0 ENABLED An interrupt is generated when the CMDCRC status rises in SDMMC_EISTR. 1 CMDEND Command End Bit Error Signal Enable [2:2] read-write true MASKED No interrupt is generated when the CMDEND status rises in SDMMC_EISTR. 0 ENABLED An interrupt is generated when the CMDEND status rises in SDMMC_EISTR. 1 CMDIDX Command Index Error Signal Enable [3:3] read-write true MASKED No interrupt is generated when the CMDIDX status rises in SDMMC_EISTR. 0 ENABLED An interrupt is generated when the CMDIDX status rises in SDMMC_EISTR. 1 DATTEO Data Timeout Error Signal Enable [4:4] read-write true MASKED No interrupt is generated when the DATTEO status rises in SDMMC_EISTR. 0 ENABLED An interrupt is generated when the DATTEO status rises in SDMMC_EISTR. 1 DATCRC Data CRC Error Signal Enable [5:5] read-write true MASKED No interrupt is generated when the DATCRC status rises in SDMMC_EISTR. 0 ENABLED An interrupt is generated when the DATCRC status rises in SDMMC_EISTR. 1 DATEND Data End Bit Error Signal Enable [6:6] read-write true MASKED No interrupt is generated when the DATEND status rises in SDMMC_EISTR. 0 ENABLED An interrupt is generated when the DATEND status rises in SDMMC_EISTR. 1 CURLIM Current Limit Error Signal Enable [7:7] read-write true MASKED No interrupt is generated when the CURLIM status rises in SDMMC_EISTR. 0 ENABLED An interrupt is generated when the CURLIM status rises in SDMMC_EISTR. 1 ACMD Auto CMD Error Signal Enable [8:8] read-write true MASKED No interrupt is generated when the ACMD status rises in SDMMC_EISTR. 0 ENABLED An interrupt is generated when the ACMD status rises in SDMMC_EISTR. 1 ADMA ADMA Error Signal Enable [9:9] read-write true MASKED No interrupt is generated when the ADMA status rises in SDMMC_EISTR. 0 ENABLED An interrupt is generated when the ADMA status rises in SDMMC_EISTR. 1 BOOTAE Boot Acknowledge Error Signal Enable [12:12] read-write true MASKED No interrupt is generated when the BOOTAE status rises in SDMMC_EISTR. 0 ENABLED An interrupt is generated when the BOOTAE status rises in SDMMC_EISTR. 1 EISTER Error Interrupt Status Enable Register 0x36 0x10 read-write CMDTEO Command Timeout Error Status Enable [0:0] read-write true MASKED The CMDTEO status flag in SDMMC_EISTR is masked. 0 ENABLED The CMDTEO status flag in SDMMC_EISTR is enabled. 1 CMDCRC Command CRC Error Status Enable [1:1] read-write true MASKED The CMDCRC status flag in SDMMC_EISTR is masked. 0 ENABLED The CMDCRC status flag in SDMMC_EISTR is enabled. 1 CMDEND Command End Bit Error Status Enable [2:2] read-write true MASKED The CMDEND status flag in SDMMC_EISTR is masked. 0 ENABLED The CMDEND status flag in SDMMC_EISTR is enabled. 1 CMDIDX Command Index Error Status Enable [3:3] read-write true MASKED The CMDIDX status flag in SDMMC_EISTR is masked. 0 ENABLED The CMDIDX status flag in SDMMC_EISTR is enabled. 1 DATTEO Data Timeout Error Status Enable [4:4] read-write true MASKED The DATTEO status flag in SDMMC_EISTR is masked. 0 ENABLED The DATTEO status flag in SDMMC_EISTR is enabled. 1 DATCRC Data CRC Error Status Enable [5:5] read-write true MASKED The DATCRC status flag in SDMMC_EISTR is masked. 0 ENABLED The DATCRC status flag in SDMMC_EISTR is enabled. 1 DATEND Data End Bit Error Status Enable [6:6] read-write true MASKED The DATEND status flag in SDMMC_EISTR is masked. 0 ENABLED The DATEND status flag in SDMMC_EISTR is enabled. 1 CURLIM Current Limit Error Status Enable [7:7] read-write true MASKED The CURLIM status flag in SDMMC_EISTR is masked. 0 ENABLED The CURLIM status flag in SDMMC_EISTR is enabled. 1 ACMD Auto CMD Error Status Enable [8:8] read-write true MASKED The ACMD status flag in SDMMC_EISTR is masked. 0 ENABLED The ACMD status flag in SDMMC_EISTR is enabled. 1 ADMA ADMA Error Status Enable [9:9] read-write true MASKED The ADMA status flag in SDMMC_EISTR is masked. 0 ENABLED The ADMA status flag in SDMMC_EISTR is enabled. 1 BOOTAE Boot Acknowledge Error Status Enable [12:12] read-write true MASKED The BOOTAE status flag in SDMMC_EISTR is masked. 0 ENABLED The BOOTAE status flag in SDMMC_EISTR is enabled. 1 EISTR Error Interrupt Status Register 0x32 0x10 read-write CMDTEO Command Timeout Error [0:0] read-write CMDCRC Command CRC Error [1:1] read-write CMDEND Command End Bit Error [2:2] read-write CMDIDX Command Index Error [3:3] read-write DATTEO Data Timeout error [4:4] read-write DATCRC Data CRC Error [5:5] read-write DATEND Data End Bit Error [6:6] read-write CURLIM Current Limit Error [7:7] read-write ACMD Auto CMD Error [8:8] read-write ADMA ADMA Error [9:9] read-write BOOTAE Boot Acknowledge Error [12:12] read-write FERACES Force Event Register for Auto CMD Error Status 0x50 0x10 write-only ACMD12NE Force Event for Auto CMD12 Not Executed [0:0] read-write ACMDTEO Force Event for Auto CMD Timeout Error [1:1] read-write ACMDCRC Force Event for Auto CMD CRC Error [2:2] read-write ACMDEND Force Event for Auto CMD End Bit Error [3:3] read-write ACMDIDX Force Event for Auto CMD Index Error [4:4] read-write CMDNI Force Event for Command Not Issued by Auto CMD12 Error [7:7] read-write FEREIS Force Event Register for Error Interrupt Status 0x52 0x10 write-only CMDTEO Force Event for Command Timeout Error [0:0] read-write CMDCRC Force Event for Command CRC Error [1:1] read-write CMDEND Force Event for Command End Bit Error [2:2] read-write CMDIDX Force Event for Command Index Error [3:3] read-write DATTEO Force Event for Data Timeout error [4:4] read-write DATCRC Force Event for Data CRC error [5:5] read-write DATEND Force Event for Data End Bit Error [6:6] read-write CURLIM Force Event for Current Limit Error [7:7] read-write ACMD Force Event for Auto CMD Error [8:8] read-write ADMA Force Event for ADMA Error [9:9] read-write BOOTAE Force Event for Boot Acknowledge Error [12:12] read-write HC1R Host Control 1 Register 0x28 0x8 read-write LEDCTRL LED Control [0:0] read-write true OFF LED off. 0 ON LED on. 1 DW Data Width [1:1] read-write true _1_BIT 1-bit mode. 0 _4_BIT 4-bit mode. 1 HSEN High Speed Enable [2:2] read-write DMASEL DMA Select [4:3] read-write true SDMA SDMA is selected 0 ADMA32 32-bit Address ADMA2 is selected 2 EXTDW Extended Data Width [5:5] read-write CARDDTL Card Detect Test Level [6:6] read-write CARDDSEL Card Detect Signal Selection [7:7] read-write HC2R Host Control 2 Register 0x3E 0x10 read-write HS200EN HS200 Mode Enable [3:0] read-write 0 15 UHSMS UHS Mode Select [2:0] read-write true SDR12 UHS SDR12 Mode 0 SDR25 UHS SDR25 Mode 1 SDR50 UHS SDR50 Mode 2 SDR104 UHS SDR104 Mode 3 DDR50 UHS DDR50 Mode 4 VS18EN 1.8V Signaling Enable [3:3] read-write DRVSEL Driver Strength Select [5:4] read-write true TYPEB Driver Type B is selected (Default) 0 TYPEA Driver Type A is selected 1 TYPEC Driver Type C is selected 2 TYPED Driver Type D is selected 3 EXTUN Execute Tuning [6:6] read-write SCLKSEL Sampling Clock Select [7:7] read-write ASINTEN Asynchronous Interrupt Enable [14:14] read-write PVALEN Preset Value Enable [15:15] read-write HCVR Host Controller Version Register 0xFE 0x10 read-only SVER Specification Version Number [7:0] read-write 0 255 VVER Vendor Version Number [15:8] read-write 0 255 MC1R e.MMC Control 1 Register 0x204 0x8 read-write CMDTYP e.MMC Command Type [1:0] read-write true NORMAL The command is not an e.MMC specific command. 0 WAITIRQ This bit must be set to 1 when the e.MMC is in Interrupt mode (CMD40). Refer to "Interrupt Mode" in the "Embedded MultiMedia Card (e.MMC) Electrical Standard 4.51" . 1 STREAM This bit must be set to 1 in the case of Stream Read(CMD11) or Stream Write (CMD20). Only effective for e.MMC up to revision 4.41. 2 BOOT Starts a Boot Operation mode at the next write to SDMMC_CR. Boot data are read directly from e.MMC device. 3 DDR e.MMC HSDDR Mode [3:3] read-write OPD e.MMC Open Drain Mode [4:4] read-write BOOTA e.MMC Boot Acknowledge Enable [5:5] read-write RSTN e.MMC Reset Signal [6:6] read-write FCD e.MMC Force Card Detect [7:7] read-write MC2R e.MMC Control 2 Register 0x205 0x8 write-only SRESP e.MMC Abort Wait IRQ [0:0] read-write ABOOT e.MMC Abort Boot [1:1] read-write MCCAR Maximum Current Capabilities Register 0x48 0x20 read-write MAXCUR33V Maximum Current for 3.3V [7:0] read-write 0 255 MAXCUR30V Maximum Current for 3.0V [15:8] read-write 0 255 MAXCUR18V Maximum Current for 1.8V [23:16] read-write 0 255 NISIER Normal Interrupt Signal Enable Register 0x38 0x10 read-write CMDC Command Complete Signal Enable [0:0] read-write true MASKED No interrupt is generated when the CMDC status rises in SDMMC_NISTR. 0 ENABLED An interrupt is generated when the CMDC status rises in SDMMC_NISTR. 1 TRFC Transfer Complete Signal Enable [1:1] read-write true MASKED No interrupt is generated when the TRFC status rises in SDMMC_NISTR. 0 ENABLED An interrupt is generated when the TRFC status rises in SDMMC_NISTR. 1 BLKGE Block Gap Event Signal Enable [2:2] read-write true MASKED No interrupt is generated when the BLKGE status rises in SDMMC_NISTR. 0 ENABLED An interrupt is generated when the BLKGE status rises in SDMMC_NISTR. 1 DMAINT DMA Interrupt Signal Enable [3:3] read-write true MASKED No interrupt is generated when the DMAINT status rises in SDMMC_NISTR. 0 ENABLED An interrupt is generated when the DMAINT status rises in SDMMC_NISTR. 1 BWRRDY Buffer Write Ready Signal Enable [4:4] read-write true MASKED No interrupt is generated when the BWRRDY status rises in SDMMC_NISTR. 0 ENABLED An interrupt is generated when the BWRRDY status rises in SDMMC_NISTR. 1 BRDRDY Buffer Read Ready Signal Enable [5:5] read-write true MASKED No interrupt is generated when the BRDRDY status rises in SDMMC_NISTR. 0 ENABLED An interrupt is generated when the BRDRDY status rises in SDMMC_NISTR. 1 CINS Card Insertion Signal Enable [6:6] read-write true MASKED No interrupt is generated when the CINS status rises in SDMMC_NISTR. 0 ENABLED An interrupt is generated when the CINS status rises in SDMMC_NISTR. 1 CREM Card Removal Signal Enable [7:7] read-write true MASKED No interrupt is generated when the CREM status rises in SDMMC_NISTR. 0 ENABLED An interrupt is generated when the CREM status rises in SDMMC_NISTR. 1 CINT Card Interrupt Signal Enable [8:8] read-write true MASKED No interrupt is generated when the CINT status rises in SDMMC_NISTR. 0 ENABLED An interrupt is generated when the CINT status rises in SDMMC_NISTR. 1 BOOTAR Boot Acknowledge Received Signal Enable [14:14] read-write true MASKED No interrupt is generated when the BOOTAR status rises in SDMMC_NISTR. 0 ENABLED An interrupt is generated when the BOOTAR status rises in SDMMC_NISTR. 1 NISTER Normal Interrupt Status Enable Register 0x34 0x10 read-write CMDC Command Complete Status Enable [0:0] read-write true MASKED The CMDC status flag in SDMMC_NISTR is masked. 0 ENABLED The CMDC status flag in SDMMC_NISTR is enabled. 1 TRFC Transfer Complete Status Enable [1:1] read-write true MASKED The TRFC status flag in SDMMC_NISTR is masked. 0 ENABLED The TRFC status flag in SDMMC_NISTR is enabled. 1 BLKGE Block Gap Event Status Enable [2:2] read-write true MASKED The BLKGE status flag in SDMMC_NISTR is masked. 0 ENABLED The BLKGE status flag in SDMMC_NISTR is enabled. 1 DMAINT DMA Interrupt Status Enable [3:3] read-write true MASKED The DMAINT status flag in SDMMC_NISTR is masked. 0 ENABLED The DMAINT status flag in SDMMC_NISTR is enabled. 1 BWRRDY Buffer Write Ready Status Enable [4:4] read-write true MASKED The BWRRDY status flag in SDMMC_NISTR is masked. 0 ENABLED The BWRRDY status flag in SDMMC_NISTR is enabled. 1 BRDRDY Buffer Read Ready Status Enable [5:5] read-write true MASKED The BRDRDY status flag in SDMMC_NISTR is masked. 0 ENABLED The BRDRDY status flag in SDMMC_NISTR is enabled. 1 CINS Card Insertion Status Enable [6:6] read-write true MASKED The CINS status flag in SDMMC_NISTR is masked. 0 ENABLED The CINS status flag in SDMMC_NISTR is enabled. 1 CREM Card Removal Status Enable [7:7] read-write true MASKED The CREM status flag in SDMMC_NISTR is masked. 0 ENABLED The CREM status flag in SDMMC_NISTR is enabled. 1 CINT Card Interrupt Status Enable [8:8] read-write true MASKED The CINT status flag in SDMMC_NISTR is masked. 0 ENABLED The CINT status flag in SDMMC_NISTR is enabled. 1 BOOTAR Boot Acknowledge Received Status Enable [14:14] read-write true MASKED The BOOTAR status flag in SDMMC_NISTR is masked. 0 ENABLED The BOOTAR status flag in SDMMC_NISTR is enabled. 1 NISTR Normal Interrupt Status Register 0x30 0x10 read-write CMDC Command Complete [0:0] read-write TRFC Transfer Complete [1:1] read-write BLKGE Block Gap Event [2:2] read-write DMAINT DMA Interrupt [3:3] read-write BWRRDY Buffer Write Ready [4:4] read-write BRDRDY Buffer Read Ready [5:5] read-write CINS Card Insertion [6:6] read-write CREM Card Removal [7:7] read-write CINT Card Interrupt [8:8] read-write BOOTAR Boot Acknowledge Received [14:14] read-write ERRINT Error Interrupt [15:15] read-write PCR Power Control Register 0x29 0x8 read-write SDBPWR SD Bus Power [0:0] read-write PSR Present State Register 0x24 0x20 read-only CMDINHC Command Inhibit (CMD) [0:0] read-write CMDINHD Command Inhibit (DAT) [1:1] read-write DLACT DAT Line Active [2:2] read-write WTACT Write Transfer Active [8:8] read-write RTACT Read Transfer Active [9:9] read-write BUFWREN Buffer Write Enable [10:10] read-write BUFRDEN Buffer Read Enable [11:11] read-write CARDINS Card Inserted [16:16] read-write CARDSS Card State Stable [17:17] read-write CARDDPL Card Detect Pin Level [18:18] read-write WRPPL Write Protect Pin Level [19:19] read-write DATLL DAT[3:0] Line Level [23:20] read-write 0 15 CMDLL CMD Line Level [24:24] read-write PVR Preset Value Register 0 (for initialization) 0x60 0x10 read-write SDCLKFSEL SDCLK Frequency Select [9:0] read-write 0 1023 CLKGSEL Clock Generator Select [10:10] read-write DRVSEL Driver Strength Select [15:14] read-write 0 3 RR Response Register 0x10 0x20 read-only CMDRESP Command Response [31:0] read-write 0 4294967295 RTC1R Retuning Timer Control 1 Register 0x210 0x8 read-write TMREN Retuning Timer Enable [0:0] read-write true DISABLED The retuning timer is disabled. 0 ENABLED The retuning timer is enabled. 1 RTC2R Retuning Timer Control 2 Register 0x211 0x8 write-only RLD Retuning Timer Reload [0:0] read-write RTCVR Retuning Timer Counter Value Register 0x214 0x20 read-write TCVAL Retuning Timer Counter Value [3:0] read-write 0 15 RTISIER Retuning Timer Interrupt Signal Enable Register 0x219 0x8 read-write TEVT Retuning Timer Event [0:0] read-write true MASKED No interrupt is generated when the TEVT status rises in SDMMC_RTISTR. 0 ENABLED An interrupt is generated when the TEVT status rises in SDMMC_RTISTR. 1 RTISTER Retuning Timer Interrupt Status Enable Register 0x218 0x8 read-write TEVT Retuning Timer Event [0:0] read-write true MASKED The TEVT status flag in SDMMC_RTISTR is masked. 0 ENABLED The TEVT status flag in SDMMC_RTISTR is enabled. 1 RTISTR Retuning Timer Interrupt Status Register 0x21C 0x8 read-write TEVT Retuning Timer Event [0:0] read-write RTSSR Retuning Timer Status Slots Register 0x21D 0x8 read-only TEVTSLOT Retuning Timer Event Slots [1:0] read-write 0 3 SISR Slot Interrupt Status Register 0xFC 0x10 read-only INTSSL Interrupt Signal for Each Slot [1:0] read-write 0 3 SRR Software Reset Register 0x2F 0x8 read-write SWRSTALL Software reset for All [0:0] read-write SWRSTCMD Software reset for CMD line [1:1] read-write SWRSTDAT Software reset for DAT line [2:2] read-write SSAR SDMA System Address / Argument 2 Register 0x0 0x20 read-write ADDR SDMA System Address [31:0] read-write 0 4294967295 ARG2 Argument 2 [31:0] read-write 0 4294967295 TCR Timeout Control Register 0x2E 0x8 read-write DTCVAL Data Timeout Counter Value [3:0] read-write 0 15 TMR Transfer Mode Register 0xC 0x10 read-write DMAEN DMA Enable [0:0] read-write true DISABLED DMA functionality is disabled. 0 ENABLED DMA functionality is enabled. 1 BCEN Block Count Enable [1:1] read-write true DISABLED Block count is disabled. 0 ENABLED Block count is enabled. 1 ACMDEN Auto Command Enable [3:2] read-write true DISABLED Auto Command Disabled 0 CMD12 Auto CMD12 Enabled 1 CMD23 Auto CMD23 Enabled 2 DTDSEL Data Transfer Direction Selection [4:4] read-write true WRITE Writes data from the SDMMC to the device. 0 READ Reads data from the device to the SDMMC. 1 MSBSEL Multi/Single Block Selection [5:5] read-write TUNCR Tuning Control Register 0x220 0x20 read-write SMPLPT Sampling Point [0:0] read-write WCR Wakeup Control Register 0x2B 0x8 read-write WKENCINT Wakeup Event Enable on Card Interrupt [0:0] read-write true DISABLED Wakeup Event disabled. 0 ENABLED Wakeup Event enabled. 1 WKENCINS Wakeup Event Enable on Card Insertion [1:1] read-write true DISABLED Wakeup Event disabled. 0 ENABLED Wakeup Event enabled. 1 WKENCREM Wakeup Event Enable on Card Removal [2:2] read-write true DISABLED Wakeup Event disabled. 0 ENABLED Wakeup Event enabled. 1 SDMMC1 Secure Digital MultiMedia Card Controller 0xB0000000 SECUMOD Security Module 0xFC040000 0x0 0xC registers 0x10 0xC registers 0x68 0x4 registers 0x70 0x24 registers BMPR Backup Mode Protection Register 0x7C 0x20 read-write DET0 PIOBU Intrusion Detector Protection [16:16] read-write DET1 PIOBU Intrusion Detector Protection [17:17] read-write DET2 PIOBU Intrusion Detector Protection [18:18] read-write DET3 PIOBU Intrusion Detector Protection [19:19] read-write DET4 PIOBU Intrusion Detector Protection [20:20] read-write DET5 PIOBU Intrusion Detector Protection [21:21] read-write DET6 PIOBU Intrusion Detector Protection [22:22] read-write DET7 PIOBU Intrusion Detector Protection [23:23] read-write CR Control Register 0x0 0x20 write-only BACKUP Backup Mode [0:0] read-write NORMAL Normal Mode [1:1] read-write SWPROT Software Protection [2:2] read-write SCRAMB Memory Scrambling Enable [10:9] read-write 0 3 KEY Password [31:16] read-write 0 65535 JTAGCR JTAG Protection Control Register 0x68 0x20 read-write FNTRST Force NTRST [0:0] read-write CA5_DEBUG_MODE Cortex-A5 Invasive/Non-Invasive Secure/Non-Secure Debug Permissions [3:1] read-write 0 7 WZO Write ZERO [4:4] read-write NIDPR Normal Interrupt Disable Protection Register 0x88 0x20 write-only DET0 PIOBU Intrusion Detector Protection Interrupt Disable [16:16] read-write DET1 PIOBU Intrusion Detector Protection Interrupt Disable [17:17] read-write DET2 PIOBU Intrusion Detector Protection Interrupt Disable [18:18] read-write DET3 PIOBU Intrusion Detector Protection Interrupt Disable [19:19] read-write DET4 PIOBU Intrusion Detector Protection Interrupt Disable [20:20] read-write DET5 PIOBU Intrusion Detector Protection Interrupt Disable [21:21] read-write DET6 PIOBU Intrusion Detector Protection Interrupt Disable [22:22] read-write DET7 PIOBU Intrusion Detector Protection Interrupt Disable [23:23] read-write NIEPR Normal Interrupt Enable Protection Register 0x84 0x20 write-only DET0 PIOBU Intrusion Detector Protection Interrupt Enable [16:16] read-write DET1 PIOBU Intrusion Detector Protection Interrupt Enable [17:17] read-write DET2 PIOBU Intrusion Detector Protection Interrupt Enable [18:18] read-write DET3 PIOBU Intrusion Detector Protection Interrupt Enable [19:19] read-write DET4 PIOBU Intrusion Detector Protection Interrupt Enable [20:20] read-write DET5 PIOBU Intrusion Detector Protection Interrupt Enable [21:21] read-write DET6 PIOBU Intrusion Detector Protection Interrupt Enable [22:22] read-write DET7 PIOBU Intrusion Detector Protection Interrupt Enable [23:23] read-write NIMPR Normal Interrupt Mask Protection Register 0x8C 0x20 read-only DET0 PIOBU Intrusion Detector Protection Interrupt Mask [16:16] read-write DET1 PIOBU Intrusion Detector Protection Interrupt Mask [17:17] read-write DET2 PIOBU Intrusion Detector Protection Interrupt Mask [18:18] read-write DET3 PIOBU Intrusion Detector Protection Interrupt Mask [19:19] read-write DET4 PIOBU Intrusion Detector Protection Interrupt Mask [20:20] read-write DET5 PIOBU Intrusion Detector Protection Interrupt Mask [21:21] read-write DET6 PIOBU Intrusion Detector Protection Interrupt Mask [22:22] read-write DET7 PIOBU Intrusion Detector Protection Interrupt Mask [23:23] read-write NMPR Normal Mode Protection Register 0x80 0x20 read-write DET0 PIOBU Intrusion Detector Protection [16:16] read-write DET1 PIOBU Intrusion Detector Protection [17:17] read-write DET2 PIOBU Intrusion Detector Protection [18:18] read-write DET3 PIOBU Intrusion Detector Protection [19:19] read-write DET4 PIOBU Intrusion Detector Protection [20:20] read-write DET5 PIOBU Intrusion Detector Protection [21:21] read-write DET6 PIOBU Intrusion Detector Protection [22:22] read-write DET7 PIOBU Intrusion Detector Protection [23:23] read-write PIOBU PIO Backup Register 0x18 0x20 read-write PIOBU_AFV PIOBU Alarm Filter Value [3:0] read-write 0 15 PIOBU_RFV PIOBUx Reset Filter Value [7:4] read-write 0 15 OUTPUT Configure I/O Line in Input/Output [8:8] read-write PIO_SOD Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1) [9:9] read-write PIO_PDS Level on the Pin in Input Mode (OUTPUT = 0) (Read-only) [10:10] read-write PULLUP Programmable Pull-up State [13:12] read-write 0 3 SCHEDULE Pull-up/Down Scheduled [14:14] read-write SWITCH Switch State for Intrusion Detection [15:15] read-write RAMACC RAM Access Rights Register 0x74 0x20 read-write RW0 Access right for RAM region [0; 1 Kbyte] [1:0] read-write 0 3 RW1 Access right for RAM region [1 Kbyte; 2 Kbytes] [3:2] read-write 0 3 RW2 Access right for RAM region [2 Kbytes; 3 Kbytes] [5:4] read-write 0 3 RW3 Access right for RAM region [3 Kbytes; 4 Kbytes] [7:6] read-write 0 3 RW4 Access right for RAM region [4 Kbytes; 5 Kbytes] [9:8] read-write 0 3 RW5 Access right for RAM region [5 Kbytes; 6 Kbytes] (register bank BUREG256b) [11:10] read-write 0 3 RAMACCSR RAM Access Rights Status Register 0x78 0x20 read-write RW0 Access right status for RAM region [0; 1 Kbyte] [1:0] read-write 0 3 RW1 Access right status for RAM region [1 Kbytes; 2 Kbytes] [3:2] read-write 0 3 RW2 Access right status for RAM region [2 Kbytes; 3 Kbytes] [5:4] read-write 0 3 RW3 Access right status for RAM region [3 Kbytes; 4 Kbytes] [7:6] read-write 0 3 RW4 Access right status for RAM region [4 Kbytes; 5 Kbytes] [9:8] read-write 0 3 RW5 Access right status for RAM region [5 Kbytes; 6 Kbytes] (register bank BUREG256b) [11:10] read-write 0 3 RAMRDY RAM Access Ready Register 0x14 0x20 read-only READY Ready for system access flag [0:0] read-write SCR Status Clear Register 0x10 0x20 write-only DET0 PIOBU Intrusion Detector [16:16] read-write DET1 PIOBU Intrusion Detector [17:17] read-write DET2 PIOBU Intrusion Detector [18:18] read-write DET3 PIOBU Intrusion Detector [19:19] read-write DET4 PIOBU Intrusion Detector [20:20] read-write DET5 PIOBU Intrusion Detector [21:21] read-write DET6 PIOBU Intrusion Detector [22:22] read-write DET7 PIOBU Intrusion Detector [23:23] read-write SCRKEY Scrambling Key Register 0x70 0x20 read-write SCRKEY Scrambling Key Value [31:0] read-write 0 4294967295 SR Status Register 0x8 0x20 read-only DET0 PIOBU Intrusion Detector [16:16] read-write DET1 PIOBU Intrusion Detector [17:17] read-write DET2 PIOBU Intrusion Detector [18:18] read-write DET3 PIOBU Intrusion Detector [19:19] read-write DET4 PIOBU Intrusion Detector [20:20] read-write DET5 PIOBU Intrusion Detector [21:21] read-write DET6 PIOBU Intrusion Detector [22:22] read-write DET7 PIOBU Intrusion Detector [23:23] read-write SYSR System Status Register 0x4 0x20 read-write ERASE_DONE Erasable Memories State (RW) [0:0] read-write ERASE_ON Erase Process Ongoing (RO) [1:1] read-write BACKUP Backup Mode (RO) [2:2] read-write SWKUP SWKUP State (RO) [3:3] read-write AUTOBKP Automatic Backup Mode Enabled (RO) [6:6] read-write SCRAMB Scrambling Enabled (RO) [7:7] read-write WKPR Wakeup Protection Register 0x90 0x20 read-write DET0 PIOBU Intrusion Detector Protection [16:16] read-write DET1 PIOBU Intrusion Detector Protection [17:17] read-write DET2 PIOBU Intrusion Detector Protection [18:18] read-write DET3 PIOBU Intrusion Detector Protection [19:19] read-write DET4 PIOBU Intrusion Detector Protection [20:20] read-write DET5 PIOBU Intrusion Detector Protection [21:21] read-write DET6 PIOBU Intrusion Detector Protection [22:22] read-write DET7 PIOBU Intrusion Detector Protection [23:23] read-write SFC Secure Fuse Controller 0xF804C000 0x0 0x8 registers 0x10 0x14 registers DR SFC Data Register 0x20 0x20 read-write DATA Fuse Data [31:0] read-write 0 4294967295 IDR SFC Interrupt Disable Register 0x14 0x20 write-only PGMC Programming Sequence Completed Interrupt Disable [0:0] read-write PGMF Programming Sequence Failed Interrupt Disable [1:1] read-write LCHECK Live Integrity Check Error Interrupt Disable [4:4] read-write ACE Area Check Error Interrupt Disable [17:17] read-write IER SFC Interrupt Enable Register 0x10 0x20 write-only PGMC Programming Sequence Completed Interrupt Enable [0:0] read-write PGMF Programming Sequence Failed Interrupt Enable [1:1] read-write LCHECK Live Integrity Check Error Interrupt Enable [4:4] read-write ACE Area Check Error Interrupt Enable [17:17] read-write IMR SFC Interrupt Mask Register 0x18 0x20 read-only PGMC Programming Sequence Completed Interrupt Mask [0:0] read-write PGMF Programming Sequence Failed Interrupt Mask [1:1] read-write LCHECK Live Integrity Checking Error Interrupt Mask [4:4] read-write ACE Area Check Error Interrupt Mask [17:17] read-write KR SFC Key Register 0x0 0x20 write-only KEY Key Code [7:0] read-write 0 255 MR SFC Mode Register 0x4 0x20 read-write MSK Mask Data Registers [0:0] read-write SASEL Sense Amplifier Selection [4:4] read-write SR SFC Status Register 0x1C 0x20 read-only PGMC Programming Sequence Completed (cleared on read) [0:0] read-write PGMF Programming Sequence Failed (cleared on read) [1:1] read-write LCHECK Live Integrity Checking Error (cleared on read) [4:4] read-write APLE Area Programming Lock Error (cleared on read) [16:16] read-write ACE Area Check Error (cleared on read) [17:17] read-write SFR Special Function Registers 0xF8030004 0x0 0x4 registers 0xC 0x8 registers 0x24 0x4 registers 0x2C 0x10 registers 0x44 0x14 registers 0x8C 0x8 registers QSPICLK_REG QSPI Clock Pad Supply Select Register 0x90 0x20 read-write SUP_SEL Supply Selection [0:0] read-write SFR_AICREDIR AIC Interrupt Redirection Register 0x50 0x20 read-write NSAIC Interrupt Redirection to Non-Secure AIC [0:0] read-write AICREDIRKEY Unlock Key [31:1] read-write 0 2147483647 SFR_CAN CAN Memories Address-based Register 0x44 0x20 read-write EXT_MEM_CAN0_ADDR MSB CAN0 DMA Base Address [15:0] read-write 0 65535 EXT_MEM_CAN1_ADDR MSB CAN1 DMA Base Address [31:16] read-write 0 65535 SFR_DDRCFG DDR Configuration Register 0x0 0x20 read-write FDQIEN Force DDR_DQ Input Buffer Always On [16:16] read-write FDQSIEN Force DDR_DQS Input Buffer Always On [17:17] read-write SFR_I2SCLKSEL I2SC Register 0x8C 0x20 read-write CLKSEL0 Clock Selection 0 [0:0] read-write CLKSEL1 Clock Selection 1 [1:1] read-write SFR_L2CC_HRAMC L2CC_HRAMC1 0x54 0x20 read-write SRAM_SEL SRAM Selector [0:0] read-write SFR_OHCIICR OHCI Interrupt Configuration Register 0xC 0x20 read-write RES0 USB PORTx RESET [0:0] read-write RES1 USB PORTx RESET [1:1] read-write RES2 USB PORTx RESET [2:2] read-write ARIE OHCI Asynchronous Resume Interrupt Enable [4:4] read-write APPSTART Reserved [5:5] read-write SUSPEND_A USB PORT A [8:8] read-write SUSPEND_B USB PORT B [9:9] read-write SUSPEND_C USB PORT C [10:10] read-write UDPPUDIS USB DEVICE PULLUP DISABLE [23:23] read-write HSIC_SEL Reserved [27:27] read-write SFR_OHCIISR OHCI Interrupt Status Register 0x10 0x20 read-only RIS0 OHCI Resume Interrupt Status Port 0 [0:0] read-write RIS1 OHCI Resume Interrupt Status Port 1 [1:1] read-write RIS2 OHCI Resume Interrupt Status Port 2 [2:2] read-write SFR_SECURE Security Configuration Register 0x24 0x20 read-write ROM Disable Access to ROM Code [0:0] read-write FUSE Disable Access to Fuse Controller [8:8] read-write SFR_SN0 Serial Number 0 Register 0x48 0x20 read-only SN0 Serial Number 0 [31:0] read-write 0 4294967295 SFR_SN1 Serial Number 1 Register 0x4C 0x20 read-only SN1 Serial Number 1 [31:0] read-write 0 4294967295 SFR_UTMICKTRIM UTMI Clock Trimming Register 0x2C 0x20 read-write FREQ UTMI Reference Clock Frequency [1:0] read-write true _12 12 MHz reference clock 0 _16 16 MHz reference clock 1 _24 24 MHz reference clock 2 VBG UTMI Band Gap Voltage Trimming [17:16] read-write 0 3 SFR_UTMIFSTRIM UTMI Full-Speed Trimming Register 0x34 0x20 read-write RISE FS Transceiver Output Rising Slope Trimming [2:0] read-write 0 7 FALL FS Transceiver Output Falling Slope Trimming [6:4] read-write 0 7 XCVR FS Transceiver Crossover Voltage Trimming [9:8] read-write 0 3 ZN FS Transceiver NMOS Impedance Trimming [18:16] read-write 0 7 ZP FS Transceiver PMOS Impedance Trimming [22:20] read-write 0 7 SFR_UTMIHSTRIM UTMI High-Speed Trimming Register 0x30 0x20 read-write SQUELCH UTMI HS SQUELCH Voltage Trimming [2:0] read-write 0 7 DISC UTMI Disconnect Voltage Trimming [6:4] read-write 0 7 SLOPE0 UTMI HS PORTx Transceiver Slope Trimming [10:8] read-write 0 7 SLOPE1 UTMI HS PORTx Transceiver Slope Trimming [14:12] read-write 0 7 SLOPE2 UTMI HS PORTx Transceiver Slope Trimming [18:16] read-write 0 7 SFR_UTMISWAP UTMI DP/DM Pin Swapping Register 0x38 0x20 read-write PORT0 PORT 0 DP/DM Pin Swapping [0:0] read-write true NORMAL DP/DM normal pinout. 0 SWAPPED DP/DM swapped pinout. 1 PORT1 PORT 1 DP/DM Pin Swapping [1:1] read-write true NORMAL DP/DM normal pinout. 0 SWAPPED DP/DM swapped pinout. 1 PORT2 PORT 2 DP/DM Pin Swapping [2:2] read-write true NORMAL DP/DM normal pinout. 0 SWAPPED DP/DM swapped pinout. 1 SFRBU Special Function Registers Backup 0xFC05C000 0x0 0x8 registers 0x10 0x8 registers DDRBUMCR DDR BU Mode Control Register 0x10 0x20 read-write BUMEN DDR BU Mode Enable [0:0] read-write PSWBUCTRL Power Switch BU Control Register 0x0 0x20 read-write SCTRL Power Switch BU Software Control [0:0] read-write SSWCTRL Power Switch BU Source Selection [1:1] read-write SMCTRL Allow Power Switch BU Control by Security Module Autobackup (Hardware) [2:2] read-write STATE Power Switch BU state (Read-only) [3:3] read-write KEYPSWMODE No Description. [31:8] read-write 0 16777215 RXLPPUCR RXLP Pull-Up Control Register 0x14 0x20 read-write RXDPUCTRL RXLP RXD Pull-Up Control [0:0] read-write TSRANGECFG TS Range Configuration Register 0x4 0x20 read-write TSHRSEL Temperature Sensor Range Selection [0:0] read-write SHA Secure Hash Algorithm 0xF0028000 0x0 0x8 registers 0x10 0x14 registers 0x30 0x4 registers 0x40 0x4 registers 0x80 0x4 registers BCR Bytes Count Register 0x30 0x20 read-write BYTCNT Remaining Byte Count Before Auto Padding [31:0] read-write 0 4294967295 CR Control Register 0x0 0x20 write-only START Start Processing [0:0] read-write FIRST First Block of a Message [4:4] read-write SWRST Software Reset [8:8] read-write WUIHV Write User Initial Hash Values [12:12] read-write WUIEHV Write User Initial or Expected Hash Values [13:13] read-write IDATAR Input Data 0 Register 0x40 0x20 write-only IDATA Input Data [31:0] read-write 0 4294967295 IDR Interrupt Disable Register 0x14 0x20 write-only DATRDY Data Ready Interrupt Disable [0:0] read-write URAD Unspecified Register Access Detection Interrupt Disable [8:8] read-write CHECKF Check Done Interrupt Disable [16:16] read-write IER Interrupt Enable Register 0x10 0x20 write-only DATRDY Data Ready Interrupt Enable [0:0] read-write URAD Unspecified Register Access Detection Interrupt Enable [8:8] read-write CHECKF Check Done Interrupt Enable [16:16] read-write IMR Interrupt Mask Register 0x18 0x20 read-only DATRDY Data Ready Interrupt Mask [0:0] read-write URAD Unspecified Register Access Detection Interrupt Mask [8:8] read-write CHECKF Check Done Interrupt Mask [16:16] read-write IODATAR Input/Output Data 0 Register 0x80 0x20 read-write IODATA Input/Output Data [31:0] read-write 0 4294967295 ISR Interrupt Status Register 0x1C 0x20 read-only DATRDY Data Ready (cleared by writing a 1 to bit SWRST or START in SHA_CR, or by reading SHA_IODATARx) [0:0] read-write WRDY Input Data Register Write Ready [4:4] read-write URAD Unspecified Register Access Detection Status (cleared by writing a 1 to SWRST bit in SHA_CR) [8:8] read-write URAT Unspecified Register Access Type (cleared by writing a 1 to SWRST bit in SHA_CR) [14:12] read-write 0 7 CHECKF Check Done Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx) [16:16] read-write CHKST Check Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx) [23:20] read-write 0 15 MR Mode Register 0x4 0x20 read-write SMOD Start Mode [1:0] read-write true MANUAL_START Manual mode 0 AUTO_START Auto mode 1 IDATAR0_START SHA_IDATAR0 access only mode (mandatory when DMA is used) 2 PROCDLY Processing Delay [4:4] read-write true SHORTEST SHA processing runtime is the shortest one 0 LONGEST SHA processing runtime is the longest one (reduces the SHA bandwidth requirement, reduces the system bus overload) 1 UIHV User Initial Hash Value Registers [5:5] read-write UIEHV User Initial or Expected Hash Value Registers [6:6] read-write ALGO SHA Algorithm [11:8] read-write true SHA1 SHA1 algorithm processed 0 SHA256 SHA256 algorithm processed 1 SHA384 SHA384 algorithm processed 2 SHA512 SHA512 algorithm processed 3 SHA224 SHA224 algorithm processed 4 HMAC_SHA1 HMAC algorithm with SHA1 Hash processed 8 HMAC_SHA256 HMAC algorithm with SHA256 Hash processed 9 HMAC_SHA384 HMAC algorithm with SHA384 Hash processed 10 HMAC_SHA512 HMAC algorithm with SHA512 Hash processed 11 HMAC_SHA224 HMAC algorithm with SHA224 Hash processed 12 DUALBUFF Dual Input Buffer [16:16] read-write true INACTIVE SHA_IDATARx and SHA_IODATARx cannot be written during processing of previous block. 0 ACTIVE SHA_IDATARx and SHA_IODATARx can be written during processing of previous block when SMOD value = 2. It speeds up the overall runtime of large files. 1 CHECK Hash Check [25:24] read-write true NO_CHECK No check is performed 0 CHECK_EHV Check is performed with expected hash stored in internal expected hash value registers. 1 CHECK_MESSAGE Check is performed with expected hash provided after the message. 2 CHKCNT Check Counter [31:28] read-write 0 15 MSR Message Size Register 0x20 0x20 read-write MSGSIZE Message Size [31:0] read-write 0 4294967295 SHDWC Shutdown Controller 0xF8048010 0x0 0x10 registers CR Shutdown Control Register 0x0 0x20 write-only SHDW Shutdown Command [0:0] read-write KEY Password [31:24] read-write true PASSWD Writing any other value in this field aborts the write operation. 165 MR Shutdown Mode Register 0x4 0x20 read-write RTCWKEN Real-time Clock Wake-up Enable [17:17] read-write ACCWKEN Analog Comparator Controller Wake-up Enable [18:18] read-write RXLPWKEN Debug Unit Wake-up Enable [19:19] read-write WKUPDBC Wake-up Inputs Debouncer Period [26:24] read-write true IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge 0 _3_SLCK PIOBUx shall be in its active state for at least 3 SLCK periods 1 _32_SLCK PIOBUx shall be in its active state for at least 32 SLCK periods 2 _512_SLCK PIOBUx shall be in its active state for at least 512 SLCK periods 3 _4096_SLCK PIOBUx shall be in its active state for at least 4,096 SLCK periods 4 _32768_SLCK PIOBUx shall be in its active state for at least 32,768 SLCK periods 5 SR Shutdown Status Register 0x8 0x20 read-only WKUPS PIOBU, WKUP Wake-up Status [0:0] read-write true NO No wake-up due to the assertion of the PIOBU, WKUP pins has occurred since the last read of SHDW_SR. 0 PRESENT At least one wake-up due to the assertion of the PIOBU, WKUP pins has occurred since the last read of SHDW_SR. 1 RTCWK No Description. [5:5] read-write ACCWK Analog Comparator Controller Wake-up [6:6] read-write RXLPWK Debug Unit Wake-up [7:7] read-write WKUPIS0 Wake-up 0 Input Status [16:16] read-write true DISABLE The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 ENABLE The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS1 Wake-up 1 Input Status [17:17] read-write true DISABLE The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 ENABLE The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS2 Wake-up 2 Input Status [18:18] read-write true DISABLE The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 ENABLE The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS3 Wake-up 3 Input Status [19:19] read-write true DISABLE The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 ENABLE The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS4 Wake-up 4 Input Status [20:20] read-write true DISABLE The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 ENABLE The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS5 Wake-up 5 Input Status [21:21] read-write true DISABLE The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 ENABLE The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS6 Wake-up 6 Input Status [22:22] read-write true DISABLE The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 ENABLE The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS7 Wake-up 7 Input Status [23:23] read-write true DISABLE The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 ENABLE The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS8 Wake-up 8 Input Status [24:24] read-write true DISABLE The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 ENABLE The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WKUPIS9 Wake-up 9 Input Status [25:25] read-write true DISABLE The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 ENABLE The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. 1 WUIR Shutdown Wake-up Inputs Register 0xC 0x20 read-write WKUPEN0 Wake-up 0 Input Enable [0:0] read-write true DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN1 Wake-up 1 Input Enable [1:1] read-write true DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN2 Wake-up 2 Input Enable [2:2] read-write true DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN3 Wake-up 3 Input Enable [3:3] read-write true DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN4 Wake-up 4 Input Enable [4:4] read-write true DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN5 Wake-up 5 Input Enable [5:5] read-write true DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN6 Wake-up 6 Input Enable [6:6] read-write true DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN7 Wake-up 7 Input Enable [7:7] read-write true DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN8 Wake-up 8 Input Enable [8:8] read-write true DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPEN9 Wake-up 9 Input Enable [9:9] read-write true DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPT0 Wake-up 0 Input Type [16:16] read-write true LOW A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPT1 Wake-up 1 Input Type [17:17] read-write true LOW A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPT2 Wake-up 2 Input Type [18:18] read-write true LOW A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPT3 Wake-up 3 Input Type [19:19] read-write true LOW A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPT4 Wake-up 4 Input Type [20:20] read-write true LOW A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPT5 Wake-up 5 Input Type [21:21] read-write true LOW A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPT6 Wake-up 6 Input Type [22:22] read-write true LOW A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPT7 Wake-up 7 Input Type [23:23] read-write true LOW A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPT8 Wake-up 8 Input Type [24:24] read-write true LOW A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 1 WKUPT9 Wake-up 9 Input Type [25:25] read-write true LOW A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. 1 SMC Static Memory Controller 0xF8014000 0x0 0x20 registers 0x70 0x10 registers 0x84 0x18 registers 0x500 0x24 registers 0x528 0x88 registers 0x7A0 0xC registers 0x7E4 0x8 registers ADDR NFC Address Cycle Zero Register 0x18 0x20 read-write ADDR_CYCLE0 NAND Flash Array Address Cycle 0 [7:0] read-write 0 255 BANK Bank Address Register 0x1C 0x20 read-write BANK Bank Identifier [0:0] read-write CFG NFC Configuration Register 0x0 0x20 read-write PAGESIZE Page Size of the NAND Flash Device [2:0] read-write true PS512 Main area 512 bytes 0 PS1024 Main area 1024 bytes 1 PS2048 Main area 2048 bytes 2 PS4096 Main area 4096 bytes 3 PS8192 Main area 8192 bytes 4 WSPARE Write Spare Area [8:8] read-write RSPARE Read Spare Area [9:9] read-write EDGECTRL Rising/Falling Edge Detection Control [12:12] read-write RBEDGE Ready/Busy Signal Edge Detection [13:13] read-write DTOCYC Data Timeout Cycle Number [19:16] read-write 0 15 DTOMUL Data Timeout Multiplier [22:20] read-write true X1 DTOCYC 0 X16 DTOCYC x 16 1 X128 DTOCYC x 128 2 X256 DTOCYC x 256 3 X1024 DTOCYC x 1024 4 X4096 DTOCYC x 4096 5 X65536 DTOCYC x 65536 6 X1048576 DTOCYC x 1048576 7 NFCSPARESIZE NAND Flash Spare Area Size Retrieved by the Host Controller [30:24] read-write 0 127 CTRL NFC Control Register 0x4 0x20 write-only NFCEN NAND Flash Controller Enable [0:0] read-write NFCDIS NAND Flash Controller Disable [1:1] read-write ELCFG PMECC Error Location Configuration Register 0x500 0x20 read-write SECTORSZ Sector Size [0:0] read-write true SECTORSZ0 Use 512 Byte Sector in Location Computation 0 SECTORSZ1 Use 1024 Byte Sector in Location Computation 1 ERRNUM Number of Errors [20:16] read-write 0 31 ELDIS PMECC Error Location Disable Register 0x50C 0x20 write-only DIS Disable Error Location Engine [0:0] read-write ELEN PMECC Error Location Enable Register 0x508 0x20 write-only ENINIT Error Location Enable [13:0] read-write 0 16383 ELIDR PMECC Error Location Interrupt Disable Register 0x518 0x20 write-only DONE Computation Terminated Interrupt Disable [0:0] read-write ELIER PMECC Error Location Interrupt Enable register 0x514 0x20 write-only DONE Computation Terminated Interrupt Enable [0:0] read-write ELIMR PMECC Error Location Interrupt Mask Register 0x51C 0x20 read-only DONE Computation Terminated Interrupt Mask [0:0] read-write ELISR PMECC Error Location Interrupt Status Register 0x520 0x20 read-only DONE Computation Terminated Interrupt Status [0:0] read-write ERR_CNT Error Counter value [13:8] read-write 0 63 ELPRIM PMECC Error Location Primitive Register 0x504 0x20 read-only PRIMITIV Primitive Polynomial [15:0] read-write 0 65535 ELSR PMECC Error Location Status Register 0x510 0x20 read-only BUSY Error Location Engine Busy [0:0] read-write ERRLOC PMECC Error Location 0 Register 0x5AC 0x20 read-only ERRLOCN Error Position within the Set {sector area, spare area} [13:0] read-write 0 16383 IDR NFC Interrupt Disable Register 0x10 0x20 write-only RB_RISE Ready Busy Rising Edge Detection Interrupt Disable [4:4] read-write RB_FALL Ready Busy Falling Edge Detection Interrupt Disable [5:5] read-write XFRDONE Transfer Done Interrupt Disable [16:16] read-write CMDDONE Command Done Interrupt Disable [17:17] read-write DTOE Data Timeout Error Interrupt Disable [20:20] read-write UNDEF Undefined Area Access Interrupt Disable [21:21] read-write AWB Accessing While Busy Interrupt Disable [22:22] read-write NFCASE NFC Access Size Error Interrupt Disable [23:23] read-write RB_EDGE0 Ready/Busy Line 0 Interrupt Disable [24:24] read-write IER NFC Interrupt Enable Register 0xC 0x20 write-only RB_RISE Ready Busy Rising Edge Detection Interrupt Enable [4:4] read-write RB_FALL Ready Busy Falling Edge Detection Interrupt Enable [5:5] read-write XFRDONE Transfer Done Interrupt Enable [16:16] read-write CMDDONE Command Done Interrupt Enable [17:17] read-write DTOE Data Timeout Error Interrupt Enable [20:20] read-write UNDEF Undefined Area Access Interrupt Enable [21:21] read-write AWB Accessing While Busy Interrupt Enable [22:22] read-write NFCASE NFC Access Size Error Interrupt Enable [23:23] read-write RB_EDGE0 Ready/Busy Line 0 Interrupt Enable [24:24] read-write IMR NFC Interrupt Mask Register 0x14 0x20 read-only RB_RISE Ready Busy Rising Edge Detection Interrupt Mask [4:4] read-write RB_FALL Ready Busy Falling Edge Detection Interrupt Mask [5:5] read-write XFRDONE Transfer Done Interrupt Mask [16:16] read-write CMDDONE Command Done Interrupt Mask [17:17] read-write DTOE Data Timeout Error Interrupt Mask [20:20] read-write UNDEF Undefined Area Access Interrupt Mask5 [21:21] read-write AWB Accessing While Busy Interrupt Mask [22:22] read-write NFCASE NFC Access Size Error Interrupt Mask [23:23] read-write RB_EDGE0 Ready/Busy Line 0 Interrupt Mask [24:24] read-write KEY1 Off Chip Memory Scrambling KEY1 Register 0x7A4 0x20 write-only KEY1 Off Chip Memory Scrambling (OCMS) Key Part 1 [31:0] read-write 0 4294967295 KEY2 Off Chip Memory Scrambling KEY2 Register 0x7A8 0x20 write-only KEY2 Off Chip Memory Scrambling (OCMS) Key Part 2 [31:0] read-write 0 4294967295 OCMS Off Chip Memory Scrambling Register 0x7A0 0x20 read-write SMSE Static Memory Controller Scrambling Enable [0:0] read-write SRSE NFC Internal SRAM Scrambling Enable [1:1] read-write PMECCEADDR PMECC End Address Register 0x7C 0x20 read-write ENDADDR ECC Area End Address [8:0] read-write 0 511 PMECCFG PMECC Configuration Register 0x70 0x20 read-write BCH_ERR Error Correcting Capability [2:0] read-write true BCH_ERR2 2 errors 0 BCH_ERR4 4 errors 1 BCH_ERR8 8 errors 2 BCH_ERR12 12 errors 3 BCH_ERR24 24 errors 4 BCH_ERR32 32 errors 5 SECTORSZ Sector Size [4:4] read-write true SECTORSZ0 Use 512 Byte Sector in ECC Computation 0 SECTORSZ1 Use 1024 Byte Sector in ECC Computation 1 PAGESIZE Number of Sectors in the Page [9:8] read-write true PAGESIZE_1SEC 1 sector for main area (512 or 1024 bytes) 0 PAGESIZE_2SEC 2 sectors for main area (1024 or 2048 bytes) 1 PAGESIZE_4SEC 4 sectors for main area (2048 or 4096 bytes) 2 PAGESIZE_8SEC 8 sectors for main area (4096 or 8192 bytes) 3 NANDWR NAND Write Access [12:12] read-write SPAREEN Spare Enable [16:16] read-write AUTO Automatic Mode Enable [20:20] read-write PMECCIDR PMECC Interrupt Disable Register 0x90 0x20 write-only ERRID Error Interrupt Disable [0:0] read-write PMECCIER PMECC Interrupt Enable register 0x8C 0x20 write-only ERRIE Error Interrupt Enable [0:0] read-write PMECCIMR PMECC Interrupt Mask Register 0x94 0x20 read-only ERRIM Error Interrupt Mask [0:0] read-write PMECCISR PMECC Interrupt Status Register 0x98 0x20 read-only ERRIS Error Interrupt Status Register [7:0] read-write 0 255 PMECCSADDR PMECC Start Address Register 0x78 0x20 read-write STARTADDR ECC Area Start Address [8:0] read-write 0 511 PMECCSAREA PMECC Spare Area Size Register 0x74 0x20 read-write SPARESIZE Spare Area Size [8:0] read-write 0 511 PMECCSR PMECC Status Register 0x88 0x20 read-only BUSY The kernel of the PMECC is busy [0:0] read-write ENABLE PMECC Enable bit [4:4] read-write PMECCTRL PMECC Control Register 0x84 0x20 write-only RST Reset the PMECC Module [0:0] read-write DATA Start a Data Phase [1:1] read-write USER Start a User Mode Phase [2:2] read-write ENABLE PMECC Enable [4:4] read-write DISABLE PMECC Enable [5:5] read-write SIGMA0 PMECC Error Location SIGMA 0 Register 0x528 0x20 read-only SIGMA0 Coefficient of degree 0 in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA1 PMECC Error Location SIGMA 1 Register 0x52C 0x20 read-write SIGMA1 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA10 PMECC Error Location SIGMA 10 Register 0x550 0x20 read-write SIGMA10 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA11 PMECC Error Location SIGMA 11 Register 0x554 0x20 read-write SIGMA11 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA12 PMECC Error Location SIGMA 12 Register 0x558 0x20 read-write SIGMA12 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA13 PMECC Error Location SIGMA 13 Register 0x55C 0x20 read-write SIGMA13 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA14 PMECC Error Location SIGMA 14 Register 0x560 0x20 read-write SIGMA14 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA15 PMECC Error Location SIGMA 15 Register 0x564 0x20 read-write SIGMA15 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA16 PMECC Error Location SIGMA 16 Register 0x568 0x20 read-write SIGMA16 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA17 PMECC Error Location SIGMA 17 Register 0x56C 0x20 read-write SIGMA17 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA18 PMECC Error Location SIGMA 18 Register 0x570 0x20 read-write SIGMA18 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA19 PMECC Error Location SIGMA 19 Register 0x574 0x20 read-write SIGMA19 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA2 PMECC Error Location SIGMA 2 Register 0x530 0x20 read-write SIGMA2 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA20 PMECC Error Location SIGMA 20 Register 0x578 0x20 read-write SIGMA20 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA21 PMECC Error Location SIGMA 21 Register 0x57C 0x20 read-write SIGMA21 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA22 PMECC Error Location SIGMA 22 Register 0x580 0x20 read-write SIGMA22 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA23 PMECC Error Location SIGMA 23 Register 0x584 0x20 read-write SIGMA23 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA24 PMECC Error Location SIGMA 24 Register 0x588 0x20 read-write SIGMA24 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA25 PMECC Error Location SIGMA 25 Register 0x58C 0x20 read-write SIGMA25 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA26 PMECC Error Location SIGMA 26 Register 0x590 0x20 read-write SIGMA26 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA27 PMECC Error Location SIGMA 27 Register 0x594 0x20 read-write SIGMA27 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA28 PMECC Error Location SIGMA 28 Register 0x598 0x20 read-write SIGMA28 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA29 PMECC Error Location SIGMA 29 Register 0x59C 0x20 read-write SIGMA29 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA3 PMECC Error Location SIGMA 3 Register 0x534 0x20 read-write SIGMA3 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA30 PMECC Error Location SIGMA 30 Register 0x5A0 0x20 read-write SIGMA30 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA31 PMECC Error Location SIGMA 31 Register 0x5A4 0x20 read-write SIGMA31 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA32 PMECC Error Location SIGMA 32 Register 0x5A8 0x20 read-write SIGMA32 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA4 PMECC Error Location SIGMA 4 Register 0x538 0x20 read-write SIGMA4 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA5 PMECC Error Location SIGMA 5 Register 0x53C 0x20 read-write SIGMA5 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA6 PMECC Error Location SIGMA 6 Register 0x540 0x20 read-write SIGMA6 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA7 PMECC Error Location SIGMA 7 Register 0x544 0x20 read-write SIGMA7 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA8 PMECC Error Location SIGMA 8 Register 0x548 0x20 read-write SIGMA8 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SIGMA9 PMECC Error Location SIGMA 9 Register 0x54C 0x20 read-write SIGMA9 Coefficient of degree x in the SIGMA polynomial [13:0] read-write 0 16383 SR NFC Status Register 0x8 0x20 read-only SMCSTS NAND Flash Controller Status (this field cannot be reset) [0:0] read-write RB_RISE Selected Ready Busy Rising Edge Detected [4:4] read-write RB_FALL Selected Ready Busy Falling Edge Detected [5:5] read-write NFCBUSY NFC Busy (this field cannot be reset) [8:8] read-write NFCWR NFC Write/Read Operation (this field cannot be reset) [11:11] read-write NFCSID NFC Chip Select ID (this field cannot be reset) [14:12] read-write 0 7 XFRDONE NFC Data Transfer Terminated [16:16] read-write CMDDONE Command Done [17:17] read-write DTOE Data Timeout Error [20:20] read-write UNDEF Undefined Area Error [21:21] read-write AWB Accessing While Busy [22:22] read-write NFCASE NFC Access Size Error [23:23] read-write RB_EDGE0 Ready/Busy Line 0 Edge Detected [24:24] read-write WPMR Write Protection Mode Register 0x7E4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. 5459267 WPSR Write Protection Status Register 0x7E8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [23:8] read-write 0 65535 SPI0 Serial Peripheral Interface 0xF8000000 0x0 0x20 registers 0x30 0x4 registers 0x40 0xC registers 0xE4 0x8 registers CMPR Comparison Register 0x48 0x20 read-only VAL1 First Comparison Value for Received Character [15:0] read-write 0 65535 VAL2 Second Comparison Value for Received Character [31:16] read-write 0 65535 CR Control Register 0x0 0x20 write-only SPIEN SPI Enable [0:0] read-write SPIDIS SPI Disable [1:1] read-write SWRST SPI Software Reset [7:7] read-write REQCLR Request to Clear the Comparison Trigger [12:12] read-write TXFCLR Transmit FIFO Clear [16:16] read-write RXFCLR Receive FIFO Clear [17:17] read-write LASTXFER Last Transfer [24:24] read-write FIFOEN FIFO Enable [30:30] read-write FIFODIS FIFO Disable [31:31] read-write CSR Chip Select Register 0x30 0x20 read-write CPOL Clock Polarity [0:0] read-write true IDLE_LOW Clock is low when inactive (CPOL=0) 0 IDLE_HIGH Clock is high when inactive (CPOL=1) 1 NCPHA Clock Phase [1:1] read-write true VALID_TRAILING_EDGE Data is valid on clock trailing edge (NCPHA=0) 0 VALID_LEADING_EDGE Data is valid on clock leading edge (NCPHA=1) 1 CSNAAT Chip Select Not Active After Transfer (ignored if CSAAT = 1) [2:2] read-write CSAAT Chip Select Active After Transfer [3:3] read-write BITS Bits Per Transfer [7:4] read-write true _8_BIT 8 bits for transfer 0 _9_BIT 9 bits for transfer 1 _10_BIT 10 bits for transfer 2 _11_BIT 11 bits for transfer 3 _12_BIT 12 bits for transfer 4 _13_BIT 13 bits for transfer 5 _14_BIT 14 bits for transfer 6 _15_BIT 15 bits for transfer 7 _16_BIT 16 bits for transfer 8 SCBR Serial Clock Bit Rate [15:8] read-write 0 255 DLYBS Delay Before SPCK [23:16] read-write 0 255 DLYBCT Delay Between Consecutive Transfers [31:24] read-write 0 255 FLR FIFO Level Register 0x44 0x20 read-only TXFL Transmit FIFO Level [5:0] read-write 0 63 RXFL Receive FIFO Level [21:16] read-write 0 63 FMR FIFO Mode Register 0x40 0x20 read-write TXRDYM Transmit Data Register Empty Mode [1:0] read-write true ONE_DATA TDRE will be at level '1' when at least one data can be written in the Transmit FIFO. 0 TWO_DATA TDRE will be at level '1' when at least two data can be written in the Transmit FIFO. Cannot be used if SPI_MR.PS =1. 1 RXRDYM Receive Data Register Full Mode [5:4] read-write true ONE_DATA RDRF will be at level '1' when at least one unread data is in the Receive FIFO. 0 TWO_DATA RDRF will be at level '1' when at least two unread data are in the Receive FIFO. Cannot be used if SPI_MR.PS =1. 1 FOUR_DATA RDRF will be at level '1' when at least four unread data are in the Receive FIFO. Cannot be used when SPI_CSRx.BITS is greater than 0, or if SPI_MR.MSTR =1, or if SPI_MR.PS =1. 2 TXFTHRES Transmit FIFO Threshold [21:16] read-write 0 63 RXFTHRES Receive FIFO Threshold [29:24] read-write 0 63 IDR Interrupt Disable Register 0x18 0x20 write-only RDRF Receive Data Register Full Interrupt Disable [0:0] read-write TDRE SPI Transmit Data Register Empty Interrupt Disable [1:1] read-write MODF Mode Fault Error Interrupt Disable [2:2] read-write OVRES Overrun Error Interrupt Disable [3:3] read-write NSSR NSS Rising Interrupt Disable [8:8] read-write TXEMPTY Transmission Registers Empty Disable [9:9] read-write UNDES Underrun Error Interrupt Disable [10:10] read-write CMP Comparison Interrupt Disable [11:11] read-write TXFEF TXFEF Interrupt Disable [24:24] read-write TXFFF TXFFF Interrupt Disable [25:25] read-write TXFTHF TXFTHF Interrupt Disable [26:26] read-write RXFEF RXFEF Interrupt Disable [27:27] read-write RXFFF RXFFF Interrupt Disable [28:28] read-write RXFTHF RXFTHF Interrupt Disable [29:29] read-write TXFPTEF TXFPTEF Interrupt Disable [30:30] read-write RXFPTEF RXFPTEF Interrupt Disable [31:31] read-write IER Interrupt Enable Register 0x14 0x20 write-only RDRF Receive Data Register Full Interrupt Enable [0:0] read-write TDRE SPI Transmit Data Register Empty Interrupt Enable [1:1] read-write MODF Mode Fault Error Interrupt Enable [2:2] read-write OVRES Overrun Error Interrupt Enable [3:3] read-write NSSR NSS Rising Interrupt Enable [8:8] read-write TXEMPTY Transmission Registers Empty Enable [9:9] read-write UNDES Underrun Error Interrupt Enable [10:10] read-write CMP Comparison Interrupt Enable [11:11] read-write TXFEF TXFEF Interrupt Enable [24:24] read-write TXFFF TXFFF Interrupt Enable [25:25] read-write TXFTHF TXFTHF Interrupt Enable [26:26] read-write RXFEF RXFEF Interrupt Enable [27:27] read-write RXFFF RXFFF Interrupt Enable [28:28] read-write RXFTHF RXFTHF Interrupt Enable [29:29] read-write TXFPTEF TXFPTEF Interrupt Enable [30:30] read-write RXFPTEF RXFPTEF Interrupt Enable [31:31] read-write IMR Interrupt Mask Register 0x1C 0x20 read-only RDRF Receive Data Register Full Interrupt Mask [0:0] read-write TDRE SPI Transmit Data Register Empty Interrupt Mask [1:1] read-write MODF Mode Fault Error Interrupt Mask [2:2] read-write OVRES Overrun Error Interrupt Mask [3:3] read-write NSSR NSS Rising Interrupt Mask [8:8] read-write TXEMPTY Transmission Registers Empty Mask [9:9] read-write UNDES Underrun Error Interrupt Mask [10:10] read-write CMP Comparison Interrupt Mask [11:11] read-write TXFEF TXFEF Interrupt Mask [24:24] read-write TXFFF TXFFF Interrupt Mask [25:25] read-write TXFTHF TXFTHF Interrupt Mask [26:26] read-write RXFEF RXFEF Interrupt Mask [27:27] read-write RXFFF RXFFF Interrupt Mask [28:28] read-write RXFTHF RXFTHF Interrupt Mask [29:29] read-write TXFPTEF TXFPTEF Interrupt Mask [30:30] read-write RXFPTEF RXFPTEF Interrupt Mask [31:31] read-write MR Mode Register 0x4 0x20 read-write MSTR Master/Slave Mode [0:0] read-write true SLAVE Slave 0 MASTER Master 1 PS Peripheral Select [1:1] read-write PCSDEC Chip Select Decode [2:2] read-write BRSRCCLK Bit Rate Source Clock [3:3] read-write true PERIPH_CLK The peripheral clock is the source clock for the bit rate generation. 0 GCLK PMC GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock. 1 MODFDIS Mode Fault Detection [4:4] read-write WDRBT Wait Data Read Before Transfer [5:5] read-write LLB Local Loopback Enable [7:7] read-write LSBHALF LSB Timing Selection [8:8] read-write CMPMODE Comparison Mode [12:12] read-write true FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception of all incoming characters until REQCLR is set. 1 PCS Peripheral Chip Select [19:16] read-write true NPCS3 NPCS3 as Chip Select 7 NPCS2 NPCS2 as Chip Select 11 NPCS1 NPCS1 as Chip Select 13 NPCS0 NPCS0 as Chip Select 14 DLYBCS Delay Between Chip Selects [31:24] read-write 0 255 RDR Receive Data Register 0x8 0x20 read-only RD Receive Data [15:0] read-write 0 65535 RD16_0 Receive Data [15:0] read-write 0 65535 RD8_0 Receive Data [7:0] read-write 0 255 RD8_1 Receive Data [15:8] read-write 0 255 PCS Peripheral Chip Select [19:16] read-write 0 15 RD16_1 Receive Data [31:16] read-write 0 65535 RD8_2 Receive Data [23:16] read-write 0 255 RD8_3 Receive Data [31:24] read-write 0 255 SR Status Register 0x10 0x20 read-only RDRF Receive Data Register Full (cleared by reading SPI_RDR) [0:0] read-write TDRE Transmit Data Register Empty (cleared by writing SPI_TDR) [1:1] read-write MODF Mode Fault Error (cleared on read) [2:2] read-write OVRES Overrun Error Status (cleared on read) [3:3] read-write NSSR NSS Rising (cleared on read) [8:8] read-write TXEMPTY Transmission Registers Empty (cleared by writing SPI_TDR) [9:9] read-write UNDES Underrun Error Status (Slave mode only) (cleared on read) [10:10] read-write CMP Comparison Status (cleared on read) [11:11] read-write SPIENS SPI Enable Status [16:16] read-write TXFEF Transmit FIFO Empty Flag (cleared on read) [24:24] read-write TXFFF Transmit FIFO Full Flag (cleared on read) [25:25] read-write TXFTHF Transmit FIFO Threshold Flag (cleared on read) [26:26] read-write RXFEF Receive FIFO Empty Flag [27:27] read-write RXFFF Receive FIFO Full Flag [28:28] read-write RXFTHF Receive FIFO Threshold Flag [29:29] read-write TXFPTEF Transmit FIFO Pointer Error Flag [30:30] read-write RXFPTEF Receive FIFO Pointer Error Flag [31:31] read-write TDR Transmit Data Register 0xC 0x20 write-only TD Transmit Data [15:0] read-write 0 65535 TD0 Transmit Data [15:0] read-write 0 65535 PCS Peripheral Chip Select [19:16] read-write true NPCS3 NPCS3 as Chip Select 7 NPCS2 NPCS2 as Chip Select 11 NPCS1 NPCS1 as Chip Select 13 NPCS0 NPCS0 as Chip Select 14 TD1 Transmit Data [31:16] read-write 0 65535 LASTXFER Last Transfer [24:24] read-write WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5460041 WPSR Write Protection Status Register 0xE8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [15:8] read-write 0 255 SPI1 Serial Peripheral Interface 0xFC000000 0x0 0x20 registers 0x30 0x4 registers 0x40 0xC registers 0xE4 0x8 registers CMPR Comparison Register 0x48 0x20 read-only VAL1 First Comparison Value for Received Character [15:0] read-write 0 65535 VAL2 Second Comparison Value for Received Character [31:16] read-write 0 65535 CR Control Register 0x0 0x20 write-only SPIEN SPI Enable [0:0] read-write SPIDIS SPI Disable [1:1] read-write SWRST SPI Software Reset [7:7] read-write REQCLR Request to Clear the Comparison Trigger [12:12] read-write TXFCLR Transmit FIFO Clear [16:16] read-write RXFCLR Receive FIFO Clear [17:17] read-write LASTXFER Last Transfer [24:24] read-write FIFOEN FIFO Enable [30:30] read-write FIFODIS FIFO Disable [31:31] read-write CSR Chip Select Register 0x30 0x20 read-write CPOL Clock Polarity [0:0] read-write true IDLE_LOW Clock is low when inactive (CPOL=0) 0 IDLE_HIGH Clock is high when inactive (CPOL=1) 1 NCPHA Clock Phase [1:1] read-write true VALID_TRAILING_EDGE Data is valid on clock trailing edge (NCPHA=0) 0 VALID_LEADING_EDGE Data is valid on clock leading edge (NCPHA=1) 1 CSNAAT Chip Select Not Active After Transfer (ignored if CSAAT = 1) [2:2] read-write CSAAT Chip Select Active After Transfer [3:3] read-write BITS Bits Per Transfer [7:4] read-write true _8_BIT 8 bits for transfer 0 _9_BIT 9 bits for transfer 1 _10_BIT 10 bits for transfer 2 _11_BIT 11 bits for transfer 3 _12_BIT 12 bits for transfer 4 _13_BIT 13 bits for transfer 5 _14_BIT 14 bits for transfer 6 _15_BIT 15 bits for transfer 7 _16_BIT 16 bits for transfer 8 SCBR Serial Clock Bit Rate [15:8] read-write 0 255 DLYBS Delay Before SPCK [23:16] read-write 0 255 DLYBCT Delay Between Consecutive Transfers [31:24] read-write 0 255 FLR FIFO Level Register 0x44 0x20 read-only TXFL Transmit FIFO Level [5:0] read-write 0 63 RXFL Receive FIFO Level [21:16] read-write 0 63 FMR FIFO Mode Register 0x40 0x20 read-write TXRDYM Transmit Data Register Empty Mode [1:0] read-write true ONE_DATA TDRE will be at level '1' when at least one data can be written in the Transmit FIFO. 0 TWO_DATA TDRE will be at level '1' when at least two data can be written in the Transmit FIFO. Cannot be used if SPI_MR.PS =1. 1 RXRDYM Receive Data Register Full Mode [5:4] read-write true ONE_DATA RDRF will be at level '1' when at least one unread data is in the Receive FIFO. 0 TWO_DATA RDRF will be at level '1' when at least two unread data are in the Receive FIFO. Cannot be used if SPI_MR.PS =1. 1 FOUR_DATA RDRF will be at level '1' when at least four unread data are in the Receive FIFO. Cannot be used when SPI_CSRx.BITS is greater than 0, or if SPI_MR.MSTR =1, or if SPI_MR.PS =1. 2 TXFTHRES Transmit FIFO Threshold [21:16] read-write 0 63 RXFTHRES Receive FIFO Threshold [29:24] read-write 0 63 IDR Interrupt Disable Register 0x18 0x20 write-only RDRF Receive Data Register Full Interrupt Disable [0:0] read-write TDRE SPI Transmit Data Register Empty Interrupt Disable [1:1] read-write MODF Mode Fault Error Interrupt Disable [2:2] read-write OVRES Overrun Error Interrupt Disable [3:3] read-write NSSR NSS Rising Interrupt Disable [8:8] read-write TXEMPTY Transmission Registers Empty Disable [9:9] read-write UNDES Underrun Error Interrupt Disable [10:10] read-write CMP Comparison Interrupt Disable [11:11] read-write TXFEF TXFEF Interrupt Disable [24:24] read-write TXFFF TXFFF Interrupt Disable [25:25] read-write TXFTHF TXFTHF Interrupt Disable [26:26] read-write RXFEF RXFEF Interrupt Disable [27:27] read-write RXFFF RXFFF Interrupt Disable [28:28] read-write RXFTHF RXFTHF Interrupt Disable [29:29] read-write TXFPTEF TXFPTEF Interrupt Disable [30:30] read-write RXFPTEF RXFPTEF Interrupt Disable [31:31] read-write IER Interrupt Enable Register 0x14 0x20 write-only RDRF Receive Data Register Full Interrupt Enable [0:0] read-write TDRE SPI Transmit Data Register Empty Interrupt Enable [1:1] read-write MODF Mode Fault Error Interrupt Enable [2:2] read-write OVRES Overrun Error Interrupt Enable [3:3] read-write NSSR NSS Rising Interrupt Enable [8:8] read-write TXEMPTY Transmission Registers Empty Enable [9:9] read-write UNDES Underrun Error Interrupt Enable [10:10] read-write CMP Comparison Interrupt Enable [11:11] read-write TXFEF TXFEF Interrupt Enable [24:24] read-write TXFFF TXFFF Interrupt Enable [25:25] read-write TXFTHF TXFTHF Interrupt Enable [26:26] read-write RXFEF RXFEF Interrupt Enable [27:27] read-write RXFFF RXFFF Interrupt Enable [28:28] read-write RXFTHF RXFTHF Interrupt Enable [29:29] read-write TXFPTEF TXFPTEF Interrupt Enable [30:30] read-write RXFPTEF RXFPTEF Interrupt Enable [31:31] read-write IMR Interrupt Mask Register 0x1C 0x20 read-only RDRF Receive Data Register Full Interrupt Mask [0:0] read-write TDRE SPI Transmit Data Register Empty Interrupt Mask [1:1] read-write MODF Mode Fault Error Interrupt Mask [2:2] read-write OVRES Overrun Error Interrupt Mask [3:3] read-write NSSR NSS Rising Interrupt Mask [8:8] read-write TXEMPTY Transmission Registers Empty Mask [9:9] read-write UNDES Underrun Error Interrupt Mask [10:10] read-write CMP Comparison Interrupt Mask [11:11] read-write TXFEF TXFEF Interrupt Mask [24:24] read-write TXFFF TXFFF Interrupt Mask [25:25] read-write TXFTHF TXFTHF Interrupt Mask [26:26] read-write RXFEF RXFEF Interrupt Mask [27:27] read-write RXFFF RXFFF Interrupt Mask [28:28] read-write RXFTHF RXFTHF Interrupt Mask [29:29] read-write TXFPTEF TXFPTEF Interrupt Mask [30:30] read-write RXFPTEF RXFPTEF Interrupt Mask [31:31] read-write MR Mode Register 0x4 0x20 read-write MSTR Master/Slave Mode [0:0] read-write true SLAVE Slave 0 MASTER Master 1 PS Peripheral Select [1:1] read-write PCSDEC Chip Select Decode [2:2] read-write BRSRCCLK Bit Rate Source Clock [3:3] read-write true PERIPH_CLK The peripheral clock is the source clock for the bit rate generation. 0 GCLK PMC GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock. 1 MODFDIS Mode Fault Detection [4:4] read-write WDRBT Wait Data Read Before Transfer [5:5] read-write LLB Local Loopback Enable [7:7] read-write LSBHALF LSB Timing Selection [8:8] read-write CMPMODE Comparison Mode [12:12] read-write true FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception of all incoming characters until REQCLR is set. 1 PCS Peripheral Chip Select [19:16] read-write true NPCS3 NPCS3 as Chip Select 7 NPCS2 NPCS2 as Chip Select 11 NPCS1 NPCS1 as Chip Select 13 NPCS0 NPCS0 as Chip Select 14 DLYBCS Delay Between Chip Selects [31:24] read-write 0 255 RDR Receive Data Register 0x8 0x20 read-only RD Receive Data [15:0] read-write 0 65535 RD16_0 Receive Data [15:0] read-write 0 65535 RD8_0 Receive Data [7:0] read-write 0 255 RD8_1 Receive Data [15:8] read-write 0 255 PCS Peripheral Chip Select [19:16] read-write 0 15 RD16_1 Receive Data [31:16] read-write 0 65535 RD8_2 Receive Data [23:16] read-write 0 255 RD8_3 Receive Data [31:24] read-write 0 255 SR Status Register 0x10 0x20 read-only RDRF Receive Data Register Full (cleared by reading SPI_RDR) [0:0] read-write TDRE Transmit Data Register Empty (cleared by writing SPI_TDR) [1:1] read-write MODF Mode Fault Error (cleared on read) [2:2] read-write OVRES Overrun Error Status (cleared on read) [3:3] read-write NSSR NSS Rising (cleared on read) [8:8] read-write TXEMPTY Transmission Registers Empty (cleared by writing SPI_TDR) [9:9] read-write UNDES Underrun Error Status (Slave mode only) (cleared on read) [10:10] read-write CMP Comparison Status (cleared on read) [11:11] read-write SPIENS SPI Enable Status [16:16] read-write TXFEF Transmit FIFO Empty Flag (cleared on read) [24:24] read-write TXFFF Transmit FIFO Full Flag (cleared on read) [25:25] read-write TXFTHF Transmit FIFO Threshold Flag (cleared on read) [26:26] read-write RXFEF Receive FIFO Empty Flag [27:27] read-write RXFFF Receive FIFO Full Flag [28:28] read-write RXFTHF Receive FIFO Threshold Flag [29:29] read-write TXFPTEF Transmit FIFO Pointer Error Flag [30:30] read-write RXFPTEF Receive FIFO Pointer Error Flag [31:31] read-write TDR Transmit Data Register 0xC 0x20 write-only TD Transmit Data [15:0] read-write 0 65535 TD0 Transmit Data [15:0] read-write 0 65535 PCS Peripheral Chip Select [19:16] read-write true NPCS3 NPCS3 as Chip Select 7 NPCS2 NPCS2 as Chip Select 11 NPCS1 NPCS1 as Chip Select 13 NPCS0 NPCS0 as Chip Select 14 TD1 Transmit Data [31:16] read-write 0 65535 LASTXFER Last Transfer [24:24] read-write WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5460041 WPSR Write Protection Status Register 0xE8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [15:8] read-write 0 255 SSC0 Synchronous Serial Controller 0xF8004000 0x0 0x8 registers 0x10 0x18 registers 0x30 0x20 registers 0xE4 0x8 registers CMR Clock Mode Register 0x4 0x20 read-write DIV Clock Divider [11:0] read-write 0 4095 CR Control Register 0x0 0x20 write-only RXEN Receive Enable [0:0] read-write RXDIS Receive Disable [1:1] read-write TXEN Transmit Enable [8:8] read-write TXDIS Transmit Disable [9:9] read-write SWRST Software Reset [15:15] read-write IDR Interrupt Disable Register 0x48 0x20 write-only TXRDY Transmit Ready Interrupt Disable [0:0] read-write TXEMPTY Transmit Empty Interrupt Disable [1:1] read-write RXRDY Receive Ready Interrupt Disable [4:4] read-write OVRUN Receive Overrun Interrupt Disable [5:5] read-write CP0 Compare 0 Interrupt Disable [8:8] read-write CP1 Compare 1 Interrupt Disable [9:9] read-write TXSYN Tx Sync Interrupt Enable [10:10] read-write RXSYN Rx Sync Interrupt Enable [11:11] read-write IER Interrupt Enable Register 0x44 0x20 write-only TXRDY Transmit Ready Interrupt Enable [0:0] read-write TXEMPTY Transmit Empty Interrupt Enable [1:1] read-write RXRDY Receive Ready Interrupt Enable [4:4] read-write OVRUN Receive Overrun Interrupt Enable [5:5] read-write CP0 Compare 0 Interrupt Enable [8:8] read-write CP1 Compare 1 Interrupt Enable [9:9] read-write TXSYN Tx Sync Interrupt Enable [10:10] read-write RXSYN Rx Sync Interrupt Enable [11:11] read-write IMR Interrupt Mask Register 0x4C 0x20 read-only TXRDY Transmit Ready Interrupt Mask [0:0] read-write TXEMPTY Transmit Empty Interrupt Mask [1:1] read-write RXRDY Receive Ready Interrupt Mask [4:4] read-write OVRUN Receive Overrun Interrupt Mask [5:5] read-write CP0 Compare 0 Interrupt Mask [8:8] read-write CP1 Compare 1 Interrupt Mask [9:9] read-write TXSYN Tx Sync Interrupt Mask [10:10] read-write RXSYN Rx Sync Interrupt Mask [11:11] read-write RC0R Receive Compare 0 Register 0x38 0x20 read-write CP0 Receive Compare Data 0 [15:0] read-write 0 65535 RC1R Receive Compare 1 Register 0x3C 0x20 read-write CP1 Receive Compare Data 1 [15:0] read-write 0 65535 RCMR Receive Clock Mode Register 0x10 0x20 read-write CKS Receive Clock Selection [1:0] read-write true MCK Divided Clock 0 TK TK Clock signal 1 RK RK pin 2 CKO Receive Clock Output Mode Selection [4:2] read-write true NONE None, RK pin is an input 0 CONTINUOUS Continuous Receive Clock, RK pin is an output 1 TRANSFER Receive Clock only during data transfers, RK pin is an output 2 CKI Receive Clock Inversion [5:5] read-write CKG Receive Clock Gating Selection [7:6] read-write true CONTINUOUS None 0 EN_RF_LOW Receive Clock enabled only if RF Low 1 EN_RF_HIGH Receive Clock enabled only if RF High 2 START Receive Start Selection [11:8] read-write true CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0 TRANSMIT Transmit start 1 RF_LOW Detection of a low level on RF signal 2 RF_HIGH Detection of a high level on RF signal 3 RF_FALLING Detection of a falling edge on RF signal 4 RF_RISING Detection of a rising edge on RF signal 5 RF_LEVEL Detection of any level change on RF signal 6 RF_EDGE Detection of any edge on RF signal 7 CMP_0 Compare 0 8 STOP Receive Stop Selection [12:12] read-write STTDLY Receive Start Delay [23:16] read-write 0 255 PERIOD Receive Period Divider Selection [31:24] read-write 0 255 RFMR Receive Frame Mode Register 0x14 0x20 read-write DATLEN Data Length [4:0] read-write 0 31 LOOP Loop Mode [5:5] read-write MSBF Most Significant Bit First [7:7] read-write DATNB Data Number per Frame [11:8] read-write 0 15 FSLEN Receive Frame Sync Length [19:16] read-write 0 15 FSOS Receive Frame Sync Output Selection [22:20] read-write true NONE None, RF pin is an input 0 NEGATIVE Negative Pulse, RF pin is an output 1 POSITIVE Positive Pulse, RF pin is an output 2 LOW Driven Low during data transfer, RF pin is an output 3 HIGH Driven High during data transfer, RF pin is an output 4 TOGGLING Toggling at each start of data transfer, RF pin is an output 5 FSEDGE Frame Sync Edge Detection [24:24] read-write true POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN_EXT FSLEN Field Extension [31:28] read-write 0 15 RHR Receive Holding Register 0x20 0x20 read-only RDAT Receive Data [31:0] read-write 0 4294967295 RSHR Receive Sync. Holding Register 0x30 0x20 read-only RSDAT Receive Synchronization Data [15:0] read-write 0 65535 SR Status Register 0x40 0x20 read-only TXRDY Transmit Ready [0:0] read-write TXEMPTY Transmit Empty [1:1] read-write RXRDY Receive Ready [4:4] read-write OVRUN Receive Overrun [5:5] read-write CP0 Compare 0 [8:8] read-write CP1 Compare 1 [9:9] read-write TXSYN Transmit Sync [10:10] read-write RXSYN Receive Sync [11:11] read-write TXEN Transmit Enable [16:16] read-write RXEN Receive Enable [17:17] read-write TCMR Transmit Clock Mode Register 0x18 0x20 read-write CKS Transmit Clock Selection [1:0] read-write true MCK Divided Clock 0 RK RK Clock signal 1 TK TK pin 2 CKO Transmit Clock Output Mode Selection [4:2] read-write true NONE None, TK pin is an input 0 CONTINUOUS Continuous Transmit Clock, TK pin is an output 1 TRANSFER Transmit Clock only during data transfers, TK pin is an output 2 CKI Transmit Clock Inversion [5:5] read-write CKG Transmit Clock Gating Selection [7:6] read-write true CONTINUOUS None 0 EN_TF_LOW Transmit Clock enabled only if TF Low 1 EN_TF_HIGH Transmit Clock enabled only if TF High 2 START Transmit Start Selection [11:8] read-write true CONTINUOUS Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data 0 RECEIVE Receive start 1 TF_LOW Detection of a low level on TF signal 2 TF_HIGH Detection of a high level on TF signal 3 TF_FALLING Detection of a falling edge on TF signal 4 TF_RISING Detection of a rising edge on TF signal 5 TF_LEVEL Detection of any level change on TF signal 6 TF_EDGE Detection of any edge on TF signal 7 STTDLY Transmit Start Delay [23:16] read-write 0 255 PERIOD Transmit Period Divider Selection [31:24] read-write 0 255 TFMR Transmit Frame Mode Register 0x1C 0x20 read-write DATLEN Data Length [4:0] read-write 0 31 DATDEF Data Default Value [5:5] read-write MSBF Most Significant Bit First [7:7] read-write DATNB Data Number per Frame [11:8] read-write 0 15 FSLEN Transmit Frame Sync Length [19:16] read-write 0 15 FSOS Transmit Frame Sync Output Selection [22:20] read-write true NONE None, TF pin is an input 0 NEGATIVE Negative Pulse, TF pin is an output 1 POSITIVE Positive Pulse, TF pin is an output 2 LOW Driven Low during data transfer 3 HIGH Driven High during data transfer 4 TOGGLING Toggling at each start of data transfer 5 FSDEN Frame Sync Data Enable [23:23] read-write FSEDGE Frame Sync Edge Detection [24:24] read-write true POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN_EXT FSLEN Field Extension [31:28] read-write 0 15 THR Transmit Holding Register 0x24 0x20 write-only TDAT Transmit Data [31:0] read-write 0 4294967295 TSHR Transmit Sync. Holding Register 0x34 0x20 read-write TSDAT Transmit Synchronization Data [15:0] read-write 0 65535 WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5460803 WPSR Write Protection Status Register 0xE8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protect Violation Source [23:8] read-write 0 65535 SSC1 Synchronous Serial Controller 0xFC004000 TC0 Timer Counter 0xF800C000 0x0 0x1C registers 0x24 0x4 registers BCR Block Control Register 0x0 0x20 write-only SYNC Synchro Command [0:0] read-write BMR Block Mode Register 0x4 0x20 read-write TC0XC0S External Clock Signal 0 Selection [1:0] read-write true TCLK0 Signal connected to XC0: TCLK0 0 TIOA1 Signal connected to XC0: TIOA1 2 TIOA2 Signal connected to XC0: TIOA2 3 TC1XC1S External Clock Signal 1 Selection [3:2] read-write true TCLK1 Signal connected to XC1: TCLK1 0 TIOA0 Signal connected to XC1: TIOA0 2 TIOA2 Signal connected to XC1: TIOA2 3 TC2XC2S External Clock Signal 2 Selection [5:4] read-write true TCLK2 Signal connected to XC2: TCLK2 0 TIOA0 Signal connected to XC2: TIOA0 2 TIOA1 Signal connected to XC2: TIOA1 3 QDEN Quadrature Decoder Enabled [8:8] read-write POSEN Position Enabled [9:9] read-write SPEEDEN Speed Enabled [10:10] read-write QDTRANS Quadrature Decoding Transparent [11:11] read-write EDGPHA Edge on PHA Count Mode [12:12] read-write INVA Inverted PHA [13:13] read-write INVB Inverted PHB [14:14] read-write INVIDX Inverted Index [15:15] read-write SWAP Swap PHA and PHB [16:16] read-write IDXPHB Index Pin is PHB Pin [17:17] read-write AUTOC AutoCorrection of missing pulses [18:18] read-write true DISABLED The detection and autocorrection function is disabled. 0 ENABLED The detection and autocorrection function is enabled. 1 MAXFILT Maximum Filter [25:20] read-write 0 63 MAXCMP Maximum Consecutive Missing Pulses [29:26] read-write 0 15 FMR Fault Mode Register 0x18 0x20 read-write ENCF0 Enable Compare Fault Channel 0 [0:0] read-write ENCF1 Enable Compare Fault Channel 1 [1:1] read-write QIDR QDEC Interrupt Disable Register 0xC 0x20 write-only IDX Index [0:0] read-write DIRCHG Direction Change [1:1] read-write QERR Quadrature Error [2:2] read-write MPE Consecutive Missing Pulse Error [3:3] read-write QIER QDEC Interrupt Enable Register 0x8 0x20 write-only IDX Index [0:0] read-write DIRCHG Direction Change [1:1] read-write QERR Quadrature Error [2:2] read-write MPE Consecutive Missing Pulse Error [3:3] read-write QIMR QDEC Interrupt Mask Register 0x10 0x20 read-only IDX Index [0:0] read-write DIRCHG Direction Change [1:1] read-write QERR Quadrature Error [2:2] read-write MPE Consecutive Missing Pulse Error [3:3] read-write QISR QDEC Interrupt Status Register 0x14 0x20 read-only IDX Index [0:0] read-write DIRCHG Direction Change [1:1] read-write QERR Quadrature Error [2:2] read-write MPE Consecutive Missing Pulse Error [3:3] read-write DIR Direction [8:8] read-write WPMR Write Protection Mode Register 0x24 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5523789 CCR0 Channel Control Register. 0x00 CLKEN Counter Clock Enable Command. 0 1 CLKDIS Counter Clock Disable Command. 1 1 SWTRG Software Trigger Command. 2 1 CCR1 Channel Control Register. 0x40 CLKEN Counter Clock Enable Command. 0 1 CLKDIS Counter Clock Disable Command. 1 1 SWTRG Software Trigger Command. 2 1 CCR2 Channel Control Register. 0x80 CLKEN Counter Clock Enable Command. 0 1 CLKDIS Counter Clock Disable Command. 1 1 SWTRG Software Trigger Command. 2 1 CMR0 Channel Mode Register. 0x04 CMR1 Channel Mode Register. 0x44 CMR2 Channel Mode Register. 0x84 SMMR0 Stepper Motor Mode Register. 0x08 GCEN Gray Count Enable 0 1 DOWN Down Count 1 1 SMMR1 Stepper Motor Mode Register. 0x48 GCEN Gray Count Enable 0 1 DOWN Down Count 1 1 SMMR2 Stepper Motor Mode Register. 0x88 GCEN Gray Count Enable 0 1 DOWN Down Count 1 1 RAB0 Register A or B. 0x0C RAB1 Register A or B. 0x4C RAB2 Register A or B. 0x8C CV0 Counter Value. 0x10 CV1 Counter Value. 0x50 CV2 Counter Value. 0x90 RA0 Register A. 0x14 RA1 Register A. 0x54 RA2 Register A. 0x84 RB0 Register B. 0x18 RB1 Register B. 0x58 RB2 Register B. 0x88 RC0 Register C. 0x1C RC1 Register C. 0x5C RC2 Register C. 0x8C SR0 Interrupt Status Register. 0x20 COVFS Counter Overflow Status (cleared on read) 0 1 LOVRS Load Overrun Status (cleared on read) 1 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 ETRGS External Trigger Status (cleared on read) 7 1 CLKSTA Clock Enabling Status 16 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 SR1 Interrupt Status Register. 0x60 COVFS Counter Overflow Status (cleared on read) 0 1 LOVRS Load Overrun Status (cleared on read) 1 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 ETRGS External Trigger Status (cleared on read) 7 1 CLKSTA Clock Enabling Status 16 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 SR2 Interrupt Status Register. 0xA0 COVFS Counter Overflow Status (cleared on read) 0 1 LOVRS Load Overrun Status (cleared on read) 1 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 ETRGS External Trigger Status (cleared on read) 7 1 CLKSTA Clock Enabling Status 16 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 IER0 Interrupt Enable Register 0x24 COVFS Counter Overflow 0 1 LOVRS Load Overrun 1 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 ETRGS External Trigger 7 1 IER1 Interrupt Enable Register 0x64 COVFS Counter Overflow 0 1 LOVRS Load Overrun 1 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 ETRGS External Trigger 7 1 IER2 Interrupt Enable Register 0xA4 COVFS Counter Overflow 0 1 LOVRS Load Overrun 1 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 ETRGS External Trigger 7 1 IDR0 Interrupt Disable Register 0x28 COVFS Counter Overflow 0 1 LOVRS Load Overrun 1 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 ETRGS External Trigger 7 1 IDR1 Interrupt Disable Register 0x68 COVFS Counter Overflow 0 1 LOVRS Load Overrun 1 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 ETRGS External Trigger 7 1 IDR2 Interrupt Disable Register 0xA8 COVFS Counter Overflow 0 1 LOVRS Load Overrun 1 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 ETRGS External Trigger 7 1 IMR0 Interrupt Mask Register 0x2C COVFS Counter Overflow 0 1 LOVRS Load Overrun 1 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 ETRGS External Trigger 7 1 IMR1 Interrupt Mask Register 0x6C COVFS Counter Overflow 0 1 LOVRS Load Overrun 1 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 ETRGS External Trigger 7 1 IMR2 Interrupt Mask Register 0xAC COVFS Counter Overflow 0 1 LOVRS Load Overrun 1 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 ETRGS External Trigger 7 1 EMR0 Extended Mode Register. 0x30 TRIGSRCA Trigger Source for Input A. 0 2 TRIGSRCB Trigger Source for Input B. 4 2 NODIVCLK No Divided Clock. 8 1 EMR1 Extended Mode Register. 0xB0 TRIGSRCA Trigger Source for Input A. 0 2 TRIGSRCB Trigger Source for Input B. 4 2 NODIVCLK No Divided Clock. 8 1 EMR2 Extended Mode Register. 0xF0 TRIGSRCA Trigger Source for Input A. 0 2 TRIGSRCB Trigger Source for Input B. 4 2 NODIVCLK No Divided Clock. 8 1 TC1 Timer Counter 0xF8010000 TDES Triple Data Encryption Standard 0xFC044000 0x0 0x8 registers 0x10 0x14 registers 0x28 0x4 registers 0x30 0x4 registers 0x40 0x4 registers 0x50 0x4 registers 0x60 0x4 registers 0x70 0x4 registers CR Control Register 0x0 0x20 write-only START Start Processing [0:0] read-write SWRST Software Reset [8:8] read-write IDATAR Input Data Register 0x40 0x20 write-only IDATA Input Data [31:0] read-write 0 4294967295 IDR Interrupt Disable Register 0x14 0x20 write-only DATRDY Data Ready Interrupt Disable [0:0] read-write URAD Unspecified Register Access Detection Interrupt Disable [8:8] read-write IER Interrupt Enable Register 0x10 0x20 write-only DATRDY Data Ready Interrupt Enable [0:0] read-write URAD Unspecified Register Access Detection Interrupt Enable [8:8] read-write IMR Interrupt Mask Register 0x18 0x20 read-only DATRDY Data Ready Interrupt Mask [0:0] read-write URAD Unspecified Register Access Detection Interrupt Mask [8:8] read-write ISR Interrupt Status Register 0x1C 0x20 read-only DATRDY Data Ready (cleared by setting bit START or bit SWRST in TDES_CR or by reading TDES_ODATARx) [0:0] read-write URAD Unspecified Register Access Detection Status (cleared by setting bit TDES_CR.SWRST) [8:8] read-write URAT Unspecified Register Access (cleared by setting bit TDES_CR.SWRST) [13:12] read-write true IDR_WR_PROCESSING Input Data Register written during data processing when SMOD = 0x2 mode. 0 ODR_RD_PROCESSING Output Data Register read during data processing. 1 MR_WR_PROCESSING Mode Register written during data processing. 2 WOR_RD_ACCESS Write-only register read access. 3 IVR Initialization Vector Register 0x60 0x20 write-only IV Initialization Vector [31:0] read-write 0 4294967295 KEY1WR Key 1 Word Register 0x20 0x20 write-only KEY1W Key 1 Word [31:0] read-write 0 4294967295 KEY2WR Key 2 Word Register 0x28 0x20 write-only KEY2W Key 2 Word [31:0] read-write 0 4294967295 KEY3WR Key 3 Word Register 0x30 0x20 write-only KEY3W Key 3 Word [31:0] read-write 0 4294967295 MR Mode Register 0x4 0x20 read-write CIPHER Processing Mode [0:0] read-write true DECRYPT Decrypts data. 0 ENCRYPT Encrypts data. 1 TDESMOD ALGORITHM Mode [2:1] read-write true SINGLE_DES Single DES processing using Key 1 Registers 0 TRIPLE_DES Triple DES processing using Key 1, Key 2 and Key 3 Registers 1 XTEA XTEA processing using Key 1 and Key 2 Registers 2 KEYMOD Key Mode [4:4] read-write SMOD Start Mode [9:8] read-write true MANUAL_START Manual Mode 0 AUTO_START Auto Mode 1 IDATAR0_START TDES_IDATAR0 accesses only Auto Mode 2 OPMOD Operating Mode [13:12] read-write true ECB Electronic Code Book mode 0 CBC Cipher Block Chaining mode 1 OFB Output Feedback mode 2 CFB Cipher Feedback mode 3 LOD Last Output Data Mode [15:15] read-write CFBS Cipher Feedback Data Size [17:16] read-write true SIZE_64BIT 64-bit 0 SIZE_32BIT 32-bit 1 SIZE_16BIT 16-bit 2 SIZE_8BIT 8-bit 3 ODATAR Output Data Register 0x50 0x20 read-only ODATA Output Data [31:0] read-write 0 4294967295 XTEA_RNDR XTEA Rounds Register 0x70 0x20 read-write XTEA_RNDS Number of Rounds [5:0] read-write 0 63 TRNG True Random Number Generator 0xFC01C000 0x0 0x4 registers 0x10 0x10 registers 0x50 0x4 registers CR Control Register 0x0 0x20 write-only ENABLE Enables the TRNG to Provide Random Values [0:0] read-write WAKEY Register Write Access Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation. 5393991 IDR Interrupt Disable Register 0x14 0x20 write-only DATRDY Data Ready Interrupt Disable [0:0] read-write IER Interrupt Enable Register 0x10 0x20 write-only DATRDY Data Ready Interrupt Enable [0:0] read-write IMR Interrupt Mask Register 0x18 0x20 read-only DATRDY Data Ready Interrupt Mask [0:0] read-write ISR Interrupt Status Register 0x1C 0x20 read-only DATRDY Data Ready (cleared on read) [0:0] read-write ODATA Output Data Register 0x50 0x20 read-only ODATA Output Data [31:0] read-write 0 4294967295 TWIHS0 Two-wire Interface High Speed 0xF8028000 0x0 0x14 registers 0x20 0x1C registers 0x40 0x8 registers 0x4C 0xC registers 0x60 0x10 registers 0xD0 0x4 registers 0xE4 0x8 registers ACR Alternative Command Register 0x40 0x20 read-write DATAL Data Length [7:0] read-write 0 255 DIR Transfer Direction [8:8] read-write PEC PEC Request (SMBus Mode only) [9:9] read-write NDATAL Next Data Length [23:16] read-write 0 255 NDIR Next Transfer Direction [24:24] read-write NPEC Next PEC Request (SMBus Mode only) [25:25] read-write CR Control Register 0x0 0x20 write-only START Send a START Condition [0:0] read-write STOP Send a STOP Condition [1:1] read-write MSEN TWIHS Master Mode Enabled [2:2] read-write MSDIS TWIHS Master Mode Disabled [3:3] read-write SVEN TWIHS Slave Mode Enabled [4:4] read-write SVDIS TWIHS Slave Mode Disabled [5:5] read-write QUICK SMBus Quick Command [6:6] read-write SWRST Software Reset [7:7] read-write HSEN TWIHS High-Speed Mode Enabled [8:8] read-write HSDIS TWIHS High-Speed Mode Disabled [9:9] read-write SMBEN SMBus Mode Enabled [10:10] read-write SMBDIS SMBus Mode Disabled [11:11] read-write PECEN Packet Error Checking Enable [12:12] read-write PECDIS Packet Error Checking Disable [13:13] read-write PECRQ PEC Request [14:14] read-write CLEAR Bus CLEAR Command [15:15] read-write ACMEN Alternative Command Mode Enable [16:16] read-write ACMDIS Alternative Command Mode Disable [17:17] read-write THRCLR Transmit Holding Register Clear [24:24] read-write TXFCLR Transmit FIFO Clear [24:24] read-write RXFCLR Receive FIFO Clear [25:25] read-write LOCKCLR Lock Clear [26:26] read-write TXFLCLR Transmit FIFO Lock CLEAR [26:26] read-write FIFOEN FIFO Enable [28:28] read-write FIFODIS FIFO Disable [29:29] read-write CWGR Clock Waveform Generator Register 0x10 0x20 read-write CLDIV Clock Low Divider [7:0] read-write 0 255 CHDIV Clock High Divider [15:8] read-write 0 255 CKDIV Clock Divider [18:16] read-write 0 7 CKSRC Transfer Rate Clock Source [20:20] read-write true PERIPH_CK Peripheral clock is used to generate the TWIHS baud rate. 0 GCLK GCLK is used to generate the TWIHS baud rate. 1 HOLD TWD Hold Time Versus TWCK Falling [28:24] read-write 0 31 DR Debug Register 0xD0 0x20 read-only SWEN SleepWalking Enable [0:0] read-write CLKRQ Clock Request [1:1] read-write SWMATCH SleepWalking Match [2:2] read-write TRP Transfer Pending [3:3] read-write FIDR FIFO Interrupt Disable Register 0x68 0x20 write-only TXFEF TXFEF Interrupt Disable [0:0] read-write TXFFF TXFFF Interrupt Disable [1:1] read-write TXFTHF TXFTHF Interrupt Disable [2:2] read-write RXFEF RXFEF Interrupt Disable [3:3] read-write RXFFF RXFFF Interrupt Disable [4:4] read-write RXFTHF RXFTHF Interrupt Disable [5:5] read-write TXFPTEF TXFPTEF Interrupt Disable [6:6] read-write RXFPTEF RXFPTEF Interrupt Disable [7:7] read-write FIER FIFO Interrupt Enable Register 0x64 0x20 write-only TXFEF TXFEF Interrupt Enable [0:0] read-write TXFFF TXFFF Interrupt Enable [1:1] read-write TXFTHF TXFTHF Interrupt Enable [2:2] read-write RXFEF RXFEF Interrupt Enable [3:3] read-write RXFFF RXFFF Interrupt Enable [4:4] read-write RXFTHF RXFTHF Interrupt Enable [5:5] read-write TXFPTEF TXFPTEF Interrupt Enable [6:6] read-write RXFPTEF RXFPTEF Interrupt Enable [7:7] read-write FILTR Filter Register 0x44 0x20 read-write FILT RX Digital Filter [0:0] read-write PADFEN PAD Filter Enable [1:1] read-write PADFCFG PAD Filter Config [2:2] read-write THRES Digital Filter Threshold [10:8] read-write 0 7 FIMR FIFO Interrupt Mask Register 0x6C 0x20 read-only TXFEF TXFEF Interrupt Mask [0:0] read-write TXFFF TXFFF Interrupt Mask [1:1] read-write TXFTHF TXFTHF Interrupt Mask [2:2] read-write RXFEF RXFEF Interrupt Mask [3:3] read-write RXFFF RXFFF Interrupt Mask [4:4] read-write RXFTHF RXFTHF Interrupt Mask [5:5] read-write TXFPTEF TXFPTEF Interrupt Mask [6:6] read-write RXFPTEF RXFPTEF Interrupt Mask [7:7] read-write FLR FIFO Level Register 0x54 0x20 read-only TXFL Transmit FIFO Level [5:0] read-write 0 63 RXFL Receive FIFO Level [21:16] read-write 0 63 FMR FIFO Mode Register 0x50 0x20 read-write TXRDYM Transmitter Ready Mode [1:0] read-write true ONE_DATA TXRDY will be at level '1' when at least one data can be written in the Transmit FIFO 0 TWO_DATA TXRDY will be at level '1' when at least two data can be written in the Transmit FIFO 1 FOUR_DATA TXRDY will be at level '1' when at least four data can be written in the Transmit FIFO 2 RXRDYM Receiver Ready Mode [5:4] read-write true ONE_DATA RXRDY will be at level '1' when at least one unread data is in the Receive FIFO 0 TWO_DATA RXRDY will be at level '1' when at least two unread data are in the Receive FIFO 1 FOUR_DATA RXRDY will be at level '1' when at least four unread data are in the Receive FIFO 2 TXFTHRES Transmit FIFO Threshold [21:16] read-write 0 63 RXFTHRES Receive FIFO Threshold [29:24] read-write 0 63 FSR FIFO Status Register 0x60 0x20 read-only TXFEF Transmit FIFO Empty Flag (cleared on read) [0:0] read-write TXFFF Transmit FIFO Full Flag (cleared on read) [1:1] read-write TXFTHF Transmit FIFO Threshold Flag (cleared on read) [2:2] read-write RXFEF Receive FIFO Empty Flag [3:3] read-write RXFFF Receive FIFO Full Flag [4:4] read-write RXFTHF Receive FIFO Threshold Flag [5:5] read-write TXFPTEF Transmit FIFO Pointer Error Flag [6:6] read-write RXFPTEF Receive FIFO Pointer Error Flag [7:7] read-write IADR Internal Address Register 0xC 0x20 read-write IADR Internal Address [23:0] read-write 0 16777215 IDR Interrupt Disable Register 0x28 0x20 write-only TXCOMP Transmission Completed Interrupt Disable [0:0] read-write RXRDY Receive Holding Register Ready Interrupt Disable [1:1] read-write TXRDY Transmit Holding Register Ready Interrupt Disable [2:2] read-write SVACC Slave Access Interrupt Disable [4:4] read-write GACC General Call Access Interrupt Disable [5:5] read-write OVRE Overrun Error Interrupt Disable [6:6] read-write UNRE Underrun Error Interrupt Disable [7:7] read-write NACK Not Acknowledge Interrupt Disable [8:8] read-write ARBLST Arbitration Lost Interrupt Disable [9:9] read-write SCL_WS Clock Wait State Interrupt Disable [10:10] read-write EOSACC End Of Slave Access Interrupt Disable [11:11] read-write MCACK Master Code Acknowledge Interrupt Disable [16:16] read-write TOUT Timeout Error Interrupt Disable [18:18] read-write PECERR PEC Error Interrupt Disable [19:19] read-write SMBDAM SMBus Default Address Match Interrupt Disable [20:20] read-write SMBHHM SMBus Host Header Address Match Interrupt Disable [21:21] read-write IER Interrupt Enable Register 0x24 0x20 write-only TXCOMP Transmission Completed Interrupt Enable [0:0] read-write RXRDY Receive Holding Register Ready Interrupt Enable [1:1] read-write TXRDY Transmit Holding Register Ready Interrupt Enable [2:2] read-write SVACC Slave Access Interrupt Enable [4:4] read-write GACC General Call Access Interrupt Enable [5:5] read-write OVRE Overrun Error Interrupt Enable [6:6] read-write UNRE Underrun Error Interrupt Enable [7:7] read-write NACK Not Acknowledge Interrupt Enable [8:8] read-write ARBLST Arbitration Lost Interrupt Enable [9:9] read-write SCL_WS Clock Wait State Interrupt Enable [10:10] read-write EOSACC End Of Slave Access Interrupt Enable [11:11] read-write MCACK Master Code Acknowledge Interrupt Enable [16:16] read-write TOUT Timeout Error Interrupt Enable [18:18] read-write PECERR PEC Error Interrupt Enable [19:19] read-write SMBDAM SMBus Default Address Match Interrupt Enable [20:20] read-write SMBHHM SMBus Host Header Address Match Interrupt Enable [21:21] read-write IMR Interrupt Mask Register 0x2C 0x20 read-only TXCOMP Transmission Completed Interrupt Mask [0:0] read-write RXRDY Receive Holding Register Ready Interrupt Mask [1:1] read-write TXRDY Transmit Holding Register Ready Interrupt Mask [2:2] read-write SVACC Slave Access Interrupt Mask [4:4] read-write GACC General Call Access Interrupt Mask [5:5] read-write OVRE Overrun Error Interrupt Mask [6:6] read-write UNRE Underrun Error Interrupt Mask [7:7] read-write NACK Not Acknowledge Interrupt Mask [8:8] read-write ARBLST Arbitration Lost Interrupt Mask [9:9] read-write SCL_WS Clock Wait State Interrupt Mask [10:10] read-write EOSACC End Of Slave Access Interrupt Mask [11:11] read-write MCACK Master Code Acknowledge Interrupt Mask [16:16] read-write TOUT Timeout Error Interrupt Mask [18:18] read-write PECERR PEC Error Interrupt Mask [19:19] read-write SMBDAM SMBus Default Address Match Interrupt Mask [20:20] read-write SMBHHM SMBus Host Header Address Match Interrupt Mask [21:21] read-write MMR Master Mode Register 0x4 0x20 read-write IADRSZ Internal Device Address Size [9:8] read-write true NONE No internal device address 0 _1_BYTE One-byte internal device address 1 _2_BYTE Two-byte internal device address 2 _3_BYTE Three-byte internal device address 3 MREAD Master Read Direction [12:12] read-write DADR Device Address [22:16] read-write 0 127 RHR Receive Holding Register 0x30 0x20 read-only RXDATA Master or Slave Receive Holding Data [7:0] read-write 0 255 RXDATA0 Master or Slave Receive Holding Data 0 [7:0] read-write 0 255 RXDATA1 Master or Slave Receive Holding Data 1 [15:8] read-write 0 255 RXDATA2 Master or Slave Receive Holding Data 2 [23:16] read-write 0 255 RXDATA3 Master or Slave Receive Holding Data 3 [31:24] read-write 0 255 SMBTR SMBus Timing Register 0x38 0x20 read-write PRESC SMBus Clock Prescaler [3:0] read-write 0 15 TLOWS Slave Clock Stretch Maximum Cycles [15:8] read-write 0 255 TLOWM Master Clock Stretch Maximum Cycles [23:16] read-write 0 255 THMAX Clock High Maximum Cycles [31:24] read-write 0 255 SMR Slave Mode Register 0x8 0x20 read-write NACKEN Slave Receiver Data Phase NACK enable [0:0] read-write SMDA SMBus Default Address [2:2] read-write SMHH SMBus Host Header [3:3] read-write SCLWSDIS Clock Wait State Disable [6:6] read-write MASK Slave Address Mask [14:8] read-write 0 127 SADR Slave Address [22:16] read-write 0 127 SADR1EN Slave Address 1 Enable [28:28] read-write SADR2EN Slave Address 2 Enable [29:29] read-write SADR3EN Slave Address 3 Enable [30:30] read-write DATAMEN Data Matching Enable [31:31] read-write SR Status Register 0x20 0x20 read-only TXCOMP Transmission Completed (cleared by writing TWIHS_THR) [0:0] read-write RXRDY Receive Holding Register Ready (cleared by reading TWIHS_RHR) [1:1] read-write TXRDY Transmit Holding Register Ready (cleared by writing TWIHS_THR) [2:2] read-write SVREAD Slave Read [3:3] read-write SVACC Slave Access [4:4] read-write GACC General Call Access (cleared on read) [5:5] read-write OVRE Overrun Error (cleared on read) [6:6] read-write UNRE Underrun Error (cleared on read) [7:7] read-write NACK Not Acknowledged (cleared on read) [8:8] read-write ARBLST Arbitration Lost (cleared on read) [9:9] read-write SCLWS Clock Wait State [10:10] read-write EOSACC End Of Slave Access (cleared on read) [11:11] read-write MCACK Master Code Acknowledge (cleared on read) [16:16] read-write TOUT Timeout Error (cleared on read) [18:18] read-write PECERR PEC Error (cleared on read) [19:19] read-write SMBDAM SMBus Default Address Match (cleared on read) [20:20] read-write SMBHHM SMBus Host Header Address Match (cleared on read) [21:21] read-write LOCK TWIHS Lock due to Frame Errors (cleared by writing a one to bit LOCKCLR in TWIHS_CR) [23:23] read-write TXFLOCK Transmit FIFO Lock [23:23] read-write SCL SCL Line Value [24:24] read-write SDA SDA Line Value [25:25] read-write SWMR SleepWalking Matching Register 0x4C 0x20 read-write SADR1 Slave Address 1 [6:0] read-write 0 127 SADR2 Slave Address 2 [14:8] read-write 0 127 SADR3 Slave Address 3 [22:16] read-write 0 127 DATAM Data Match [31:24] read-write 0 255 THR Transmit Holding Register 0x34 0x20 write-only TXDATA Master or Slave Transmit Holding Data [7:0] read-write 0 255 TXDATA0 Master or Slave Transmit Holding Data 02 [7:0] read-write 0 255 TXDATA1 Master or Slave Transmit Holding Data 1 [15:8] read-write 0 255 TXDATA2 Master or Slave Transmit Holding Data 2 [23:16] read-write 0 255 TXDATA3 Master or Slave Transmit Holding Data 3 [31:24] read-write 0 255 WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 5527369 WPSR Write Protection Status Register 0xE8 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [31:8] read-write 0 16777215 TWIHS1 Two-wire Interface High Speed 0xFC028000 UART0 Universal Asynchronous Receiver Transmitter 0xF801C000 0x0 0x2C registers 0xE4 0x4 registers BRGR Baud Rate Generator Register 0x20 0x20 read-write CD Clock Divisor [15:0] read-write 0 65535 CMPR Comparison Register 0x24 0x20 read-write VAL1 First Comparison Value for Received Character [7:0] read-write 0 255 CMPMODE Comparison Mode [12:12] read-write true FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity [14:14] read-write VAL2 Second Comparison Value for Received Character [23:16] read-write 0 255 CR Control Register 0x0 0x20 write-only RSTRX Reset Receiver [2:2] read-write RSTTX Reset Transmitter [3:3] read-write RXEN Receiver Enable [4:4] read-write RXDIS Receiver Disable [5:5] read-write TXEN Transmitter Enable [6:6] read-write TXDIS Transmitter Disable [7:7] read-write RSTSTA Reset Status [8:8] read-write RETTO Rearm Time-out [10:10] read-write STTTO Start Time-out [11:11] read-write REQCLR Request Clear [12:12] read-write DBGE Debug Enable [15:15] read-write IDR Interrupt Disable Register 0xC 0x20 write-only RXRDY Disable RXRDY Interrupt [0:0] read-write TXRDY Disable TXRDY Interrupt [1:1] read-write OVRE Disable Overrun Error Interrupt [5:5] read-write FRAME Disable Framing Error Interrupt [6:6] read-write PARE Disable Parity Error Interrupt [7:7] read-write TIMEOUT Disable Time-out Interrupt [8:8] read-write TXEMPTY Disable TXEMPTY Interrupt [9:9] read-write CMP Disable Comparison Interrupt [15:15] read-write IER Interrupt Enable Register 0x8 0x20 write-only RXRDY Enable RXRDY Interrupt [0:0] read-write TXRDY Enable TXRDY Interrupt [1:1] read-write OVRE Enable Overrun Error Interrupt [5:5] read-write FRAME Enable Framing Error Interrupt [6:6] read-write PARE Enable Parity Error Interrupt [7:7] read-write TIMEOUT Enable Time-out Interrupt [8:8] read-write TXEMPTY Enable TXEMPTY Interrupt [9:9] read-write CMP Enable Comparison Interrupt [15:15] read-write IMR Interrupt Mask Register 0x10 0x20 read-only RXRDY Mask RXRDY Interrupt [0:0] read-write TXRDY Disable TXRDY Interrupt [1:1] read-write OVRE Mask Overrun Error Interrupt [5:5] read-write FRAME Mask Framing Error Interrupt [6:6] read-write PARE Mask Parity Error Interrupt [7:7] read-write TIMEOUT Mask Time-out Interrupt [8:8] read-write TXEMPTY Mask TXEMPTY Interrupt [9:9] read-write CMP Mask Comparison Interrupt [15:15] read-write MR Mode Register 0x4 0x20 read-write FILTER Receiver Digital Filter [4:4] read-write true DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type [11:9] read-write true EVEN Even Parity 0 ODD Odd Parity 1 SPACE Space: parity forced to 0 2 MARK Mark: parity forced to 1 3 NO No parity 4 BRSRCCK Baud Rate Source Clock [12:12] read-write true PERIPH_CLK The baud rate is driven by the peripheral clock 0 GCLK The baud rate is driven by a PMC-programmable clock GCLK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode [15:14] read-write true NORMAL Normal mode 0 AUTOMATIC Automatic echo 1 LOCAL_LOOPBACK Local loopback 2 REMOTE_LOOPBACK Remote loopback 3 RHR Receive Holding Register 0x18 0x20 read-only RXCHR Received Character [7:0] read-write 0 255 RTOR Receiver Time-out Register 0x28 0x20 read-write TO Time-out Value [7:0] read-write 0 255 SR Status Register 0x14 0x20 read-only RXRDY Receiver Ready [0:0] read-write TXRDY Transmitter Ready [1:1] read-write OVRE Overrun Error [5:5] read-write FRAME Framing Error [6:6] read-write PARE Parity Error [7:7] read-write TIMEOUT Receiver Time-out [8:8] read-write TXEMPTY Transmitter Empty [9:9] read-write CMP Comparison Match [15:15] read-write SWES SleepWalking Enable Status [21:21] read-write CLKREQ Clock Request [22:22] read-write WKUPREQ Wake-Up Request [23:23] read-write THR Transmit Holding Register 0x1C 0x20 write-only TXCHR Character to be Transmitted [7:0] read-write 0 255 WPMR Write Protection Mode Register 0xE4 0x20 read-write WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 5587282 UART1 Universal Asynchronous Receiver Transmitter 0xF8020000 UART2 Universal Asynchronous Receiver Transmitter 0xF8024000 UART3 Universal Asynchronous Receiver Transmitter 0xFC008000 UART4 Universal Asynchronous Receiver Transmitter 0xFC00C000 UDPHS USB High Speed Device Port 0xFC02C000 0x0 0x8 registers 0x10 0x10 registers 0xE0 0x4 registers 0xEC 0x8 registers 0xF8 0x4 registers ADDRSIZE UDPHS IP Address Size Register 0xEC 0x20 read-only ADDRSIZE Peripheral Bus Address Size [31:0] read-write 0 4294967295 CLRINT UDPHS Clear Interrupt Register 0x18 0x20 write-only DET_SUSPD Suspend Interrupt Clear [1:1] read-write MICRO_SOF Micro Start Of Frame Interrupt Clear [2:2] read-write INT_SOF Start Of Frame Interrupt Clear [3:3] read-write ENDRESET End Of Reset Interrupt Clear [4:4] read-write WAKE_UP Wake Up CPU Interrupt Clear [5:5] read-write ENDOFRSM End Of Resume Interrupt Clear [6:6] read-write UPSTR_RES Upstream Resume Interrupt Clear [7:7] read-write CTRL UDPHS Control Register 0x0 0x20 read-write DEV_ADDR UDPHS Address (cleared upon USB reset) [6:0] read-write 0 127 FADDR_EN Function Address Enable (cleared upon USB reset) [7:7] read-write EN_UDPHS UDPHS Enable [8:8] read-write DETACH Detach Command [9:9] read-write REWAKEUP Send Remote Wakeup (cleared upon USB reset) [10:10] read-write PULLD_DIS Pulldown Disable (cleared upon USB reset) [11:11] read-write EPTRST UDPHS Endpoints Reset Register 0x1C 0x20 write-only EPT_0 Endpoint 0 Reset [0:0] read-write EPT_1 Endpoint 1 Reset [1:1] read-write EPT_2 Endpoint 2 Reset [2:2] read-write EPT_3 Endpoint 3 Reset [3:3] read-write EPT_4 Endpoint 4 Reset [4:4] read-write EPT_5 Endpoint 5 Reset [5:5] read-write EPT_6 Endpoint 6 Reset [6:6] read-write EPT_7 Endpoint 7 Reset [7:7] read-write EPT_8 Endpoint 8 Reset [8:8] read-write EPT_9 Endpoint 9 Reset [9:9] read-write EPT_10 Endpoint 10 Reset [10:10] read-write EPT_11 Endpoint 11 Reset [11:11] read-write EPT_12 Endpoint 12 Reset [12:12] read-write EPT_13 Endpoint 13 Reset [13:13] read-write EPT_14 Endpoint 14 Reset [14:14] read-write EPT_15 Endpoint 15 Reset [15:15] read-write FEATURES UDPHS Features Register 0xF8 0x20 read-only 0 4294967295 FNUM UDPHS Frame Number Register 0x4 0x20 read-only MICRO_FRAME_NUM Microframe Number (cleared upon USB reset) [2:0] read-write 0 7 FRAME_NUMBER Frame Number as defined in the Packet Field Formats (cleared upon USB reset) [13:3] read-write 0 2047 FNUM_ERR Frame Number CRC Error (cleared upon USB reset) [31:31] read-write IEN UDPHS Interrupt Enable Register 0x10 0x20 read-write DET_SUSPD Suspend Interrupt Enable (cleared upon USB reset) [1:1] read-write MICRO_SOF Micro-SOF Interrupt Enable (cleared upon USB reset) [2:2] read-write INT_SOF SOF Interrupt Enable (cleared upon USB reset) [3:3] read-write ENDRESET End Of Reset Interrupt Enable (cleared upon USB reset) [4:4] read-write WAKE_UP Wake Up CPU Interrupt Enable (cleared upon USB reset) [5:5] read-write ENDOFRSM End Of Resume Interrupt Enable (cleared upon USB reset) [6:6] read-write UPSTR_RES Upstream Resume Interrupt Enable (cleared upon USB reset) [7:7] read-write EPT_0 Endpoint 0 Interrupt Enable (cleared upon USB reset) [8:8] read-write EPT_1 Endpoint 1 Interrupt Enable (cleared upon USB reset) [9:9] read-write EPT_2 Endpoint 2 Interrupt Enable (cleared upon USB reset) [10:10] read-write EPT_3 Endpoint 3 Interrupt Enable (cleared upon USB reset) [11:11] read-write EPT_4 Endpoint 4 Interrupt Enable (cleared upon USB reset) [12:12] read-write EPT_5 Endpoint 5 Interrupt Enable (cleared upon USB reset) [13:13] read-write EPT_6 Endpoint 6 Interrupt Enable (cleared upon USB reset) [14:14] read-write EPT_7 Endpoint 7 Interrupt Enable (cleared upon USB reset) [15:15] read-write EPT_8 Endpoint 8 Interrupt Enable (cleared upon USB reset) [16:16] read-write EPT_9 Endpoint 9 Interrupt Enable (cleared upon USB reset) [17:17] read-write EPT_10 Endpoint 10 Interrupt Enable (cleared upon USB reset) [18:18] read-write EPT_11 Endpoint 11 Interrupt Enable (cleared upon USB reset) [19:19] read-write EPT_12 Endpoint 12 Interrupt Enable (cleared upon USB reset) [20:20] read-write EPT_13 Endpoint 13 Interrupt Enable (cleared upon USB reset) [21:21] read-write EPT_14 Endpoint 14 Interrupt Enable (cleared upon USB reset) [22:22] read-write EPT_15 Endpoint 15 Interrupt Enable (cleared upon USB reset) [23:23] read-write DMA_1 DMA Channel 1 Interrupt Enable (cleared upon USB reset) [25:25] read-write DMA_2 DMA Channel 2 Interrupt Enable (cleared upon USB reset) [26:26] read-write DMA_3 DMA Channel 3 Interrupt Enable (cleared upon USB reset) [27:27] read-write DMA_4 DMA Channel 4 Interrupt Enable (cleared upon USB reset) [28:28] read-write DMA_5 DMA Channel 5 Interrupt Enable (cleared upon USB reset) [29:29] read-write DMA_6 DMA Channel 6 Interrupt Enable (cleared upon USB reset) [30:30] read-write DMA_7 DMA Channel 7 Interrupt Enable (cleared upon USB reset) [31:31] read-write INTSTA UDPHS Interrupt Status Register 0x14 0x20 read-only SPEED Speed Status [0:0] read-write DET_SUSPD Suspend Interrupt [1:1] read-write MICRO_SOF Micro Start Of Frame Interrupt [2:2] read-write INT_SOF Start Of Frame Interrupt [3:3] read-write ENDRESET End Of Reset Interrupt [4:4] read-write WAKE_UP Wake Up CPU Interrupt [5:5] read-write ENDOFRSM End Of Resume Interrupt [6:6] read-write UPSTR_RES Upstream Resume Interrupt [7:7] read-write EPT_0 Endpoint 0 Interrupt (cleared upon USB reset) [8:8] read-write EPT_1 Endpoint 1 Interrupt (cleared upon USB reset) [9:9] read-write EPT_2 Endpoint 2 Interrupt (cleared upon USB reset) [10:10] read-write EPT_3 Endpoint 3 Interrupt (cleared upon USB reset) [11:11] read-write EPT_4 Endpoint 4 Interrupt (cleared upon USB reset) [12:12] read-write EPT_5 Endpoint 5 Interrupt (cleared upon USB reset) [13:13] read-write EPT_6 Endpoint 6 Interrupt (cleared upon USB reset) [14:14] read-write EPT_7 Endpoint 7 Interrupt (cleared upon USB reset) [15:15] read-write EPT_8 Endpoint 8 Interrupt (cleared upon USB reset) [16:16] read-write EPT_9 Endpoint 9 Interrupt (cleared upon USB reset) [17:17] read-write EPT_10 Endpoint 10 Interrupt (cleared upon USB reset) [18:18] read-write EPT_11 Endpoint 11 Interrupt (cleared upon USB reset) [19:19] read-write EPT_12 Endpoint 12 Interrupt (cleared upon USB reset) [20:20] read-write EPT_13 Endpoint 13 Interrupt (cleared upon USB reset) [21:21] read-write EPT_14 Endpoint 14 Interrupt (cleared upon USB reset) [22:22] read-write EPT_15 Endpoint 15 Interrupt (cleared upon USB reset) [23:23] read-write DMA_1 DMA Channel 1 Interrupt [25:25] read-write DMA_2 DMA Channel 2 Interrupt [26:26] read-write DMA_3 DMA Channel 3 Interrupt [27:27] read-write DMA_4 DMA Channel 4 Interrupt [28:28] read-write DMA_5 DMA Channel 5 Interrupt [29:29] read-write DMA_6 DMA Channel 6 Interrupt [30:30] read-write DMA_7 DMA Channel 7 Interrupt [31:31] read-write IPNAME UDPHS IP Name1 Register 0xF0 0x20 read-only IPNAME IP Name in ASCII Format [31:0] read-write 0 4294967295 TST UDPHS Test Register 0xE0 0x20 read-write SPEED_CFG Speed Configuration [1:0] read-write true NORMAL Normal mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode. 0 HIGH_SPEED Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. 2 FULL_SPEED Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. 3 TST_J Test J Mode [2:2] read-write TST_K Test K Mode [3:3] read-write TST_PKT Test Packet Mode [4:4] read-write OPMODE2 OpMode2 [5:5] read-write WDT Watchdog Timer 0xF8048040 0x0 0xC registers CR Control Register 0x0 0x20 write-only WDRSTT Watchdog Restart [0:0] read-write LOCKMR Lock Mode Register Write Access [4:4] read-write KEY Password [31:24] read-write true PASSWD Writing any other value in this field aborts the write operation. 165 MR Mode Register 0x4 0x20 read-write WDV Watchdog Counter Value [11:0] read-write 0 4095 WDFIEN Watchdog Fault Interrupt Enable [12:12] read-write WDRSTEN Watchdog Reset Enable [13:13] read-write WDDIS Watchdog Disable [15:15] read-write WDD Watchdog Delta Value [27:16] read-write 0 4095 WDDBGHLT Watchdog Debug Halt [28:28] read-write WDIDLEHLT Watchdog Idle Halt [29:29] read-write SR Status Register 0x8 0x20 read-only WDUNF Watchdog Underflow (cleared on read) [0:0] read-write WDERR Watchdog Error (cleared on read) [1:1] read-write XDMAC0 Extensible DMA Controller 0xF0010000 0x0 0x44 registers XDMAC_GCFG Global Configuration Register 0x4 0x20 read-write CGDISREG Configuration Registers Clock Gating Disable [0:0] read-write CGDISPIPE Pipeline Clock Gating Disable [1:1] read-write CGDISFIFO FIFO Clock Gating Disable [2:2] read-write CGDISIF Bus Interface Clock Gating Disable [3:3] read-write BXKBEN Boundary X Kilobyte Enable [8:8] read-write XDMAC_GD Global Channel Disable Register 0x20 0x20 write-only DI0 XDMAC Channel 0 Disable Bit [0:0] read-write DI1 XDMAC Channel 1 Disable Bit [1:1] read-write DI2 XDMAC Channel 2 Disable Bit [2:2] read-write DI3 XDMAC Channel 3 Disable Bit [3:3] read-write DI4 XDMAC Channel 4 Disable Bit [4:4] read-write DI5 XDMAC Channel 5 Disable Bit [5:5] read-write DI6 XDMAC Channel 6 Disable Bit [6:6] read-write DI7 XDMAC Channel 7 Disable Bit [7:7] read-write DI8 XDMAC Channel 8 Disable Bit [8:8] read-write DI9 XDMAC Channel 9 Disable Bit [9:9] read-write DI10 XDMAC Channel 10 Disable Bit [10:10] read-write DI11 XDMAC Channel 11 Disable Bit [11:11] read-write DI12 XDMAC Channel 12 Disable Bit [12:12] read-write DI13 XDMAC Channel 13 Disable Bit [13:13] read-write DI14 XDMAC Channel 14 Disable Bit [14:14] read-write DI15 XDMAC Channel 15 Disable Bit [15:15] read-write XDMAC_GE Global Channel Enable Register 0x1C 0x20 write-only EN0 XDMAC Channel 0 Enable Bit [0:0] read-write EN1 XDMAC Channel 1 Enable Bit [1:1] read-write EN2 XDMAC Channel 2 Enable Bit [2:2] read-write EN3 XDMAC Channel 3 Enable Bit [3:3] read-write EN4 XDMAC Channel 4 Enable Bit [4:4] read-write EN5 XDMAC Channel 5 Enable Bit [5:5] read-write EN6 XDMAC Channel 6 Enable Bit [6:6] read-write EN7 XDMAC Channel 7 Enable Bit [7:7] read-write EN8 XDMAC Channel 8 Enable Bit [8:8] read-write EN9 XDMAC Channel 9 Enable Bit [9:9] read-write EN10 XDMAC Channel 10 Enable Bit [10:10] read-write EN11 XDMAC Channel 11 Enable Bit [11:11] read-write EN12 XDMAC Channel 12 Enable Bit [12:12] read-write EN13 XDMAC Channel 13 Enable Bit [13:13] read-write EN14 XDMAC Channel 14 Enable Bit [14:14] read-write EN15 XDMAC Channel 15 Enable Bit [15:15] read-write XDMAC_GID Global Interrupt Disable Register 0x10 0x20 write-only ID0 XDMAC Channel 0 Interrupt Disable Bit [0:0] read-write ID1 XDMAC Channel 1 Interrupt Disable Bit [1:1] read-write ID2 XDMAC Channel 2 Interrupt Disable Bit [2:2] read-write ID3 XDMAC Channel 3 Interrupt Disable Bit [3:3] read-write ID4 XDMAC Channel 4 Interrupt Disable Bit [4:4] read-write ID5 XDMAC Channel 5 Interrupt Disable Bit [5:5] read-write ID6 XDMAC Channel 6 Interrupt Disable Bit [6:6] read-write ID7 XDMAC Channel 7 Interrupt Disable Bit [7:7] read-write ID8 XDMAC Channel 8 Interrupt Disable Bit [8:8] read-write ID9 XDMAC Channel 9 Interrupt Disable Bit [9:9] read-write ID10 XDMAC Channel 10 Interrupt Disable Bit [10:10] read-write ID11 XDMAC Channel 11 Interrupt Disable Bit [11:11] read-write ID12 XDMAC Channel 12 Interrupt Disable Bit [12:12] read-write ID13 XDMAC Channel 13 Interrupt Disable Bit [13:13] read-write ID14 XDMAC Channel 14 Interrupt Disable Bit [14:14] read-write ID15 XDMAC Channel 15 Interrupt Disable Bit [15:15] read-write XDMAC_GIE Global Interrupt Enable Register 0xC 0x20 write-only IE0 XDMAC Channel 0 Interrupt Enable Bit [0:0] read-write IE1 XDMAC Channel 1 Interrupt Enable Bit [1:1] read-write IE2 XDMAC Channel 2 Interrupt Enable Bit [2:2] read-write IE3 XDMAC Channel 3 Interrupt Enable Bit [3:3] read-write IE4 XDMAC Channel 4 Interrupt Enable Bit [4:4] read-write IE5 XDMAC Channel 5 Interrupt Enable Bit [5:5] read-write IE6 XDMAC Channel 6 Interrupt Enable Bit [6:6] read-write IE7 XDMAC Channel 7 Interrupt Enable Bit [7:7] read-write IE8 XDMAC Channel 8 Interrupt Enable Bit [8:8] read-write IE9 XDMAC Channel 9 Interrupt Enable Bit [9:9] read-write IE10 XDMAC Channel 10 Interrupt Enable Bit [10:10] read-write IE11 XDMAC Channel 11 Interrupt Enable Bit [11:11] read-write IE12 XDMAC Channel 12 Interrupt Enable Bit [12:12] read-write IE13 XDMAC Channel 13 Interrupt Enable Bit [13:13] read-write IE14 XDMAC Channel 14 Interrupt Enable Bit [14:14] read-write IE15 XDMAC Channel 15 Interrupt Enable Bit [15:15] read-write XDMAC_GIM Global Interrupt Mask Register 0x14 0x20 read-only IM0 XDMAC Channel 0 Interrupt Mask Bit [0:0] read-write IM1 XDMAC Channel 1 Interrupt Mask Bit [1:1] read-write IM2 XDMAC Channel 2 Interrupt Mask Bit [2:2] read-write IM3 XDMAC Channel 3 Interrupt Mask Bit [3:3] read-write IM4 XDMAC Channel 4 Interrupt Mask Bit [4:4] read-write IM5 XDMAC Channel 5 Interrupt Mask Bit [5:5] read-write IM6 XDMAC Channel 6 Interrupt Mask Bit [6:6] read-write IM7 XDMAC Channel 7 Interrupt Mask Bit [7:7] read-write IM8 XDMAC Channel 8 Interrupt Mask Bit [8:8] read-write IM9 XDMAC Channel 9 Interrupt Mask Bit [9:9] read-write IM10 XDMAC Channel 10 Interrupt Mask Bit [10:10] read-write IM11 XDMAC Channel 11 Interrupt Mask Bit [11:11] read-write IM12 XDMAC Channel 12 Interrupt Mask Bit [12:12] read-write IM13 XDMAC Channel 13 Interrupt Mask Bit [13:13] read-write IM14 XDMAC Channel 14 Interrupt Mask Bit [14:14] read-write IM15 XDMAC Channel 15 Interrupt Mask Bit [15:15] read-write XDMAC_GIS Global Interrupt Status Register 0x18 0x20 read-only IS0 XDMAC Channel 0 Interrupt Status Bit [0:0] read-write IS1 XDMAC Channel 1 Interrupt Status Bit [1:1] read-write IS2 XDMAC Channel 2 Interrupt Status Bit [2:2] read-write IS3 XDMAC Channel 3 Interrupt Status Bit [3:3] read-write IS4 XDMAC Channel 4 Interrupt Status Bit [4:4] read-write IS5 XDMAC Channel 5 Interrupt Status Bit [5:5] read-write IS6 XDMAC Channel 6 Interrupt Status Bit [6:6] read-write IS7 XDMAC Channel 7 Interrupt Status Bit [7:7] read-write IS8 XDMAC Channel 8 Interrupt Status Bit [8:8] read-write IS9 XDMAC Channel 9 Interrupt Status Bit [9:9] read-write IS10 XDMAC Channel 10 Interrupt Status Bit [10:10] read-write IS11 XDMAC Channel 11 Interrupt Status Bit [11:11] read-write IS12 XDMAC Channel 12 Interrupt Status Bit [12:12] read-write IS13 XDMAC Channel 13 Interrupt Status Bit [13:13] read-write IS14 XDMAC Channel 14 Interrupt Status Bit [14:14] read-write IS15 XDMAC Channel 15 Interrupt Status Bit [15:15] read-write XDMAC_GRS Global Channel Read Suspend Register 0x28 0x20 read-write RS0 XDMAC Channel 0 Read Suspend Bit [0:0] read-write RS1 XDMAC Channel 1 Read Suspend Bit [1:1] read-write RS2 XDMAC Channel 2 Read Suspend Bit [2:2] read-write RS3 XDMAC Channel 3 Read Suspend Bit [3:3] read-write RS4 XDMAC Channel 4 Read Suspend Bit [4:4] read-write RS5 XDMAC Channel 5 Read Suspend Bit [5:5] read-write RS6 XDMAC Channel 6 Read Suspend Bit [6:6] read-write RS7 XDMAC Channel 7 Read Suspend Bit [7:7] read-write RS8 XDMAC Channel 8 Read Suspend Bit [8:8] read-write RS9 XDMAC Channel 9 Read Suspend Bit [9:9] read-write RS10 XDMAC Channel 10 Read Suspend Bit [10:10] read-write RS11 XDMAC Channel 11 Read Suspend Bit [11:11] read-write RS12 XDMAC Channel 12 Read Suspend Bit [12:12] read-write RS13 XDMAC Channel 13 Read Suspend Bit [13:13] read-write RS14 XDMAC Channel 14 Read Suspend Bit [14:14] read-write RS15 XDMAC Channel 15 Read Suspend Bit [15:15] read-write XDMAC_GRWR Global Channel Read Write Resume Register 0x34 0x20 write-only RWR0 XDMAC Channel 0 Read Write Resume Bit [0:0] read-write RWR1 XDMAC Channel 1 Read Write Resume Bit [1:1] read-write RWR2 XDMAC Channel 2 Read Write Resume Bit [2:2] read-write RWR3 XDMAC Channel 3 Read Write Resume Bit [3:3] read-write RWR4 XDMAC Channel 4 Read Write Resume Bit [4:4] read-write RWR5 XDMAC Channel 5 Read Write Resume Bit [5:5] read-write RWR6 XDMAC Channel 6 Read Write Resume Bit [6:6] read-write RWR7 XDMAC Channel 7 Read Write Resume Bit [7:7] read-write RWR8 XDMAC Channel 8 Read Write Resume Bit [8:8] read-write RWR9 XDMAC Channel 9 Read Write Resume Bit [9:9] read-write RWR10 XDMAC Channel 10 Read Write Resume Bit [10:10] read-write RWR11 XDMAC Channel 11 Read Write Resume Bit [11:11] read-write RWR12 XDMAC Channel 12 Read Write Resume Bit [12:12] read-write RWR13 XDMAC Channel 13 Read Write Resume Bit [13:13] read-write RWR14 XDMAC Channel 14 Read Write Resume Bit [14:14] read-write RWR15 XDMAC Channel 15 Read Write Resume Bit [15:15] read-write XDMAC_GRWS Global Channel Read Write Suspend Register 0x30 0x20 write-only RWS0 XDMAC Channel 0 Read Write Suspend Bit [0:0] read-write RWS1 XDMAC Channel 1 Read Write Suspend Bit [1:1] read-write RWS2 XDMAC Channel 2 Read Write Suspend Bit [2:2] read-write RWS3 XDMAC Channel 3 Read Write Suspend Bit [3:3] read-write RWS4 XDMAC Channel 4 Read Write Suspend Bit [4:4] read-write RWS5 XDMAC Channel 5 Read Write Suspend Bit [5:5] read-write RWS6 XDMAC Channel 6 Read Write Suspend Bit [6:6] read-write RWS7 XDMAC Channel 7 Read Write Suspend Bit [7:7] read-write RWS8 XDMAC Channel 8 Read Write Suspend Bit [8:8] read-write RWS9 XDMAC Channel 9 Read Write Suspend Bit [9:9] read-write RWS10 XDMAC Channel 10 Read Write Suspend Bit [10:10] read-write RWS11 XDMAC Channel 11 Read Write Suspend Bit [11:11] read-write RWS12 XDMAC Channel 12 Read Write Suspend Bit [12:12] read-write RWS13 XDMAC Channel 13 Read Write Suspend Bit [13:13] read-write RWS14 XDMAC Channel 14 Read Write Suspend Bit [14:14] read-write RWS15 XDMAC Channel 15 Read Write Suspend Bit [15:15] read-write XDMAC_GS Global Channel Status Register 0x24 0x20 read-only ST0 XDMAC Channel 0 Status Bit [0:0] read-write ST1 XDMAC Channel 1 Status Bit [1:1] read-write ST2 XDMAC Channel 2 Status Bit [2:2] read-write ST3 XDMAC Channel 3 Status Bit [3:3] read-write ST4 XDMAC Channel 4 Status Bit [4:4] read-write ST5 XDMAC Channel 5 Status Bit [5:5] read-write ST6 XDMAC Channel 6 Status Bit [6:6] read-write ST7 XDMAC Channel 7 Status Bit [7:7] read-write ST8 XDMAC Channel 8 Status Bit [8:8] read-write ST9 XDMAC Channel 9 Status Bit [9:9] read-write ST10 XDMAC Channel 10 Status Bit [10:10] read-write ST11 XDMAC Channel 11 Status Bit [11:11] read-write ST12 XDMAC Channel 12 Status Bit [12:12] read-write ST13 XDMAC Channel 13 Status Bit [13:13] read-write ST14 XDMAC Channel 14 Status Bit [14:14] read-write ST15 XDMAC Channel 15 Status Bit [15:15] read-write XDMAC_GSWF Global Channel Software Flush Request Register 0x40 0x20 write-only SWF0 XDMAC Channel 0 Software Flush Request Bit [0:0] read-write SWF1 XDMAC Channel 1 Software Flush Request Bit [1:1] read-write SWF2 XDMAC Channel 2 Software Flush Request Bit [2:2] read-write SWF3 XDMAC Channel 3 Software Flush Request Bit [3:3] read-write SWF4 XDMAC Channel 4 Software Flush Request Bit [4:4] read-write SWF5 XDMAC Channel 5 Software Flush Request Bit [5:5] read-write SWF6 XDMAC Channel 6 Software Flush Request Bit [6:6] read-write SWF7 XDMAC Channel 7 Software Flush Request Bit [7:7] read-write SWF8 XDMAC Channel 8 Software Flush Request Bit [8:8] read-write SWF9 XDMAC Channel 9 Software Flush Request Bit [9:9] read-write SWF10 XDMAC Channel 10 Software Flush Request Bit [10:10] read-write SWF11 XDMAC Channel 11 Software Flush Request Bit [11:11] read-write SWF12 XDMAC Channel 12 Software Flush Request Bit [12:12] read-write SWF13 XDMAC Channel 13 Software Flush Request Bit [13:13] read-write SWF14 XDMAC Channel 14 Software Flush Request Bit [14:14] read-write SWF15 XDMAC Channel 15 Software Flush Request Bit [15:15] read-write XDMAC_GSWR Global Channel Software Request Register 0x38 0x20 write-only SWREQ0 XDMAC Channel 0 Software Request Bit [0:0] read-write SWREQ1 XDMAC Channel 1 Software Request Bit [1:1] read-write SWREQ2 XDMAC Channel 2 Software Request Bit [2:2] read-write SWREQ3 XDMAC Channel 3 Software Request Bit [3:3] read-write SWREQ4 XDMAC Channel 4 Software Request Bit [4:4] read-write SWREQ5 XDMAC Channel 5 Software Request Bit [5:5] read-write SWREQ6 XDMAC Channel 6 Software Request Bit [6:6] read-write SWREQ7 XDMAC Channel 7 Software Request Bit [7:7] read-write SWREQ8 XDMAC Channel 8 Software Request Bit [8:8] read-write SWREQ9 XDMAC Channel 9 Software Request Bit [9:9] read-write SWREQ10 XDMAC Channel 10 Software Request Bit [10:10] read-write SWREQ11 XDMAC Channel 11 Software Request Bit [11:11] read-write SWREQ12 XDMAC Channel 12 Software Request Bit [12:12] read-write SWREQ13 XDMAC Channel 13 Software Request Bit [13:13] read-write SWREQ14 XDMAC Channel 14 Software Request Bit [14:14] read-write SWREQ15 XDMAC Channel 15 Software Request Bit [15:15] read-write XDMAC_GSWS Global Channel Software Request Status Register 0x3C 0x20 read-only SWRS0 XDMAC Channel 0 Software Request Status Bit [0:0] read-write SWRS1 XDMAC Channel 1 Software Request Status Bit [1:1] read-write SWRS2 XDMAC Channel 2 Software Request Status Bit [2:2] read-write SWRS3 XDMAC Channel 3 Software Request Status Bit [3:3] read-write SWRS4 XDMAC Channel 4 Software Request Status Bit [4:4] read-write SWRS5 XDMAC Channel 5 Software Request Status Bit [5:5] read-write SWRS6 XDMAC Channel 6 Software Request Status Bit [6:6] read-write SWRS7 XDMAC Channel 7 Software Request Status Bit [7:7] read-write SWRS8 XDMAC Channel 8 Software Request Status Bit [8:8] read-write SWRS9 XDMAC Channel 9 Software Request Status Bit [9:9] read-write SWRS10 XDMAC Channel 10 Software Request Status Bit [10:10] read-write SWRS11 XDMAC Channel 11 Software Request Status Bit [11:11] read-write SWRS12 XDMAC Channel 12 Software Request Status Bit [12:12] read-write SWRS13 XDMAC Channel 13 Software Request Status Bit [13:13] read-write SWRS14 XDMAC Channel 14 Software Request Status Bit [14:14] read-write SWRS15 XDMAC Channel 15 Software Request Status Bit [15:15] read-write XDMAC_GTYPE Global Type Register 0x0 0x20 read-only NB_CH Number of Channels Minus One [4:0] read-write 0 31 FIFO_SZ Number of Bytes [15:5] read-write 0 2047 NB_REQ Number of Peripheral Requests Minus One [22:16] read-write 0 127 XDMAC_GWAC Global Weighted Arbiter Configuration Register 0x8 0x20 read-write PW0 Pool Weight 0 [3:0] read-write 0 15 PW1 Pool Weight 1 [7:4] read-write 0 15 PW2 Pool Weight 2 [11:8] read-write 0 15 PW3 Pool Weight 3 [15:12] read-write 0 15 XDMAC_GWS Global Channel Write Suspend Register 0x2C 0x20 read-write WS0 XDMAC Channel 0 Write Suspend Bit [0:0] read-write WS1 XDMAC Channel 1 Write Suspend Bit [1:1] read-write WS2 XDMAC Channel 2 Write Suspend Bit [2:2] read-write WS3 XDMAC Channel 3 Write Suspend Bit [3:3] read-write WS4 XDMAC Channel 4 Write Suspend Bit [4:4] read-write WS5 XDMAC Channel 5 Write Suspend Bit [5:5] read-write WS6 XDMAC Channel 6 Write Suspend Bit [6:6] read-write WS7 XDMAC Channel 7 Write Suspend Bit [7:7] read-write WS8 XDMAC Channel 8 Write Suspend Bit [8:8] read-write WS9 XDMAC Channel 9 Write Suspend Bit [9:9] read-write WS10 XDMAC Channel 10 Write Suspend Bit [10:10] read-write WS11 XDMAC Channel 11 Write Suspend Bit [11:11] read-write WS12 XDMAC Channel 12 Write Suspend Bit [12:12] read-write WS13 XDMAC Channel 13 Write Suspend Bit [13:13] read-write WS14 XDMAC Channel 14 Write Suspend Bit [14:14] read-write WS15 XDMAC Channel 15 Write Suspend Bit [15:15] read-write XDMAC1 Extensible DMA Controller 0xF0004000 SPIO Parallel Input/Output Controller. 0xFC039000 0x0 0x1000 registers PIO_WPMR PIO Write Protection Mode Register. 0x5E0 0x20 write-only WPEN Write Protection Enable [0:0] read-write WPKEY Write Protection Key [31:8] read-write true PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 5261647 PIO_WPSR Write Protection Status Register. 0x5E4 0x20 read-only WPVS Write Protection Violation Status [0:0] read-write WPVSRC Write Protection Violation Source [23:8] read-write 0 65535 PIO_MSKR0 PIO Mask Register. 0x000 MSK0 Selects the I/O line 0 to be configured when writing the PIO Configuration Register. 0 1 MSK1 Selects the I/O line 1 to be configured when writing the PIO Configuration Register. 1 1 MSK2 Selects the I/O line 2 to be configured when writing the PIO Configuration Register. 2 1 MSK3 Selects the I/O line 3 to be configured when writing the PIO Configuration Register. 3 1 MSK4 Selects the I/O line 4 to be configured when writing the PIO Configuration Register. 4 1 MSK5 Selects the I/O line 5 to be configured when writing the PIO Configuration Register. 5 1 MSK6 Selects the I/O line 6 to be configured when writing the PIO Configuration Register. 6 1 MSK7 Selects the I/O line 7 to be configured when writing the PIO Configuration Register. 7 1 MSK8 Selects the I/O line 8 to be configured when writing the PIO Configuration Register. 8 1 MSK9 Selects the I/O line 9 to be configured when writing the PIO Configuration Register. 9 1 MSK10 Selects the I/O line 10 to be configured when writing the PIO Configuration Register. 10 1 MSK11 Selects the I/O line 11 to be configured when writing the PIO Configuration Register. 11 1 MSK12 Selects the I/O line 12 to be configured when writing the PIO Configuration Register. 12 1 MSK13 Selects the I/O line 13 to be configured when writing the PIO Configuration Register. 13 1 MSK14 Selects the I/O line 14 to be configured when writing the PIO Configuration Register. 14 1 MSK15 Selects the I/O line 15 to be configured when writing the PIO Configuration Register. 15 1 MSK16 Selects the I/O line 16 to be configured when writing the PIO Configuration Register. 16 1 MSK17 Selects the I/O line 17 to be configured when writing the PIO Configuration Register. 17 1 MSK18 Selects the I/O line 18 to be configured when writing the PIO Configuration Register. 18 1 MSK19 Selects the I/O line 19 to be configured when writing the PIO Configuration Register. 19 1 MSK20 Selects the I/O line 20 to be configured when writing the PIO Configuration Register. 20 1 MSK21 Selects the I/O line 21 to be configured when writing the PIO Configuration Register. 21 1 MSK22 Selects the I/O line 22 to be configured when writing the PIO Configuration Register. 22 1 MSK23 Selects the I/O line 23 to be configured when writing the PIO Configuration Register. 23 1 MSK24 Selects the I/O line 24 to be configured when writing the PIO Configuration Register. 24 1 MSK25 Selects the I/O line 25 to be configured when writing the PIO Configuration Register. 25 1 MSK26 Selects the I/O line 26 to be configured when writing the PIO Configuration Register. 26 1 MSK27 Selects the I/O line 27 to be configured when writing the PIO Configuration Register. 27 1 MSK28 Selects the I/O line 28 to be configured when writing the PIO Configuration Register. 28 1 MSK29 Selects the I/O line 29 to be configured when writing the PIO Configuration Register. 29 1 MSK30 Selects the I/O line 30 to be configured when writing the PIO Configuration Register. 30 1 PIO_MSKR1 PIO Mask Register. 0x040 MSK0 Selects the I/O line 0 to be configured when writing the PIO Configuration Register. 0 1 MSK1 Selects the I/O line 1 to be configured when writing the PIO Configuration Register. 1 1 MSK2 Selects the I/O line 2 to be configured when writing the PIO Configuration Register. 2 1 MSK3 Selects the I/O line 3 to be configured when writing the PIO Configuration Register. 3 1 MSK4 Selects the I/O line 4 to be configured when writing the PIO Configuration Register. 4 1 MSK5 Selects the I/O line 5 to be configured when writing the PIO Configuration Register. 5 1 MSK6 Selects the I/O line 6 to be configured when writing the PIO Configuration Register. 6 1 MSK7 Selects the I/O line 7 to be configured when writing the PIO Configuration Register. 7 1 MSK8 Selects the I/O line 8 to be configured when writing the PIO Configuration Register. 8 1 MSK9 Selects the I/O line 9 to be configured when writing the PIO Configuration Register. 9 1 MSK10 Selects the I/O line 10 to be configured when writing the PIO Configuration Register. 10 1 MSK11 Selects the I/O line 11 to be configured when writing the PIO Configuration Register. 11 1 MSK12 Selects the I/O line 12 to be configured when writing the PIO Configuration Register. 12 1 MSK13 Selects the I/O line 13 to be configured when writing the PIO Configuration Register. 13 1 MSK14 Selects the I/O line 14 to be configured when writing the PIO Configuration Register. 14 1 MSK15 Selects the I/O line 15 to be configured when writing the PIO Configuration Register. 15 1 MSK16 Selects the I/O line 16 to be configured when writing the PIO Configuration Register. 16 1 MSK17 Selects the I/O line 17 to be configured when writing the PIO Configuration Register. 17 1 MSK18 Selects the I/O line 18 to be configured when writing the PIO Configuration Register. 18 1 MSK19 Selects the I/O line 19 to be configured when writing the PIO Configuration Register. 19 1 MSK20 Selects the I/O line 20 to be configured when writing the PIO Configuration Register. 20 1 MSK21 Selects the I/O line 21 to be configured when writing the PIO Configuration Register. 21 1 MSK22 Selects the I/O line 22 to be configured when writing the PIO Configuration Register. 22 1 MSK23 Selects the I/O line 23 to be configured when writing the PIO Configuration Register. 23 1 MSK24 Selects the I/O line 24 to be configured when writing the PIO Configuration Register. 24 1 MSK25 Selects the I/O line 25 to be configured when writing the PIO Configuration Register. 25 1 MSK26 Selects the I/O line 26 to be configured when writing the PIO Configuration Register. 26 1 MSK27 Selects the I/O line 27 to be configured when writing the PIO Configuration Register. 27 1 MSK28 Selects the I/O line 28 to be configured when writing the PIO Configuration Register. 28 1 MSK29 Selects the I/O line 29 to be configured when writing the PIO Configuration Register. 29 1 MSK30 Selects the I/O line 30 to be configured when writing the PIO Configuration Register. 30 1 PIO_MSKR2 PIO Mask Register. 0x080 MSK0 Selects the I/O line 0 to be configured when writing the PIO Configuration Register. 0 1 MSK1 Selects the I/O line 1 to be configured when writing the PIO Configuration Register. 1 1 MSK2 Selects the I/O line 2 to be configured when writing the PIO Configuration Register. 2 1 MSK3 Selects the I/O line 3 to be configured when writing the PIO Configuration Register. 3 1 MSK4 Selects the I/O line 4 to be configured when writing the PIO Configuration Register. 4 1 MSK5 Selects the I/O line 5 to be configured when writing the PIO Configuration Register. 5 1 MSK6 Selects the I/O line 6 to be configured when writing the PIO Configuration Register. 6 1 MSK7 Selects the I/O line 7 to be configured when writing the PIO Configuration Register. 7 1 MSK8 Selects the I/O line 8 to be configured when writing the PIO Configuration Register. 8 1 MSK9 Selects the I/O line 9 to be configured when writing the PIO Configuration Register. 9 1 MSK10 Selects the I/O line 10 to be configured when writing the PIO Configuration Register. 10 1 MSK11 Selects the I/O line 11 to be configured when writing the PIO Configuration Register. 11 1 MSK12 Selects the I/O line 12 to be configured when writing the PIO Configuration Register. 12 1 MSK13 Selects the I/O line 13 to be configured when writing the PIO Configuration Register. 13 1 MSK14 Selects the I/O line 14 to be configured when writing the PIO Configuration Register. 14 1 MSK15 Selects the I/O line 15 to be configured when writing the PIO Configuration Register. 15 1 MSK16 Selects the I/O line 16 to be configured when writing the PIO Configuration Register. 16 1 MSK17 Selects the I/O line 17 to be configured when writing the PIO Configuration Register. 17 1 MSK18 Selects the I/O line 18 to be configured when writing the PIO Configuration Register. 18 1 MSK19 Selects the I/O line 19 to be configured when writing the PIO Configuration Register. 19 1 MSK20 Selects the I/O line 20 to be configured when writing the PIO Configuration Register. 20 1 MSK21 Selects the I/O line 21 to be configured when writing the PIO Configuration Register. 21 1 MSK22 Selects the I/O line 22 to be configured when writing the PIO Configuration Register. 22 1 MSK23 Selects the I/O line 23 to be configured when writing the PIO Configuration Register. 23 1 MSK24 Selects the I/O line 24 to be configured when writing the PIO Configuration Register. 24 1 MSK25 Selects the I/O line 25 to be configured when writing the PIO Configuration Register. 25 1 MSK26 Selects the I/O line 26 to be configured when writing the PIO Configuration Register. 26 1 MSK27 Selects the I/O line 27 to be configured when writing the PIO Configuration Register. 27 1 MSK28 Selects the I/O line 28 to be configured when writing the PIO Configuration Register. 28 1 MSK29 Selects the I/O line 29 to be configured when writing the PIO Configuration Register. 29 1 MSK30 Selects the I/O line 30 to be configured when writing the PIO Configuration Register. 30 1 PIO_MSKR3 PIO Mask Register. 0x0C0 MSK0 Selects the I/O line 0 to be configured when writing the PIO Configuration Register. 0 1 MSK1 Selects the I/O line 1 to be configured when writing the PIO Configuration Register. 1 1 MSK2 Selects the I/O line 2 to be configured when writing the PIO Configuration Register. 2 1 MSK3 Selects the I/O line 3 to be configured when writing the PIO Configuration Register. 3 1 MSK4 Selects the I/O line 4 to be configured when writing the PIO Configuration Register. 4 1 MSK5 Selects the I/O line 5 to be configured when writing the PIO Configuration Register. 5 1 MSK6 Selects the I/O line 6 to be configured when writing the PIO Configuration Register. 6 1 MSK7 Selects the I/O line 7 to be configured when writing the PIO Configuration Register. 7 1 MSK8 Selects the I/O line 8 to be configured when writing the PIO Configuration Register. 8 1 MSK9 Selects the I/O line 9 to be configured when writing the PIO Configuration Register. 9 1 MSK10 Selects the I/O line 10 to be configured when writing the PIO Configuration Register. 10 1 MSK11 Selects the I/O line 11 to be configured when writing the PIO Configuration Register. 11 1 MSK12 Selects the I/O line 12 to be configured when writing the PIO Configuration Register. 12 1 MSK13 Selects the I/O line 13 to be configured when writing the PIO Configuration Register. 13 1 MSK14 Selects the I/O line 14 to be configured when writing the PIO Configuration Register. 14 1 MSK15 Selects the I/O line 15 to be configured when writing the PIO Configuration Register. 15 1 MSK16 Selects the I/O line 16 to be configured when writing the PIO Configuration Register. 16 1 MSK17 Selects the I/O line 17 to be configured when writing the PIO Configuration Register. 17 1 MSK18 Selects the I/O line 18 to be configured when writing the PIO Configuration Register. 18 1 MSK19 Selects the I/O line 19 to be configured when writing the PIO Configuration Register. 19 1 MSK20 Selects the I/O line 20 to be configured when writing the PIO Configuration Register. 20 1 MSK21 Selects the I/O line 21 to be configured when writing the PIO Configuration Register. 21 1 MSK22 Selects the I/O line 22 to be configured when writing the PIO Configuration Register. 22 1 MSK23 Selects the I/O line 23 to be configured when writing the PIO Configuration Register. 23 1 MSK24 Selects the I/O line 24 to be configured when writing the PIO Configuration Register. 24 1 MSK25 Selects the I/O line 25 to be configured when writing the PIO Configuration Register. 25 1 MSK26 Selects the I/O line 26 to be configured when writing the PIO Configuration Register. 26 1 MSK27 Selects the I/O line 27 to be configured when writing the PIO Configuration Register. 27 1 MSK28 Selects the I/O line 28 to be configured when writing the PIO Configuration Register. 28 1 MSK29 Selects the I/O line 29 to be configured when writing the PIO Configuration Register. 29 1 MSK30 Selects the I/O line 30 to be configured when writing the PIO Configuration Register. 30 1 PIO_CFGR0 PIO Configuration Register. 0x004 0x20 read-write ICFS Interrupt Configuration Freeze Status. 30 1 read-only PCFS Physical Configuration Freeze Status. 29 1 read-only EVTSEL Event Selection. 24 3 EVTSEL read-write FALLING Event detection on input falling edge. 0 RISING Event detection on input rising edge. 1 BOTH Event detection on input both edge. 2 LOW Event detection on low level input. 3 HIGH Event detection on high level input. 4 DRVSTR Drive Strength. 16 2 DRVSTR read-write LO0 Low drive. 0 LO1 Low drive. 1 ME Medium drive. 2 HI Medium drive. 3 SCHMITT Schmitt Trigger. 15 1 SCHMITT read-write ENABLED Schmitt trigger is enabled for the selected I/O lines. 0 DISABLED Schmitt trigger is disabled for the selected I/O lines. 1 OPD Open Drain. 14 1 OPD read-write DISABLED Open drain is disabled for the selected I/O lines. 0 ENABLED Open drain is enabled for the selected I/O lines. 1 IFSCEN Input Filter Slow Clock Enable. 13 1 IFSCEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 IFEN Input Filter Enable. 12 1 IFEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 PDEN Pull-Down Enable. 10 1 PDEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 PUEN Pull-Up Enable. 9 1 PUEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 DIR Direction. 8 1 DIR read-write INPUT The selected I/O lines are pure inputs. 0 OUTPUT The selected I/O lines are enabled in output. 1 FUNC I/O Line Function. 0 3 FUNC read-write GPIO Selects GPIO mode for the selected I/O lines. 0 PERIPH_A Selects peripheral A for the selected I/O lines. 1 PERIPH_B Selects peripheral B for the selected I/O lines. 2 PERIPH_C Selects peripheral C for the selected I/O lines. 3 PERIPH_D Selects peripheral D for the selected I/O lines. 4 PERIPH_E Selects peripheral E for the selected I/O lines. 5 PERIPH_F Selects peripheral F for the selected I/O lines. 6 PIO_CFGR1 PIO Configuration Register. 0x044 0x20 read-write ICFS Interrupt Configuration Freeze Status. 30 1 read-only PCFS Physical Configuration Freeze Status. 29 1 read-only EVTSEL Event Selection. 24 3 EVTSEL read-write FALLING Event detection on input falling edge. 0 RISING Event detection on input rising edge. 1 BOTH Event detection on input both edge. 2 LOW Event detection on low level input. 3 HIGH Event detection on high level input. 4 DRVSTR Drive Strength. 16 2 DRVSTR read-write LO0 Low drive. 0 LO1 Low drive. 1 ME Medium drive. 2 HI Medium drive. 3 SCHMITT Schmitt Trigger. 15 1 SCHMITT read-write ENABLED Schmitt trigger is enabled for the selected I/O lines. 0 DISABLED Schmitt trigger is disabled for the selected I/O lines. 1 OPD Open Drain. 14 1 OPD read-write DISABLED Open drain is disabled for the selected I/O lines. 0 ENABLED Open drain is enabled for the selected I/O lines. 1 IFSCEN Input Filter Slow Clock Enable. 13 1 IFSCEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 IFEN Input Filter Enable. 12 1 IFEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 PDEN Pull-Down Enable. 10 1 PDEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 PUEN Pull-Up Enable. 9 1 PUEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 DIR Direction. 8 1 DIR read-write INPUT The selected I/O lines are pure inputs. 0 OUTPUT The selected I/O lines are enabled in output. 1 FUNC I/O Line Function. 0 3 FUNC read-write GPIO Selects GPIO mode for the selected I/O lines. 0 PERIPH_A Selects peripheral A for the selected I/O lines. 1 PERIPH_B Selects peripheral B for the selected I/O lines. 2 PERIPH_C Selects peripheral C for the selected I/O lines. 3 PERIPH_D Selects peripheral D for the selected I/O lines. 4 PERIPH_E Selects peripheral E for the selected I/O lines. 5 PERIPH_F Selects peripheral F for the selected I/O lines. 6 PIO_CFGR2 PIO Configuration Register. 0x084 0x20 read-write ICFS Interrupt Configuration Freeze Status. 30 1 read-only PCFS Physical Configuration Freeze Status. 29 1 read-only EVTSEL Event Selection. 24 3 EVTSEL read-write FALLING Event detection on input falling edge. 0 RISING Event detection on input rising edge. 1 BOTH Event detection on input both edge. 2 LOW Event detection on low level input. 3 HIGH Event detection on high level input. 4 DRVSTR Drive Strength. 16 2 DRVSTR read-write LO0 Low drive. 0 LO1 Low drive. 1 ME Medium drive. 2 HI Medium drive. 3 SCHMITT Schmitt Trigger. 15 1 SCHMITT read-write ENABLED Schmitt trigger is enabled for the selected I/O lines. 0 DISABLED Schmitt trigger is disabled for the selected I/O lines. 1 OPD Open Drain. 14 1 OPD read-write DISABLED Open drain is disabled for the selected I/O lines. 0 ENABLED Open drain is enabled for the selected I/O lines. 1 IFSCEN Input Filter Slow Clock Enable. 13 1 IFSCEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 IFEN Input Filter Enable. 12 1 IFEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 PDEN Pull-Down Enable. 10 1 PDEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 PUEN Pull-Up Enable. 9 1 PUEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 DIR Direction. 8 1 DIR read-write INPUT The selected I/O lines are pure inputs. 0 OUTPUT The selected I/O lines are enabled in output. 1 FUNC I/O Line Function. 0 3 FUNC read-write GPIO Selects GPIO mode for the selected I/O lines. 0 PERIPH_A Selects peripheral A for the selected I/O lines. 1 PERIPH_B Selects peripheral B for the selected I/O lines. 2 PERIPH_C Selects peripheral C for the selected I/O lines. 3 PERIPH_D Selects peripheral D for the selected I/O lines. 4 PERIPH_E Selects peripheral E for the selected I/O lines. 5 PERIPH_F Selects peripheral F for the selected I/O lines. 6 PIO_CFGR3 PIO Configuration Register. 0x0C4 0x20 read-write ICFS Interrupt Configuration Freeze Status. 30 1 read-only PCFS Physical Configuration Freeze Status. 29 1 read-only EVTSEL Event Selection. 24 3 EVTSEL read-write FALLING Event detection on input falling edge. 0 RISING Event detection on input rising edge. 1 BOTH Event detection on input both edge. 2 LOW Event detection on low level input. 3 HIGH Event detection on high level input. 4 DRVSTR Drive Strength. 16 2 DRVSTR read-write LO0 Low drive. 0 LO1 Low drive. 1 ME Medium drive. 2 HI Medium drive. 3 SCHMITT Schmitt Trigger. 15 1 SCHMITT read-write ENABLED Schmitt trigger is enabled for the selected I/O lines. 0 DISABLED Schmitt trigger is disabled for the selected I/O lines. 1 OPD Open Drain. 14 1 OPD read-write DISABLED Open drain is disabled for the selected I/O lines. 0 ENABLED Open drain is enabled for the selected I/O lines. 1 IFSCEN Input Filter Slow Clock Enable. 13 1 IFSCEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 IFEN Input Filter Enable. 12 1 IFEN read-write DISABLED The input filter is disabled for the selected I/O lines. 0 ENABLED The input filter is enabled for the selected I/O lines. 1 PDEN Pull-Down Enable. 10 1 PDEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 PUEN Pull-Up Enable. 9 1 PUEN read-write DISABLED Pull-Up is disabled for the selected I/O lines. 0 ENABLED Pull-Up is enabled for the selected I/O lines. 1 DIR Direction. 8 1 DIR read-write INPUT The selected I/O lines are pure inputs. 0 OUTPUT The selected I/O lines are enabled in output. 1 FUNC I/O Line Function. 0 3 FUNC read-write GPIO Selects GPIO mode for the selected I/O lines. 0 PERIPH_A Selects peripheral A for the selected I/O lines. 1 PERIPH_B Selects peripheral B for the selected I/O lines. 2 PERIPH_C Selects peripheral C for the selected I/O lines. 3 PERIPH_D Selects peripheral D for the selected I/O lines. 4 PERIPH_E Selects peripheral E for the selected I/O lines. 5 PERIPH_F Selects peripheral F for the selected I/O lines. 6 PIO_PDSR0 PIO Pin Data Status Register. 0x008 P0 The input data status of the I/O line 0. 0 1 P1 The input data status of the I/O line 1. 1 1 P2 The input data status of the I/O line 2. 2 1 P3 The input data status of the I/O line 3. 3 1 P4 The input data status of the I/O line 4. 4 1 P5 The input data status of the I/O line 5. 5 1 P6 The input data status of the I/O line 6. 6 1 P7 The input data status of the I/O line 7. 7 1 P8 The input data status of the I/O line 8. 8 1 P9 The input data status of the I/O line 9. 9 1 P10 The input data status of the I/O line 10. 10 1 P11 The input data status of the I/O line 11. 11 1 P12 The input data status of the I/O line 12. 12 1 P13 The input data status of the I/O line 13. 13 1 P14 The input data status of the I/O line 14. 14 1 P15 The input data status of the I/O line 15. 15 1 P16 The input data status of the I/O line 16. 16 1 P17 The input data status of the I/O line 17. 17 1 P18 The input data status of the I/O line 18. 18 1 P19 The input data status of the I/O line 19. 19 1 P20 The input data status of the I/O line 20. 20 1 P21 The input data status of the I/O line 21. 21 1 P22 The input data status of the I/O line 22. 22 1 P23 The input data status of the I/O line 23. 23 1 P24 The input data status of the I/O line 24. 24 1 P25 The input data status of the I/O line 25. 25 1 P26 The input data status of the I/O line 26. 26 1 P27 The input data status of the I/O line 27. 27 1 P28 The input data status of the I/O line 28. 28 1 P29 The input data status of the I/O line 29. 29 1 P30 The input data status of the I/O line 30. 30 1 P31 The input data status of the I/O line 31. 31 1 PIO_PDSR1 PIO Pin Data Status Register. 0x048 P0 The input data status of the I/O line 0. 0 1 P1 The input data status of the I/O line 1. 1 1 P2 The input data status of the I/O line 2. 2 1 P3 The input data status of the I/O line 3. 3 1 P4 The input data status of the I/O line 4. 4 1 P5 The input data status of the I/O line 5. 5 1 P6 The input data status of the I/O line 6. 6 1 P7 The input data status of the I/O line 7. 7 1 P8 The input data status of the I/O line 8. 8 1 P9 The input data status of the I/O line 9. 9 1 P10 The input data status of the I/O line 10. 10 1 P11 The input data status of the I/O line 11. 11 1 P12 The input data status of the I/O line 12. 12 1 P13 The input data status of the I/O line 13. 13 1 P14 The input data status of the I/O line 14. 14 1 P15 The input data status of the I/O line 15. 15 1 P16 The input data status of the I/O line 16. 16 1 P17 The input data status of the I/O line 17. 17 1 P18 The input data status of the I/O line 18. 18 1 P19 The input data status of the I/O line 19. 19 1 P20 The input data status of the I/O line 20. 20 1 P21 The input data status of the I/O line 21. 21 1 P22 The input data status of the I/O line 22. 22 1 P23 The input data status of the I/O line 23. 23 1 P24 The input data status of the I/O line 24. 24 1 P25 The input data status of the I/O line 25. 25 1 P26 The input data status of the I/O line 26. 26 1 P27 The input data status of the I/O line 27. 27 1 P28 The input data status of the I/O line 28. 28 1 P29 The input data status of the I/O line 29. 29 1 P30 The input data status of the I/O line 30. 30 1 P31 The input data status of the I/O line 31. 31 1 PIO_PDSR2 PIO Pin Data Status Register. 0x088 P0 The input data status of the I/O line 0. 0 1 P1 The input data status of the I/O line 1. 1 1 P2 The input data status of the I/O line 2. 2 1 P3 The input data status of the I/O line 3. 3 1 P4 The input data status of the I/O line 4. 4 1 P5 The input data status of the I/O line 5. 5 1 P6 The input data status of the I/O line 6. 6 1 P7 The input data status of the I/O line 7. 7 1 P8 The input data status of the I/O line 8. 8 1 P9 The input data status of the I/O line 9. 9 1 P10 The input data status of the I/O line 10. 10 1 P11 The input data status of the I/O line 11. 11 1 P12 The input data status of the I/O line 12. 12 1 P13 The input data status of the I/O line 13. 13 1 P14 The input data status of the I/O line 14. 14 1 P15 The input data status of the I/O line 15. 15 1 P16 The input data status of the I/O line 16. 16 1 P17 The input data status of the I/O line 17. 17 1 P18 The input data status of the I/O line 18. 18 1 P19 The input data status of the I/O line 19. 19 1 P20 The input data status of the I/O line 20. 20 1 P21 The input data status of the I/O line 21. 21 1 P22 The input data status of the I/O line 22. 22 1 P23 The input data status of the I/O line 23. 23 1 P24 The input data status of the I/O line 24. 24 1 P25 The input data status of the I/O line 25. 25 1 P26 The input data status of the I/O line 26. 26 1 P27 The input data status of the I/O line 27. 27 1 P28 The input data status of the I/O line 28. 28 1 P29 The input data status of the I/O line 29. 29 1 P30 The input data status of the I/O line 30. 30 1 P31 The input data status of the I/O line 31. 31 1 PIO_PDSR3 PIO Pin Data Status Register. 0x0C8 P0 The input data status of the I/O line 0. 0 1 P1 The input data status of the I/O line 1. 1 1 P2 The input data status of the I/O line 2. 2 1 P3 The input data status of the I/O line 3. 3 1 P4 The input data status of the I/O line 4. 4 1 P5 The input data status of the I/O line 5. 5 1 P6 The input data status of the I/O line 6. 6 1 P7 The input data status of the I/O line 7. 7 1 P8 The input data status of the I/O line 8. 8 1 P9 The input data status of the I/O line 9. 9 1 P10 The input data status of the I/O line 10. 10 1 P11 The input data status of the I/O line 11. 11 1 P12 The input data status of the I/O line 12. 12 1 P13 The input data status of the I/O line 13. 13 1 P14 The input data status of the I/O line 14. 14 1 P15 The input data status of the I/O line 15. 15 1 P16 The input data status of the I/O line 16. 16 1 P17 The input data status of the I/O line 17. 17 1 P18 The input data status of the I/O line 18. 18 1 P19 The input data status of the I/O line 19. 19 1 P20 The input data status of the I/O line 20. 20 1 P21 The input data status of the I/O line 21. 21 1 P22 The input data status of the I/O line 22. 22 1 P23 The input data status of the I/O line 23. 23 1 P24 The input data status of the I/O line 24. 24 1 P25 The input data status of the I/O line 25. 25 1 P26 The input data status of the I/O line 26. 26 1 P27 The input data status of the I/O line 27. 27 1 P28 The input data status of the I/O line 28. 28 1 P29 The input data status of the I/O line 29. 29 1 P30 The input data status of the I/O line 30. 30 1 P31 The input data status of the I/O line 31. 31 1 PIO_LOCKSR0 PIO Lock Status Register. 0x00C P0 The lock status status of the I/O line 0. 0 1 P1 The lock status status of the I/O line 1. 1 1 P2 The lock status status of the I/O line 2. 2 1 P3 The lock status status of the I/O line 3. 3 1 P4 The lock status status of the I/O line 4. 4 1 P5 The lock status status of the I/O line 5. 5 1 P6 The lock status status of the I/O line 6. 6 1 P7 The lock status status of the I/O line 7. 7 1 P8 The lock status status of the I/O line 8. 8 1 P9 The lock status status of the I/O line 9. 9 1 P10 The lock status status of the I/O line 10. 10 1 P11 The lock status status of the I/O line 11. 11 1 P12 The lock status status of the I/O line 12. 12 1 P13 The lock status status of the I/O line 13. 13 1 P14 The lock status status of the I/O line 14. 14 1 P15 The lock status status of the I/O line 15. 15 1 P16 The lock status status of the I/O line 16. 16 1 P17 The lock status status of the I/O line 17. 17 1 P18 The lock status status of the I/O line 18. 18 1 P19 The lock status status of the I/O line 19. 19 1 P20 The lock status status of the I/O line 20. 20 1 P21 The lock status status of the I/O line 21. 21 1 P22 The lock status status of the I/O line 22. 22 1 P23 The lock status status of the I/O line 23. 23 1 P24 The lock status status of the I/O line 24. 24 1 P25 The lock status status of the I/O line 25. 25 1 P26 The lock status status of the I/O line 26. 26 1 P27 The lock status status of the I/O line 27. 27 1 P28 The lock status status of the I/O line 28. 28 1 P29 The lock status status of the I/O line 29. 29 1 P30 The lock status status of the I/O line 30. 30 1 P31 The lock status status of the I/O line 31. 31 1 PIO_LOCKSR1 PIO Lock Status Register. 0x04C P0 The lock status status of the I/O line 0. 0 1 P1 The lock status status of the I/O line 1. 1 1 P2 The lock status status of the I/O line 2. 2 1 P3 The lock status status of the I/O line 3. 3 1 P4 The lock status status of the I/O line 4. 4 1 P5 The lock status status of the I/O line 5. 5 1 P6 The lock status status of the I/O line 6. 6 1 P7 The lock status status of the I/O line 7. 7 1 P8 The lock status status of the I/O line 8. 8 1 P9 The lock status status of the I/O line 9. 9 1 P10 The lock status status of the I/O line 10. 10 1 P11 The lock status status of the I/O line 11. 11 1 P12 The lock status status of the I/O line 12. 12 1 P13 The lock status status of the I/O line 13. 13 1 P14 The lock status status of the I/O line 14. 14 1 P15 The lock status status of the I/O line 15. 15 1 P16 The lock status status of the I/O line 16. 16 1 P17 The lock status status of the I/O line 17. 17 1 P18 The lock status status of the I/O line 18. 18 1 P19 The lock status status of the I/O line 19. 19 1 P20 The lock status status of the I/O line 20. 20 1 P21 The lock status status of the I/O line 21. 21 1 P22 The lock status status of the I/O line 22. 22 1 P23 The lock status status of the I/O line 23. 23 1 P24 The lock status status of the I/O line 24. 24 1 P25 The lock status status of the I/O line 25. 25 1 P26 The lock status status of the I/O line 26. 26 1 P27 The lock status status of the I/O line 27. 27 1 P28 The lock status status of the I/O line 28. 28 1 P29 The lock status status of the I/O line 29. 29 1 P30 The lock status status of the I/O line 30. 30 1 P31 The lock status status of the I/O line 31. 31 1 PIO_LOCKSR2 PIO Lock Status Register. 0x08C P0 The lock status status of the I/O line 0. 0 1 P1 The lock status status of the I/O line 1. 1 1 P2 The lock status status of the I/O line 2. 2 1 P3 The lock status status of the I/O line 3. 3 1 P4 The lock status status of the I/O line 4. 4 1 P5 The lock status status of the I/O line 5. 5 1 P6 The lock status status of the I/O line 6. 6 1 P7 The lock status status of the I/O line 7. 7 1 P8 The lock status status of the I/O line 8. 8 1 P9 The lock status status of the I/O line 9. 9 1 P10 The lock status status of the I/O line 10. 10 1 P11 The lock status status of the I/O line 11. 11 1 P12 The lock status status of the I/O line 12. 12 1 P13 The lock status status of the I/O line 13. 13 1 P14 The lock status status of the I/O line 14. 14 1 P15 The lock status status of the I/O line 15. 15 1 P16 The lock status status of the I/O line 16. 16 1 P17 The lock status status of the I/O line 17. 17 1 P18 The lock status status of the I/O line 18. 18 1 P19 The lock status status of the I/O line 19. 19 1 P20 The lock status status of the I/O line 20. 20 1 P21 The lock status status of the I/O line 21. 21 1 P22 The lock status status of the I/O line 22. 22 1 P23 The lock status status of the I/O line 23. 23 1 P24 The lock status status of the I/O line 24. 24 1 P25 The lock status status of the I/O line 25. 25 1 P26 The lock status status of the I/O line 26. 26 1 P27 The lock status status of the I/O line 27. 27 1 P28 The lock status status of the I/O line 28. 28 1 P29 The lock status status of the I/O line 29. 29 1 P30 The lock status status of the I/O line 30. 30 1 P31 The lock status status of the I/O line 31. 31 1 PIO_LOCKSR3 PIO Lock Status Register. 0x0CC P0 The lock status status of the I/O line 0. 0 1 P1 The lock status status of the I/O line 1. 1 1 P2 The lock status status of the I/O line 2. 2 1 P3 The lock status status of the I/O line 3. 3 1 P4 The lock status status of the I/O line 4. 4 1 P5 The lock status status of the I/O line 5. 5 1 P6 The lock status status of the I/O line 6. 6 1 P7 The lock status status of the I/O line 7. 7 1 P8 The lock status status of the I/O line 8. 8 1 P9 The lock status status of the I/O line 9. 9 1 P10 The lock status status of the I/O line 10. 10 1 P11 The lock status status of the I/O line 11. 11 1 P12 The lock status status of the I/O line 12. 12 1 P13 The lock status status of the I/O line 13. 13 1 P14 The lock status status of the I/O line 14. 14 1 P15 The lock status status of the I/O line 15. 15 1 P16 The lock status status of the I/O line 16. 16 1 P17 The lock status status of the I/O line 17. 17 1 P18 The lock status status of the I/O line 18. 18 1 P19 The lock status status of the I/O line 19. 19 1 P20 The lock status status of the I/O line 20. 20 1 P21 The lock status status of the I/O line 21. 21 1 P22 The lock status status of the I/O line 22. 22 1 P23 The lock status status of the I/O line 23. 23 1 P24 The lock status status of the I/O line 24. 24 1 P25 The lock status status of the I/O line 25. 25 1 P26 The lock status status of the I/O line 26. 26 1 P27 The lock status status of the I/O line 27. 27 1 P28 The lock status status of the I/O line 28. 28 1 P29 The lock status status of the I/O line 29. 29 1 P30 The lock status status of the I/O line 30. 30 1 P31 The lock status status of the I/O line 31. 31 1 PIO_SODR0 PIO Set Output Data Register 0x010 P0 Set the output data to be driven on the I/O line 0. 0 1 P1 Set the output data to be driven on the I/O line 1. 1 1 P2 Set the output data to be driven on the I/O line 2. 2 1 P3 Set the output data to be driven on the I/O line 3. 3 1 P4 Set the output data to be driven on the I/O line 4. 4 1 P5 Set the output data to be driven on the I/O line 5. 5 1 P6 Set the output data to be driven on the I/O line 6. 6 1 P7 Set the output data to be driven on the I/O line 7. 7 1 P8 Set the output data to be driven on the I/O line 8. 8 1 P9 Set the output data to be driven on the I/O line 9. 9 1 P10 Set the output data to be driven on the I/O line 10. 10 1 P11 Set the output data to be driven on the I/O line 11. 11 1 P12 Set the output data to be driven on the I/O line 12. 12 1 P13 Set the output data to be driven on the I/O line 13. 13 1 P14 Set the output data to be driven on the I/O line 14. 14 1 P15 Set the output data to be driven on the I/O line 15. 15 1 P16 Set the output data to be driven on the I/O line 16. 16 1 P17 Set the output data to be driven on the I/O line 17. 17 1 P18 Set the output data to be driven on the I/O line 18. 18 1 P19 Set the output data to be driven on the I/O line 19. 19 1 P20 Set the output data to be driven on the I/O line 20. 20 1 P21 Set the output data to be driven on the I/O line 21. 21 1 P22 Set the output data to be driven on the I/O line 22. 22 1 P23 Set the output data to be driven on the I/O line 23. 23 1 P24 Set the output data to be driven on the I/O line 24. 24 1 P25 Set the output data to be driven on the I/O line 25. 25 1 P26 Set the output data to be driven on the I/O line 26. 26 1 P27 Set the output data to be driven on the I/O line 27. 27 1 P28 Set the output data to be driven on the I/O line 28. 28 1 P29 Set the output data to be driven on the I/O line 29. 29 1 P30 Set the output data to be driven on the I/O line 30. 30 1 P31 Set the output data to be driven on the I/O line 31. 31 1 PIO_SODR1 PIO Set Output Data Register 0x050 P0 Set the output data to be driven on the I/O line 0. 0 1 P1 Set the output data to be driven on the I/O line 1. 1 1 P2 Set the output data to be driven on the I/O line 2. 2 1 P3 Set the output data to be driven on the I/O line 3. 3 1 P4 Set the output data to be driven on the I/O line 4. 4 1 P5 Set the output data to be driven on the I/O line 5. 5 1 P6 Set the output data to be driven on the I/O line 6. 6 1 P7 Set the output data to be driven on the I/O line 7. 7 1 P8 Set the output data to be driven on the I/O line 8. 8 1 P9 Set the output data to be driven on the I/O line 9. 9 1 P10 Set the output data to be driven on the I/O line 10. 10 1 P11 Set the output data to be driven on the I/O line 11. 11 1 P12 Set the output data to be driven on the I/O line 12. 12 1 P13 Set the output data to be driven on the I/O line 13. 13 1 P14 Set the output data to be driven on the I/O line 14. 14 1 P15 Set the output data to be driven on the I/O line 15. 15 1 P16 Set the output data to be driven on the I/O line 16. 16 1 P17 Set the output data to be driven on the I/O line 17. 17 1 P18 Set the output data to be driven on the I/O line 18. 18 1 P19 Set the output data to be driven on the I/O line 19. 19 1 P20 Set the output data to be driven on the I/O line 20. 20 1 P21 Set the output data to be driven on the I/O line 21. 21 1 P22 Set the output data to be driven on the I/O line 22. 22 1 P23 Set the output data to be driven on the I/O line 23. 23 1 P24 Set the output data to be driven on the I/O line 24. 24 1 P25 Set the output data to be driven on the I/O line 25. 25 1 P26 Set the output data to be driven on the I/O line 26. 26 1 P27 Set the output data to be driven on the I/O line 27. 27 1 P28 Set the output data to be driven on the I/O line 28. 28 1 P29 Set the output data to be driven on the I/O line 29. 29 1 P30 Set the output data to be driven on the I/O line 30. 30 1 P31 Set the output data to be driven on the I/O line 31. 31 1 PIO_SODR2 PIO Set Output Data Register 0x090 P0 Set the output data to be driven on the I/O line 0. 0 1 P1 Set the output data to be driven on the I/O line 1. 1 1 P2 Set the output data to be driven on the I/O line 2. 2 1 P3 Set the output data to be driven on the I/O line 3. 3 1 P4 Set the output data to be driven on the I/O line 4. 4 1 P5 Set the output data to be driven on the I/O line 5. 5 1 P6 Set the output data to be driven on the I/O line 6. 6 1 P7 Set the output data to be driven on the I/O line 7. 7 1 P8 Set the output data to be driven on the I/O line 8. 8 1 P9 Set the output data to be driven on the I/O line 9. 9 1 P10 Set the output data to be driven on the I/O line 10. 10 1 P11 Set the output data to be driven on the I/O line 11. 11 1 P12 Set the output data to be driven on the I/O line 12. 12 1 P13 Set the output data to be driven on the I/O line 13. 13 1 P14 Set the output data to be driven on the I/O line 14. 14 1 P15 Set the output data to be driven on the I/O line 15. 15 1 P16 Set the output data to be driven on the I/O line 16. 16 1 P17 Set the output data to be driven on the I/O line 17. 17 1 P18 Set the output data to be driven on the I/O line 18. 18 1 P19 Set the output data to be driven on the I/O line 19. 19 1 P20 Set the output data to be driven on the I/O line 20. 20 1 P21 Set the output data to be driven on the I/O line 21. 21 1 P22 Set the output data to be driven on the I/O line 22. 22 1 P23 Set the output data to be driven on the I/O line 23. 23 1 P24 Set the output data to be driven on the I/O line 24. 24 1 P25 Set the output data to be driven on the I/O line 25. 25 1 P26 Set the output data to be driven on the I/O line 26. 26 1 P27 Set the output data to be driven on the I/O line 27. 27 1 P28 Set the output data to be driven on the I/O line 28. 28 1 P29 Set the output data to be driven on the I/O line 29. 29 1 P30 Set the output data to be driven on the I/O line 30. 30 1 P31 Set the output data to be driven on the I/O line 31. 31 1 PIO_SODR3 PIO Set Output Data Register 0x0D0 P0 Set the output data to be driven on the I/O line 0. 0 1 P1 Set the output data to be driven on the I/O line 1. 1 1 P2 Set the output data to be driven on the I/O line 2. 2 1 P3 Set the output data to be driven on the I/O line 3. 3 1 P4 Set the output data to be driven on the I/O line 4. 4 1 P5 Set the output data to be driven on the I/O line 5. 5 1 P6 Set the output data to be driven on the I/O line 6. 6 1 P7 Set the output data to be driven on the I/O line 7. 7 1 P8 Set the output data to be driven on the I/O line 8. 8 1 P9 Set the output data to be driven on the I/O line 9. 9 1 P10 Set the output data to be driven on the I/O line 10. 10 1 P11 Set the output data to be driven on the I/O line 11. 11 1 P12 Set the output data to be driven on the I/O line 12. 12 1 P13 Set the output data to be driven on the I/O line 13. 13 1 P14 Set the output data to be driven on the I/O line 14. 14 1 P15 Set the output data to be driven on the I/O line 15. 15 1 P16 Set the output data to be driven on the I/O line 16. 16 1 P17 Set the output data to be driven on the I/O line 17. 17 1 P18 Set the output data to be driven on the I/O line 18. 18 1 P19 Set the output data to be driven on the I/O line 19. 19 1 P20 Set the output data to be driven on the I/O line 20. 20 1 P21 Set the output data to be driven on the I/O line 21. 21 1 P22 Set the output data to be driven on the I/O line 22. 22 1 P23 Set the output data to be driven on the I/O line 23. 23 1 P24 Set the output data to be driven on the I/O line 24. 24 1 P25 Set the output data to be driven on the I/O line 25. 25 1 P26 Set the output data to be driven on the I/O line 26. 26 1 P27 Set the output data to be driven on the I/O line 27. 27 1 P28 Set the output data to be driven on the I/O line 28. 28 1 P29 Set the output data to be driven on the I/O line 29. 29 1 P30 Set the output data to be driven on the I/O line 30. 30 1 P31 Set the output data to be driven on the I/O line 31. 31 1 PIO_CODR0 PIO Clear Output Data Register. 0x014 P0 Clear the output data to be driven on the I/O line 0. 0 1 P1 Clear the output data to be driven on the I/O line 1. 1 1 P2 Clear the output data to be driven on the I/O line 2. 2 1 P3 Clear the output data to be driven on the I/O line 3. 3 1 P4 Clear the output data to be driven on the I/O line 4. 4 1 P5 Clear the output data to be driven on the I/O line 5. 5 1 P6 Clear the output data to be driven on the I/O line 6. 6 1 P7 Clear the output data to be driven on the I/O line 7. 7 1 P8 Clear the output data to be driven on the I/O line 8. 8 1 P9 Clear the output data to be driven on the I/O line 9. 9 1 P10 Clear the output data to be driven on the I/O line 10. 10 1 P11 Clear the output data to be driven on the I/O line 11. 11 1 P12 Clear the output data to be driven on the I/O line 12. 12 1 P13 Clear the output data to be driven on the I/O line 13. 13 1 P14 Clear the output data to be driven on the I/O line 14. 14 1 P15 Clear the output data to be driven on the I/O line 15. 15 1 P16 Clear the output data to be driven on the I/O line 16. 16 1 P17 Clear the output data to be driven on the I/O line 17. 17 1 P18 Clear the output data to be driven on the I/O line 18. 18 1 P19 Clear the output data to be driven on the I/O line 19. 19 1 P20 Clear the output data to be driven on the I/O line 20. 20 1 P21 Clear the output data to be driven on the I/O line 21. 21 1 P22 Clear the output data to be driven on the I/O line 22. 22 1 P23 Clear the output data to be driven on the I/O line 23. 23 1 P24 Clear the output data to be driven on the I/O line 24. 24 1 P25 Clear the output data to be driven on the I/O line 25. 25 1 P26 Clear the output data to be driven on the I/O line 26. 26 1 P27 Clear the output data to be driven on the I/O line 27. 27 1 P28 Clear the output data to be driven on the I/O line 28. 28 1 P29 Clear the output data to be driven on the I/O line 29. 29 1 P30 Clear the output data to be driven on the I/O line 30. 30 1 P31 Clear the output data to be driven on the I/O line 31. 31 1 PIO_CODR1 PIO Clear Output Data Register. 0x054 P0 Clear the output data to be driven on the I/O line 0. 0 1 P1 Clear the output data to be driven on the I/O line 1. 1 1 P2 Clear the output data to be driven on the I/O line 2. 2 1 P3 Clear the output data to be driven on the I/O line 3. 3 1 P4 Clear the output data to be driven on the I/O line 4. 4 1 P5 Clear the output data to be driven on the I/O line 5. 5 1 P6 Clear the output data to be driven on the I/O line 6. 6 1 P7 Clear the output data to be driven on the I/O line 7. 7 1 P8 Clear the output data to be driven on the I/O line 8. 8 1 P9 Clear the output data to be driven on the I/O line 9. 9 1 P10 Clear the output data to be driven on the I/O line 10. 10 1 P11 Clear the output data to be driven on the I/O line 11. 11 1 P12 Clear the output data to be driven on the I/O line 12. 12 1 P13 Clear the output data to be driven on the I/O line 13. 13 1 P14 Clear the output data to be driven on the I/O line 14. 14 1 P15 Clear the output data to be driven on the I/O line 15. 15 1 P16 Clear the output data to be driven on the I/O line 16. 16 1 P17 Clear the output data to be driven on the I/O line 17. 17 1 P18 Clear the output data to be driven on the I/O line 18. 18 1 P19 Clear the output data to be driven on the I/O line 19. 19 1 P20 Clear the output data to be driven on the I/O line 20. 20 1 P21 Clear the output data to be driven on the I/O line 21. 21 1 P22 Clear the output data to be driven on the I/O line 22. 22 1 P23 Clear the output data to be driven on the I/O line 23. 23 1 P24 Clear the output data to be driven on the I/O line 24. 24 1 P25 Clear the output data to be driven on the I/O line 25. 25 1 P26 Clear the output data to be driven on the I/O line 26. 26 1 P27 Clear the output data to be driven on the I/O line 27. 27 1 P28 Clear the output data to be driven on the I/O line 28. 28 1 P29 Clear the output data to be driven on the I/O line 29. 29 1 P30 Clear the output data to be driven on the I/O line 30. 30 1 P31 Clear the output data to be driven on the I/O line 31. 31 1 PIO_CODR2 PIO Clear Output Data Register. 0x094 P0 Clear the output data to be driven on the I/O line 0. 0 1 P1 Clear the output data to be driven on the I/O line 1. 1 1 P2 Clear the output data to be driven on the I/O line 2. 2 1 P3 Clear the output data to be driven on the I/O line 3. 3 1 P4 Clear the output data to be driven on the I/O line 4. 4 1 P5 Clear the output data to be driven on the I/O line 5. 5 1 P6 Clear the output data to be driven on the I/O line 6. 6 1 P7 Clear the output data to be driven on the I/O line 7. 7 1 P8 Clear the output data to be driven on the I/O line 8. 8 1 P9 Clear the output data to be driven on the I/O line 9. 9 1 P10 Clear the output data to be driven on the I/O line 10. 10 1 P11 Clear the output data to be driven on the I/O line 11. 11 1 P12 Clear the output data to be driven on the I/O line 12. 12 1 P13 Clear the output data to be driven on the I/O line 13. 13 1 P14 Clear the output data to be driven on the I/O line 14. 14 1 P15 Clear the output data to be driven on the I/O line 15. 15 1 P16 Clear the output data to be driven on the I/O line 16. 16 1 P17 Clear the output data to be driven on the I/O line 17. 17 1 P18 Clear the output data to be driven on the I/O line 18. 18 1 P19 Clear the output data to be driven on the I/O line 19. 19 1 P20 Clear the output data to be driven on the I/O line 20. 20 1 P21 Clear the output data to be driven on the I/O line 21. 21 1 P22 Clear the output data to be driven on the I/O line 22. 22 1 P23 Clear the output data to be driven on the I/O line 23. 23 1 P24 Clear the output data to be driven on the I/O line 24. 24 1 P25 Clear the output data to be driven on the I/O line 25. 25 1 P26 Clear the output data to be driven on the I/O line 26. 26 1 P27 Clear the output data to be driven on the I/O line 27. 27 1 P28 Clear the output data to be driven on the I/O line 28. 28 1 P29 Clear the output data to be driven on the I/O line 29. 29 1 P30 Clear the output data to be driven on the I/O line 30. 30 1 P31 Clear the output data to be driven on the I/O line 31. 31 1 PIO_CODR3 PIO Clear Output Data Register. 0x0D4 P0 Clear the output data to be driven on the I/O line 0. 0 1 P1 Clear the output data to be driven on the I/O line 1. 1 1 P2 Clear the output data to be driven on the I/O line 2. 2 1 P3 Clear the output data to be driven on the I/O line 3. 3 1 P4 Clear the output data to be driven on the I/O line 4. 4 1 P5 Clear the output data to be driven on the I/O line 5. 5 1 P6 Clear the output data to be driven on the I/O line 6. 6 1 P7 Clear the output data to be driven on the I/O line 7. 7 1 P8 Clear the output data to be driven on the I/O line 8. 8 1 P9 Clear the output data to be driven on the I/O line 9. 9 1 P10 Clear the output data to be driven on the I/O line 10. 10 1 P11 Clear the output data to be driven on the I/O line 11. 11 1 P12 Clear the output data to be driven on the I/O line 12. 12 1 P13 Clear the output data to be driven on the I/O line 13. 13 1 P14 Clear the output data to be driven on the I/O line 14. 14 1 P15 Clear the output data to be driven on the I/O line 15. 15 1 P16 Clear the output data to be driven on the I/O line 16. 16 1 P17 Clear the output data to be driven on the I/O line 17. 17 1 P18 Clear the output data to be driven on the I/O line 18. 18 1 P19 Clear the output data to be driven on the I/O line 19. 19 1 P20 Clear the output data to be driven on the I/O line 20. 20 1 P21 Clear the output data to be driven on the I/O line 21. 21 1 P22 Clear the output data to be driven on the I/O line 22. 22 1 P23 Clear the output data to be driven on the I/O line 23. 23 1 P24 Clear the output data to be driven on the I/O line 24. 24 1 P25 Clear the output data to be driven on the I/O line 25. 25 1 P26 Clear the output data to be driven on the I/O line 26. 26 1 P27 Clear the output data to be driven on the I/O line 27. 27 1 P28 Clear the output data to be driven on the I/O line 28. 28 1 P29 Clear the output data to be driven on the I/O line 29. 29 1 P30 Clear the output data to be driven on the I/O line 30. 30 1 P31 Clear the output data to be driven on the I/O line 31. 31 1 PIO_ODSR0 PIO Output Data Status Register. 0x018 P0 The output data status to be driven on the I/O line 0. 0 1 P1 The output data status to be driven on the I/O line 1. 1 1 P2 The output data status to be driven on the I/O line 2. 2 1 P3 The output data status to be driven on the I/O line 3. 3 1 P4 The output data status to be driven on the I/O line 4. 4 1 P5 The output data status to be driven on the I/O line 5. 5 1 P6 The output data status to be driven on the I/O line 6. 6 1 P7 The output data status to be driven on the I/O line 7. 7 1 P8 The output data status to be driven on the I/O line 8. 8 1 P9 The output data status to be driven on the I/O line 9. 9 1 P10 The output data status to be driven on the I/O line 10. 10 1 P11 The output data status to be driven on the I/O line 11. 11 1 P12 The output data status to be driven on the I/O line 12. 12 1 P13 The output data status to be driven on the I/O line 13. 13 1 P14 The output data status to be driven on the I/O line 14. 14 1 P15 The output data status to be driven on the I/O line 15. 15 1 P16 The output data status to be driven on the I/O line 16. 16 1 P17 The output data status to be driven on the I/O line 17. 17 1 P18 The output data status to be driven on the I/O line 18. 18 1 P19 The output data status to be driven on the I/O line 19. 19 1 P20 The output data status to be driven on the I/O line 20. 20 1 P21 The output data status to be driven on the I/O line 21. 21 1 P22 The output data status to be driven on the I/O line 22. 22 1 P23 The output data status to be driven on the I/O line 23. 23 1 P24 The output data status to be driven on the I/O line 24. 24 1 P25 The output data status to be driven on the I/O line 25. 25 1 P26 The output data status to be driven on the I/O line 26. 26 1 P27 The output data status to be driven on the I/O line 27. 27 1 P28 The output data status to be driven on the I/O line 28. 28 1 P29 The output data status to be driven on the I/O line 29. 29 1 P30 The output data status to be driven on the I/O line 30. 30 1 P31 The output data status to be driven on the I/O line 31. 31 1 PIO_ODSR1 PIO Output Data Status Register. 0x058 P0 The output data status to be driven on the I/O line 0. 0 1 P1 The output data status to be driven on the I/O line 1. 1 1 P2 The output data status to be driven on the I/O line 2. 2 1 P3 The output data status to be driven on the I/O line 3. 3 1 P4 The output data status to be driven on the I/O line 4. 4 1 P5 The output data status to be driven on the I/O line 5. 5 1 P6 The output data status to be driven on the I/O line 6. 6 1 P7 The output data status to be driven on the I/O line 7. 7 1 P8 The output data status to be driven on the I/O line 8. 8 1 P9 The output data status to be driven on the I/O line 9. 9 1 P10 The output data status to be driven on the I/O line 10. 10 1 P11 The output data status to be driven on the I/O line 11. 11 1 P12 The output data status to be driven on the I/O line 12. 12 1 P13 The output data status to be driven on the I/O line 13. 13 1 P14 The output data status to be driven on the I/O line 14. 14 1 P15 The output data status to be driven on the I/O line 15. 15 1 P16 The output data status to be driven on the I/O line 16. 16 1 P17 The output data status to be driven on the I/O line 17. 17 1 P18 The output data status to be driven on the I/O line 18. 18 1 P19 The output data status to be driven on the I/O line 19. 19 1 P20 The output data status to be driven on the I/O line 20. 20 1 P21 The output data status to be driven on the I/O line 21. 21 1 P22 The output data status to be driven on the I/O line 22. 22 1 P23 The output data status to be driven on the I/O line 23. 23 1 P24 The output data status to be driven on the I/O line 24. 24 1 P25 The output data status to be driven on the I/O line 25. 25 1 P26 The output data status to be driven on the I/O line 26. 26 1 P27 The output data status to be driven on the I/O line 27. 27 1 P28 The output data status to be driven on the I/O line 28. 28 1 P29 The output data status to be driven on the I/O line 29. 29 1 P30 The output data status to be driven on the I/O line 30. 30 1 P31 The output data status to be driven on the I/O line 31. 31 1 PIO_ODSR2 PIO Output Data Status Register. 0x098 P0 The output data status to be driven on the I/O line 0. 0 1 P1 The output data status to be driven on the I/O line 1. 1 1 P2 The output data status to be driven on the I/O line 2. 2 1 P3 The output data status to be driven on the I/O line 3. 3 1 P4 The output data status to be driven on the I/O line 4. 4 1 P5 The output data status to be driven on the I/O line 5. 5 1 P6 The output data status to be driven on the I/O line 6. 6 1 P7 The output data status to be driven on the I/O line 7. 7 1 P8 The output data status to be driven on the I/O line 8. 8 1 P9 The output data status to be driven on the I/O line 9. 9 1 P10 The output data status to be driven on the I/O line 10. 10 1 P11 The output data status to be driven on the I/O line 11. 11 1 P12 The output data status to be driven on the I/O line 12. 12 1 P13 The output data status to be driven on the I/O line 13. 13 1 P14 The output data status to be driven on the I/O line 14. 14 1 P15 The output data status to be driven on the I/O line 15. 15 1 P16 The output data status to be driven on the I/O line 16. 16 1 P17 The output data status to be driven on the I/O line 17. 17 1 P18 The output data status to be driven on the I/O line 18. 18 1 P19 The output data status to be driven on the I/O line 19. 19 1 P20 The output data status to be driven on the I/O line 20. 20 1 P21 The output data status to be driven on the I/O line 21. 21 1 P22 The output data status to be driven on the I/O line 22. 22 1 P23 The output data status to be driven on the I/O line 23. 23 1 P24 The output data status to be driven on the I/O line 24. 24 1 P25 The output data status to be driven on the I/O line 25. 25 1 P26 The output data status to be driven on the I/O line 26. 26 1 P27 The output data status to be driven on the I/O line 27. 27 1 P28 The output data status to be driven on the I/O line 28. 28 1 P29 The output data status to be driven on the I/O line 29. 29 1 P30 The output data status to be driven on the I/O line 30. 30 1 P31 The output data status to be driven on the I/O line 31. 31 1 PIO_ODSR3 PIO Output Data Status Register. 0x0D8 P0 The output data status to be driven on the I/O line 0. 0 1 P1 The output data status to be driven on the I/O line 1. 1 1 P2 The output data status to be driven on the I/O line 2. 2 1 P3 The output data status to be driven on the I/O line 3. 3 1 P4 The output data status to be driven on the I/O line 4. 4 1 P5 The output data status to be driven on the I/O line 5. 5 1 P6 The output data status to be driven on the I/O line 6. 6 1 P7 The output data status to be driven on the I/O line 7. 7 1 P8 The output data status to be driven on the I/O line 8. 8 1 P9 The output data status to be driven on the I/O line 9. 9 1 P10 The output data status to be driven on the I/O line 10. 10 1 P11 The output data status to be driven on the I/O line 11. 11 1 P12 The output data status to be driven on the I/O line 12. 12 1 P13 The output data status to be driven on the I/O line 13. 13 1 P14 The output data status to be driven on the I/O line 14. 14 1 P15 The output data status to be driven on the I/O line 15. 15 1 P16 The output data status to be driven on the I/O line 16. 16 1 P17 The output data status to be driven on the I/O line 17. 17 1 P18 The output data status to be driven on the I/O line 18. 18 1 P19 The output data status to be driven on the I/O line 19. 19 1 P20 The output data status to be driven on the I/O line 20. 20 1 P21 The output data status to be driven on the I/O line 21. 21 1 P22 The output data status to be driven on the I/O line 22. 22 1 P23 The output data status to be driven on the I/O line 23. 23 1 P24 The output data status to be driven on the I/O line 24. 24 1 P25 The output data status to be driven on the I/O line 25. 25 1 P26 The output data status to be driven on the I/O line 26. 26 1 P27 The output data status to be driven on the I/O line 27. 27 1 P28 The output data status to be driven on the I/O line 28. 28 1 P29 The output data status to be driven on the I/O line 29. 29 1 P30 The output data status to be driven on the I/O line 30. 30 1 P31 The output data status to be driven on the I/O line 31. 31 1 PIO_IER0 PIO Interrupt Enable Register. 0x020 write-only P0 Enables the Input Change interrupt on the I/O line 0. 0 1 P1 Enables the Input Change interrupt on the I/O line 1. 1 1 P2 Enables the Input Change interrupt on the I/O line 2. 2 1 P3 Enables the Input Change interrupt on the I/O line 3. 3 1 P4 Enables the Input Change interrupt on the I/O line 4. 4 1 P5 Enables the Input Change interrupt on the I/O line 5. 5 1 P6 Enables the Input Change interrupt on the I/O line 6. 6 1 P7 Enables the Input Change interrupt on the I/O line 7. 7 1 P8 Enables the Input Change interrupt on the I/O line 8. 8 1 P9 Enables the Input Change interrupt on the I/O line 9. 9 1 P10 Enables the Input Change interrupt on the I/O line 10. 10 1 P11 Enables the Input Change interrupt on the I/O line 11. 11 1 P12 Enables the Input Change interrupt on the I/O line 12. 12 1 P13 Enables the Input Change interrupt on the I/O line 13. 13 1 P14 Enables the Input Change interrupt on the I/O line 14. 14 1 P15 Enables the Input Change interrupt on the I/O line 15. 15 1 P16 Enables the Input Change interrupt on the I/O line 16. 16 1 P17 Enables the Input Change interrupt on the I/O line 17. 17 1 P18 Enables the Input Change interrupt on the I/O line 18. 18 1 P19 Enables the Input Change interrupt on the I/O line 19. 19 1 P20 Enables the Input Change interrupt on the I/O line 20. 20 1 P21 Enables the Input Change interrupt on the I/O line 21. 21 1 P22 Enables the Input Change interrupt on the I/O line 22. 22 1 P23 Enables the Input Change interrupt on the I/O line 23. 23 1 P24 Enables the Input Change interrupt on the I/O line 24. 24 1 P25 Enables the Input Change interrupt on the I/O line 25. 25 1 P26 Enables the Input Change interrupt on the I/O line 26. 26 1 P27 Enables the Input Change interrupt on the I/O line 27. 27 1 P28 Enables the Input Change interrupt on the I/O line 28. 28 1 P29 Enables the Input Change interrupt on the I/O line 29. 29 1 P30 Enables the Input Change interrupt on the I/O line 30. 30 1 P31 Enables the Input Change interrupt on the I/O line 31. 31 1 PIO_IER1 PIO Interrupt Enable Register. 0x060 write-only P0 Enables the Input Change interrupt on the I/O line 0. 0 1 P1 Enables the Input Change interrupt on the I/O line 1. 1 1 P2 Enables the Input Change interrupt on the I/O line 2. 2 1 P3 Enables the Input Change interrupt on the I/O line 3. 3 1 P4 Enables the Input Change interrupt on the I/O line 4. 4 1 P5 Enables the Input Change interrupt on the I/O line 5. 5 1 P6 Enables the Input Change interrupt on the I/O line 6. 6 1 P7 Enables the Input Change interrupt on the I/O line 7. 7 1 P8 Enables the Input Change interrupt on the I/O line 8. 8 1 P9 Enables the Input Change interrupt on the I/O line 9. 9 1 P10 Enables the Input Change interrupt on the I/O line 10. 10 1 P11 Enables the Input Change interrupt on the I/O line 11. 11 1 P12 Enables the Input Change interrupt on the I/O line 12. 12 1 P13 Enables the Input Change interrupt on the I/O line 13. 13 1 P14 Enables the Input Change interrupt on the I/O line 14. 14 1 P15 Enables the Input Change interrupt on the I/O line 15. 15 1 P16 Enables the Input Change interrupt on the I/O line 16. 16 1 P17 Enables the Input Change interrupt on the I/O line 17. 17 1 P18 Enables the Input Change interrupt on the I/O line 18. 18 1 P19 Enables the Input Change interrupt on the I/O line 19. 19 1 P20 Enables the Input Change interrupt on the I/O line 20. 20 1 P21 Enables the Input Change interrupt on the I/O line 21. 21 1 P22 Enables the Input Change interrupt on the I/O line 22. 22 1 P23 Enables the Input Change interrupt on the I/O line 23. 23 1 P24 Enables the Input Change interrupt on the I/O line 24. 24 1 P25 Enables the Input Change interrupt on the I/O line 25. 25 1 P26 Enables the Input Change interrupt on the I/O line 26. 26 1 P27 Enables the Input Change interrupt on the I/O line 27. 27 1 P28 Enables the Input Change interrupt on the I/O line 28. 28 1 P29 Enables the Input Change interrupt on the I/O line 29. 29 1 P30 Enables the Input Change interrupt on the I/O line 30. 30 1 P31 Enables the Input Change interrupt on the I/O line 31. 31 1 PIO_IER2 PIO Interrupt Enable Register. 0x0A0 write-only P0 Enables the Input Change interrupt on the I/O line 0. 0 1 P1 Enables the Input Change interrupt on the I/O line 1. 1 1 P2 Enables the Input Change interrupt on the I/O line 2. 2 1 P3 Enables the Input Change interrupt on the I/O line 3. 3 1 P4 Enables the Input Change interrupt on the I/O line 4. 4 1 P5 Enables the Input Change interrupt on the I/O line 5. 5 1 P6 Enables the Input Change interrupt on the I/O line 6. 6 1 P7 Enables the Input Change interrupt on the I/O line 7. 7 1 P8 Enables the Input Change interrupt on the I/O line 8. 8 1 P9 Enables the Input Change interrupt on the I/O line 9. 9 1 P10 Enables the Input Change interrupt on the I/O line 10. 10 1 P11 Enables the Input Change interrupt on the I/O line 11. 11 1 P12 Enables the Input Change interrupt on the I/O line 12. 12 1 P13 Enables the Input Change interrupt on the I/O line 13. 13 1 P14 Enables the Input Change interrupt on the I/O line 14. 14 1 P15 Enables the Input Change interrupt on the I/O line 15. 15 1 P16 Enables the Input Change interrupt on the I/O line 16. 16 1 P17 Enables the Input Change interrupt on the I/O line 17. 17 1 P18 Enables the Input Change interrupt on the I/O line 18. 18 1 P19 Enables the Input Change interrupt on the I/O line 19. 19 1 P20 Enables the Input Change interrupt on the I/O line 20. 20 1 P21 Enables the Input Change interrupt on the I/O line 21. 21 1 P22 Enables the Input Change interrupt on the I/O line 22. 22 1 P23 Enables the Input Change interrupt on the I/O line 23. 23 1 P24 Enables the Input Change interrupt on the I/O line 24. 24 1 P25 Enables the Input Change interrupt on the I/O line 25. 25 1 P26 Enables the Input Change interrupt on the I/O line 26. 26 1 P27 Enables the Input Change interrupt on the I/O line 27. 27 1 P28 Enables the Input Change interrupt on the I/O line 28. 28 1 P29 Enables the Input Change interrupt on the I/O line 29. 29 1 P30 Enables the Input Change interrupt on the I/O line 30. 30 1 P31 Enables the Input Change interrupt on the I/O line 31. 31 1 PIO_IER3 PIO Interrupt Enable Register. 0x0E0 write-only P0 Enables the Input Change interrupt on the I/O line 0. 0 1 P1 Enables the Input Change interrupt on the I/O line 1. 1 1 P2 Enables the Input Change interrupt on the I/O line 2. 2 1 P3 Enables the Input Change interrupt on the I/O line 3. 3 1 P4 Enables the Input Change interrupt on the I/O line 4. 4 1 P5 Enables the Input Change interrupt on the I/O line 5. 5 1 P6 Enables the Input Change interrupt on the I/O line 6. 6 1 P7 Enables the Input Change interrupt on the I/O line 7. 7 1 P8 Enables the Input Change interrupt on the I/O line 8. 8 1 P9 Enables the Input Change interrupt on the I/O line 9. 9 1 P10 Enables the Input Change interrupt on the I/O line 10. 10 1 P11 Enables the Input Change interrupt on the I/O line 11. 11 1 P12 Enables the Input Change interrupt on the I/O line 12. 12 1 P13 Enables the Input Change interrupt on the I/O line 13. 13 1 P14 Enables the Input Change interrupt on the I/O line 14. 14 1 P15 Enables the Input Change interrupt on the I/O line 15. 15 1 P16 Enables the Input Change interrupt on the I/O line 16. 16 1 P17 Enables the Input Change interrupt on the I/O line 17. 17 1 P18 Enables the Input Change interrupt on the I/O line 18. 18 1 P19 Enables the Input Change interrupt on the I/O line 19. 19 1 P20 Enables the Input Change interrupt on the I/O line 20. 20 1 P21 Enables the Input Change interrupt on the I/O line 21. 21 1 P22 Enables the Input Change interrupt on the I/O line 22. 22 1 P23 Enables the Input Change interrupt on the I/O line 23. 23 1 P24 Enables the Input Change interrupt on the I/O line 24. 24 1 P25 Enables the Input Change interrupt on the I/O line 25. 25 1 P26 Enables the Input Change interrupt on the I/O line 26. 26 1 P27 Enables the Input Change interrupt on the I/O line 27. 27 1 P28 Enables the Input Change interrupt on the I/O line 28. 28 1 P29 Enables the Input Change interrupt on the I/O line 29. 29 1 P30 Enables the Input Change interrupt on the I/O line 30. 30 1 P31 Enables the Input Change interrupt on the I/O line 31. 31 1 PIO_IDR0 PIO Interrupt Disable Register. 0x024 write-only P0 Disables the Input Change interrupt on the I/O line 0. 0 1 P1 Disables the Input Change interrupt on the I/O line 1. 1 1 P2 Disables the Input Change interrupt on the I/O line 2. 2 1 P3 Disables the Input Change interrupt on the I/O line 3. 3 1 P4 Disables the Input Change interrupt on the I/O line 4. 4 1 P5 Disables the Input Change interrupt on the I/O line 5. 5 1 P6 Disables the Input Change interrupt on the I/O line 6. 6 1 P7 Disables the Input Change interrupt on the I/O line 7. 7 1 P8 Disables the Input Change interrupt on the I/O line 8. 8 1 P9 Disables the Input Change interrupt on the I/O line 9. 9 1 P10 Disables the Input Change interrupt on the I/O line 10. 10 1 P11 Disables the Input Change interrupt on the I/O line 11. 11 1 P12 Disables the Input Change interrupt on the I/O line 12. 12 1 P13 Disables the Input Change interrupt on the I/O line 13. 13 1 P14 Disables the Input Change interrupt on the I/O line 14. 14 1 P15 Disables the Input Change interrupt on the I/O line 15. 15 1 P16 Disables the Input Change interrupt on the I/O line 16. 16 1 P17 Disables the Input Change interrupt on the I/O line 17. 17 1 P18 Disables the Input Change interrupt on the I/O line 18. 18 1 P19 Disables the Input Change interrupt on the I/O line 19. 19 1 P20 Disables the Input Change interrupt on the I/O line 20. 20 1 P21 Disables the Input Change interrupt on the I/O line 21. 21 1 P22 Disables the Input Change interrupt on the I/O line 22. 22 1 P23 Disables the Input Change interrupt on the I/O line 23. 23 1 P24 Disables the Input Change interrupt on the I/O line 24. 24 1 P25 Disables the Input Change interrupt on the I/O line 25. 25 1 P26 Disables the Input Change interrupt on the I/O line 26. 26 1 P27 Disables the Input Change interrupt on the I/O line 27. 27 1 P28 Disables the Input Change interrupt on the I/O line 28. 28 1 P29 Disables the Input Change interrupt on the I/O line 29. 29 1 P30 Disables the Input Change interrupt on the I/O line 30. 30 1 P31 Disables the Input Change interrupt on the I/O line 31. 31 1 PIO_IDR1 PIO Interrupt Disable Register. 0x064 write-only P0 Disables the Input Change interrupt on the I/O line 0. 0 1 P1 Disables the Input Change interrupt on the I/O line 1. 1 1 P2 Disables the Input Change interrupt on the I/O line 2. 2 1 P3 Disables the Input Change interrupt on the I/O line 3. 3 1 P4 Disables the Input Change interrupt on the I/O line 4. 4 1 P5 Disables the Input Change interrupt on the I/O line 5. 5 1 P6 Disables the Input Change interrupt on the I/O line 6. 6 1 P7 Disables the Input Change interrupt on the I/O line 7. 7 1 P8 Disables the Input Change interrupt on the I/O line 8. 8 1 P9 Disables the Input Change interrupt on the I/O line 9. 9 1 P10 Disables the Input Change interrupt on the I/O line 10. 10 1 P11 Disables the Input Change interrupt on the I/O line 11. 11 1 P12 Disables the Input Change interrupt on the I/O line 12. 12 1 P13 Disables the Input Change interrupt on the I/O line 13. 13 1 P14 Disables the Input Change interrupt on the I/O line 14. 14 1 P15 Disables the Input Change interrupt on the I/O line 15. 15 1 P16 Disables the Input Change interrupt on the I/O line 16. 16 1 P17 Disables the Input Change interrupt on the I/O line 17. 17 1 P18 Disables the Input Change interrupt on the I/O line 18. 18 1 P19 Disables the Input Change interrupt on the I/O line 19. 19 1 P20 Disables the Input Change interrupt on the I/O line 20. 20 1 P21 Disables the Input Change interrupt on the I/O line 21. 21 1 P22 Disables the Input Change interrupt on the I/O line 22. 22 1 P23 Disables the Input Change interrupt on the I/O line 23. 23 1 P24 Disables the Input Change interrupt on the I/O line 24. 24 1 P25 Disables the Input Change interrupt on the I/O line 25. 25 1 P26 Disables the Input Change interrupt on the I/O line 26. 26 1 P27 Disables the Input Change interrupt on the I/O line 27. 27 1 P28 Disables the Input Change interrupt on the I/O line 28. 28 1 P29 Disables the Input Change interrupt on the I/O line 29. 29 1 P30 Disables the Input Change interrupt on the I/O line 30. 30 1 P31 Disables the Input Change interrupt on the I/O line 31. 31 1 PIO_IDR2 PIO Interrupt Disable Register. 0x0A4 write-only P0 Disables the Input Change interrupt on the I/O line 0. 0 1 P1 Disables the Input Change interrupt on the I/O line 1. 1 1 P2 Disables the Input Change interrupt on the I/O line 2. 2 1 P3 Disables the Input Change interrupt on the I/O line 3. 3 1 P4 Disables the Input Change interrupt on the I/O line 4. 4 1 P5 Disables the Input Change interrupt on the I/O line 5. 5 1 P6 Disables the Input Change interrupt on the I/O line 6. 6 1 P7 Disables the Input Change interrupt on the I/O line 7. 7 1 P8 Disables the Input Change interrupt on the I/O line 8. 8 1 P9 Disables the Input Change interrupt on the I/O line 9. 9 1 P10 Disables the Input Change interrupt on the I/O line 10. 10 1 P11 Disables the Input Change interrupt on the I/O line 11. 11 1 P12 Disables the Input Change interrupt on the I/O line 12. 12 1 P13 Disables the Input Change interrupt on the I/O line 13. 13 1 P14 Disables the Input Change interrupt on the I/O line 14. 14 1 P15 Disables the Input Change interrupt on the I/O line 15. 15 1 P16 Disables the Input Change interrupt on the I/O line 16. 16 1 P17 Disables the Input Change interrupt on the I/O line 17. 17 1 P18 Disables the Input Change interrupt on the I/O line 18. 18 1 P19 Disables the Input Change interrupt on the I/O line 19. 19 1 P20 Disables the Input Change interrupt on the I/O line 20. 20 1 P21 Disables the Input Change interrupt on the I/O line 21. 21 1 P22 Disables the Input Change interrupt on the I/O line 22. 22 1 P23 Disables the Input Change interrupt on the I/O line 23. 23 1 P24 Disables the Input Change interrupt on the I/O line 24. 24 1 P25 Disables the Input Change interrupt on the I/O line 25. 25 1 P26 Disables the Input Change interrupt on the I/O line 26. 26 1 P27 Disables the Input Change interrupt on the I/O line 27. 27 1 P28 Disables the Input Change interrupt on the I/O line 28. 28 1 P29 Disables the Input Change interrupt on the I/O line 29. 29 1 P30 Disables the Input Change interrupt on the I/O line 30. 30 1 P31 Disables the Input Change interrupt on the I/O line 31. 31 1 PIO_IDR3 PIO Interrupt Disable Register. 0x0E4 write-only P0 Disables the Input Change interrupt on the I/O line 0. 0 1 P1 Disables the Input Change interrupt on the I/O line 1. 1 1 P2 Disables the Input Change interrupt on the I/O line 2. 2 1 P3 Disables the Input Change interrupt on the I/O line 3. 3 1 P4 Disables the Input Change interrupt on the I/O line 4. 4 1 P5 Disables the Input Change interrupt on the I/O line 5. 5 1 P6 Disables the Input Change interrupt on the I/O line 6. 6 1 P7 Disables the Input Change interrupt on the I/O line 7. 7 1 P8 Disables the Input Change interrupt on the I/O line 8. 8 1 P9 Disables the Input Change interrupt on the I/O line 9. 9 1 P10 Disables the Input Change interrupt on the I/O line 10. 10 1 P11 Disables the Input Change interrupt on the I/O line 11. 11 1 P12 Disables the Input Change interrupt on the I/O line 12. 12 1 P13 Disables the Input Change interrupt on the I/O line 13. 13 1 P14 Disables the Input Change interrupt on the I/O line 14. 14 1 P15 Disables the Input Change interrupt on the I/O line 15. 15 1 P16 Disables the Input Change interrupt on the I/O line 16. 16 1 P17 Disables the Input Change interrupt on the I/O line 17. 17 1 P18 Disables the Input Change interrupt on the I/O line 18. 18 1 P19 Disables the Input Change interrupt on the I/O line 19. 19 1 P20 Disables the Input Change interrupt on the I/O line 20. 20 1 P21 Disables the Input Change interrupt on the I/O line 21. 21 1 P22 Disables the Input Change interrupt on the I/O line 22. 22 1 P23 Disables the Input Change interrupt on the I/O line 23. 23 1 P24 Disables the Input Change interrupt on the I/O line 24. 24 1 P25 Disables the Input Change interrupt on the I/O line 25. 25 1 P26 Disables the Input Change interrupt on the I/O line 26. 26 1 P27 Disables the Input Change interrupt on the I/O line 27. 27 1 P28 Disables the Input Change interrupt on the I/O line 28. 28 1 P29 Disables the Input Change interrupt on the I/O line 29. 29 1 P30 Disables the Input Change interrupt on the I/O line 30. 30 1 P31 Disables the Input Change interrupt on the I/O line 31. 31 1 PIO_IMR0 PIO Interrupt Mask Register. 0x028 read-only P0 Input Change interrupt mask on the I/O line 0. 0 1 P1 Input Change interrupt mask on the I/O line 1. 1 1 P2 Input Change interrupt mask on the I/O line 2. 2 1 P3 Input Change interrupt mask on the I/O line 3. 3 1 P4 Input Change interrupt mask on the I/O line 4. 4 1 P5 Input Change interrupt mask on the I/O line 5. 5 1 P6 Input Change interrupt mask on the I/O line 6. 6 1 P7 Input Change interrupt mask on the I/O line 7. 7 1 P8 Input Change interrupt mask on the I/O line 8. 8 1 P9 Input Change interrupt mask on the I/O line 9. 9 1 P10 Input Change interrupt mask on the I/O line 10. 10 1 P11 Input Change interrupt mask on the I/O line 11. 11 1 P12 Input Change interrupt mask on the I/O line 12. 12 1 P13 Input Change interrupt mask on the I/O line 13. 13 1 P14 Input Change interrupt mask on the I/O line 14. 14 1 P15 Input Change interrupt mask on the I/O line 15. 15 1 P16 Input Change interrupt mask on the I/O line 16. 16 1 P17 Input Change interrupt mask on the I/O line 17. 17 1 P18 Input Change interrupt mask on the I/O line 18. 18 1 P19 Input Change interrupt mask on the I/O line 19. 19 1 P20 Input Change interrupt mask on the I/O line 20. 20 1 P21 Input Change interrupt mask on the I/O line 21. 21 1 P22 Input Change interrupt mask on the I/O line 22. 22 1 P23 Input Change interrupt mask on the I/O line 23. 23 1 P24 Input Change interrupt mask on the I/O line 24. 24 1 P25 Input Change interrupt mask on the I/O line 25. 25 1 P26 Input Change interrupt mask on the I/O line 26. 26 1 P27 Input Change interrupt mask on the I/O line 27. 27 1 P28 Input Change interrupt mask on the I/O line 28. 28 1 P29 Input Change interrupt mask on the I/O line 29. 29 1 P30 Input Change interrupt mask on the I/O line 30. 30 1 P31 Input Change interrupt mask on the I/O line 31. 31 1 PIO_IMR1 PIO Interrupt Mask Register. 0x068 read-only P0 Input Change interrupt mask on the I/O line 0. 0 1 P1 Input Change interrupt mask on the I/O line 1. 1 1 P2 Input Change interrupt mask on the I/O line 2. 2 1 P3 Input Change interrupt mask on the I/O line 3. 3 1 P4 Input Change interrupt mask on the I/O line 4. 4 1 P5 Input Change interrupt mask on the I/O line 5. 5 1 P6 Input Change interrupt mask on the I/O line 6. 6 1 P7 Input Change interrupt mask on the I/O line 7. 7 1 P8 Input Change interrupt mask on the I/O line 8. 8 1 P9 Input Change interrupt mask on the I/O line 9. 9 1 P10 Input Change interrupt mask on the I/O line 10. 10 1 P11 Input Change interrupt mask on the I/O line 11. 11 1 P12 Input Change interrupt mask on the I/O line 12. 12 1 P13 Input Change interrupt mask on the I/O line 13. 13 1 P14 Input Change interrupt mask on the I/O line 14. 14 1 P15 Input Change interrupt mask on the I/O line 15. 15 1 P16 Input Change interrupt mask on the I/O line 16. 16 1 P17 Input Change interrupt mask on the I/O line 17. 17 1 P18 Input Change interrupt mask on the I/O line 18. 18 1 P19 Input Change interrupt mask on the I/O line 19. 19 1 P20 Input Change interrupt mask on the I/O line 20. 20 1 P21 Input Change interrupt mask on the I/O line 21. 21 1 P22 Input Change interrupt mask on the I/O line 22. 22 1 P23 Input Change interrupt mask on the I/O line 23. 23 1 P24 Input Change interrupt mask on the I/O line 24. 24 1 P25 Input Change interrupt mask on the I/O line 25. 25 1 P26 Input Change interrupt mask on the I/O line 26. 26 1 P27 Input Change interrupt mask on the I/O line 27. 27 1 P28 Input Change interrupt mask on the I/O line 28. 28 1 P29 Input Change interrupt mask on the I/O line 29. 29 1 P30 Input Change interrupt mask on the I/O line 30. 30 1 P31 Input Change interrupt mask on the I/O line 31. 31 1 PIO_IMR2 PIO Interrupt Mask Register. 0x0A8 read-only P0 Input Change interrupt mask on the I/O line 0. 0 1 P1 Input Change interrupt mask on the I/O line 1. 1 1 P2 Input Change interrupt mask on the I/O line 2. 2 1 P3 Input Change interrupt mask on the I/O line 3. 3 1 P4 Input Change interrupt mask on the I/O line 4. 4 1 P5 Input Change interrupt mask on the I/O line 5. 5 1 P6 Input Change interrupt mask on the I/O line 6. 6 1 P7 Input Change interrupt mask on the I/O line 7. 7 1 P8 Input Change interrupt mask on the I/O line 8. 8 1 P9 Input Change interrupt mask on the I/O line 9. 9 1 P10 Input Change interrupt mask on the I/O line 10. 10 1 P11 Input Change interrupt mask on the I/O line 11. 11 1 P12 Input Change interrupt mask on the I/O line 12. 12 1 P13 Input Change interrupt mask on the I/O line 13. 13 1 P14 Input Change interrupt mask on the I/O line 14. 14 1 P15 Input Change interrupt mask on the I/O line 15. 15 1 P16 Input Change interrupt mask on the I/O line 16. 16 1 P17 Input Change interrupt mask on the I/O line 17. 17 1 P18 Input Change interrupt mask on the I/O line 18. 18 1 P19 Input Change interrupt mask on the I/O line 19. 19 1 P20 Input Change interrupt mask on the I/O line 20. 20 1 P21 Input Change interrupt mask on the I/O line 21. 21 1 P22 Input Change interrupt mask on the I/O line 22. 22 1 P23 Input Change interrupt mask on the I/O line 23. 23 1 P24 Input Change interrupt mask on the I/O line 24. 24 1 P25 Input Change interrupt mask on the I/O line 25. 25 1 P26 Input Change interrupt mask on the I/O line 26. 26 1 P27 Input Change interrupt mask on the I/O line 27. 27 1 P28 Input Change interrupt mask on the I/O line 28. 28 1 P29 Input Change interrupt mask on the I/O line 29. 29 1 P30 Input Change interrupt mask on the I/O line 30. 30 1 P31 Input Change interrupt mask on the I/O line 31. 31 1 PIO_IMR3 PIO Interrupt Mask Register. 0x0E8 read-only P0 Input Change interrupt mask on the I/O line 0. 0 1 P1 Input Change interrupt mask on the I/O line 1. 1 1 P2 Input Change interrupt mask on the I/O line 2. 2 1 P3 Input Change interrupt mask on the I/O line 3. 3 1 P4 Input Change interrupt mask on the I/O line 4. 4 1 P5 Input Change interrupt mask on the I/O line 5. 5 1 P6 Input Change interrupt mask on the I/O line 6. 6 1 P7 Input Change interrupt mask on the I/O line 7. 7 1 P8 Input Change interrupt mask on the I/O line 8. 8 1 P9 Input Change interrupt mask on the I/O line 9. 9 1 P10 Input Change interrupt mask on the I/O line 10. 10 1 P11 Input Change interrupt mask on the I/O line 11. 11 1 P12 Input Change interrupt mask on the I/O line 12. 12 1 P13 Input Change interrupt mask on the I/O line 13. 13 1 P14 Input Change interrupt mask on the I/O line 14. 14 1 P15 Input Change interrupt mask on the I/O line 15. 15 1 P16 Input Change interrupt mask on the I/O line 16. 16 1 P17 Input Change interrupt mask on the I/O line 17. 17 1 P18 Input Change interrupt mask on the I/O line 18. 18 1 P19 Input Change interrupt mask on the I/O line 19. 19 1 P20 Input Change interrupt mask on the I/O line 20. 20 1 P21 Input Change interrupt mask on the I/O line 21. 21 1 P22 Input Change interrupt mask on the I/O line 22. 22 1 P23 Input Change interrupt mask on the I/O line 23. 23 1 P24 Input Change interrupt mask on the I/O line 24. 24 1 P25 Input Change interrupt mask on the I/O line 25. 25 1 P26 Input Change interrupt mask on the I/O line 26. 26 1 P27 Input Change interrupt mask on the I/O line 27. 27 1 P28 Input Change interrupt mask on the I/O line 28. 28 1 P29 Input Change interrupt mask on the I/O line 29. 29 1 P30 Input Change interrupt mask on the I/O line 30. 30 1 P31 Input Change interrupt mask on the I/O line 31. 31 1 PIO_ISR0 PIO Interrupt Status Register 0x02C read-only P0 Input Change interrupt status on the I/O line 0. 0 1 P1 Input Change interrupt status on the I/O line 1. 1 1 P2 Input Change interrupt status on the I/O line 2. 2 1 P3 Input Change interrupt status on the I/O line 3. 3 1 P4 Input Change interrupt status on the I/O line 4. 4 1 P5 Input Change interrupt status on the I/O line 5. 5 1 P6 Input Change interrupt status on the I/O line 6. 6 1 P7 Input Change interrupt status on the I/O line 7. 7 1 P8 Input Change interrupt status on the I/O line 8. 8 1 P9 Input Change interrupt status on the I/O line 9. 9 1 P10 Input Change interrupt status on the I/O line 10. 10 1 P11 Input Change interrupt status on the I/O line 11. 11 1 P12 Input Change interrupt status on the I/O line 12. 12 1 P13 Input Change interrupt status on the I/O line 13. 13 1 P14 Input Change interrupt status on the I/O line 14. 14 1 P15 Input Change interrupt status on the I/O line 15. 15 1 P16 Input Change interrupt status on the I/O line 16. 16 1 P17 Input Change interrupt status on the I/O line 17. 17 1 P18 Input Change interrupt status on the I/O line 18. 18 1 P19 Input Change interrupt status on the I/O line 19. 19 1 P20 Input Change interrupt status on the I/O line 20. 20 1 P21 Input Change interrupt status on the I/O line 21. 21 1 P22 Input Change interrupt status on the I/O line 22. 22 1 P23 Input Change interrupt status on the I/O line 23. 23 1 P24 Input Change interrupt status on the I/O line 24. 24 1 P25 Input Change interrupt status on the I/O line 25. 25 1 P26 Input Change interrupt status on the I/O line 26. 26 1 P27 Input Change interrupt status on the I/O line 27. 27 1 P28 Input Change interrupt status on the I/O line 28. 28 1 P29 Input Change interrupt status on the I/O line 29. 29 1 P30 Input Change interrupt status on the I/O line 30. 30 1 P31 Input Change interrupt status on the I/O line 31. 31 1 PIO_ISR1 PIO Interrupt Status Register 0x06C read-only P0 Input Change interrupt status on the I/O line 0. 0 1 P1 Input Change interrupt status on the I/O line 1. 1 1 P2 Input Change interrupt status on the I/O line 2. 2 1 P3 Input Change interrupt status on the I/O line 3. 3 1 P4 Input Change interrupt status on the I/O line 4. 4 1 P5 Input Change interrupt status on the I/O line 5. 5 1 P6 Input Change interrupt status on the I/O line 6. 6 1 P7 Input Change interrupt status on the I/O line 7. 7 1 P8 Input Change interrupt status on the I/O line 8. 8 1 P9 Input Change interrupt status on the I/O line 9. 9 1 P10 Input Change interrupt status on the I/O line 10. 10 1 P11 Input Change interrupt status on the I/O line 11. 11 1 P12 Input Change interrupt status on the I/O line 12. 12 1 P13 Input Change interrupt status on the I/O line 13. 13 1 P14 Input Change interrupt status on the I/O line 14. 14 1 P15 Input Change interrupt status on the I/O line 15. 15 1 P16 Input Change interrupt status on the I/O line 16. 16 1 P17 Input Change interrupt status on the I/O line 17. 17 1 P18 Input Change interrupt status on the I/O line 18. 18 1 P19 Input Change interrupt status on the I/O line 19. 19 1 P20 Input Change interrupt status on the I/O line 20. 20 1 P21 Input Change interrupt status on the I/O line 21. 21 1 P22 Input Change interrupt status on the I/O line 22. 22 1 P23 Input Change interrupt status on the I/O line 23. 23 1 P24 Input Change interrupt status on the I/O line 24. 24 1 P25 Input Change interrupt status on the I/O line 25. 25 1 P26 Input Change interrupt status on the I/O line 26. 26 1 P27 Input Change interrupt status on the I/O line 27. 27 1 P28 Input Change interrupt status on the I/O line 28. 28 1 P29 Input Change interrupt status on the I/O line 29. 29 1 P30 Input Change interrupt status on the I/O line 30. 30 1 P31 Input Change interrupt status on the I/O line 31. 31 1 PIO_ISR2 PIO Interrupt Status Register 0x0AC read-only P0 Input Change interrupt status on the I/O line 0. 0 1 P1 Input Change interrupt status on the I/O line 1. 1 1 P2 Input Change interrupt status on the I/O line 2. 2 1 P3 Input Change interrupt status on the I/O line 3. 3 1 P4 Input Change interrupt status on the I/O line 4. 4 1 P5 Input Change interrupt status on the I/O line 5. 5 1 P6 Input Change interrupt status on the I/O line 6. 6 1 P7 Input Change interrupt status on the I/O line 7. 7 1 P8 Input Change interrupt status on the I/O line 8. 8 1 P9 Input Change interrupt status on the I/O line 9. 9 1 P10 Input Change interrupt status on the I/O line 10. 10 1 P11 Input Change interrupt status on the I/O line 11. 11 1 P12 Input Change interrupt status on the I/O line 12. 12 1 P13 Input Change interrupt status on the I/O line 13. 13 1 P14 Input Change interrupt status on the I/O line 14. 14 1 P15 Input Change interrupt status on the I/O line 15. 15 1 P16 Input Change interrupt status on the I/O line 16. 16 1 P17 Input Change interrupt status on the I/O line 17. 17 1 P18 Input Change interrupt status on the I/O line 18. 18 1 P19 Input Change interrupt status on the I/O line 19. 19 1 P20 Input Change interrupt status on the I/O line 20. 20 1 P21 Input Change interrupt status on the I/O line 21. 21 1 P22 Input Change interrupt status on the I/O line 22. 22 1 P23 Input Change interrupt status on the I/O line 23. 23 1 P24 Input Change interrupt status on the I/O line 24. 24 1 P25 Input Change interrupt status on the I/O line 25. 25 1 P26 Input Change interrupt status on the I/O line 26. 26 1 P27 Input Change interrupt status on the I/O line 27. 27 1 P28 Input Change interrupt status on the I/O line 28. 28 1 P29 Input Change interrupt status on the I/O line 29. 29 1 P30 Input Change interrupt status on the I/O line 30. 30 1 P31 Input Change interrupt status on the I/O line 31. 31 1 PIO_ISR3 PIO Interrupt Status Register 0x0EC read-only P0 Input Change interrupt status on the I/O line 0. 0 1 P1 Input Change interrupt status on the I/O line 1. 1 1 P2 Input Change interrupt status on the I/O line 2. 2 1 P3 Input Change interrupt status on the I/O line 3. 3 1 P4 Input Change interrupt status on the I/O line 4. 4 1 P5 Input Change interrupt status on the I/O line 5. 5 1 P6 Input Change interrupt status on the I/O line 6. 6 1 P7 Input Change interrupt status on the I/O line 7. 7 1 P8 Input Change interrupt status on the I/O line 8. 8 1 P9 Input Change interrupt status on the I/O line 9. 9 1 P10 Input Change interrupt status on the I/O line 10. 10 1 P11 Input Change interrupt status on the I/O line 11. 11 1 P12 Input Change interrupt status on the I/O line 12. 12 1 P13 Input Change interrupt status on the I/O line 13. 13 1 P14 Input Change interrupt status on the I/O line 14. 14 1 P15 Input Change interrupt status on the I/O line 15. 15 1 P16 Input Change interrupt status on the I/O line 16. 16 1 P17 Input Change interrupt status on the I/O line 17. 17 1 P18 Input Change interrupt status on the I/O line 18. 18 1 P19 Input Change interrupt status on the I/O line 19. 19 1 P20 Input Change interrupt status on the I/O line 20. 20 1 P21 Input Change interrupt status on the I/O line 21. 21 1 P22 Input Change interrupt status on the I/O line 22. 22 1 P23 Input Change interrupt status on the I/O line 23. 23 1 P24 Input Change interrupt status on the I/O line 24. 24 1 P25 Input Change interrupt status on the I/O line 25. 25 1 P26 Input Change interrupt status on the I/O line 26. 26 1 P27 Input Change interrupt status on the I/O line 27. 27 1 P28 Input Change interrupt status on the I/O line 28. 28 1 P29 Input Change interrupt status on the I/O line 29. 29 1 P30 Input Change interrupt status on the I/O line 30. 30 1 P31 Input Change interrupt status on the I/O line 31. 31 1 PIO_IOFR0 PIO Freeze Configuration Register. 0x03C write-only FRZKEY Freeze Key. 8 24 FRZKEY read-write PASSWD Freeze key. 0x494F46 FINT Freeze Interrupt Configuration. 1 1 FINT read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): IFEN, IFSCEN and EVTSEL. 1 FPHY Freeze Physical Configuration. 0 1 FPHY read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): FUNC, DIR, PUEN, PDEN, OPD, SCHMITT and DRVSTR. 1 PIO_IOFR1 PIO Freeze Configuration Register. 0x07C write-only FRZKEY Freeze Key. 8 24 FRZKEY read-write PASSWD Freeze key. 0x494F46 FINT Freeze Interrupt Configuration. 1 1 FINT read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): IFEN, IFSCEN and EVTSEL. 1 FPHY Freeze Physical Configuration. 0 1 FPHY read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): FUNC, DIR, PUEN, PDEN, OPD, SCHMITT and DRVSTR. 1 PIO_IOFR2 PIO Freeze Configuration Register. 0x0BC write-only FRZKEY Freeze Key. 8 24 FRZKEY read-write PASSWD Freeze key. 0x494F46 FINT Freeze Interrupt Configuration. 1 1 FINT read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): IFEN, IFSCEN and EVTSEL. 1 FPHY Freeze Physical Configuration. 0 1 FPHY read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): FUNC, DIR, PUEN, PDEN, OPD, SCHMITT and DRVSTR. 1 PIO_IOFR3 PIO Freeze Configuration Register. 0x0FC write-only FRZKEY Freeze Key. 8 24 FRZKEY read-write PASSWD Freeze key. 0x494F46 FINT Freeze Interrupt Configuration. 1 1 FINT read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): IFEN, IFSCEN and EVTSEL. 1 FPHY Freeze Physical Configuration. 0 1 FPHY read-write NONE No effect. 0 FREEZE Freezes the following configuration of Non-Secure I/O lines if FRZKEY corresponds to 0x494F46, ("IOF" in ASCII): FUNC, DIR, PUEN, PDEN, OPD, SCHMITT and DRVSTR. 1 PIO_SIONR0 PIO Set I/O Non-Secure Register 0x030 write-only P0 Set the I/O line 0 in Non-Secure mode. 0 1 P1 Set the I/O line 1 in Non-Secure mode. 1 1 P2 Set the I/O line 2 in Non-Secure mode. 2 1 P3 Set the I/O line 3 in Non-Secure mode. 3 1 P4 Set the I/O line 4 in Non-Secure mode. 4 1 P5 Set the I/O line 5 in Non-Secure mode. 5 1 P6 Set the I/O line 6 in Non-Secure mode. 6 1 P7 Set the I/O line 7 in Non-Secure mode. 7 1 P8 Set the I/O line 8 in Non-Secure mode. 8 1 P9 Set the I/O line 9 in Non-Secure mode. 9 1 P10 Set the I/O line 10 in Non-Secure mode. 10 1 P11 Set the I/O line 11 in Non-Secure mode. 11 1 P12 Set the I/O line 12 in Non-Secure mode. 12 1 P13 Set the I/O line 13 in Non-Secure mode. 13 1 P14 Set the I/O line 14 in Non-Secure mode. 14 1 P15 Set the I/O line 15 in Non-Secure mode. 15 1 P16 Set the I/O line 16 in Non-Secure mode. 16 1 P17 Set the I/O line 17 in Non-Secure mode. 17 1 P18 Set the I/O line 18 in Non-Secure mode. 18 1 P19 Set the I/O line 19 in Non-Secure mode. 19 1 P20 Set the I/O line 20 in Non-Secure mode. 20 1 P21 Set the I/O line 21 in Non-Secure mode. 21 1 P22 Set the I/O line 22 in Non-Secure mode. 22 1 P23 Set the I/O line 23 in Non-Secure mode. 23 1 P24 Set the I/O line 24 in Non-Secure mode. 24 1 P25 Set the I/O line 25 in Non-Secure mode. 25 1 P26 Set the I/O line 26 in Non-Secure mode. 26 1 P27 Set the I/O line 27 in Non-Secure mode. 27 1 P28 Set the I/O line 28 in Non-Secure mode. 28 1 P29 Set the I/O line 29 in Non-Secure mode. 29 1 P30 Set the I/O line 30 in Non-Secure mode. 30 1 P31 Set the I/O line 31 in Non-Secure mode. 31 1 PIO_SIONR1 PIO Set I/O Non-Secure Register 0x070 write-only P0 Set the I/O line 0 in Non-Secure mode. 0 1 P1 Set the I/O line 1 in Non-Secure mode. 1 1 P2 Set the I/O line 2 in Non-Secure mode. 2 1 P3 Set the I/O line 3 in Non-Secure mode. 3 1 P4 Set the I/O line 4 in Non-Secure mode. 4 1 P5 Set the I/O line 5 in Non-Secure mode. 5 1 P6 Set the I/O line 6 in Non-Secure mode. 6 1 P7 Set the I/O line 7 in Non-Secure mode. 7 1 P8 Set the I/O line 8 in Non-Secure mode. 8 1 P9 Set the I/O line 9 in Non-Secure mode. 9 1 P10 Set the I/O line 10 in Non-Secure mode. 10 1 P11 Set the I/O line 11 in Non-Secure mode. 11 1 P12 Set the I/O line 12 in Non-Secure mode. 12 1 P13 Set the I/O line 13 in Non-Secure mode. 13 1 P14 Set the I/O line 14 in Non-Secure mode. 14 1 P15 Set the I/O line 15 in Non-Secure mode. 15 1 P16 Set the I/O line 16 in Non-Secure mode. 16 1 P17 Set the I/O line 17 in Non-Secure mode. 17 1 P18 Set the I/O line 18 in Non-Secure mode. 18 1 P19 Set the I/O line 19 in Non-Secure mode. 19 1 P20 Set the I/O line 20 in Non-Secure mode. 20 1 P21 Set the I/O line 21 in Non-Secure mode. 21 1 P22 Set the I/O line 22 in Non-Secure mode. 22 1 P23 Set the I/O line 23 in Non-Secure mode. 23 1 P24 Set the I/O line 24 in Non-Secure mode. 24 1 P25 Set the I/O line 25 in Non-Secure mode. 25 1 P26 Set the I/O line 26 in Non-Secure mode. 26 1 P27 Set the I/O line 27 in Non-Secure mode. 27 1 P28 Set the I/O line 28 in Non-Secure mode. 28 1 P29 Set the I/O line 29 in Non-Secure mode. 29 1 P30 Set the I/O line 30 in Non-Secure mode. 30 1 P31 Set the I/O line 31 in Non-Secure mode. 31 1 PIO_SIONR2 PIO Set I/O Non-Secure Register 0x0B0 write-only P0 Set the I/O line 0 in Non-Secure mode. 0 1 P1 Set the I/O line 1 in Non-Secure mode. 1 1 P2 Set the I/O line 2 in Non-Secure mode. 2 1 P3 Set the I/O line 3 in Non-Secure mode. 3 1 P4 Set the I/O line 4 in Non-Secure mode. 4 1 P5 Set the I/O line 5 in Non-Secure mode. 5 1 P6 Set the I/O line 6 in Non-Secure mode. 6 1 P7 Set the I/O line 7 in Non-Secure mode. 7 1 P8 Set the I/O line 8 in Non-Secure mode. 8 1 P9 Set the I/O line 9 in Non-Secure mode. 9 1 P10 Set the I/O line 10 in Non-Secure mode. 10 1 P11 Set the I/O line 11 in Non-Secure mode. 11 1 P12 Set the I/O line 12 in Non-Secure mode. 12 1 P13 Set the I/O line 13 in Non-Secure mode. 13 1 P14 Set the I/O line 14 in Non-Secure mode. 14 1 P15 Set the I/O line 15 in Non-Secure mode. 15 1 P16 Set the I/O line 16 in Non-Secure mode. 16 1 P17 Set the I/O line 17 in Non-Secure mode. 17 1 P18 Set the I/O line 18 in Non-Secure mode. 18 1 P19 Set the I/O line 19 in Non-Secure mode. 19 1 P20 Set the I/O line 20 in Non-Secure mode. 20 1 P21 Set the I/O line 21 in Non-Secure mode. 21 1 P22 Set the I/O line 22 in Non-Secure mode. 22 1 P23 Set the I/O line 23 in Non-Secure mode. 23 1 P24 Set the I/O line 24 in Non-Secure mode. 24 1 P25 Set the I/O line 25 in Non-Secure mode. 25 1 P26 Set the I/O line 26 in Non-Secure mode. 26 1 P27 Set the I/O line 27 in Non-Secure mode. 27 1 P28 Set the I/O line 28 in Non-Secure mode. 28 1 P29 Set the I/O line 29 in Non-Secure mode. 29 1 P30 Set the I/O line 30 in Non-Secure mode. 30 1 P31 Set the I/O line 31 in Non-Secure mode. 31 1 PIO_SIONR3 PIO Set I/O Non-Secure Register 0x0F0 write-only P0 Set the I/O line 0 in Non-Secure mode. 0 1 P1 Set the I/O line 1 in Non-Secure mode. 1 1 P2 Set the I/O line 2 in Non-Secure mode. 2 1 P3 Set the I/O line 3 in Non-Secure mode. 3 1 P4 Set the I/O line 4 in Non-Secure mode. 4 1 P5 Set the I/O line 5 in Non-Secure mode. 5 1 P6 Set the I/O line 6 in Non-Secure mode. 6 1 P7 Set the I/O line 7 in Non-Secure mode. 7 1 P8 Set the I/O line 8 in Non-Secure mode. 8 1 P9 Set the I/O line 9 in Non-Secure mode. 9 1 P10 Set the I/O line 10 in Non-Secure mode. 10 1 P11 Set the I/O line 11 in Non-Secure mode. 11 1 P12 Set the I/O line 12 in Non-Secure mode. 12 1 P13 Set the I/O line 13 in Non-Secure mode. 13 1 P14 Set the I/O line 14 in Non-Secure mode. 14 1 P15 Set the I/O line 15 in Non-Secure mode. 15 1 P16 Set the I/O line 16 in Non-Secure mode. 16 1 P17 Set the I/O line 17 in Non-Secure mode. 17 1 P18 Set the I/O line 18 in Non-Secure mode. 18 1 P19 Set the I/O line 19 in Non-Secure mode. 19 1 P20 Set the I/O line 20 in Non-Secure mode. 20 1 P21 Set the I/O line 21 in Non-Secure mode. 21 1 P22 Set the I/O line 22 in Non-Secure mode. 22 1 P23 Set the I/O line 23 in Non-Secure mode. 23 1 P24 Set the I/O line 24 in Non-Secure mode. 24 1 P25 Set the I/O line 25 in Non-Secure mode. 25 1 P26 Set the I/O line 26 in Non-Secure mode. 26 1 P27 Set the I/O line 27 in Non-Secure mode. 27 1 P28 Set the I/O line 28 in Non-Secure mode. 28 1 P29 Set the I/O line 29 in Non-Secure mode. 29 1 P30 Set the I/O line 30 in Non-Secure mode. 30 1 P31 Set the I/O line 31 in Non-Secure mode. 31 1 PIO_SIOSR0 PIO Set I/O Secure Register 0x034 write-only P0 Set the I/O line 0 in Secure mode. 0 1 P1 Set the I/O line 1 in Secure mode. 1 1 P2 Set the I/O line 2 in Secure mode. 2 1 P3 Set the I/O line 3 in Secure mode. 3 1 P4 Set the I/O line 4 in Secure mode. 4 1 P5 Set the I/O line 5 in Secure mode. 5 1 P6 Set the I/O line 6 in Secure mode. 6 1 P7 Set the I/O line 7 in Secure mode. 7 1 P8 Set the I/O line 8 in Secure mode. 8 1 P9 Set the I/O line 9 in Secure mode. 9 1 P10 Set the I/O line 10 in Secure mode. 10 1 P11 Set the I/O line 11 in Secure mode. 11 1 P12 Set the I/O line 12 in Secure mode. 12 1 P13 Set the I/O line 13 in Secure mode. 13 1 P14 Set the I/O line 14 in Secure mode. 14 1 P15 Set the I/O line 15 in Secure mode. 15 1 P16 Set the I/O line 16 in Secure mode. 16 1 P17 Set the I/O line 17 in Secure mode. 17 1 P18 Set the I/O line 18 in Secure mode. 18 1 P19 Set the I/O line 19 in Secure mode. 19 1 P20 Set the I/O line 20 in Secure mode. 20 1 P21 Set the I/O line 21 in Secure mode. 21 1 P22 Set the I/O line 22 in Secure mode. 22 1 P23 Set the I/O line 23 in Secure mode. 23 1 P24 Set the I/O line 24 in Secure mode. 24 1 P25 Set the I/O line 25 in Secure mode. 25 1 P26 Set the I/O line 26 in Secure mode. 26 1 P27 Set the I/O line 27 in Secure mode. 27 1 P28 Set the I/O line 28 in Secure mode. 28 1 P29 Set the I/O line 29 in Secure mode. 29 1 P30 Set the I/O line 30 in Secure mode. 30 1 P31 Set the I/O line 31 in Secure mode. 31 1 PIO_SIOSR1 PIO Set I/O Secure Register 0x074 write-only P0 Set the I/O line 0 in Secure mode. 0 1 P1 Set the I/O line 1 in Secure mode. 1 1 P2 Set the I/O line 2 in Secure mode. 2 1 P3 Set the I/O line 3 in Secure mode. 3 1 P4 Set the I/O line 4 in Secure mode. 4 1 P5 Set the I/O line 5 in Secure mode. 5 1 P6 Set the I/O line 6 in Secure mode. 6 1 P7 Set the I/O line 7 in Secure mode. 7 1 P8 Set the I/O line 8 in Secure mode. 8 1 P9 Set the I/O line 9 in Secure mode. 9 1 P10 Set the I/O line 10 in Secure mode. 10 1 P11 Set the I/O line 11 in Secure mode. 11 1 P12 Set the I/O line 12 in Secure mode. 12 1 P13 Set the I/O line 13 in Secure mode. 13 1 P14 Set the I/O line 14 in Secure mode. 14 1 P15 Set the I/O line 15 in Secure mode. 15 1 P16 Set the I/O line 16 in Secure mode. 16 1 P17 Set the I/O line 17 in Secure mode. 17 1 P18 Set the I/O line 18 in Secure mode. 18 1 P19 Set the I/O line 19 in Secure mode. 19 1 P20 Set the I/O line 20 in Secure mode. 20 1 P21 Set the I/O line 21 in Secure mode. 21 1 P22 Set the I/O line 22 in Secure mode. 22 1 P23 Set the I/O line 23 in Secure mode. 23 1 P24 Set the I/O line 24 in Secure mode. 24 1 P25 Set the I/O line 25 in Secure mode. 25 1 P26 Set the I/O line 26 in Secure mode. 26 1 P27 Set the I/O line 27 in Secure mode. 27 1 P28 Set the I/O line 28 in Secure mode. 28 1 P29 Set the I/O line 29 in Secure mode. 29 1 P30 Set the I/O line 30 in Secure mode. 30 1 P31 Set the I/O line 31 in Secure mode. 31 1 PIO_SIOSR2 PIO Set I/O Secure Register 0x0B4 write-only P0 Set the I/O line 0 in Secure mode. 0 1 P1 Set the I/O line 1 in Secure mode. 1 1 P2 Set the I/O line 2 in Secure mode. 2 1 P3 Set the I/O line 3 in Secure mode. 3 1 P4 Set the I/O line 4 in Secure mode. 4 1 P5 Set the I/O line 5 in Secure mode. 5 1 P6 Set the I/O line 6 in Secure mode. 6 1 P7 Set the I/O line 7 in Secure mode. 7 1 P8 Set the I/O line 8 in Secure mode. 8 1 P9 Set the I/O line 9 in Secure mode. 9 1 P10 Set the I/O line 10 in Secure mode. 10 1 P11 Set the I/O line 11 in Secure mode. 11 1 P12 Set the I/O line 12 in Secure mode. 12 1 P13 Set the I/O line 13 in Secure mode. 13 1 P14 Set the I/O line 14 in Secure mode. 14 1 P15 Set the I/O line 15 in Secure mode. 15 1 P16 Set the I/O line 16 in Secure mode. 16 1 P17 Set the I/O line 17 in Secure mode. 17 1 P18 Set the I/O line 18 in Secure mode. 18 1 P19 Set the I/O line 19 in Secure mode. 19 1 P20 Set the I/O line 20 in Secure mode. 20 1 P21 Set the I/O line 21 in Secure mode. 21 1 P22 Set the I/O line 22 in Secure mode. 22 1 P23 Set the I/O line 23 in Secure mode. 23 1 P24 Set the I/O line 24 in Secure mode. 24 1 P25 Set the I/O line 25 in Secure mode. 25 1 P26 Set the I/O line 26 in Secure mode. 26 1 P27 Set the I/O line 27 in Secure mode. 27 1 P28 Set the I/O line 28 in Secure mode. 28 1 P29 Set the I/O line 29 in Secure mode. 29 1 P30 Set the I/O line 30 in Secure mode. 30 1 P31 Set the I/O line 31 in Secure mode. 31 1 PIO_SIOSR3 PIO Set I/O Secure Register 0x0F4 write-only P0 Set the I/O line 0 in Secure mode. 0 1 P1 Set the I/O line 1 in Secure mode. 1 1 P2 Set the I/O line 2 in Secure mode. 2 1 P3 Set the I/O line 3 in Secure mode. 3 1 P4 Set the I/O line 4 in Secure mode. 4 1 P5 Set the I/O line 5 in Secure mode. 5 1 P6 Set the I/O line 6 in Secure mode. 6 1 P7 Set the I/O line 7 in Secure mode. 7 1 P8 Set the I/O line 8 in Secure mode. 8 1 P9 Set the I/O line 9 in Secure mode. 9 1 P10 Set the I/O line 10 in Secure mode. 10 1 P11 Set the I/O line 11 in Secure mode. 11 1 P12 Set the I/O line 12 in Secure mode. 12 1 P13 Set the I/O line 13 in Secure mode. 13 1 P14 Set the I/O line 14 in Secure mode. 14 1 P15 Set the I/O line 15 in Secure mode. 15 1 P16 Set the I/O line 16 in Secure mode. 16 1 P17 Set the I/O line 17 in Secure mode. 17 1 P18 Set the I/O line 18 in Secure mode. 18 1 P19 Set the I/O line 19 in Secure mode. 19 1 P20 Set the I/O line 20 in Secure mode. 20 1 P21 Set the I/O line 21 in Secure mode. 21 1 P22 Set the I/O line 22 in Secure mode. 22 1 P23 Set the I/O line 23 in Secure mode. 23 1 P24 Set the I/O line 24 in Secure mode. 24 1 P25 Set the I/O line 25 in Secure mode. 25 1 P26 Set the I/O line 26 in Secure mode. 26 1 P27 Set the I/O line 27 in Secure mode. 27 1 P28 Set the I/O line 28 in Secure mode. 28 1 P29 Set the I/O line 29 in Secure mode. 29 1 P30 Set the I/O line 30 in Secure mode. 30 1 P31 Set the I/O line 31 in Secure mode. 31 1 PIO_IOSSR0 PIO Set I/O Secure Register 0x038 read-only P0 I/O line 0 security status. 0 1 P1 I/O line 1 security status. 1 1 P2 I/O line 2 security status. 2 1 P3 I/O line 3 security status. 3 1 P4 I/O line 4 security status. 4 1 P5 I/O line 5 security status. 5 1 P6 I/O line 6 security status. 6 1 P7 I/O line 7 security status. 7 1 P8 I/O line 8 security status. 8 1 P9 I/O line 9 security status. 9 1 P10 I/O line 10 security status. 10 1 P11 I/O line 11 security status. 11 1 P12 I/O line 12 security status. 12 1 P13 I/O line 13 security status. 13 1 P14 I/O line 14 security status. 14 1 P15 I/O line 15 security status. 15 1 P16 I/O line 16 security status. 16 1 P17 I/O line 17 security status. 17 1 P18 I/O line 18 security status. 18 1 P19 I/O line 19 security status. 19 1 P20 I/O line 20 security status. 20 1 P21 I/O line 21 security status. 21 1 P22 I/O line 22 security status. 22 1 P23 I/O line 23 security status. 23 1 P24 I/O line 24 security status. 24 1 P25 I/O line 25 security status. 25 1 P26 I/O line 26 security status. 26 1 P27 I/O line 27 security status. 27 1 P28 I/O line 28 security status. 28 1 P29 I/O line 29 security status. 29 1 P30 I/O line 30 security status. 30 1 P31 I/O line 31 security status. 31 1 PIO_IOSSR1 PIO Set I/O Secure Register 0x078 read-only P0 I/O line 0 security status. 0 1 P1 I/O line 1 security status. 1 1 P2 I/O line 2 security status. 2 1 P3 I/O line 3 security status. 3 1 P4 I/O line 4 security status. 4 1 P5 I/O line 5 security status. 5 1 P6 I/O line 6 security status. 6 1 P7 I/O line 7 security status. 7 1 P8 I/O line 8 security status. 8 1 P9 I/O line 9 security status. 9 1 P10 I/O line 10 security status. 10 1 P11 I/O line 11 security status. 11 1 P12 I/O line 12 security status. 12 1 P13 I/O line 13 security status. 13 1 P14 I/O line 14 security status. 14 1 P15 I/O line 15 security status. 15 1 P16 I/O line 16 security status. 16 1 P17 I/O line 17 security status. 17 1 P18 I/O line 18 security status. 18 1 P19 I/O line 19 security status. 19 1 P20 I/O line 20 security status. 20 1 P21 I/O line 21 security status. 21 1 P22 I/O line 22 security status. 22 1 P23 I/O line 23 security status. 23 1 P24 I/O line 24 security status. 24 1 P25 I/O line 25 security status. 25 1 P26 I/O line 26 security status. 26 1 P27 I/O line 27 security status. 27 1 P28 I/O line 28 security status. 28 1 P29 I/O line 29 security status. 29 1 P30 I/O line 30 security status. 30 1 P31 I/O line 31 security status. 31 1 PIO_IOSSR2 PIO Set I/O Secure Register 0x0B8 read-only P0 I/O line 0 security status. 0 1 P1 I/O line 1 security status. 1 1 P2 I/O line 2 security status. 2 1 P3 I/O line 3 security status. 3 1 P4 I/O line 4 security status. 4 1 P5 I/O line 5 security status. 5 1 P6 I/O line 6 security status. 6 1 P7 I/O line 7 security status. 7 1 P8 I/O line 8 security status. 8 1 P9 I/O line 9 security status. 9 1 P10 I/O line 10 security status. 10 1 P11 I/O line 11 security status. 11 1 P12 I/O line 12 security status. 12 1 P13 I/O line 13 security status. 13 1 P14 I/O line 14 security status. 14 1 P15 I/O line 15 security status. 15 1 P16 I/O line 16 security status. 16 1 P17 I/O line 17 security status. 17 1 P18 I/O line 18 security status. 18 1 P19 I/O line 19 security status. 19 1 P20 I/O line 20 security status. 20 1 P21 I/O line 21 security status. 21 1 P22 I/O line 22 security status. 22 1 P23 I/O line 23 security status. 23 1 P24 I/O line 24 security status. 24 1 P25 I/O line 25 security status. 25 1 P26 I/O line 26 security status. 26 1 P27 I/O line 27 security status. 27 1 P28 I/O line 28 security status. 28 1 P29 I/O line 29 security status. 29 1 P30 I/O line 30 security status. 30 1 P31 I/O line 31 security status. 31 1 PIO_IOSSR3 PIO Set I/O Secure Register 0x0F8 read-only P0 I/O line 0 security status. 0 1 P1 I/O line 1 security status. 1 1 P2 I/O line 2 security status. 2 1 P3 I/O line 3 security status. 3 1 P4 I/O line 4 security status. 4 1 P5 I/O line 5 security status. 5 1 P6 I/O line 6 security status. 6 1 P7 I/O line 7 security status. 7 1 P8 I/O line 8 security status. 8 1 P9 I/O line 9 security status. 9 1 P10 I/O line 10 security status. 10 1 P11 I/O line 11 security status. 11 1 P12 I/O line 12 security status. 12 1 P13 I/O line 13 security status. 13 1 P14 I/O line 14 security status. 14 1 P15 I/O line 15 security status. 15 1 P16 I/O line 16 security status. 16 1 P17 I/O line 17 security status. 17 1 P18 I/O line 18 security status. 18 1 P19 I/O line 19 security status. 19 1 P20 I/O line 20 security status. 20 1 P21 I/O line 21 security status. 21 1 P22 I/O line 22 security status. 22 1 P23 I/O line 23 security status. 23 1 P24 I/O line 24 security status. 24 1 P25 I/O line 25 security status. 25 1 P26 I/O line 26 security status. 26 1 P27 I/O line 27 security status. 27 1 P28 I/O line 28 security status. 28 1 P29 I/O line 29 security status. 29 1 P30 I/O line 30 security status. 30 1 P31 I/O line 31 security status. 31 1 PIO_SCDR PIO Slow Clock Divider Debouncing Register 0x500 read-write DIV I/O Security Status. 0 14 0 16383