cramium SOC 8 32 32 read-write 0x00000000 0xFFFFFFFF PL230 PL230 DMA Controller Core 1073811456 0x0 0x40 registers 0x40 0xc reserved 0x4c 0x4 registers STATUS DMA Status Register 0x00 32 read-only 0x101f0000 0xffffff0f TEST_STATUS Test status configuration 28 4 read-only CHNLS_MINUS1 Number of available DMA channels minus 1 16 5 read-only STATE Current state of the control machine 4 4 read-only MASTER_ENABLE Master enable status 0 1 read-only CFG DMA Configuration Register 0x04 32 write-only 0x00000000 0x00000000 CHNL_PROT_CTRL Set AHB-Lite configuration 5 3 read-only MASTER_ENABLE MASTER_ENABLE 0 1 write-only CTRLBASEPTR DMA Control Data Base Pointer Register 0x08 32 read-write 0x00000000 0xffffffff CTRL_BASE_PTR CTRL_BASE_PTR 8 24 read-write ALTCTRLBASEPTR DMA Channel Alternate Control Data Base Pointer Register 0x0C 32 read-only 0x00000000 0xffffffff ALT_CTRL_BASE_PTR ALT_CTRL_BASE_PTR 0 32 read-only DMA_WAITONREQ_STATUS Channel wait on request status 0x10 32 read-only 0x00000000 0xffffffff DMA_WAITONREQ_STATUS Wait on request status, one bit per channel 0 8 read-only CHNLSWREQUEST DMA Channel Software Request Register 0x14 32 write-only 0x00000000 0x00000000 CHNL_SW_REQUEST CHNL_SW_REQUEST 0 8 write-only CHNLUSEBURSTSET DMA Channel Useburst Set Register 0x18 32 read-write 0x00000000 0xffffffff CHNL_USEBURST_SET CHNL_USEBURST_SET 0 8 read-write CHNLUSEBURSTCLR DMA Channel Useburst Clear Register 0x1C 32 write-only 0x00000000 0x00000000 CHNL_USEBURST_CLR CHNL_USEBURST_CLR 0 8 write-only CHNLREQMASKSET DMA Channel Request Mask Set Register 0x20 32 read-write 0x00000000 0xffffffff CHNL_REQ_MASK_SET CHNL_REQ_MASK_SET 0 8 read-write CHNLREQMASKCLR DMA Channel Request Mask Clear Register 0x24 32 write-only 0x00000000 0x00000000 CHNL_REQ_MASK_CLR CHNL_REQ_MASK_CLR 0 8 write-only CHNLENABLESET DMA Channel Enable Set Register 0x28 32 read-write 0x00000000 0xffffffff CHNL_ENABLE_SET CHNL_ENABLE_SET 0 8 read-write CHNLENABLECLR DMA Channel Enable Clear Register 0x2C 32 write-only 0x00000000 0x00000000 CHNL_ENABLE_CLR CHNL_ENABLE_CLR 0 8 write-only CHNLPRIALTSET DMA Channel Primary-Alternate Set Register 0x30 32 read-write 0x00000000 0xffffffff CHNL_PRI_ALT_SET CHNL_PRI_ALT_SET 0 8 read-write CHNLPRIALTCLR DMA Channel Primary-Alternate Clear Register 0x34 32 write-only 0x00000000 0x00000000 CHNL_PRI_ALT_CLR CHNL_PRI_ALT_CLR 0 8 write-only CHNLPRIORITYSET DMA Channel Priority Set Register 0x38 32 read-write 0x00000000 0xffffffff CHNL_PRIORITY_SET CHNL_PRIORITY_SET 0 8 read-write CHNLPRIORITYCLR DMA Channel Priority Clear Register 0x3C 32 write-only 0x00000000 0x00000000 CHNL_PRIORITY_CLR CHNL_PRIORITY_CLR 0 8 write-only ERRCLR DMA Bus Error Clear Register 0x4C 32 read-write 0x00000000 0xffffffff ERR_CLR ERR_CLR 0 1 read-write PERIPH_ID_0 Peripheral ID byte 0 0xFE0 32 read-write 0x00000000 0xffffffff PART_NUMBER_LSB Identifies the part number 0 8 read-only PERIPH_ID_1 Peripheral ID byte 1 0xFE4 32 read-write 0x00000000 0xffffffff PART_NUMBER_MSB Identifies the part number 0 4 read-only JEP106_LSB Designer ID LSB 4 3 read-only PERIPH_ID_2 Peripheral ID byte 2 0xFE8 32 read-write 0x00000000 0xffffffff JEP106_MSB Designer ID MSB 0 3 read-only JEDEC_USED Identifies if JP106 ID code is used 3 1 read-only REVISION Identifies revision number of peripheral 4 4 read-only UDMA_CTRL 0x50100000 UDMA_CTRL REG_CG 0x0000 0x00 32 r_cg 5 [5:0] 0 REG_CFG_EVT 0x0004 0x00 32 r_cmp_evt_0 7 [7:0] 0 r_cmp_evt_1 15 [15:8] 8 r_cmp_evt_2 23 [23:16] 16 r_cmp_evt_3 31 [31:24] 24 REG_RST 0x0008 0x00 32 r_rst 5 [5:0] 0 0 0xc registers UDMA_UART_0 0x50101000 UDMA_UART_0 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_STATUS 0x0020 0x00 32 status_i 0 [0:0] 0 REG_UART_SETUP 0x0024 0x00 32 r_uart_parity_en 0 [0:0] 0 r_uart_bits 2 [2:1] 1 r_uart_stop_bits 3 [3:3] 3 r_uart_rx_polling_en 4 [4:4] 4 r_uart_rx_clean_fifo 5 [5:5] 5 r_uart_en_tx 8 [8:8] 8 r_uart_en_rx 9 [9:9] 9 r_uart_div 31 [31:16] 16 REG_ERROR 0x0028 0x00 32 r_err_overflow 0 [0:0] 0 r_err_parity 1 [1:1] 1 REG_IRQ_EN 0x002c 0x00 32 r_uart_rx_irq_en 0 [0:0] 0 r_uart_err_irq_en 1 [1:1] 1 REG_VALID 0x0030 0x00 32 r_uart_rx_data_valid 0 [0:0] 0 REG_DATA 0x0034 0x00 32 r_uart_rx_data 7 [7:0] 0 0 0x38 registers UDMA_UART_1 0x50102000 UDMA_UART_1 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_STATUS 0x0020 0x00 32 status_i 0 [0:0] 0 REG_UART_SETUP 0x0024 0x00 32 r_uart_parity_en 0 [0:0] 0 r_uart_bits 2 [2:1] 1 r_uart_stop_bits 3 [3:3] 3 r_uart_rx_polling_en 4 [4:4] 4 r_uart_rx_clean_fifo 5 [5:5] 5 r_uart_en_tx 8 [8:8] 8 r_uart_en_rx 9 [9:9] 9 r_uart_div 31 [31:16] 16 REG_ERROR 0x0028 0x00 32 r_err_overflow 0 [0:0] 0 r_err_parity 1 [1:1] 1 REG_IRQ_EN 0x002c 0x00 32 r_uart_rx_irq_en 0 [0:0] 0 r_uart_err_irq_en 1 [1:1] 1 REG_VALID 0x0030 0x00 32 r_uart_rx_data_valid 0 [0:0] 0 REG_DATA 0x0034 0x00 32 r_uart_rx_data 7 [7:0] 0 0 0x38 registers UDMA_UART_2 0x50103000 UDMA_UART_2 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_STATUS 0x0020 0x00 32 status_i 0 [0:0] 0 REG_UART_SETUP 0x0024 0x00 32 r_uart_parity_en 0 [0:0] 0 r_uart_bits 2 [2:1] 1 r_uart_stop_bits 3 [3:3] 3 r_uart_rx_polling_en 4 [4:4] 4 r_uart_rx_clean_fifo 5 [5:5] 5 r_uart_en_tx 8 [8:8] 8 r_uart_en_rx 9 [9:9] 9 r_uart_div 31 [31:16] 16 REG_ERROR 0x0028 0x00 32 r_err_overflow 0 [0:0] 0 r_err_parity 1 [1:1] 1 REG_IRQ_EN 0x002c 0x00 32 r_uart_rx_irq_en 0 [0:0] 0 r_uart_err_irq_en 1 [1:1] 1 REG_VALID 0x0030 0x00 32 r_uart_rx_data_valid 0 [0:0] 0 REG_DATA 0x0034 0x00 32 r_uart_rx_data 7 [7:0] 0 0 0x38 registers UDMA_UART_3 0x50104000 UDMA_UART_3 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_STATUS 0x0020 0x00 32 status_i 0 [0:0] 0 REG_UART_SETUP 0x0024 0x00 32 r_uart_parity_en 0 [0:0] 0 r_uart_bits 2 [2:1] 1 r_uart_stop_bits 3 [3:3] 3 r_uart_rx_polling_en 4 [4:4] 4 r_uart_rx_clean_fifo 5 [5:5] 5 r_uart_en_tx 8 [8:8] 8 r_uart_en_rx 9 [9:9] 9 r_uart_div 31 [31:16] 16 REG_ERROR 0x0028 0x00 32 r_err_overflow 0 [0:0] 0 r_err_parity 1 [1:1] 1 REG_IRQ_EN 0x002c 0x00 32 r_uart_rx_irq_en 0 [0:0] 0 r_uart_err_irq_en 1 [1:1] 1 REG_VALID 0x0030 0x00 32 r_uart_rx_data_valid 0 [0:0] 0 REG_DATA 0x0034 0x00 32 r_uart_rx_data 7 [7:0] 0 0 0x38 registers UDMA_SPIM_0 0x50105000 UDMA_SPIM_0 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_datasize 2 [2:1] 1 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_datasize 2 [2:1] 1 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_CMD_SADDR 0x0020 0x00 32 r_cmd_startaddr 11 [11:0] 0 REG_CMD_SIZE 0x0024 0x00 32 r_cmd_size 15 [15:0] 0 REG_CMD_CFG 0x0028 0x00 32 r_cmd_continuous 0 [0:0] 0 r_cmd_en 4 [4:4] 4 r_cmd_clr 6 [6:6] 6 REG_STATUS 0x0030 0x00 32 status_i 0 [0:0] 0 0 0x34 registers UDMA_SPIM_1 0x50106000 UDMA_SPIM_1 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_datasize 2 [2:1] 1 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_datasize 2 [2:1] 1 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_CMD_SADDR 0x0020 0x00 32 r_cmd_startaddr 11 [11:0] 0 REG_CMD_SIZE 0x0024 0x00 32 r_cmd_size 15 [15:0] 0 REG_CMD_CFG 0x0028 0x00 32 r_cmd_continuous 0 [0:0] 0 r_cmd_en 4 [4:4] 4 r_cmd_clr 6 [6:6] 6 REG_STATUS 0x0030 0x00 32 status_i 0 [0:0] 0 0 0x34 registers UDMA_SPIM_2 0x50107000 UDMA_SPIM_2 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_datasize 2 [2:1] 1 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_datasize 2 [2:1] 1 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_CMD_SADDR 0x0020 0x00 32 r_cmd_startaddr 11 [11:0] 0 REG_CMD_SIZE 0x0024 0x00 32 r_cmd_size 15 [15:0] 0 REG_CMD_CFG 0x0028 0x00 32 r_cmd_continuous 0 [0:0] 0 r_cmd_en 4 [4:4] 4 r_cmd_clr 6 [6:6] 6 REG_STATUS 0x0030 0x00 32 status_i 0 [0:0] 0 0 0x34 registers UDMA_SPIM_3 0x50108000 UDMA_SPIM_3 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_datasize 2 [2:1] 1 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_datasize 2 [2:1] 1 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_CMD_SADDR 0x0020 0x00 32 r_cmd_startaddr 11 [11:0] 0 REG_CMD_SIZE 0x0024 0x00 32 r_cmd_size 15 [15:0] 0 REG_CMD_CFG 0x0028 0x00 32 r_cmd_continuous 0 [0:0] 0 r_cmd_en 4 [4:4] 4 r_cmd_clr 6 [6:6] 6 REG_STATUS 0x0030 0x00 32 status_i 0 [0:0] 0 0 0x34 registers UDMA_I2C_0 0x50109000 UDMA_I2C_0 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_CMD_SADDR 0x0020 0x00 32 r_cmd_startaddr 11 [11:0] 0 REG_CMD_SIZE 0x0024 0x00 32 r_cmd_size 15 [15:0] 0 REG_CMD_CFG 0x0028 0x00 32 r_cmd_continuous 0 [0:0] 0 r_cmd_en 4 [4:4] 4 r_cmd_clr 6 [6:6] 6 REG_STATUS 0x0030 0x00 32 r_busy 0 [0:0] 0 r_al 1 [1:1] 1 REG_SETUP 0x0034 0x00 32 r_do_rst 0 [0:0] 0 REG_ACK 0x0038 0x00 32 r_nack 0 [0:0] 0 0 0x3c registers UDMA_I2C_1 0x5010A000 UDMA_I2C_1 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_CMD_SADDR 0x0020 0x00 32 r_cmd_startaddr 11 [11:0] 0 REG_CMD_SIZE 0x0024 0x00 32 r_cmd_size 15 [15:0] 0 REG_CMD_CFG 0x0028 0x00 32 r_cmd_continuous 0 [0:0] 0 r_cmd_en 4 [4:4] 4 r_cmd_clr 6 [6:6] 6 REG_STATUS 0x0030 0x00 32 r_busy 0 [0:0] 0 r_al 1 [1:1] 1 REG_SETUP 0x0034 0x00 32 r_do_rst 0 [0:0] 0 REG_ACK 0x0038 0x00 32 r_nack 0 [0:0] 0 0 0x3c registers UDMA_I2C_2 0x5010B000 UDMA_I2C_2 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_CMD_SADDR 0x0020 0x00 32 r_cmd_startaddr 11 [11:0] 0 REG_CMD_SIZE 0x0024 0x00 32 r_cmd_size 15 [15:0] 0 REG_CMD_CFG 0x0028 0x00 32 r_cmd_continuous 0 [0:0] 0 r_cmd_en 4 [4:4] 4 r_cmd_clr 6 [6:6] 6 REG_STATUS 0x0030 0x00 32 r_busy 0 [0:0] 0 r_al 1 [1:1] 1 REG_SETUP 0x0034 0x00 32 r_do_rst 0 [0:0] 0 REG_ACK 0x0038 0x00 32 r_nack 0 [0:0] 0 0 0x3c registers UDMA_I2C_3 0x5010C000 UDMA_I2C_3 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_CMD_SADDR 0x0020 0x00 32 r_cmd_startaddr 11 [11:0] 0 REG_CMD_SIZE 0x0024 0x00 32 r_cmd_size 15 [15:0] 0 REG_CMD_CFG 0x0028 0x00 32 r_cmd_continuous 0 [0:0] 0 r_cmd_en 4 [4:4] 4 r_cmd_clr 6 [6:6] 6 REG_STATUS 0x0030 0x00 32 r_busy 0 [0:0] 0 r_al 1 [1:1] 1 REG_SETUP 0x0034 0x00 32 r_do_rst 0 [0:0] 0 REG_ACK 0x0038 0x00 32 r_nack 0 [0:0] 0 0 0x3c registers UDMA_I2S_0 0x5010D000 UDMA_I2S_0 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_datasize 2 [2:1] 1 r_rx_en 4 [4:4] 4 r_rx_clr 5 [5:5] 5 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_datasize 2 [2:1] 1 r_tx_en 4 [4:4] 4 r_tx_clr 5 [5:5] 5 REG_I2S_CLKCFG_SETUP 0x0020 0x00 32 r_master_gen_clk_div 7 [7:0] 0 r_slave_gen_clk_div 15 [15:8] 8 r_common_gen_clk_div 23 [23:16] 16 r_slave_clk_en 24 [24:24] 24 r_master_clk_en 25 [25:25] 25 r_pdm_clk_en 26 [26:26] 26 r_slave_sel_ext 28 [28:28] 28 r_slave_sel_num 29 [29:29] 29 r_master_sel_ext 30 [30:30] 30 r_master_sel_num 31 [31:31] 31 REG_I2S_SLV_SETUP 0x0024 0x00 32 r_slave_i2s_words 2 [2:0] 0 r_slave_i2s_bits_word 12 [12:8] 8 r_slave_i2s_lsb_first 16 [16:16] 16 r_slave_i2s_2ch 17 [17:17] 17 r_slave_i2s_en 31 [31:31] 31 REG_I2S_MST_SETUP 0x0028 0x00 32 r_master_i2s_words 2 [2:0] 0 r_master_i2s_bits_word 12 [12:8] 8 r_master_i2s_lsb_first 16 [16:16] 16 r_master_i2s_2ch 17 [17:17] 17 r_master_i2s_en 31 [31:31] 31 REG_I2S_PDM_SETUP 0x002c 0x00 32 r_slave_pdm_shift 2 [2:0] 0 r_slave_pdm_decimation 12 [12:3] 3 r_slave_pdm_mode 14 [14:13] 13 r_slave_pdm_en 31 [31:31] 31 0 0x30 registers UDMA_I2S_1 0x5010E000 UDMA_I2S_1 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_datasize 2 [2:1] 1 r_rx_en 4 [4:4] 4 r_rx_clr 5 [5:5] 5 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_datasize 2 [2:1] 1 r_tx_en 4 [4:4] 4 r_tx_clr 5 [5:5] 5 REG_I2S_CLKCFG_SETUP 0x0020 0x00 32 r_master_gen_clk_div 7 [7:0] 0 r_slave_gen_clk_div 15 [15:8] 8 r_common_gen_clk_div 23 [23:16] 16 r_slave_clk_en 24 [24:24] 24 r_master_clk_en 25 [25:25] 25 r_pdm_clk_en 26 [26:26] 26 r_slave_sel_ext 28 [28:28] 28 r_slave_sel_num 29 [29:29] 29 r_master_sel_ext 30 [30:30] 30 r_master_sel_num 31 [31:31] 31 REG_I2S_SLV_SETUP 0x0024 0x00 32 r_slave_i2s_words 2 [2:0] 0 r_slave_i2s_bits_word 12 [12:8] 8 r_slave_i2s_lsb_first 16 [16:16] 16 r_slave_i2s_2ch 17 [17:17] 17 r_slave_i2s_en 31 [31:31] 31 REG_I2S_MST_SETUP 0x0028 0x00 32 r_master_i2s_words 2 [2:0] 0 r_master_i2s_bits_word 12 [12:8] 8 r_master_i2s_lsb_first 16 [16:16] 16 r_master_i2s_2ch 17 [17:17] 17 r_master_i2s_en 31 [31:31] 31 REG_I2S_PDM_SETUP 0x002c 0x00 32 r_slave_pdm_shift 2 [2:0] 0 r_slave_pdm_decimation 12 [12:3] 3 r_slave_pdm_mode 14 [14:13] 13 r_slave_pdm_en 31 [31:31] 31 0 0x30 registers UDMA_CAMERA 0x5010F000 UDMA_CAMERA REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_datasize 2 [2:1] 1 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_CAM_CFG_GLOB 0x0020 0x00 32 r_cam_cfg 29 [29:0] 0 cfg_cam_ip_en_i 30 [30:30] 30 REG_CAM_CFG_LL 0x0024 0x00 32 r_cam_cfg_ll 31 [31:0] 0 REG_CAM_CFG_UR 0x0028 0x00 32 r_cam_cfg_ur 31 [31:0] 0 REG_CAM_CFG_SIZE 0x002c 0x00 32 r_cam_cfg_size 31 [31:0] 0 REG_CAM_CFG_FILTER 0x0030 0x00 32 r_cam_cfg_filter 31 [31:0] 0 REG_CAM_VSYNC_POLARITY 0x0034 0x00 32 r_cam_vsync_polarity 0 [0:0] 0 r_cam_hsync_polarity 1 [1:1] 1 0 0x38 registers UDMA_FILTER 0x50110000 UDMA_FILTER REG_TX_CH0_ADD 0x0000 0x00 32 r_filter_tx_start_addr_0 14 [14:0] 0 REG_TX_CH0_CFG 0x0004 0x00 32 r_filter_tx_datasize_0 1 [1:0] 0 r_filter_tx_mode_0 9 [9:8] 8 REG_TX_CH0_LEN0 0x0008 0x00 32 r_filter_tx_len0_0 14 [14:0] 0 REG_TX_CH0_LEN1 0x000c 0x00 32 r_filter_tx_len1_0 14 [14:0] 0 REG_TX_CH0_LEN2 0x0010 0x00 32 r_filter_tx_len2_0 14 [14:0] 0 REG_TX_CH1_ADD 0x0014 0x00 32 r_filter_tx_start_addr_1 14 [14:0] 0 REG_TX_CH1_CFG 0x0018 0x00 32 r_filter_tx_datasize_1 1 [1:0] 0 r_filter_tx_mode_1 9 [9:8] 8 REG_TX_CH1_LEN0 0x001c 0x00 32 r_filter_tx_len0_1 14 [14:0] 0 REG_TX_CH1_LEN1 0x0020 0x00 32 r_filter_tx_len1_1 14 [14:0] 0 REG_TX_CH1_LEN2 0x0024 0x00 32 r_filter_tx_len2_1 14 [14:0] 0 REG_RX_CH_ADD 0x0028 0x00 32 r_filter_rx_start_addr 14 [14:0] 0 REG_RX_CH_CFG 0x002c 0x00 32 r_filter_rx_datasize 1 [1:0] 0 r_filter_rx_mode 9 [9:8] 8 REG_RX_CH_LEN0 0x0030 0x00 32 r_filter_rx_len0 15 [15:0] 0 REG_RX_CH_LEN1 0x0034 0x00 32 r_filter_rx_len1 15 [15:0] 0 REG_RX_CH_LEN2 0x0038 0x00 32 r_filter_rx_len2 15 [15:0] 0 REG_AU_CFG 0x003c 0x00 32 r_au_use_signed 0 [0:0] 0 r_au_bypass 1 [1:1] 1 r_au_mode 11 [11:8] 8 r_au_shift 20 [20:16] 16 REG_AU_REG0 0x0040 0x00 32 r_commit_au_reg0 31 [31:0] 0 REG_AU_REG1 0x0044 0x00 32 r_commit_au_reg1 31 [31:0] 0 REG_BINCU_TH 0x0048 0x00 32 r_commit_bincu_threshold 31 [31:0] 0 REG_BINCU_CNT 0x004c 0x00 32 r_bincu_counter 14 [14:0] 0 r_bincu_en_counter 31 [31:31] 31 REG_BINCU_SETUP 0x0050 0x00 32 r_bincu_datasize 1 [1:0] 0 REG_BINCU_VAL 0x0054 0x00 32 bincu_counter_i 14 [14:0] 0 REG_FILT 0x0058 0x00 32 r_filter_mode 3 [3:0] 0 REG_STATUS 0x0060 0x00 32 r_filter_done 0 [0:0] 0 0 0x64 registers UDMA_SCIF 0x50111000 UDMA_SCIF REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 REG_STATUS 0x0020 0x00 32 status_i 0 [0:0] 0 REG_SCIF_SETUP 0x0024 0x00 32 r_scif_parity_en 0 [0:0] 0 r_scif_bits 2 [2:1] 1 r_scif_stop_bits 3 [3:3] 3 r_scif_rx_polling_en 4 [4:4] 4 r_scif_rx_clean_fifo 5 [5:5] 5 r_scif_en_tx 8 [8:8] 8 r_scif_en_rx 9 [9:9] 9 r_scif_clksel 15 [15:14] 14 r_scif_div 31 [31:16] 16 REG_ERROR 0x0028 0x00 32 r_err_overflow 0 [0:0] 0 r_err_parity 1 [1:1] 1 REG_IRQ_EN 0x002c 0x00 32 r_scif_rx_irq_en 0 [0:0] 0 r_scif_err_irq_en 1 [1:1] 1 REG_VALID 0x0030 0x00 32 r_scif_rx_data_valid 0 [0:0] 0 REG_DATA 0x0034 0x00 32 r_scif_rx_data 7 [7:0] 0 REG_SCIF_ETU 0x0038 0x00 32 r_scif_etu 15 [15:0] 0 0 0x3c registers UDMA_SPIS_0 0x50112000 UDMA_SPIS_0 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_SPIS_SETUP 0x0020 0x00 32 cfgcpol 0 [0:0] 0 cfgcpha 1 [1:1] 1 REG_SEOT_CNT 0x0024 0x00 32 sr_seot_cnt 15 [15:0] 0 REG_SPIS_IRQ_EN 0x0028 0x00 32 seot_irq_en 0 [0:0] 0 REG_SPIS_RXCNT 0x002c 0x00 32 cfgrxcnt 15 [15:0] 0 REG_SPIS_TXCNT 0x0030 0x00 32 cfgtxcnt 15 [15:0] 0 REG_SPIS_DMCNT 0x0034 0x00 32 cfgdmcnt 15 [15:0] 0 0 0x38 registers UDMA_SPIS_1 0x50113000 UDMA_SPIS_1 REG_RX_SADDR 0x0000 0x00 32 r_rx_startaddr 11 [11:0] 0 REG_RX_SIZE 0x0004 0x00 32 r_rx_size 15 [15:0] 0 REG_RX_CFG 0x0008 0x00 32 r_rx_continuous 0 [0:0] 0 r_rx_en 4 [4:4] 4 r_rx_clr 6 [6:6] 6 REG_TX_SADDR 0x0010 0x00 32 r_tx_startaddr 11 [11:0] 0 REG_TX_SIZE 0x0014 0x00 32 r_tx_size 15 [15:0] 0 REG_TX_CFG 0x0018 0x00 32 r_tx_continuous 0 [0:0] 0 r_tx_en 4 [4:4] 4 r_tx_clr 6 [6:6] 6 REG_SPIS_SETUP 0x0020 0x00 32 cfgcpol 0 [0:0] 0 cfgcpha 1 [1:1] 1 REG_SEOT_CNT 0x0024 0x00 32 sr_seot_cnt 15 [15:0] 0 REG_SPIS_IRQ_EN 0x0028 0x00 32 seot_irq_en 0 [0:0] 0 REG_SPIS_RXCNT 0x002c 0x00 32 cfgrxcnt 15 [15:0] 0 REG_SPIS_TXCNT 0x0030 0x00 32 cfgtxcnt 15 [15:0] 0 REG_SPIS_DMCNT 0x0034 0x00 32 cfgdmcnt 15 [15:0] 0 0 0x38 registers UDMA_ADC 0x50114000 UDMA_ADC 0 0x4 registers AES 0x4002D000 AES SFR_CRFUNC 0x0000 0x00 32 sfr_crfunc 7 [7:0] 0 SFR_AR 0x0004 0x00 32 sfr_ar 31 [31:0] 0 SFR_SRMFSM 0x0008 0x00 32 sfr_srmfsm 7 [7:0] 0 SFR_FR 0x000c 0x00 32 mfsm_done 0 [0:0] 0 acore_done 1 [1:1] 1 chnlo_done 2 [2:2] 2 chnli_done 3 [3:3] 3 SFR_OPT 0x0010 0x00 32 opt_klen0 3 [3:0] 0 opt_mode0 7 [7:4] 4 opt_ifstart0 8 [8:8] 8 SFR_OPT1 0x0014 0x00 32 sfr_opt1 15 [15:0] 0 SFR_OPTLTX 0x0018 0x00 32 sfr_optltx 5 [5:0] 0 SFR_MASKSEED 0x0020 0x00 32 sfr_maskseed 31 [31:0] 0 SFR_MASKSEEDAR 0x0024 0x00 32 sfr_maskseedar 31 [31:0] 0 SFR_SEGPTR_PTRID_IV 0x0030 0x00 32 PTRID_IV 11 [11:0] 0 SFR_SEGPTR_PTRID_AKEY 0x0034 0x00 32 PTRID_AKEY 11 [11:0] 0 SFR_SEGPTR_PTRID_AIB 0x0038 0x00 32 PTRID_AIB 11 [11:0] 0 SFR_SEGPTR_PTRID_AOB 0x003c 0x00 32 PTRID_AOB 11 [11:0] 0 0 0x40 registers COMBOHASH 0x4002B000 COMBOHASH SFR_CRFUNC 0x0000 0x00 32 cr_func 7 [7:0] 0 SFR_AR 0x0004 0x00 32 sfr_ar 31 [31:0] 0 SFR_SRMFSM 0x0008 0x00 32 mfsm 7 [7:0] 0 SFR_FR 0x000c 0x00 32 mfsm_done 0 [0:0] 0 hash_done 1 [1:1] 1 chnlo_done 2 [2:2] 2 chnli_done 3 [3:3] 3 chkdone 4 [4:4] 4 chkpass 5 [5:5] 5 SFR_OPT1 0x0010 0x00 32 cr_opt_hashcnt 15 [15:0] 0 SFR_OPT2 0x0014 0x00 32 cr_opt_scrtchk 0 [0:0] 0 cr_opt_ifsob 1 [1:1] 1 cr_opt_ifstart 2 [2:2] 2 SFR_OPT3 0x0018 0x00 32 sfr_opt3 7 [7:0] 0 SFR_BLKT0 0x001c 0x00 32 sfr_blkt0 7 [7:0] 0 SFR_SEGPTR_SEGID_LKEY 0x0020 0x00 32 SEGID_LKEY 11 [11:0] 0 SFR_SEGPTR_SEGID_KEY 0x0024 0x00 32 SEGID_KEY 11 [11:0] 0 SFR_SEGPTR_SEGID_SCRT 0x002c 0x00 32 SEGID_SCRT 11 [11:0] 0 SFR_SEGPTR_SEGID_MSG 0x0030 0x00 32 SEGID_MSG 11 [11:0] 0 SFR_SEGPTR_SEGID_HOUT 0x0034 0x00 32 SEGID_HOUT 11 [11:0] 0 SFR_SEGPTR_SEGID_HOUT2 0x003c 0x00 32 SEGID_HOUT2 11 [11:0] 0 0 0x40 registers PKE 0x4002C000 PKE SFR_CRFUNC 0x0000 0x00 32 cr_func 7 [7:0] 0 cr_pcoreir 15 [15:8] 8 SFR_AR 0x0004 0x00 32 sfr_ar 31 [31:0] 0 SFR_SRMFSM 0x0008 0x00 32 mfsm 7 [7:0] 0 modinvready 8 [8:8] 8 SFR_FR 0x000c 0x00 32 mfsm_done 0 [0:0] 0 pcore_done 1 [1:1] 1 chnlo_done 2 [2:2] 2 chnli_done 3 [3:3] 3 chnlx_done 4 [4:4] 4 SFR_OPTNW 0x0010 0x00 32 sfr_optnw 12 [12:0] 0 SFR_OPTEW 0x0014 0x00 32 sfr_optew 12 [12:0] 0 SFR_OPTRW 0x0018 0x00 32 sfr_optrw 9 [9:0] 0 SFR_OPTLTX 0x001c 0x00 32 sfr_optltx 4 [4:0] 0 SFR_OPTMASK 0x0020 0x00 32 sfr_optmask 15 [15:0] 0 SFR_SEGPTR_PTRID_PCON 0x0030 0x00 32 PTRID_PCON 11 [11:0] 0 SFR_SEGPTR_PTRID_PIB0 0x0034 0x00 32 PTRID_PIB0 11 [11:0] 0 SFR_SEGPTR_PTRID_PIB1 0x0038 0x00 32 PTRID_PIB1 11 [11:0] 0 SFR_SEGPTR_PTRID_PKB 0x003c 0x00 32 PTRID_PKB 11 [11:0] 0 SFR_SEGPTR_PTRID_POB 0x0040 0x00 32 PTRID_POB 11 [11:0] 0 0 0x44 registers SCEDMA 0x40029000 SCEDMA SFR_SCHSTART_AR 0x0000 0x00 32 sfr_schstart_ar 31 [31:0] 0 SFR_XCH_FUNC 0x0010 0x00 32 sfr_xch_func 0 [0:0] 0 SFR_XCH_OPT 0x0014 0x00 32 sfr_xch_opt 7 [7:0] 0 SFR_XCH_AXSTART 0x0018 0x00 32 sfr_xch_axstart 31 [31:0] 0 SFR_XCH_SEGID 0x001c 0x00 32 sfr_xch_segid 7 [7:0] 0 SFR_XCH_SEGSTART 0x0020 0x00 32 xchcr_segstart 11 [11:0] 0 SFR_XCH_TRANSIZE 0x0024 0x00 32 xchcr_transize 29 [29:0] 0 SFR_SCH_FUNC 0x0030 0x00 32 sfr_sch_func 0 [0:0] 0 SFR_SCH_OPT 0x0034 0x00 32 sfr_sch_opt 7 [7:0] 0 SFR_SCH_AXSTART 0x0038 0x00 32 sfr_sch_axstart 31 [31:0] 0 SFR_SCH_SEGID 0x003c 0x00 32 sfr_sch_segid 7 [7:0] 0 SFR_SCH_SEGSTART 0x0040 0x00 32 schcr_segstart 11 [11:0] 0 SFR_SCH_TRANSIZE 0x0044 0x00 32 schcr_transize 29 [29:0] 0 SFR_ICH_OPT 0x0050 0x00 32 sfr_ich_opt 3 [3:0] 0 SFR_ICH_SEGID 0x0054 0x00 32 sfr_ich_segid 15 [15:0] 0 SFR_ICH_RPSTART 0x0058 0x00 32 ichcr_rpstart 11 [11:0] 0 SFR_ICH_WPSTART 0x005c 0x00 32 ichcr_wpstart 11 [11:0] 0 SFR_ICH_TRANSIZE 0x0060 0x00 32 ichcr_transize 11 [11:0] 0 0 0x64 registers SCE_GLBSFR 0x40028000 SCE_GLBSFR SFR_SCEMODE 0x0000 0x00 32 cr_scemode 1 [1:0] 0 SFR_SUBEN 0x0004 0x00 32 cr_suben 15 [15:0] 0 SFR_AHBS 0x0008 0x00 32 cr_ahbsopt 4 [4:0] 0 SFR_SRBUSY 0x0010 0x00 32 sr_busy 15 [15:0] 0 SFR_FRDONE 0x0014 0x00 32 fr_done 15 [15:0] 0 SFR_FRERR 0x0018 0x00 32 fr_err 15 [15:0] 0 SFR_ARCLR 0x001c 0x00 32 ar_clrram 31 [31:0] 0 SFR_FRACERR 0x0020 0x00 32 fr_acerr 7 [7:0] 0 SFR_TICKCNT 0x0024 0x00 32 sfr_tickcnt 31 [31:0] 0 SFR_FFEN 0x0030 0x00 32 cr_ffen 5 [5:0] 0 SFR_FFCLR 0x0034 0x00 32 ar_ffclr 31 [31:0] 0 SFR_FFCNT_SR_FF0 0x0040 0x00 32 sr_ff0 15 [15:0] 0 SFR_FFCNT_SR_FF1 0x0044 0x00 32 sr_ff1 15 [15:0] 0 SFR_FFCNT_SR_FF2 0x0048 0x00 32 sr_ff2 15 [15:0] 0 SFR_FFCNT_SR_FF3 0x004c 0x00 32 sr_ff3 15 [15:0] 0 SFR_FFCNT_SR_FF4 0x0050 0x00 32 sr_ff4 15 [15:0] 0 SFR_FFCNT_SR_FF5 0x0054 0x00 32 sr_ff5 15 [15:0] 0 SFR_TS 0x00fc 0x00 32 cr_ts 15 [15:0] 0 0 0x100 registers TRNG 0x4002E000 TRNG SFR_CRSRC 0x0000 0x00 32 sfr_crsrc 11 [11:0] 0 SFR_CRANA 0x0004 0x00 32 sfr_crana 15 [15:0] 0 SFR_PP 0x0008 0x00 32 sfr_pp 16 [16:0] 0 SFR_OPT 0x000c 0x00 32 sfr_opt 16 [16:0] 0 SFR_SR 0x0010 0x00 32 sr_rng 31 [31:0] 0 SFR_AR_GEN 0x0014 0x00 32 sfr_ar_gen 31 [31:0] 0 SFR_FR 0x0018 0x00 32 sfr_fr 1 [1:0] 0 SFR_DRPSZ 0x0020 0x00 32 sfr_drpsz 31 [31:0] 0 SFR_DRGEN 0x0024 0x00 32 sfr_drgen 31 [31:0] 0 SFR_DRRESEED 0x0028 0x00 32 sfr_drreseed 31 [31:0] 0 SFR_BUF 0x0030 0x00 32 sfr_buf 31 [31:0] 0 SFR_CHAIN_RNGCHAINEN0 0x0040 0x00 32 rngchainen0 31 [31:0] 0 SFR_CHAIN_RNGCHAINEN1 0x0044 0x00 32 rngchainen1 31 [31:0] 0 0 0x48 registers ALU 0x4002F000 ALU 0 0x4 registers DUART 0x40042000 DUART SFR_TXD 0x0000 0x00 32 sfr_txd 7 [7:0] 0 SFR_CR 0x0004 0x00 32 sfr_cr 0 [0:0] 0 SFR_SR 0x0008 0x00 32 sfr_sr 0 [0:0] 0 SFR_ETUC 0x000c 0x00 32 sfr_etuc 15 [15:0] 0 0 0x10 registers WDG_INTF 0x40041000 WDG_INTF 0 0x4 registers TIMER_INTF 0x40043000 TIMER_INTF 0 0x4 registers EVC 0x40044000 EVC SFR_CM7EVSEL_CM7EVSEL0 0x0000 0x00 32 cm7evsel0 7 [7:0] 0 SFR_CM7EVSEL_CM7EVSEL1 0x0004 0x00 32 cm7evsel1 7 [7:0] 0 SFR_CM7EVSEL_CM7EVSEL2 0x0008 0x00 32 cm7evsel2 7 [7:0] 0 SFR_CM7EVSEL_CM7EVSEL3 0x000c 0x00 32 cm7evsel3 7 [7:0] 0 SFR_CM7EVSEL_CM7EVSEL4 0x0010 0x00 32 cm7evsel4 7 [7:0] 0 SFR_CM7EVSEL_CM7EVSEL5 0x0014 0x00 32 cm7evsel5 7 [7:0] 0 SFR_CM7EVSEL_CM7EVSEL6 0x0018 0x00 32 cm7evsel6 7 [7:0] 0 SFR_CM7EVSEL_CM7EVSEL7 0x001c 0x00 32 cm7evsel7 7 [7:0] 0 SFR_CM7EVEN 0x0020 0x00 32 cm7even 7 [7:0] 0 SFR_CM7EVFR 0x0024 0x00 32 cm7evs 7 [7:0] 0 SFR_TMREVSEL 0x0030 0x00 32 tmr_evsel 15 [15:0] 0 SFR_PWMEVSEL 0x0034 0x00 32 pwm_evsel 31 [31:0] 0 SFR_IFEVEN_IFEVEN0 0x0040 0x00 32 ifeven0 31 [31:0] 0 SFR_IFEVEN_IFEVEN1 0x0044 0x00 32 ifeven1 31 [31:0] 0 SFR_IFEVEN_IFEVEN2 0x0048 0x00 32 ifeven2 31 [31:0] 0 SFR_IFEVEN_IFEVEN3 0x004c 0x00 32 ifeven3 31 [31:0] 0 SFR_IFEVEN_IFEVEN4 0x0050 0x00 32 ifeven4 31 [31:0] 0 SFR_IFEVEN_IFEVEN5 0x0054 0x00 32 ifeven5 31 [31:0] 0 SFR_IFEVEN_IFEVEN6 0x0058 0x00 32 ifeven6 31 [31:0] 0 SFR_IFEVEN_IFEVEN7 0x005c 0x00 32 ifeven7 31 [31:0] 0 SFR_IFEVERRFR 0x0060 0x00 32 ifev_errs 31 [31:0] 0 SFR_CM7ERRFR 0x0080 0x00 32 errin 31 [31:0] 0 0 0x84 registers SYSCTRL 0x40040000 SYSCTRL SFR_CGUSEC 0x0000 0x00 32 sfr_cgusec 15 [15:0] 0 SFR_CGULP 0x0004 0x00 32 sfr_cgulp 15 [15:0] 0 SFR_SEED 0x0008 0x00 32 sfr_seed 31 [31:0] 0 SFR_SEEDAR 0x000c 0x00 32 sfr_seedar 31 [31:0] 0 SFR_CGUSEL0 0x0010 0x00 32 sfr_cgusel0 1 [1:0] 0 SFR_CGUFD_CFGFDCR_0_4_0 0x0014 0x00 32 cfgfdcr_0_4_0 15 [15:0] 0 SFR_CGUFD_CFGFDCR_0_4_1 0x0018 0x00 32 cfgfdcr_0_4_1 15 [15:0] 0 SFR_CGUFD_CFGFDCR_0_4_2 0x001c 0x00 32 cfgfdcr_0_4_2 15 [15:0] 0 SFR_CGUFD_CFGFDCR_0_4_3 0x0020 0x00 32 cfgfdcr_0_4_3 15 [15:0] 0 SFR_CGUFD_CFGFDCR_0_4_4 0x0024 0x00 32 cfgfdcr_0_4_4 15 [15:0] 0 SFR_CGUFDAO 0x0028 0x00 32 cfgfdcr 15 [15:0] 0 SFR_CGUSET 0x002c 0x00 32 sfr_cguset 31 [31:0] 0 SFR_CGUSEL1 0x0030 0x00 32 sfr_cgusel1 0 [0:0] 0 SFR_CGUFDPKE 0x0034 0x00 32 sfr_cgufdpke 8 [8:0] 0 SFR_CGUFSSR_FSFREQ0 0x0040 0x00 32 fsfreq0 15 [15:0] 0 SFR_CGUFSSR_FSFREQ1 0x0044 0x00 32 fsfreq1 15 [15:0] 0 SFR_CGUFSSR_FSFREQ2 0x0048 0x00 32 fsfreq2 15 [15:0] 0 SFR_CGUFSSR_FSFREQ3 0x004c 0x00 32 fsfreq3 15 [15:0] 0 SFR_CGUFSVLD 0x0050 0x00 32 sfr_cgufsvld 3 [3:0] 0 SFR_CGUFSCR 0x0054 0x00 32 sfr_cgufscr 15 [15:0] 0 SFR_ACLKGR 0x0060 0x00 32 sfr_aclkgr 7 [7:0] 0 SFR_HCLKGR 0x0064 0x00 32 sfr_hclkgr 7 [7:0] 0 SFR_ICLKGR 0x0068 0x00 32 sfr_iclkgr 7 [7:0] 0 SFR_PCLKGR 0x006c 0x00 32 sfr_pclkgr 7 [7:0] 0 SFR_RCURST0 0x0080 0x00 32 sfr_rcurst0 31 [31:0] 0 SFR_RCURST1 0x0084 0x00 32 sfr_rcurst1 31 [31:0] 0 SFR_RCUSRCFR 0x0088 0x00 32 sfr_rcusrcfr 15 [15:0] 0 SFR_IPCARIPFLOW 0x0090 0x00 32 sfr_ipcaripflow 31 [31:0] 0 SFR_IPCEN 0x0094 0x00 32 sfr_ipcen 15 [15:0] 0 SFR_IPCLPEN 0x0098 0x00 32 sfr_ipclpen 15 [15:0] 0 SFR_IPCOSC 0x009c 0x00 32 sfr_ipcosc 6 [6:0] 0 SFR_IPCPLLMN 0x00a0 0x00 32 sfr_ipcpllmn 16 [16:0] 0 SFR_IPCPLLF 0x00a4 0x00 32 sfr_ipcpllf 24 [24:0] 0 SFR_IPCPLLQ 0x00a8 0x00 32 sfr_ipcpllq 14 [14:0] 0 SFR_IPCCR 0x00ac 0x00 32 sfr_ipccr 15 [15:0] 0 0 0xb0 registers APB_THRU 0x50122000 APB_THRU 0 0x4 registers IOX 0x5012F000 IOX SFR_AFSEL_CRAFSEL0 0x0000 0x00 32 crafsel0 15 [15:0] 0 SFR_AFSEL_CRAFSEL1 0x0004 0x00 32 crafsel1 15 [15:0] 0 SFR_AFSEL_CRAFSEL2 0x0008 0x00 32 crafsel2 15 [15:0] 0 SFR_AFSEL_CRAFSEL3 0x000c 0x00 32 crafsel3 15 [15:0] 0 SFR_AFSEL_CRAFSEL4 0x0010 0x00 32 crafsel4 15 [15:0] 0 SFR_AFSEL_CRAFSEL5 0x0014 0x00 32 crafsel5 15 [15:0] 0 SFR_AFSEL_CRAFSEL6 0x0018 0x00 32 crafsel6 15 [15:0] 0 SFR_AFSEL_CRAFSEL7 0x001c 0x00 32 crafsel7 15 [15:0] 0 SFR_AFSEL_CRAFSEL8 0x0020 0x00 32 crafsel8 15 [15:0] 0 SFR_AFSEL_CRAFSEL9 0x0024 0x00 32 crafsel9 15 [15:0] 0 SFR_AFSEL_CRAFSEL10 0x0028 0x00 32 crafsel10 15 [15:0] 0 SFR_AFSEL_CRAFSEL11 0x002c 0x00 32 crafsel11 15 [15:0] 0 SFR_INTCR_CRINT0 0x0100 0x00 32 crint0 9 [9:0] 0 SFR_INTCR_CRINT1 0x0104 0x00 32 crint1 9 [9:0] 0 SFR_INTCR_CRINT2 0x0108 0x00 32 crint2 9 [9:0] 0 SFR_INTCR_CRINT3 0x010c 0x00 32 crint3 9 [9:0] 0 SFR_INTCR_CRINT4 0x0110 0x00 32 crint4 9 [9:0] 0 SFR_INTCR_CRINT5 0x0114 0x00 32 crint5 9 [9:0] 0 SFR_INTCR_CRINT6 0x0118 0x00 32 crint6 9 [9:0] 0 SFR_INTCR_CRINT7 0x011c 0x00 32 crint7 9 [9:0] 0 SFR_INTFR 0x0120 0x00 32 frint 7 [7:0] 0 SFR_GPIOOUT_CRGO0 0x0130 0x00 32 crgo0 15 [15:0] 0 SFR_GPIOOUT_CRGO1 0x0134 0x00 32 crgo1 15 [15:0] 0 SFR_GPIOOUT_CRGO2 0x0138 0x00 32 crgo2 15 [15:0] 0 SFR_GPIOOUT_CRGO3 0x013c 0x00 32 crgo3 15 [15:0] 0 SFR_GPIOOUT_CRGO4 0x0140 0x00 32 crgo4 15 [15:0] 0 SFR_GPIOOUT_CRGO5 0x0144 0x00 32 crgo5 15 [15:0] 0 SFR_GPIOOE_CRGOE0 0x0148 0x00 32 crgoe0 15 [15:0] 0 SFR_GPIOOE_CRGOE1 0x014c 0x00 32 crgoe1 15 [15:0] 0 SFR_GPIOOE_CRGOE2 0x0150 0x00 32 crgoe2 15 [15:0] 0 SFR_GPIOOE_CRGOE3 0x0154 0x00 32 crgoe3 15 [15:0] 0 SFR_GPIOOE_CRGOE4 0x0158 0x00 32 crgoe4 15 [15:0] 0 SFR_GPIOOE_CRGOE5 0x015c 0x00 32 crgoe5 15 [15:0] 0 SFR_GPIOPU_CRGPU0 0x0160 0x00 32 crgpu0 15 [15:0] 0 SFR_GPIOPU_CRGPU1 0x0164 0x00 32 crgpu1 15 [15:0] 0 SFR_GPIOPU_CRGPU2 0x0168 0x00 32 crgpu2 15 [15:0] 0 SFR_GPIOPU_CRGPU3 0x016c 0x00 32 crgpu3 15 [15:0] 0 SFR_GPIOPU_CRGPU4 0x0170 0x00 32 crgpu4 15 [15:0] 0 SFR_GPIOPU_CRGPU5 0x0174 0x00 32 crgpu5 15 [15:0] 0 SFR_GPIOIN_SRGI0 0x0178 0x00 32 srgi0 15 [15:0] 0 SFR_GPIOIN_SRGI1 0x017c 0x00 32 srgi1 15 [15:0] 0 SFR_GPIOIN_SRGI2 0x0180 0x00 32 srgi2 15 [15:0] 0 SFR_GPIOIN_SRGI3 0x0184 0x00 32 srgi3 15 [15:0] 0 SFR_GPIOIN_SRGI4 0x0188 0x00 32 srgi4 15 [15:0] 0 SFR_GPIOIN_SRGI5 0x018c 0x00 32 srgi5 15 [15:0] 0 SFR_PIOSEL 0x0200 0x00 32 piosel 31 [31:0] 0 SFR_CFG_SCHM_CR_CFG_SCHMSEL0 0x0230 0x00 32 cr_cfg_schmsel0 15 [15:0] 0 SFR_CFG_SCHM_CR_CFG_SCHMSEL1 0x0234 0x00 32 cr_cfg_schmsel1 15 [15:0] 0 SFR_CFG_SCHM_CR_CFG_SCHMSEL2 0x0238 0x00 32 cr_cfg_schmsel2 15 [15:0] 0 SFR_CFG_SCHM_CR_CFG_SCHMSEL3 0x023c 0x00 32 cr_cfg_schmsel3 15 [15:0] 0 SFR_CFG_SCHM_CR_CFG_SCHMSEL4 0x0240 0x00 32 cr_cfg_schmsel4 15 [15:0] 0 SFR_CFG_SCHM_CR_CFG_SCHMSEL5 0x0244 0x00 32 cr_cfg_schmsel5 15 [15:0] 0 SFR_CFG_SLEW_CR_CFG_SLEWSLOW0 0x0248 0x00 32 cr_cfg_slewslow0 15 [15:0] 0 SFR_CFG_SLEW_CR_CFG_SLEWSLOW1 0x024c 0x00 32 cr_cfg_slewslow1 15 [15:0] 0 SFR_CFG_SLEW_CR_CFG_SLEWSLOW2 0x0250 0x00 32 cr_cfg_slewslow2 15 [15:0] 0 SFR_CFG_SLEW_CR_CFG_SLEWSLOW3 0x0254 0x00 32 cr_cfg_slewslow3 15 [15:0] 0 SFR_CFG_SLEW_CR_CFG_SLEWSLOW4 0x0258 0x00 32 cr_cfg_slewslow4 15 [15:0] 0 SFR_CFG_SLEW_CR_CFG_SLEWSLOW5 0x025c 0x00 32 cr_cfg_slewslow5 15 [15:0] 0 SFR_CFG_DRVSEL_CR_CFG_DRVSEL0 0x0260 0x00 32 cr_cfg_drvsel0 31 [31:0] 0 SFR_CFG_DRVSEL_CR_CFG_DRVSEL1 0x0264 0x00 32 cr_cfg_drvsel1 31 [31:0] 0 SFR_CFG_DRVSEL_CR_CFG_DRVSEL2 0x0268 0x00 32 cr_cfg_drvsel2 31 [31:0] 0 SFR_CFG_DRVSEL_CR_CFG_DRVSEL3 0x026c 0x00 32 cr_cfg_drvsel3 31 [31:0] 0 SFR_CFG_DRVSEL_CR_CFG_DRVSEL4 0x0270 0x00 32 cr_cfg_drvsel4 31 [31:0] 0 SFR_CFG_DRVSEL_CR_CFG_DRVSEL5 0x0274 0x00 32 cr_cfg_drvsel5 31 [31:0] 0 0 0x278 registers PWM 0x50120000 PWM 0 0x4 registers SDDC 0x50121000 SDDC SFR_IO 0x0000 0x00 32 sfr_io 1 [1:0] 0 SFR_AR 0x0004 0x00 32 sfr_ar 31 [31:0] 0 CR_OCR 0x0010 0x00 32 cr_ocr 23 [23:0] 0 CR_RDFFTHRES 0x0014 0x00 32 cr_rdffthres 7 [7:0] 0 CR_REV 0x0018 0x00 32 cfg_reg_sd_spec_revision 7 [7:0] 0 cfg_reg_cccr_sdio_revision 15 [15:8] 8 CR_BACSA 0x001c 0x00 32 cfg_base_addr_csa 17 [17:0] 0 CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC0 0x0020 0x00 32 cfg_base_addr_io_func0 17 [17:0] 0 CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC1 0x0024 0x00 32 cfg_base_addr_io_func1 17 [17:0] 0 CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC2 0x0028 0x00 32 cfg_base_addr_io_func2 17 [17:0] 0 CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC3 0x002c 0x00 32 cfg_base_addr_io_func3 17 [17:0] 0 CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC4 0x0030 0x00 32 cfg_base_addr_io_func4 17 [17:0] 0 CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC5 0x0034 0x00 32 cfg_base_addr_io_func5 17 [17:0] 0 CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC6 0x0038 0x00 32 cfg_base_addr_io_func6 17 [17:0] 0 CR_BAIOFN_CFG_BASE_ADDR_IO_FUNC7 0x003c 0x00 32 cfg_base_addr_io_func7 17 [17:0] 0 CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR0 0x0040 0x00 32 cfg_reg_func_cis_ptr0 16 [16:0] 0 CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR1 0x0044 0x00 32 cfg_reg_func_cis_ptr1 16 [16:0] 0 CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR2 0x0048 0x00 32 cfg_reg_func_cis_ptr2 16 [16:0] 0 CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR3 0x004c 0x00 32 cfg_reg_func_cis_ptr3 16 [16:0] 0 CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR4 0x0050 0x00 32 cfg_reg_func_cis_ptr4 16 [16:0] 0 CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR5 0x0054 0x00 32 cfg_reg_func_cis_ptr5 16 [16:0] 0 CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR6 0x0058 0x00 32 cfg_reg_func_cis_ptr6 16 [16:0] 0 CR_FNCISPTR_CFG_REG_FUNC_CIS_PTR7 0x005c 0x00 32 cfg_reg_func_cis_ptr7 16 [16:0] 0 CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE0 0x0060 0x00 32 cfg_reg_func_ext_std_code0 7 [7:0] 0 CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE1 0x0064 0x00 32 cfg_reg_func_ext_std_code1 7 [7:0] 0 CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE2 0x0068 0x00 32 cfg_reg_func_ext_std_code2 7 [7:0] 0 CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE3 0x006c 0x00 32 cfg_reg_func_ext_std_code3 7 [7:0] 0 CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE4 0x0070 0x00 32 cfg_reg_func_ext_std_code4 7 [7:0] 0 CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE5 0x0074 0x00 32 cfg_reg_func_ext_std_code5 7 [7:0] 0 CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE6 0x0078 0x00 32 cfg_reg_func_ext_std_code6 7 [7:0] 0 CR_FNEXTSTDCODE_CFG_REG_FUNC_EXT_STD_CODE7 0x007c 0x00 32 cfg_reg_func_ext_std_code7 7 [7:0] 0 CR_WRITE_PROTECT 0x0080 0x00 32 cr_write_protect 0 [0:0] 0 CR_REG_DSR 0x0084 0x00 32 cr_reg_dsr 15 [15:0] 0 CR_REG_CID_CFG_REG_CID0 0x0088 0x00 32 cfg_reg_cid0 31 [31:0] 0 CR_REG_CID_CFG_REG_CID1 0x008c 0x00 32 cfg_reg_cid1 31 [31:0] 0 CR_REG_CID_CFG_REG_CID2 0x0090 0x00 32 cfg_reg_cid2 31 [31:0] 0 CR_REG_CID_CFG_REG_CID3 0x0094 0x00 32 cfg_reg_cid3 31 [31:0] 0 CR_REG_CSD_CFG_REG_CSD0 0x0098 0x00 32 cfg_reg_csd0 31 [31:0] 0 CR_REG_CSD_CFG_REG_CSD1 0x009c 0x00 32 cfg_reg_csd1 31 [31:0] 0 CR_REG_CSD_CFG_REG_CSD2 0x00a0 0x00 32 cfg_reg_csd2 31 [31:0] 0 CR_REG_CSD_CFG_REG_CSD3 0x00a4 0x00 32 cfg_reg_csd3 31 [31:0] 0 CR_REG_SCR_CFG_REG_SCR0 0x00a8 0x00 32 cfg_reg_scr0 31 [31:0] 0 CR_REG_SCR_CFG_REG_SCR1 0x00ac 0x00 32 cfg_reg_scr1 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS0 0x00b0 0x00 32 cfg_reg_sd_status0 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS1 0x00b4 0x00 32 cfg_reg_sd_status1 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS2 0x00b8 0x00 32 cfg_reg_sd_status2 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS3 0x00bc 0x00 32 cfg_reg_sd_status3 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS4 0x00c0 0x00 32 cfg_reg_sd_status4 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS5 0x00c4 0x00 32 cfg_reg_sd_status5 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS6 0x00c8 0x00 32 cfg_reg_sd_status6 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS7 0x00cc 0x00 32 cfg_reg_sd_status7 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS8 0x00d0 0x00 32 cfg_reg_sd_status8 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS9 0x00d4 0x00 32 cfg_reg_sd_status9 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS10 0x00d8 0x00 32 cfg_reg_sd_status10 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS11 0x00dc 0x00 32 cfg_reg_sd_status11 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS12 0x00e0 0x00 32 cfg_reg_sd_status12 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS13 0x00e4 0x00 32 cfg_reg_sd_status13 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS14 0x00e8 0x00 32 cfg_reg_sd_status14 31 [31:0] 0 CR_REG_SD_STATUS_CFG_REG_SD_STATUS15 0x00ec 0x00 32 cfg_reg_sd_status15 31 [31:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC0 0x0100 0x00 32 cfg_base_addr_mem_func0 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC1 0x0104 0x00 32 cfg_base_addr_mem_func1 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC2 0x0108 0x00 32 cfg_base_addr_mem_func2 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC3 0x010c 0x00 32 cfg_base_addr_mem_func3 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC4 0x0110 0x00 32 cfg_base_addr_mem_func4 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC5 0x0114 0x00 32 cfg_base_addr_mem_func5 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC6 0x0118 0x00 32 cfg_base_addr_mem_func6 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC7 0x011c 0x00 32 cfg_base_addr_mem_func7 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC8 0x0120 0x00 32 cfg_base_addr_mem_func8 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC9 0x0124 0x00 32 cfg_base_addr_mem_func9 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC10 0x0128 0x00 32 cfg_base_addr_mem_func10 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC11 0x012c 0x00 32 cfg_base_addr_mem_func11 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC12 0x0130 0x00 32 cfg_base_addr_mem_func12 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC13 0x0134 0x00 32 cfg_base_addr_mem_func13 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC14 0x0138 0x00 32 cfg_base_addr_mem_func14 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC15 0x013c 0x00 32 cfg_base_addr_mem_func15 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC16 0x0140 0x00 32 cfg_base_addr_mem_func16 17 [17:0] 0 CR_BASE_ADDR_MEM_FUNC_CFG_BASE_ADDR_MEM_FUNC17 0x0144 0x00 32 cfg_base_addr_mem_func17 17 [17:0] 0 CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE0 0x0148 0x00 32 cfg_reg_func_isdio_interface_code0 7 [7:0] 0 CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE1 0x014c 0x00 32 cfg_reg_func_isdio_interface_code1 7 [7:0] 0 CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE2 0x0150 0x00 32 cfg_reg_func_isdio_interface_code2 7 [7:0] 0 CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE3 0x0154 0x00 32 cfg_reg_func_isdio_interface_code3 7 [7:0] 0 CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE4 0x0158 0x00 32 cfg_reg_func_isdio_interface_code4 7 [7:0] 0 CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE5 0x015c 0x00 32 cfg_reg_func_isdio_interface_code5 7 [7:0] 0 CR_REG_FUNC_ISDIO_INTERFACE_CODE_CFG_REG_FUNC_ISDIO_INTERFACE_CODE6 0x0160 0x00 32 cfg_reg_func_isdio_interface_code6 7 [7:0] 0 CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE0 0x0168 0x00 32 cfg_reg_func_manufact_code0 15 [15:0] 0 CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE1 0x016c 0x00 32 cfg_reg_func_manufact_code1 15 [15:0] 0 CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE2 0x0170 0x00 32 cfg_reg_func_manufact_code2 15 [15:0] 0 CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE3 0x0174 0x00 32 cfg_reg_func_manufact_code3 15 [15:0] 0 CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE4 0x0178 0x00 32 cfg_reg_func_manufact_code4 15 [15:0] 0 CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE5 0x017c 0x00 32 cfg_reg_func_manufact_code5 15 [15:0] 0 CR_REG_FUNC_MANUFACT_CODE_CFG_REG_FUNC_MANUFACT_CODE6 0x0180 0x00 32 cfg_reg_func_manufact_code6 15 [15:0] 0 CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO0 0x0188 0x00 32 cfg_reg_func_manufact_info0 15 [15:0] 0 CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO1 0x018c 0x00 32 cfg_reg_func_manufact_info1 15 [15:0] 0 CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO2 0x0190 0x00 32 cfg_reg_func_manufact_info2 15 [15:0] 0 CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO3 0x0194 0x00 32 cfg_reg_func_manufact_info3 15 [15:0] 0 CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO4 0x0198 0x00 32 cfg_reg_func_manufact_info4 15 [15:0] 0 CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO5 0x019c 0x00 32 cfg_reg_func_manufact_info5 15 [15:0] 0 CR_REG_FUNC_MANUFACT_INFO_CFG_REG_FUNC_MANUFACT_INFO6 0x01a0 0x00 32 cfg_reg_func_manufact_info6 15 [15:0] 0 CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE0 0x01a8 0x00 32 cfg_reg_func_isdio_type_sup_code0 7 [7:0] 0 CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE1 0x01ac 0x00 32 cfg_reg_func_isdio_type_sup_code1 7 [7:0] 0 CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE2 0x01b0 0x00 32 cfg_reg_func_isdio_type_sup_code2 7 [7:0] 0 CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE3 0x01b4 0x00 32 cfg_reg_func_isdio_type_sup_code3 7 [7:0] 0 CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE4 0x01b8 0x00 32 cfg_reg_func_isdio_type_sup_code4 7 [7:0] 0 CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE5 0x01bc 0x00 32 cfg_reg_func_isdio_type_sup_code5 7 [7:0] 0 CR_REG_FUNC_ISDIO_TYPE_SUP_CODE_CFG_REG_FUNC_ISDIO_TYPE_SUP_CODE6 0x01c0 0x00 32 cfg_reg_func_isdio_type_sup_code6 7 [7:0] 0 CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO0 0x01c8 0x00 32 cfg_reg_func_info0 15 [15:0] 0 CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO1 0x01cc 0x00 32 cfg_reg_func_info1 15 [15:0] 0 CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO2 0x01d0 0x00 32 cfg_reg_func_info2 15 [15:0] 0 CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO3 0x01d4 0x00 32 cfg_reg_func_info3 15 [15:0] 0 CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO4 0x01d8 0x00 32 cfg_reg_func_info4 15 [15:0] 0 CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO5 0x01dc 0x00 32 cfg_reg_func_info5 15 [15:0] 0 CR_REG_FUNC_INFO_CFG_REG_FUNC_INFO6 0x01e0 0x00 32 cfg_reg_func_info6 15 [15:0] 0 CR_REG_UHS_1_SUPPORT 0x01f0 0x00 32 cfg_reg_max_current 15 [15:0] 0 cfg_reg_data_strc_version 23 [23:16] 16 cfg_reg_uhs_1_support 31 [31:24] 24 0 0x1f4 registers RP_PIO 0x50123000 RP_PIO SFR_CTRL 0x0000 0x00 32 en 3 [3:0] 0 restart 7 [7:4] 4 clkdiv_restart 11 [11:8] 8 SFR_FSTAT 0x0004 0x00 32 rx_full 3 [3:0] 0 constant0 7 [7:4] 4 rx_empty 11 [11:8] 8 constant1 15 [15:12] 12 tx_full 19 [19:16] 16 constant2 23 [23:20] 20 tx_empty 27 [27:24] 24 constant3 31 [31:28] 28 SFR_FDEBUG 0x0008 0x00 32 rxstall 3 [3:0] 0 nc_dbg3 7 [7:4] 4 rxunder 11 [11:8] 8 nc_dbg2 15 [15:12] 12 txover 19 [19:16] 16 nc_dbg1 23 [23:20] 20 txstall 27 [27:24] 24 nc_dbg0 31 [31:28] 28 SFR_FLEVEL 0x000c 0x00 32 tx_level0 2 [2:0] 0 constant0 3 [3:3] 3 rx_level0 6 [6:4] 4 constant1 7 [7:7] 7 tx_level1 10 [10:8] 8 constant2 11 [11:11] 11 rx_level1 14 [14:12] 12 constant3 15 [15:15] 15 tx_level2 18 [18:16] 16 constant4 19 [19:19] 19 rx_level2 22 [22:20] 20 constant5 23 [23:23] 23 tx_level3 26 [26:24] 24 constant6 27 [27:27] 27 rx_level3 30 [30:28] 28 constant7 31 [31:31] 31 SFR_TXF0 0x0010 0x00 32 fdin 31 [31:0] 0 SFR_TXF1 0x0014 0x00 32 fdin 31 [31:0] 0 SFR_TXF2 0x0018 0x00 32 fdin 31 [31:0] 0 SFR_TXF3 0x001c 0x00 32 fdin 31 [31:0] 0 SFR_RXF0 0x0020 0x00 32 pdout 31 [31:0] 0 SFR_RXF1 0x0024 0x00 32 pdout 31 [31:0] 0 SFR_RXF2 0x0028 0x00 32 pdout 31 [31:0] 0 SFR_RXF3 0x002c 0x00 32 pdout 31 [31:0] 0 SFR_IRQ 0x0030 0x00 32 sfr_irq 7 [7:0] 0 SFR_IRQ_FORCE 0x0034 0x00 32 sfr_irq_force 7 [7:0] 0 SFR_SYNC_BYPASS 0x0038 0x00 32 sfr_sync_bypass 31 [31:0] 0 SFR_DBG_PADOUT 0x003c 0x00 32 sfr_dbg_padout 31 [31:0] 0 SFR_DBG_PADOE 0x0040 0x00 32 sfr_dbg_padoe 31 [31:0] 0 SFR_DBG_CFGINFO 0x0044 0x00 32 constant0 7 [7:0] 0 constant1 15 [15:8] 8 constant2 31 [31:16] 16 SFR_INSTR_MEM0 0x0048 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM1 0x004c 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM2 0x0050 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM3 0x0054 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM4 0x0058 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM5 0x005c 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM6 0x0060 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM7 0x0064 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM8 0x0068 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM9 0x006c 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM10 0x0070 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM11 0x0074 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM12 0x0078 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM13 0x007c 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM14 0x0080 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM15 0x0084 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM16 0x0088 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM17 0x008c 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM18 0x0090 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM19 0x0094 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM20 0x0098 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM21 0x009c 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM22 0x00a0 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM23 0x00a4 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM24 0x00a8 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM25 0x00ac 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM26 0x00b0 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM27 0x00b4 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM28 0x00b8 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM29 0x00bc 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM30 0x00c0 0x00 32 instr 15 [15:0] 0 SFR_INSTR_MEM31 0x00c4 0x00 32 instr 15 [15:0] 0 SFR_SM0_CLKDIV 0x00c8 0x00 32 unused_div 7 [7:0] 0 div_frac 15 [15:8] 8 div_int 31 [31:16] 16 SFR_SM0_EXECCTRL 0x00cc 0x00 32 status_n 3 [3:0] 0 status_sel 4 [4:4] 4 resvd_exec 6 [6:5] 5 wrap_target 11 [11:7] 7 pend 16 [16:12] 12 out_sticky 17 [17:17] 17 inline_out_en 18 [18:18] 18 out_en_sel 23 [23:19] 19 jmp_pin 28 [28:24] 24 side_pindir 29 [29:29] 29 sideset_enable_bit 30 [30:30] 30 exec_stalled_ro0 31 [31:31] 31 SFR_SM0_SHIFTCTRL 0x00d0 0x00 32 resvd_shift 15 [15:0] 0 auto_push 16 [16:16] 16 auto_pull 17 [17:17] 17 in_shift_dir 18 [18:18] 18 out_shift_dir 19 [19:19] 19 isr_threshold 24 [24:20] 20 osr_threshold 29 [29:25] 25 join_tx 30 [30:30] 30 join_rx 31 [31:31] 31 SFR_SM0_ADDR 0x00d4 0x00 32 pc 4 [4:0] 0 SFR_SM0_INSTR 0x00d8 0x00 32 imm_instr 15 [15:0] 0 SFR_SM0_PINCTRL 0x00dc 0x00 32 pins_out_base 4 [4:0] 0 pins_set_base 9 [9:5] 5 pins_side_base 14 [14:10] 10 pins_in_base 19 [19:15] 15 pins_out_count 25 [25:20] 20 pins_set_count 28 [28:26] 26 pins_side_count 31 [31:29] 29 SFR_SM1_CLKDIV 0x00e0 0x00 32 unused_div 7 [7:0] 0 div_frac 15 [15:8] 8 div_int 31 [31:16] 16 SFR_SM1_EXECCTRL 0x00e4 0x00 32 status_n 3 [3:0] 0 status_sel 4 [4:4] 4 resvd_exec 6 [6:5] 5 wrap_target 11 [11:7] 7 pend 16 [16:12] 12 out_sticky 17 [17:17] 17 inline_out_en 18 [18:18] 18 out_en_sel 23 [23:19] 19 jmp_pin 28 [28:24] 24 side_pindir 29 [29:29] 29 sideset_enable_bit 30 [30:30] 30 exec_stalled_ro1 31 [31:31] 31 SFR_SM1_SHIFTCTRL 0x00e8 0x00 32 resvd_shift 15 [15:0] 0 auto_push 16 [16:16] 16 auto_pull 17 [17:17] 17 in_shift_dir 18 [18:18] 18 out_shift_dir 19 [19:19] 19 isr_threshold 24 [24:20] 20 osr_threshold 29 [29:25] 25 join_tx 30 [30:30] 30 join_rx 31 [31:31] 31 SFR_SM1_ADDR 0x00ec 0x00 32 pc 4 [4:0] 0 SFR_SM1_INSTR 0x00f0 0x00 32 imm_instr 15 [15:0] 0 SFR_SM1_PINCTRL 0x00f4 0x00 32 pins_out_base 4 [4:0] 0 pins_set_base 9 [9:5] 5 pins_side_base 14 [14:10] 10 pins_in_base 19 [19:15] 15 pins_out_count 25 [25:20] 20 pins_set_count 28 [28:26] 26 pins_side_count 31 [31:29] 29 SFR_SM2_CLKDIV 0x00f8 0x00 32 unused_div 7 [7:0] 0 div_frac 15 [15:8] 8 div_int 31 [31:16] 16 SFR_SM2_EXECCTRL 0x00fc 0x00 32 status_n 3 [3:0] 0 status_sel 4 [4:4] 4 resvd_exec 6 [6:5] 5 wrap_target 11 [11:7] 7 pend 16 [16:12] 12 out_sticky 17 [17:17] 17 inline_out_en 18 [18:18] 18 out_en_sel 23 [23:19] 19 jmp_pin 28 [28:24] 24 side_pindir 29 [29:29] 29 sideset_enable_bit 30 [30:30] 30 exec_stalled_ro2 31 [31:31] 31 SFR_SM2_SHIFTCTRL 0x0100 0x00 32 resvd_shift 15 [15:0] 0 auto_push 16 [16:16] 16 auto_pull 17 [17:17] 17 in_shift_dir 18 [18:18] 18 out_shift_dir 19 [19:19] 19 isr_threshold 24 [24:20] 20 osr_threshold 29 [29:25] 25 join_tx 30 [30:30] 30 join_rx 31 [31:31] 31 SFR_SM2_ADDR 0x0104 0x00 32 pc 4 [4:0] 0 SFR_SM2_INSTR 0x0108 0x00 32 imm_instr 15 [15:0] 0 SFR_SM2_PINCTRL 0x010c 0x00 32 pins_out_base 4 [4:0] 0 pins_set_base 9 [9:5] 5 pins_side_base 14 [14:10] 10 pins_in_base 19 [19:15] 15 pins_out_count 25 [25:20] 20 pins_set_count 28 [28:26] 26 pins_side_count 31 [31:29] 29 SFR_SM3_CLKDIV 0x0110 0x00 32 unused_div 7 [7:0] 0 div_frac 15 [15:8] 8 div_int 31 [31:16] 16 SFR_SM3_EXECCTRL 0x0114 0x00 32 status_n 3 [3:0] 0 status_sel 4 [4:4] 4 resvd_exec 6 [6:5] 5 wrap_target 11 [11:7] 7 pend 16 [16:12] 12 out_sticky 17 [17:17] 17 inline_out_en 18 [18:18] 18 out_en_sel 23 [23:19] 19 jmp_pin 28 [28:24] 24 side_pindir 29 [29:29] 29 sideset_enable_bit 30 [30:30] 30 exec_stalled_ro3 31 [31:31] 31 SFR_SM3_SHIFTCTRL 0x0118 0x00 32 resvd_shift 15 [15:0] 0 auto_push 16 [16:16] 16 auto_pull 17 [17:17] 17 in_shift_dir 18 [18:18] 18 out_shift_dir 19 [19:19] 19 isr_threshold 24 [24:20] 20 osr_threshold 29 [29:25] 25 join_tx 30 [30:30] 30 join_rx 31 [31:31] 31 SFR_SM3_ADDR 0x011c 0x00 32 pc 4 [4:0] 0 SFR_SM3_INSTR 0x0120 0x00 32 imm_instr 15 [15:0] 0 SFR_SM3_PINCTRL 0x0124 0x00 32 pins_out_base 4 [4:0] 0 pins_set_base 9 [9:5] 5 pins_side_base 14 [14:10] 10 pins_in_base 19 [19:15] 15 pins_out_count 25 [25:20] 20 pins_set_count 28 [28:26] 26 pins_side_count 31 [31:29] 29 SFR_INTR 0x0128 0x00 32 intr_rxnempty 3 [3:0] 0 intr_txnfull 7 [7:4] 4 intr_sm 11 [11:8] 8 SFR_IRQ0_INTE 0x012c 0x00 32 irq0_inte_rxnempty 3 [3:0] 0 irq0_inte_txnfull 7 [7:4] 4 irq0_inte_sm 11 [11:8] 8 SFR_IRQ0_INTF 0x0130 0x00 32 irq0_intf_rxnempty 3 [3:0] 0 irq0_intf_txnfull 7 [7:4] 4 irq0_intf_sm 11 [11:8] 8 SFR_IRQ0_INTS 0x0134 0x00 32 irq0_ints_rxnempty 3 [3:0] 0 irq0_ints_txnfull 7 [7:4] 4 irq0_ints_sm 11 [11:8] 8 SFR_IRQ1_INTE 0x0138 0x00 32 irq1_inte_rxnempty 3 [3:0] 0 irq1_inte_txnfull 7 [7:4] 4 irq1_inte_sm 11 [11:8] 8 SFR_IRQ1_INTF 0x013c 0x00 32 irq1_intf_rxnempty 3 [3:0] 0 irq1_intf_txnfull 7 [7:4] 4 irq1_intf_sm 11 [11:8] 8 SFR_IRQ1_INTS 0x0140 0x00 32 irq1_ints_rxnempty 3 [3:0] 0 irq1_ints_txnfull 7 [7:4] 4 irq1_ints_sm 11 [11:8] 8 SFR_IO_OE_INV 0x0180 0x00 32 sfr_io_oe_inv 31 [31:0] 0 SFR_IO_O_INV 0x0184 0x00 32 sfr_io_o_inv 31 [31:0] 0 SFR_IO_I_INV 0x0188 0x00 32 sfr_io_i_inv 31 [31:0] 0 SFR_FIFO_MARGIN 0x018c 0x00 32 fifo_tx_margin0 1 [1:0] 0 fifo_rx_margin0 3 [3:2] 2 fifo_tx_margin1 5 [5:4] 4 fifo_rx_margin1 7 [7:6] 6 fifo_tx_margin2 9 [9:8] 8 fifo_rx_margin2 11 [11:10] 10 fifo_tx_margin3 13 [13:12] 12 fifo_rx_margin3 15 [15:14] 14 SFR_ZERO0 0x0190 0x00 32 sfr_zero0 31 [31:0] 0 SFR_ZERO1 0x0194 0x00 32 sfr_zero1 31 [31:0] 0 SFR_ZERO2 0x0198 0x00 32 sfr_zero2 31 [31:0] 0 SFR_ZERO3 0x019c 0x00 32 sfr_zero3 31 [31:0] 0 0 0x1a0 registers BIO_BDMA 0x50124000 BIO_BDMA SFR_CTRL 0x0000 0x00 32 en 3 [3:0] 0 restart 7 [7:4] 4 clkdiv_restart 11 [11:8] 8 SFR_CFGINFO 0x0004 0x00 32 constant0 7 [7:0] 0 constant1 15 [15:8] 8 constant2 31 [31:16] 16 SFR_CONFIG 0x0008 0x00 32 snap_output_to_which 1 [1:0] 0 snap_output_to_quantum 2 [2:2] 2 snap_input_to_which 4 [4:3] 3 snap_input_to_quantum 5 [5:5] 5 disable_filter_peri 6 [6:6] 6 disable_filter_mem 7 [7:7] 7 SFR_FLEVEL 0x000c 0x00 32 pclk_regfifo_level0 3 [3:0] 0 pclk_regfifo_level1 7 [7:4] 4 pclk_regfifo_level2 11 [11:8] 8 pclk_regfifo_level3 15 [15:12] 12 SFR_TXF0 0x0010 0x00 32 fdin 31 [31:0] 0 SFR_TXF1 0x0014 0x00 32 fdin 31 [31:0] 0 SFR_TXF2 0x0018 0x00 32 fdin 31 [31:0] 0 SFR_TXF3 0x001c 0x00 32 fdin 31 [31:0] 0 SFR_RXF0 0x0020 0x00 32 fdout 31 [31:0] 0 SFR_RXF1 0x0024 0x00 32 fdout 31 [31:0] 0 SFR_RXF2 0x0028 0x00 32 fdout 31 [31:0] 0 SFR_RXF3 0x002c 0x00 32 fdout 31 [31:0] 0 SFR_ELEVEL 0x0030 0x00 32 fifo_event_level0 3 [3:0] 0 fifo_event_level1 7 [7:4] 4 fifo_event_level2 11 [11:8] 8 fifo_event_level3 15 [15:12] 12 fifo_event_level4 19 [19:16] 16 fifo_event_level5 23 [23:20] 20 fifo_event_level6 27 [27:24] 24 fifo_event_level7 31 [31:28] 28 SFR_ETYPE 0x0034 0x00 32 fifo_event_lt_mask 7 [7:0] 0 fifo_event_eq_mask 15 [15:8] 8 fifo_event_gt_mask 23 [23:16] 16 SFR_EVENT_SET 0x0038 0x00 32 sfr_event_set 23 [23:0] 0 SFR_EVENT_CLR 0x003c 0x00 32 sfr_event_clr 23 [23:0] 0 SFR_EVENT_STATUS 0x0040 0x00 32 sfr_event_status 31 [31:0] 0 SFR_EXTCLOCK 0x0044 0x00 32 use_extclk 3 [3:0] 0 extclk_gpio_0 8 [8:4] 4 extclk_gpio_1 13 [13:9] 9 extclk_gpio_2 18 [18:14] 14 extclk_gpio_3 23 [23:19] 19 SFR_FIFO_CLR 0x0048 0x00 32 sfr_fifo_clr 3 [3:0] 0 SFR_QDIV0 0x0050 0x00 32 unused_div 0 [0:0] 0 div_frac 1 [1:1] 1 div_int 2 [2:2] 2 SFR_QDIV1 0x0054 0x00 32 unused_div 0 [0:0] 0 div_frac 1 [1:1] 1 div_int 2 [2:2] 2 SFR_QDIV2 0x0058 0x00 32 unused_div 0 [0:0] 0 div_frac 1 [1:1] 1 div_int 2 [2:2] 2 SFR_QDIV3 0x005c 0x00 32 unused_div 0 [0:0] 0 div_frac 1 [1:1] 1 div_int 2 [2:2] 2 SFR_SYNC_BYPASS 0x0060 0x00 32 sfr_sync_bypass 31 [31:0] 0 SFR_IO_OE_INV 0x0064 0x00 32 sfr_io_oe_inv 31 [31:0] 0 SFR_IO_O_INV 0x0068 0x00 32 sfr_io_o_inv 31 [31:0] 0 SFR_IO_I_INV 0x006c 0x00 32 sfr_io_i_inv 31 [31:0] 0 SFR_IRQMASK_0 0x0070 0x00 32 sfr_irqmask_0 31 [31:0] 0 SFR_IRQMASK_1 0x0074 0x00 32 sfr_irqmask_1 31 [31:0] 0 SFR_IRQMASK_2 0x0078 0x00 32 sfr_irqmask_2 31 [31:0] 0 SFR_IRQMASK_3 0x007c 0x00 32 sfr_irqmask_3 31 [31:0] 0 SFR_IRQ_EDGE 0x0080 0x00 32 sfr_irq_edge 3 [3:0] 0 SFR_DBG_PADOUT 0x0084 0x00 32 sfr_dbg_padout 31 [31:0] 0 SFR_DBG_PADOE 0x0088 0x00 32 sfr_dbg_padoe 31 [31:0] 0 SFR_DBG0 0x0090 0x00 32 dbg_pc 0 [0:0] 0 trap 1 [1:1] 1 SFR_DBG1 0x0094 0x00 32 dbg_pc 0 [0:0] 0 trap 1 [1:1] 1 SFR_DBG2 0x0098 0x00 32 dbg_pc 0 [0:0] 0 trap 1 [1:1] 1 SFR_DBG3 0x009c 0x00 32 dbg_pc 0 [0:0] 0 trap 1 [1:1] 1 SFR_MEM_GUTTER 0x00a0 0x00 32 sfr_mem_gutter 19 [19:0] 0 SFR_PERI_GUTTER 0x00a4 0x00 32 sfr_peri_gutter 19 [19:0] 0 SFR_DMAREQ_MAP_CR_EVMAP0 0x00b0 0x00 32 cr_evmap0 31 [31:0] 0 SFR_DMAREQ_MAP_CR_EVMAP1 0x00b4 0x00 32 cr_evmap1 31 [31:0] 0 SFR_DMAREQ_MAP_CR_EVMAP2 0x00b8 0x00 32 cr_evmap2 31 [31:0] 0 SFR_DMAREQ_MAP_CR_EVMAP3 0x00bc 0x00 32 cr_evmap3 31 [31:0] 0 SFR_DMAREQ_MAP_CR_EVMAP4 0x00c0 0x00 32 cr_evmap4 31 [31:0] 0 SFR_DMAREQ_MAP_CR_EVMAP5 0x00c4 0x00 32 cr_evmap5 31 [31:0] 0 SFR_DMAREQ_STAT_SR_EVSTAT0 0x00c8 0x00 32 sr_evstat0 31 [31:0] 0 SFR_DMAREQ_STAT_SR_EVSTAT1 0x00cc 0x00 32 sr_evstat1 31 [31:0] 0 SFR_DMAREQ_STAT_SR_EVSTAT2 0x00d0 0x00 32 sr_evstat2 31 [31:0] 0 SFR_DMAREQ_STAT_SR_EVSTAT3 0x00d4 0x00 32 sr_evstat3 31 [31:0] 0 SFR_DMAREQ_STAT_SR_EVSTAT4 0x00d8 0x00 32 sr_evstat4 31 [31:0] 0 SFR_DMAREQ_STAT_SR_EVSTAT5 0x00dc 0x00 32 sr_evstat5 31 [31:0] 0 SFR_FILTER_BASE_0 0x00e0 0x00 32 filter_base 19 [19:0] 0 SFR_FILTER_BOUNDS_0 0x00e4 0x00 32 filter_bounds 19 [19:0] 0 SFR_FILTER_BASE_1 0x00e8 0x00 32 filter_base 19 [19:0] 0 SFR_FILTER_BOUNDS_1 0x00ec 0x00 32 filter_bounds 19 [19:0] 0 SFR_FILTER_BASE_2 0x00f0 0x00 32 filter_base 19 [19:0] 0 SFR_FILTER_BOUNDS_2 0x00f4 0x00 32 filter_bounds 19 [19:0] 0 SFR_FILTER_BASE_3 0x00f8 0x00 32 filter_base 19 [19:0] 0 SFR_FILTER_BOUNDS_3 0x00fc 0x00 32 filter_bounds 19 [19:0] 0 0 0x100 registers CORESUB_SRAMTRM 0x40014000 CORESUB_SRAMTRM SFR_CACHE 0x0000 0x00 32 sfr_cache 2 [2:0] 0 SFR_ITCM 0x0004 0x00 32 sfr_itcm 4 [4:0] 0 SFR_DTCM 0x0008 0x00 32 sfr_dtcm 4 [4:0] 0 SFR_SRAM0 0x000c 0x00 32 sfr_sram0 4 [4:0] 0 SFR_SRAM1 0x0010 0x00 32 sfr_sram1 4 [4:0] 0 SFR_VEXRAM 0x0014 0x00 32 sfr_vexram 2 [2:0] 0 SFR_SRAMERR 0x0020 0x00 32 srambankerr 3 [3:0] 0 0 0x24 registers MDMA 0x40012000 MDMA SFR_EVSEL_CR_EVSEL0 0x0000 0x00 32 cr_evsel0 7 [7:0] 0 SFR_EVSEL_CR_EVSEL1 0x0004 0x00 32 cr_evsel1 7 [7:0] 0 SFR_EVSEL_CR_EVSEL2 0x0008 0x00 32 cr_evsel2 7 [7:0] 0 SFR_EVSEL_CR_EVSEL3 0x000c 0x00 32 cr_evsel3 7 [7:0] 0 SFR_EVSEL_CR_EVSEL4 0x0010 0x00 32 cr_evsel4 7 [7:0] 0 SFR_EVSEL_CR_EVSEL5 0x0014 0x00 32 cr_evsel5 7 [7:0] 0 SFR_EVSEL_CR_EVSEL6 0x0018 0x00 32 cr_evsel6 7 [7:0] 0 SFR_EVSEL_CR_EVSEL7 0x001c 0x00 32 cr_evsel7 7 [7:0] 0 SFR_CR_CR_MDMAREQ0 0x0020 0x00 32 cr_mdmareq0 4 [4:0] 0 SFR_CR_CR_MDMAREQ1 0x0024 0x00 32 cr_mdmareq1 4 [4:0] 0 SFR_CR_CR_MDMAREQ2 0x0028 0x00 32 cr_mdmareq2 4 [4:0] 0 SFR_CR_CR_MDMAREQ3 0x002c 0x00 32 cr_mdmareq3 4 [4:0] 0 SFR_CR_CR_MDMAREQ4 0x0030 0x00 32 cr_mdmareq4 4 [4:0] 0 SFR_CR_CR_MDMAREQ5 0x0034 0x00 32 cr_mdmareq5 4 [4:0] 0 SFR_CR_CR_MDMAREQ6 0x0038 0x00 32 cr_mdmareq6 4 [4:0] 0 SFR_CR_CR_MDMAREQ7 0x003c 0x00 32 cr_mdmareq7 4 [4:0] 0 SFR_SR_SR_MDMAREQ0 0x0040 0x00 32 sr_mdmareq0 4 [4:0] 0 SFR_SR_SR_MDMAREQ1 0x0044 0x00 32 sr_mdmareq1 4 [4:0] 0 SFR_SR_SR_MDMAREQ2 0x0048 0x00 32 sr_mdmareq2 4 [4:0] 0 SFR_SR_SR_MDMAREQ3 0x004c 0x00 32 sr_mdmareq3 4 [4:0] 0 SFR_SR_SR_MDMAREQ4 0x0050 0x00 32 sr_mdmareq4 4 [4:0] 0 SFR_SR_SR_MDMAREQ5 0x0054 0x00 32 sr_mdmareq5 4 [4:0] 0 SFR_SR_SR_MDMAREQ6 0x0058 0x00 32 sr_mdmareq6 4 [4:0] 0 SFR_SR_SR_MDMAREQ7 0x005c 0x00 32 sr_mdmareq7 4 [4:0] 0 0 0x60 registers QFC 0x40010000 QFC SFR_IO 0x0000 0x00 32 sfr_io 7 [7:0] 0 SFR_AR 0x0004 0x00 32 sfr_ar 31 [31:0] 0 SFR_IODRV 0x0008 0x00 32 paddrvsel 11 [11:0] 0 CR_XIP_ADDRMODE 0x0010 0x00 32 cr_xip_addrmode 1 [1:0] 0 CR_XIP_OPCODE 0x0014 0x00 32 cr_xip_opcode 31 [31:0] 0 CR_XIP_WIDTH 0x0018 0x00 32 cr_xip_width 5 [5:0] 0 CR_XIP_SSEL 0x001c 0x00 32 cr_xip_ssel 6 [6:0] 0 CR_XIP_DUMCYC 0x0020 0x00 32 cr_xip_dumcyc 15 [15:0] 0 CR_XIP_CFG 0x0024 0x00 32 cr_xip_cfg 13 [13:0] 0 CR_AESKEY_AESKEYIN0 0x0040 0x00 32 aeskeyin0 31 [31:0] 0 CR_AESKEY_AESKEYIN1 0x0044 0x00 32 aeskeyin1 31 [31:0] 0 CR_AESKEY_AESKEYIN2 0x0048 0x00 32 aeskeyin2 31 [31:0] 0 CR_AESKEY_AESKEYIN3 0x004c 0x00 32 aeskeyin3 31 [31:0] 0 CR_AESENA 0x0050 0x00 32 cr_aesena 0 [0:0] 0 0 0x54 registers MBOX_APB 0x40013000 MBOX_APB SFR_WDATA 0x0000 0x00 32 sfr_wdata 31 [31:0] 0 SFR_RDATA 0x0004 0x00 32 sfr_rdata 31 [31:0] 0 SFR_STATUS 0x0008 0x00 32 rx_avail 0 [0:0] 0 tx_free 1 [1:1] 1 abort_in_progress 2 [2:2] 2 abort_ack 3 [3:3] 3 tx_err 4 [4:4] 4 rx_err 5 [5:5] 5 SFR_ABORT 0x0018 0x00 32 sfr_abort 31 [31:0] 0 SFR_DONE 0x001c 0x00 32 sfr_done 31 [31:0] 0 0 0x20 registers GLUECHAIN 0x40054000 GLUECHAIN SFR_GCMASK 0x0000 0x00 32 cr_gcmask 31 [31:0] 0 SFR_GCSR 0x0004 0x00 32 gluereg 31 [31:0] 0 SFR_GCRST 0x0008 0x00 32 gluerst 31 [31:0] 0 SFR_GCTEST 0x000c 0x00 32 gluetest 31 [31:0] 0 0 0x10 registers BIO_FIFO0 0x50129000 BIO_FIFO0 SFR_FLEVEL 0x000c 0x00 32 pclk_regfifo_level0 3 [3:0] 0 pclk_regfifo_level1 7 [7:4] 4 pclk_regfifo_level2 11 [11:8] 8 pclk_regfifo_level3 15 [15:12] 12 SFR_TXF0 0x0010 0x00 32 fdin 31 [31:0] 0 SFR_RXF0 0x0020 0x00 32 fdout 31 [31:0] 0 SFR_EVENT_SET 0x0038 0x00 32 sfr_event_set 23 [23:0] 0 SFR_EVENT_CLR 0x003c 0x00 32 sfr_event_clr 23 [23:0] 0 SFR_EVENT_STATUS 0x0040 0x00 32 sfr_event_status 31 [31:0] 0 0 0x44 registers BIO_FIFO1 0x5012A000 BIO_FIFO1 SFR_FLEVEL 0x000c 0x00 32 pclk_regfifo_level0 3 [3:0] 0 pclk_regfifo_level1 7 [7:4] 4 pclk_regfifo_level2 11 [11:8] 8 pclk_regfifo_level3 15 [15:12] 12 SFR_TXF1 0x0014 0x00 32 fdin 31 [31:0] 0 SFR_RXF1 0x0024 0x00 32 fdout 31 [31:0] 0 SFR_EVENT_SET 0x0038 0x00 32 sfr_event_set 23 [23:0] 0 SFR_EVENT_CLR 0x003c 0x00 32 sfr_event_clr 23 [23:0] 0 SFR_EVENT_STATUS 0x0040 0x00 32 sfr_event_status 31 [31:0] 0 0 0x44 registers BIO_FIFO2 0x5012B000 BIO_FIFO2 SFR_FLEVEL 0x000c 0x00 32 pclk_regfifo_level0 3 [3:0] 0 pclk_regfifo_level1 7 [7:4] 4 pclk_regfifo_level2 11 [11:8] 8 pclk_regfifo_level3 15 [15:12] 12 SFR_TXF2 0x0018 0x00 32 fdin 31 [31:0] 0 SFR_RXF2 0x0028 0x00 32 fdout 31 [31:0] 0 SFR_EVENT_SET 0x0038 0x00 32 sfr_event_set 23 [23:0] 0 SFR_EVENT_CLR 0x003c 0x00 32 sfr_event_clr 23 [23:0] 0 SFR_EVENT_STATUS 0x0040 0x00 32 sfr_event_status 31 [31:0] 0 0 0x44 registers BIO_FIFO3 0x5012C000 BIO_FIFO3 SFR_FLEVEL 0x000c 0x00 32 pclk_regfifo_level0 3 [3:0] 0 pclk_regfifo_level1 7 [7:4] 4 pclk_regfifo_level2 11 [11:8] 8 pclk_regfifo_level3 15 [15:12] 12 SFR_TXF3 0x001c 0x00 32 fdin 31 [31:0] 0 SFR_RXF3 0x002c 0x00 32 fdout 31 [31:0] 0 SFR_EVENT_SET 0x0038 0x00 32 sfr_event_set 23 [23:0] 0 SFR_EVENT_CLR 0x003c 0x00 32 sfr_event_clr 23 [23:0] 0 SFR_EVENT_STATUS 0x0040 0x00 32 sfr_event_status 31 [31:0] 0 0 0x44 registers PL230 PL230 DMA Controller Core 1073811456 0x0 0x40 registers 0x40 0xc reserved 0x4c 0x4 registers STATUS DMA Status Register 0x00 32 read-only 0x101f0000 0xffffff0f TEST_STATUS Test status configuration 28 4 read-only CHNLS_MINUS1 Number of available DMA channels minus 1 16 5 read-only STATE Current state of the control machine 4 4 read-only MASTER_ENABLE Master enable status 0 1 read-only CFG DMA Configuration Register 0x04 32 write-only 0x00000000 0x00000000 CHNL_PROT_CTRL Set AHB-Lite configuration 5 3 read-only MASTER_ENABLE MASTER_ENABLE 0 1 write-only CTRLBASEPTR DMA Control Data Base Pointer Register 0x08 32 read-write 0x00000000 0xffffffff CTRL_BASE_PTR CTRL_BASE_PTR 8 24 read-write ALTCTRLBASEPTR DMA Channel Alternate Control Data Base Pointer Register 0x0C 32 read-only 0x00000000 0xffffffff ALT_CTRL_BASE_PTR ALT_CTRL_BASE_PTR 0 32 read-only DMA_WAITONREQ_STATUS Channel wait on request status 0x10 32 read-only 0x00000000 0xffffffff DMA_WAITONREQ_STATUS Wait on request status, one bit per channel 0 8 read-only CHNLSWREQUEST DMA Channel Software Request Register 0x14 32 write-only 0x00000000 0x00000000 CHNL_SW_REQUEST CHNL_SW_REQUEST 0 8 write-only CHNLUSEBURSTSET DMA Channel Useburst Set Register 0x18 32 read-write 0x00000000 0xffffffff CHNL_USEBURST_SET CHNL_USEBURST_SET 0 8 read-write CHNLUSEBURSTCLR DMA Channel Useburst Clear Register 0x1C 32 write-only 0x00000000 0x00000000 CHNL_USEBURST_CLR CHNL_USEBURST_CLR 0 8 write-only CHNLREQMASKSET DMA Channel Request Mask Set Register 0x20 32 read-write 0x00000000 0xffffffff CHNL_REQ_MASK_SET CHNL_REQ_MASK_SET 0 8 read-write CHNLREQMASKCLR DMA Channel Request Mask Clear Register 0x24 32 write-only 0x00000000 0x00000000 CHNL_REQ_MASK_CLR CHNL_REQ_MASK_CLR 0 8 write-only CHNLENABLESET DMA Channel Enable Set Register 0x28 32 read-write 0x00000000 0xffffffff CHNL_ENABLE_SET CHNL_ENABLE_SET 0 8 read-write CHNLENABLECLR DMA Channel Enable Clear Register 0x2C 32 write-only 0x00000000 0x00000000 CHNL_ENABLE_CLR CHNL_ENABLE_CLR 0 8 write-only CHNLPRIALTSET DMA Channel Primary-Alternate Set Register 0x30 32 read-write 0x00000000 0xffffffff CHNL_PRI_ALT_SET CHNL_PRI_ALT_SET 0 8 read-write CHNLPRIALTCLR DMA Channel Primary-Alternate Clear Register 0x34 32 write-only 0x00000000 0x00000000 CHNL_PRI_ALT_CLR CHNL_PRI_ALT_CLR 0 8 write-only CHNLPRIORITYSET DMA Channel Priority Set Register 0x38 32 read-write 0x00000000 0xffffffff CHNL_PRIORITY_SET CHNL_PRIORITY_SET 0 8 read-write CHNLPRIORITYCLR DMA Channel Priority Clear Register 0x3C 32 write-only 0x00000000 0x00000000 CHNL_PRIORITY_CLR CHNL_PRIORITY_CLR 0 8 write-only ERRCLR DMA Bus Error Clear Register 0x4C 32 read-write 0x00000000 0xffffffff ERR_CLR ERR_CLR 0 1 read-write PERIPH_ID_0 Peripheral ID byte 0 0xFE0 32 read-write 0x00000000 0xffffffff PART_NUMBER_LSB Identifies the part number 0 8 read-only PERIPH_ID_1 Peripheral ID byte 1 0xFE4 32 read-write 0x00000000 0xffffffff PART_NUMBER_MSB Identifies the part number 0 4 read-only JEP106_LSB Designer ID LSB 4 3 read-only PERIPH_ID_2 Peripheral ID byte 2 0xFE8 32 read-write 0x00000000 0xffffffff JEP106_MSB Designer ID MSB 0 3 read-only JEDEC_USED Identifies if JP106 ID code is used 3 1 read-only REVISION Identifies revision number of peripheral 4 4 read-only SCE 0x40028000 0x00008000 SYSCTRL 0x40040000 0x00010000 IFSUB 0x50120000 0x00003000 CORESUB 0x40010000 0x00010000 SECSUB 0x40050000 0x00010000 PIO 0x50123000 0x00001000 BIO_BDMA 0x50124000 0x00001000 SEG_LKEY 0x40020000 0x00000100 SEG_KEY 0x40020100 0x00000100 SEG_SKEY 0x40020200 0x00000100 SEG_SCRT 0x40020300 0x00000100 SEG_MSG 0x40020400 0x00000200 SEG_HOUT 0x40020600 0x00000100 SEG_SOB 0x40020700 0x00000100 SEG_PCON 0x40020800 0x00000000 SEG_PKB 0x40020800 0x00000200 SEG_PIB 0x40020A00 0x00000400 SEG_PSIB 0x40020E00 0x00000400 SEG_POB 0x40021200 0x00000400 SEG_PSOB 0x40021600 0x00000400 SEG_AKEY 0x40021A00 0x00000100 SEG_AIB 0x40021B00 0x00000100 SEG_AOB 0x40021C00 0x00000100 SEG_RNGA 0x40021D00 0x00000400 SEG_RNGB 0x40022100 0x00000400 IFRAM0 0x50000000 0x00020000 IFRAM1 0x50020000 0x00020000 NULL 0x50040000 0x00010000 UDMA 0x50100000 0x00020000 UDP 0x50122000 0x00001000 SDDC_DAT 0x50140000 0x00010000 UDC 0x50200000 0x00010000 SRAM 0x61000000 0x00200000 RERAM 0x60000000 0x00400000 XIP 0x70000000 0x04000000 PL230 0x40011000 0x00001000 MDMA 0x40012000 0x00001000 MBOX_APB 0x40013000 0x00001000 IOX 0x5012F000 0x00001000 AOC 0x40060000 0x00001000 BIO_IMEM0 0x50125000 0x00001000 BIO_IMEM1 0x50126000 0x00001000 BIO_IMEM2 0x50127000 0x00001000 BIO_IMEM3 0x50128000 0x00001000 BIO_FIFO0 0x50129000 0x00001000 BIO_FIFO1 0x5012A000 0x00001000 BIO_FIFO2 0x5012B000 0x00001000 BIO_FIFO3 0x5012C000 0x00001000