// vim: ft=bitsy
pub mod Top {
  input clk : Clock;
  output out : UInt<8>;
  input in : UInt<8>;

  mod buffer of Buffer;
  buffer.clk $= clk;
  buffer.in := in;

  out := buffer.out->add(1);
}

mod Buffer {
  input clk : Clock;
  output out : UInt<8>;
  input in : UInt<8>;

  reg r : UInt<8> on clk;
  r <= in;
  out := r;
}

mod ShiftReg {
  input clk : Clock;
  input in : Valid<Word<8>>;
  output out: Bit;

  reg r : Vec<Bit, 4> on clk;
  r <= match in {
    Valid(in_value) => in_valid;
    Invalid() => r[3..1]->prepend(0);
  };
  out := r[0];
}

/*

virdant.module @Top {
  %clk = virdant.input : !virdant.clock
  %in = virdant.input : !virdant.word<8>

  %out = virdant.output : !virdant.word<8> {
    %buffer_out = virdant.outport(%buffer) { port = "out" }
    virdant.connect(%buffer_out)
  }

  %buffer = virdant.submodule(@Buffer)  {
    virdant.inport(%clk) { name = "clk" }
    virdant.inport(%in) { name = "in" }
  }
}

virdant.module @Buffer()  {
  %clk = virdant.input @clk : !virdant.clock
  %in = virdant.input @in : !virdant.word<8>
  %out = virdant.output @out(%r) : !virdant.word<8>

  %r = virdant.reg(%clock, %in)
}


Ops Summary:
  virdant.methodcall(...)

  virdant.module
    declares a module.
    Inside is a list of all the components.
    the inside is a graph region.
    has a attribute to preserve the name

  virdant.input
    declares an input port
    has a attribute to preserve the name

  virdant.output
    declares an output port
    has an SSA region that represents the right-hand side of the := statement.
    has a attribute to preserve the name

  virdant.reg
    declares a reg

  virdant.wire
    declares a wire

  virdant.connect
    a terminator for the SSA blocks for virdant.output, virdant.reg, virdant.wire
    only valid within virdant.output, virdant.reg, virdant.wire, virdant.port

  virdant.submodule { def = @Buffer }
    instantiate a submodule instance
    Takes a (symbol) argument

  virdant.port { name = "clk" }
    opens a region for connecting to the named input port
    only valid inside a virdant.submodule

*/