WIZnet W7500x 1.0.0 The IOP (Internet Offload Processor) W7500P is the one-chip solution which integrates an ARM Cortex-M0, 128KB Flash and hardwired TCP/IP core & PHY for various embedded application platform especially requiring ‘Internet of things’. The TCP/IP core is a market-proven hardwired TCP/IP stack with an integrated Ethernet MAC. The Hardwired TCP/IP stack supports the TCP, UDP, IPv4, ICMP, ARP, IGMP and PPPoE which has been used in various applications for years. W7500P suits best for users who need Internet connectivity for application. CM0 r0p0 little false false 2 false 8 32 32 read-write 0x00000000 0xFFFFFFFF WDT WDT 0x40000000 0 0xc04 registers LOAD Watchdog timer Load register 0x000 0xffffffff WLR Watchdog timer Load [31:0] VALUE Watchdog timer Value register 0x004 read-only 0xffffffff WVR Watchdog timer Value [31:0] CONTROL Watchdog timer Control register 0x008 0x3 REN Reset Request Enable [1:1] Disable 0 Enable 1 IEN Interrupt Enable [0:0] Disable 0 Enable 1 INTCLR Watchdog timer Clear Interrupt register 0x00C write-only 0x1 WIC Watchdog timer Interrupt Clear [0:0] Clear 1 RIS Watchdog timer Raw Interrupt Status register 0x010 read-only 0x1 RIS Watchdog timer Raw Interrupt Status [0:0] MIS Watchdog timer Masked Interrupt Status register 0x014 read-only 0x1 MIS Watchdog timer Masked Interrupt Status [0:0] LOCK Watchdog timer Lock register 0xC00 0xffffffff ERW ERW[31:1] bits (Enable Register Writes) [31:1] Lock 0 UnLock 0x1ACCE551 WES Register Write Enable status [0:0] NotLocked 0 Locked 1 DUALTIMER0_0 DUALTIMER 0x40001000 0 0x84 registers DUALTIMER0 Dual Timer 0 Interrupt 12 LOAD Timer Load register 0x00 0xffffffff TLR Timer Load [31:0] VALUE Timer Counter Current Value register 0x04 read-only 0xffffffff TVR Timer Value [31:0] CONTROL Timer Control register 0x08 0xef TE Timer Enable [7:7] TM Timer Mode [6:6] IE Interrupt Enable [5:5] TP Timer Prescale [3:2] TS Timer Size [1:1] OC One-shot Count [0:0] INTCLR Timer Interrupt Clear register 0x0C write-only 0x1 TIC Interrupt Clear [0:0] RIS Timer Raw Interrupt Status register 0x10 read-only 0x1 RIS Raw Interrupt Status flag [0:0] MIS Timer Masked Interrupt Status register 0x14 read-only 0x1 MIS Masked Interrupt Status flag [0:0] BGLOAD Background Load register 0x18 0xffffffff BGL Background Load [31:0] CE Clock enable register 0x80 0x0 DUALTIMER0_1 0x40001020 DUALTIMER0 Dual Timer 0 Interrupt 12 DUALTIMER1_0 0x40002000 DUALTIMER1 Dual Timer 1 Interrupt 13 DUALTIMER1_1 0x40002020 DUALTIMER1 Dual Timer 1 Interrupt 13 PWM PWM 0x40005800 0 0xc registers IER Interrupt enable register 0x00 0xff IE7 Channel 7 [7:7] Disable 0 Enable 1 IE6 Channel 6 [6:6] Disable 0 Enable 1 IE5 Channel 5 [5:5] Disable 0 Enable 1 IE4 Channel 4 [4:4] Disable 0 Enable 1 IE3 Channel 3 [3:3] Disable 0 Enable 1 IE2 Channel 2 [2:2] Disable 0 Enable 1 IE1 Channel 1 [1:1] Disable 0 Enable 1 IE0 Channel 0 [0:0] Disable 0 Enable 1 SSR Start Stop register 0x04 0xff SS7 Channel 7 [7:7] Stop 0 Start 1 SS6 Channel 6 [6:6] Stop 0 Start 1 SS5 Channel 5 [5:5] Stop 0 Start 1 SS4 Channel 4 [4:4] Stop 0 Start 1 SS3 Channel 3 [3:3] Stop 0 Start 1 SS2 Channel 2 [2:2] Stop 0 Start 1 SS1 Channel 1 [1:1] Stop 0 Start 1 SS0 Channel 0 [0:0] Stop 0 Start 1 PSR Pause register 0x08 0xff PS7 Channel 7 [7:7] NotPaused 0 Paused 1 PS6 Channel 6 [6:6] NotPaused 0 Paused 1 PS5 Channel 5 [5:5] NotPaused 0 Paused 1 PS4 Channel 4 [4:4] NotPaused 0 Paused 1 PS3 Channel 3 [3:3] NotPaused 0 Paused 1 PS2 Channel 2 [2:2] NotPaused 0 Paused 1 PS1 Channel 1 [1:1] NotPaused 0 Paused 1 PS0 Channel 0 [0:0] NotPaused 0 Paused 1 PWM0 PWM 0x40005000 0 0x40 registers PWM0 PWM 0 Interrupt 14 IR Interrupt register 0x00 read-only 0x7 CI Capture Interrupt occurs [2:2] NotOccured 0 Occured 1 OI Overflow Interrupt occurs [1:1] NotOccured 0 Occured 1 MI Match Interrupt occurs [0:0] NotOccured 0 Occured 1 IER Interrupt enable register 0x04 0x7 CIE Capture Interrupt Enable [2:2] NotEnabled 0 Enabled 1 OIE Overflow Interrupt Enable [1:1] NotEnabled 0 Enabled 1 MIE Match Interrupt Enable [0:0] NotEnabled 0 Enabled 1 ICR Interrupt clear register 0x08 write-only 0x7 CIC Capture Interrupt is cleared [2:2] Clear 1 OIC Overflow Interrupt is cleared [1:1] Clear 1 MIC Match Interrupt is cleared [0:0] Clear 1 TCR Timer/Counter register 0x0C read-only 0xffffffff TCR Timer/Counter [31:0] PCR Prescale counter register 0x10 read-only 0x3f PCR Prescale Counter [5:0] PR Prescale register 0x14 0x3f PR Prescale [5:0] MR Match register 0x18 0xffffffff MR Match [31:0] LR Limit register 0x1C 0xffffffff LR Limit [31:0] UDMR Up-Down mode register 0x20 0x1 UDM Up-Down mode [0:0] Up 0 Down 1 TCMR Timer/Counter mode register 0x24 0x3 TCM TCM[1:0] bits (Timer/Counter mode) [1:0] Timer 0b00 CounterRising 0b01 CounterFalling 0b10 CounterToggle 0b11 PEEER PWM output enable and external input enable register 0x28 0x3 PEEE PWM output Enable and External input Enable [1:0] OutDisableInDisable 0b00 OutDisableInEnable 0b01 OutEnableInDisable 0b10 CMR Capture mode register 0x2C 0x1 CM Capture mode [0:0] RisingEdge 0 FallingEdge 1 CR Capture register 0x30 read-only 0xffffffff CR Capture [31:0] PDMR Periodic mode register 0x34 0x1 PDM Periodic Mode [0:0] Periodic 0 OneShot 1 DZER Dead-zone enable register 0x38 0x1 DZE Dead Zone Enable [0:0] Disable 0 Enable 1 DZCR Dead-zone counter register 0x3C 0x3ff DZC Dead Zone Counter value [9:0] PWM1 0x40005100 PWM1 PWM 1 Interrupt 15 PWM2 0x40005200 PWM2 PWM 2 Interrupt 16 PWM3 0x40005300 PWM3 PWM 3 Interrupt 17 PWM4 0x40005400 PWM4 PWM 4 Interrupt 18 PWM5 0x40005500 PWM5 PWM 5 Interrupt 19 PWM6 0x40005600 PWM6 PWM 6 Interrupt 20 PWM7 0x40005700 PWM7 PWM 7 Interrupt 21 UART2 UART 0x40006000 0 0x14 registers UART2 UART 2 Interrupt 4 DR Data register 0x00 0xff DATA Receive (READ)/Transmit (WRITE) data [7:0] SR Status register 0x04 0xf RXO RX buffer overrun, wirte 1 to clear [3:3] TXO TX buffer overrun, wirte 1 to clear [2:2] RXBF RX buffer full, read only [1:1] TXBF TX buffer full, read only [0:0] CR Control register 0x08 0x3f ROIE RX overrun interrupt enable [5:5] TOIE TX overrun interrupt enable [4:4] RXIE RX interrupt enable [3:3] TXIE TX interrupt enable [2:2] RXE RX enable [1:1] TXE TX enable [0:0] ISR Interrupt Status register 0x0C read-only 0xf RXOI Receive Overrun Interrupt [3:3] TXOI Transmit Overrun Interrupt [2:2] RXI Receive Interrupt [1:1] TXI Transmit Interrupt [0:0] ICR Interrupt Clear register 0x0C write-only 0xf RXOI Receive Overrun Interrupt. Wirte 1 to clear [3:3] TXOI Transmit Overrun Interrupt. Wirte 1 to clear [2:2] RXI Receive Interrupt. Wirte 1 to clear [1:1] TXI Transmit Interrupt. Wirte 1 to clear [0:0] BDR Baudrate Divider register 0x10 0xfffff BAUDDIV Baud rate divider [19:0] RNG RNG 0x40007000 0 0x18 registers RUN RNG run register 0x000 0x1 RUN RUN RNG shift flag [0:0] Stop 0 Run 1 SEED RNG seed value register 0x004 0xffffffff SEED seed value of random number generator shift register [31:0] CLKSEL RNG Clock source select register 0x008 0x1 CLKSEL select clock source register of RNG shift register [0:0] RNG refer to clock generator block 0 PCLK 1 MODE RNG MODE select register 0x00C 0x1 MODE RNG run mode select register [0:0] PLL_LOCK which is for power on random number 0 RNG_RUN 1 RN RNG random number value register 0x010 read-only 0xffffffff RN random number of RNG shift register [31:0] POLY RNG polynomial register 0x014 0xE0000202 0xffffffff POLY 32bit polynomial of random number generator [31:0] SSP0 SSP 0x4000a000 0 0x28 registers SSP0 SSP 0 Interrupt 0 CR0 Control register 0 0x00 0xffff SCR Serial clock rate [15:8] SPH SSPCLKOUT phase [7:7] SPO SSPCLKOUT polarity [6:6] FRF Frame Format [5:4] DSS Data size select [3:0] CR1 Control register 1 0x04 0xf SOD Slave-mode output disable [3:3] MS Master or Slave mode select [2:2] SSE Synchronous serial port enable [1:1] LBM Loop back mode [0:0] DR Data register 0x08 0xffff DATA Transmit/Receive FIFO [15:0] SR Status register 0x0C 0x1f BSY SSP busy flag [4:4] RFF Receive FIFO full [3:3] RNE Receive FIFO not empty [2:2] TNF Transmit FIFO not full [1:1] TFE Transmit FIFO empty [0:0] CPSR Clock prescale register 0x10 0xff CPSDVSR Clock prescale divisor [7:0] IMSC Interrupt mask set or clear register 0x14 0xf TXIM Transmit FIFO interrupt mask [3:3] RXIM Receive FIFO interrupt mask [2:2] RTIM Receive timeout interrupt mask [1:1] RORIM Receive overrun interrupt mask [0:0] RIS Raw interrupt status register 0x18 0xf TXRIS Transmit FIFO interrupt status [3:3] RXRIS Receive FIFO interrupt status [2:2] RTRIS Receive timeout interrupt status [1:1] RORRIS Receive overrun interrupt status [0:0] MIS Masked interrupt status register 0x1C 0xf TXMIS Transmit FIFO masked interrupt status [3:3] RXMIS Receive FIFO masked interrupt status [2:2] RTMIS Receive timeout masked interrupt status [1:1] RORMIS Receive overrun masked interrupt status [0:0] ICR Interrupt clear register 0x20 0x3 RTIC Receive timeout interrupt clear [1:1] RORIC Receive overrun interrupt clear [0:0] DMACR DMA control register 0x24 0x3 TXDMAE Receive DMA Enable [0:0] RXDMAE Transmit DMA Enable [1:1] SSP1 0x4000b000 SSP1 SSP 1 Interrupt 1 UART0 UART 0x4000c000 0 0x4c registers UART0 UART 0 Interrupt 2 DR Data 0x00 0xfff OE Overrun Error [11:11] FIFOFull 1 BE Break Error [10:10] Error indicates that the received data input was held LOW of longer than a full word transmission time(defined as start, data, parity and stop bits) 1 PE Parity Error [9:9] Error indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the line control register, UARTLCR_H select 1 FE Framing Error [8:8] Error indicates that the received character didn’t have a valid stop bit 1 DATA DATA[7:0] bits (Receive (READ)/Transmit (WRITE) data) [7:0] RSR Receive Status 0x04 read-only 0xf OE Overrun Error [3:3] FIFOFull 1 BE Break Error [2:2] Error indicates that the received data input was held LOW of longer than a full word transmission time(defined as start, data, parity and stop bits) 1 PE Parity Error [1:1] Error indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the line control register, UARTLCR_H select 1 FE Framing Error [0:0] Error indicates that the received character didn’t have a valid stop bit 1 ECR Error Clear 0x04 write-only 0xf OE Overrun Error [3:3] Clear 1 BE Break Error [2:2] Clear 1 PE Parity Error [1:1] Clear 1 FE Framing Error [0:0] Clear 1 FR Flags 0x18 read-only 0bx11000xxx 0x1ff RI Ring indicator [8:8] High 0 Low 1 TXFE Transmit FIFO empty [7:7] TxHoldEmpty 0 TxFIFOEmpty 1 RXFF Receive FIFO full [6:6] RxHoldFull 0 RxFIFOFull 1 TXFF Transmit FIFO fULl [5:5] TxHoldFull 0 TxFIFOFull 1 RXFE Receive FIFO empty [4:4] RxHoldEmpty 0 RxFIFOEmpty 1 BUSY UART busy [3:3] Busy 1 DCD Data carrier detect [2:2] DataCarrierDetect 1 DSR Data set ready [1:1] DataSetReady 1 CTS Clear to send [0:0] ClearToSend 1 ILPR IrDA Low-power Counter 0x20 0xff ILPDVSR low-power divisor value [7:0] IBRD Integer Baud Rate 0x24 0x0 FBRD Fractional Baud Rate 0x28 0x0 LCR_H Line Control 0x2C 0xf7 SPS Stick parity select [7:7] Disable 0 Enable 1 WLEN Word length [6:5] 5Bits 0b00 6Bits 0b01 7Bits 0b10 8Bits 0b11 FEN Enable FIFOs [4:4] Disable 0 Enable 1 EPS Even parity select [2:2] Odd 0 Even 1 PEN Parity enable [1:1] Disable 0 Enable 1 BRK Send break [0:0] Disable 0 Enable 1 CR Control 0x30 0x0300 0xff07 CTSEn CTS hardware flow control enable [15:15] Disable 0 Enable 1 RTSEn RTS hardware flow control enable [14:14] Disable 0 Enable 1 Out2 Complement of Out2 modem status output [13:13] High 0 Low 1 Out1 Complement of Out1 modem status output [12:12] High 0 Low 1 RTS Request to send [11:11] High 0 Low 1 DTR Data transmit ready [10:10] High 0 Low 1 RXE Receive enable [9:9] Disable 0 Enable 1 TXE Transmit enable [8:8] Disable 0 Enable 1 SIRLP IrDA SIR low power mode [2:2] Disable low level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. 0 Enable low level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. 1 SIREN SIR enable [1:1] Disable 0 Enable 1 UARTEN UART enable [0:0] Disable 0 Enable 1 IFLS Interrupt FIFO Level Select 0x34 0x12 0x3f RXIFLSEL Receive interrupt FIFO level select [5:3] Full1_8 0b000 Full1_4 0b001 Full1_2 0b010 Full3_4 0b011 Full7_8 0b100 TXIFLSEL Transmit interrupt FIFO level select [2:0] Full1_8 0b000 Full1_4 0b001 Full1_2 0b010 Full3_4 0b011 Full7_8 0b100 IMSC Interrupt Mask Set / Clear 0x38 0x7ff OEIM Overrun error interrupt mask [10:10] Disable 0 Enable 1 BEIM Break error interrupt mask [9:9] Disable 0 Enable 1 PEIM Parity error interrupt mask [8:8] Disable 0 Enable 1 FEIM Framing error interrupt mask [7:7] Disable 0 Enable 1 RTIM Receive interrupt mask [6:6] Disable 0 Enable 1 TXIM Transmit interrupt mask [5:5] Disable 0 Enable 1 RXIM Receive interrupt mask [4:4] Disable 0 Enable 1 DSRMIM nUARTDSR modem interrupt mask [3:3] Disable 0 Enable 1 DCDMIM nUARTDCD modem interrupt mask [2:2] Disable 0 Enable 1 CTSMIM nUARTCTS modem interrupt mask [1:1] Disable 0 Enable 1 RIMIM nUARTRI modem interrupt mask [0:0] Disable 0 Enable 1 RIS Raw Interrupt Status 0x3C read-only 0x7ff OEIM Overrun error interrupt status [10:10] BEIM Break error interrupt status [9:9] Set 1 PEIM Parity error interrupt status [8:8] Set 1 FEIM Framing error interrupt status [7:7] Set 1 RTIM Receive interrupt status [6:6] Set 1 TXIM Transmit interrupt status [5:5] Set 1 RXIM Receive interrupt status [4:4] Set 1 DSRMIM nUARTDSR modem interrupt status [3:3] Set 1 DCDMIM nUARTDCD modem interrupt status [2:2] Set 1 CTSMIM nUARTCTS modem interrupt status [1:1] Set 1 RIMIM nUARTRI modem interrupt status [0:0] Set 1 MIS Masked Interrupt Status 0x40 read-only 0x7ff OEIM Overrun error masked interrupt status [10:10] Set 1 BEIM Break error masked interrupt status [9:9] Set 1 PEIM Parity error masked interrupt status [8:8] Set 1 FEIM Framing error masked interrupt status [7:7] Set 1 RTIM Receive masked interrupt status [6:6] Set 1 TXIM Transmit masked interrupt status [5:5] Set 1 RXIM Receive masked interrupt status [4:4] Set 1 DSRMIM nUARTDSR modem masked interrupt status [3:3] Set 1 DCDMIM nUARTDCD modem masked interrupt status [2:2] Set 1 CTSMIM nUARTCTS modem masked interrupt status [1:1] Set 1 RIMIM nUARTRI modem masked interrupt status [0:0] Set 1 ICR Interrupt Clear 0x44 write-only 0x7ff OEIM Overrun error interrupt clear [10:10] Clear 1 BEIM Break error interrupt clear [9:9] Clear 1 PEIM Parity error interrupt clear [8:8] Clear 1 FEIM Framing error interrupt clear [7:7] Clear 1 RTIM Receive interrupt clear [6:6] Clear 1 TXIM Transmit interrupt clear [5:5] Clear 1 RXIM Receive interrupt clear [4:4] Clear 1 DSRMIM nUARTDSR modem interrupt clear [3:3] Clear 1 DCDMIM nUARTDCD modem interrupt clear [2:2] Clear 1 CTSMIM nUARTCTS modem interrupt clear [1:1] Clear 1 RIMIM nUARTRI modem interrupt clear [0:0] Clear 1 DMACR DMA Control 0x48 0x7 DMAONERR DMA on error [2:2] Disable 0 Enable 1 TXDMAE Transmit DMA enable [1:1] Disable 0 Enable 1 RXDMAE Receive DMA enable [0:0] Disable 0 Enable 1 UART1 0x4000d000 UART1 UART 1 Interrupt 3 RTC RTC 0x4000e000 0 0x50 registers RTC RTC Interrupt 22 RTCCON control register 0x00 0x23 INTEN RTC Interrupt Enable [5:5] Disable 0 Enable 1 DIVRST RTC Divider Reset [1:1] Reset 1 CLKEN Clock Enable [0:0] Disable 0 Enable 1 RTCINTE Interrupt Mask register 0x04 0x7f AINT RTC Alarm Interrupt Enable [6:6] Disable 0 Enable 1 IMMON RTC Month Interrupt Enable [5:5] Disable 0 Enable 1 IMDAY RTC Day Interrupt Enable [4:4] Disable 0 Enable 1 IMDATE RTC Date Interrupt Enable [3:3] Disable 0 Enable 1 IMHOUR RTC Hour Interrupt Enable [2:2] Disable 0 Enable 1 IMMIN RTC Minute Interrupt Enable [1:1] Disable 0 Enable 1 IMSEC RTC Second Interrupt Enable [0:0] Disable 0 Enable 1 RTCINTP Interrupt Pending register 0x08 0x3 RTCALF RTC Alarm interrupt pending flag [1:1] Clear 1 RTCCIF RTC Counter Interrupt pending flag [0:0] Clear 1 RTCAMR Alarm Mask register 0x0C 0x7f AMRYEAR RTC Alarm Mask for Year [6:6] Enable 1 AMRMON RTC Alarm Mask for Month [5:5] Enable 1 AMRDATE RTC Alarm Mask for Date [4:4] Enable 1 AMRDAY RTC Alarm Mask for Day [3:3] Enable 1 AMRHOUR RTC Alarm Mask for Hour [2:2] Enable 1 AMRMIN RTC Alarm Mask for Minute [1:1] Enable 1 AMRSEC RTC Alarm Mask for Second [0:0] Enable 1 BCDSEC BCD Second register 0x10 0x7f BCDSEC BCDSEC[6:0] bits (RTC Seconds value (0 to 59)) [6:0] BCDMIN BCD Minute register 0x14 0x7f BCDMIN BCDMIN[6:0] bits (RTC Minute value (0 to 59)) [6:0] BCDHOUR BCD Hour register 0x18 0x3f BCDHOUR BCDHOUR[5:0] bits (RTC Hour value (0 to 23)) [5:0] BCDDAY BCD Day register 0x1C 0xf BCDDAY BCDDAY[3:0] bits (RTC Day of Week value (1 to 7)) [3:0] BCDDATE BCD Date register 0x20 0x3f BCDDATE BCDDATE[5:0] bits (RTC Day of Month value (1 to 28, 29, 30, or 31)) [5:0] BCDMON BCD Month register 0x24 0x1f BCDMON BCDMON[4:0] bits (RTC Month value (1 to 12)) [4:0] BCDYEAR BCD Year register 0x28 0xffff BCDYEAR BCDYEAR[15:0] bits (RTC Year value (0 to 4095)) [15:0] PRESEC Predetermining Second register 0x2C 0x7f PRESEC PRESEC[6:0] bits (RTC PREDETERMINING Seconds value (0 to 59)) [6:0] PREMIN Predetermining Minute register 0x30 0x7f PREMIN PREMIN[6:0] bits (RTC Predetermining Minute value (0 to 59)) [6:0] PREHOUR Predetermining Hour register 0x34 0x3f PREHOUR PREHOUR[5:0] bits (RTC Predetermining Hour value (0 to 23)) [5:0] PREDAY Predetermining Day register 0x38 0xf PREDAY PREDAY[3:0] bits (RTC Predetermining Day of Week value (1 to 7)) [3:0] PREDATE Predetermining Date register 0x3C 0x3f PREDATE PREDATE[3:0] bits (RTC Predetermining Day of Month value (1 to 28, 29, 30, or 31)) [5:0] PREMON Predetermining Month register 0x40 0x1f PREMON PREMON[3:0] bits (RTC Predetermining Month value (1 to 12)) [4:0] PREYEAR Predetermining Year register 0x44 0xffff PREYEAR PREYEAR[15:0] bits (RTC Predetermining Year value (0 to 4095)) [15:0] RTCTIME0 Consolidated Time0 register 0x48 read-only 0xf3f7f7f CBCDDAY CBCDDAY[27:24] bits ( RTC Consolidated Day of Week value (1 to 7)) [27:24] CBCDHOUR CBCDHOUR[21:16] bits (RTC Consolidated Hour value (0 to 23)) [21:16] CBCDMIN CBCDMIN[14:8] bits (RTC Consolidated Minute value (0 to 59)) [14:8] CBCDSEC CBCDSEC[6:0] bits (RTC Consolidated Second value (0 to 59)) [6:0] RTCTIME1 Consolidated Time1 register 0x4C read-only 0xffff1f3f CBCDYEAR CBCDYEAR[31:16] bits (RTC Consolidated Year value (0 to 4095)) [31:16] CBCDMON CBCDMON[12:8] bits (RTC Consolidated Month value (1 to 12)) [12:8] CBCDDATE CBCDDATE[5:0] bits (RTC Consolidated Day of Month value (1 to 28, 29, 30, or 31)) [5:0] SYSCFG SYSCFG 0x4001f000 0 0x14 registers REMAP Remap Control Register (R/W) 0x00 0x0 PMUCTRL PMU Control Register (R/W) 0x04 0x0 RESETOP Reset Option Register (R/W) 0x08 0x0 EMICTRL EMI Control Register (R/W) 0x0C 0x0 RSTINFO Reset Information Register (R/W) 0x10 0x3 SYS Reset Request Enable [0:0] RST Interrupt Enable [1:1] ADC ADC 0x41000000 0 0x20 registers ADC ADC Interrupt 23 CTR ADC control register 0x00 0x00000003 0x3 PWD power down flag [1:1] Active 0 PowerDown 1 SMPSEL Sampling mode [0:0] Abnormal 0 Normal 1 CHSEL ADC channel select register 0x04 0xf CHSEL ADC Channel Select bits [3:0] Channel0 0b0000 Channel1 0b0001 Channel2 0b0010 Channel3 0b0011 Channel4 0b0100 Channel5 0b0101 Channel6 0b0110 Channel7 0b0111 NoChannel 0b1000 LDOOutput1V5 0b1111 START ADC start register 0x08 write-only 0x1 ADC_SRT Start ADC for conversion [0:0] Ready 0 Start This bit clear automatically after conversion 1 DATA ADC conversion data register 0x0C read-only 0xfff ADC_DATA ADC conversion result data [11:0] INT ADC interrupt register 0x10 0x3 MASK Interrupt mask signal [1:1] Disable 0 Enable 1 INT ADC conversion is done of Interrupt bit [0:0] Done 0 NotDone 1 INTCLR ADC interrupt clear register 0x1C write-only 0x1 INTCLR ADC conversion is done of Interrupt bit [0:0] Clear 1 CRG CRG 0x41001000 0 0x174 registers OSC_PDR Oscillator power down register 0x000 0x1 OSCPD Internal 8MHz RC oscillator power down flag [0:0] Normal 0 PowerDown 1 PLL_PDR PLL power down register 0x010 0x00000001 0x1 PLLPD PLL power down flag [0:0] PowerDown 0 Normal 1 PLL_FCR PLL frequency calculating register 0x014 0x00050200 0x3f3f03 M Loop divider control bits [21:16] N Pre divider control bits [13:8] OD Output divider control bits [1:0] PLL_OER PLL output enable register 0x018 0x00000001 0x1 PLLOEN PLL output flag [0:0] Disable VCO is working but FOUT is low only 0 Enable 1 PLL_BPR PLL bypass register 0x01C 0x1 PLLBP PLL bypass flag [0:0] PLL_IFSR PLL input frequency select register 0x020 0x1 PLLIS PLL input clock source select flag [0:0] Internal Internal 8MHz RC oscillator clock (RCLK) 0 External External oscillator clock (OCLK, 8MHz-24MHz) 1 FCLK_SSR FCLK source select register 0x030 0x00000001 0x3 FCKSRC FCLK source select bits [1:0] PLL Output clock of PLL (MCLK) true Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 FCLK_PVSR FCLK prescale value select register 0x034 0x3 FCKPRE FCLK prescale value select bits [1:0] Bypass 1/1 0b00 Half 1/2 0b01 By4 1/4 0b10 By8 1/8 0b11 SSPCLK_SSR SSPCLK source select register 0x040 0x00000001 0x3 SSPCSS SSPCLK source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 SSPCLK_PVSR SSPCLK prescale value select register 0x044 0x3 SSPCP SSPCLK prescale value select bits [1:0] Bypass 1/1 0b00 Half 1/2 0b01 By4 1/4 0b10 By8 1/8 0b11 ADCCLK_SSR ADCCLK source select register 0x060 0x00000001 0x3 ADCSS ADCCLK source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 ADCCLK_PVSR ADCCLK prescale value select register 0x064 0x3 ADCCP ADCCLK prescale value select bits [1:0] Bypass 1/1 0b00 Half 1/2 0b01 By4 1/4 0b10 By8 1/8 0b11 TIMER0CLK_SSR TIMER0CLK source select register 0x070 0x00000001 0x3 TCSS TIMERnCLK source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 TIMER0CLK_PVSR TIMER0CLK prescale value select register 0x074 0x7 TCPS TIMERnCLK prescale value select bits [2:0] Bypass 1/1 0b000 Half 1/2 0b001 By4 1/4 0b010 By8 1/8 0b011 By16 1/16 0b100 By32 1/32 0b101 By64 1/64 0b110 By128 1/128 0b111 TIMER1CLK_SSR TIMER1CLK source select register 0x080 0x00000001 0x3 TCSS TIMERnCLK source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 TIMER1CLK_PVSR TIMER1CLK prescale value select register 0x084 0x7 TCPS TIMERnCLK prescale value select bits [2:0] Bypass 1/1 0b000 Half 1/2 0b001 By4 1/4 0b010 By8 1/8 0b011 By16 1/16 0b100 By32 1/32 0b101 By64 1/64 0b110 By128 1/128 0b111 PWM0CLK_SSR PWM0CLK source select register 0x0B0 0x00000001 0x3 PCSS PWMnCLK source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 PWM0CLK_PVSR PWM0CLK prescale value select register 0x0B4 0x7 PCPS PWMnCLK prescale value select bits [2:0] Bypass 1/1 0b000 Half 1/2 0b001 By4 1/4 0b010 By8 1/8 0b011 By16 1/16 0b100 By32 1/32 0b101 By64 1/64 0b110 By128 1/128 0b111 PWM1CLK_SSR PWM1CLK source select register 0x0C0 0x00000001 0x3 PCSS PWMnCLK source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 PWM1CLK_PVSR PWM1CLK prescale value select register 0x0C4 0x7 PCPS PWMnCLK prescale value select bits [2:0] Bypass 1/1 0b000 Half 1/2 0b001 By4 1/4 0b010 By8 1/8 0b011 By16 1/16 0b100 By32 1/32 0b101 By64 1/64 0b110 By128 1/128 0b111 PWM2CLK_SSR PWM2CLK source select register 0x0D0 0x00000001 0x3 PCSS PWMnCLK source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 PWM2CLK_PVSR PWM2CLK prescale value select register 0x0D4 0x7 PCPS PWMnCLK prescale value select bits [2:0] Bypass 1/1 0b000 Half 1/2 0b001 By4 1/4 0b010 By8 1/8 0b011 By16 1/16 0b100 By32 1/32 0b101 By64 1/64 0b110 By128 1/128 0b111 PWM3CLK_SSR PWM3CLK source select register 0x0E0 0x00000001 0x3 PCSS PWMnCLK source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 PWM3CLK_PVSR PWM3CLK prescale value select register 0x0E4 0x7 PCPS PWMnCLK prescale value select bits [2:0] Bypass 1/1 0b000 Half 1/2 0b001 By4 1/4 0b010 By8 1/8 0b011 By16 1/16 0b100 By32 1/32 0b101 By64 1/64 0b110 By128 1/128 0b111 PWM4CLK_SSR PWM4CLK source select register 0x0F0 0x00000001 0x3 PCSS PWMnCLK source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 PWM4CLK_PVSR PWM4CLK prescale value select register 0x0F4 0x7 PCPS PWMnCLK prescale value select bits [2:0] Bypass 1/1 0b000 Half 1/2 0b001 By4 1/4 0b010 By8 1/8 0b011 By16 1/16 0b100 By32 1/32 0b101 By64 1/64 0b110 By128 1/128 0b111 PWM5CLK_SSR PWM5CLK source select register 0x100 0x00000001 0x3 PCSS PWMnCLK source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 PWM5CLK_PVSR PWM5CLK prescale value select register 0x104 0x7 PCPS PWMnCLK prescale value select bits [2:0] Bypass 1/1 0b000 Half 1/2 0b001 By4 1/4 0b010 By8 1/8 0b011 By16 1/16 0b100 By32 1/32 0b101 By64 1/64 0b110 By128 1/128 0b111 PWM6CLK_SSR PWM6CLK source select register 0x110 0x00000001 0x3 PCSS PWMnCLK source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 PWM6CLK_PVSR PWM6CLK prescale value select register 0x114 0x7 PCPS PWMnCLK prescale value select bits [2:0] Bypass 1/1 0b000 Half 1/2 0b001 By4 1/4 0b010 By8 1/8 0b011 By16 1/16 0b100 By32 1/32 0b101 By64 1/64 0b110 By128 1/128 0b111 PWM7CLK_SSR PWM7CLK source select register 0x120 0x00000001 0x3 PCSS PWMnCLK source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 PWM7CLK_PVSR PWM7CLK prescale value select register 0x124 0x7 PCPS PWMnCLK prescale value select bits [2:0] Bypass 1/1 0b000 Half 1/2 0b001 By4 1/4 0b010 By8 1/8 0b011 By16 1/16 0b100 By32 1/32 0b101 By64 1/64 0b110 By128 1/128 0b111 RTC_HS_SSR RTCCLK source select register 0x130 0x00000001 0x3 RTCHS RTC High Speed source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 RTC_HS_PVSR RTCCLK prescale value select register 0x134 0x7 RTCPRE RTC High Speed prescale value select bits [2:0] Bypass 1/1 0b000 Half 1/2 0b001 By4 1/4 0b010 By8 1/8 0b011 By16 1/16 0b100 By32 1/32 0b101 By64 1/64 0b110 By128 1/128 0b111 RTC_SSR RTCCLK 32K select register 0x13C 0x1 RTCSEL RTC source select bits [0:0] RTCCLK_hs 0 32K_OSC_CLK Low speed external oscillator clock 1 WDOGCLK_HS_SSR WDOGCLK High Speed source select register 0x140 0x00000001 0x3 WDHS WDOGCLK High Speed source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 WDOGCLK_HS_PVSR WDOGCLK High Speed prescale value select register 0x144 0x7 WDPRE WDOGCLK High Speed prescale value select bits [2:0] Bypass 1/1 0b000 Half 1/2 0b001 By4 1/4 0b010 By8 1/8 0b011 By16 1/16 0b100 By32 1/32 0b101 By64 1/64 0b110 By128 1/128 0b111 UARTCLK_SSR UARTCLK source select register 0x150 0x00000001 0x3 UCSS UARTCLK source select bits [1:0] Disable 0b00 PLL Output clock of PLL (MCLK) 0b01 Internal Internal 8MHz RC oscillator clock (RCLK) 0b10 External External oscillator clock (OCLK, 8MHz-24MHz) 0b11 UARTCLK_PVSR UARTCLK prescale value select register 0x154 0x3 UCP UARTCLK prescale value select bits [1:0] Bypass 1/1 0b00 Half 1/2 0b01 By4 1/4 0b10 By8 1/8 0b11 MIICLK_ECR MII clock enable control register 0x160 0x00000003 0x3 EN_MIITEN MII TX Clock source enable flag [1:1] EN_MIIREN MII RX Clock source enable register flag [0:0] MONCLK_SSR Select clock source for monitoring (monitoring pin : PA_02) 0x170 0x1f CLKMON_SEL Monitoring Clock source select bits [4:0] PLL MCLK 0b00000 FCLK 0b00001 Internal Internal 8MHz RC oscillator clock (RCLK) 0b00010 External External oscillator clock (OCLK, 8MHz-24MHz) 0b00011 ADCCLK 0b00100 SSPCLK 0b00101 TIMCLK0 0b00110 TIMCLK1 0b00111 PWMCLK0 0b01000 PWMCLK1 0b01001 PWMCLK2 0b01010 PWMCLK3 0b01011 PWMCLK4 0b01100 PWMCLK5 0b01101 PWMCLK6 0b01110 PWMCLK7 0b01111 UARTCLK 0b10000 MII_RCK 0b10001 MII_TCK 0b10010 RTCCLK 0b10011 DMA DMA 0x41004000 0 0x50 registers DMA DMA combined Interrupt 11 STATUS DMA status register 0x00 read-only 0x00050000 0xf1 STATE Current state of the control state machine [7:4] Idle 0b0000 ReadingChanCtrlData 0b0001 ReadingSrcDataEndPtr 0b0010 ReadingDstDataEndPtr 0b0011 ReadingSrcData 0b0100 WritingDstData 0b0101 WritingChanCtrlData 0b0110 Stalled 0b1000 Done 0b1001 PeriphScatGathTrans 0b1010 ENABLE Enable status of the controller [0:0] Disable 0 Enable 1 CFG DMA configuration register 0x04 write-only 0xe1 PROT_CTRL Set the AHB-Lite protection [7:5] ENABLE Enable for the controller [0:0] Disable 0 Enable 1 CTRL_BASE_PTR Channel Control Data Base Pointer register 0x08 0xffffff00 CTRL_BASE_PTR Pointer to the base address of the primary data structure [31:8] ALT_CTRL_BASE_PTR Channel Alternate Control Data Base Pointer register 0x0C read-only 0xffffffff ALT_CTRL_BASE_PTR Base address of the alternate data structure [31:0] WAITONREQ_STATUS Channel Wait On Request Status register 0x10 read-only 0x3f DMA_WAITONREQ Channel wait on request status [5:0] CHNL_SW_REQUEST Channel Software Request register 0x14 write-only 0x3f CHNL_SW_REQUEST Set the appropriate bit to generate a software DMA request [5:0] CHNL_USEBURST_SET Channel UseBurst Set register 0x18 0x3f CHNL_USEBURST_SET CHNL_USEBURST_SET[5:0] bits (Returns the useburst status, or disable dma_sreq[Channel-1] form generating DMA requests) [5:0] CHNL_USEBURST_CLR Channel UseBurst Clear register 0x1C write-only 0x3f CHNL_USEBURST_CLR CHNL_USEBURST_CLR[5:0] bits (Set the appropriate bit to enable dma_sreq[Channel-1] to generate requests) [5:0] CHNL_REQ_MASK_SET Channel Request Mask Set register 0x20 0x3f CHNL_REQ_MASK_SET CHNL_REQ_MASK_SET[5:0] bits (Returns the request mask status of dma_req[Channel-1] and dma_sreq[Channel-1], or disables the corresponding channel from generating DMA requests) [5:0] CHNL_REQ_MASK_CLR Channel Request Mask Clear register 0x24 write-only 0x3f CHNL_REQ_MASK_CLR CHNL_REQ_MASK_CLR[5:0] bits (Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req[Channel-1] and dma_sreq[Channel-1]) [5:0] CHNL_ENABLE_SET Channel Enable Set register 0x28 0x3f CHNL_ENABLE_SET CHNL_ENABLE_SET[5:0] bits (Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req[Channel-1] and dma_sreq[Channel-1]) [5:0] CHNL_ENABLE_CLR Channel Enable Clear register 0x2C write-only 0x3f CHNL_ENABLE_CLR Set the appropriate bit to disable the corresponding DMA channel [5:0] CHNL_PRI_ALT_SET Channel Primary-Alterante Set register 0x30 0x3f CHNL_PRI_ALT_SET CHNL_PRI_ALT_SET[5:0] bits (Returns the channel control data structure status, or selects the alternate data structure for the corresponding DMA channels) [5:0] CHNL_PRI_ALT_CLR Channel Primary-Alterante Clear register 0x34 write-only 0x3f CHNL_PRI_ALT_CLR Set the appropriate bit to select the primary data structure for the corresponding DMA channel [5:0] CHNL_PRIORITY_SET Channel Priority Set register 0x38 0x3f CHNL_PRIORITY_SET CHNL_PRIORITY_SET[5:0] bits (Returns the channel priority mask status, or set the channel priority to high) [5:0] CHNL_PRIORITY_CLR Channel Priority Clear register 0x3C write-only 0x3f CHNL_PRIORITY_CLR Set the appropriate bit to select the default priority level for the specified DMA channel [5:0] ERR_CLR Bus Error Clear register 0x4C 0x1 ERR_CLR Returns the status of DMA_ERR, or set the signal LOW [0:0] Low 0 High 1 GPIOA GPIO 0x42000000 0 0xc00 registers PORT0 Port 0 combined Interrupt 7 DATA DATA register 0x000 read-only 0xffff DAT15 Port input data bit [15:15] DAT14 Port input data bit [14:14] DAT13 Port input data bit [13:13] DAT12 Port input data bit [12:12] DAT11 Port input data bit [11:11] DAT10 Port input data bit [10:10] DAT9 Port input data bit [9:9] DAT8 Port input data bit [8:8] DAT7 Port input data bit [7:7] DAT6 Port input data bit [6:6] DAT5 Port input data bit [5:5] DAT4 Port input data bit [4:4] DAT3 Port input data bit [3:3] DAT2 Port input data bit [2:2] DAT1 Port input data bit [1:1] DAT0 Port input data bit [0:0] DATAOUT Data Output Latch register 0x004 0xffff DAO15 Port out data bit [15:15] DAO14 Port out data bit [14:14] DAO13 Port out data bit [13:13] DAO12 Port out data bit [12:12] DAO11 Port out data bit [11:11] DAO10 Port out data bit [10:10] DAO9 Port out data bit [9:9] DAO8 Port out data bit [8:8] DAO7 Port out data bit [7:7] DAO6 Port out data bit [6:6] DAO5 Port out data bit [5:5] DAO4 Port out data bit [4:4] DAO3 Port out data bit [3:3] DAO2 Port out data bit [2:2] DAO1 Port out data bit [1:1] DAO0 Port out data bit [0:0] OUTENSET Output Enable Set register 0x010 0xffff ES15 sets the corresponding output enable bit, indicates the signal direction [15:15] ES14 sets the corresponding output enable bit, indicates the signal direction [14:14] ES13 sets the corresponding output enable bit, indicates the signal direction [13:13] ES12 sets the corresponding output enable bit, indicates the signal direction [12:12] ES11 sets the corresponding output enable bit, indicates the signal direction [11:11] ES10 sets the corresponding output enable bit, indicates the signal direction [10:10] ES9 sets the corresponding output enable bit, indicates the signal direction [9:9] ES8 sets the corresponding output enable bit, indicates the signal direction [8:8] ES7 sets the corresponding output enable bit, indicates the signal direction [7:7] ES6 sets the corresponding output enable bit, indicates the signal direction [6:6] ES5 sets the corresponding output enable bit, indicates the signal direction [5:5] ES4 sets the corresponding output enable bit, indicates the signal direction [4:4] ES3 sets the corresponding output enable bit, indicates the signal direction [3:3] ES2 sets the corresponding output enable bit, indicates the signal direction [2:2] ES1 sets the corresponding output enable bit, indicates the signal direction [1:1] ES0 sets the corresponding output enable bit, indicates the signal direction [0:0] OUTENCLR Output Enable Clear register 0x014 0xffff EC15 clears the output enable bit, indicates the signal direction [15:15] EC14 clears the output enable bit, indicates the signal direction [14:14] EC13 clears the output enable bit, indicates the signal direction [13:13] EC12 clears the output enable bit, indicates the signal direction [12:12] EC11 clears the output enable bit, indicates the signal direction [11:11] EC10 clears the output enable bit, indicates the signal direction [10:10] EC9 clears the output enable bit, indicates the signal direction [9:9] EC8 clears the output enable bit, indicates the signal direction [8:8] EC7 clears the output enable bit, indicates the signal direction [7:7] EC6 clears the output enable bit, indicates the signal direction [6:6] EC5 clears the output enable bit, indicates the signal direction [5:5] EC4 clears the output enable bit, indicates the signal direction [4:4] EC3 clears the output enable bit, indicates the signal direction [3:3] EC2 clears the output enable bit, indicates the signal direction [2:2] EC1 clears the output enable bit, indicates the signal direction [1:1] EC0 clears the output enable bit, indicates the signal direction [0:0] INTENSET Interrupt Enable Set register 0x020 0xffff IES15 sets the interrupt enable bit, indicates the interrupt [15:15] IES14 sets the interrupt enable bit, indicates the interrupt [14:14] IES13 sets the interrupt enable bit, indicates the interrupt [13:13] IES12 sets the interrupt enable bit, indicates the interrupt [12:12] IES11 sets the interrupt enable bit, indicates the interrupt [11:11] IES10 sets the interrupt enable bit, indicates the interrupt [10:10] IES9 sets the interrupt enable bit, indicates the interrupt [9:9] IES8 sets the interrupt enable bit, indicates the interrupt [8:8] IES7 sets the interrupt enable bit, indicates the interrupt [7:7] IES6 sets the interrupt enable bit, indicates the interrupt [6:6] IES5 sets the interrupt enable bit, indicates the interrupt [5:5] IES4 sets the interrupt enable bit, indicates the interrupt [4:4] IES3 sets the interrupt enable bit, indicates the interrupt [3:3] IES2 sets the interrupt enable bit, indicates the interrupt [2:2] IES1 sets the interrupt enable bit, indicates the interrupt [1:1] IES0 sets the interrupt enable bit, indicates the interrupt [0:0] INTENCLR Interrupt Enable Clear register 0x024 0xffff IEC15 clears the interrupt enable bit, indicates the interrupt [15:15] IEC14 clears the interrupt enable bit, indicates the interrupt [14:14] IEC13 clears the interrupt enable bit, indicates the interrupt [13:13] IEC12 clears the interrupt enable bit, indicates the interrupt [12:12] IEC11 clears the interrupt enable bit, indicates the interrupt [11:11] IEC10 clears the interrupt enable bit, indicates the interrupt [10:10] IEC9 clears the interrupt enable bit, indicates the interrupt [9:9] IEC8 clears the interrupt enable bit, indicates the interrupt [8:8] IEC7 clears the interrupt enable bit, indicates the interrupt [7:7] IEC6 clears the interrupt enable bit, indicates the interrupt [6:6] IEC5 clears the interrupt enable bit, indicates the interrupt [5:5] IEC4 clears the interrupt enable bit, indicates the interrupt [4:4] IEC3 clears the interrupt enable bit, indicates the interrupt [3:3] IEC2 clears the interrupt enable bit, indicates the interrupt [2:2] IEC1 clears the interrupt enable bit, indicates the interrupt [1:1] IEC0 clears the interrupt enable bit, indicates the interrupt [0:0] INTTYPESET Interrupt Type Set register 0x028 0xffff ITS15 sets the interrupt type bit, indicates for edge or level [15:15] ITS14 sets the interrupt type bit, indicates for edge or level [14:14] ITS13 sets the interrupt type bit, indicates for edge or level [13:13] ITS12 sets the interrupt type bit, indicates for edge or level [12:12] ITS11 sets the interrupt type bit, indicates for edge or level [11:11] ITS10 sets the interrupt type bit, indicates for edge or level [10:10] ITS9 sets the interrupt type bit, indicates for edge or level [9:9] ITS8 sets the interrupt type bit, indicates for edge or level [8:8] ITS7 sets the interrupt type bit, indicates for edge or level [7:7] ITS6 sets the interrupt type bit, indicates for edge or level [6:6] ITS5 sets the interrupt type bit, indicates for edge or level [5:5] ITS4 sets the interrupt type bit, indicates for edge or level [4:4] ITS3 sets the interrupt type bit, indicates for edge or level [3:3] ITS2 sets the interrupt type bit, indicates for edge or level [2:2] ITS1 sets the interrupt type bit, indicates for edge or level [1:1] ITS0 sets the interrupt type bit, indicates for edge or level [0:0] INTTYPECLR Interrupt Type Clear register 0x02C 0xffff ITC15 clears the interrupt type bit, indicates for edge or level [15:15] ITC14 clears the interrupt type bit, indicates for edge or level [14:14] ITC13 clears the interrupt type bit, indicates for edge or level [13:13] ITC12 clears the interrupt type bit, indicates for edge or level [12:12] ITC11 clears the interrupt type bit, indicates for edge or level [11:11] ITC10 clears the interrupt type bit, indicates for edge or level [10:10] ITC9 clears the interrupt type bit, indicates for edge or level [9:9] ITC8 clears the interrupt type bit, indicates for edge or level [8:8] ITC7 clears the interrupt type bit, indicates for edge or level [7:7] ITC6 clears the interrupt type bit, indicates for edge or level [6:6] ITC5 clears the interrupt type bit, indicates for edge or level [5:5] ITC4 clears the interrupt type bit, indicates for edge or level [4:4] ITC3 clears the interrupt type bit, indicates for edge or level [3:3] ITC2 clears the interrupt type bit, indicates for edge or level [2:2] ITC1 clears the interrupt type bit, indicates for edge or level [1:1] ITC0 clears the interrupt type bit, indicates for edge or level [0:0] INTPOLSET Interrupt Polarity Set register 0x030 0xffff IPS15 sets the interrupt polarity bit, indicates for edge or level [15:15] IPS14 sets the interrupt polarity bit, indicates for edge or level [14:14] IPS13 sets the interrupt polarity bit, indicates for edge or level [13:13] IPS12 sets the interrupt polarity bit, indicates for edge or level [12:12] IPS11 sets the interrupt polarity bit, indicates for edge or level [11:11] IPS10 sets the interrupt polarity bit, indicates for edge or level [10:10] IPS9 sets the interrupt polarity bit, indicates for edge or level [9:9] IPS8 sets the interrupt polarity bit, indicates for edge or level [8:8] IPS7 sets the interrupt polarity bit, indicates for edge or level [7:7] IPS6 sets the interrupt polarity bit, indicates for edge or level [6:6] IPS5 sets the interrupt polarity bit, indicates for edge or level [5:5] IPS4 sets the interrupt polarity bit, indicates for edge or level [4:4] IPS3 sets the interrupt polarity bit, indicates for edge or level [3:3] IPS2 sets the interrupt polarity bit, indicates for edge or level [2:2] IPS1 sets the interrupt polarity bit, indicates for edge or level [1:1] IPS0 sets the interrupt polarity bit, indicates for edge or level [0:0] INTPOLCLR Interrupt Polarity Clear register 0x034 0xffff IPC15 clears the interrupt polarity bit, indicates for edge or level [15:15] IPC14 clears the interrupt polarity bit, indicates for edge or level [14:14] IPC13 clears the interrupt polarity bit, indicates for edge or level [13:13] IPC12 clears the interrupt polarity bit, indicates for edge or level [12:12] IPC11 clears the interrupt polarity bit, indicates for edge or level [11:11] IPC10 clears the interrupt polarity bit, indicates for edge or level [10:10] IPC9 clears the interrupt polarity bit, indicates for edge or level [9:9] IPC8 clears the interrupt polarity bit, indicates for edge or level [8:8] IPC7 clears the interrupt polarity bit, indicates for edge or level [7:7] IPC6 clears the interrupt polarity bit, indicates for edge or level [6:6] IPC5 clears the interrupt polarity bit, indicates for edge or level [5:5] IPC4 clears the interrupt polarity bit, indicates for edge or level [4:4] IPC3 clears the interrupt polarity bit, indicates for edge or level [3:3] IPC2 clears the interrupt polarity bit, indicates for edge or level [2:2] IPC1 clears the interrupt polarity bit, indicates for edge or level [1:1] IPC0 clears the interrupt polarity bit, indicates for edge or level [0:0] INTSTATUS Interrupt Status register 0x038 read-only 0x0 INTCLEAR Interrupt Clear register 0x038 write-only 0x0 256 4 LB_MASKED[%s] Lower byte Masked Access register 0x400 0xff LBM Data for lower byte access [7:0] 256 4 UB_MASKED[%s] Upper byte Masked Access register 0x800 0xff00 HBM Data for higher byte access [15:8] GPIOB 0x43000000 PORT1 Port 1 combined Interrupt 8 GPIOC 0x44000000 PORT2 Port 2 combined Interrupt 9 GPIOD 0x45000000 PORT3 Port 3 combined Interrupt 10