$version Generated by VerilatedVcd $end
$date Mon Mar  7 16:03:36 2022
 $end
$timescale   1ps $end

 $scope module TOP $end
  $var wire  1 ' clk $end
  $var wire  8 & io_state [7:0] $end
  $var wire  1 ( reset $end
  $scope module MyTopLevel $end
   $var wire  1 ' clk $end
   $var wire  8 ) counter [7:0] $end
  $upscope $end
  $scope module MyTest $end
   $var wire  1 ' clk $end
  $upscope $end
 $upscope $end
$enddefinitions $end