---
name: CH32V20x Series
mcu_type: 9
device_type: 0x19
support_net: false
support_usb: true
support_serial: true
description: CH32V20x (RISC-V4B/V4C) Series
config_registers:
  # Ref: section "32.6 User option bytes" of RM manual
  - offset: 0x00
    name: RDPR_USER
    description: RDPR, nRDPR, USER, nUSER
    reset: 0x00FF5AA5
    type: u32
    fields: # TODO
      - bit_range: [7, 0]
        name: RDPR
        description: Read Protection. 0xA5 for unprotected, otherwise read-protected(ignoring WRP)
        explaination:
          0xa5: Unprotected
          _: Protected
      - bit_range: [16, 16]
        name: IWDG_SW
        description: Independent watchdog (IWDG) hardware enable
        explaination:
          1: IWDG enabled by the software, and disabled by hardware
          0: IWDG enabled by the software (decided along with the LSI clock)
      # [1:1] + 16
      - bit_range: [17, 17]
        name: STOP_RST
        description: System reset control under the stop mode
        explaination:
          1: Disable
          0: Enable
      # [2:2] + 16
      - bit_range: [18, 18]
        name: STANDBY_RST
        description: System reset control under the standby mode, STANDY_RST
        explaination:
          1: Disable, entering standby-mode without RST
          0: Enable
      # [7:6] + 16
      - bit_range: [23, 22]
        name: SRAM_CODE_MODE
        description: SRAM Code Mode
        explaination:
          0b00: CODE-192KB + RAM-128KB / CODE-128KB + RAM-64KB depending on the chip
          0b01: CODE-224KB + RAM-96KB / CODE-144KB + RAM-48KB depending on the chip
          0b10: CODE-256KB + RAM-64KB / CODE-160KB + RAM-32KB depending on the chip
          0b11: CODE-228KB + RAM-32KB / CODE-160KB + RAM-32KB depending on the chip
  - offset: 0x04
    name: DATA
    description: Customizable 2 byte data, DATA0, nDATA0, DATA1, nDATA1
    reset: 0xFF00FF00
    type: u32
    fields:
      - bit_range: [7, 0]
        name: DATA0
      - bit_range: [23, 16]
        name: DATA1
  - offset: 0x08
    name: WRP
    # Each bit represents 4K bytes (16 pages) to store the write protection status
    description: Flash memory write protection status
    type: u32
    reset: 0xFFFFFFFF
    explaination:
      0xFFFFFFFF: Unprotected
      _: Some 4K sections are protected

# chip_id 0x8X for V4B, chip_id 0x3X for V4C
variants:
  - name: CH32V208WBU6
    chip_id: 0x80
    flash_size: 128K
  - name: CH32V208RBT6
    chip_id: 0x81
    flash_size: 128K
  - name: CH32V208CBU6
    chip_id: 0x82
    flash_size: 128K
  - name: CH32V208GBU6
    chip_id: 0x83
    flash_size: 128K
  - name: CH32V203C8U6
    chip_id: 0x30
    flash_size: 64K
  - name: CH32V203C8T6
    chip_id: 0x31
    flash_size: 64K
  - name: CH32V203K8T6
    chip_id: 0x32
    flash_size: 64K
  - name: CH32V203C6T6
    chip_id: 0x33
    flash_size: 32K
  - name: CH32V203RBT6
    chip_id: 0x34
    flash_size: 128K
  - name: CH32V203K6T6
    chip_id: 0x35
    flash_size: 32K
  - name: CH32V203G6U6
    chip_id: 0x36
    flash_size: 32K
  - name: CH32V203F6P6
    chip_id: 0x37
    alt_chip_ids: [0x39]
    flash_size: 32K
  # FIXME: missing 0x38