--- name: CH32X03x Series # NOTE: mcu_type is hex-encoded, not "10" in base-10 mcu_type: 0x13 device_type: 0x23 support_net: false support_usb: true support_serial: true description: CH32X03x RISC-V4C Series # RM Section 20.5 config_registers: - offset: 0x00 name: RDPR_USER description: RDPR, nRDPR, USER, nUSER reset: 0xFFFF5AA5 fields: - bit_range: [7, 0] name: RDPR description: Read Protection. 0xA5 for unprotected, otherwise read-protected(ignoring WRP) explaination: 0xa5: Unprotected _: Protected # byte 2, [0:0] + 16 - bit_range: [16, 16] name: IWDG_SW description: Independent watchdog (IWDG) hardware enable explaination: 1: IWDG enabled by the software, and disabled by hardware 0: IWDG enabled by the software (decided along with the LSI clock) # [1:1] + 16 - bit_range: [17, 17] name: STOP_RST description: System reset control under the stop mode explaination: 1: Disable 0: Enable # [2:2] + 16 - bit_range: [18, 18] name: STANDBY_RST description: System reset control under the standby mode, STANDY_RST explaination: 1: Disable, entering standby-mode without RST 0: Enable # [4:3] + 16 - bit_range: [20, 19] name: RST_MOD description: Reset mode explaination: 0b00: Enable RST alternative function 0b11: Disable RST alternative function, use PA21/PC3/PB7 as GPIO _: Error - offset: 0x04 name: DATA description: Customizable 2 byte data, DATA0, nDATA0, DATA1, nDATA1 reset: 0xFF00FF00 type: u32 fields: - bit_range: [7, 0] name: DATA0 - bit_range: [23, 16] name: DATA1 - offset: 0x08 name: WRP # Each bit represents 4K bytes (16 pages) to store the write protection status description: Flash memory write protection status type: u32 reset: 0xFFFFFFFF explaination: 0xFFFFFFFF: Unprotected _: Some 4K sections are protected variants: - name: CH32X035R8T6 chip_id: 80 flash_size: 64K - name: CH32X035C8T6 chip_id: 81 flash_size: 64K - name: CH32X035F8U6 chip_id: 94 flash_size: 64K - name: CH32X035G8U6 chip_id: 86 flash_size: 64K - name: CH32X035G8R6 chip_id: 91 flash_size: 64K - name: CH32X035F7P6 chip_id: 87 flash_size: 49152