# Performance Monitoring Events for the Fifth Generation Intel Core Processors Based on the Broadwell Microarchitecture - V23
# 8/7/2018 8:47:47 AM
# Copyright (c) 2007 - 2017 Intel Corporation. All rights reserved.
Unit	EventCode	UMask	EventName	Description	Counter	CounterMask	Invert	EdgeDetect
CBO	0x22	0x41	UNC_CBO_XSNP_RESPONSE.MISS_XCORE	A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.	0,1	0	0	0
CBO	0x22	0x81	UNC_CBO_XSNP_RESPONSE.MISS_EVICTION	A cross-core snoop resulted from L3 Eviction which misses in some processor core.	0,1	0	0	0
CBO	0x22	0x44	UNC_CBO_XSNP_RESPONSE.HIT_XCORE	A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.	0,1	0	0	0
CBO	0x22	0x48	UNC_CBO_XSNP_RESPONSE.HITM_XCORE	A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.	0,1	0	0	0
CBO	0x34	0x11	UNC_CBO_CACHE_LOOKUP.READ_M	L3 Lookup read request that access cache and found line in M-state	0,1	0	0	0
CBO	0x34	0x21	UNC_CBO_CACHE_LOOKUP.WRITE_M	L3 Lookup write request that access cache and found line in M-state	0,1	0	0	0
CBO	0x34	0x81	UNC_CBO_CACHE_LOOKUP.ANY_M	L3 Lookup any request that access cache and found line in M-state	0,1	0	0	0
CBO	0x34	0x18	UNC_CBO_CACHE_LOOKUP.READ_I	L3 Lookup read request that access cache and found line in I-state	0,1	0	0	0
CBO	0x34	0x88	UNC_CBO_CACHE_LOOKUP.ANY_I	L3 Lookup any request that access cache and found line in I-state	0,1	0	0	0
CBO	0x34	0x1f	UNC_CBO_CACHE_LOOKUP.READ_MESI	L3 Lookup read request that access cache and found line in any MESI-state	0,1	0	0	0
CBO	0x34	0x2f	UNC_CBO_CACHE_LOOKUP.WRITE_MESI	L3 Lookup write request that access cache and found line in MESI-state	0,1	0	0	0
CBO	0x34	0x8f	UNC_CBO_CACHE_LOOKUP.ANY_MESI	L3 Lookup any request that access cache and found line in MESI-state	0,1	0	0	0
CBO	0x34	0x86	UNC_CBO_CACHE_LOOKUP.ANY_ES	L3 Lookup any request that access cache and found line in E or S-state	0,1	0	0	0
CBO	0x34	0x16	UNC_CBO_CACHE_LOOKUP.READ_ES	L3 Lookup read request that access cache and found line in E or S-state	0,1	0	0	0
CBO	0x34	0x26	UNC_CBO_CACHE_LOOKUP.WRITE_ES	L3 Lookup write request that access cache and found line in E or S-state	0,1	0	0	0
NCU	0x0	0x01	UNC_CLOCK.SOCKET	This 48-bit fixed counter counts the UCLK cycles	FIXED	0	0	0
iMPH-U	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.ALL	Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.	0,	0	0	0
iMPH-U	0x80	0x02	UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT	Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.	0,	0	0	0
iMPH-U	0x81	0x01	UNC_ARB_TRK_REQUESTS.ALL	Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.	0,1	0	0	0
iMPH-U	0x81	0x02	UNC_ARB_TRK_REQUESTS.DRD_DIRECT	Number of Core coherent Data Read entries allocated in DirectData mode	0,1	0	0	0
iMPH-U	0x81	0x20	UNC_ARB_TRK_REQUESTS.WRITES	Number of Writes allocated - any write transactions: full/partials writes and evictions.	0,1	0	0	0
iMPH-U	0x84	0x01	UNC_ARB_COH_TRK_REQUESTS.ALL	Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.	0,1	0	0	0
iMPH-U	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST	Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;	0,	1	0	0