[
  {
    "BitName": "DEMAND_DATA_RD",
    "BitIndex": "0",
    "Type": "1",
    "Description": "Counts demand cacheable data reads of full cache lines",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "DEMAND_RFO",
    "BitIndex": "1",
    "Type": "1",
    "Description": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "DEMAND_CODE_RD",
    "BitIndex": "2",
    "Type": "1",
    "Description": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "COREWB",
    "BitIndex": "3",
    "Type": "1",
    "Description": "Counts the number of writeback transactions caused by L1 or L2 cache evictions",
    "MATRIX_REG": "0",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "PF_L2_DATA_RD",
    "BitIndex": "4",
    "Type": "1",
    "Description": "Counts data cacheline reads generated by hardware L2 cache prefetcher",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "PF_L2_RFO",
    "BitIndex": "5",
    "Type": "1",
    "Description": "Counts reads for ownership (RFO) requests generated by L2 prefetcher",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "PARTIAL_READS",
    "BitIndex": "7",
    "Type": "1",
    "Description": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "PARTIAL_WRITES",
    "BitIndex": "8",
    "Type": "1",
    "Description": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "BUS_LOCKS",
    "BitIndex": "10",
    "Type": "1",
    "Description": "Counts bus lock and split lock requests",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "FULL_STREAMING_STORES",
    "BitIndex": "11",
    "Type": "1",
    "Description": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "SW_PREFETCH",
    "BitIndex": "12",
    "Type": "1",
    "Description": "Counts data cache lines requests by software prefetch instructions",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "PF_L1_DATA_RD",
    "BitIndex": "13",
    "Type": "1",
    "Description": "Counts data cache line reads generated by hardware L1 data cache prefetcher",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "PARTIAL_STREAMING_STORES",
    "BitIndex": "14",
    "Type": "1",
    "Description": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "STREAMING_STORES",
    "BitIndex": "11,14",
    "Type": "1",
    "Description": "Counts any data writes to uncacheable write combining (USWC) memory region",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "ANY_REQUEST",
    "BitIndex": "15",
    "Type": "1",
    "Description": "Counts requests to the uncore subsystem",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "ANY_PF_DATA_RD",
    "BitIndex": "4,12,13",
    "Type": "1",
    "Description": "Counts data reads generated by L1 or L2 prefetchers",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "ANY_DATA_RD",
    "BitIndex": "0,4,7,12,13",
    "Type": "1",
    "Description": "Counts data reads (demand & prefetch)",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "ANY_RFO",
    "BitIndex": "1,5",
    "Type": "1",
    "Description": "Counts reads for ownership (RFO) requests (demand & prefetch)",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "ANY_READ",
    "BitIndex": "0,1,2,4,5,7,9,12,13",
    "Type": "1",
    "Description": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch)",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "ANY_RESPONSE",
    "BitIndex": "16",
    "Type": "2",
    "Description": "have any transaction responses from the uncore subsystem.",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "L2_HIT",
    "BitIndex": "18",
    "Type": "2",
    "Description": "hit the L2 cache.",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
    "BitIndex": "33",
    "Type": "2",
    "Description": "true miss for the L2 cache with a snoop miss in the other processor module. ",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "L2_MISS.HIT_OTHER_CORE_NO_FWD",
    "BitIndex": "34",
    "Type": "2",
    "Description": "miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "L2_MISS.HITM_OTHER_CORE",
    "BitIndex": "36",
    "Type": "2",
    "Description": "miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "L2_MISS.NON_DRAM",
    "BitIndex": "37",
    "Type": "2",
    "Description": "miss the L2 cache and targets non-DRAM system address.",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "L2_MISS.ANY",
    "BitIndex": "33,34,36,37",
    "Type": "2",
    "Description": "miss the L2 cache.",
    "MATRIX_REG": "0,1",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  },
  {
    "BitName": "OUTSTANDING",
    "BitIndex": "38",
    "Type": "2",
    "Description": "outstanding, per cycle, from the time of the L2 miss to when any response is received.",
    "MATRIX_REG": "0",
    "BitsNotCombinedWith": "",
    "Errata": "na"
  }
]