# Performance Monitoring Events for Intel Atom Processors Based on the Goldmont Microarchitecture - V13
# 3/2/2018 3:20:06 PM
# Copyright (c) 2007 - 2017 Intel Corporation. All rights reserved.
BitName	BitIndex	Type	Description	MATRIX_REG	BitsNotCombinedWith	Errata
DEMAND_DATA_RD	0	1	Counts demand cacheable data reads of full cache lines	0,1		na
DEMAND_RFO	1	1	Counts demand reads for ownership (RFO) requests generated by a write to full data cache line	0,1		na
DEMAND_CODE_RD	2	1	Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache	0,1		na
COREWB	3	1	Counts the number of writeback transactions caused by L1 or L2 cache evictions	0		na
PF_L2_DATA_RD	4	1	Counts data cacheline reads generated by hardware L2 cache prefetcher	0,1		na
PF_L2_RFO	5	1	Counts reads for ownership (RFO) requests generated by L2 prefetcher	0,1		na
PARTIAL_READS	7	1	Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types	0,1		na
PARTIAL_WRITES	8	1	Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory	0,1		na
BUS_LOCKS	10	1	Counts bus lock and split lock requests	0,1		na
FULL_STREAMING_STORES	11	1	Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes	0,1		na
SW_PREFETCH	12	1	Counts data cache lines requests by software prefetch instructions	0,1		na
PF_L1_DATA_RD	13	1	Counts data cache line reads generated by hardware L1 data cache prefetcher	0,1		na
PARTIAL_STREAMING_STORES	14	1	Counts partial cache line data writes to uncacheable write combining (USWC) memory region	0,1		na
STREAMING_STORES	11,14	1	Counts any data writes to uncacheable write combining (USWC) memory region	0,1		na
ANY_REQUEST	15	1	Counts requests to the uncore subsystem	0,1		na
ANY_PF_DATA_RD	4,12,13	1	Counts data reads generated by L1 or L2 prefetchers	0,1		na
ANY_DATA_RD	0,4,7,12,13	1	Counts data reads (demand & prefetch)	0,1		na
ANY_RFO	1,5	1	Counts reads for ownership (RFO) requests (demand & prefetch)	0,1		na
ANY_READ	0,1,2,4,5,7,9,12,13	1	Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch)	0,1		na
ANY_RESPONSE	16	2	have any transaction responses from the uncore subsystem.	0,1		na
L2_HIT	18	2	hit the L2 cache.	0,1		na
L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED	33	2	true miss for the L2 cache with a snoop miss in the other processor module. 	0,1		na
L2_MISS.HIT_OTHER_CORE_NO_FWD	34	2	miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.	0,1		na
L2_MISS.HITM_OTHER_CORE	36	2	miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.	0,1		na
L2_MISS.NON_DRAM	37	2	miss the L2 cache and targets non-DRAM system address.	0,1		na
L2_MISS.ANY	33,34,36,37	2	miss the L2 cache.	0,1		na
OUTSTANDING	38	2	outstanding, per cycle, from the time of the L2 miss to when any response is received.	0		na