# Performance Monitoring Events for Intel Atom Processors Based on the GoldmontPlus Microarchitecture - V1.01 # 3/2/2018 3:19:18 PM # Copyright (c) 2007 - 2017 Intel Corporation. All rights reserved. EventCode UMask EventName BriefDescription Counter PEBScounters SampleAfterValue MSRIndex MSRValue CollectPEBSRecord CounterMask Invert AnyThread EdgeDetect PEBS Data_LA Errata PDIR_COUNTER 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000010001 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT Counts demand cacheable data reads of full cache lines hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000040001 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200000001 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000000001 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000000001 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000010002 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000040002 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200000002 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000000002 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000000002 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000010004 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000040004 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200000004 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HITM_OTHER_CORE Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000000004 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000000004 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.COREWB.ANY_RESPONSE Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000010008 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.COREWB.L2_HIT Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000040008 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200000008 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000000008 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.COREWB.OUTSTANDING Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000000008 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000010010 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000040010 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200000010 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000000010 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L2_DATA_RD.OUTSTANDING Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000000010 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000010020 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000040020 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200000020 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000000020 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L2_RFO.OUTSTANDING Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000000020 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000010400 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT Counts bus lock and split lock requests hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000040400 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200000400 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.HITM_OTHER_CORE Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000000400 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000000400 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000010800 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000040800 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200000800 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000000800 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.FULL_STREAMING_STORES.OUTSTANDING Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000000800 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.SW_PREFETCH.ANY_RESPONSE Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000011000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT Counts data cache lines requests by software prefetch instructions hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000041000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200001000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000001000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.SW_PREFETCH.OUTSTANDING Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000001000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000012000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000042000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200002000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000002000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000002000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000014800 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000044800 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200004800 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.HITM_OTHER_CORE Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000004800 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.STREAMING_STORES.OUTSTANDING Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000004800 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000018000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT Counts requests to the uncore subsystem hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000048000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200008000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000008000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000008000 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_PF_DATA_RD.ANY_RESPONSE Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000013010 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000043010 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200003010 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000003010 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_PF_DATA_RD.OUTSTANDING Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000003010 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000013091 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT Counts data reads (demand & prefetch) hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000043091 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200003091 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000003091 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000003091 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000010022 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_RFO.L2_HIT Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0000040022 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x0200000022 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x1000000022 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x4000000022 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x00000132b7 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_READ.L2_HIT Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x00000432b7 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x02000032b7 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. 0,1,2,3 0,1,2,3 100007 0x1a6, 0x1a7 0x10000032b7 1 0 0 0 0 0 0 0 na 0xB7 0x01,0x02 OFFCORE_RESPONSE.ANY_READ.OUTSTANDING Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. 0,1,2,3 0,1,2,3 100007 0x1a6 0x40000032b7 1 0 0 0 0 0 0 0 na