# Performance Monitoring Events for the Fourth Generation Intel Core Processors Based on the Haswell Microarchitecture - V28
# 8/7/2018 1:02:46 AM
# Copyright (c) 2007 - 2017 Intel Corporation. All rights reserved.
BitName	BitIndex	Type	Description	MATRIX_REG	BitsNotCombinedWith	Errata
DEMAND_DATA_RD	0	1	Counts demand data reads	0,1		na
DEMAND_RFO	1	1	Counts all demand data writes (RFOs)	0,1		na
DEMAND_CODE_RD	2	1	Counts all demand code reads	0,1		na
COREWB	3	1		0,1		HSD150
PF_L2_DATA_RD	4	1	Counts prefetch (that bring data to L2) data reads	0,1		na
PF_L2_RFO	5	1	Counts all prefetch (that bring data to L2) RFOs	0,1		na
PF_L2_CODE_RD	6	1	Counts all prefetch (that bring data to LLC only) code reads	0,1		na
PF_L3_DATA_RD	7	1	Counts all prefetch (that bring data to LLC only) data reads	0,1		HSD150
PF_L3_RFO	8	1	Counts all prefetch (that bring data to LLC only) RFOs	0,1		HSD150
PF_L3_CODE_RD	9	1	Counts prefetch (that bring data to LLC only) code reads	0,1		HSD150
SPLIT_LOCK_UC_LOCK	10	1		0,1		HSD150
STREAMING_STORES	11	1		0,1		HSD150
OTHER	15	1	Counts any other requests	0,1		na
ALL_PF_DATA_RD	4,7	1	Counts all prefetch data reads	0,1		HSD150
ALL_PF_RFO	5,8	1	Counts prefetch RFOs	0,1		HSD150
ALL_PF_CODE_RD	6,9	1	Counts all prefetch code reads	0,1		HSD150
ALL_DATA_RD	0,4,7	1	Counts all demand & prefetch data reads	0,1		HSD150
ALL_RFO	1,5,8	1	Counts all demand & prefetch RFOs	0,1		HSD150
ALL_CODE_RD	2,6,9	1	Counts all demand & prefetch code reads	0,1		HSD150
ALL_READS	0,1,2,4,5,6,7,8,9,10	1		0,1		HSD150
ALL_REQUESTS	0,1,2,3,4,5,6,7,8,9,10,11,15	1	Counts all requests	0,1		HSD150
ANY_RESPONSE	16	2	have any response type.	0,1		na
SUPPLIER_NONE	17	3		0,1	116,117,118,119,120,121,122,123,124	na
L3_HIT_M	18	3		0,1	116,117,118,119,120,121,122,123,124	na
L3_HIT_E	19	3		0,1	116,117,118,119,120,121,122,123,124	na
L3_HIT_S	20	3		0,1	116,117,118,119,120,121,122,123,124	na
L3_HIT	18,19,20	3		0,1	116,117,118,119,120,121,122,123,124	na
L3_MISS_LOCAL_DRAM	22	3		0,1	116,117,118,119,120,121,122,123,124	na
SNOOP_NONE	31	4		0,1	na	na
SNOOP_NOT_NEEDED	32	4		0,1	na	na
SNOOP_MISS	33	4		0,1	na	na
SNOOP_HIT_NO_FWD	34	4		0,1	na	na
SNOOP_HIT_WITH_FWD	35	4		0,1	na	na
SNOOP_HITM	36	4		0,1	na	na
SNOOP_NON_DRAM	37	4		0,1	na	na
ANY_SNOOP	31,32,33,34,35,36,37	4		0,1	na	na
L3_HIT.NO_SNOOP_NEEDED	18,19,20,21,32	2	hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores	0,1	na	na
L3_HIT.HIT_OTHER_CORE_NO_FWD	18,19,20,21,34	2	hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded	0,1	na	na
L3_HIT.HITM_OTHER_CORE	18,19,20,21,36	2	hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded	0,1	na	na
L3_MISS.LOCAL_DRAM	22,32	2	miss the L3 and the data is returned from local dram	0,1	na	na
L3_MISS.ANY_DRAM	22,23,24,25,26,27,28,29,30,33,34	2	miss the L3 and the data is returned from local or remote dram	0,1	na	na
L3_HIT.ANY_RESPONSE	18,19,20,21,31,32,33,34,35,36,37	2	hit in the L3	0,1	na	na
L3_MISS.ANY_RESPONSE	22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37	2	miss in the L3	0,1	na	na