# Performance Monitoring Events for the Third Generation Intel Core Processors Based on the Ivy Bridge Microarchitecture - V21
# 2/28/2018 4:20:34 PM
# Copyright (c) 2007 - 2017 Intel Corporation. All rights reserved.
Unit	EventCode	UMask	EventName	Description	Counter	CounterMask	Invert	EdgeDetect
ARB	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.ALL	Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.	0	0	0	0
ARB	0x81	0x01	UNC_ARB_TRK_REQUESTS.ALL	Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.	0,1	0	0	0
ARB	0x81	0x20	UNC_ARB_TRK_REQUESTS.WRITES	Counts the number of allocated write entries, include full, partial, and LLC evictions.	0,1	0	0	0
ARB	0x81	0x80	UNC_ARB_TRK_REQUESTS.EVICTIONS	Counts the number of LLC evictions allocated.	0,1	0	0	0
ARB	0x83	0x01	UNC_ARB_COH_TRK_OCCUPANCY.ALL	Cycles weighted by number of requests pending in Coherency Tracker.	0	0	0	0
ARB	0x84	0x01	UNC_ARB_COH_TRK_REQUESTS.ALL	Number of requests allocated in Coherency Tracker.	0,1	0	0	0
ARB	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST	Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.	0,1	1	0	0
ARB	0x80	0x01	UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL	Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.	0,1	10	0	0
ARB	0x0	0x01	UNC_CLOCK.SOCKET	This 48-bit fixed counter counts the UCLK cycles.	Fixed	0	0	0
CBO	0x34	0x11	UNC_CBO_CACHE_LOOKUP.READ_M	L3 Lookup read request that access cache and found line in M-state.	0,1	0	0	0
CBO	0x34	0x21	UNC_CBO_CACHE_LOOKUP.WRITE_M	L3 Lookup write request that access cache and found line in M-state.	0,1	0	0	0
CBO	0x34	0x41	UNC_CBO_CACHE_LOOKUP.EXTSNP_M	L3 Lookup external snoop request that access cache and found line in M-state.	0,1	0	0	0
CBO	0x34	0x81	UNC_CBO_CACHE_LOOKUP.ANY_M	L3 Lookup any request that access cache and found line in M-state.	0,1	0	0	0
CBO	0x34	0x18	UNC_CBO_CACHE_LOOKUP.READ_I	L3 Lookup read request that access cache and found line in I-state.	0,1	0	0	0
CBO	0x34	0x28	UNC_CBO_CACHE_LOOKUP.WRITE_I	L3 Lookup write request that access cache and found line in I-state.	0,1	0	0	0
CBO	0x34	0x48	UNC_CBO_CACHE_LOOKUP.EXTSNP_I	L3 Lookup external snoop request that access cache and found line in I-state.	0,1	0	0	0
CBO	0x34	0x88	UNC_CBO_CACHE_LOOKUP.ANY_I	L3 Lookup any request that access cache and found line in I-state.	0,1	0	0	0
CBO	0x34	0x1f	UNC_CBO_CACHE_LOOKUP.READ_MESI	L3 Lookup read request that access cache and found line in any MESI-state.	0,1	0	0	0
CBO	0x34	0x2f	UNC_CBO_CACHE_LOOKUP.WRITE_MESI	L3 Lookup write request that access cache and found line in MESI-state.	0,1	0	0	0
CBO	0x34	0x4f	UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI	L3 Lookup external snoop request that access cache and found line in MESI-state.	0,1	0	0	0
CBO	0x34	0x8f	UNC_CBO_CACHE_LOOKUP.ANY_MESI	L3 Lookup any request that access cache and found line in MESI-state.	0,1	0	0	0
CBO	0x34	0x86	UNC_CBO_CACHE_LOOKUP.ANY_ES	L3 Lookup any request that access cache and found line in E or S-state.	0,1	0	0	0
CBO	0x34	0x46	UNC_CBO_CACHE_LOOKUP.EXTSNP_ES	L3 Lookup external snoop request that access cache and found line in E or S-state.	0,1	0	0	0
CBO	0x34	0x16	UNC_CBO_CACHE_LOOKUP.READ_ES	L3 Lookup read request that access cache and found line in E or S-state.	0,1	0	0	0
CBO	0x34	0x26	UNC_CBO_CACHE_LOOKUP.WRITE_ES	L3 Lookup write request that access cache and found line in E or S-state.	0,1	0	0	0
CBO	0x22	0x21	UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL	An external snoop misses in some processor core.	0,1	0	0	0
CBO	0x22	0x41	UNC_CBO_XSNP_RESPONSE.MISS_XCORE	A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.	0,1	0	0	0
CBO	0x22	0x81	UNC_CBO_XSNP_RESPONSE.MISS_EVICTION	A cross-core snoop resulted from L3 Eviction which misses in some processor core.	0,1	0	0	0
CBO	0x22	0x24	UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL	An external snoop hits a non-modified line in some processor core.	0,1	0	0	0
CBO	0x22	0x44	UNC_CBO_XSNP_RESPONSE.HIT_XCORE	A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.	0,1	0	0	0
CBO	0x22	0x84	UNC_CBO_XSNP_RESPONSE.HIT_EVICTION	A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.	0,1	0	0	0
CBO	0x22	0x28	UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL	An external snoop hits a modified line in some processor core.	0,1	0	0	0
CBO	0x22	0x48	UNC_CBO_XSNP_RESPONSE.HITM_XCORE	A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.	0,1	0	0	0
CBO	0x22	0x88	UNC_CBO_XSNP_RESPONSE.HITM_EVICTION	A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.	0,1	0	0	0