# Performance Monitoring Events for Intel(R) Xeon(R) processor E5 family Based on the Sandy Bridge-EP Microarchitecture - V20
# 9/16/2016 11:35:14 AM
# Copyright (c) 2007 - 2016 Intel Corporation. All rights reserved.
BitName	BitIndex	Type	Description	MATRIX_REG	BitsNotCombinedWith	Errata
DEMAND_DATA_RD	0	1	TBD	0,1	Null	Null
DEMAND_RFO	1	1	TBD	0,1	Null	Null
DEMAND_CODE_RD	2	1	TBD	0,1	Null	Null
COREWB	3	1	TBD	0,1	Null	Null
PF_L2_DATA_RD	4	1	TBD	0,1	Null	Null
PF_L2_RFO	5	1	TBD	0,1	Null	Null
PF_L2_CODE_RD	6	1	TBD	0,1	Null	Null
PF_LLC_DATA_RD	7	1	TBD	0,1	Null	Null
PF_LLC_RFO	8	1	TBD	0,1	Null	Null
PF_LLC_CODE_RD	9	1	TBD	0,1	Null	Null
SPLIT_LOCK_UC_LOCK	10	1	TBD	0,1	Null	Null
STREAMING_STORES	11	1	TBD	0,1	Null	Null
OTHER	15	1	TBD	0,1	Null	Null
ALL_PF_DATA_RD	4,7	1	TBD	0,1	Null	Null
ALL_PF_RFO	5,8	1	TBD	0,1	Null	Null
ALL_PF_CODE_RD	6,9	1	TBD	0,1	Null	Null
ALL_DATA_RD	0,4,7	1	TBD	0,1	Null	Null
ALL_RFO	1,5,8	1	TBD	0,1	Null	Null
ALL_CODE_RD	2,6,9	1	TBD	0,1	Null	Null
ALL_READS	0,1,2,4,5,6,7,8,9	1	TBD	0,1	Null	Null
ALL_REQUESTS	0,1,2,3,4,5,6,7,8,9,10,11,15	1	TBD	0,1	Null	Null
ANY_RESPONSE	16	2	TBD	0,1	Null	Null
SUPPLIER_NONE	17	3	TBD	0,1	Null	Null
LLC_HIT_M	18	3	TBD	0,1	Null	Null
LLC_HIT_E	19	3	TBD	0,1	Null	Null
LLC_HIT_S	20	3	TBD	0,1	Null	Null
LLC_HIT_F	21	3	TBD	0,1	Null	Null
LLC_HIT	18,19,20,21	3	TBD	0,1	Null	Null
L3_MISS_LOCAL_DRAM	22	3	TBD	0,1	Null	Null
L3_MISS_REMOTE_DRAM	22,23,24,25,26,27,28,29,30	3	TBD	0,1	Null	Null
SNOOP_NONE	31	4	TBD	0,1	Null	Null
SNOOP_NOT_NEEDED	32	4	TBD	0,1	Null	Null
SNOOP_MISS	33	4	TBD	0,1	Null	Null
SNOOP_HIT_NO_FWD	34	4	TBD	0,1	Null	Null
SNOOP_HIT_WITH_FWD	35	4	TBD	0,1	18,19,20,21	Null
SNOOP_HITM	36	4	TBD	0,1	Null	Null
SNOOP_NON_DRAM	37	4	TBD	0,1	Null	Null
ANY_SNOOP	31,32,33,34,35,36,37	4	TBD	0,1	Null	Null