[
  {
    "EventCode": "0x14",
    "UMask": "0x1",
    "EventName": "ARITH.CYCLES_DIV_BUSY",
    "BriefDescription": "Cycles the divider is busy",
    "PublicDescription": "Cycles the divider is busy",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x14",
    "UMask": "0x1",
    "EventName": "ARITH.DIV",
    "BriefDescription": "Divide Operations executed",
    "PublicDescription": "Divide Operations executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "1",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x14",
    "UMask": "0x2",
    "EventName": "ARITH.MUL",
    "BriefDescription": "Multiply operations executed",
    "PublicDescription": "Multiply operations executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xE6",
    "UMask": "0x2",
    "EventName": "BACLEAR.BAD_TARGET",
    "BriefDescription": "BACLEAR asserted with bad target address",
    "PublicDescription": "BACLEAR asserted with bad target address",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xE6",
    "UMask": "0x1",
    "EventName": "BACLEAR.CLEAR",
    "BriefDescription": "BACLEAR asserted, regardless of cause ",
    "PublicDescription": "BACLEAR asserted, regardless of cause ",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA7",
    "UMask": "0x1",
    "EventName": "BACLEAR_FORCE_IQ",
    "BriefDescription": "Instruction queue forced BACLEAR",
    "PublicDescription": "Instruction queue forced BACLEAR",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xE8",
    "UMask": "0x1",
    "EventName": "BPU_CLEARS.EARLY",
    "BriefDescription": "Early Branch Prediciton Unit clears",
    "PublicDescription": "Early Branch Prediciton Unit clears",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xE8",
    "UMask": "0x2",
    "EventName": "BPU_CLEARS.LATE",
    "BriefDescription": "Late Branch Prediction Unit clears",
    "PublicDescription": "Late Branch Prediction Unit clears",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xE5",
    "UMask": "0x1",
    "EventName": "BPU_MISSED_CALL_RET",
    "BriefDescription": "Branch prediction unit missed call or return",
    "PublicDescription": "Branch prediction unit missed call or return",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xE0",
    "UMask": "0x1",
    "EventName": "BR_INST_DECODED",
    "BriefDescription": "Branch instructions decoded",
    "PublicDescription": "Branch instructions decoded",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x7F",
    "EventName": "BR_INST_EXEC.ANY",
    "BriefDescription": "Branch instructions executed",
    "PublicDescription": "Branch instructions executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x1",
    "EventName": "BR_INST_EXEC.COND",
    "BriefDescription": "Conditional branch instructions executed",
    "PublicDescription": "Conditional branch instructions executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x2",
    "EventName": "BR_INST_EXEC.DIRECT",
    "BriefDescription": "Unconditional branches executed",
    "PublicDescription": "Unconditional branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x10",
    "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
    "BriefDescription": "Unconditional call branches executed",
    "PublicDescription": "Unconditional call branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x20",
    "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
    "BriefDescription": "Indirect call branches executed",
    "PublicDescription": "Indirect call branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x4",
    "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
    "BriefDescription": "Indirect non call branches executed",
    "PublicDescription": "Indirect non call branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x30",
    "EventName": "BR_INST_EXEC.NEAR_CALLS",
    "BriefDescription": "Call branches executed",
    "PublicDescription": "Call branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x7",
    "EventName": "BR_INST_EXEC.NON_CALLS",
    "BriefDescription": "All non call branches executed",
    "PublicDescription": "All non call branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x8",
    "EventName": "BR_INST_EXEC.RETURN_NEAR",
    "BriefDescription": "Indirect return branches executed",
    "PublicDescription": "Indirect return branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x40",
    "EventName": "BR_INST_EXEC.TAKEN",
    "BriefDescription": "Taken branches executed",
    "PublicDescription": "Taken branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC4",
    "UMask": "0x4",
    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
    "BriefDescription": "Retired branch instructions (Precise Event)",
    "PublicDescription": "Retired branch instructions (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC4",
    "UMask": "0x1",
    "EventName": "BR_INST_RETIRED.CONDITIONAL",
    "BriefDescription": "Retired conditional branch instructions (Precise Event)",
    "PublicDescription": "Retired conditional branch instructions (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC4",
    "UMask": "0x2",
    "EventName": "BR_INST_RETIRED.NEAR_CALL",
    "BriefDescription": "Retired near call instructions (Precise Event)",
    "PublicDescription": "Retired near call instructions (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x7F",
    "EventName": "BR_MISP_EXEC.ANY",
    "BriefDescription": "Mispredicted branches executed",
    "PublicDescription": "Mispredicted branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x1",
    "EventName": "BR_MISP_EXEC.COND",
    "BriefDescription": "Mispredicted conditional branches executed",
    "PublicDescription": "Mispredicted conditional branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x2",
    "EventName": "BR_MISP_EXEC.DIRECT",
    "BriefDescription": "Mispredicted unconditional branches executed",
    "PublicDescription": "Mispredicted unconditional branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x10",
    "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
    "BriefDescription": "Mispredicted non call branches executed",
    "PublicDescription": "Mispredicted non call branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x20",
    "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
    "BriefDescription": "Mispredicted indirect call branches executed",
    "PublicDescription": "Mispredicted indirect call branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x4",
    "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
    "BriefDescription": "Mispredicted indirect non call branches executed",
    "PublicDescription": "Mispredicted indirect non call branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x30",
    "EventName": "BR_MISP_EXEC.NEAR_CALLS",
    "BriefDescription": "Mispredicted call branches executed",
    "PublicDescription": "Mispredicted call branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x7",
    "EventName": "BR_MISP_EXEC.NON_CALLS",
    "BriefDescription": "Mispredicted non call branches executed",
    "PublicDescription": "Mispredicted non call branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x8",
    "EventName": "BR_MISP_EXEC.RETURN_NEAR",
    "BriefDescription": "Mispredicted return branches executed",
    "PublicDescription": "Mispredicted return branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x40",
    "EventName": "BR_MISP_EXEC.TAKEN",
    "BriefDescription": "Mispredicted taken branches executed",
    "PublicDescription": "Mispredicted taken branches executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC5",
    "UMask": "0x2",
    "EventName": "BR_MISP_RETIRED.NEAR_CALL",
    "BriefDescription": "Mispredicted near retired calls (Precise Event)",
    "PublicDescription": "Mispredicted near retired calls (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0x63",
    "UMask": "0x2",
    "EventName": "CACHE_LOCK_CYCLES.L1D",
    "BriefDescription": "Cycles L1D locked",
    "PublicDescription": "Cycles L1D locked",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x63",
    "UMask": "0x1",
    "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
    "BriefDescription": "Cycles L1D and L2 locked",
    "PublicDescription": "Cycles L1D and L2 locked",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0",
    "UMask": "0x0",
    "EventName": "CPU_CLK_UNHALTED.REF",
    "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
    "PublicDescription": "Reference cycles when thread is not halted (fixed counter)",
    "Counter": "Fixed counter 3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3C",
    "UMask": "0x1",
    "EventName": "CPU_CLK_UNHALTED.REF_P",
    "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
    "PublicDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0",
    "UMask": "0x0",
    "EventName": "CPU_CLK_UNHALTED.THREAD",
    "BriefDescription": "Cycles when thread is not halted (fixed counter)",
    "PublicDescription": "Cycles when thread is not halted (fixed counter)",
    "Counter": "Fixed counter 2",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3C",
    "UMask": "0x0",
    "EventName": "CPU_CLK_UNHALTED.THREAD_P",
    "BriefDescription": "Cycles when thread is not halted (programmable counter)",
    "PublicDescription": "Cycles when thread is not halted (programmable counter)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3C",
    "UMask": "0x0",
    "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
    "BriefDescription": "Total CPU cycles",
    "PublicDescription": "Total CPU cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "2",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x8",
    "UMask": "0x1",
    "EventName": "DTLB_LOAD_MISSES.ANY",
    "BriefDescription": "DTLB load misses",
    "PublicDescription": "DTLB load misses",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x8",
    "UMask": "0x20",
    "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
    "BriefDescription": "DTLB load miss caused by low part of address",
    "PublicDescription": "DTLB load miss caused by low part of address",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x8",
    "UMask": "0x10",
    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
    "BriefDescription": "DTLB second level hit",
    "PublicDescription": "DTLB second level hit",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x8",
    "UMask": "0x2",
    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
    "BriefDescription": "DTLB load miss page walks complete",
    "PublicDescription": "DTLB load miss page walks complete",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x1",
    "EventName": "DTLB_MISSES.ANY",
    "BriefDescription": "DTLB misses",
    "PublicDescription": "DTLB misses",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x10",
    "EventName": "DTLB_MISSES.STLB_HIT",
    "BriefDescription": "DTLB first level misses but second level hit",
    "PublicDescription": "DTLB first level misses but second level hit",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x2",
    "EventName": "DTLB_MISSES.WALK_COMPLETED",
    "BriefDescription": "DTLB miss page walks",
    "PublicDescription": "DTLB miss page walks",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD5",
    "UMask": "0x1",
    "EventName": "ES_REG_RENAMES",
    "BriefDescription": "ES segment renames",
    "PublicDescription": "ES segment renames",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF7",
    "UMask": "0x1",
    "EventName": "FP_ASSIST.ALL",
    "BriefDescription": "X87 Floating point assists (Precise Event)",
    "PublicDescription": "X87 Floating point assists (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF7",
    "UMask": "0x4",
    "EventName": "FP_ASSIST.INPUT",
    "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
    "PublicDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF7",
    "UMask": "0x2",
    "EventName": "FP_ASSIST.OUTPUT",
    "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
    "PublicDescription": "X87 Floating point assists for invalid output value (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0x10",
    "UMask": "0x2",
    "EventName": "FP_COMP_OPS_EXE.MMX",
    "BriefDescription": "MMX Uops",
    "PublicDescription": "MMX Uops",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x10",
    "UMask": "0x80",
    "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
    "BriefDescription": "SSE* FP double precision Uops",
    "PublicDescription": "SSE* FP double precision Uops",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x10",
    "UMask": "0x4",
    "EventName": "FP_COMP_OPS_EXE.SSE_FP",
    "BriefDescription": "SSE and SSE2 FP Uops",
    "PublicDescription": "SSE and SSE2 FP Uops",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x10",
    "UMask": "0x10",
    "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
    "BriefDescription": "SSE FP packed Uops",
    "PublicDescription": "SSE FP packed Uops",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x10",
    "UMask": "0x20",
    "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
    "BriefDescription": "SSE FP scalar Uops",
    "PublicDescription": "SSE FP scalar Uops",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x10",
    "UMask": "0x40",
    "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
    "BriefDescription": "SSE* FP single precision Uops",
    "PublicDescription": "SSE* FP single precision Uops",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x10",
    "UMask": "0x8",
    "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
    "BriefDescription": "SSE2 integer Uops",
    "PublicDescription": "SSE2 integer Uops",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x10",
    "UMask": "0x1",
    "EventName": "FP_COMP_OPS_EXE.X87",
    "BriefDescription": "Computational floating-point operations executed",
    "PublicDescription": "Computational floating-point operations executed",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCC",
    "UMask": "0x3",
    "EventName": "FP_MMX_TRANS.ANY",
    "BriefDescription": "All Floating Point to and from MMX transitions",
    "PublicDescription": "All Floating Point to and from MMX transitions",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCC",
    "UMask": "0x1",
    "EventName": "FP_MMX_TRANS.TO_FP",
    "BriefDescription": "Transitions from MMX to Floating Point instructions",
    "PublicDescription": "Transitions from MMX to Floating Point instructions",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCC",
    "UMask": "0x2",
    "EventName": "FP_MMX_TRANS.TO_MMX",
    "BriefDescription": "Transitions from Floating Point to MMX instructions",
    "PublicDescription": "Transitions from Floating Point to MMX instructions",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x87",
    "UMask": "0xF",
    "EventName": "ILD_STALL.ANY",
    "BriefDescription": "Any Instruction Length Decoder stall cycles",
    "PublicDescription": "Any Instruction Length Decoder stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x87",
    "UMask": "0x4",
    "EventName": "ILD_STALL.IQ_FULL",
    "BriefDescription": "Instruction Queue full stall cycles",
    "PublicDescription": "Instruction Queue full stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x87",
    "UMask": "0x1",
    "EventName": "ILD_STALL.LCP",
    "BriefDescription": "Length Change Prefix stall cycles",
    "PublicDescription": "Length Change Prefix stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x87",
    "UMask": "0x2",
    "EventName": "ILD_STALL.MRU",
    "BriefDescription": "Stall cycles due to BPU MRU bypass",
    "PublicDescription": "Stall cycles due to BPU MRU bypass",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x87",
    "UMask": "0x8",
    "EventName": "ILD_STALL.REGEN",
    "BriefDescription": "Regen stall cycles",
    "PublicDescription": "Regen stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x18",
    "UMask": "0x1",
    "EventName": "INST_DECODED.DEC0",
    "BriefDescription": "Instructions that must be decoded by decoder 0",
    "PublicDescription": "Instructions that must be decoded by decoder 0",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x1E",
    "UMask": "0x1",
    "EventName": "INST_QUEUE_WRITE_CYCLES",
    "BriefDescription": "Cycles instructions are written to the instruction queue",
    "PublicDescription": "Cycles instructions are written to the instruction queue",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x17",
    "UMask": "0x1",
    "EventName": "INST_QUEUE_WRITES",
    "BriefDescription": "Instructions written to instruction queue.",
    "PublicDescription": "Instructions written to instruction queue.",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0",
    "UMask": "0x0",
    "EventName": "INST_RETIRED.ANY",
    "BriefDescription": "Instructions retired (fixed counter)",
    "PublicDescription": "Instructions retired (fixed counter)",
    "Counter": "Fixed counter 1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC0",
    "UMask": "0x1",
    "EventName": "INST_RETIRED.ANY_P",
    "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
    "PublicDescription": "Instructions retired (Programmable counter and Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC0",
    "UMask": "0x4",
    "EventName": "INST_RETIRED.MMX",
    "BriefDescription": "Retired MMX instructions (Precise Event)",
    "PublicDescription": "Retired MMX instructions (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC0",
    "UMask": "0x1",
    "EventName": "INST_RETIRED.TOTAL_CYCLES",
    "BriefDescription": "Total cycles (Precise Event)",
    "PublicDescription": "Total cycles (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "16",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC0",
    "UMask": "0x2",
    "EventName": "INST_RETIRED.X87",
    "BriefDescription": "Retired floating-point operations (Precise Event)",
    "PublicDescription": "Retired floating-point operations (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0x6C",
    "UMask": "0x1",
    "EventName": "IO_TRANSACTIONS",
    "BriefDescription": "I/O transactions",
    "PublicDescription": "I/O transactions",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xAE",
    "UMask": "0x1",
    "EventName": "ITLB_FLUSH",
    "BriefDescription": "ITLB flushes",
    "PublicDescription": "ITLB flushes",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC8",
    "UMask": "0x20",
    "EventName": "ITLB_MISS_RETIRED",
    "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
    "PublicDescription": "Retired instructions that missed the ITLB (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x1",
    "EventName": "ITLB_MISSES.ANY",
    "BriefDescription": "ITLB miss",
    "PublicDescription": "ITLB miss",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x2",
    "EventName": "ITLB_MISSES.WALK_COMPLETED",
    "BriefDescription": "ITLB miss page walks",
    "PublicDescription": "ITLB miss page walks",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x51",
    "UMask": "0x4",
    "EventName": "L1D.M_EVICT",
    "BriefDescription": "L1D cache lines replaced in M state",
    "PublicDescription": "L1D cache lines replaced in M state",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x51",
    "UMask": "0x2",
    "EventName": "L1D.M_REPL",
    "BriefDescription": "L1D cache lines allocated in the M state",
    "PublicDescription": "L1D cache lines allocated in the M state",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x51",
    "UMask": "0x8",
    "EventName": "L1D.M_SNOOP_EVICT",
    "BriefDescription": "L1D snoop eviction of cache lines in M state",
    "PublicDescription": "L1D snoop eviction of cache lines in M state",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x51",
    "UMask": "0x1",
    "EventName": "L1D.REPL",
    "BriefDescription": "L1 data cache lines allocated",
    "PublicDescription": "L1 data cache lines allocated",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x43",
    "UMask": "0x1",
    "EventName": "L1D_ALL_REF.ANY",
    "BriefDescription": "All references to the L1 data cache",
    "PublicDescription": "All references to the L1 data cache",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x43",
    "UMask": "0x2",
    "EventName": "L1D_ALL_REF.CACHEABLE",
    "BriefDescription": "L1 data cacheable reads and writes",
    "PublicDescription": "L1 data cacheable reads and writes",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x40",
    "UMask": "0x4",
    "EventName": "L1D_CACHE_LD.E_STATE",
    "BriefDescription": "L1 data cache read in E state",
    "PublicDescription": "L1 data cache read in E state",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x40",
    "UMask": "0x1",
    "EventName": "L1D_CACHE_LD.I_STATE",
    "BriefDescription": "L1 data cache read in I state (misses)",
    "PublicDescription": "L1 data cache read in I state (misses)",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x40",
    "UMask": "0x8",
    "EventName": "L1D_CACHE_LD.M_STATE",
    "BriefDescription": "L1 data cache read in M state",
    "PublicDescription": "L1 data cache read in M state",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x40",
    "UMask": "0xF",
    "EventName": "L1D_CACHE_LD.MESI",
    "BriefDescription": "L1 data cache reads",
    "PublicDescription": "L1 data cache reads",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x40",
    "UMask": "0x2",
    "EventName": "L1D_CACHE_LD.S_STATE",
    "BriefDescription": "L1 data cache read in S state",
    "PublicDescription": "L1 data cache read in S state",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x42",
    "UMask": "0x4",
    "EventName": "L1D_CACHE_LOCK.E_STATE",
    "BriefDescription": "L1 data cache load locks in E state",
    "PublicDescription": "L1 data cache load locks in E state",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x42",
    "UMask": "0x1",
    "EventName": "L1D_CACHE_LOCK.HIT",
    "BriefDescription": "L1 data cache load lock hits",
    "PublicDescription": "L1 data cache load lock hits",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x42",
    "UMask": "0x8",
    "EventName": "L1D_CACHE_LOCK.M_STATE",
    "BriefDescription": "L1 data cache load locks in M state",
    "PublicDescription": "L1 data cache load locks in M state",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x42",
    "UMask": "0x2",
    "EventName": "L1D_CACHE_LOCK.S_STATE",
    "BriefDescription": "L1 data cache load locks in S state",
    "PublicDescription": "L1 data cache load locks in S state",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x53",
    "UMask": "0x1",
    "EventName": "L1D_CACHE_LOCK_FB_HIT",
    "BriefDescription": "L1D load lock accepted in fill buffer",
    "PublicDescription": "L1D load lock accepted in fill buffer",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x52",
    "UMask": "0x1",
    "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
    "BriefDescription": "L1D prefetch load lock accepted in fill buffer",
    "PublicDescription": "L1D prefetch load lock accepted in fill buffer",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x41",
    "UMask": "0x4",
    "EventName": "L1D_CACHE_ST.E_STATE",
    "BriefDescription": "L1 data cache stores in E state",
    "PublicDescription": "L1 data cache stores in E state",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x41",
    "UMask": "0x8",
    "EventName": "L1D_CACHE_ST.M_STATE",
    "BriefDescription": "L1 data cache stores in M state",
    "PublicDescription": "L1 data cache stores in M state",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x41",
    "UMask": "0x2",
    "EventName": "L1D_CACHE_ST.S_STATE",
    "BriefDescription": "L1 data cache stores in S state",
    "PublicDescription": "L1 data cache stores in S state",
    "Counter": "0,1",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x4E",
    "UMask": "0x2",
    "EventName": "L1D_PREFETCH.MISS",
    "BriefDescription": "L1D hardware prefetch misses",
    "PublicDescription": "L1D hardware prefetch misses",
    "Counter": "0,1",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x4E",
    "UMask": "0x1",
    "EventName": "L1D_PREFETCH.REQUESTS",
    "BriefDescription": "L1D hardware prefetch requests",
    "PublicDescription": "L1D hardware prefetch requests",
    "Counter": "0,1",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x4E",
    "UMask": "0x4",
    "EventName": "L1D_PREFETCH.TRIGGERS",
    "BriefDescription": "L1D hardware prefetch requests triggered",
    "PublicDescription": "L1D hardware prefetch requests triggered",
    "Counter": "0,1",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x28",
    "UMask": "0x4",
    "EventName": "L1D_WB_L2.E_STATE",
    "BriefDescription": "L1 writebacks to L2 in E state",
    "PublicDescription": "L1 writebacks to L2 in E state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x28",
    "UMask": "0x1",
    "EventName": "L1D_WB_L2.I_STATE",
    "BriefDescription": "L1 writebacks to L2 in I state (misses)",
    "PublicDescription": "L1 writebacks to L2 in I state (misses)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x28",
    "UMask": "0x8",
    "EventName": "L1D_WB_L2.M_STATE",
    "BriefDescription": "L1 writebacks to L2 in M state",
    "PublicDescription": "L1 writebacks to L2 in M state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x28",
    "UMask": "0xF",
    "EventName": "L1D_WB_L2.MESI",
    "BriefDescription": "All L1 writebacks to L2",
    "PublicDescription": "All L1 writebacks to L2",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x28",
    "UMask": "0x2",
    "EventName": "L1D_WB_L2.S_STATE",
    "BriefDescription": "L1 writebacks to L2 in S state",
    "PublicDescription": "L1 writebacks to L2 in S state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x80",
    "UMask": "0x4",
    "EventName": "L1I.CYCLES_STALLED",
    "BriefDescription": "L1I instruction fetch stall cycles",
    "PublicDescription": "L1I instruction fetch stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x80",
    "UMask": "0x1",
    "EventName": "L1I.HITS",
    "BriefDescription": "L1I instruction fetch hits",
    "PublicDescription": "L1I instruction fetch hits",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x80",
    "UMask": "0x2",
    "EventName": "L1I.MISSES",
    "BriefDescription": "L1I instruction fetch misses",
    "PublicDescription": "L1I instruction fetch misses",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x80",
    "UMask": "0x3",
    "EventName": "L1I.READS",
    "BriefDescription": "L1I Instruction fetches",
    "PublicDescription": "L1I Instruction fetches",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x26",
    "UMask": "0xFF",
    "EventName": "L2_DATA_RQSTS.ANY",
    "BriefDescription": "All L2 data requests",
    "PublicDescription": "All L2 data requests",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x26",
    "UMask": "0x4",
    "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
    "BriefDescription": "L2 data demand loads in E state",
    "PublicDescription": "L2 data demand loads in E state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x26",
    "UMask": "0x1",
    "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
    "BriefDescription": "L2 data demand loads in I state (misses)",
    "PublicDescription": "L2 data demand loads in I state (misses)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x26",
    "UMask": "0x8",
    "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
    "BriefDescription": "L2 data demand loads in M state",
    "PublicDescription": "L2 data demand loads in M state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x26",
    "UMask": "0xF",
    "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
    "BriefDescription": "L2 data demand requests",
    "PublicDescription": "L2 data demand requests",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x26",
    "UMask": "0x2",
    "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
    "BriefDescription": "L2 data demand loads in S state",
    "PublicDescription": "L2 data demand loads in S state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x26",
    "UMask": "0x40",
    "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
    "BriefDescription": "L2 data prefetches in E state",
    "PublicDescription": "L2 data prefetches in E state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x26",
    "UMask": "0x10",
    "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
    "BriefDescription": "L2 data prefetches in the I state (misses)",
    "PublicDescription": "L2 data prefetches in the I state (misses)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x26",
    "UMask": "0x80",
    "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
    "BriefDescription": "L2 data prefetches in M state",
    "PublicDescription": "L2 data prefetches in M state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x26",
    "UMask": "0xF0",
    "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
    "BriefDescription": "All L2 data prefetches",
    "PublicDescription": "All L2 data prefetches",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x26",
    "UMask": "0x20",
    "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
    "BriefDescription": "L2 data prefetches in the S state",
    "PublicDescription": "L2 data prefetches in the S state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF1",
    "UMask": "0x7",
    "EventName": "L2_LINES_IN.ANY",
    "BriefDescription": "L2 lines alloacated",
    "PublicDescription": "L2 lines alloacated",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF1",
    "UMask": "0x4",
    "EventName": "L2_LINES_IN.E_STATE",
    "BriefDescription": "L2 lines allocated in the E state",
    "PublicDescription": "L2 lines allocated in the E state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF1",
    "UMask": "0x2",
    "EventName": "L2_LINES_IN.S_STATE",
    "BriefDescription": "L2 lines allocated in the S state",
    "PublicDescription": "L2 lines allocated in the S state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF2",
    "UMask": "0xF",
    "EventName": "L2_LINES_OUT.ANY",
    "BriefDescription": "L2 lines evicted",
    "PublicDescription": "L2 lines evicted",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF2",
    "UMask": "0x1",
    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
    "BriefDescription": "L2 lines evicted by a demand request",
    "PublicDescription": "L2 lines evicted by a demand request",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF2",
    "UMask": "0x2",
    "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
    "BriefDescription": "L2 modified lines evicted by a demand request",
    "PublicDescription": "L2 modified lines evicted by a demand request",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF2",
    "UMask": "0x4",
    "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
    "BriefDescription": "L2 lines evicted by a prefetch request",
    "PublicDescription": "L2 lines evicted by a prefetch request",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF2",
    "UMask": "0x8",
    "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
    "BriefDescription": "L2 modified lines evicted by a prefetch request",
    "PublicDescription": "L2 modified lines evicted by a prefetch request",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x10",
    "EventName": "L2_RQSTS.IFETCH_HIT",
    "BriefDescription": "L2 instruction fetch hits",
    "PublicDescription": "L2 instruction fetch hits",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x20",
    "EventName": "L2_RQSTS.IFETCH_MISS",
    "BriefDescription": "L2 instruction fetch misses",
    "PublicDescription": "L2 instruction fetch misses",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x30",
    "EventName": "L2_RQSTS.IFETCHES",
    "BriefDescription": "L2 instruction fetches",
    "PublicDescription": "L2 instruction fetches",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x1",
    "EventName": "L2_RQSTS.LD_HIT",
    "BriefDescription": "L2 load hits",
    "PublicDescription": "L2 load hits",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x2",
    "EventName": "L2_RQSTS.LD_MISS",
    "BriefDescription": "L2 load misses",
    "PublicDescription": "L2 load misses",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x3",
    "EventName": "L2_RQSTS.LOADS",
    "BriefDescription": "L2 requests",
    "PublicDescription": "L2 requests",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xAA",
    "EventName": "L2_RQSTS.MISS",
    "BriefDescription": "All L2 misses",
    "PublicDescription": "All L2 misses",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x40",
    "EventName": "L2_RQSTS.PREFETCH_HIT",
    "BriefDescription": "L2 prefetch hits",
    "PublicDescription": "L2 prefetch hits",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x80",
    "EventName": "L2_RQSTS.PREFETCH_MISS",
    "BriefDescription": "L2 prefetch misses",
    "PublicDescription": "L2 prefetch misses",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xC0",
    "EventName": "L2_RQSTS.PREFETCHES",
    "BriefDescription": "All L2 prefetches",
    "PublicDescription": "All L2 prefetches",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xFF",
    "EventName": "L2_RQSTS.REFERENCES",
    "BriefDescription": "All L2 requests",
    "PublicDescription": "All L2 requests",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x4",
    "EventName": "L2_RQSTS.RFO_HIT",
    "BriefDescription": "L2 RFO hits",
    "PublicDescription": "L2 RFO hits",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x8",
    "EventName": "L2_RQSTS.RFO_MISS",
    "BriefDescription": "L2 RFO misses",
    "PublicDescription": "L2 RFO misses",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xC",
    "EventName": "L2_RQSTS.RFOS",
    "BriefDescription": "L2 RFO requests",
    "PublicDescription": "L2 RFO requests",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x80",
    "EventName": "L2_TRANSACTIONS.ANY",
    "BriefDescription": "All L2 transactions",
    "PublicDescription": "All L2 transactions",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x20",
    "EventName": "L2_TRANSACTIONS.FILL",
    "BriefDescription": "L2 fill transactions",
    "PublicDescription": "L2 fill transactions",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x4",
    "EventName": "L2_TRANSACTIONS.IFETCH",
    "BriefDescription": "L2 instruction fetch transactions",
    "PublicDescription": "L2 instruction fetch transactions",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x10",
    "EventName": "L2_TRANSACTIONS.L1D_WB",
    "BriefDescription": "L1D writeback to L2 transactions",
    "PublicDescription": "L1D writeback to L2 transactions",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x1",
    "EventName": "L2_TRANSACTIONS.LOAD",
    "BriefDescription": "L2 Load transactions",
    "PublicDescription": "L2 Load transactions",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x8",
    "EventName": "L2_TRANSACTIONS.PREFETCH",
    "BriefDescription": "L2 prefetch transactions",
    "PublicDescription": "L2 prefetch transactions",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x2",
    "EventName": "L2_TRANSACTIONS.RFO",
    "BriefDescription": "L2 RFO transactions",
    "PublicDescription": "L2 RFO transactions",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x40",
    "EventName": "L2_TRANSACTIONS.WB",
    "BriefDescription": "L2 writeback to LLC transactions",
    "PublicDescription": "L2 writeback to LLC transactions",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x27",
    "UMask": "0x40",
    "EventName": "L2_WRITE.LOCK.E_STATE",
    "BriefDescription": "L2 demand lock RFOs in E state",
    "PublicDescription": "L2 demand lock RFOs in E state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x27",
    "UMask": "0xE0",
    "EventName": "L2_WRITE.LOCK.HIT",
    "BriefDescription": "All demand L2 lock RFOs that hit the cache",
    "PublicDescription": "All demand L2 lock RFOs that hit the cache",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x27",
    "UMask": "0x10",
    "EventName": "L2_WRITE.LOCK.I_STATE",
    "BriefDescription": "L2 demand lock RFOs in I state (misses)",
    "PublicDescription": "L2 demand lock RFOs in I state (misses)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x27",
    "UMask": "0x80",
    "EventName": "L2_WRITE.LOCK.M_STATE",
    "BriefDescription": "L2 demand lock RFOs in M state",
    "PublicDescription": "L2 demand lock RFOs in M state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x27",
    "UMask": "0xF0",
    "EventName": "L2_WRITE.LOCK.MESI",
    "BriefDescription": "All demand L2 lock RFOs",
    "PublicDescription": "All demand L2 lock RFOs",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x27",
    "UMask": "0x20",
    "EventName": "L2_WRITE.LOCK.S_STATE",
    "BriefDescription": "L2 demand lock RFOs in S state",
    "PublicDescription": "L2 demand lock RFOs in S state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x27",
    "UMask": "0xE",
    "EventName": "L2_WRITE.RFO.HIT",
    "BriefDescription": "All L2 demand store RFOs that hit the cache",
    "PublicDescription": "All L2 demand store RFOs that hit the cache",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x27",
    "UMask": "0x1",
    "EventName": "L2_WRITE.RFO.I_STATE",
    "BriefDescription": "L2 demand store RFOs in I state (misses)",
    "PublicDescription": "L2 demand store RFOs in I state (misses)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x27",
    "UMask": "0x8",
    "EventName": "L2_WRITE.RFO.M_STATE",
    "BriefDescription": "L2 demand store RFOs in M state",
    "PublicDescription": "L2 demand store RFOs in M state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x27",
    "UMask": "0xF",
    "EventName": "L2_WRITE.RFO.MESI",
    "BriefDescription": "All L2 demand store RFOs",
    "PublicDescription": "All L2 demand store RFOs",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x27",
    "UMask": "0x2",
    "EventName": "L2_WRITE.RFO.S_STATE",
    "BriefDescription": "L2 demand store RFOs in S state",
    "PublicDescription": "L2 demand store RFOs in S state",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x82",
    "UMask": "0x1",
    "EventName": "LARGE_ITLB.HIT",
    "BriefDescription": "Large ITLB hit",
    "PublicDescription": "Large ITLB hit",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x13",
    "UMask": "0x7",
    "EventName": "LOAD_DISPATCH.ANY",
    "BriefDescription": "All loads dispatched",
    "PublicDescription": "All loads dispatched",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x13",
    "UMask": "0x4",
    "EventName": "LOAD_DISPATCH.MOB",
    "BriefDescription": "Loads dispatched from the MOB",
    "PublicDescription": "Loads dispatched from the MOB",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x13",
    "UMask": "0x1",
    "EventName": "LOAD_DISPATCH.RS",
    "BriefDescription": "Loads dispatched that bypass the MOB",
    "PublicDescription": "Loads dispatched that bypass the MOB",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x13",
    "UMask": "0x2",
    "EventName": "LOAD_DISPATCH.RS_DELAYED",
    "BriefDescription": "Loads dispatched from stage 305",
    "PublicDescription": "Loads dispatched from stage 305",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x4C",
    "UMask": "0x1",
    "EventName": "LOAD_HIT_PRE",
    "BriefDescription": "Load operations conflicting with software prefetches",
    "PublicDescription": "Load operations conflicting with software prefetches",
    "Counter": "0,1",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x2E",
    "UMask": "0x41",
    "EventName": "LONGEST_LAT_CACHE.MISS",
    "BriefDescription": "Longest latency cache miss",
    "PublicDescription": "Longest latency cache miss",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x2E",
    "UMask": "0x4F",
    "EventName": "LONGEST_LAT_CACHE.REFERENCE",
    "BriefDescription": "Longest latency cache reference",
    "PublicDescription": "Longest latency cache reference",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA8",
    "UMask": "0x1",
    "EventName": "LSD.ACTIVE",
    "BriefDescription": "Cycles when uops were delivered by the LSD",
    "PublicDescription": "Cycles when uops were delivered by the LSD",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA8",
    "UMask": "0x1",
    "EventName": "LSD.INACTIVE",
    "BriefDescription": "Cycles no uops were delivered by the LSD",
    "PublicDescription": "Cycles no uops were delivered by the LSD",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x20",
    "UMask": "0x1",
    "EventName": "LSD_OVERFLOW",
    "BriefDescription": "Loops that can't stream from the instruction queue",
    "PublicDescription": "Loops that can't stream from the instruction queue",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC3",
    "UMask": "0x1",
    "EventName": "MACHINE_CLEARS.CYCLES",
    "BriefDescription": "Cycles machine clear asserted",
    "PublicDescription": "Cycles machine clear asserted",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC3",
    "UMask": "0x2",
    "EventName": "MACHINE_CLEARS.MEM_ORDER",
    "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
    "PublicDescription": "Execution pipeline restart due to Memory ordering conflicts",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC3",
    "UMask": "0x4",
    "EventName": "MACHINE_CLEARS.SMC",
    "BriefDescription": "Self-Modifying Code detected",
    "PublicDescription": "Self-Modifying Code detected",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD0",
    "UMask": "0x1",
    "EventName": "MACRO_INSTS.DECODED",
    "BriefDescription": "Instructions decoded",
    "PublicDescription": "Instructions decoded",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA6",
    "UMask": "0x1",
    "EventName": "MACRO_INSTS.FUSIONS_DECODED",
    "BriefDescription": "Macro-fused instructions decoded",
    "PublicDescription": "Macro-fused instructions decoded",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x1",
    "EventName": "MEM_INST_RETIRED.LOADS",
    "BriefDescription": "Instructions retired which contains a load (Precise Event)",
    "PublicDescription": "Instructions retired which contains a load (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x2",
    "EventName": "MEM_INST_RETIRED.STORES",
    "BriefDescription": "Instructions retired which contains a store (Precise Event)",
    "PublicDescription": "Instructions retired which contains a store (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCB",
    "UMask": "0x80",
    "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
    "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
    "PublicDescription": "Retired loads that miss the DTLB (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCB",
    "UMask": "0x40",
    "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
    "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
    "PublicDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCB",
    "UMask": "0x1",
    "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
    "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
    "PublicDescription": "Retired loads that hit the L1 data cache (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCB",
    "UMask": "0x2",
    "EventName": "MEM_LOAD_RETIRED.L2_HIT",
    "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
    "PublicDescription": "Retired loads that hit the L2 cache (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCB",
    "UMask": "0x10",
    "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
    "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
    "PublicDescription": "Retired loads that miss the LLC cache (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "10000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCB",
    "UMask": "0x4",
    "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
    "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
    "PublicDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "40000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCB",
    "UMask": "0x8",
    "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
    "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
    "PublicDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "40000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC",
    "UMask": "0x1",
    "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
    "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
    "PublicDescription": "Retired stores that miss the DTLB (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF",
    "UMask": "0x20",
    "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM",
    "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",
    "PublicDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "10000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF",
    "UMask": "0x2",
    "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",
    "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
    "PublicDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "40000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF",
    "UMask": "0x8",
    "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",
    "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)",
    "PublicDescription": "Load instructions retired remote cache HIT data source (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF",
    "UMask": "0x10",
    "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
    "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
    "PublicDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "10000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF",
    "UMask": "0x80",
    "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
    "BriefDescription": "Load instructions retired IO (Precise Event)",
    "PublicDescription": "Load instructions retired IO (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "4000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB0",
    "UMask": "0x40",
    "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
    "BriefDescription": "Offcore L1 data cache writebacks",
    "PublicDescription": "Offcore L1 data cache writebacks",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB2",
    "UMask": "0x1",
    "EventName": "OFFCORE_REQUESTS_SQ_FULL",
    "BriefDescription": "Offcore requests blocked due to Super Queue full",
    "PublicDescription": "Offcore requests blocked due to Super Queue full",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x7",
    "UMask": "0x1",
    "EventName": "PARTIAL_ADDRESS_ALIAS",
    "BriefDescription": "False dependencies due to partial address aliasing",
    "PublicDescription": "False dependencies due to partial address aliasing",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD2",
    "UMask": "0xF",
    "EventName": "RAT_STALLS.ANY",
    "BriefDescription": "All RAT stall cycles",
    "PublicDescription": "All RAT stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD2",
    "UMask": "0x1",
    "EventName": "RAT_STALLS.FLAGS",
    "BriefDescription": "Flag stall cycles",
    "PublicDescription": "Flag stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD2",
    "UMask": "0x2",
    "EventName": "RAT_STALLS.REGISTERS",
    "BriefDescription": "Partial register stall cycles",
    "PublicDescription": "Partial register stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD2",
    "UMask": "0x4",
    "EventName": "RAT_STALLS.ROB_READ_PORT",
    "BriefDescription": "ROB read port stalls cycles",
    "PublicDescription": "ROB read port stalls cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD2",
    "UMask": "0x8",
    "EventName": "RAT_STALLS.SCOREBOARD",
    "BriefDescription": "Scoreboard stall cycles",
    "PublicDescription": "Scoreboard stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA2",
    "UMask": "0x1",
    "EventName": "RESOURCE_STALLS.ANY",
    "BriefDescription": "Resource related stall cycles",
    "PublicDescription": "Resource related stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA2",
    "UMask": "0x20",
    "EventName": "RESOURCE_STALLS.FPCW",
    "BriefDescription": "FPU control word write stall cycles",
    "PublicDescription": "FPU control word write stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA2",
    "UMask": "0x2",
    "EventName": "RESOURCE_STALLS.LOAD",
    "BriefDescription": "Load buffer stall cycles",
    "PublicDescription": "Load buffer stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA2",
    "UMask": "0x40",
    "EventName": "RESOURCE_STALLS.MXCSR",
    "BriefDescription": "MXCSR rename stall cycles",
    "PublicDescription": "MXCSR rename stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA2",
    "UMask": "0x80",
    "EventName": "RESOURCE_STALLS.OTHER",
    "BriefDescription": "Other Resource related stall cycles",
    "PublicDescription": "Other Resource related stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA2",
    "UMask": "0x10",
    "EventName": "RESOURCE_STALLS.ROB_FULL",
    "BriefDescription": "ROB full stall cycles",
    "PublicDescription": "ROB full stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA2",
    "UMask": "0x4",
    "EventName": "RESOURCE_STALLS.RS_FULL",
    "BriefDescription": "Reservation Station full stall cycles",
    "PublicDescription": "Reservation Station full stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA2",
    "UMask": "0x8",
    "EventName": "RESOURCE_STALLS.STORE",
    "BriefDescription": "Store buffer stall cycles",
    "PublicDescription": "Store buffer stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x4",
    "UMask": "0x7",
    "EventName": "SB_DRAIN.ANY",
    "BriefDescription": "All Store buffer stall cycles",
    "PublicDescription": "All Store buffer stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD4",
    "UMask": "0x1",
    "EventName": "SEG_RENAME_STALLS",
    "BriefDescription": "Segment rename stall cycles",
    "PublicDescription": "Segment rename stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x12",
    "UMask": "0x4",
    "EventName": "SIMD_INT_128.PACK",
    "BriefDescription": "128 bit SIMD integer pack operations",
    "PublicDescription": "128 bit SIMD integer pack operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x12",
    "UMask": "0x20",
    "EventName": "SIMD_INT_128.PACKED_ARITH",
    "BriefDescription": "128 bit SIMD integer arithmetic operations",
    "PublicDescription": "128 bit SIMD integer arithmetic operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x12",
    "UMask": "0x10",
    "EventName": "SIMD_INT_128.PACKED_LOGICAL",
    "BriefDescription": "128 bit SIMD integer logical operations",
    "PublicDescription": "128 bit SIMD integer logical operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x12",
    "UMask": "0x1",
    "EventName": "SIMD_INT_128.PACKED_MPY",
    "BriefDescription": "128 bit SIMD integer multiply operations",
    "PublicDescription": "128 bit SIMD integer multiply operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x12",
    "UMask": "0x2",
    "EventName": "SIMD_INT_128.PACKED_SHIFT",
    "BriefDescription": "128 bit SIMD integer shift operations",
    "PublicDescription": "128 bit SIMD integer shift operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x12",
    "UMask": "0x40",
    "EventName": "SIMD_INT_128.SHUFFLE_MOVE",
    "BriefDescription": "128 bit SIMD integer shuffle/move operations",
    "PublicDescription": "128 bit SIMD integer shuffle/move operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x12",
    "UMask": "0x8",
    "EventName": "SIMD_INT_128.UNPACK",
    "BriefDescription": "128 bit SIMD integer unpack operations",
    "PublicDescription": "128 bit SIMD integer unpack operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xFD",
    "UMask": "0x4",
    "EventName": "SIMD_INT_64.PACK",
    "BriefDescription": "SIMD integer 64 bit pack operations",
    "PublicDescription": "SIMD integer 64 bit pack operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xFD",
    "UMask": "0x20",
    "EventName": "SIMD_INT_64.PACKED_ARITH",
    "BriefDescription": "SIMD integer 64 bit arithmetic operations",
    "PublicDescription": "SIMD integer 64 bit arithmetic operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xFD",
    "UMask": "0x10",
    "EventName": "SIMD_INT_64.PACKED_LOGICAL",
    "BriefDescription": "SIMD integer 64 bit logical operations",
    "PublicDescription": "SIMD integer 64 bit logical operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xFD",
    "UMask": "0x1",
    "EventName": "SIMD_INT_64.PACKED_MPY",
    "BriefDescription": "SIMD integer 64 bit packed multiply operations",
    "PublicDescription": "SIMD integer 64 bit packed multiply operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xFD",
    "UMask": "0x2",
    "EventName": "SIMD_INT_64.PACKED_SHIFT",
    "BriefDescription": "SIMD integer 64 bit shift operations",
    "PublicDescription": "SIMD integer 64 bit shift operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xFD",
    "UMask": "0x40",
    "EventName": "SIMD_INT_64.SHUFFLE_MOVE",
    "BriefDescription": "SIMD integer 64 bit shuffle/move operations",
    "PublicDescription": "SIMD integer 64 bit shuffle/move operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xFD",
    "UMask": "0x8",
    "EventName": "SIMD_INT_64.UNPACK",
    "BriefDescription": "SIMD integer 64 bit unpack operations",
    "PublicDescription": "SIMD integer 64 bit unpack operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB8",
    "UMask": "0x1",
    "EventName": "SNOOP_RESPONSE.HIT",
    "BriefDescription": "Thread responded HIT to snoop",
    "PublicDescription": "Thread responded HIT to snoop",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB8",
    "UMask": "0x2",
    "EventName": "SNOOP_RESPONSE.HITE",
    "BriefDescription": "Thread responded HITE to snoop",
    "PublicDescription": "Thread responded HITE to snoop",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB8",
    "UMask": "0x4",
    "EventName": "SNOOP_RESPONSE.HITM",
    "BriefDescription": "Thread responded HITM to snoop",
    "PublicDescription": "Thread responded HITM to snoop",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "100000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF6",
    "UMask": "0x1",
    "EventName": "SQ_FULL_STALL_CYCLES",
    "BriefDescription": "Super Queue full stall cycles",
    "PublicDescription": "Super Queue full stall cycles",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF4",
    "UMask": "0x10",
    "EventName": "SQ_MISC.SPLIT_LOCK",
    "BriefDescription": "Super Queue lock splits across a cache line",
    "PublicDescription": "Super Queue lock splits across a cache line",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x4",
    "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
    "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
    "PublicDescription": "SIMD Packed-Double Uops retired (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x1",
    "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
    "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
    "PublicDescription": "SIMD Packed-Single Uops retired (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x8",
    "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
    "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
    "PublicDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x2",
    "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
    "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
    "PublicDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x10",
    "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
    "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
    "PublicDescription": "SIMD Vector Integer Uops retired (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0x6",
    "UMask": "0x4",
    "EventName": "STORE_BLOCKS.AT_RET",
    "BriefDescription": "Loads delayed with at-Retirement block code",
    "PublicDescription": "Loads delayed with at-Retirement block code",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x6",
    "UMask": "0x8",
    "EventName": "STORE_BLOCKS.L1D_BLOCK",
    "BriefDescription": "Cacheable loads delayed with L1D block code",
    "PublicDescription": "Cacheable loads delayed with L1D block code",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "200000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x19",
    "UMask": "0x1",
    "EventName": "TWO_UOP_INSTS_DECODED",
    "BriefDescription": "Two Uop instructions decoded",
    "PublicDescription": "Two Uop instructions decoded",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xDB",
    "UMask": "0x1",
    "EventName": "UOP_UNFUSION",
    "BriefDescription": "Uop unfusions due to FP exceptions",
    "PublicDescription": "Uop unfusions due to FP exceptions",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD1",
    "UMask": "0x4",
    "EventName": "UOPS_DECODED.ESP_FOLDING",
    "BriefDescription": "Stack pointer instructions decoded",
    "PublicDescription": "Stack pointer instructions decoded",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD1",
    "UMask": "0x8",
    "EventName": "UOPS_DECODED.ESP_SYNC",
    "BriefDescription": "Stack pointer sync operations",
    "PublicDescription": "Stack pointer sync operations",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD1",
    "UMask": "0x2",
    "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
    "BriefDescription": "Uops decoded by Microcode Sequencer",
    "PublicDescription": "Uops decoded by Microcode Sequencer",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD1",
    "UMask": "0x1",
    "EventName": "UOPS_DECODED.STALL_CYCLES",
    "BriefDescription": "Cycles no Uops are decoded",
    "PublicDescription": "Cycles no Uops are decoded",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x3F",
    "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
    "BriefDescription": "Cycles Uops executed on any port (core count)",
    "PublicDescription": "Cycles Uops executed on any port (core count)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x1F",
    "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
    "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
    "PublicDescription": "Cycles Uops executed on ports 0-4 (core count)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x3F",
    "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
    "BriefDescription": "Uops executed on any port (core count)",
    "PublicDescription": "Uops executed on any port (core count)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "1",
    "EdgeDetect": "1",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x1F",
    "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
    "BriefDescription": "Uops executed on ports 0-4 (core count)",
    "PublicDescription": "Uops executed on ports 0-4 (core count)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "1",
    "EdgeDetect": "1",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x3F",
    "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
    "BriefDescription": "Cycles no Uops issued on any port (core count)",
    "PublicDescription": "Cycles no Uops issued on any port (core count)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x1F",
    "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
    "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
    "PublicDescription": "Cycles no Uops issued on ports 0-4 (core count)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x1",
    "EventName": "UOPS_EXECUTED.PORT0",
    "BriefDescription": "Uops executed on port 0",
    "PublicDescription": "Uops executed on port 0",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x40",
    "EventName": "UOPS_EXECUTED.PORT015",
    "BriefDescription": "Uops issued on ports 0, 1 or 5",
    "PublicDescription": "Uops issued on ports 0, 1 or 5",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x40",
    "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
    "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
    "PublicDescription": "Cycles no Uops issued on ports 0, 1 or 5",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x2",
    "EventName": "UOPS_EXECUTED.PORT1",
    "BriefDescription": "Uops executed on port 1",
    "PublicDescription": "Uops executed on port 1",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x4",
    "EventName": "UOPS_EXECUTED.PORT2_CORE",
    "BriefDescription": "Uops executed on port 2 (core count)",
    "PublicDescription": "Uops executed on port 2 (core count)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x80",
    "EventName": "UOPS_EXECUTED.PORT234_CORE",
    "BriefDescription": "Uops issued on ports 2, 3 or 4",
    "PublicDescription": "Uops issued on ports 2, 3 or 4",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x8",
    "EventName": "UOPS_EXECUTED.PORT3_CORE",
    "BriefDescription": "Uops executed on port 3 (core count)",
    "PublicDescription": "Uops executed on port 3 (core count)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x10",
    "EventName": "UOPS_EXECUTED.PORT4_CORE",
    "BriefDescription": "Uops executed on port 4 (core count)",
    "PublicDescription": "Uops executed on port 4 (core count)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x20",
    "EventName": "UOPS_EXECUTED.PORT5",
    "BriefDescription": "Uops executed on port 5",
    "PublicDescription": "Uops executed on port 5",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xE",
    "UMask": "0x1",
    "EventName": "UOPS_ISSUED.ANY",
    "BriefDescription": "Uops issued",
    "PublicDescription": "Uops issued",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xE",
    "UMask": "0x1",
    "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
    "BriefDescription": "Cycles no Uops were issued on any thread",
    "PublicDescription": "Cycles no Uops were issued on any thread",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xE",
    "UMask": "0x1",
    "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
    "BriefDescription": "Cycles Uops were issued on either thread",
    "PublicDescription": "Cycles Uops were issued on either thread",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xE",
    "UMask": "0x2",
    "EventName": "UOPS_ISSUED.FUSED",
    "BriefDescription": "Fused Uops issued",
    "PublicDescription": "Fused Uops issued",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xE",
    "UMask": "0x1",
    "EventName": "UOPS_ISSUED.STALL_CYCLES",
    "BriefDescription": "Cycles no Uops were issued",
    "PublicDescription": "Cycles no Uops were issued",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC2",
    "UMask": "0x1",
    "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
    "BriefDescription": "Cycles Uops are being retired",
    "PublicDescription": "Cycles Uops are being retired",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC2",
    "UMask": "0x1",
    "EventName": "UOPS_RETIRED.ANY",
    "BriefDescription": "Uops retired (Precise Event)",
    "PublicDescription": "Uops retired (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC2",
    "UMask": "0x4",
    "EventName": "UOPS_RETIRED.MACRO_FUSED",
    "BriefDescription": "Macro-fused Uops retired (Precise Event)",
    "PublicDescription": "Macro-fused Uops retired (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC2",
    "UMask": "0x2",
    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
    "BriefDescription": "Retirement slots used (Precise Event)",
    "PublicDescription": "Retirement slots used (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC2",
    "UMask": "0x1",
    "EventName": "UOPS_RETIRED.STALL_CYCLES",
    "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
    "PublicDescription": "Cycles Uops are not retiring (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC2",
    "UMask": "0x1",
    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
    "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
    "PublicDescription": "Total cycles using precise uop retired event (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "16",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC0",
    "UMask": "0x1",
    "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
    "BriefDescription": "Total cycles (Precise Event)",
    "PublicDescription": "Total cycles (Precise Event)",
    "Counter": "0,1,2,3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0",
    "MSRValue": "0",
    "CounterMask": "16",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
    "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 0 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "2000000",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
    "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "100",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x400",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
    "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 128 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "1000",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x80",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
    "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 16 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "10000",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x10",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
    "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "5",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x4000",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
    "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "50",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x800",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
    "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 256 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "500",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x100",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
    "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 32 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "5000",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x20",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
    "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "3",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x8000",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
    "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 4 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "50000",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x4",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
    "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "20",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x1000",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
    "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 512 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "200",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x200",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
    "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 64 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "2000",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x40",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
    "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 8 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "20000",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x8",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB",
    "UMask": "0x10",
    "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
    "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
    "PublicDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
    "Counter": "3",
    "SampleAfterValue": "10",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x2000",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Offcore": "0"
  }
,
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
    "PublicDescription": "Offcore data reads satisfied by any cache or DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F11",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_DRAM",
    "BriefDescription": "Offcore data reads satisfied by any DRAM",
    "PublicDescription": "Offcore data reads satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6011",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_LLC_MISS",
    "BriefDescription": "Offcore data reads that missed the LLC",
    "PublicDescription": "Offcore data reads that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF811",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.ANY_LOCATION",
    "BriefDescription": "All offcore data reads",
    "PublicDescription": "All offcore data reads",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF11",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.IO_CSR_MMIO",
    "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
    "PublicDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8011",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x111",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x211",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x411",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE",
    "BriefDescription": "Offcore data reads satisfied by the LLC",
    "PublicDescription": "Offcore data reads satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x711",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore data reads satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4711",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_DRAM",
    "BriefDescription": "Offcore data reads satisfied by the local DRAM",
    "PublicDescription": "Offcore data reads satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4011",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE",
    "BriefDescription": "Offcore data reads satisfied by a remote cache",
    "PublicDescription": "Offcore data reads satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1811",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3811",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore data reads that HIT in a remote cache",
    "PublicDescription": "Offcore data reads that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1011",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore data reads that HITM in a remote cache",
    "PublicDescription": "Offcore data reads that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x811",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_DRAM",
    "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
    "PublicDescription": "Offcore data reads satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2011",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
    "PublicDescription": "Offcore code reads satisfied by any cache or DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F44",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_DRAM",
    "BriefDescription": "Offcore code reads satisfied by any DRAM",
    "PublicDescription": "Offcore code reads satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6044",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LLC_MISS",
    "BriefDescription": "Offcore code reads that missed the LLC",
    "PublicDescription": "Offcore code reads that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF844",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LOCATION",
    "BriefDescription": "All offcore code reads",
    "PublicDescription": "All offcore code reads",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF44",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.IO_CSR_MMIO",
    "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
    "PublicDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8044",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x144",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x244",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x444",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE",
    "BriefDescription": "Offcore code reads satisfied by the LLC",
    "PublicDescription": "Offcore code reads satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x744",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore code reads satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4744",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_DRAM",
    "BriefDescription": "Offcore code reads satisfied by the local DRAM",
    "PublicDescription": "Offcore code reads satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4044",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE",
    "BriefDescription": "Offcore code reads satisfied by a remote cache",
    "PublicDescription": "Offcore code reads satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1844",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3844",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore code reads that HIT in a remote cache",
    "PublicDescription": "Offcore code reads that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1044",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore code reads that HITM in a remote cache",
    "PublicDescription": "Offcore code reads that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x844",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_DRAM",
    "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
    "PublicDescription": "Offcore code reads satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2044",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore requests satisfied by any cache or DRAM",
    "PublicDescription": "Offcore requests satisfied by any cache or DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7FFF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_DRAM",
    "BriefDescription": "Offcore requests satisfied by any DRAM",
    "PublicDescription": "Offcore requests satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x60FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LLC_MISS",
    "BriefDescription": "Offcore requests that missed the LLC",
    "PublicDescription": "Offcore requests that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF8FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LOCATION",
    "BriefDescription": "All offcore requests",
    "PublicDescription": "All offcore requests",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFFFF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.IO_CSR_MMIO",
    "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
    "PublicDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x80FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE",
    "BriefDescription": "Offcore requests satisfied by the LLC",
    "PublicDescription": "Offcore requests satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore requests satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x47FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_DRAM",
    "BriefDescription": "Offcore requests satisfied by the local DRAM",
    "PublicDescription": "Offcore requests satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x40FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE",
    "BriefDescription": "Offcore requests satisfied by a remote cache",
    "PublicDescription": "Offcore requests satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x18FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x38FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore requests that HIT in a remote cache",
    "PublicDescription": "Offcore requests that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x10FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore requests that HITM in a remote cache",
    "PublicDescription": "Offcore requests that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_DRAM",
    "BriefDescription": "Offcore requests satisfied by a remote DRAM",
    "PublicDescription": "Offcore requests satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x20FF",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
    "PublicDescription": "Offcore RFO requests satisfied by any cache or DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F22",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_DRAM",
    "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
    "PublicDescription": "Offcore RFO requests satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6022",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS",
    "BriefDescription": "Offcore RFO requests that missed the LLC",
    "PublicDescription": "Offcore RFO requests that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF822",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.ANY_LOCATION",
    "BriefDescription": "All offcore RFO requests",
    "PublicDescription": "All offcore RFO requests",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF22",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.IO_CSR_MMIO",
    "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
    "PublicDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8022",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x122",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x222",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x422",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE",
    "BriefDescription": "Offcore RFO requests satisfied by the LLC",
    "PublicDescription": "Offcore RFO requests satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x722",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4722",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_DRAM",
    "BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
    "PublicDescription": "Offcore RFO requests satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4022",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE",
    "BriefDescription": "Offcore RFO requests satisfied by a remote cache",
    "PublicDescription": "Offcore RFO requests satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1822",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3822",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore RFO requests that HIT in a remote cache",
    "PublicDescription": "Offcore RFO requests that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1022",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore RFO requests that HITM in a remote cache",
    "PublicDescription": "Offcore RFO requests that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x822",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_DRAM",
    "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
    "PublicDescription": "Offcore RFO requests satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2022",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore writebacks to any cache or DRAM.",
    "PublicDescription": "Offcore writebacks to any cache or DRAM.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F08",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_DRAM",
    "BriefDescription": "Offcore writebacks to any DRAM",
    "PublicDescription": "Offcore writebacks to any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6008",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_LLC_MISS",
    "BriefDescription": "Offcore writebacks that missed the LLC",
    "PublicDescription": "Offcore writebacks that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF808",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.ANY_LOCATION",
    "BriefDescription": "All offcore writebacks",
    "PublicDescription": "All offcore writebacks",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF08",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.IO_CSR_MMIO",
    "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
    "PublicDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8008",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
    "PublicDescription": "Offcore writebacks to the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x108",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x408",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE",
    "BriefDescription": "Offcore writebacks to the LLC",
    "PublicDescription": "Offcore writebacks to the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x708",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore writebacks to the LLC or local DRAM",
    "PublicDescription": "Offcore writebacks to the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4708",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.LOCAL_DRAM",
    "BriefDescription": "Offcore writebacks to the local DRAM",
    "PublicDescription": "Offcore writebacks to the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4008",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE",
    "BriefDescription": "Offcore writebacks to a remote cache",
    "PublicDescription": "Offcore writebacks to a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1808",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
    "PublicDescription": "Offcore writebacks to a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3808",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore writebacks that HIT in a remote cache",
    "PublicDescription": "Offcore writebacks that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1008",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore writebacks that HITM in a remote cache",
    "PublicDescription": "Offcore writebacks that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x808",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.COREWB.REMOTE_DRAM",
    "BriefDescription": "Offcore writebacks to a remote DRAM",
    "PublicDescription": "Offcore writebacks to a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2008",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
    "PublicDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F77",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_DRAM",
    "BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
    "PublicDescription": "Offcore code or data read requests satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6077",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LLC_MISS",
    "BriefDescription": "Offcore code or data read requests that missed the LLC",
    "PublicDescription": "Offcore code or data read requests that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF877",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LOCATION",
    "BriefDescription": "All offcore code or data read requests",
    "PublicDescription": "All offcore code or data read requests",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF77",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.IO_CSR_MMIO",
    "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
    "PublicDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8077",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x177",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x277",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x477",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE",
    "BriefDescription": "Offcore code or data read requests satisfied by the LLC",
    "PublicDescription": "Offcore code or data read requests satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x777",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4777",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_DRAM",
    "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
    "PublicDescription": "Offcore code or data read requests satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4077",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE",
    "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
    "PublicDescription": "Offcore code or data read requests satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1877",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3877",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
    "PublicDescription": "Offcore code or data read requests that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1077",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
    "PublicDescription": "Offcore code or data read requests that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x877",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_DRAM",
    "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
    "PublicDescription": "Offcore code or data read requests satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2077",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore request = all data, response = any cache_dram",
    "PublicDescription": "Offcore request = all data, response = any cache_dram",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F33",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_DRAM",
    "BriefDescription": "Offcore request = all data, response = any DRAM",
    "PublicDescription": "Offcore request = all data, response = any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6033",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_LLC_MISS",
    "BriefDescription": "Offcore request = all data, response = any LLC miss",
    "PublicDescription": "Offcore request = all data, response = any LLC miss",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF833",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.ANY_LOCATION",
    "BriefDescription": "Offcore request = all data, response = any location",
    "PublicDescription": "Offcore request = all data, response = any location",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF33",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.IO_CSR_MMIO",
    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit",
    "PublicDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8033",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x133",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x233",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x433",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE",
    "BriefDescription": "Offcore request = all data, response = local cache",
    "PublicDescription": "Offcore request = all data, response = local cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x733",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore request = all data, response = local cache or dram",
    "PublicDescription": "Offcore request = all data, response = local cache or dram",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4733",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.LOCAL_DRAM",
    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.",
    "PublicDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4033",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE",
    "BriefDescription": "Offcore request = all data, response = remote cache",
    "PublicDescription": "Offcore request = all data, response = remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1833",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore request = all data, response = remote cache or dram",
    "PublicDescription": "Offcore request = all data, response = remote cache or dram",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3833",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ",
    "PublicDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1033",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache",
    "PublicDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x833",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DATA_IN.REMOTE_DRAM",
    "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM",
    "PublicDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2033",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
    "PublicDescription": "Offcore demand data requests satisfied by any cache or DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F03",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_DRAM",
    "BriefDescription": "Offcore demand data requests satisfied by any DRAM",
    "PublicDescription": "Offcore demand data requests satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6003",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LLC_MISS",
    "BriefDescription": "Offcore demand data requests that missed the LLC",
    "PublicDescription": "Offcore demand data requests that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF803",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LOCATION",
    "BriefDescription": "All offcore demand data requests",
    "PublicDescription": "All offcore demand data requests",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF03",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.IO_CSR_MMIO",
    "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
    "PublicDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8003",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x103",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x203",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x403",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE",
    "BriefDescription": "Offcore demand data requests satisfied by the LLC",
    "PublicDescription": "Offcore demand data requests satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x703",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4703",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_DRAM",
    "BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
    "PublicDescription": "Offcore demand data requests satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4003",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE",
    "BriefDescription": "Offcore demand data requests satisfied by a remote cache",
    "PublicDescription": "Offcore demand data requests satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1803",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3803",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore demand data requests that HIT in a remote cache",
    "PublicDescription": "Offcore demand data requests that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1003",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore demand data requests that HITM in a remote cache",
    "PublicDescription": "Offcore demand data requests that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x803",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_DRAM",
    "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
    "PublicDescription": "Offcore demand data requests satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2003",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
    "PublicDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F01",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_DRAM",
    "BriefDescription": "Offcore demand data reads satisfied by any DRAM",
    "PublicDescription": "Offcore demand data reads satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6001",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LLC_MISS",
    "BriefDescription": "Offcore demand data reads that missed the LLC",
    "PublicDescription": "Offcore demand data reads that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF801",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LOCATION",
    "BriefDescription": "All offcore demand data reads",
    "PublicDescription": "All offcore demand data reads",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF01",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.IO_CSR_MMIO",
    "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
    "PublicDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8001",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x101",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x201",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x401",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE",
    "BriefDescription": "Offcore demand data reads satisfied by the LLC",
    "PublicDescription": "Offcore demand data reads satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x701",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4701",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_DRAM",
    "BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
    "PublicDescription": "Offcore demand data reads satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4001",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE",
    "BriefDescription": "Offcore demand data reads satisfied by a remote cache",
    "PublicDescription": "Offcore demand data reads satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1801",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3801",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore demand data reads that HIT in a remote cache",
    "PublicDescription": "Offcore demand data reads that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1001",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore demand data reads that HITM in a remote cache",
    "PublicDescription": "Offcore demand data reads that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x801",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_DRAM",
    "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
    "PublicDescription": "Offcore demand data reads satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2001",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
    "PublicDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F04",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_DRAM",
    "BriefDescription": "Offcore demand code reads satisfied by any DRAM",
    "PublicDescription": "Offcore demand code reads satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6004",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LLC_MISS",
    "BriefDescription": "Offcore demand code reads that missed the LLC",
    "PublicDescription": "Offcore demand code reads that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF804",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LOCATION",
    "BriefDescription": "All offcore demand code reads",
    "PublicDescription": "All offcore demand code reads",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF04",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.IO_CSR_MMIO",
    "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
    "PublicDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8004",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x104",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x204",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x404",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE",
    "BriefDescription": "Offcore demand code reads satisfied by the LLC",
    "PublicDescription": "Offcore demand code reads satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x704",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4704",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_DRAM",
    "BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
    "PublicDescription": "Offcore demand code reads satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4004",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE",
    "BriefDescription": "Offcore demand code reads satisfied by a remote cache",
    "PublicDescription": "Offcore demand code reads satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1804",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3804",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore demand code reads that HIT in a remote cache",
    "PublicDescription": "Offcore demand code reads that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1004",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore demand code reads that HITM in a remote cache",
    "PublicDescription": "Offcore demand code reads that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x804",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_DRAM",
    "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
    "PublicDescription": "Offcore demand code reads satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2004",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
    "PublicDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F02",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_DRAM",
    "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
    "PublicDescription": "Offcore demand RFO requests satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6002",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LLC_MISS",
    "BriefDescription": "Offcore demand RFO requests that missed the LLC",
    "PublicDescription": "Offcore demand RFO requests that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF802",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LOCATION",
    "BriefDescription": "All offcore demand RFO requests",
    "PublicDescription": "All offcore demand RFO requests",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF02",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.IO_CSR_MMIO",
    "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
    "PublicDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8002",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x102",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x202",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x402",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE",
    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
    "PublicDescription": "Offcore demand RFO requests satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x702",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4702",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_DRAM",
    "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
    "PublicDescription": "Offcore demand RFO requests satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4002",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE",
    "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
    "PublicDescription": "Offcore demand RFO requests satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1802",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3802",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
    "PublicDescription": "Offcore demand RFO requests that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1002",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
    "PublicDescription": "Offcore demand RFO requests that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x802",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_DRAM",
    "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
    "PublicDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2002",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
    "PublicDescription": "Offcore other requests satisfied by any cache or DRAM.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F80",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_DRAM",
    "BriefDescription": "Offcore other requests satisfied by any DRAM",
    "PublicDescription": "Offcore other requests satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6080",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_LLC_MISS",
    "BriefDescription": "Offcore other requests that missed the LLC",
    "PublicDescription": "Offcore other requests that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF880",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.ANY_LOCATION",
    "BriefDescription": "All offcore other requests",
    "PublicDescription": "All offcore other requests",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF80",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.IO_CSR_MMIO",
    "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
    "PublicDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8080",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x180",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x280",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x480",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE",
    "BriefDescription": "Offcore other requests satisfied by the LLC",
    "PublicDescription": "Offcore other requests satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x780",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore other requests satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4780",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE",
    "BriefDescription": "Offcore other requests satisfied by a remote cache",
    "PublicDescription": "Offcore other requests satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1880",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3880",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore other requests that HIT in a remote cache",
    "PublicDescription": "Offcore other requests that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1080",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore other requests that HITM in a remote cache",
    "PublicDescription": "Offcore other requests that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x880",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.OTHER.REMOTE_DRAM",
    "BriefDescription": "Offcore other requests satisfied by a remote DRAM",
    "PublicDescription": "Offcore other requests satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2080",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
    "PublicDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F30",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_DRAM",
    "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
    "PublicDescription": "Offcore prefetch data requests satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6030",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_LLC_MISS",
    "BriefDescription": "Offcore prefetch data requests that missed the LLC",
    "PublicDescription": "Offcore prefetch data requests that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF830",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.ANY_LOCATION",
    "BriefDescription": "All offcore prefetch data requests",
    "PublicDescription": "All offcore prefetch data requests",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF30",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.IO_CSR_MMIO",
    "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
    "PublicDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8030",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x130",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x230",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x430",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE",
    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
    "PublicDescription": "Offcore prefetch data requests satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x730",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4730",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.LOCAL_DRAM",
    "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
    "PublicDescription": "Offcore prefetch data requests satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4030",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE",
    "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
    "PublicDescription": "Offcore prefetch data requests satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1830",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3830",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
    "PublicDescription": "Offcore prefetch data requests that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1030",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
    "PublicDescription": "Offcore prefetch data requests that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x830",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA.REMOTE_DRAM",
    "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
    "PublicDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2030",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
    "PublicDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F10",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_DRAM",
    "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
    "PublicDescription": "Offcore prefetch data reads satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6010",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LLC_MISS",
    "BriefDescription": "Offcore prefetch data reads that missed the LLC",
    "PublicDescription": "Offcore prefetch data reads that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF810",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LOCATION",
    "BriefDescription": "All offcore prefetch data reads",
    "PublicDescription": "All offcore prefetch data reads",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF10",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.IO_CSR_MMIO",
    "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
    "PublicDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8010",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x110",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x210",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x410",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE",
    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
    "PublicDescription": "Offcore prefetch data reads satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x710",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4710",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_DRAM",
    "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
    "PublicDescription": "Offcore prefetch data reads satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4010",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE",
    "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
    "PublicDescription": "Offcore prefetch data reads satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1810",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3810",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
    "PublicDescription": "Offcore prefetch data reads that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1010",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
    "PublicDescription": "Offcore prefetch data reads that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x810",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_DRAM",
    "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
    "PublicDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2010",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
    "PublicDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F40",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_DRAM",
    "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
    "PublicDescription": "Offcore prefetch code reads satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6040",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LLC_MISS",
    "BriefDescription": "Offcore prefetch code reads that missed the LLC",
    "PublicDescription": "Offcore prefetch code reads that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF840",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LOCATION",
    "BriefDescription": "All offcore prefetch code reads",
    "PublicDescription": "All offcore prefetch code reads",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF40",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.IO_CSR_MMIO",
    "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
    "PublicDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8040",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x140",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x240",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x440",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE",
    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
    "PublicDescription": "Offcore prefetch code reads satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x740",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4740",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_DRAM",
    "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
    "PublicDescription": "Offcore prefetch code reads satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4040",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE",
    "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
    "PublicDescription": "Offcore prefetch code reads satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1840",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3840",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
    "PublicDescription": "Offcore prefetch code reads that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1040",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
    "PublicDescription": "Offcore prefetch code reads that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x840",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_DRAM",
    "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
    "PublicDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2040",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
    "PublicDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F20",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_DRAM",
    "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
    "PublicDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6020",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_LLC_MISS",
    "BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
    "PublicDescription": "Offcore prefetch RFO requests that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF820",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.ANY_LOCATION",
    "BriefDescription": "All offcore prefetch RFO requests",
    "PublicDescription": "All offcore prefetch RFO requests",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF20",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.IO_CSR_MMIO",
    "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
    "PublicDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8020",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x120",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x220",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x420",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE",
    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
    "PublicDescription": "Offcore prefetch RFO requests satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x720",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4720",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.LOCAL_DRAM",
    "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
    "PublicDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4020",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE",
    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
    "PublicDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1820",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3820",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
    "PublicDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1020",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
    "PublicDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x820",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PF_RFO.REMOTE_DRAM",
    "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
    "PublicDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2020",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
    "PublicDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x7F70",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_DRAM",
    "BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
    "PublicDescription": "Offcore prefetch requests satisfied by any DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x6070",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_LLC_MISS",
    "BriefDescription": "Offcore prefetch requests that missed the LLC",
    "PublicDescription": "Offcore prefetch requests that missed the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xF870",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.ANY_LOCATION",
    "BriefDescription": "All offcore prefetch requests",
    "PublicDescription": "All offcore prefetch requests",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0xFF70",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.IO_CSR_MMIO",
    "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
    "PublicDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x8070",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_NO_OTHER_CORE",
    "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
    "PublicDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x170",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
    "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
    "PublicDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x270",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
    "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",
    "PublicDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x470",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE",
    "BriefDescription": "Offcore prefetch requests satisfied by the LLC",
    "PublicDescription": "Offcore prefetch requests satisfied by the LLC",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x770",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
    "PublicDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4770",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.LOCAL_DRAM",
    "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
    "PublicDescription": "Offcore prefetch requests satisfied by the local DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x4070",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE",
    "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
    "PublicDescription": "Offcore prefetch requests satisfied by a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1870",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_DRAM",
    "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
    "PublicDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x3870",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HIT",
    "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
    "PublicDescription": "Offcore prefetch requests that HIT in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x1070",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HITM",
    "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
    "PublicDescription": "Offcore prefetch requests that HITM in a remote cache",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x870",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  },
  {
    "EventCode": "0xB7",
    "UMask": "0x1",
    "EventName": "OFFCORE_RESPONSE_0.PREFETCH.REMOTE_DRAM",
    "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
    "PublicDescription": "Offcore prefetch requests satisfied by a remote DRAM",
    "Counter": "2",
    "SampleAfterValue": "100000",
    "MSRIndex": "0x1A6",
    "MSRValue": "0x2070",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Offcore": "1"
  }
]