# Performance Monitoring Events for the Sixth Generation Intel Core Processors Based on the Skylake Microarchitecture - V42 # 8/6/2018 3:30:52 PM # Copyright (c) 2007 - 2017 Intel Corporation. All rights reserved. MATRIX_REQUEST MATRIX_RESPONSE MATRIX_VALUE MATRIX_REGISTER DESCRIPTION DEMAND_DATA_RD Null 0x0001 0,1 Counts demand data reads DEMAND_RFO Null 0x0002 0,1 Counts all demand data writes (RFOs) DEMAND_CODE_RD Null 0x0004 0,1 Counts all demand code reads OTHER Null 0x8000 0,1 Counts any other requests Null ANY_RESPONSE 0x000001 0,1 have any response type. Null SUPPLIER_NONE.SPL_HIT 0x004002 0,1 tbd Null SUPPLIER_NONE.SNOOP_NONE 0x008002 0,1 tbd Null SUPPLIER_NONE.SNOOP_NOT_NEEDED 0x010002 0,1 tbd Null SUPPLIER_NONE.SNOOP_MISS 0x020002 0,1 tbd Null SUPPLIER_NONE.SNOOP_HIT_NO_FWD 0x040002 0,1 tbd Null SUPPLIER_NONE.SNOOP_HITM 0x100002 0,1 tbd Null SUPPLIER_NONE.SNOOP_NON_DRAM 0x200002 0,1 tbd Null SUPPLIER_NONE.ANY_SNOOP 0x3fc002 0,1 tbd Null L3_HIT_M.SPL_HIT 0x004004 0,1 tbd Null L3_HIT_M.SNOOP_NONE 0x008004 0,1 tbd Null L3_HIT_M.SNOOP_NOT_NEEDED 0x010004 0,1 tbd Null L3_HIT_M.SNOOP_MISS 0x020004 0,1 tbd Null L3_HIT_M.SNOOP_HIT_NO_FWD 0x040004 0,1 tbd Null L3_HIT_M.SNOOP_HITM 0x100004 0,1 tbd Null L3_HIT_M.SNOOP_NON_DRAM 0x200004 0,1 tbd Null L3_HIT_M.ANY_SNOOP 0x3fc004 0,1 tbd Null L3_HIT_E.SPL_HIT 0x004008 0,1 tbd Null L3_HIT_E.SNOOP_NONE 0x008008 0,1 tbd Null L3_HIT_E.SNOOP_NOT_NEEDED 0x010008 0,1 tbd Null L3_HIT_E.SNOOP_MISS 0x020008 0,1 tbd Null L3_HIT_E.SNOOP_HIT_NO_FWD 0x040008 0,1 tbd Null L3_HIT_E.SNOOP_HITM 0x100008 0,1 tbd Null L3_HIT_E.SNOOP_NON_DRAM 0x200008 0,1 tbd Null L3_HIT_E.ANY_SNOOP 0x3fc008 0,1 tbd Null L3_HIT_S.SPL_HIT 0x004010 0,1 tbd Null L3_HIT_S.SNOOP_NONE 0x008010 0,1 tbd Null L3_HIT_S.SNOOP_NOT_NEEDED 0x010010 0,1 tbd Null L3_HIT_S.SNOOP_MISS 0x020010 0,1 tbd Null L3_HIT_S.SNOOP_HIT_NO_FWD 0x040010 0,1 tbd Null L3_HIT_S.SNOOP_HITM 0x100010 0,1 tbd Null L3_HIT_S.SNOOP_NON_DRAM 0x200010 0,1 tbd Null L3_HIT_S.ANY_SNOOP 0x3fc010 0,1 tbd Null L3_HIT.SPL_HIT 0x00401c 0,1 tbd Null L3_HIT.SNOOP_NONE 0x00801c 0,1 tbd Null L3_HIT.SNOOP_NOT_NEEDED 0x01001c 0,1 hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Null L3_HIT.SNOOP_MISS 0x02001c 0,1 hit in the L3 and the snoops sent to sibling cores return clean response. Null L3_HIT.SNOOP_HIT_NO_FWD 0x04001c 0,1 hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Null L3_HIT.SNOOP_HITM 0x10001c 0,1 tbd Null L3_HIT.SNOOP_NON_DRAM 0x20001c 0,1 tbd Null L3_HIT.ANY_SNOOP 0x3fc01c 0,1 tbd Null L4_HIT_LOCAL_L4.SPL_HIT 0x004040 0,1 tbd Null L4_HIT_LOCAL_L4.SNOOP_NONE 0x008040 0,1 tbd Null L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED 0x010040 0,1 tbd Null L4_HIT_LOCAL_L4.SNOOP_MISS 0x020040 0,1 tbd Null L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD 0x040040 0,1 tbd Null L4_HIT_LOCAL_L4.SNOOP_HIT_WITH_FWD 0x080040 0,1 tbd Null L4_HIT_LOCAL_L4.SNOOP_HITM 0x100040 0,1 tbd Null L4_HIT_LOCAL_L4.SNOOP_NON_DRAM 0x200040 0,1 tbd Null L4_HIT_LOCAL_L4.ANY_SNOOP 0x3fc040 0,1 tbd Null L3_MISS_LOCAL_DRAM.SPL_HIT 0x004400 0,1 tbd Null L3_MISS_LOCAL_DRAM.SNOOP_NONE 0x008400 0,1 tbd Null L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED 0x010400 0,1 tbd Null L3_MISS_LOCAL_DRAM.SNOOP_MISS 0x020400 0,1 tbd Null L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD 0x040400 0,1 tbd Null L3_MISS_LOCAL_DRAM.SNOOP_HITM 0x100400 0,1 tbd Null L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM 0x200400 0,1 tbd Null L3_MISS_LOCAL_DRAM.ANY_SNOOP 0x3fc400 0,1 tbd Null L3_MISS.SPL_HIT 0x007c40 0,1 tbd Null L3_MISS.SNOOP_NONE 0x00bc40 0,1 tbd Null L3_MISS.SNOOP_NOT_NEEDED 0x013c40 0,1 tbd Null L3_MISS.SNOOP_MISS 0x023c40 0,1 tbd Null L3_MISS.SNOOP_HIT_NO_FWD 0x043c40 0,1 tbd Null L3_MISS.SNOOP_HITM 0x103c40 0,1 tbd Null L3_MISS.SNOOP_NON_DRAM 0x203c40 0,1 tbd Null L3_MISS.ANY_SNOOP 0x3ffc40 0,1 tbd