# Performance Monitoring Events for Intel Xeon Processors Based on the Skylake Microarchitecture - V1.12
# 8/6/2018 10:15:59 PM
# Copyright (c) 2007 - 2017 Intel Corporation. All rights reserved.
BitName	BitIndex	Type	Description	MATRIX_REG	BitsNotCombinedWith	Errata
DEMAND_DATA_RD	0	1	Counts demand data reads	0,1	na	na
DEMAND_RFO	1	1	Counts all demand data writes (RFOs)	0,1	na	na
DEMAND_CODE_RD	2	1	Counts demand instruction fetches and L1 instruction cache prefetches that	0,1	na	na
PF_L2_DATA_RD	4	1	Counts prefetch (that bring data to L2) data reads	0,1	na	na
PF_L2_RFO	5	1	Counts all prefetch (that bring data to L2) RFOs	0,1	na	na
PF_L3_DATA_RD	7	1	Counts all prefetch (that bring data to LLC only) data reads	0,1	na	na
PF_L3_RFO	8	1	Counts all prefetch (that bring data to LLC only) RFOs	0,1	na	na
PF_L1D_AND_SW	10	1	Counts L1 data cache hardware prefetch requests and software prefetch requests	0,1	na	na
OTHER	15	1	Counts any other requests	0,1	na	na
ALL_PF_DATA_RD	4,7,10	1	TBD	0,1	na	na
ALL_PF_RFO	5,8	1	TBD	0,1	na	na
ALL_DATA_RD	0,4,7,10	1	TBD	0,1	na	na
ALL_RFO	1,5,8	1	TBD	0,1	na	na
ALL_READS	0,1,2,4,5,6,7,8,9,10	1	TBD	0,1	na	na
ANY_RESPONSE	16	2	have any response type.	0,1	na	na
SUPPLIER_NONE	17	3		0,1	na	na
L3_HIT_M	18	3		0,1	na	na
L3_HIT_E	19	3		0,1	na	na
L3_HIT_S	20	3		0,1	na	na
L3_HIT_F	21	3		0,1	na	na
L3_HIT	18,19,20,21	3	TBD	0,1	na	na
L3_MISS_LOCAL_DRAM	26	3		0,1	na	na
L3_MISS_REMOTE_HOP1_DRAM	28	3		0,1	na	na
L3_MISS	26,27,28,29	3	TBD	0,1	na	na
SNOOP_NONE	31	4		0,1	na	na
NO_SNOOP_NEEDED	32	4	TBD	0,1	na	na
SNOOP_MISS	33	4		0,1	na	na
HIT_OTHER_CORE_NO_FWD	34	4	TBD	0,1	na	na
HIT_OTHER_CORE_FWD	35	4	TBD	0,1	18,19,20,21	na
HITM_OTHER_CORE	36	4	TBD	0,1	na	na
ANY_SNOOP	31,32,33,34,35,36,37	4	TBD	0,1	na	na
L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD	23,24,25,27,28,29,33,34	2	TBD	0,1	na	na
L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD	26,33,34	2	TBD	0,1	na	na
L3_HIT.NO_SNOOP_NEEDED	18,19,20,21,32	2	hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.	tbd	na	na
L3_HIT.HIT_OTHER_CORE_NO_FWD	18,19,20,21,34	2	hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	tbd	na	na
L3_HIT.HIT_OTHER_CORE_FWD	18,19,20,21,35	2	hit in the L3 and the snoop to one of the sibling cores hits the line in E/S/F state and the line is forwarded.	tbd	na	na
L3_HIT.HITM_OTHER_CORE	18,19,20,21,36	2	hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.	tbd	na	na
L3_HIT.ANY_SNOOP	18,19,20,21,31,32,33,34,35,36,37	2	hit in the L3.	tbd	na	na
L3_MISS.ANY_SNOOP	26,27,28,29,31,32,33,34,35,36,37	2	miss in the L3.	tbd	na	na
L3_HIT.SNOOP_HIT_WITH_FWD	18, 19, 20, 21, 22, 35	2		0,1	18,19,20,21	na