# Performance Monitoring Events for Intel Atom Processors Based on the Silvermont Microarchitecture - V14
# 3/14/2017 1:13:51 PM
# Copyright (c) 2007 - 2016 Intel Corporation. All rights reserved.
MATRIX_REQUEST	MATRIX_RESPONSE	MATRIX_VALUE	MATRIX_REGISTER	DESCRIPTION
DEMAND_DATA_RD	Null	0x0001	0,1	Counts demand and DCU prefetch data read
DEMAND_RFO	Null	0x0002	0,1	Counts demand and DCU prefetch RFOs
DEMAND_CODE_RD	Null	0x0004	0,1	Counts demand and DCU prefetch instruction cacheline
COREWB	Null	0x0008	0,1	Counts writeback (modified to exclusive)
PF_L2_DATA_RD	Null	0x0010	0,1	Counts data cacheline reads generated by L2 prefetchers
PF_L2_RFO	Null	0x0020	0,1	Counts RFO requests generated by L2 prefetchers
PF_L2_CODE_RD	Null	0x0040	0,1	Counts code reads generated by L2 prefetchers
PARTIAL_READS	Null	0x0080	0,1	Counts demand reads of partial cache lines (including UC and WC)
PARTIAL_WRITES	Null	0x0100	0,1	Countsof demand RFO requests to write to partial cache lines
UC_CODE_READS	Null	0x0200	0,1	Counts UC instruction fetch
BUS_LOCKS	Null	0x0400	0,1	Bus lock and split lock
PF_L1_DATA_RD	Null	0x2000	0,1	Counts DCU hardware prefetcher data read
ANY_REQUEST	Null	0x8008	0,1	Counts any request
STREAMING_STORES	Null	0x4800	0,1	Counts streaming store
ANY_DATA_RD	Null	0x3091	0,1	Counts any data read (demand & prefetch)
ANY_RFO	Null	0x0022	0,1	Counts any rfo reads (demand & prefetch)
ANY_CODE_RD	Null	0x0044	0,1	Counts any code reads (demand & prefetch)
ANY_READS	Null	0x32f7	0,1	Counts any data/code/rfo reads (demand & prefetch)
ANY_PF_L2	Null	0x0070	0,1	Counts any prefetch read
Null	ANY_RESPONSE	0x000001	0,1	have any response type.
Null	L2_MISS.NO_SNOOP_NEEDED	0x008000	0,1	miss L2 with no details on snoop-related information.
Null	L2_MISS.SNOOP_MISS	0x020000	0,1	miss L2 with a snoop miss response.
Null	L2_MISS.HIT_OTHER_CORE_NO_FWD	0x040000	0,1	miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.
Null	L2_MISS.HITM_OTHER_CORE	0x100000	0,1	hit in the other module where modified copies were found in other core's L1 cache.
Null	L2_MISS.NON_DRAM	0x200000	0,1	miss L2 and the target was non-DRAM system address.
Null	L2_MISS.ANY	0x168000	0,1	miss L2.
Null	OUTSTANDING	0x400000	0	are outstanding, per cycle, from the time of the L2 miss to when any response is received.