# Performance Monitoring Events for Intel Atom Processors Based on the Silvermont Microarchitecture - V14
# 3/14/2017 1:13:51 PM
# Copyright (c) 2007 - 2016 Intel Corporation. All rights reserved.
EventCode	UMask	EventName	BriefDescription	Counter	PEBScounters	SampleAfterValue	MSRIndex	MSRValue	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	Errata
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY	Counts any code reads (demand & prefetch) that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680000044	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE	Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.	0,1	0	100007	0x1a6,0x1a7	0x1000000044	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1	0	100007	0x1a6,0x1a7	0x0400000044	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS	Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response.	0,1	0	100007	0x1a6,0x1a7	0x0200000044	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE	Counts any code reads (demand & prefetch) that have any response type.	0,1	0	100007	0x1a6,0x1a7	0x0000010044	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY	Counts any rfo reads (demand & prefetch) that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680000022	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE	Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.	0,1	0	100007	0x1a6,0x1a7	0x1000000022	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1	0	100007	0x1a6,0x1a7	0x0400000022	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS	Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response.	0,1	0	100007	0x1a6,0x1a7	0x0200000022	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE	Counts any rfo reads (demand & prefetch) that have any response type.	0,1	0	100007	0x1a6,0x1a7	0x0000010022	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY	Counts any data read (demand & prefetch) that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680003091	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE	Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.	0,1	0	100007	0x1a6,0x1a7	0x1000003091	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1	0	100007	0x1a6,0x1a7	0x0400003091	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS	Counts any data read (demand & prefetch) that miss L2 with a snoop miss response.	0,1	0	100007	0x1a6,0x1a7	0x0200003091	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE	Counts any data read (demand & prefetch) that have any response type.	0,1	0	100007	0x1a6,0x1a7	0x0000013091	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY	Counts streaming store that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680004800	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE	Counts any request that hit in the other module where modified copies were found in other core's L1 cache.	0,1	0	100007	0x1a6,0x1a7	0x1000008008	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1	0	100007	0x1a6,0x1a7	0x0400008008	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS	Counts any request that miss L2 with a snoop miss response.	0,1	0	100007	0x1a6,0x1a7	0x0200008008	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE	Counts any request that have any response type.	0,1	0	100007	0x1a6,0x1a7	0x0000018008	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY	Counts DCU hardware prefetcher data read that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680002000	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE	Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache.	0,1	0	100007	0x1a6,0x1a7	0x1000002000	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1	0	100007	0x1a6,0x1a7	0x0400002000	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS	Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response.	0,1	0	100007	0x1a6,0x1a7	0x0200002000	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE	Counts DCU hardware prefetcher data read that have any response type.	0,1	0	100007	0x1a6,0x1a7	0x0000012000	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY	Countsof demand RFO requests to write to partial cache lines that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680000100	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY	Counts demand reads of partial cache lines (including UC and WC) that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680000080	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY	Counts code reads generated by L2 prefetchers that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680000040	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1	0	100007	0x1a6,0x1a7	0x0400000040	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS	Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response.	0,1	0	100007	0x1a6,0x1a7	0x0200000040	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY	Counts RFO requests generated by L2 prefetchers that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680000020	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE	Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.	0,1	0	100007	0x1a6,0x1a7	0x1000000020	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1	0	100007	0x1a6,0x1a7	0x0400000020	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS	Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response.	0,1	0	100007	0x1a6,0x1a7	0x0200000020	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY	Counts data cacheline reads generated by L2 prefetchers that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680000010	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE	Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.	0,1	0	100007	0x1a6,0x1a7	0x1000000010	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1	0	100007	0x1a6,0x1a7	0x0400000010	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS	Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response.	0,1	0	100007	0x1a6,0x1a7	0x0200000010	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.COREWB.L2_MISS.ANY	Counts writeback (modified to exclusive) that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680000008	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED	Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information.	0,1	0	100007	0x1a6,0x1a7	0x0080000008	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING	Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.	0,1	0	100007	0x1a6	0x4000000004	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY	Counts demand and DCU prefetch instruction cacheline that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680000004	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1	0	100007	0x1a6,0x1a7	0x0400000004	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS	Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response.	0,1	0	100007	0x1a6,0x1a7	0x0200000004	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE	Counts demand and DCU prefetch instruction cacheline that have any response type.	0,1	0	100007	0x1a6,0x1a7	0x0000010004	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING	Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.	0,1	0	100007	0x1a6	0x4000000002	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY	Counts demand and DCU prefetch RFOs that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680000002	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE	Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache.	0,1	0	100007	0x1a6,0x1a7	0x1000000002	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1	0	100007	0x1a6,0x1a7	0x0400000002	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS	Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response.	0,1	0	100007	0x1a6,0x1a7	0x0200000002	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING	Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.	0,1	0	100007	0x1a6	0x4000000001	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY	Counts demand and DCU prefetch data read that miss L2.	0,1	0	100007	0x1a6,0x1a7	0x1680000001	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE	Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache.	0,1	0	100007	0x1a6,0x1a7	0x1000000001	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD	Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.	0,1	0	100007	0x1a6,0x1a7	0x0400000001	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS	Counts demand and DCU prefetch data read that miss L2 with a snoop miss response.	0,1	0	100007	0x1a6,0x1a7	0x0200000001	0	0	0	0	0	null
0xB7	0x01,0x02	OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE	Counts demand and DCU prefetch data read that have any response type.	0,1	0	100007	0x1a6,0x1a7	0x0000010001	0	0	0	0	0	null