# Performance Monitoring Events for the Second Generation Intel Core Processors Based on the Sandy Bridge Microarchitecture - V16
# 3/2/2018 2:51:47 PM
# Copyright (c) 2007 - 2017 Intel Corporation. All rights reserved.
EventCode	UMask	EventName	BriefDescription	Counter	CounterHTOff	SampleAfterValue	MSRIndex	MSRValue	TakenAlone	CounterMask	Invert	AnyThread	EdgeDetect	PEBS	PRECISE_STORE	Errata
0x00	0x01	INST_RETIRED.ANY	Instructions retired from execution.	Fixed counter 0	Fixed counter 0	2000003	0	0	0	0	0	0	0	0	0	0
0x00	0x02	CPU_CLK_UNHALTED.THREAD	Core cycles when the thread is not in halt state.	Fixed counter 1	Fixed counter 1	2000003	0	0	0	0	0	0	0	0	0	0
0x00	0x02	CPU_CLK_UNHALTED.THREAD_ANY	Core cycles when at least one thread on the physical core is not in halt state.	Fixed counter 1	Fixed counter 1	2000003	0	0	0	0	0	1	0	0	0	0
0x00	0x03	CPU_CLK_UNHALTED.REF_TSC	Reference cycles when the core is not in halt state.	Fixed counter 2	Fixed counter 2	2000003	0	0	0	0	0	0	0	0	0	0
0x03	0x01	LD_BLOCKS.DATA_UNKNOWN	Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x03	0x02	LD_BLOCKS.STORE_FORWARD	Cases when loads get true Block-on-Store blocking code preventing store forwarding.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x03	0x08	LD_BLOCKS.NO_SR	This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x03	0x10	LD_BLOCKS.ALL_BLOCK	Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x05	0x01	MISALIGN_MEM_REF.LOADS	Speculative cache line split load uops dispatched to L1 cache.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x05	0x02	MISALIGN_MEM_REF.STORES	Speculative cache line split STA uops dispatched to L1 cache.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x07	0x01	LD_BLOCKS_PARTIAL.ADDRESS_ALIAS	False dependencies in MOB due to partial compare.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x07	0x08	LD_BLOCKS_PARTIAL.ALL_STA_BLOCK	This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x08	0x01	DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK	Load misses in all DTLB levels that cause page walks.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x08	0x02	DTLB_LOAD_MISSES.WALK_COMPLETED	Load misses at all DTLB levels that cause completed page walks.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x08	0x04	DTLB_LOAD_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x08	0x10	DTLB_LOAD_MISSES.STLB_HIT	Load operations that miss the first DTLB level but hit the second and do not cause page walks.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x0D	0x03	INT_MISC.RECOVERY_CYCLES	Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0
0x0D	0x03	INT_MISC.RECOVERY_STALLS_COUNT	Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	0
0x0D	0x03	INT_MISC.RECOVERY_CYCLES_ANY	Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	1	0	0	0	0
0x0D	0x40	INT_MISC.RAT_STALL_CYCLES	Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x0E	0x01	UOPS_ISSUED.ANY	Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x0E	0x01	UOPS_ISSUED.STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0
0x0E	0x01	UOPS_ISSUED.CORE_STALL_CYCLES	Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	1	0	0	0	0
0x10	0x01	FP_COMP_OPS_EXE.X87	Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x10	0x10	FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE	Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x10	0x20	FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE	Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x10	0x40	FP_COMP_OPS_EXE.SSE_PACKED_SINGLE	Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x10	0x80	FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE	Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x11	0x01	SIMD_FP_256.PACKED_SINGLE	Number of GSSE-256 Computational FP single precision uops issued this cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x11	0x02	SIMD_FP_256.PACKED_DOUBLE	Number of AVX-256 Computational FP double precision uops issued this cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x14	0x01	ARITH.FPU_DIV_ACTIVE	Cycles when divider is busy executing divide operations.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x14	0x01	ARITH.FPU_DIV	Divide operations executed.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	0
0x17	0x01	INSTS_WRITTEN_TO_IQ.INSTS	Valid instructions written to IQ per cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x24	0x01	L2_RQSTS.DEMAND_DATA_RD_HIT	Demand Data Read requests that hit L2 cache.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x24	0x03	L2_RQSTS.ALL_DEMAND_DATA_RD	Demand Data Read requests.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x24	0x04	L2_RQSTS.RFO_HIT	RFO requests that hit L2 cache.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x24	0x08	L2_RQSTS.RFO_MISS	RFO requests that miss L2 cache.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x24	0x0C	L2_RQSTS.ALL_RFO	RFO requests to L2 cache.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x24	0x10	L2_RQSTS.CODE_RD_HIT	L2 cache hits when fetching instructions, code reads.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x24	0x20	L2_RQSTS.CODE_RD_MISS	L2 cache misses when fetching instructions.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x24	0x30	L2_RQSTS.ALL_CODE_RD	L2 code requests.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x24	0x40	L2_RQSTS.PF_HIT	Requests from the L2 hardware prefetchers that hit L2 cache.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x24	0x80	L2_RQSTS.PF_MISS	Requests from the L2 hardware prefetchers that miss L2 cache.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x24	0xC0	L2_RQSTS.ALL_PF	Requests from L2 hardware prefetchers.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x27	0x01	L2_STORE_LOCK_RQSTS.MISS	RFOs that miss cache lines.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x27	0x04	L2_STORE_LOCK_RQSTS.HIT_E	RFOs that hit cache lines in E state.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x27	0x08	L2_STORE_LOCK_RQSTS.HIT_M	RFOs that hit cache lines in M state.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x27	0x0F	L2_STORE_LOCK_RQSTS.ALL	RFOs that access cache lines in any state.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x28	0x01	L2_L1D_WB_RQSTS.MISS	Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x28	0x02	L2_L1D_WB_RQSTS.HIT_S	Not rejected writebacks from L1D to L2 cache lines in S state.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x28	0x04	L2_L1D_WB_RQSTS.HIT_E	Not rejected writebacks from L1D to L2 cache lines in E state.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x28	0x08	L2_L1D_WB_RQSTS.HIT_M	Not rejected writebacks from L1D to L2 cache lines in M state.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x28	0x0F	L2_L1D_WB_RQSTS.ALL	Not rejected writebacks from L1D to L2 cache lines in any state.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x2E	0x41	LONGEST_LAT_CACHE.MISS	Core-originated cacheable demand requests missed LLC.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x2E	0x4F	LONGEST_LAT_CACHE.REFERENCE	Core-originated cacheable demand requests that refer to LLC.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P	Thread cycles when thread is not in halt state.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x3C	0x00	CPU_CLK_UNHALTED.THREAD_P_ANY	Core cycles when at least one thread on the physical core is not in halt state.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0
0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK	Reference cycles when the thread is unhalted (counts at 100 MHz rate).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x3C	0x01	CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY	Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	0	0	1	0	0	0	0
0x3C	0x01	CPU_CLK_UNHALTED.REF_XCLK	Reference cycles when the thread is unhalted (counts at 100 MHz rate).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	0	0	0	0	0	0	0
0x3C	0x01	CPU_CLK_UNHALTED.REF_XCLK_ANY	Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	0	0	1	0	0	0	0
0x3C	0x02	CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE	Count XClk pulses when this thread is unhalted and the other is halted.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0
0x3C	0x02	CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE	Count XClk pulses when this thread is unhalted and the other thread is halted.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	0	0	0	0	0	0	0
0x48	0x01	L1D_PEND_MISS.PENDING	L1D miss oustandings duration in cycles.	2	2	2000003	0	0	0	0	0	0	0	0	0	0
0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES	Cycles with L1D load Misses outstanding.	2	2	2000003	0	0	0	1	0	0	0	0	0	0
0x48	0x01	L1D_PEND_MISS.PENDING_CYCLES_ANY	Cycles with L1D load Misses outstanding from any thread on physical core.	2	2	2000003	0x00	0x00	0	1	0	1	0	0	0	0
0x48	0x02	L1D_PEND_MISS.FB_FULL	Cycles a demand request was blocked due to Fill Buffers inavailability.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	1	0	0	0	0	0	0
0x49	0x01	DTLB_STORE_MISSES.MISS_CAUSES_A_WALK	Store misses in all DTLB levels that cause page walks.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x49	0x02	DTLB_STORE_MISSES.WALK_COMPLETED	Store misses in all DTLB levels that cause completed page walks.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x49	0x04	DTLB_STORE_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x49	0x10	DTLB_STORE_MISSES.STLB_HIT	Store operations that miss the first TLB level but hit the second and do not cause page walks.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x4C	0x01	LOAD_HIT_PRE.SW_PF	Not software-prefetch load dispatches that hit FB allocated for software prefetch.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x4C	0x02	LOAD_HIT_PRE.HW_PF	Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x4E	0x02	HW_PRE_REQ.DL1_MISS	Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x4F	0x10	EPT.WALK_CYCLES	Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x51	0x01	L1D.REPLACEMENT	L1D data line replacements.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x51	0x02	L1D.ALLOCATED_IN_M	Allocated L1D data cache lines in M state.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x51	0x04	L1D.EVICTION	L1D data cache lines in M state evicted due to replacement.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x51	0x08	L1D.ALL_M_REPLACEMENT	Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x59	0x20	PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP	Increments the number of flags-merge uops in flight each cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x59	0x20	PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES	Performance sensitive flags-merging uops added by Sandy Bridge u-arch.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0
0x59	0x40	PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW	Cycles with at least one slow LEA uop being allocated.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x59	0x80	PARTIAL_RAT_STALLS.MUL_SINGLE_UOP	Multiply packed/scalar single precision uops allocated.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x5B	0x0C	RESOURCE_STALLS2.ALL_FL_EMPTY	Cycles with either free list is empty.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x5B	0x0F	RESOURCE_STALLS2.ALL_PRF_CONTROL	Resource stalls2 control structures full for physical registers.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x5B	0x40	RESOURCE_STALLS2.BOB_FULL	Cycles when Allocator is stalled if BOB is full and new branch needs it.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x5B	0x4F	RESOURCE_STALLS2.OOO_RSRC	Resource stalls out of order resources full.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x5C	0x01	CPL_CYCLES.RING0	Unhalted core cycles when the thread is in ring 0.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x5C	0x01	CPL_CYCLES.RING0_TRANS	Number of intervals between processor halts while thread is in ring 0.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	1	0	0	1	0	0	0
0x5C	0x02	CPL_CYCLES.RING123	Unhalted core cycles when thread is in rings 1, 2, or 3.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x5E	0x01	RS_EVENTS.EMPTY_CYCLES	Cycles when Reservation Station (RS) is empty for the thread.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x5E	0x01	RS_EVENTS.EMPTY_END	Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	1	0	1	0	0	0
0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD	Offcore outstanding Demand Data Read transactions in uncore queue.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD	Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0
0x60	0x01	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6	Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	6	0	0	0	0	0	0
0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO	Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x60	0x04	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO	Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0
0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD	Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x60	0x08	OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD	Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0
0x63	0x01	LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION	Cycles when L1 and L2 are locked due to UC or split lock.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x63	0x02	LOCK_CYCLES.CACHE_LOCK_DURATION	Cycles when L1D is locked.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x79	0x02	IDQ.EMPTY	Instruction Decode Queue (IDQ) empty cycles.	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0
0x79	0x04	IDQ.MITE_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x79	0x04	IDQ.MITE_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0
0x79	0x08	IDQ.DSB_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x79	0x08	IDQ.DSB_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0
0x79	0x10	IDQ.MS_DSB_UOPS	Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x79	0x10	IDQ.MS_DSB_CYCLES	Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0
0x79	0x10	IDQ.MS_DSB_OCCUR	Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	1	0	0	0
0x79	0x18	IDQ.ALL_DSB_CYCLES_4_UOPS	Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0
0x79	0x18	IDQ.ALL_DSB_CYCLES_ANY_UOPS	Cycles Decode Stream Buffer (DSB) is delivering any Uop.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0
0x79	0x20	IDQ.MS_MITE_UOPS	Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x79	0x24	IDQ.ALL_MITE_CYCLES_4_UOPS	Cycles MITE is delivering 4 Uops.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0
0x79	0x24	IDQ.ALL_MITE_CYCLES_ANY_UOPS	Cycles MITE is delivering any Uop.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0
0x79	0x30	IDQ.MS_UOPS	Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x79	0x30	IDQ.MS_CYCLES	Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0
0x79	0x30	IDQ.MS_SWITCHES	Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0x00	0	1	0	0	1	0	0	0
0x79	0x3c	IDQ.MITE_ALL_UOPS	Uops delivered to Instruction Decode Queue (IDQ) from MITE path.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x80	0x01	ICACHE.HIT	Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x80	0x02	ICACHE.MISSES	Instruction cache, streaming buffer and victim cache misses.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x85	0x01	ITLB_MISSES.MISS_CAUSES_A_WALK	Misses at all ITLB levels that cause page walks.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x85	0x02	ITLB_MISSES.WALK_COMPLETED	Misses in all ITLB levels that cause completed page walks.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x85	0x04	ITLB_MISSES.WALK_DURATION	Cycles when PMH is busy with page walks.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x85	0x10	ITLB_MISSES.STLB_HIT	Operations that miss the first ITLB level but hit the second and do not cause any page walks.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0x87	0x01	ILD_STALL.LCP	Stalls caused by changing prefix length of the instruction.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x87	0x04	ILD_STALL.IQ_FULL	Stall cycles because IQ is full.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0x88	0x41	BR_INST_EXEC.NONTAKEN_CONDITIONAL	Not taken macro-conditional branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x88	0x81	BR_INST_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired macro-conditional branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x88	0x82	BR_INST_EXEC.TAKEN_DIRECT_JUMP	Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x88	0x84	BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired indirect branches excluding calls and returns.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x88	0x88	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN	Taken speculative and retired indirect branches with return mnemonic.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x88	0x90	BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL	Taken speculative and retired direct near calls.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x88	0xA0	BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired indirect calls.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x88	0xC1	BR_INST_EXEC.ALL_CONDITIONAL	Speculative and retired macro-conditional branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x88	0xC2	BR_INST_EXEC.ALL_DIRECT_JMP	Speculative and retired macro-unconditional branches excluding calls and indirects.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x88	0xC4	BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Speculative and retired indirect branches excluding calls and returns.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x88	0xC8	BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN	Speculative and retired indirect return branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x88	0xD0	BR_INST_EXEC.ALL_DIRECT_NEAR_CALL	Speculative and retired direct near calls.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x88	0xFF	BR_INST_EXEC.ALL_BRANCHES	Speculative and retired  branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x89	0x41	BR_MISP_EXEC.NONTAKEN_CONDITIONAL	Not taken speculative and retired mispredicted macro conditional branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x89	0x81	BR_MISP_EXEC.TAKEN_CONDITIONAL	Taken speculative and retired mispredicted macro conditional branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x89	0x84	BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET	Taken speculative and retired mispredicted indirect branches excluding calls and returns.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x89	0x88	BR_MISP_EXEC.TAKEN_RETURN_NEAR	Taken speculative and retired mispredicted indirect branches with return mnemonic.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x89	0x90	BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL	Taken speculative and retired mispredicted direct near calls.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x89	0xA0	BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL	Taken speculative and retired mispredicted indirect calls.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x89	0xC1	BR_MISP_EXEC.ALL_CONDITIONAL	Speculative and retired mispredicted macro conditional branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x89	0xC4	BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET	Mispredicted indirect branches excluding calls and returns.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x89	0xD0	BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL	Speculative and retired mispredicted direct near calls.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x89	0xFF	BR_MISP_EXEC.ALL_BRANCHES	Speculative and retired mispredicted macro conditional branches.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CORE	Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	0	0	0
0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE	Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0
0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE	Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.	0,1,2,3	0,1,2,3	2000003	0	0	0	3	0	0	0	0	0	0
0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE	Cycles with less than 2 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	2	0	0	0	0	0	0
0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE	Cycles with less than 3 uops delivered by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	0	0	0	0	0	0
0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE	Cycles when 1 or more uops were delivered to the by the front end.	0,1,2,3	0,1,2,3	2000003	0	0	0	4	1	0	0	0	0	0
0x9C	0x01	IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK	Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0
0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0	Cycles per thread when uops are dispatched to port 0.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA1	0x01	UOPS_DISPATCHED_PORT.PORT_0_CORE	Cycles per core when uops are dispatched to port 0.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0
0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1	Cycles per thread when uops are dispatched to port 1.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA1	0x02	UOPS_DISPATCHED_PORT.PORT_1_CORE	Cycles per core when uops are dispatched to port 1.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0
0xA1	0x0C	UOPS_DISPATCHED_PORT.PORT_2	Cycles per thread when load or STA uops are dispatched to port 2.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA1	0x0C	UOPS_DISPATCHED_PORT.PORT_2_CORE	Cycles per core when load or STA uops are dispatched to port 2.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0
0xA1	0x30	UOPS_DISPATCHED_PORT.PORT_3	Cycles per thread when load or STA uops are dispatched to port 3.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA1	0x30	UOPS_DISPATCHED_PORT.PORT_3_CORE	Cycles per core when load or STA uops are dispatched to port 3.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0
0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_4	Cycles per thread when uops are dispatched to port 4.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA1	0x40	UOPS_DISPATCHED_PORT.PORT_4_CORE	Cycles per core when uops are dispatched to port 4.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0
0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_5	Cycles per thread when uops are dispatched to port 5.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA1	0x80	UOPS_DISPATCHED_PORT.PORT_5_CORE	Cycles per core when uops are dispatched to port 5.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	1	0	0	0	0
0xA2	0x01	RESOURCE_STALLS.ANY	Resource-related stall cycles.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA2	0x02	RESOURCE_STALLS.LB	Counts the cycles of stall due to lack of load buffers.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA2	0x04	RESOURCE_STALLS.RS	Cycles stalled due to no eligible RS entry available.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA2	0x08	RESOURCE_STALLS.SB	Cycles stalled due to no store buffers available. (not including draining form sync).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA2	0x0A	RESOURCE_STALLS.LB_SB	Resource stalls due to load or store buffers all being in use.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA2	0x0E	RESOURCE_STALLS.MEM_RS	Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA2	0x10	RESOURCE_STALLS.ROB	Cycles stalled due to re-order buffer full.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA2	0xF0	RESOURCE_STALLS.OOO_RSRC	Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA3	0x01	CYCLE_ACTIVITY.CYCLES_L2_PENDING	Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0
0xA3	0x02	CYCLE_ACTIVITY.CYCLES_L1D_PENDING	Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.	2	2	2000003	0	0	0	2	0	0	0	0	0	0
0xA3	0x04	CYCLE_ACTIVITY.CYCLES_NO_DISPATCH	Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.	0,1,2,3	0,1,2,3	2000003	0	0	0	4	0	0	0	0	0	0
0xA3	0x05	CYCLE_ACTIVITY.STALLS_L2_PENDING	Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.	0,1,2,3	0,1,2,3	2000003	0	0	0	5	0	0	0	0	0	0
0xA3	0x06	CYCLE_ACTIVITY.STALLS_L1D_PENDING	Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.	2	2	2000003	0	0	0	6	0	0	0	0	0	0
0xA8	0x01	LSD.UOPS	Number of Uops delivered by the LSD.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xA8	0x01	LSD.CYCLES_ACTIVE	Cycles Uops delivered by the LSD, but didn't come from the decoder.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	1	0	0	0	0	0	0
0xA8	0x01	LSD.CYCLES_4_UOPS	Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	4	0	0	0	0	0	0
0xAB	0x01	DSB2MITE_SWITCHES.COUNT	Decode Stream Buffer (DSB)-to-MITE switches.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xAB	0x02	DSB2MITE_SWITCHES.PENALTY_CYCLES	Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xAC	0x02	DSB_FILL.OTHER_CANCEL	Cases of cancelling valid DSB fill not because of exceeding way limit.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xAC	0x08	DSB_FILL.EXCEED_DSB_LINES	Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xAC	0x0A	DSB_FILL.ALL_CANCEL	Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xAE	0x01	ITLB.ITLB_FLUSH	Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	0
0xB0	0x01	OFFCORE_REQUESTS.DEMAND_DATA_RD	Demand Data Read requests sent to uncore.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xB0	0x02	OFFCORE_REQUESTS.DEMAND_CODE_RD	Cacheable and noncachaeble code read requests.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xB0	0x04	OFFCORE_REQUESTS.DEMAND_RFO	Demand RFO requests including regular RFOs, locks, ItoM.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xB0	0x08	OFFCORE_REQUESTS.ALL_DATA_RD	Demand and prefetch data reads.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xB1	0x01	UOPS_DISPATCHED.THREAD	Uops dispatched per thread.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xB1	0x02	UOPS_DISPATCHED.CORE	Uops dispatched from any thread.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_1	Cycles at least 1 micro-op is executed from any thread on physical core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	1	0	0	0	0	0	0
0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_2	Cycles at least 2 micro-op is executed from any thread on physical core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	0	0	0	0	0
0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_3	Cycles at least 3 micro-op is executed from any thread on physical core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	3	0	0	0	0	0	0
0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_GE_4	Cycles at least 4 micro-op is executed from any thread on physical core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	4	0	0	0	0	0	0
0xB1	0x02	UOPS_EXECUTED.CORE_CYCLES_NONE	Cycles with no micro-ops executed from any thread on physical core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	0	1	0	0	0	0	0
0xB2	0x01	OFFCORE_REQUESTS_BUFFER.SQ_FULL	Cases when offcore requests buffer cannot take more entries for core.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xB6	0x01	AGU_BYPASS_CANCEL.COUNT	This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xBD	0x01	TLB_FLUSH.DTLB_THREAD	DTLB flush attempts of the thread-specific entries.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	0
0xBD	0x20	TLB_FLUSH.STLB_ANY	STLB flush attempts.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	0
0xBE	0x01	PAGE_WALKS.LLC_MISS	Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xBF	0x05	L1D_BLOCKS.BANK_CONFLICT_CYCLES	Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	0	0	0	0
0xC0	0x00	INST_RETIRED.ANY_P	Number of instructions retired. General Counter   - architectural event.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xC0	0x01	INST_RETIRED.PREC_DIST	Instructions retired. (Precise Event - PEBS).	1	1	2000003	0	0	1	0	0	0	0	2	0	0
0xC1	0x02	OTHER_ASSISTS.ITLB_MISS_RETIRED	Retired instructions experiencing ITLB misses.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xC1	0x08	OTHER_ASSISTS.AVX_STORE	Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xC1	0x10	OTHER_ASSISTS.AVX_TO_SSE	Number of transitions from AVX-256 to legacy SSE when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xC1	0x20	OTHER_ASSISTS.SSE_TO_AVX	Number of transitions from SSE to AVX-256 when penalty applicable.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xC2	0x01	UOPS_RETIRED.ALL	Actually retired uops. (Precise Event - PEBS).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	0
0xC2	0x01	UOPS_RETIRED.STALL_CYCLES	Cycles without actually retired uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0
0xC2	0x01	UOPS_RETIRED.TOTAL_CYCLES	Cycles with less than 10 actually retired uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	10	1	0	0	0	0	0
0xC2	0x01	UOPS_RETIRED.CORE_STALL_CYCLES	Cycles without actually retired uops.	0,1,2,3	0,1,2,3	2000003	0	0	0	1	1	0	0	0	0	0
0xC2	0x02	UOPS_RETIRED.RETIRE_SLOTS	Retirement slots used. (Precise Event - PEBS).	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	1	0	0
0xc3	0x01	MACHINE_CLEARS.COUNT	Number of machine clears (nukes) of any type.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	1	0	0	1	0	0	0
0xC3	0x02	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory order conflicts.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xC3	0x04	MACHINE_CLEARS.SMC	Self-modifying code (SMC) detected.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xC3	0x20	MACHINE_CLEARS.MASKMOV	This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xC4	0x00	BR_INST_RETIRED.ALL_BRANCHES	All (macro) branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0
0xC4	0x01	BR_INST_RETIRED.CONDITIONAL	Conditional branch instructions retired. (Precise Event - PEBS).	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0
0xC4	0x02	BR_INST_RETIRED.NEAR_CALL	Direct and indirect near call instructions retired. (Precise Event - PEBS).	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0
0xC4	0x02	BR_INST_RETIRED.NEAR_CALL_R3	Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0
0xC4	0x04	BR_INST_RETIRED.ALL_BRANCHES_PEBS	All (macro) branch instructions retired. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	0
0xC4	0x08	BR_INST_RETIRED.NEAR_RETURN	Return instructions retired. (Precise Event - PEBS).	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0
0xC4	0x10	BR_INST_RETIRED.NOT_TAKEN	Not taken branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0
0xC4	0x20	BR_INST_RETIRED.NEAR_TAKEN	Taken branch instructions retired. (Precise Event - PEBS).	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0
0xC4	0x40	BR_INST_RETIRED.FAR_BRANCH	Far branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	0	0	0
0xC5	0x00	BR_MISP_RETIRED.ALL_BRANCHES	All mispredicted macro branch instructions retired.	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	0	0	0
0xC5	0x01	BR_MISP_RETIRED.CONDITIONAL	Mispredicted conditional branch instructions retired. (Precise Event - PEBS).	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0
0xC5	0x02	BR_MISP_RETIRED.NEAR_CALL	Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).	0,1,2,3	0,1,2,3,4,5,6,7	100007	0	0	0	0	0	0	0	1	0	0
0xC5	0x04	BR_MISP_RETIRED.ALL_BRANCHES_PEBS	Mispredicted macro branch instructions retired. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	400009	0	0	0	0	0	0	0	2	0	0
0xC5	0x10	BR_MISP_RETIRED.NOT_TAKEN	Mispredicted not taken branch instructions retired.(Precise Event - PEBS).	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0
0xC5	0x20	BR_MISP_RETIRED.TAKEN	Mispredicted taken branch instructions retired. (Precise Event - PEBS).	0,1,2,3	0,1,2,3,4,5,6,7	400009	0	0	0	0	0	0	0	1	0	0
0xCA	0x02	FP_ASSIST.X87_OUTPUT	Number of X87 assists due to output value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xCA	0x04	FP_ASSIST.X87_INPUT	Number of X87 assists due to input value.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xCA	0x08	FP_ASSIST.SIMD_OUTPUT	Number of SIMD FP assists due to Output values.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xCA	0x10	FP_ASSIST.SIMD_INPUT	Number of SIMD FP assists due to input values.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xCA	0x1E	FP_ASSIST.ANY	Cycles with any input/output SSE or FP assist.	0,1,2,3	0,1,2,3	100003	0	0	0	1	0	0	0	0	0	0
0xCC	0x20	ROB_MISC_EVENTS.LBR_INSERTS	Count cases of saving new LBR.	0,1,2,3	0,1,2,3,4,5,6,7	2000003	0	0	0	0	0	0	0	0	0	0
0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4	Loads with latency value being above 4 .	3	3	100003	0x3F6	0x4	1	0	0	0	0	2	0	0
0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8	Loads with latency value being above 8.	3	3	50021	0x3F6	0x8	1	0	0	0	0	2	0	0
0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16	Loads with latency value being above 16.	3	3	20011	0x3F6	0x10	1	0	0	0	0	2	0	0
0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32	Loads with latency value being above 32.	3	3	100007	0x3F6	0x20	1	0	0	0	0	2	0	0
0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64	Loads with latency value being above 64.	3	3	2003	0x3F6	0x40	1	0	0	0	0	2	0	0
0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128	Loads with latency value being above 128.	3	3	1009	0x3F6	0x80	1	0	0	0	0	2	0	0
0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256	Loads with latency value being above 256.	3	3	503	0x3F6	0x100	1	0	0	0	0	2	0	0
0xCD	0x01	MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512	Loads with latency value being above 512.	3	3	101	0x3F6	0x200	1	0	0	0	0	2	0	0
0xCD	0x02	MEM_TRANS_RETIRED.PRECISE_STORE	Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).	3	3	2000003	0	0	1	0	0	0	0	2	1	0
0xD0	0x11	MEM_UOPS_RETIRED.STLB_MISS_LOADS	Retired load uops that miss the STLB. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	0
0xD0	0x12	MEM_UOPS_RETIRED.STLB_MISS_STORES	Retired store uops that miss the STLB. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	0
0xD0	0x21	MEM_UOPS_RETIRED.LOCK_LOADS	Retired load uops with locked access. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	0	0
0xD0	0x41	MEM_UOPS_RETIRED.SPLIT_LOADS	Retired load uops that split across a cacheline boundary. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	0
0xD0	0x42	MEM_UOPS_RETIRED.SPLIT_STORES	Retired store uops that split across a cacheline boundary. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	0
0xD0	0x81	MEM_UOPS_RETIRED.ALL_LOADS	All retired load uops. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0
0xD0	0x82	MEM_UOPS_RETIRED.ALL_STORES	All retired store uops. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0
0xD1	0x01	MEM_LOAD_UOPS_RETIRED.L1_HIT	Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	2000003	0	0	0	0	0	0	0	1	0	0
0xD1	0x02	MEM_LOAD_UOPS_RETIRED.L2_HIT	Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	0
0xD1	0x04	MEM_LOAD_UOPS_RETIRED.LLC_HIT	Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	50021	0	0	0	0	0	0	0	1	0	0
0xD1	0x40	MEM_LOAD_UOPS_RETIRED.HIT_LFB	Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	0
0xD2	0x01	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS	Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	0	0
0xD2	0x02	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT	Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	0	0
0xD2	0x04	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM	Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	20011	0	0	0	0	0	0	0	1	0	0
0xD2	0x08	MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE	Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	100003	0	0	0	0	0	0	0	1	0	0
0xD4	0x02	MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS	Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS).	0,1,2,3	0,1,2,3	100007	0	0	0	0	0	0	0	1	0	0
0xE6	0x1F	BACLEARS.ANY	Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xF0	0x01	L2_TRANS.DEMAND_DATA_RD	Demand Data Read requests that access L2 cache.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0xF0	0x02	L2_TRANS.RFO	RFO requests that access L2 cache.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0xF0	0x04	L2_TRANS.CODE_RD	L2 cache accesses when fetching instructions.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0xF0	0x08	L2_TRANS.ALL_PF	L2 or LLC HW prefetches that access L2 cache.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0xF0	0x10	L2_TRANS.L1D_WB	L1D writebacks that access L2 cache.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0xF0	0x20	L2_TRANS.L2_FILL	L2 fill requests that access L2 cache.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0xF0	0x40	L2_TRANS.L2_WB	L2 writebacks that access L2 cache.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0xF0	0x80	L2_TRANS.ALL_REQUESTS	Transactions accessing L2 pipe.	0,1,2,3	0,1,2,3,4,5,6,7	200003	0	0	0	0	0	0	0	0	0	0
0xF1	0x01	L2_LINES_IN.I	L2 cache lines in I state filling L2.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xF1	0x02	L2_LINES_IN.S	L2 cache lines in S state filling L2.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xF1	0x04	L2_LINES_IN.E	L2 cache lines in E state filling L2.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xF1	0x07	L2_LINES_IN.ALL	L2 cache lines filling L2.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xF2	0x01	L2_LINES_OUT.DEMAND_CLEAN	Clean L2 cache lines evicted by demand.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xF2	0x02	L2_LINES_OUT.DEMAND_DIRTY	Dirty L2 cache lines evicted by demand.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xF2	0x04	L2_LINES_OUT.PF_CLEAN	Clean L2 cache lines evicted by L2 prefetch.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xF2	0x08	L2_LINES_OUT.PF_DIRTY	Dirty L2 cache lines evicted by L2 prefetch.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xF2	0x0A	L2_LINES_OUT.DIRTY_ALL	Dirty L2 cache lines filling the L2.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0
0xF4	0x10	SQ_MISC.SPLIT_LOCK	Split locks in SQ.	0,1,2,3	0,1,2,3,4,5,6,7	100003	0	0	0	0	0	0	0	0	0	0