TMA,Version,3.5-public,,,,,,,,,,,,,,,,,3.503,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
.,,,,,Server,,Server,,Server,,Server,,Server,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Key,Level1,Level2,Level3,Level4,SKX/CLX,SKL/KBL/KBLR/CFL,BDX,BDW/BDW-DE,HSX,HSW,IVT,IVB,JKT/SNB-EP,SNB,Locate-with,Count Domain,Metric Description,Threshold,Version,Metric Group,Metric Max,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
FE,Frontend_Bound,,,,,,,,,,,,,IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? #NA : FRONTEND_RETIRED.LATENCY_GE_8_PS,Slots,This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.,> 0.2,3.0,TopDownL1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
FE,,Frontend_Latency,,,,,,#Pipeline_Width * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS,,,,,,#Pipeline_Width * #Frontend_Latency_Cycles / SLOTS,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? RS_EVENTS.EMPTY_END : FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_32_PS,Slots,This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.,> 0.15 & P,3.0,Frontend_Bound;TopDownL2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
FE,,,ICache_Misses,,,( ICACHE_16B.IFDATA_STALL + 2 * ICACHE_16B.IFDATA_STALL:c1:e1 ) / CLKS,,,,ICACHE.IFDATA_STALL / CLKS,,ICACHE.IFETCH_STALL / CLKS - ITLB_Misses,,#NA,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? #NA : FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS,Clocks,This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.,> 0.05 & P,3.1,Frontend_Latency,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
FE,,,ITLB_Misses,,,ICACHE_64B.IFTAG_STALL / CLKS,,,,,,,,#ITLB_Miss_Cycles / CLKS,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? ITLB_MISSES.WALK_COMPLETED : FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS,Clocks,This metric represents fraction of cycles the CPU was stalled due to instruction TLB misses.,> 0.05 & P,3.2,Frontend_Latency;TLB,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
FE,,,Branch_Resteers,,,( INT_MISC.CLEAR_RESTEER_CYCLES + #BAClear_Cost * BACLEARS.ANY ) / CLKS,,,,,,,,#BAClear_Cost * ( BR_MISP_RETIRED.ALL_BRANCHES_PS + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CLKS,BR_MISP_RETIRED.ALL_BRANCHES_PS,Clocks_Estimated,This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.,> 0.05 & P; ~overlap,3.3,Bad_Speculation;Frontend_Latency,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
FE,,,MS_Switches,,,,,,,,,,,#MS_Switches_Cost * IDQ.MS_SWITCHES / CLKS,IDQ.MS_SWITCHES,Clocks,This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.,> 0.05 & P; $issueMS; $issueSO,3.4,Frontend_Latency;Microcode_Sequencer,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
FE,,Frontend_Bandwidth,,,,,,,,,,,,Frontend_Bound - Frontend_Latency,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? #NA : FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS,Slots,This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or code restrictions for caching in the DSB (decoded uops cache) are categorized under Frontend Bandwidth. In such cases; the Frontend typically delivers non-optimal amount of uops to the Backend (less than four).,> 0.1 & P & (#HighIPC > 0),3.2,Frontend_Bound;TopDownL2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BAD,Bad_Speculation,,,,,,,,,,,,,( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + #Pipeline_Width * #Recovery_Cycles ) / SLOTS,,Slots,This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.,> 0.1,3.4,Bad_Speculation;TopDownL1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BAD,,Branch_Mispredicts,,,,,,,,,,,,#Mispred_Clears_Fraction * Bad_Speculation,BR_MISP_RETIRED.ALL_BRANCHES_PS,Slots,This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.,> 0.05 & P; $issueBR,2.0,Bad_Speculation;Branch_Mispredicts;TopDownL2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BAD,,Machine_Clears,,,,,,,,,,,,Bad_Speculation - Branch_Mispredicts,MACHINE_CLEARS.COUNT,Slots,This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.,> 0.05 & P,2.0,Bad_Speculation;Machine_Clears;TopDownL2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE,Backend_Bound,,,,,,,,,,,,,1 - ( Frontend_Bound + Bad_Speculation + Retiring ),,Slots,This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.,> 0.1,3.4,TopDownL1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Mem,,Memory_Bound,,,,,,,,,,,,#Memory_Bound_Fraction * Backend_Bound,,Slots,This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).,> 0.1 & P,3.2,Backend_Bound;TopDownL2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Mem,,,L1_Bound,,,,,( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CLKS,,,,( #STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_PENDING ) / CLKS,,#NA,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX ? MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS : MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS,Stalls,This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.,(> 0.1 & P),3.4,Cache_Misses;Memory_Bound,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Mem,,,,DTLB_Load,,( #Mem_STLB_Hit_Cost * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_ACTIVE ) / CLKS,,( #Mem_STLB_Hit_Cost * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION:c1 + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED ) / CLKS,,,,,,( #Mem_STLB_Hit_Cost * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION ) / CLKS,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS : MEM_INST_RETIRED.STLB_MISS_LOADS_PS,Clocks_Estimated,This metric roughly estimates the fraction of cycles where the TLB was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.,> 0.1 & P,3.4,TLB,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Mem,,,,FB_Full,,,,Load_Miss_Real_Latency * L1D_PEND_MISS.FB_FULL:c1 / CLKS,,Load_Miss_Real_Latency * L1D_PEND_MISS.REQUEST_FB_FULL:c1 / CLKS,,Load_Miss_Real_Latency * L1D_PEND_MISS.FB_FULL:c1 / CLKS,,,,Clocks_Calculated,This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).,> 0.3; $issueBW; $issueSL,3.3,Memory_BW,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Mem,,,L2_Bound,,,( 1 if FB_Full < 1.5 else #LOAD_L2_HIT / ( #LOAD_L2_HIT + L1D_PEND_MISS.FB_FULL:c1 ) ) * #L2_Bound_Ratio,,( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CLKS,,,,( CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING ) / CLKS,,#NA,SNB/JKT ? #NA : IVB/IVT/HSW/HSX/BDW/BDX ? MEM_LOAD_UOPS_RETIRED.L2_HIT_PS : MEM_LOAD_RETIRED.L2_HIT_PS,Stalls,This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.,> 0.05 & P,3.3,Cache_Misses;Memory_Bound,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Mem,,,L3_Bound,,,( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CLKS,,#Mem_L3_Hit_Fraction * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS,,,,,,#Mem_L3_Hit_Fraction * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS,SNB/JKT/IVB/IVT ? MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS : HSW/HSX/BDW/BDX ? MEM_LOAD_UOPS_RETIRED.L3_HIT_PS : MEM_LOAD_RETIRED.L3_HIT_PS,Stalls,This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.,> 0.05 & P,3.3,Cache_Misses;Memory_Bound,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Mem,,,DRAM_Bound,,( #MEM_Bound_Ratio - PMM_Bound ) if #PMM_App_Direct else #MEM_Bound_Ratio,#MEM_Bound_Ratio,,( 1 - #Mem_L3_Hit_Fraction ) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS,,,,,,( 1 - #Mem_L3_Hit_Fraction ) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS,SNB ? MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS : IVB/IVT/JKT ? MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS : HSW/HSX/BDW/BDX ? MEM_LOAD_UOPS_RETIRED.L3_MISS_PS : MEM_LOAD_RETIRED.L3_MISS_PS,Stalls,This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.,> 0.1 & P,3.4,Memory_Bound,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Mem,,,,MEM_Bandwidth,,,,,,,,,,#ORO_DRD_BW_Cycles / CLKS,,Clocks,This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this thread; requests from other IA threads/cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).,> 0.1 & P; $issueBW,3.1,Memory_BW,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Mem,,,,MEM_Latency,,,,,,,,,,#ORO_DRD_Any_Cycles / CLKS - MEM_Bandwidth,,Clocks,This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other threads/cores/sockets (see Uncore counters for that).,> 0.1 & P; $issueLat,3.1,Memory_Lat,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Mem,,,PMM_Bound,,( ( ( 1 - #Mem_DDR_Hit_Fraction ) * #MEM_Bound_Ratio ) if ( #OneMillion * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM_PS + MEM_LOAD_RETIRED.LOCAL_PMM_PS ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) if #PMM_App_Direct else #NA,,,,,,,,,#NA,,Stalls,"This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",> 0.1 & P,3.5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Mem,,,Store_Bound,,,EXE_ACTIVITY.BOUND_ON_STORES / CLKS,,,,,,,,RESOURCE_STALLS.SB / CLKS,SNB/JKT/IVB/IVT/HSW/HSX/BDW/BDX ? MEM_UOPS_RETIRED.ALL_STORES_PS : MEM_INST_RETIRED.ALL_STORES_PS,Stalls,This metric estimates how often CPU was stalled  due to store memory accesses. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should any of these cases be a bottleneck.,> 0.2 & P,3.3,Memory_Bound,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Core,,Core_Bound,,,,,,,,,,,,Backend_Bound - Memory_Bound,,Slots,This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).,> 0.1 & P,3.2,Backend_Bound;TopDownL2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Core,,,Divider,,,ARITH.DIVIDER_ACTIVE / CLKS,,ARITH.FPU_DIV_ACTIVE / CORE_CLKS,,10 * ARITH.DIVIDER_UOPS / CORE_CLKS,,,,ARITH.FPU_DIV_ACTIVE / CORE_CLKS,SNB/JKT/IVB/IVT/BDW/BDX ? ARITH.FPU_DIV_ACTIVE : HSW/HSX ? ARITH.DIVIDER_UOPS : ARITH.DIVIDER_ACTIVE,Clocks,This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.,> 0.2 & P,3.1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Core,,,Ports_Utilization,,,( #Backend_Bound_Cycles - CYCLE_ACTIVITY.STALLS_MEM_ANY - EXE_ACTIVITY.BOUND_ON_STORES ) / CLKS if ( ARITH.DIVIDER_ACTIVE < EXE_ACTIVITY.EXE_BOUND_0_PORTS ) else ( #Backend_Bound_Cycles - CYCLE_ACTIVITY.STALLS_MEM_ANY - EXE_ACTIVITY.BOUND_ON_STORES - EXE_ACTIVITY.EXE_BOUND_0_PORTS ) / CLKS,,( #Backend_Bound_Cycles - RESOURCE_STALLS.SB -  CYCLE_ACTIVITY.STALLS_MEM_ANY ) / CLKS,,,,,,( #Backend_Bound_Cycles - RESOURCE_STALLS.SB -  #STALLS_MEM_ANY ) / CLKS,,Clocks,This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.,> 0.2 & P,3.4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
BE/Core,,,,Serializing_Operation,,PARTIAL_RAT_STALLS.SCOREBOARD / CLKS,,,,,,,,#NA,,Clocks,This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.,> 0.1 & P; $issueSO,3.4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
RET,Retiring,,,,,,,,,,,,,UOPS_RETIRED.RETIRE_SLOTS / SLOTS,,Slots,This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved.  Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. ,(> 0.75 | Microcode_Sequencer),3.4,TopDownL1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
RET,,Base,,,,,,,,,,,,Retiring - Microcode_Sequencer,INST_RETIRED.PREC_DIST,Slots,This metric represents fraction of slots where the CPU was retiring regular uops (ones not originated from the microcode-sequencer). This correlates with total number of instructions used by the program. A uops-per-instruction ratio of 1 should be expected. While this is the most desirable of the top 4 categories; high values does not necessarily mean there no room for performance optimizations.,> 0.6 & P,2.8,TopDownL2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
RET,,,FP_Arith,,,,,FP_Scalar + FP_Vector,,#NA,,,,FP_Scalar + FP_Vector,,Uops,This metric represents overall arithmetic floating-point (FP) uops fraction the CPU has executed (retired),> 0.2 & P,3.0,Retiring,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
RET,,,,FP_Scalar,,,,( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) / UOPS_RETIRED.RETIRE_SLOTS,,#NA,,( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) / UOPS_EXECUTED.THREAD,,( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) / UOPS_DISPATCHED.THREAD,,Uops,This metric represents arithmetic floating-point (FP) scalar uops fraction the CPU has executed (retired).,> 0.1 & P,2.9,FLOPS,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
RET,,,,FP_Vector,( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / UOPS_RETIRED.RETIRE_SLOTS,,,( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / UOPS_RETIRED.RETIRE_SLOTS,,#NA,,( FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) / UOPS_EXECUTED.THREAD,,( FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) / UOPS_DISPATCHED.THREAD,,Uops,This metric represents arithmetic floating-point (FP) vector uops fraction the CPU has executed (retired) aggregated across all vector widths.,> 0.2 & P,2.9,FLOPS,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
RET,,,Other,,,,,1 - FP_Arith,,#NA,,,,1 - FP_Arith,,Uops,This metric represents non-floating-point (FP) uop fraction the CPU has executed. If you application has no FP operations and performs with decent IPC (Instructions Per Cycle); this node will likely be biggest fraction.,> 0.3 & P,3.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
RET,,Microcode_Sequencer,,,,,,,,,,,,#Retire_Uop_Fraction * IDQ.MS_UOPS / SLOTS,IDQ.MS_UOPS,Slots,This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.,> 0.05; $issueMS,2.4,Microcode_Sequencer;Retiring;TopDownL2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
.,metrics,,,,,,,,,,,,,,,-,,,2.5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Thread,IPC,,,,,,,,,,,,,INST_RETIRED.ANY / CLKS,,Metric,Instructions Per Cycle (per logical thread),,2.9,TopDownL1,5.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Thread,UPI,,,,,,,,,,,,,UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY,,Metric,Uops Per Instruction,> 1.05,3.4,Pipeline;Retiring,2.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Thread,IpTB,,,,,,,,,,,INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN,,,,Metric,Instruction per taken branch,< 5,3.4,Branches;PGO,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Thread,BpTB,,,,,,,,,,,BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN,,,,Metric,Branch instructions per taken branch. ,,3.4,Branches;PGO,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Thread,IFetch_Line_Utilization,,,,,"min( 1 , UOPS_ISSUED.ANY / ( UPI * 64 * ( ICACHE_64B.IFTAG_HIT + ICACHE_64B.IFTAG_MISS ) / 4.1 ) )",,,,"min( 1 , IDQ.MITE_UOPS / ( UPI * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )",,,,"min( 1 , UOPS_ISSUED.ANY / ( UPI * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )",,Metric,Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions,< 0.5,3.4,PGO,1.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Thread,DSB_Coverage,,,,,IDQ.DSB_UOPS / #Fetched_Uops,,,,,,,,IDQ.DSB_UOPS / #Fetched_Uops,,Metric,Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache),< 0.7 & (#HighIPC > 0),3.4,DSB;Frontend_Bandwidth,1.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Thread,CPI,,,,,,,,,,,,,1 / IPC,,Metric,Cycles Per Instruction (threaded),,2.7,Pipeline;Summary,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Thread,CLKS,,,,,,,,,,,,,CPU_CLK_UNHALTED.THREAD,,Count,Per-thread actual clocks when the logical processor is active.,,2.0,Summary,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Thread,SLOTS,,,,,,,,,,,,,#Pipeline_Width * CORE_CLKS,,Count,Total issue-pipeline slots (per core),,2.7,TopDownL1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Inst_Mix,IpL,,,,,INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS_PS,,,,,,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS_PS,,,,Metric,Instructions per Load (lower number means loads are more frequent),,3.2,Instruction_Type;L1_Bound,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Inst_Mix,IpS,,,,,INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES_PS,,,,,,INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES_PS,,,,Metric,Instructions per Store,,3.2,Instruction_Type;Store_Bound,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Inst_Mix,IpB,,,,,,,,,,,INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES,,,,Metric,Instructions per Branch,,3.2,Branches;Instruction_Type;Port_5;Port_6,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Inst_Mix,IpCall,,,,,,,,,,,INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL,,,,Metric,Instruction per (near) call,< 100,3.2,Branches,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Inst_Mix,Instructions,,,,,,,,,,,,,INST_RETIRED.ANY,INST_RETIRED.PREC_DIST,Count,Total number of retired Instructions,,3.2,Summary,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Core,CoreIPC,,,,,,,,,,,,,INST_RETIRED.ANY / CORE_CLKS,,CoreMetric,Instructions Per Cycle (per physical core),,2.9,SMT,5.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Core,FLOPc,,,,,,,#FLOP_Count / CORE_CLKS,,#NA,,,,#FLOP_Count / CORE_CLKS,,CoreMetric,Floating Point Operations Per Cycle,,3.0,FLOPS,10.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Core,ILP,,,,,,,UOPS_EXECUTED.THREAD / #Execute_Cycles,,( UOPS_EXECUTED.CORE / 2 / #Execute_Cycles ) if #SMT_on else UOPS_EXECUTED.CORE / #Execute_Cycles,,UOPS_EXECUTED.THREAD / #Execute_Cycles,,UOPS_DISPATCHED.THREAD / #Execute_Cycles,,CoreMetric,Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed),,2.9,Pipeline;Ports_Utilization,10.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Core,Branch_Misprediction_Cost,,,,,,,( Branch_Mispredicts + Frontend_Latency * Branch_Resteers / ##Frontend_Latency ) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES_PS,,,,,,#NA,,CoreMetric,Branch Misprediction Cost: Fraction of TopDown slots wasted per branch misprediction (jeclear and baclear),,3.3,Branch_Mispredicts,300.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Core,IpMispredict,,,,,,,,,,,INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES_PS,,,,Metric,Number of Instructions per non-speculative Branch Misprediction (JEClear),,3.4,Branch_Mispredicts,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Core,CORE_CLKS,,,,,,,,,,,,,( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) if #EBS_Mode else ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CLKS,,Count,Core actual clocks when any thread is active on the physical core,,3.3,SMT,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Memory,Load_Miss_Real_Latency,,,,,L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS_PS + MEM_LOAD_RETIRED.FB_HIT_PS ),,,,,,L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS ),,#NA,,Metric,Actual Average Latency for L1 data-cache miss demand loads (in core cycles),,3.1,Memory_Bound;Memory_Lat,1000.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Memory,MLP,,,,,,,,,,,L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES,,#NA,,Metric,Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-thread),,3.4,Memory_Bound;Memory_BW,10.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Memory,Page_Walks_Utilization,,,,,( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CORE_CLKS ),( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * CORE_CLKS ),( ITLB_MISSES.WALK_DURATION:c1 + DTLB_LOAD_MISSES.WALK_DURATION:c1 + DTLB_STORE_MISSES.WALK_DURATION:c1 + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / CORE_CLKS,,,,( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / CORE_CLKS,,#NA,,CoreMetric,Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses,> 0.5,3.1,TLB,1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Memory,L1D_Cache_Fill_BW,,,,,,,,,,,64 * L1D.REPLACEMENT / #OneBillion / Time,,#NA,,CoreMetric,Average data fill bandwidth to the L1 data cache [GB / sec],,3.4,Memory_BW,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Memory,L2_Cache_Fill_BW,,,,,,,,,,,64 * L2_LINES_IN.ALL / #OneBillion / Time,,#NA,,CoreMetric,Average data fill bandwidth to the L2 cache [GB / sec],,3.4,Memory_BW,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Memory,L3_Cache_Fill_BW,,,,,,,,,,,64 * LONGEST_LAT_CACHE.MISS / #OneBillion / Time,,#NA,,CoreMetric,Average per-core data fill bandwidth to the L3 cache [GB / sec],,3.5,Memory_BW,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Memory,L3_Cache_Access_BW,,,,,64 * OFFCORE_REQUESTS.ALL_REQUESTS / #OneBillion / Time,,,,,,,,#NA,,CoreMetric,Average per-core data fill bandwidth to the L3 cache [GB / sec],,3.5,Memory_BW,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Memory,L1MPKI,,,,,1000 * MEM_LOAD_RETIRED.L1_MISS_PS / INST_RETIRED.ANY,,,,,,1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY,,#NA,,Metric,L1 cache true misses per kilo instruction for retired demand loads,,3.3,Cache_Misses;,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Memory,L2MPKI,,,,,1000 * MEM_LOAD_RETIRED.L2_MISS_PS / INST_RETIRED.ANY,,,,,,1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY,,#NA,,Metric,L2 cache true misses per kilo instruction for retired demand loads,,3.3,Cache_Misses;,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Memory,L2MPKI_All,,,,,,,1000 * L2_RQSTS.MISS / INST_RETIRED.ANY,,,,1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY,,#NA,,Metric,L2 cache misses per kilo instruction for all request types (including speculative),,3.5,Cache_Misses;,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Memory,L2HPKI_All,,,,,,,1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY,,,,1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY,,#NA,,Metric,L2 cache hits per kilo instruction for all request types (including speculative),,3.5,Cache_Misses;,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.Memory,L3MPKI,,,,,1000 * MEM_LOAD_RETIRED.L3_MISS_PS / INST_RETIRED.ANY,,,,1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS_PS / INST_RETIRED.ANY,,1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS / INST_RETIRED.ANY,,#NA,,Metric,L3 cache true misses per kilo instruction for retired demand loads,,3.3,Cache_Misses;,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,CPU_Utilization,,,,,,,,,,,,,CPU_CLK_UNHALTED.REF_TSC / TSC,,Metric,Average CPU Utilization,,2.5,Summary,200.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,Average_Frequency,,,,,,,,,,,,,Base_Frequency * Turbo_Utilization / 1000,,SystemMetric,Measured Average Frequency for unhalted processors [GHz],,3.4,Summary;Power,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,GFLOPs,,,,,,,( #FLOP_Count / #OneBillion ) / #DurationTimeInSeconds,,#NA,,,,( #FLOP_Count / #OneBillion ) / #DurationTimeInSeconds,,Metric,Giga Floating Point Operations Per Second,,3.4,FLOPS;Summary,200.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,Turbo_Utilization,,,,,,,,,,,,,CLKS / CPU_CLK_UNHALTED.REF_TSC,,CoreMetric,Average Frequency Utilization relative nominal frequency,,3.0,Power,10.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,SMT_2T_Utilization,,,,,,,,,,,,,1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0,,CoreMetric,Fraction of cycles where both hardware threads were active,,3.1,SMT;Summary,1.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,Kernel_Utilization,,,,,,,,,,,,,CPU_CLK_UNHALTED.REF_TSC:sup / CPU_CLK_UNHALTED.REF_TSC,,Metric,Fraction of cycles spent in Kernel mode,> 0.1,3.1,,1.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,DRAM_BW_Use,,,,,,,,,,,,( 64 * ( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) / #OneBillion ) / #DurationTimeInSeconds,64 * ( UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL ) / #OneMillion / #DurationTimeInSeconds / 1000,,SystemMetric,Average external Memory Bandwidth Use for reads and writes [GB / sec],; $issueBW,3.4,Memory_BW,200.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,DRAM_Read_Latency,,,,#OneBillion * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( Socket_CLKS / Time ),#OneBillion * ( UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_REQUESTS.DATA_READ ) / ( Socket_CLKS / Time ),,,#OneBillion * ( UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182 / UNC_C_TOR_INSERTS.MISS_OPCODE:opc=0x182 ) / ( Socket_CLKS / Time ),,,,"#OneBillion * ( ""UNC_C_TOR_OCCUPANCY.MISS_OPCODE/Match=0x182"" / ""UNC_C_TOR_INSERTS.MISS_OPCODE/Match=0x182"" ) / ( Socket_CLKS / Time )",#NA,,SystemMetric,Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches,,3.5,Memory_Lat,1000.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,DRAM_Parallel_Reads,,,,UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1,UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_OCCUPANCY.DATA_READ:c1,,,UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182 / UNC_C_TOR_OCCUPANCY.MISS_OPCODE:opc=0x182:c1,,,,"""UNC_C_TOR_OCCUPANCY.MISS_OPCODE/Match=0x182"" / ""UNC_C_TOR_OCCUPANCY.MISS_OPCODE/Match=0x182:c1""",#NA,,SystemMetric,Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches,,3.5,Memory_BW,100.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,MEM_PMM_Read_Latency,,,,( #OneBillion * ( UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS ) / UNC_M_CLOCKTICKS:one_unit ) if #PMM_App_Direct else #NA,,,,,,,,,#NA,,SystemMetric,Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches,,3.5,Memory_Lat,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,PMM_Read_BW,,,,( ( 64 * UNC_M_PMM_RPQ_INSERTS / #OneBillion ) / #DurationTimeInSeconds ) if #PMM_App_Direct else #NA,,,,,,,,,#NA,,SystemMetric,Average 3DXP Memory Bandwidth Use for reads [GB / sec],,3.5,Memory_BW,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,PMM_Write_BW,,,,( ( 64 * UNC_M_PMM_WPQ_INSERTS / #OneBillion ) / #DurationTimeInSeconds ) if #PMM_App_Direct else #NA,,,,,,,,,#NA,,SystemMetric,Average 3DXP Memory Bandwidth Use for Writes [GB / sec],,3.5,Memory_BW,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,Power,,,,,,,,( FREERUN_PKG_ENERGY_STATUS * #Energy_Unit + 15.6 * FREERUN_DRAM_ENERGY_STATUS ) / ( #DurationTimeInSeconds * #OneMillion ),UNC_PKG_ENERGY_STATUS * #Energy_Unit / ( #DurationTimeInSeconds * #OneMillion ),( FREERUN_PKG_ENERGY_STATUS + FREERUN_DRAM_ENERGY_STATUS ) * #Energy_Unit / ( #DurationTimeInSeconds * #OneMillion ),UNC_PKG_ENERGY_STATUS * #Energy_Unit / ( #DurationTimeInSeconds * #OneMillion ),,#NA,,SystemMetric,Total package Power in Watts,,2.9,Power,200.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,Time,,,,,,,,,,,,,#DurationTimeInSeconds,,SystemMetric,Run duration time in seconds,< 1,3.4,Summary,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,MUX,,,,,,,,,,,,,CPU_CLK_UNHALTED.THREAD_P / CPU_CLK_UNHALTED.THREAD,,Clocks,PerfMon Event Multiplexing accuracy indicator,( > 1.1 | < 0.9 ),3.1,Summary,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Info.System,Socket_CLKS,,,,UNC_CHA_CLOCKTICKS:one_unit,,,,,,,,UNC_C_CLOCKTICKS:one_unit,UNC_CLOCK.SOCKET,,Count,Socket actual clocks when any core is active on that socket,,3.4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
.,auxiliary,,,,,,,,,,,,,,,-,,,2.5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#FLOP_Count,,,,( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ),,,( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ),,#NA,,,,( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ),,Count,Floating Point computational (arithmetic) Operations Count,,3.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Fetched_Uops,,,,,( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) if #Model in ['KBLR' 'CFL' 'CLX'] else ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ),,,,,,,,( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) ,,Count,,,3.4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Recovery_Cycles,,,,,,,,,,,,,( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) if #SMT_on else INT_MISC.RECOVERY_CYCLES,,Count,,,3.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Execute_Cycles,,,,,( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1,,( UOPS_EXECUTED.CORE:c1 / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC,,( UOPS_EXECUTED.CORE:c1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE:c1,,( UOPS_EXECUTED.CORE:c1 / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC,,( UOPS_DISPATCHED.CORE:c1 / 2 ) if #SMT_on else UOPS_DISPATCHED.CORE:c1,,Count,,,2.9,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#ITLB_Miss_Cycles,,,,,( 14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_ACTIVE ),,( 14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION:c1 + 7 * ITLB_MISSES.WALK_COMPLETED ),,( 14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION ),,,,( 12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION ),,Count,,,3.4,TLB,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Frontend_RS_Empty_Cycles,,,,,#NA,,,,,,,,RS_EVENTS.EMPTY_CYCLES if ( Frontend_Latency > 0.1 ) else 0,,Count,,,3.1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Frontend_Latency_Cycles,,,,,,,#NA,,,,,,"min( CPU_CLK_UNHALTED.THREAD , IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE )",,Count,,,3.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#STALLS_MEM_ANY,,,,,,,#NA,,,,"min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_LDM_PENDING )",,"min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.STALLS_L1D_PENDING )",,Count,,,3.1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#STALLS_TOTAL,,,,,,,#NA,,,,"min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_EXECUTE )",,"min( CPU_CLK_UNHALTED.THREAD , CYCLE_ACTIVITY.CYCLES_NO_DISPATCH )",,Count,,,2.9,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#ORO_DRD_Any_Cycles,,,,,,,,,,,,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD )",,Count,,,3.1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#ORO_DRD_BW_Cycles,,,,,,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4 )",,,,,,"min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c6 )",,Count,,,3.1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#LOAD_L1_MISS,,,,,MEM_LOAD_RETIRED.L2_HIT_PS + MEM_LOAD_RETIRED.L3_HIT_PS + MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS + MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS,,,,MEM_LOAD_UOPS_RETIRED.L2_HIT_PS + MEM_LOAD_UOPS_RETIRED.L3_HIT_PS + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT_PS + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM_PS + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS_PS,,MEM_LOAD_UOPS_RETIRED.L2_HIT_PS + MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS_PS,,#NA,,Count,,,3.2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#LOAD_L1_MISS_NET,,,,( #LOAD_L1_MISS + MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS + MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS + MEM_LOAD_RETIRED.LOCAL_PMM_PS + MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM_PS ) if #PMM_App_Direct else ( #LOAD_L1_MISS + MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS + MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS ),#LOAD_L1_MISS + MEM_LOAD_RETIRED.L3_MISS_PS,,,#LOAD_L1_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS,#LOAD_L1_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS_PS,#LOAD_L1_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM_PS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM_PS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM_PS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD_PS,#LOAD_L1_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS,,#NA,,Count,,,3.4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#LOAD_L2_HIT,,,,,MEM_LOAD_RETIRED.L2_HIT_PS * ( 1 + MEM_LOAD_RETIRED.FB_HIT_PS / #LOAD_L1_MISS_NET ),,,,,,,,#NA,,Count,,,3.1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#LOAD_LCL_MEM,,,,MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS * ( 1 + MEM_LOAD_RETIRED.FB_HIT_PS / #LOAD_L1_MISS_NET ),,,,MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,,,,,,,3.4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#LOAD_LCL_PMM,,,,( MEM_LOAD_RETIRED.LOCAL_PMM_PS * ( 1 + MEM_LOAD_RETIRED.FB_HIT_PS / #LOAD_L1_MISS_NET ) ) if #PMM_App_Direct else #NA,,,,,,,,,,,Count,,,3.5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#LOAD_RMT_PMM,,,,( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM_PS * ( 1 + MEM_LOAD_RETIRED.FB_HIT_PS / #LOAD_L1_MISS_NET ) ) if #PMM_App_Direct else #NA,,,,,,,,,,,Count,,,3.5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#LOAD_RMT_MEM,,,,MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS * ( 1 + MEM_LOAD_RETIRED.FB_HIT_PS / #LOAD_L1_MISS_NET ),,,,MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,,,,,,,3.1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#LOAD_RMT_HITM,,,,MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS * ( 1 + MEM_LOAD_RETIRED.FB_HIT_PS / #LOAD_L1_MISS_NET ),,,,MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,,,,,,,3.1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#LOAD_RMT_FWD,,,,MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS * ( 1 + MEM_LOAD_RETIRED.FB_HIT_PS / #LOAD_L1_MISS_NET ),,,,MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD_PS * ( 1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS / #LOAD_L1_MISS_NET ),,,,,,,,3.1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Few_Uops_Executed_Threshold,,,,,EXE_ACTIVITY.2_PORTS_UTIL if ( IPC > 1.8 ) else 0,,UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( IPC > 1.8 ) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC,,UOPS_EXECUTED.CORE:c3 if ( IPC > 1.8 ) else UOPS_EXECUTED.CORE:c2,,UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if ( IPC > 1.8 ) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC,,UOPS_DISPATCHED.THREAD:c3 if ( IPC > 1.8 ) else UOPS_DISPATCHED.THREAD:c2,,Count,,,3.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Backend_Bound_Cycles,,,,,( EXE_ACTIVITY.EXE_BOUND_0_PORTS + EXE_ACTIVITY.1_PORTS_UTIL + #Few_Uops_Executed_Threshold ) + ( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) ,,( CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - #Few_Uops_Executed_Threshold - #Frontend_RS_Empty_Cycles + RESOURCE_STALLS.SB ),,( #STALLS_TOTAL + ( UOPS_EXECUTED.CORE:c1 - #Few_Uops_Executed_Threshold ) / 2 - #Frontend_RS_Empty_Cycles + RESOURCE_STALLS.SB ) if #SMT_on else ( #STALLS_TOTAL + UOPS_EXECUTED.CORE:c1 - #Few_Uops_Executed_Threshold - #Frontend_RS_Empty_Cycles + RESOURCE_STALLS.SB ),,( #STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - #Few_Uops_Executed_Threshold - #Frontend_RS_Empty_Cycles + RESOURCE_STALLS.SB ),,( #STALLS_TOTAL + UOPS_DISPATCHED.THREAD:c1 - #Few_Uops_Executed_Threshold - #Frontend_RS_Empty_Cycles + RESOURCE_STALLS.SB ),,Count,,,3.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Memory_Bound_Fraction,,,,,( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / #Backend_Bound_Cycles,,( CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB ) / #Backend_Bound_Cycles,,,,,,( #STALLS_MEM_ANY + RESOURCE_STALLS.SB ) / #Backend_Bound_Cycles,,Fraction,,,3.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#L2_Bound_Ratio,,,,,( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CLKS,,,,,,,,#NA,,Fraction,,,3.1,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#MEM_Bound_Ratio,,,,,CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + #L2_Bound_Ratio - L2_Bound,,,,,,,,,,Fraction,,,3.4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Mem_L3_Hit_Fraction,,,,,#NA,,,,MEM_LOAD_UOPS_RETIRED.L3_HIT_PS / ( MEM_LOAD_UOPS_RETIRED.L3_HIT_PS + #Mem_L3_Weight * MEM_LOAD_UOPS_RETIRED.L3_MISS_PS ),,MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS / ( MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS + #Mem_L3_Weight * MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS ),MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS / ( MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS + #Mem_L3_Weight * MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS ),MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS / ( MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS + #Mem_L3_Weight * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS ),,Fraction,,,3.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Mem_DDR_Hit_Fraction,,,,( ( 19 * #LOAD_RMT_MEM + 10 * ( #LOAD_LCL_MEM + #LOAD_RMT_FWD + #LOAD_RMT_HITM ) ) / ( ( 19 * #LOAD_RMT_MEM + 10 * ( #LOAD_LCL_MEM + #LOAD_RMT_FWD + #LOAD_RMT_HITM ) ) + ( 25 * #LOAD_LCL_PMM + 33 * #LOAD_RMT_PMM ) ) ) if #PMM_App_Direct else #NA,,,,,,,,,#NA,,Fraction,,,3.5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Mispred_Clears_Fraction,,,,,,,,,,,,,BR_MISP_RETIRED.ALL_BRANCHES_PS / ( BR_MISP_RETIRED.ALL_BRANCHES_PS + MACHINE_CLEARS.COUNT ),,Fraction,,,3.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Retire_Uop_Fraction,,,,,,,,,,,,,UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY,,Fraction,,,2.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Pipeline_Width,,,,,,,,,,,,,4,,Constant,,,2.1,TopDownL2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Mem_L3_Weight,,,,,#NA,,,,,,,,7,,Constant,,,2.5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Mem_STLB_Hit_Cost,,,,,9,,,,8,,,,7,,Constant,,,3.2,TLB,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#BAClear_Cost,,,,,9,,,,,,,,12,,Constant,,,3.3,Unknown_Branches,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#MS_Switches_Cost,,,,,,,,,2,,,,3,,Constant,,,3.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#OneMillion,,,,,,,,,,,,,1000000,,Constant,,,2.6,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#OneBillion,,,,,,,,,,,,,1000000000,,Constant,,,3.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#Energy_Unit,,,,,,,,,61,,15.6,,,,Constant,,,3.0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#DurationTimeInSeconds,,,,,,,,,,,,,,,Count,,,2.7,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#SMT_on,,,,,,,,,,,,,,,ExternalParameter,,,2.7,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#EBS_Mode,,,,,,,,,,,,,1,,ExternalParameter,Use ratios that apply to Event Based Sampling where applicable (may increase counter multiplexing),,3.3,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,Base_Frequency,,,,,,,,,,,,,,,ExternalParameter,Base frequency of the CPU in MHz (max non-turbo frequency in CPU brand string). This is an input parameter by the invoking tool. Negative value (of Turbo_Utilization) is reported by default to warn the user.,,3.4,Summary,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,Memory,,,,1 if #Model in ['CLX'] else 0,,,,,,,,,0,,ExternalParameter,,,3.5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#PMM_App_Direct,,,,1 if Memory == 1 else 0,,,,,,,,,0,,ExternalParameter,,,3.5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Aux,#HighIPC,,,,,,,,,,,,,IPC / #Pipeline_Width,,Metric,,> 0.5,3.2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,