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#Copyright (c) 2022 Intel Corporation
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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#
#
#
EVEX_INSTRUCTIONS()::
# EMITTING VP4DPWSSD (VP4DPWSSD-512-1)
{
ICLASS:      VP4DPWSSD
CPL:         3
CATEGORY:    AVX512_4VNNIW
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_4VNNIW_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX 
PATTERN:    EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] MODRM() BCRC=0  VL512  W0    ESIZE_32_BITS() NELEM_TUPLE1_4X()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32
IFORM:       VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
}


# EMITTING VP4DPWSSDS (VP4DPWSSDS-512-1)
{
ICLASS:      VP4DPWSSDS
CPL:         3
CATEGORY:    AVX512_4VNNIW
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_4VNNIW_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX 
PATTERN:    EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] MODRM() BCRC=0  VL512  W0    ESIZE_32_BITS() NELEM_TUPLE1_4X()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32
IFORM:       VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
}