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#Copyright (c) 2020 Intel Corporation
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# EXTRQ xmm:w:q, imm8, imm8     66 0F 78 /0 ib ib
# EXTRQ xmm:w:q, xmm:r:w        66 0F 79 /r

{
ICLASS    : EXTRQ
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : SSE4a
ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION AMDONLY
PATTERN   : 0x0F 0x78 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() UIMM8_1()
OPERANDS  : REG0=XMM_B():w:q      IMM0:r:b IMM1:r:b
PATTERN   : 0x0F 0x79 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] 
OPERANDS  : REG0=XMM_R():w:q      REG1=XMM_B():r:dq    
}

# INSERTQ xmm:w:q  xmm:r:q, imm8, imm8  f2 0f 78 /r ib ib
# INSERTQ xmm:w:q  xmm:r:dq,            f2 0f 79 /r

{
ICLASS    : INSERTQ
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : SSE4a
ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION AMDONLY
PATTERN   : 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()
OPERANDS  : REG0=XMM_R():w:q      REG1=XMM_B():r:q    IMM0:r:b IMM1:r:b
PATTERN   : 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 
OPERANDS  : REG0=XMM_R():w:q      REG1=XMM_B():r:dq    
}


# MOVNTSD mem64:w:q, xmm:r:q          f2 0f 2b /r
# MOVNTSS mem32:w:d, xmm:r:d          f3 0f 2b /r

{
ICLASS    : MOVNTSD
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE4a
ATTRIBUTES: NONTEMPORAL AMDONLY
PATTERN   : 0x0F 0x2B f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 
OPERANDS  : MEM0:w:q      REG0=XMM_R():r:q    
}
{
ICLASS    : MOVNTSS
CPL       : 3
CATEGORY  : DATAXFER
EXTENSION : SSE4a
ATTRIBUTES: NONTEMPORAL AMDONLY
PATTERN   : 0x0F 0x2B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 
OPERANDS  : MEM0:w:d      REG0=XMM_R():r:d   
}

#########################################################################################################
# These next one is not part of SSE4a or SSE5.

# LZCNT reg16, reg/mem16 F30FBD /r
# LZCNT reg32, reg/mem32 F30FBD /r
# LZCNT reg64, reg/mem64 F30FBD /r

{
ICLASS    : LZCNT
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : AMD
FLAGS     : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ]
PATTERN   : 0x0F 0xBD f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 
OPERANDS  : REG0=GPRv_R():w:v     MEM0:r:v     
PATTERN   : 0x0F 0xBD f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():w:v     REG1=GPRv_B():r:v
}


{
ICLASS    : BSR
VERSION   : 1
COMMENT   : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix.  This version replaces the normal version of BSR
CPL       : 3
CATEGORY  : BITBYTE
EXTENSION : BASE
ISA_SET   : I386
FLAGS     : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
PATTERN   : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
OPERANDS  : REG0=GPRv_R():cw MEM0:r:v

PATTERN   : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
OPERANDS  : REG0=GPRv_R():cw REG1=GPRv_B():r
}