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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
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#
AVX_INSTRUCTIONS()::
# EMITTING LDTILECFG (LDTILECFG-128-1)
{
ICLASS:      LDTILECFG
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TILE
EXCEPTIONS:  AMX-E1
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     VV1 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    MEM0:r:m512
IFORM:       LDTILECFG_MEM
}


# EMITTING STTILECFG (STTILECFG-128-1)
{
ICLASS:      STTILECFG
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TILE
EXCEPTIONS:  AMX-E2
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     VV1 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    MEM0:w:m512
IFORM:       STTILECFG_MEM
}


# EMITTING TDPBF16PS (TDPBF16PS-128-1)
{
ICLASS:      TDPBF16PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_BF16
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     VV1 0x5C VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:2bf16 REG2=TMM_N():r:tv:2bf16
IFORM:       TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16
}


# EMITTING TDPBSSD (TDPBSSD-128-1)
{
ICLASS:      TDPBSSD
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_INT8
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     VV1 0x5E VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:i32 REG1=TMM_B():r:tv:4i8 REG2=TMM_N():r:tv:4i8
IFORM:       TDPBSSD_TMMi32_TMM4i8_TMM4i8
}


# EMITTING TDPBSUD (TDPBSUD-128-1)
{
ICLASS:      TDPBSUD
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_INT8
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     VV1 0x5E VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:i32 REG1=TMM_B():r:tv:4i8 REG2=TMM_N():r:tv:4u8
IFORM:       TDPBSUD_TMMi32_TMM4i8_TMM4u8
}


# EMITTING TDPBUSD (TDPBUSD-128-1)
{
ICLASS:      TDPBUSD
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_INT8
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     VV1 0x5E V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:i32 REG1=TMM_B():r:tv:4u8 REG2=TMM_N():r:tv:4i8
IFORM:       TDPBUSD_TMMi32_TMM4u8_TMM4i8
}


# EMITTING TDPBUUD (TDPBUUD-128-1)
{
ICLASS:      TDPBUUD
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_INT8
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     VV1 0x5E VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:u32 REG1=TMM_B():r:tv:4u8 REG2=TMM_N():r:tv:4u8
IFORM:       TDPBUUD_TMMu32_TMM4u8_TMM4u8
}


# EMITTING TILELOADD (TILELOADD-128-1)
{
ICLASS:      TILELOADD
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TILE
EXCEPTIONS:  AMX-E3
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0x4B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32
IFORM:       TILELOADD_TMMu32_MEMu32
}


# EMITTING TILELOADDT1 (TILELOADDT1-128-1)
{
ICLASS:      TILELOADDT1
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TILE
EXCEPTIONS:  AMX-E3
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0x4B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32
IFORM:       TILELOADDT1_TMMu32_MEMu32
}


# EMITTING TILERELEASE (TILERELEASE-128-1)
{
ICLASS:      TILERELEASE
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TILE
EXCEPTIONS:  AMX-E6
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     VV1 0x49 VNP V0F38 MOD[0b11] MOD=3 REG[0b000] RM[0b000] W0 VL128 mode64 NOVSR
OPERANDS:    
IFORM:       TILERELEASE
}


# EMITTING TILESTORED (TILESTORED-128-1)
{
ICLASS:      TILESTORED
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TILE
EXCEPTIONS:  AMX-E3
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0x4B VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
OPERANDS:    MEM0:w:ptr:u32 REG0=TMM_R():r:tv:u32
IFORM:       TILESTORED_MEMu32_TMMu32
}


# EMITTING TILEZERO (TILEZERO-128-1)
{
ICLASS:      TILEZERO
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TILE
EXCEPTIONS:  AMX-E5
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     VV1 0x49 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[0b000] W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:u32
IFORM:       TILEZERO_TMMu32
}