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#
#Copyright (c) 2023 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
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#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
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#END_LEGAL


###############################################################
# Support APX EGPRs with the EVEX.vvvvv encoding field
###############################################################
###############################################################
# Historicity, we use VGPR*_N() NT for both VEX and EVEX instructions as the fifth
# EVEX.v bit was not in use (max 16 GPRs).
# Now, with EGPRs support, we should check all five EVEX.vvvvv bits.
# Create a new operand NT and separates the *GPR*_N NT to VEX and EVEX
# versions.
###############################################################
# GPRs/EGPRs encoded with EVEX.vvvvv. Available only with APX mode64

xed_reg_enum_t VGPRv_N3()::   
EOSZ=1 | OUTREG=VGPR16_N3() 
EOSZ=2 | OUTREG=VGPR32_N3()
EOSZ=3 | OUTREG=VGPR64_N3() 


xed_reg_enum_t VGPR8_N3()::
mode64 | OUTREG=VGPR8_N3_64()

xed_reg_enum_t VGPR16_N3()::
mode64 | OUTREG=VGPR16_N3_64()

xed_reg_enum_t VGPR32_N3()::
mode64 | OUTREG=VGPR32_N3_64()

xed_reg_enum_t VGPR64_N3()::
mode64 | OUTREG=VGPR64_N3_64()


# It's odd but XED ILD stores the exact bits values of VEXDEST[0-3] and inverts
# the VEXDEST4 bit.
xed_reg_enum_t VGPR64_N3_64()::
VEXDEST4=0 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_RAX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_RCX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_RDX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=4   | OUTREG=XED_REG_RBX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_RSP
VEXDEST4=0 VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_RBP
VEXDEST4=0 VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_RSI
VEXDEST4=0 VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_RDI
VEXDEST4=0 VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R8
VEXDEST4=0 VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R9
VEXDEST4=0 VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R10
VEXDEST4=0 VEXDEST3=0 VEXDEST210=4   | OUTREG=XED_REG_R11
VEXDEST4=0 VEXDEST3=0 VEXDEST210=3   | OUTREG=XED_REG_R12
VEXDEST4=0 VEXDEST3=0 VEXDEST210=2   | OUTREG=XED_REG_R13
VEXDEST4=0 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R14
VEXDEST4=0 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R15

VEXDEST4=1 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_R16 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_R17 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_R18 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=4   | OUTREG=XED_REG_R19 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_R20 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_R21 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_R22 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_R23 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R24 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R25 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R26 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=4   | OUTREG=XED_REG_R27 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=3   | OUTREG=XED_REG_R28 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=2   | OUTREG=XED_REG_R29 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R30 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R31 HAS_EGPR=1



xed_reg_enum_t VGPR32_N3_64()::
VEXDEST4=0 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_EAX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_ECX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_EDX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=4   | OUTREG=XED_REG_EBX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_ESP
VEXDEST4=0 VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_EBP
VEXDEST4=0 VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_ESI
VEXDEST4=0 VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_EDI
VEXDEST4=0 VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R8D
VEXDEST4=0 VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R9D
VEXDEST4=0 VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R10D
VEXDEST4=0 VEXDEST3=0 VEXDEST210=4   | OUTREG=XED_REG_R11D
VEXDEST4=0 VEXDEST3=0 VEXDEST210=3   | OUTREG=XED_REG_R12D
VEXDEST4=0 VEXDEST3=0 VEXDEST210=2   | OUTREG=XED_REG_R13D
VEXDEST4=0 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R14D
VEXDEST4=0 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R15D

VEXDEST4=1 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_R16D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_R17D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_R18D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=4   | OUTREG=XED_REG_R19D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_R20D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_R21D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_R22D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_R23D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R24D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R25D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R26D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=4   | OUTREG=XED_REG_R27D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=3   | OUTREG=XED_REG_R28D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=2   | OUTREG=XED_REG_R29D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R30D HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R31D HAS_EGPR=1



xed_reg_enum_t VGPR16_N3_64()::
VEXDEST4=0 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_AX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_CX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_DX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=4   | OUTREG=XED_REG_BX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_SP
VEXDEST4=0 VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_BP
VEXDEST4=0 VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_SI
VEXDEST4=0 VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_DI
VEXDEST4=0 VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R8W
VEXDEST4=0 VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R9W
VEXDEST4=0 VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R10W
VEXDEST4=0 VEXDEST3=0 VEXDEST210=4   | OUTREG=XED_REG_R11W
VEXDEST4=0 VEXDEST3=0 VEXDEST210=3   | OUTREG=XED_REG_R12W
VEXDEST4=0 VEXDEST3=0 VEXDEST210=2   | OUTREG=XED_REG_R13W
VEXDEST4=0 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R14W
VEXDEST4=0 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R15W

VEXDEST4=1 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_R16W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_R17W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_R18W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=4   | OUTREG=XED_REG_R19W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_R20W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_R21W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_R22W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_R23W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R24W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R25W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R26W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=4   | OUTREG=XED_REG_R27W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=3   | OUTREG=XED_REG_R28W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=2   | OUTREG=XED_REG_R29W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R30W HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R31W HAS_EGPR=1



xed_reg_enum_t VGPR8_N3_64()::
VEXDEST4=0 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_AL
VEXDEST4=0 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_CL
VEXDEST4=0 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_DL
VEXDEST4=0 VEXDEST3=1 VEXDEST210=4   | OUTREG=XED_REG_BL
VEXDEST4=0 VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_SPL
VEXDEST4=0 VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_BPL
VEXDEST4=0 VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_SIL
VEXDEST4=0 VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_DIL

VEXDEST4=0 VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R8B
VEXDEST4=0 VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R9B
VEXDEST4=0 VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R10B
VEXDEST4=0 VEXDEST3=0 VEXDEST210=4   | OUTREG=XED_REG_R11B
VEXDEST4=0 VEXDEST3=0 VEXDEST210=3   | OUTREG=XED_REG_R12B
VEXDEST4=0 VEXDEST3=0 VEXDEST210=2   | OUTREG=XED_REG_R13B
VEXDEST4=0 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R14B
VEXDEST4=0 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R15B

VEXDEST4=1 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_R16B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_R17B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_R18B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=4   | OUTREG=XED_REG_R19B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_R20B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_R21B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_R22B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_R23B HAS_EGPR=1
 
VEXDEST4=1 VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R24B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R25B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R26B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=4   | OUTREG=XED_REG_R27B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=3   | OUTREG=XED_REG_R28B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=2   | OUTREG=XED_REG_R29B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R30B HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R31B HAS_EGPR=1



########## APX POP2/PUSH2 ##########

xed_reg_enum_t VGPR64_N3_NORSP()::
VEXDEST4=0 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_RAX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_RCX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_RDX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=4   | OUTREG=XED_REG_RBX
VEXDEST4=0 VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_ERROR  # NO RSP
VEXDEST4=0 VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_RBP
VEXDEST4=0 VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_RSI
VEXDEST4=0 VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_RDI
VEXDEST4=0 VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R8
VEXDEST4=0 VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R9
VEXDEST4=0 VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R10
VEXDEST4=0 VEXDEST3=0 VEXDEST210=4   | OUTREG=XED_REG_R11
VEXDEST4=0 VEXDEST3=0 VEXDEST210=3   | OUTREG=XED_REG_R12
VEXDEST4=0 VEXDEST3=0 VEXDEST210=2   | OUTREG=XED_REG_R13
VEXDEST4=0 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R14
VEXDEST4=0 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R15
#EGPRs
VEXDEST4=1 VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_R16 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_R17 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_R18 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=4   | OUTREG=XED_REG_R19 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_R20 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_R21 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_R22 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_R23 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R24 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R25 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R26 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=4   | OUTREG=XED_REG_R27 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=3   | OUTREG=XED_REG_R28 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=2   | OUTREG=XED_REG_R29 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R30 HAS_EGPR=1
VEXDEST4=1 VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R31 HAS_EGPR=1


xed_reg_enum_t GPR64_B_NORSP()::
REXB4=0 REXB=0 RM=0x0  | OUTREG=XED_REG_RAX
REXB4=0 REXB=0 RM=0x1  | OUTREG=XED_REG_RCX
REXB4=0 REXB=0 RM=0x2  | OUTREG=XED_REG_RDX
REXB4=0 REXB=0 RM=0x3  | OUTREG=XED_REG_RBX
REXB4=0 REXB=0 RM=0x4  | OUTREG=XED_REG_ERROR # No RSP
REXB4=0 REXB=0 RM=0x5  | OUTREG=XED_REG_RBP
REXB4=0 REXB=0 RM=0x6  | OUTREG=XED_REG_RSI
REXB4=0 REXB=0 RM=0x7  | OUTREG=XED_REG_RDI
REXB4=0 REXB=1 RM=0x0  | OUTREG=XED_REG_R8
REXB4=0 REXB=1 RM=0x1  | OUTREG=XED_REG_R9
REXB4=0 REXB=1 RM=0x2  | OUTREG=XED_REG_R10
REXB4=0 REXB=1 RM=0x3  | OUTREG=XED_REG_R11
REXB4=0 REXB=1 RM=0x4  | OUTREG=XED_REG_R12
REXB4=0 REXB=1 RM=0x5  | OUTREG=XED_REG_R13
REXB4=0 REXB=1 RM=0x6  | OUTREG=XED_REG_R14
REXB4=0 REXB=1 RM=0x7  | OUTREG=XED_REG_R15
#EGPRs
REXB4=1 REXB=0 RM=0x0  | OUTREG=XED_REG_R16 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x1  | OUTREG=XED_REG_R17 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x2  | OUTREG=XED_REG_R18 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x3  | OUTREG=XED_REG_R19 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x4  | OUTREG=XED_REG_R20 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x5  | OUTREG=XED_REG_R21 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x6  | OUTREG=XED_REG_R22 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x7  | OUTREG=XED_REG_R23 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x0  | OUTREG=XED_REG_R24 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x1  | OUTREG=XED_REG_R25 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x2  | OUTREG=XED_REG_R26 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x3  | OUTREG=XED_REG_R27 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x4  | OUTREG=XED_REG_R28 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x5  | OUTREG=XED_REG_R29 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x6  | OUTREG=XED_REG_R30 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x7  | OUTREG=XED_REG_R31 HAS_EGPR=1



########################################################

xed_reg_enum_t DFV()::
# Enumeration for EVEX.[OF, SF, ZF, CF] default flags.
# The register index represents the default flags values. For example:
# DFV10.index == 10 == 0b1010  ->  OF=1, SF=0, ZF=1, CF=0
VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_DFV0
VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_DFV1
VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_DFV2
VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_DFV3
VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_DFV4
VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_DFV5
VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_DFV6
VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_DFV7

VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_DFV8
VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_DFV9
VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_DFV10
VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_DFV11
VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_DFV12
VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_DFV13
VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_DFV14
VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_DFV15