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#Copyright (c) 2023 Intel Corporation
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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#
#
#
EVEX_INSTRUCTIONS()::
# EMITTING LDTILECFG (LDTILECFG-128-2)
{
ICLASS:      LDTILECFG
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     APX_F_AMX
EXCEPTIONS:  AMX-E1-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    MEM0:r:m512
IFORM:       LDTILECFG_MEM_APX
}


# EMITTING STTILECFG (STTILECFG-128-2)
{
ICLASS:      STTILECFG
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     APX_F_AMX
EXCEPTIONS:  AMX-E2-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    MEM0:w:m512
IFORM:       STTILECFG_MEM_APX
}


# EMITTING TILELOADD (TILELOADD-128-2)
{
ICLASS:      TILELOADD
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     APX_F_AMX
EXCEPTIONS:  AMX-E3-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_NO_SCALE NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     EVV 0x4B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 UBIT=1 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=TMM_R3():w:tv:u32 MEM0:r:ptr:u32
IFORM:       TILELOADD_TMMu32_MEMu32_APX
}


# EMITTING TILELOADDT1 (TILELOADDT1-128-2)
{
ICLASS:      TILELOADDT1
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     APX_F_AMX
EXCEPTIONS:  AMX-E3-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_NO_SCALE NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     EVV 0x4B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 UBIT=1 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=TMM_R3():w:tv:u32 MEM0:r:ptr:u32
IFORM:       TILELOADDT1_TMMu32_MEMu32_APX
}


# EMITTING TILESTORED (TILESTORED-128-2)
{
ICLASS:      TILESTORED
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     APX_F_AMX
EXCEPTIONS:  AMX-E3-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_NO_SCALE NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     EVV 0x4B VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 UBIT=1 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    MEM0:w:ptr:u32 REG0=TMM_R3():r:tv:u32
IFORM:       TILESTORED_MEMu32_TMMu32_APX
}