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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
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AVX_INSTRUCTIONS()::
# EMITTING VBCSTNEBF162PS (VBCSTNEBF162PS-128-1)
{
ICLASS:      VBCSTNEBF162PS
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-5
REAL_OPCODE: Y
PATTERN:     VV1 0xB1 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR
OPERANDS:    REG0=XMM_R():w:dq:f32 MEM0:r:wrd:bf16 EMX_BROADCAST_1TO4_16
IFORM:       VBCSTNEBF162PS_XMMf32_MEMbf16
}


# EMITTING VBCSTNEBF162PS (VBCSTNEBF162PS-256-1)
{
ICLASS:      VBCSTNEBF162PS
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-5
REAL_OPCODE: Y
PATTERN:     VV1 0xB1 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR
OPERANDS:    REG0=YMM_R():w:qq:f32 MEM0:r:wrd:bf16 EMX_BROADCAST_1TO8_16
IFORM:       VBCSTNEBF162PS_YMMf32_MEMbf16
}


# EMITTING VBCSTNESH2PS (VBCSTNESH2PS-128-1)
{
ICLASS:      VBCSTNESH2PS
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-5
REAL_OPCODE: Y
PATTERN:     VV1 0xB1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR
OPERANDS:    REG0=XMM_R():w:dq:f32 MEM0:r:wrd:f16 EMX_BROADCAST_1TO4_16
IFORM:       VBCSTNESH2PS_XMMf32_MEMf16
}


# EMITTING VBCSTNESH2PS (VBCSTNESH2PS-256-1)
{
ICLASS:      VBCSTNESH2PS
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-5
REAL_OPCODE: Y
PATTERN:     VV1 0xB1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR
OPERANDS:    REG0=YMM_R():w:qq:f32 MEM0:r:wrd:f16 EMX_BROADCAST_1TO8_16
IFORM:       VBCSTNESH2PS_YMMf32_MEMf16
}


# EMITTING VCVTNEEBF162PS (VCVTNEEBF162PS-128-1)
{
ICLASS:      VCVTNEEBF162PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xB0 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR
OPERANDS:    REG0=XMM_R():w:dq:f32 MEM0:r:dq:2bf16
IFORM:       VCVTNEEBF162PS_XMMf32_MEM2bf16
}


# EMITTING VCVTNEEBF162PS (VCVTNEEBF162PS-256-1)
{
ICLASS:      VCVTNEEBF162PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xB0 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR
OPERANDS:    REG0=YMM_R():w:qq:f32 MEM0:r:qq:2bf16
IFORM:       VCVTNEEBF162PS_YMMf32_MEM2bf16
}


# EMITTING VCVTNEEPH2PS (VCVTNEEPH2PS-128-1)
{
ICLASS:      VCVTNEEPH2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xB0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR
OPERANDS:    REG0=XMM_R():w:dq:f32 MEM0:r:dq:2f16
IFORM:       VCVTNEEPH2PS_XMMf32_MEM2f16
}


# EMITTING VCVTNEEPH2PS (VCVTNEEPH2PS-256-1)
{
ICLASS:      VCVTNEEPH2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xB0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR
OPERANDS:    REG0=YMM_R():w:qq:f32 MEM0:r:qq:2f16
IFORM:       VCVTNEEPH2PS_YMMf32_MEM2f16
}


# EMITTING VCVTNEOBF162PS (VCVTNEOBF162PS-128-1)
{
ICLASS:      VCVTNEOBF162PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xB0 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR
OPERANDS:    REG0=XMM_R():w:dq:f32 MEM0:r:dq:2bf16
IFORM:       VCVTNEOBF162PS_XMMf32_MEM2bf16
}


# EMITTING VCVTNEOBF162PS (VCVTNEOBF162PS-256-1)
{
ICLASS:      VCVTNEOBF162PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xB0 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR
OPERANDS:    REG0=YMM_R():w:qq:f32 MEM0:r:qq:2bf16
IFORM:       VCVTNEOBF162PS_YMMf32_MEM2bf16
}


# EMITTING VCVTNEOPH2PS (VCVTNEOPH2PS-128-1)
{
ICLASS:      VCVTNEOPH2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xB0 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR
OPERANDS:    REG0=XMM_R():w:dq:f32 MEM0:r:dq:2f16
IFORM:       VCVTNEOPH2PS_XMMf32_MEM2f16
}


# EMITTING VCVTNEOPH2PS (VCVTNEOPH2PS-256-1)
{
ICLASS:      VCVTNEOPH2PS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xB0 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR
OPERANDS:    REG0=YMM_R():w:qq:f32 MEM0:r:qq:2f16
IFORM:       VCVTNEOPH2PS_YMMf32_MEM2f16
}


# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-128-2)
{
ICLASS:      VCVTNEPS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM 
PATTERN:     VV1 0x72 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 NOVSR
OPERANDS:    REG0=XMM_R():w:dq:bf16 REG1=XMM_B():r:dq:f32
IFORM:       VCVTNEPS2BF16_XMMbf16_XMMf32
}

{
ICLASS:      VCVTNEPS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM 
PATTERN:     VV1 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR
OPERANDS:    REG0=XMM_R():w:dq:bf16 MEM0:r:dq:f32
IFORM:       VCVTNEPS2BF16_XMMbf16_MEMf32_VL128
}


# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-256-2)
{
ICLASS:      VCVTNEPS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM 
PATTERN:     VV1 0x72 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 NOVSR
OPERANDS:    REG0=XMM_R():w:dq:bf16 REG1=YMM_B():r:qq:f32
IFORM:       VCVTNEPS2BF16_XMMbf16_YMMf32
}

{
ICLASS:      VCVTNEPS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX_NE_CONVERT
ISA_SET:     AVX_NE_CONVERT
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM 
PATTERN:     VV1 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR
OPERANDS:    REG0=XMM_R():w:dq:bf16 MEM0:r:qq:f32
IFORM:       VCVTNEPS2BF16_XMMbf16_MEMf32_VL256
}