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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
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#
AVX_INSTRUCTIONS()::
# EMITTING VPDPWSUD (VPDPWSUD-128-2)
{
ICLASS:      VPDPWSUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD2 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2i16 REG2=XMM_B():r:dq:2u16
IFORM:       VPDPWSUD_XMMi32_XMM2i16_XMM2u16
}

{
ICLASS:      VPDPWSUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD2 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2i16 MEM0:r:dq:2u16
IFORM:       VPDPWSUD_XMMi32_XMM2i16_MEM2u16
}


# EMITTING VPDPWSUD (VPDPWSUD-256-2)
{
ICLASS:      VPDPWSUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD2 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2i16 REG2=YMM_B():r:qq:2u16
IFORM:       VPDPWSUD_YMMi32_YMM2i16_YMM2u16
}

{
ICLASS:      VPDPWSUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD2 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2i16 MEM0:r:qq:2u16
IFORM:       VPDPWSUD_YMMi32_YMM2i16_MEM2u16
}


# EMITTING VPDPWSUDS (VPDPWSUDS-128-2)
{
ICLASS:      VPDPWSUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD3 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2i16 REG2=XMM_B():r:dq:2u16
IFORM:       VPDPWSUDS_XMMi32_XMM2i16_XMM2u16
}

{
ICLASS:      VPDPWSUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD3 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2i16 MEM0:r:dq:2u16
IFORM:       VPDPWSUDS_XMMi32_XMM2i16_MEM2u16
}


# EMITTING VPDPWSUDS (VPDPWSUDS-256-2)
{
ICLASS:      VPDPWSUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD3 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2i16 REG2=YMM_B():r:qq:2u16
IFORM:       VPDPWSUDS_YMMi32_YMM2i16_YMM2u16
}

{
ICLASS:      VPDPWSUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD3 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2i16 MEM0:r:qq:2u16
IFORM:       VPDPWSUDS_YMMi32_YMM2i16_MEM2u16
}


# EMITTING VPDPWUSD (VPDPWUSD-128-2)
{
ICLASS:      VPDPWUSD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD2 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2u16 REG2=XMM_B():r:dq:2i16
IFORM:       VPDPWUSD_XMMi32_XMM2u16_XMM2i16
}

{
ICLASS:      VPDPWUSD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2u16 MEM0:r:dq:2i16
IFORM:       VPDPWUSD_XMMi32_XMM2u16_MEM2i16
}


# EMITTING VPDPWUSD (VPDPWUSD-256-2)
{
ICLASS:      VPDPWUSD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD2 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2u16 REG2=YMM_B():r:qq:2i16
IFORM:       VPDPWUSD_YMMi32_YMM2u16_YMM2i16
}

{
ICLASS:      VPDPWUSD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2u16 MEM0:r:qq:2i16
IFORM:       VPDPWUSD_YMMi32_YMM2u16_MEM2i16
}


# EMITTING VPDPWUSDS (VPDPWUSDS-128-2)
{
ICLASS:      VPDPWUSDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD3 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2u16 REG2=XMM_B():r:dq:2i16
IFORM:       VPDPWUSDS_XMMi32_XMM2u16_XMM2i16
}

{
ICLASS:      VPDPWUSDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2u16 MEM0:r:dq:2i16
IFORM:       VPDPWUSDS_XMMi32_XMM2u16_MEM2i16
}


# EMITTING VPDPWUSDS (VPDPWUSDS-256-2)
{
ICLASS:      VPDPWUSDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD3 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2u16 REG2=YMM_B():r:qq:2i16
IFORM:       VPDPWUSDS_YMMi32_YMM2u16_YMM2i16
}

{
ICLASS:      VPDPWUSDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2u16 MEM0:r:qq:2i16
IFORM:       VPDPWUSDS_YMMi32_YMM2u16_MEM2i16
}


# EMITTING VPDPWUUD (VPDPWUUD-128-2)
{
ICLASS:      VPDPWUUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD2 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:2u16 REG2=XMM_B():r:dq:2u16
IFORM:       VPDPWUUD_XMMu32_XMM2u16_XMM2u16
}

{
ICLASS:      VPDPWUUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD2 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:2u16 MEM0:r:dq:2u16
IFORM:       VPDPWUUD_XMMu32_XMM2u16_MEM2u16
}


# EMITTING VPDPWUUD (VPDPWUUD-256-2)
{
ICLASS:      VPDPWUUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD2 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:2u16 REG2=YMM_B():r:qq:2u16
IFORM:       VPDPWUUD_YMMu32_YMM2u16_YMM2u16
}

{
ICLASS:      VPDPWUUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD2 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:2u16 MEM0:r:qq:2u16
IFORM:       VPDPWUUD_YMMu32_YMM2u16_MEM2u16
}


# EMITTING VPDPWUUDS (VPDPWUUDS-128-2)
{
ICLASS:      VPDPWUUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD3 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:2u16 REG2=XMM_B():r:dq:2u16
IFORM:       VPDPWUUDS_XMMu32_XMM2u16_XMM2u16
}

{
ICLASS:      VPDPWUUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD3 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:2u16 MEM0:r:dq:2u16
IFORM:       VPDPWUUDS_XMMu32_XMM2u16_MEM2u16
}


# EMITTING VPDPWUUDS (VPDPWUUDS-256-2)
{
ICLASS:      VPDPWUUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD3 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:2u16 REG2=YMM_B():r:qq:2u16
IFORM:       VPDPWUUDS_YMMu32_YMM2u16_YMM2u16
}

{
ICLASS:      VPDPWUUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT16
ISA_SET:     AVX_VNNI_INT16
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0xD3 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:2u16 MEM0:r:qq:2u16
IFORM:       VPDPWUUDS_YMMu32_YMM2u16_MEM2u16
}