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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
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#
AVX_INSTRUCTIONS()::
# EMITTING VPDPBSSD (VPDPBSSD-128-2)
{
ICLASS:      VPDPBSSD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x50 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 REG2=XMM_B():r:dq:4i8
IFORM:       VPDPBSSD_XMMi32_XMM4i8_XMM4i8
}

{
ICLASS:      VPDPBSSD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x50 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 MEM0:r:dq:4i8
IFORM:       VPDPBSSD_XMMi32_XMM4i8_MEM4i8
}


# EMITTING VPDPBSSD (VPDPBSSD-256-2)
{
ICLASS:      VPDPBSSD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x50 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 REG2=YMM_B():r:qq:4i8
IFORM:       VPDPBSSD_YMMi32_YMM4i8_YMM4i8
}

{
ICLASS:      VPDPBSSD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x50 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 MEM0:r:qq:4i8
IFORM:       VPDPBSSD_YMMi32_YMM4i8_MEM4i8
}


# EMITTING VPDPBSSDS (VPDPBSSDS-128-2)
{
ICLASS:      VPDPBSSDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x51 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 REG2=XMM_B():r:dq:4i8
IFORM:       VPDPBSSDS_XMMi32_XMM4i8_XMM4i8
}

{
ICLASS:      VPDPBSSDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x51 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 MEM0:r:dq:4i8
IFORM:       VPDPBSSDS_XMMi32_XMM4i8_MEM4i8
}


# EMITTING VPDPBSSDS (VPDPBSSDS-256-2)
{
ICLASS:      VPDPBSSDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x51 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 REG2=YMM_B():r:qq:4i8
IFORM:       VPDPBSSDS_YMMi32_YMM4i8_YMM4i8
}

{
ICLASS:      VPDPBSSDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x51 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 MEM0:r:qq:4i8
IFORM:       VPDPBSSDS_YMMi32_YMM4i8_MEM4i8
}


# EMITTING VPDPBSUD (VPDPBSUD-128-2)
{
ICLASS:      VPDPBSUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x50 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 REG2=XMM_B():r:dq:4u8
IFORM:       VPDPBSUD_XMMi32_XMM4i8_XMM4u8
}

{
ICLASS:      VPDPBSUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x50 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 MEM0:r:dq:4u8
IFORM:       VPDPBSUD_XMMi32_XMM4i8_MEM4u8
}


# EMITTING VPDPBSUD (VPDPBSUD-256-2)
{
ICLASS:      VPDPBSUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x50 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 REG2=YMM_B():r:qq:4u8
IFORM:       VPDPBSUD_YMMi32_YMM4i8_YMM4u8
}

{
ICLASS:      VPDPBSUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x50 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 MEM0:r:qq:4u8
IFORM:       VPDPBSUD_YMMi32_YMM4i8_MEM4u8
}


# EMITTING VPDPBSUDS (VPDPBSUDS-128-2)
{
ICLASS:      VPDPBSUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x51 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 REG2=XMM_B():r:dq:4u8
IFORM:       VPDPBSUDS_XMMi32_XMM4i8_XMM4u8
}

{
ICLASS:      VPDPBSUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x51 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 MEM0:r:dq:4u8
IFORM:       VPDPBSUDS_XMMi32_XMM4i8_MEM4u8
}


# EMITTING VPDPBSUDS (VPDPBSUDS-256-2)
{
ICLASS:      VPDPBSUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x51 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 REG2=YMM_B():r:qq:4u8
IFORM:       VPDPBSUDS_YMMi32_YMM4i8_YMM4u8
}

{
ICLASS:      VPDPBSUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x51 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 MEM0:r:qq:4u8
IFORM:       VPDPBSUDS_YMMi32_YMM4i8_MEM4u8
}


# EMITTING VPDPBUUD (VPDPBUUD-128-2)
{
ICLASS:      VPDPBUUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x50 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:4u8 REG2=XMM_B():r:dq:4u8
IFORM:       VPDPBUUD_XMMu32_XMM4u8_XMM4u8
}

{
ICLASS:      VPDPBUUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x50 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:4u8 MEM0:r:dq:4u8
IFORM:       VPDPBUUD_XMMu32_XMM4u8_MEM4u8
}


# EMITTING VPDPBUUD (VPDPBUUD-256-2)
{
ICLASS:      VPDPBUUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x50 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:4u8 REG2=YMM_B():r:qq:4u8
IFORM:       VPDPBUUD_YMMu32_YMM4u8_YMM4u8
}

{
ICLASS:      VPDPBUUD
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x50 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:4u8 MEM0:r:qq:4u8
IFORM:       VPDPBUUD_YMMu32_YMM4u8_MEM4u8
}


# EMITTING VPDPBUUDS (VPDPBUUDS-128-2)
{
ICLASS:      VPDPBUUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x51 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:4u8 REG2=XMM_B():r:dq:4u8
IFORM:       VPDPBUUDS_XMMu32_XMM4u8_XMM4u8
}

{
ICLASS:      VPDPBUUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x51 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128
OPERANDS:    REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:4u8 MEM0:r:dq:4u8
IFORM:       VPDPBUUDS_XMMu32_XMM4u8_MEM4u8
}


# EMITTING VPDPBUUDS (VPDPBUUDS-256-2)
{
ICLASS:      VPDPBUUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x51 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:4u8 REG2=YMM_B():r:qq:4u8
IFORM:       VPDPBUUDS_YMMu32_YMM4u8_YMM4u8
}

{
ICLASS:      VPDPBUUDS
CPL:         3
CATEGORY:    VEX
EXTENSION:   AVX_VNNI_INT8
ISA_SET:     AVX_VNNI_INT8
EXCEPTIONS:  avx-type-4
REAL_OPCODE: Y
PATTERN:     VV1 0x51 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256
OPERANDS:    REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:4u8 MEM0:r:qq:4u8
IFORM:       VPDPBUUDS_YMMu32_YMM4u8_MEM4u8
}