#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#  
#END_LEGAL
xed_reg_enum_t XMM_SE()::
mode16 | OUTREG=XMM_SE32()
mode32 | OUTREG=XMM_SE32()
mode64 | OUTREG=XMM_SE64()

xed_reg_enum_t XMM_SE64()::
ESRC=0x0 | OUTREG=XED_REG_XMM0
ESRC=0x1 | OUTREG=XED_REG_XMM1
ESRC=0x2 | OUTREG=XED_REG_XMM2
ESRC=0x3 | OUTREG=XED_REG_XMM3
ESRC=0x4 | OUTREG=XED_REG_XMM4
ESRC=0x5 | OUTREG=XED_REG_XMM5
ESRC=0x6 | OUTREG=XED_REG_XMM6
ESRC=0x7 | OUTREG=XED_REG_XMM7
ESRC=0x8 | OUTREG=XED_REG_XMM8
ESRC=0x9 | OUTREG=XED_REG_XMM9
ESRC=0xA | OUTREG=XED_REG_XMM10
ESRC=0xB | OUTREG=XED_REG_XMM11
ESRC=0xC | OUTREG=XED_REG_XMM12
ESRC=0xD | OUTREG=XED_REG_XMM13
ESRC=0xE | OUTREG=XED_REG_XMM14
ESRC=0xF | OUTREG=XED_REG_XMM15

xed_reg_enum_t XMM_SE32()::
ESRC=0 | OUTREG=XED_REG_XMM0    enc
ESRC=1 | OUTREG=XED_REG_XMM1    enc
ESRC=2 | OUTREG=XED_REG_XMM2    enc
ESRC=3 | OUTREG=XED_REG_XMM3    enc
ESRC=4 | OUTREG=XED_REG_XMM4    enc
ESRC=5 | OUTREG=XED_REG_XMM5    enc
ESRC=6 | OUTREG=XED_REG_XMM6    enc
ESRC=7 | OUTREG=XED_REG_XMM7    enc
# ignoring the high bit in non64b modes. Really just 0...7
ESRC=0x8 | OUTREG=XED_REG_XMM0
ESRC=0x9 | OUTREG=XED_REG_XMM1
ESRC=0xA | OUTREG=XED_REG_XMM2
ESRC=0xB | OUTREG=XED_REG_XMM3
ESRC=0xC | OUTREG=XED_REG_XMM4
ESRC=0xD | OUTREG=XED_REG_XMM5
ESRC=0xE | OUTREG=XED_REG_XMM6
ESRC=0xF | OUTREG=XED_REG_XMM7

xed_reg_enum_t YMM_SE()::
mode16 | OUTREG=YMM_SE32()
mode32 | OUTREG=YMM_SE32()
mode64 | OUTREG=YMM_SE64()

xed_reg_enum_t YMM_SE64()::
ESRC=0x0 | OUTREG=XED_REG_YMM0
ESRC=0x1 | OUTREG=XED_REG_YMM1
ESRC=0x2 | OUTREG=XED_REG_YMM2
ESRC=0x3 | OUTREG=XED_REG_YMM3
ESRC=0x4 | OUTREG=XED_REG_YMM4
ESRC=0x5 | OUTREG=XED_REG_YMM5
ESRC=0x6 | OUTREG=XED_REG_YMM6
ESRC=0x7 | OUTREG=XED_REG_YMM7
ESRC=0x8 | OUTREG=XED_REG_YMM8
ESRC=0x9 | OUTREG=XED_REG_YMM9
ESRC=0xA | OUTREG=XED_REG_YMM10
ESRC=0xB | OUTREG=XED_REG_YMM11
ESRC=0xC | OUTREG=XED_REG_YMM12
ESRC=0xD | OUTREG=XED_REG_YMM13
ESRC=0xE | OUTREG=XED_REG_YMM14
ESRC=0xF | OUTREG=XED_REG_YMM15

xed_reg_enum_t YMM_SE32()::
ESRC=0 | OUTREG=XED_REG_YMM0        enc
ESRC=1 | OUTREG=XED_REG_YMM1        enc
ESRC=2 | OUTREG=XED_REG_YMM2        enc
ESRC=3 | OUTREG=XED_REG_YMM3        enc
ESRC=4 | OUTREG=XED_REG_YMM4        enc
ESRC=5 | OUTREG=XED_REG_YMM5        enc
ESRC=6 | OUTREG=XED_REG_YMM6        enc
ESRC=7 | OUTREG=XED_REG_YMM7        enc
# ignoring the high bit in non64b modes. Really just 0...7
ESRC=0x8 | OUTREG=XED_REG_YMM0
ESRC=0x9 | OUTREG=XED_REG_YMM1
ESRC=0xA | OUTREG=XED_REG_YMM2
ESRC=0xB | OUTREG=XED_REG_YMM3
ESRC=0xC | OUTREG=XED_REG_YMM4
ESRC=0xD | OUTREG=XED_REG_YMM5
ESRC=0xE | OUTREG=XED_REG_YMM6
ESRC=0xF | OUTREG=XED_REG_YMM7


xed_reg_enum_t XMM_N()::
mode16 | OUTREG=XMM_N_32():
mode32 | OUTREG=XMM_N_32():
mode64 | OUTREG=XMM_N_64():

xed_reg_enum_t XMM_N_32()::
VEXDEST210=7 | OUTREG=XED_REG_XMM0
VEXDEST210=6 | OUTREG=XED_REG_XMM1
VEXDEST210=5 | OUTREG=XED_REG_XMM2
VEXDEST210=4 | OUTREG=XED_REG_XMM3
VEXDEST210=3 | OUTREG=XED_REG_XMM4
VEXDEST210=2 | OUTREG=XED_REG_XMM5
VEXDEST210=1 | OUTREG=XED_REG_XMM6
VEXDEST210=0 | OUTREG=XED_REG_XMM7

xed_reg_enum_t XMM_N_64()::
VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0
VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1
VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2
VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3
VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4
VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5
VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6
VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7
VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8
VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9
VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10
VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11
VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12
VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13
VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14
VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15

xed_reg_enum_t YMM_N()::
mode16 | OUTREG=YMM_N_32():
mode32 | OUTREG=YMM_N_32():
mode64 | OUTREG=YMM_N_64():

xed_reg_enum_t YMM_N_32()::
VEXDEST210=7 | OUTREG=XED_REG_YMM0
VEXDEST210=6 | OUTREG=XED_REG_YMM1
VEXDEST210=5 | OUTREG=XED_REG_YMM2
VEXDEST210=4 | OUTREG=XED_REG_YMM3
VEXDEST210=3 | OUTREG=XED_REG_YMM4
VEXDEST210=2 | OUTREG=XED_REG_YMM5
VEXDEST210=1 | OUTREG=XED_REG_YMM6
VEXDEST210=0 | OUTREG=XED_REG_YMM7
xed_reg_enum_t YMM_N_64()::
VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0
VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1
VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2
VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3
VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4
VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5
VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6
VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7
VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8
VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9
VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10
VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11
VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12
VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13
VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14
VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15

xed_reg_enum_t YMM_R()::
mode16 | OUTREG=YMM_R_32():
mode32 | OUTREG=YMM_R_32():
mode64 | OUTREG=YMM_R_64():


xed_reg_enum_t YMM_R_32()::
REG=0  | OUTREG=XED_REG_YMM0
REG=1  | OUTREG=XED_REG_YMM1
REG=2  | OUTREG=XED_REG_YMM2
REG=3  | OUTREG=XED_REG_YMM3
REG=4  | OUTREG=XED_REG_YMM4
REG=5  | OUTREG=XED_REG_YMM5
REG=6  | OUTREG=XED_REG_YMM6
REG=7  | OUTREG=XED_REG_YMM7

xed_reg_enum_t YMM_R_64()::
REXR=0 REG=0  | OUTREG=XED_REG_YMM0
REXR=0 REG=1  | OUTREG=XED_REG_YMM1
REXR=0 REG=2  | OUTREG=XED_REG_YMM2
REXR=0 REG=3  | OUTREG=XED_REG_YMM3
REXR=0 REG=4  | OUTREG=XED_REG_YMM4
REXR=0 REG=5  | OUTREG=XED_REG_YMM5
REXR=0 REG=6  | OUTREG=XED_REG_YMM6
REXR=0 REG=7  | OUTREG=XED_REG_YMM7
REXR=1 REG=0  | OUTREG=XED_REG_YMM8
REXR=1 REG=1  | OUTREG=XED_REG_YMM9
REXR=1 REG=2  | OUTREG=XED_REG_YMM10
REXR=1 REG=3  | OUTREG=XED_REG_YMM11
REXR=1 REG=4  | OUTREG=XED_REG_YMM12
REXR=1 REG=5  | OUTREG=XED_REG_YMM13
REXR=1 REG=6  | OUTREG=XED_REG_YMM14
REXR=1 REG=7  | OUTREG=XED_REG_YMM15


xed_reg_enum_t YMM_B()::
mode16 | OUTREG=YMM_B_32():
mode32 | OUTREG=YMM_B_32():
mode64 | OUTREG=YMM_B_64():


xed_reg_enum_t YMM_B_32()::
RM=0  | OUTREG=XED_REG_YMM0
RM=1  | OUTREG=XED_REG_YMM1
RM=2  | OUTREG=XED_REG_YMM2
RM=3  | OUTREG=XED_REG_YMM3
RM=4  | OUTREG=XED_REG_YMM4
RM=5  | OUTREG=XED_REG_YMM5
RM=6  | OUTREG=XED_REG_YMM6
RM=7  | OUTREG=XED_REG_YMM7

xed_reg_enum_t YMM_B_64()::
REXB=0 RM=0  | OUTREG=XED_REG_YMM0
REXB=0 RM=1  | OUTREG=XED_REG_YMM1
REXB=0 RM=2  | OUTREG=XED_REG_YMM2
REXB=0 RM=3  | OUTREG=XED_REG_YMM3
REXB=0 RM=4  | OUTREG=XED_REG_YMM4
REXB=0 RM=5  | OUTREG=XED_REG_YMM5
REXB=0 RM=6  | OUTREG=XED_REG_YMM6
REXB=0 RM=7  | OUTREG=XED_REG_YMM7
REXB=1 RM=0  | OUTREG=XED_REG_YMM8
REXB=1 RM=1  | OUTREG=XED_REG_YMM9
REXB=1 RM=2  | OUTREG=XED_REG_YMM10
REXB=1 RM=3  | OUTREG=XED_REG_YMM11
REXB=1 RM=4  | OUTREG=XED_REG_YMM12
REXB=1 RM=5  | OUTREG=XED_REG_YMM13
REXB=1 RM=6  | OUTREG=XED_REG_YMM14
REXB=1 RM=7  | OUTREG=XED_REG_YMM15