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EVEX_INSTRUCTIONS()::
# EMITTING VCVTNE2PS2BF16 (VCVTNE2PS2BF16-128-1)
{
ICLASS:      VCVTNE2PS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VCVTNE2PS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128
}


# EMITTING VCVTNE2PS2BF16 (VCVTNE2PS2BF16-256-1)
{
ICLASS:      VCVTNE2PS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512
}

{
ICLASS:      VCVTNE2PS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256
}


# EMITTING VCVTNE2PS2BF16 (VCVTNE2PS2BF16-512-1)
{
ICLASS:      VCVTNE2PS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VCVTNE2PS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512
}


# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-128-1)
{
ICLASS:      VCVTNEPS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTNEPS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128
}


# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-256-1)
{
ICLASS:      VCVTNEPS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTNEPS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256
}


# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-512-1)
{
ICLASS:      VCVTNEPS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTNEPS2BF16
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512
}


# EMITTING VDPBF16PS (VDPBF16PS-128-1)
{
ICLASS:      VDPBF16PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
IFORM:       VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512
}

{
ICLASS:      VDPBF16PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512
}


# EMITTING VDPBF16PS (VDPBF16PS-256-1)
{
ICLASS:      VDPBF16PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
IFORM:       VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512
}

{
ICLASS:      VDPBF16PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512
}


# EMITTING VDPBF16PS (VDPBF16PS-512-1)
{
ICLASS:      VDPBF16PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VDPBF16PS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_BF16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512
}