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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
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#
EVEX_INSTRUCTIONS()::
# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-512-1)
{
ICLASS:      VPBROADCASTMB2Q
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512CD_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
PATTERN:    EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO8_8
IFORM:       VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD
}


# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-512-1)
{
ICLASS:      VPBROADCASTMW2D
CPL:         3
CATEGORY:    BROADCAST
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512CD_512
EXCEPTIONS:     AVX512-E6NF
REAL_OPCODE: Y
PATTERN:    EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO16_16
IFORM:       VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD
}


# EMITTING VPCONFLICTD (VPCONFLICTD-512-1)
{
ICLASS:      VPCONFLICTD
CPL:         3
CATEGORY:    CONFLICT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512CD_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
IFORM:       VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD
}

{
ICLASS:      VPCONFLICTD
CPL:         3
CATEGORY:    CONFLICT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512CD_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD
}


# EMITTING VPCONFLICTQ (VPCONFLICTQ-512-1)
{
ICLASS:      VPCONFLICTQ
CPL:         3
CATEGORY:    CONFLICT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512CD_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
IFORM:       VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD
}

{
ICLASS:      VPCONFLICTQ
CPL:         3
CATEGORY:    CONFLICT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512CD_512
EXCEPTIONS:     AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD
}


# EMITTING VPLZCNTD (VPLZCNTD-512-1)
{
ICLASS:      VPLZCNTD
CPL:         3
CATEGORY:    CONFLICT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512CD_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
IFORM:       VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD
}

{
ICLASS:      VPLZCNTD
CPL:         3
CATEGORY:    CONFLICT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512CD_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD
}


# EMITTING VPLZCNTQ (VPLZCNTQ-512-1)
{
ICLASS:      VPLZCNTQ
CPL:         3
CATEGORY:    CONFLICT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512CD_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
IFORM:       VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD
}

{
ICLASS:      VPLZCNTQ
CPL:         3
CATEGORY:    CONFLICT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512CD_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD
}